Boot log: qemu_arm64-virt-gicv3
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
1 11:13:55.130400 lava-dispatcher, installed at version: 2023.01
2 11:13:55.130585 start: 0 validate
3 11:13:55.130699 Start time: 2023-06-05 11:13:55.130692+00:00 (UTC)
4 11:13:55.131779 Validating that http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image exists
5 11:13:55.490120 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz exists
6 11:13:55.669269 cmd: ['docker', 'pull', 'kernelci/qemu']
7 11:13:55.669458 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 11:13:55.833772 >> Using default tag: latest
9 11:13:56.942704 >> latest: Pulling from kernelci/qemu
10 11:13:56.974652 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
11 11:13:56.974865 >> Status: Image is up to date for kernelci/qemu:latest
12 11:13:57.007740 >> docker.io/kernelci/qemu:latest
13 11:13:57.011194 Returned 0 in 1 seconds
14 11:13:57.150727 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 11:13:57.151177 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 11:13:59.112798 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 11:13:59.113158 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 11:14:01.014479 Returned 0 in 3 seconds
19 11:14:01.115669 validate duration: 5.99
21 11:14:01.116031 start: 1 deployimages (timeout 00:03:00) [common]
22 11:14:01.116137 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 11:14:01.116439 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg
24 11:14:01.116586 makedir: /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin
25 11:14:01.116699 makedir: /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/tests
26 11:14:01.116807 makedir: /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/results
27 11:14:01.116949 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-add-keys
28 11:14:01.117105 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-add-sources
29 11:14:01.117235 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-background-process-start
30 11:14:01.117367 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-background-process-stop
31 11:14:01.117499 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-common-functions
32 11:14:01.117620 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-echo-ipv4
33 11:14:01.117760 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-install-packages
34 11:14:01.117886 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-installed-packages
35 11:14:01.118009 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-os-build
36 11:14:01.118134 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-probe-channel
37 11:14:01.118256 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-probe-ip
38 11:14:01.118380 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-target-ip
39 11:14:01.118504 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-target-mac
40 11:14:01.118629 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-target-storage
41 11:14:01.118775 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-test-case
42 11:14:01.118921 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-test-event
43 11:14:01.119049 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-test-feedback
44 11:14:01.119174 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-test-raise
45 11:14:01.119300 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-test-reference
46 11:14:01.119423 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-test-runner
47 11:14:01.119545 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-test-set
48 11:14:01.119666 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-test-shell
49 11:14:01.119791 Updating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-install-packages (oe)
50 11:14:01.119962 Updating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/bin/lava-installed-packages (oe)
51 11:14:01.120183 Creating /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/environment
52 11:14:01.120293 LAVA metadata
53 11:14:01.120366 - LAVA_JOB_ID=562648
54 11:14:01.120433 - LAVA_DISPATCHER_IP=172.27.0.2
55 11:14:01.120536 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 11:14:01.120609 skipped lava-vland-overlay
57 11:14:01.120686 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 11:14:01.120769 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 11:14:01.120837 skipped lava-multinode-overlay
60 11:14:01.120911 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 11:14:01.120992 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 11:14:01.121072 Loading test definitions
63 11:14:01.121169 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 11:14:01.121246 Using /lava-562648 at stage 0
65 11:14:01.121570 uuid=562648_1.1.3.1 testdef=None
66 11:14:01.121697 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 11:14:01.121781 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 11:14:01.122266 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 11:14:01.122514 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 11:14:01.123158 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 11:14:01.123411 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 11:14:01.123990 runner path: /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/0/tests/0_timesync-off test_uuid 562648_1.1.3.1
75 11:14:01.124643 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 11:14:01.124891 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 11:14:01.124965 Using /lava-562648 at stage 0
79 11:14:01.125066 Fetching tests from https://github.com/kernelci/test-definitions.git
80 11:14:01.125146 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/0/tests/1_kselftest-arm64_qemu'
81 11:14:05.817486 Running '/usr/bin/git checkout kernelci.org
82 11:14:05.979956 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 11:14:05.980633 uuid=562648_1.1.3.5 testdef=None
84 11:14:05.980772 end: 1.1.3.5 git-repo-action (duration 00:00:05) [common]
86 11:14:05.981023 start: 1.1.3.6 test-overlay (timeout 00:02:55) [common]
87 11:14:05.981852 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 11:14:05.982098 start: 1.1.3.7 test-install-overlay (timeout 00:02:55) [common]
90 11:14:05.983659 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 11:14:05.984175 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:55) [common]
93 11:14:05.986263 runner path: /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/0/tests/1_kselftest-arm64_qemu test_uuid 562648_1.1.3.5
94 11:14:05.986440 BOARD='qemu_arm64-virt-gicv3'
95 11:14:05.986566 BRANCH='cip'
96 11:14:05.986684 SKIPFILE='/dev/null'
97 11:14:05.986802 SKIP_INSTALL='True'
98 11:14:05.986918 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
99 11:14:05.987037 TST_CASENAME=''
100 11:14:05.987152 TST_CMDFILES='arm64'
101 11:14:05.987415 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 11:14:05.987872 Creating lava-test-runner.conf files
104 11:14:05.987998 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/562648/lava-overlay-w0vak6tg/lava-562648/0 for stage 0
105 11:14:05.988173 - 0_timesync-off
106 11:14:05.988307 - 1_kselftest-arm64_qemu
107 11:14:05.988486 end: 1.1.3 test-definition (duration 00:00:05) [common]
108 11:14:05.988654 start: 1.1.4 compress-overlay (timeout 00:02:55) [common]
109 11:14:14.720486 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 11:14:14.720693 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:46) [common]
111 11:14:14.720808 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 11:14:14.720932 end: 1.1 lava-overlay (duration 00:00:14) [common]
113 11:14:14.721051 start: 1.2 apply-overlay-guest (timeout 00:02:46) [common]
114 11:14:14.721137 Overlay: /var/lib/lava/dispatcher/tmp/562648/compress-overlay-3pdub7ke/overlay-1.1.4.tar.gz
115 11:14:29.722811 end: 1.2 apply-overlay-guest (duration 00:00:15) [common]
117 11:14:29.723562 start: 1.3 deploy-device-env (timeout 00:02:31) [common]
118 11:14:29.723728 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 11:14:29.723887 start: 1.4 download-retry (timeout 00:02:31) [common]
120 11:14:29.724050 start: 1.4.1 http-download (timeout 00:02:31) [common]
121 11:14:29.724330 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
122 11:14:29.724494 saving as /var/lib/lava/dispatcher/tmp/562648/deployimages-r_p1gz98/kernel/Image
123 11:14:29.724633 total size: 45746688 (43MB)
124 11:14:29.724762 No compression specified
125 11:14:30.082528 progress 0% (0MB)
126 11:14:31.150309 progress 5% (2MB)
127 11:14:31.508797 progress 10% (4MB)
128 11:14:31.692517 progress 15% (6MB)
129 11:14:32.053113 progress 20% (8MB)
130 11:14:32.231695 progress 25% (10MB)
131 11:14:32.413679 progress 30% (13MB)
132 11:14:32.596471 progress 35% (15MB)
133 11:14:32.939308 progress 40% (17MB)
134 11:14:33.122411 progress 45% (19MB)
135 11:14:33.303872 progress 50% (21MB)
136 11:14:33.484775 progress 55% (24MB)
137 11:14:33.824477 progress 60% (26MB)
138 11:14:34.006014 progress 65% (28MB)
139 11:14:34.187804 progress 70% (30MB)
140 11:14:34.368687 progress 75% (32MB)
141 11:14:34.548828 progress 80% (34MB)
142 11:14:34.729104 progress 85% (37MB)
143 11:14:35.067105 progress 90% (39MB)
144 11:14:35.247733 progress 95% (41MB)
145 11:14:35.427785 progress 100% (43MB)
146 11:14:35.428023 43MB downloaded in 5.70s (7.65MB/s)
147 11:14:35.428300 end: 1.4.1 http-download (duration 00:00:06) [common]
149 11:14:35.428796 end: 1.4 download-retry (duration 00:00:06) [common]
150 11:14:35.428956 start: 1.5 download-retry (timeout 00:02:26) [common]
151 11:14:35.429114 start: 1.5.1 http-download (timeout 00:02:26) [common]
152 11:14:35.429333 Not decompressing ramdisk as can be used compressed.
153 11:14:35.429498 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz
154 11:14:35.429626 saving as /var/lib/lava/dispatcher/tmp/562648/deployimages-r_p1gz98/ramdisk/rootfs.cpio.gz
155 11:14:35.429757 total size: 88976554 (84MB)
156 11:14:35.429875 No compression specified
157 11:14:35.608804 progress 0% (0MB)
158 11:14:35.971608 progress 5% (4MB)
159 11:14:36.505167 progress 10% (8MB)
160 11:14:37.036855 progress 15% (12MB)
161 11:14:37.567566 progress 20% (17MB)
162 11:14:38.096597 progress 25% (21MB)
163 11:14:38.466971 progress 30% (25MB)
164 11:14:38.993915 progress 35% (29MB)
165 11:14:39.518648 progress 40% (33MB)
166 11:14:39.886859 progress 45% (38MB)
167 11:14:40.410881 progress 50% (42MB)
168 11:14:40.937373 progress 55% (46MB)
169 11:14:41.303877 progress 60% (50MB)
170 11:14:41.827805 progress 65% (55MB)
171 11:14:42.193713 progress 70% (59MB)
172 11:14:42.721275 progress 75% (63MB)
173 11:14:43.243946 progress 80% (67MB)
174 11:14:43.619488 progress 85% (72MB)
175 11:14:44.136776 progress 90% (76MB)
176 11:14:44.511103 progress 95% (80MB)
177 11:14:45.029222 progress 100% (84MB)
178 11:14:45.029630 84MB downloaded in 9.60s (8.84MB/s)
179 11:14:45.030002 end: 1.5.1 http-download (duration 00:00:10) [common]
181 11:14:45.030724 end: 1.5 download-retry (duration 00:00:10) [common]
182 11:14:45.030967 end: 1 deployimages (duration 00:00:44) [common]
183 11:14:45.031201 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 11:14:45.031440 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 11:14:45.031607 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 11:14:45.031967 Extending command line for qcow2 test overlay
187 11:14:45.032643 Pulling docker image
188 11:14:45.032826 cmd: ['docker', 'pull', 'kernelci/qemu']
189 11:14:45.032962 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 11:14:45.196232 >> Using default tag: latest
191 11:14:46.355318 >> latest: Pulling from kernelci/qemu
192 11:14:46.387299 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
193 11:14:46.387489 >> Status: Image is up to date for kernelci/qemu:latest
194 11:14:46.420372 >> docker.io/kernelci/qemu:latest
195 11:14:46.423546 Returned 0 in 1 seconds
196 11:14:46.561756 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-562648-2.1.1-bznrx0998f --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/562648/deployimages-r_p1gz98/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/562648/deployimages-r_p1gz98/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/562648/apply-overlay-guest-ik42708v/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 11:14:46.700761 started a shell command
198 11:14:46.701415 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 11:14:46.701642 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 11:14:46.701861 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 11:14:46.702066 Setting prompt string to ['Linux version [0-9]']
202 11:14:46.702233 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 11:14:48.692733 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 11:14:48.693155 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
205 11:14:48.693438 [ 0.000000] random: crng init done
206 11:14:48.693633 [ 0.000000] Machine model: linux,dummy-virt
207 11:14:48.693853 [ 0.000000] efi: UEFI not found.
208 11:14:48.694097 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
209 11:14:48.694246 [ 0.000000] printk: bootconsole [pl11] enabled
210 11:14:48.694675 start: 2.2.1 login-action (timeout 00:04:56) [common]
211 11:14:48.694837 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
212 11:14:48.695033 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
213 11:14:48.695211 Using line separator: #'\n'#
214 11:14:48.695351 No login prompt set.
215 11:14:48.695506 Parsing kernel messages
216 11:14:48.695648 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
217 11:14:48.695909 [login-action] Waiting for messages, (timeout 00:04:56)
218 11:14:48.697449 [ 0.000000] NUMA: No NUMA configuration found
219 11:14:48.697963 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 11:14:48.698349 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf3a00-0x7fdf5fff]
221 11:14:48.700489 [ 0.000000] Zone ranges:
222 11:14:48.701312 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 11:14:48.701450 [ 0.000000] DMA32 empty
224 11:14:48.701559 [ 0.000000] Normal empty
225 11:14:48.701680 [ 0.000000] Movable zone start for each node
226 11:14:48.701789 [ 0.000000] Early memory node ranges
227 11:14:48.701910 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 11:14:48.702169 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 11:14:48.717156 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 11:14:48.718321 [ 0.000000] psci: probing for conduit method from DT.
231 11:14:48.718593 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 11:14:48.718708 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 11:14:48.718851 [ 0.000000] psci: Trusted OS migration not required
234 11:14:48.719206 [ 0.000000] psci: SMC Calling Convention v1.0
235 11:14:48.721455 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
236 11:14:48.722155 [ 0.000000] pcpu-alloc: s45224 r8192 d32600 u86016 alloc=21*4096
237 11:14:48.722476 [ 0.000000] pcpu-alloc: [0] 0
238 11:14:48.723767 [ 0.000000] Detected PIPT I-cache on CPU0
239 11:14:48.729283 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 11:14:48.730094 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 11:14:48.730275 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 11:14:48.730660 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 11:14:48.730745 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 11:14:48.731052 [ 0.000000] CPU features: detected: Spectre-v4
245 11:14:48.734661 [ 0.000000] alternatives: applying boot alternatives
246 11:14:48.737629 [ 0.000000] Fallback order for Node 0: 0
247 11:14:48.737804 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 11:14:48.737956 [ 0.000000] Policy zone: DMA
249 11:14:48.738387 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 11:14:48.740873 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 11:14:48.743630 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 11:14:48.744176 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 11:14:48.744529 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 11:14:48.754267 <6>[ 0.000000] Memory: 862480K/1048576K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 153328K reserved, 32768K cma-reserved)
255 11:14:48.759943 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 11:14:48.766670 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 11:14:48.766773 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 11:14:48.766872 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 11:14:48.767195 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 11:14:48.767296 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 11:14:48.767611 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 11:14:48.767783 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 11:14:48.768854 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 11:14:48.775750 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 11:14:48.775878 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 11:14:48.777537 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 11:14:48.777672 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 11:14:48.778350 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 11:14:48.782827 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 11:14:48.783602 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @43030000 (indirect, esz 8, psz 64K, shr 1)
271 11:14:48.783831 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @43040000 (flat, esz 8, psz 64K, shr 1)
272 11:14:48.784660 <6>[ 0.000000] GICv3: using LPI property table @0x0000000043050000
273 11:14:48.785109 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000043060000
274 11:14:48.786568 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 11:14:48.794813 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 11:14:48.795365 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 11:14:48.795799 <6>[ 0.000096] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 11:14:48.813522 <6>[ 0.015174] Console: colour dummy device 80x25
279 11:14:48.817615 <6>[ 0.021236] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 11:14:48.817811 <6>[ 0.022099] pid_max: default: 32768 minimum: 301
281 11:14:48.819317 <6>[ 0.023570] LSM: Security Framework initializing
282 11:14:48.823538 <6>[ 0.027720] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 11:14:48.823716 <6>[ 0.027960] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 11:14:48.855798 <4>[ 0.059964] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 11:14:48.861619 <6>[ 0.065810] cblist_init_generic: Setting adjustable number of callback queues.
286 11:14:48.861833 <6>[ 0.066134] cblist_init_generic: Setting shift to 0 and lim to 1.
287 11:14:48.862494 <6>[ 0.066703] cblist_init_generic: Setting shift to 0 and lim to 1.
288 11:14:48.864140 <6>[ 0.068366] rcu: Hierarchical SRCU implementation.
289 11:14:48.864348 <6>[ 0.068580] rcu: Max phase no-delay instances is 1000.
290 11:14:48.869763 <6>[ 0.073915] Platform MSI: its@8080000 domain created
291 11:14:48.870284 <6>[ 0.074535] PCI/MSI: /intc@8000000/its@8080000 domain created
292 11:14:48.870722 <6>[ 0.075108] fsl-mc MSI: its@8080000 domain created
293 11:14:48.874011 <6>[ 0.078212] EFI services will not be available.
294 11:14:48.874909 <6>[ 0.079100] smp: Bringing up secondary CPUs ...
295 11:14:48.875108 <6>[ 0.079332] smp: Brought up 1 node, 1 CPU
296 11:14:48.875247 <6>[ 0.079474] SMP: Total of 1 processors activated.
297 11:14:48.875417 <6>[ 0.079803] CPU features: detected: Branch Target Identification
298 11:14:48.875600 <6>[ 0.079983] CPU features: detected: 32-bit EL0 Support
299 11:14:48.875815 <6>[ 0.080120] CPU features: detected: 32-bit EL1 Support
300 11:14:48.875982 <6>[ 0.080234] CPU features: detected: ARMv8.4 Translation Table Level
301 11:14:48.876178 <6>[ 0.080470] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 11:14:48.876683 <6>[ 0.080798] CPU features: detected: Common not Private translations
303 11:14:48.876862 <6>[ 0.080984] CPU features: detected: CRC32 instructions
304 11:14:48.877103 <6>[ 0.081152] CPU features: detected: E0PD
305 11:14:48.877271 <6>[ 0.081390] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 11:14:48.877525 <6>[ 0.081564] CPU features: detected: RCpc load-acquire (LDAPR)
307 11:14:48.877740 <6>[ 0.081693] CPU features: detected: LSE atomic instructions
308 11:14:48.877917 <6>[ 0.081857] CPU features: detected: Privileged Access Never
309 11:14:48.878089 <6>[ 0.082032] CPU features: detected: RAS Extension Support
310 11:14:48.878252 <6>[ 0.082191] CPU features: detected: Random Number Generator
311 11:14:48.878466 <6>[ 0.082355] CPU features: detected: Speculation barrier (SB)
312 11:14:48.878643 <6>[ 0.082489] CPU features: detected: Stage-2 Force Write-Back
313 11:14:48.878814 <6>[ 0.082642] CPU features: detected: TLB range maintenance instructions
314 11:14:48.878943 <6>[ 0.082828] CPU features: detected: Scalable Matrix Extension
315 11:14:48.879061 <6>[ 0.082949] CPU features: detected: FA64
316 11:14:48.879177 <6>[ 0.083050] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 11:14:48.879294 <6>[ 0.083225] CPU features: detected: Scalable Vector Extension
318 11:14:48.890846 <6>[ 0.092552] SVE: maximum available vector length 256 bytes per vector
319 11:14:48.891300 <6>[ 0.095557] SVE: default vector length 64 bytes per vector
320 11:14:48.893350 <6>[ 0.097467] SME: minimum available vector length 16 bytes per vector
321 11:14:48.893535 <6>[ 0.097668] SME: maximum available vector length 256 bytes per vector
322 11:14:48.893701 <6>[ 0.097866] SME: default vector length 32 bytes per vector
323 11:14:48.893875 <6>[ 0.098316] CPU: All CPU(s) started at EL1
324 11:14:48.894293 <6>[ 0.098635] alternatives: applying system-wide alternatives
325 11:14:48.946026 <6>[ 0.150330] devtmpfs: initialized
326 11:14:48.965769 <6>[ 0.169761] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 11:14:48.966184 <6>[ 0.170569] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 11:14:48.972044 <6>[ 0.176201] pinctrl core: initialized pinctrl subsystem
329 11:14:48.982837 <6>[ 0.187067] DMI not present or invalid.
330 11:14:48.991904 <6>[ 0.196043] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 11:14:49.003333 <6>[ 0.207352] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 11:14:49.003798 <6>[ 0.208137] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 11:14:49.004233 <6>[ 0.208563] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 11:14:49.004666 <6>[ 0.209023] audit: initializing netlink subsys (disabled)
335 11:14:49.009847 <5>[ 0.213992] audit: type=2000 audit(0.176:1): state=initialized audit_enabled=0 res=1
336 11:14:49.012334 <6>[ 0.216507] thermal_sys: Registered thermal governor 'step_wise'
337 11:14:49.013028 <6>[ 0.216575] thermal_sys: Registered thermal governor 'power_allocator'
338 11:14:49.013153 <6>[ 0.217286] cpuidle: using governor menu
339 11:14:49.014120 <6>[ 0.218373] NET: Registered PF_QIPCRTR protocol family
340 11:14:49.017100 <6>[ 0.221252] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
341 11:14:49.017780 <6>[ 0.221994] ASID allocator initialised with 65536 entries
342 11:14:49.023409 <6>[ 0.227852] Serial: AMBA PL011 UART driver
343 11:14:49.072844 <6>[ 0.277168] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
344 11:14:49.074675 <6>[ 0.278809] printk: console [ttyAMA0] enabled
345 11:14:49.074794 <6>[ 0.278809] printk: console [ttyAMA0] enabled
346 11:14:49.074893 <6>[ 0.279313] printk: bootconsole [pl11] disabled
347 11:14:49.075232 <6>[ 0.279313] printk: bootconsole [pl11] disabled
348 11:14:49.085583 <6>[ 0.290028] KASLR enabled
349 11:14:49.121634 <6>[ 0.325697] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
350 11:14:49.121844 <6>[ 0.325930] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
351 11:14:49.121942 <6>[ 0.326165] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
352 11:14:49.122037 <6>[ 0.326364] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
353 11:14:49.122375 <6>[ 0.326558] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
354 11:14:49.122487 <6>[ 0.326770] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
355 11:14:49.122799 <6>[ 0.327092] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
356 11:14:49.123140 <6>[ 0.327306] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
357 11:14:49.132714 <6>[ 0.336893] ACPI: Interpreter disabled.
358 11:14:49.141074 <6>[ 0.345215] iommu: Default domain type: Translated
359 11:14:49.141239 <6>[ 0.345383] iommu: DMA domain TLB invalidation policy: strict mode
360 11:14:49.142806 <5>[ 0.347067] SCSI subsystem initialized
361 11:14:49.143793 <7>[ 0.348000] libata version 3.00 loaded.
362 11:14:49.145088 <6>[ 0.349330] usbcore: registered new interface driver usbfs
363 11:14:49.145316 <6>[ 0.349726] usbcore: registered new interface driver hub
364 11:14:49.145750 <6>[ 0.350048] usbcore: registered new device driver usb
365 11:14:49.149686 <6>[ 0.354025] pps_core: LinuxPPS API ver. 1 registered
366 11:14:49.150160 <6>[ 0.354232] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
367 11:14:49.150277 <6>[ 0.354614] PTP clock support registered
368 11:14:49.150782 <6>[ 0.355259] EDAC MC: Ver: 3.0.0
369 11:14:49.156947 <6>[ 0.361206] FPGA manager framework
370 11:14:49.157817 <6>[ 0.362180] Advanced Linux Sound Architecture Driver Initialized.
371 11:14:49.166866 <6>[ 0.371244] vgaarb: loaded
372 11:14:49.170879 <6>[ 0.375036] clocksource: Switched to clocksource arch_sys_counter
373 11:14:49.172077 <5>[ 0.376235] VFS: Disk quotas dquot_6.6.0
374 11:14:49.172287 <6>[ 0.376534] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
375 11:14:49.175328 <6>[ 0.379769] pnp: PnP ACPI: disabled
376 11:14:49.192966 <6>[ 0.397338] NET: Registered PF_INET protocol family
377 11:14:49.195374 <6>[ 0.399516] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
378 11:14:49.200175 <6>[ 0.404254] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
379 11:14:49.200384 <6>[ 0.404572] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
380 11:14:49.200600 <6>[ 0.404854] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
381 11:14:49.200967 <6>[ 0.405253] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
382 11:14:49.201612 <6>[ 0.405808] TCP: Hash tables configured (established 8192 bind 8192)
383 11:14:49.202908 <6>[ 0.407033] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
384 11:14:49.203099 <6>[ 0.407392] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
385 11:14:49.204262 <6>[ 0.408522] NET: Registered PF_UNIX/PF_LOCAL protocol family
386 11:14:49.206625 <6>[ 0.410807] RPC: Registered named UNIX socket transport module.
387 11:14:49.206870 <6>[ 0.411089] RPC: Registered udp transport module.
388 11:14:49.207060 <6>[ 0.411248] RPC: Registered tcp transport module.
389 11:14:49.207298 <6>[ 0.411389] RPC: Registered tcp NFSv4.1 backchannel transport module.
390 11:14:49.207463 <6>[ 0.411650] PCI: CLS 0 bytes, default 64
391 11:14:49.211870 <6>[ 0.416075] Unpacking initramfs...
392 11:14:49.220298 <6>[ 0.424430] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
393 11:14:49.220786 <6>[ 0.425191] kvm [1]: HYP mode not available
394 11:14:49.228848 <5>[ 0.433036] Initialise system trusted keyrings
395 11:14:49.234958 <6>[ 0.439148] workingset: timestamp_bits=42 max_order=18 bucket_order=0
396 11:14:49.270029 <6>[ 0.474189] squashfs: version 4.0 (2009/01/31) Phillip Lougher
397 11:14:49.276723 <5>[ 0.480908] NFS: Registering the id_resolver key type
398 11:14:49.276954 <5>[ 0.481297] Key type id_resolver registered
399 11:14:49.277118 <5>[ 0.481466] Key type id_legacy registered
400 11:14:49.277781 <6>[ 0.481960] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
401 11:14:49.277969 <6>[ 0.482240] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
402 11:14:49.282988 <6>[ 0.487155] 9p: Installing v9fs 9p2000 file system support
403 11:14:49.347846 <5>[ 0.551982] Key type asymmetric registered
404 11:14:49.348016 <5>[ 0.552152] Asymmetric key parser 'x509' registered
405 11:14:49.348209 <6>[ 0.552557] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
406 11:14:49.348681 <6>[ 0.552887] io scheduler mq-deadline registered
407 11:14:49.348850 <6>[ 0.553097] io scheduler kyber registered
408 11:14:49.415572 <6>[ 0.619575] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
409 11:14:49.426301 <6>[ 0.630518] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
410 11:14:49.431505 <6>[ 0.635510] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
411 11:14:49.431961 <6>[ 0.636212] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
412 11:14:49.432215 <6>[ 0.636499] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
413 11:14:49.432950 <4>[ 0.637155] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
414 11:14:49.433911 <6>[ 0.637818] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
415 11:14:49.439237 <6>[ 0.643407] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
416 11:14:49.439464 <6>[ 0.643837] pci_bus 0000:00: root bus resource [bus 00-ff]
417 11:14:49.439692 <6>[ 0.644044] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
418 11:14:49.439891 <6>[ 0.644258] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
419 11:14:49.440072 <6>[ 0.644456] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
420 11:14:49.441718 <6>[ 0.645943] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
421 11:14:49.449192 <6>[ 0.653343] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
422 11:14:49.449450 <6>[ 0.653724] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
423 11:14:49.449661 <6>[ 0.653908] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
424 11:14:49.449902 <6>[ 0.654155] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
425 11:14:49.450149 <6>[ 0.654485] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
426 11:14:49.455097 <6>[ 0.659247] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
427 11:14:49.455297 <6>[ 0.659467] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
428 11:14:49.455567 <6>[ 0.659629] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
429 11:14:49.455722 <6>[ 0.659849] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
430 11:14:49.458472 <6>[ 0.662654] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
431 11:14:49.467035 <6>[ 0.671188] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
432 11:14:49.467280 <6>[ 0.671514] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
433 11:14:49.467502 <6>[ 0.671790] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
434 11:14:49.467709 <6>[ 0.672050] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
435 11:14:49.468257 <6>[ 0.672303] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
436 11:14:49.468415 <6>[ 0.672546] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
437 11:14:49.483504 <6>[ 0.687928] EINJ: ACPI disabled.
438 11:14:49.569448 <6>[ 0.773595] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
439 11:14:49.576372 <6>[ 0.780554] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
440 11:14:49.608094 <6>[ 0.812250] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
441 11:14:49.623195 <6>[ 0.827372] SuperH (H)SCI(F) driver initialized
442 11:14:49.624576 <6>[ 0.828767] msm_serial: driver initialized
443 11:14:49.657755 <4>[ 0.861898] cacheinfo: Unable to detect cache hierarchy for CPU 0
444 11:14:49.688354 <6>[ 0.892769] loop: module loaded
445 11:14:49.689493 <6>[ 0.893617] virtio_blk virtio1: 1/0/0 default/read/poll queues
446 11:14:49.706114 <5>[ 0.910297] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
447 11:14:49.740332 <6>[ 0.944485] megasas: 07.719.03.00-rc1
448 11:14:49.756037 <5>[ 0.960149] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
449 11:14:49.757498 <6>[ 0.961624] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
450 11:14:49.757991 <6>[ 0.962258] Intel/Sharp Extended Query Table at 0x0031
451 11:14:49.762960 <6>[ 0.967142] Using buffer write method
452 11:14:49.763199 <7>[ 0.967568] erase region 0: offset=0x0,size=0x40000,blocks=256
453 11:14:49.763651 <5>[ 0.967947] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
454 11:14:49.764527 <6>[ 0.968613] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
455 11:14:49.764685 <6>[ 0.968847] Intel/Sharp Extended Query Table at 0x0031
456 11:14:49.765101 <6>[ 0.969411] Using buffer write method
457 11:14:49.765305 <7>[ 0.969536] erase region 0: offset=0x0,size=0x40000,blocks=256
458 11:14:49.765490 <5>[ 0.969750] Concatenating MTD devices:
459 11:14:49.765667 <5>[ 0.969865] (0): \"0.flash\"
460 11:14:49.765797 <5>[ 0.969951] (1): \"0.flash\"
461 11:14:49.765924 <5>[ 0.970042] into device \"0.flash\"
462 11:14:54.380022 <6>[ 5.584054] Freeing initrd memory: 86888K
463 11:14:54.493413 <6>[ 5.697675] tun: Universal TUN/TAP device driver, 1.6
464 11:14:54.502852 <6>[ 5.707265] thunder_xcv, ver 1.0
465 11:14:54.503309 <6>[ 5.707485] thunder_bgx, ver 1.0
466 11:14:54.503456 <6>[ 5.707690] nicpf, ver 1.0
467 11:14:54.506653 <6>[ 5.710858] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
468 11:14:54.506762 <6>[ 5.711053] hns3: Copyright (c) 2017 Huawei Corporation.
469 11:14:54.507085 <6>[ 5.711446] hclge is initializing
470 11:14:54.507201 <6>[ 5.711642] e1000: Intel(R) PRO/1000 Network Driver
471 11:14:54.507531 <6>[ 5.711762] e1000: Copyright (c) 1999-2006 Intel Corporation.
472 11:14:54.507646 <6>[ 5.712074] e1000e: Intel(R) PRO/1000 Network Driver
473 11:14:54.507969 <6>[ 5.712228] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
474 11:14:54.508085 <6>[ 5.712529] igb: Intel(R) Gigabit Ethernet Network Driver
475 11:14:54.508405 <6>[ 5.712685] igb: Copyright (c) 2007-2014 Intel Corporation.
476 11:14:54.508759 <6>[ 5.712967] igbvf: Intel(R) Gigabit Virtual Function Network Driver
477 11:14:54.508872 <6>[ 5.713152] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
478 11:14:54.509871 <6>[ 5.714079] sky2: driver version 1.30
479 11:14:54.513198 <6>[ 5.717354] VFIO - User Level meta-driver version: 0.3
480 11:14:54.521783 <6>[ 5.725994] usbcore: registered new interface driver usb-storage
481 11:14:54.522608 <6>[ 5.726834] usbcore: registered new device driver onboard-usb-hub
482 11:14:54.531122 <6>[ 5.735562] rtc-pl031 9010000.pl031: registered as rtc0
483 11:14:54.532343 <6>[ 5.736286] rtc-pl031 9010000.pl031: setting system clock to 2023-06-05T11:14:54 UTC (1685963694)
484 11:14:54.534438 <6>[ 5.738628] i2c_dev: i2c /dev entries driver
485 11:14:54.551494 <6>[ 5.755717] sdhci: Secure Digital Host Controller Interface driver
486 11:14:54.551604 <6>[ 5.755881] sdhci: Copyright(c) Pierre Ossman
487 11:14:54.553504 <6>[ 5.757757] Synopsys Designware Multimedia Card Interface Driver
488 11:14:54.555963 <6>[ 5.760227] sdhci-pltfm: SDHCI platform and OF driver helper
489 11:14:54.561350 <6>[ 5.765611] ledtrig-cpu: registered to indicate activity on CPUs
490 11:14:54.567093 <6>[ 5.771266] usbcore: registered new interface driver usbhid
491 11:14:54.567254 <6>[ 5.771440] usbhid: USB HID core driver
492 11:14:54.590559 <6>[ 5.794703] NET: Registered PF_PACKET protocol family
493 11:14:54.591563 <6>[ 5.795820] 9pnet: Installing 9P2000 support
494 11:14:54.592041 <5>[ 5.796227] Key type dns_resolver registered
495 11:14:54.593267 <6>[ 5.797455] registered taskstats version 1
496 11:14:54.593452 <5>[ 5.797847] Loading compiled-in X.509 certificates
497 11:14:54.614885 <6>[ 5.819013] input: gpio-keys as /devices/platform/gpio-keys/input/input0
498 11:14:54.621664 <6>[ 5.825867] ALSA device list:
499 11:14:54.621808 <6>[ 5.826021] No soundcards found.
500 11:14:54.624629 <6>[ 5.828808] uart-pl011 9000000.pl011: no DMA platform data
501 11:14:54.680971 <6>[ 5.885317] Freeing unused kernel memory: 8384K
502 11:14:54.682208 <6>[ 5.886373] Run /init as init process
503 11:14:54.682375 <7>[ 5.886544] with arguments:
504 11:14:54.682537 <7>[ 5.886671] /init
505 11:14:54.682716 <7>[ 5.886863] verbose
506 11:14:54.682845 <7>[ 5.886975] with environment:
507 11:14:54.682963 <7>[ 5.887097] HOME=/
508 11:14:54.683076 <7>[ 5.887195] TERM=linux
509 11:14:54.810766 <30>[ 6.014527] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
510 11:14:54.811822 <31>[ 6.016062] systemd[1]: No virtualization found in DMI
511 11:14:54.812639 <31>[ 6.017027] systemd[1]: UML virtualization not found in /proc/cpuinfo.
512 11:14:54.813098 <31>[ 6.017313] systemd[1]: No virtualization found in CPUID
513 11:14:54.813282 <31>[ 6.017619] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
514 11:14:54.814601 <31>[ 6.018710] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
515 11:14:54.815050 <31>[ 6.019357] systemd[1]: Found VM virtualization qemu
516 11:14:54.815261 <30>[ 6.019603] systemd[1]: Detected virtualization qemu.
517 11:14:54.815755 <30>[ 6.019945] systemd[1]: Detected architecture arm64.
518 11:14:54.815969 <31>[ 6.020313] systemd[1]: Detected initialized system, this is not the first boot.
519 11:14:54.819964
520 11:14:54.820416 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
521 11:14:54.820567
522 11:14:54.822180 <30>[ 6.026326] systemd[1]: Set hostname to <debian-bullseye-arm64>.
523 11:14:54.841911 <31>[ 6.045929] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
524 11:14:54.843350 <31>[ 6.047592] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
525 11:14:54.843710 <31>[ 6.048112] systemd[1]: Successfully brought loopback interface up
526 11:14:54.848429 <31>[ 6.052791] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
527 11:14:54.860960 <31>[ 6.065046] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
528 11:14:54.861090 <31>[ 6.065397] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
529 11:14:54.902013 <31>[ 6.106166] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
530 11:14:54.903395 <31>[ 6.107795] systemd[1]: Controller 'cpu' supported: yes
531 11:14:54.903727 <31>[ 6.107981] systemd[1]: Controller 'cpuacct' supported: no
532 11:14:54.903828 <31>[ 6.108170] systemd[1]: Controller 'cpuset' supported: yes
533 11:14:54.903923 <31>[ 6.108372] systemd[1]: Controller 'io' supported: yes
534 11:14:54.904242 <31>[ 6.108509] systemd[1]: Controller 'blkio' supported: no
535 11:14:54.904343 <31>[ 6.108660] systemd[1]: Controller 'memory' supported: yes
536 11:14:54.904444 <31>[ 6.108824] systemd[1]: Controller 'devices' supported: no
537 11:14:54.904767 <31>[ 6.109010] systemd[1]: Controller 'pids' supported: yes
538 11:14:54.904881 <31>[ 6.109225] systemd[1]: Controller 'bpf-firewall' supported: yes
539 11:14:54.905196 <31>[ 6.109409] systemd[1]: Controller 'bpf-devices' supported: yes
540 11:14:54.906397 <31>[ 6.110620] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
541 11:14:54.906985 <31>[ 6.111254] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
542 11:14:54.907558 <31>[ 6.111842] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
543 11:14:54.914047 <31>[ 6.118254] systemd[1]: Enabling (yes) showing of status (commandline).
544 11:14:54.922609 <31>[ 6.126709] systemd[1]: Successfully forked off '(sd-executor)' as PID 98.
545 11:14:54.932348 <31>[ 6.136526] systemd[98]: Successfully forked off '(direxec)' as PID 99.
546 11:14:54.934358 <31>[ 6.138535] systemd[98]: Successfully forked off '(direxec)' as PID 100.
547 11:14:54.936450 <31>[ 6.140617] systemd[98]: Successfully forked off '(direxec)' as PID 101.
548 11:14:54.938415 <31>[ 6.142570] systemd[98]: Successfully forked off '(direxec)' as PID 102.
549 11:14:54.967326 <31>[ 6.171508] systemd[98]: Successfully forked off '(direxec)' as PID 103.
550 11:14:55.098467 <31>[ 6.302698] systemd-fstab-generator[100]: Parsing /etc/fstab...
551 11:14:55.109292 <31>[ 6.313484] systemd-bless-boot-generator[99]: Skipping generator, not an EFI boot.
552 11:14:55.112919 <31>[ 6.316892] systemd-fstab-generator[100]: Found entry what=/dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76 where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
553 11:14:55.118962 <31>[ 6.323179] systemd-getty-generator[101]: Automatically adding serial getty for /dev/ttyAMA0.
554 11:14:55.126877 <31>[ 6.331053] systemd-getty-generator[101]: SELinux enabled state cached to: disabled
555 11:14:55.132637 <31>[ 6.336644] systemd-fstab-generator[100]: Checking was requested for /dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76, but fsck.ext4 does not exist.
556 11:14:55.135599 <31>[ 6.339834] systemd[98]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
557 11:14:55.136859 <31>[ 6.341117] systemd[98]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
558 11:14:55.140181 <31>[ 6.344406] systemd-fstab-generator[100]: SELinux enabled state cached to: disabled
559 11:14:55.147413 <31>[ 6.351568] systemd[98]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
560 11:14:55.147921 <31>[ 6.351986] systemd[98]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
561 11:14:55.148096 <31>[ 6.352338] systemd[98]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
562 11:14:55.150838 <31>[ 6.355060] systemd[1]: (sd-executor) succeeded.
563 11:14:55.152361 <31>[ 6.356611] systemd[1]: Looking for unit files in (higher priority first):
564 11:14:55.152477 <31>[ 6.356856] systemd[1]: /etc/systemd/system.control
565 11:14:55.152573 <31>[ 6.357033] systemd[1]: /run/systemd/system.control
566 11:14:55.152882 <31>[ 6.357192] systemd[1]: /run/systemd/transient
567 11:14:55.152984 <31>[ 6.357342] systemd[1]: /run/systemd/generator.early
568 11:14:55.153079 <31>[ 6.357487] systemd[1]: /etc/systemd/system
569 11:14:55.153383 <31>[ 6.357650] systemd[1]: /etc/systemd/system.attached
570 11:14:55.153482 <31>[ 6.357825] systemd[1]: /run/systemd/system
571 11:14:55.153812 <31>[ 6.358016] systemd[1]: /run/systemd/system.attached
572 11:14:55.153926 <31>[ 6.358217] systemd[1]: /run/systemd/generator
573 11:14:55.154026 <31>[ 6.358393] systemd[1]: /usr/local/lib/systemd/system
574 11:14:55.154118 <31>[ 6.358544] systemd[1]: /lib/systemd/system
575 11:14:55.154448 <31>[ 6.358700] systemd[1]: /usr/lib/systemd/system
576 11:14:55.155299 <31>[ 6.359536] systemd[1]: /run/systemd/generator.late
577 11:14:55.190045 <31>[ 6.394168] systemd[1]: Modification times have changed, need to update cache.
578 11:14:55.192152 <31>[ 6.396231] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
579 11:14:55.193108 <31>[ 6.397291] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
580 11:14:55.193999 <31>[ 6.398010] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
581 11:14:55.194965 <31>[ 6.399189] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
582 11:14:55.195780 <31>[ 6.400023] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
583 11:14:55.196135 <31>[ 6.400348] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
584 11:14:55.196499 <31>[ 6.400626] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
585 11:14:55.196878 <31>[ 6.401002] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
586 11:14:55.197255 <31>[ 6.401371] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
587 11:14:55.197636 <31>[ 6.401718] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
588 11:14:55.198032 <31>[ 6.402103] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
589 11:14:55.198999 <31>[ 6.403131] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
590 11:14:55.199370 <31>[ 6.403449] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
591 11:14:55.199810 <31>[ 6.403907] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
592 11:14:55.200253 <31>[ 6.404551] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
593 11:14:55.200780 <31>[ 6.404895] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
594 11:14:55.200958 <31>[ 6.405222] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
595 11:14:55.201455 <31>[ 6.405582] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
596 11:14:55.201661 <31>[ 6.405925] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
597 11:14:55.202406 <31>[ 6.406582] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
598 11:14:55.202977 <31>[ 6.407184] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp.service
599 11:14:55.203827 <31>[ 6.407871] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
600 11:14:55.204026 <31>[ 6.408151] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup-pre.target
601 11:14:55.204222 <31>[ 6.408408] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
602 11:14:55.204389 <31>[ 6.408660] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
603 11:14:55.204938 <31>[ 6.408979] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
604 11:14:55.205137 <31>[ 6.409333] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.service
605 11:14:55.205887 <31>[ 6.410007] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
606 11:14:55.206537 <31>[ 6.410685] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
607 11:14:55.207124 <31>[ 6.411348] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
608 11:14:55.207699 <31>[ 6.411729] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
609 11:14:55.208040 <31>[ 6.412241] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
610 11:14:55.208384 <31>[ 6.412606] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
611 11:14:55.208758 <31>[ 6.412959] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
612 11:14:55.209097 <31>[ 6.413321] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
613 11:14:55.209442 <31>[ 6.413664] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
614 11:14:55.209965 <31>[ 6.414033] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-device.target
615 11:14:55.210067 <31>[ 6.414366] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-parse-etc.service
616 11:14:55.210410 <31>[ 6.414690] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
617 11:14:55.211048 <31>[ 6.415310] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
618 11:14:55.211397 <31>[ 6.415653] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
619 11:14:55.211751 <31>[ 6.415976] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
620 11:14:55.212082 <31>[ 6.416341] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
621 11:14:55.212421 <31>[ 6.416695] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
622 11:14:55.212842 <31>[ 6.417027] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
623 11:14:55.213631 <31>[ 6.417674] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
624 11:14:55.213814 <31>[ 6.418049] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
625 11:14:55.214585 <31>[ 6.418699] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel2.target → multi-user.target
626 11:14:55.215038 <31>[ 6.419269] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
627 11:14:55.215660 <31>[ 6.419657] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend.target
628 11:14:55.215890 <31>[ 6.419933] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
629 11:14:55.216086 <31>[ 6.420292] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysusers.service
630 11:14:55.216849 <31>[ 6.420965] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
631 11:14:55.217053 <31>[ 6.421315] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
632 11:14:55.217578 <31>[ 6.421643] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
633 11:14:55.217803 <31>[ 6.421958] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
634 11:14:55.218586 <31>[ 6.422605] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
635 11:14:55.219139 <31>[ 6.423206] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
636 11:14:55.219347 <31>[ 6.423568] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
637 11:14:55.220153 <31>[ 6.424197] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
638 11:14:55.220394 <31>[ 6.424507] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
639 11:14:55.220604 <31>[ 6.424815] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-lookup.target
640 11:14:55.220790 <31>[ 6.425044] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/umount.target
641 11:14:55.220997 <31>[ 6.425294] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
642 11:14:55.221549 <31>[ 6.425602] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-tracing.mount
643 11:14:55.221786 <31>[ 6.425894] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.socket
644 11:14:55.221987 <31>[ 6.426205] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
645 11:14:55.222471 <31>[ 6.426509] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
646 11:14:55.223026 <31>[ 6.427057] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
647 11:14:55.223539 <31>[ 6.427344] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-online.target
648 11:14:55.223646 <31>[ 6.427670] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
649 11:14:55.223749 <31>[ 6.427977] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hybrid-sleep.service
650 11:14:55.224092 <31>[ 6.428274] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
651 11:14:55.224436 <31>[ 6.428562] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
652 11:14:55.224790 <31>[ 6.429125] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
653 11:14:55.225170 <31>[ 6.429405] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
654 11:14:55.225370 <31>[ 6.429699] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
655 11:14:55.226075 <31>[ 6.430231] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
656 11:14:55.226545 <31>[ 6.430604] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
657 11:14:55.227023 <31>[ 6.431248] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
658 11:14:55.227539 <31>[ 6.431581] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
659 11:14:55.227787 <31>[ 6.432056] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
660 11:14:55.228571 <31>[ 6.432731] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.locale1.service → systemd-localed.service
661 11:14:55.228826 <31>[ 6.433125] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
662 11:14:55.229378 <31>[ 6.433406] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
663 11:14:55.229589 <31>[ 6.433701] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
664 11:14:55.229836 <31>[ 6.434094] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
665 11:14:55.230080 <31>[ 6.434393] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
666 11:14:55.230605 <31>[ 6.434665] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
667 11:14:55.230875 <31>[ 6.435199] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsck-root.service
668 11:14:55.231417 <31>[ 6.435511] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-quotacheck.service
669 11:14:55.231644 <31>[ 6.435832] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
670 11:14:55.232161 <31>[ 6.436183] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
671 11:14:55.232341 <31>[ 6.436482] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
672 11:14:55.232532 <31>[ 6.436834] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
673 11:14:55.233052 <31>[ 6.437139] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
674 11:14:55.233237 <31>[ 6.437460] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
675 11:14:55.233683 <31>[ 6.437938] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-varlink@.socket
676 11:14:55.234139 <31>[ 6.438261] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
677 11:14:55.234254 <31>[ 6.438565] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
678 11:14:55.235279 <31>[ 6.439503] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.hostname1.service → systemd-hostnamed.service
679 11:14:55.235630 <31>[ 6.439910] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
680 11:14:55.236006 <31>[ 6.440178] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
681 11:14:55.236121 <31>[ 6.440468] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
682 11:14:55.236776 <31>[ 6.440762] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user-runtime-dir@.service
683 11:14:55.236996 <31>[ 6.441086] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kmod-static-nodes.service
684 11:14:55.237173 <31>[ 6.441400] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-logind.service
685 11:14:55.237708 <31>[ 6.441744] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
686 11:14:55.237886 <31>[ 6.442071] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-bless-boot.service
687 11:14:55.238070 <31>[ 6.442400] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
688 11:14:55.238522 <31>[ 6.442686] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
689 11:14:55.239235 <31>[ 6.443263] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-pre.target
690 11:14:55.239412 <31>[ 6.443601] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
691 11:14:55.239707 <31>[ 6.443905] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
692 11:14:55.240270 <31>[ 6.444296] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
693 11:14:55.240460 <31>[ 6.444632] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
694 11:14:55.241015 <31>[ 6.444956] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
695 11:14:55.241217 <31>[ 6.445313] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.service
696 11:14:55.241382 <31>[ 6.445637] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-cleanup.service
697 11:14:55.241959 <31>[ 6.445937] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/basic.target
698 11:14:55.242163 <31>[ 6.446234] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
699 11:14:55.242340 <31>[ 6.446530] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
700 11:14:55.242806 <31>[ 6.447078] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
701 11:14:55.243400 <31>[ 6.447386] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-kernel.socket
702 11:14:55.243619 <31>[ 6.447725] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
703 11:14:55.243864 <31>[ 6.448073] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
704 11:14:55.244082 <31>[ 6.448392] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/serial-getty@.service
705 11:14:55.244654 <31>[ 6.448712] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
706 11:14:55.244870 <31>[ 6.448946] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
707 11:14:55.245069 <31>[ 6.449194] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sockets.target
708 11:14:55.245530 <31>[ 6.449624] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks.service → /dev/null
709 11:14:55.245656 <31>[ 6.449926] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
710 11:14:55.246425 <31>[ 6.450536] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
711 11:14:55.246810 <31>[ 6.451148] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
712 11:14:55.247235 <31>[ 6.451455] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate.service
713 11:14:55.247459 <31>[ 6.451754] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
714 11:14:55.247947 <31>[ 6.452100] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
715 11:14:55.248162 <31>[ 6.452402] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
716 11:14:55.248420 <31>[ 6.452727] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
717 11:14:55.248881 <31>[ 6.453063] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sound.target
718 11:14:55.248998 <31>[ 6.453284] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
719 11:14:55.249337 <31>[ 6.453597] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
720 11:14:55.249562 <31>[ 6.453887] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
721 11:14:55.250112 <31>[ 6.454350] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
722 11:14:55.250886 <31>[ 6.455070] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
723 11:14:55.251287 <31>[ 6.455412] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
724 11:14:55.251693 <31>[ 6.455750] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
725 11:14:55.251811 <31>[ 6.456121] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
726 11:14:55.252122 <31>[ 6.456432] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/boot-complete.target
727 11:14:55.252491 <31>[ 6.456708] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
728 11:14:55.252675 <31>[ 6.456957] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
729 11:14:55.650924 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
730 11:14:55.655379 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
731 11:14:55.658378 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
732 11:14:55.661694 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
733 11:14:55.665153 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
734 11:14:55.666794 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
735 11:14:55.668971 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
736 11:14:55.669887 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
737 11:14:55.670867 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
738 11:14:55.671617 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
739 11:14:55.672371 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
740 11:14:55.675886 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
741 11:14:55.679706 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
742 11:14:55.681982 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
743 11:14:55.684376 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
744 11:14:55.686977 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
745 11:14:55.689187 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
746 11:14:55.691399 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
747 11:14:55.716579 Mounting [0;1;39mHuge Pages File System[0m...
748 11:14:55.735617 Mounting [0;1;39mPOSIX Message Queue File System[0m...
749 11:14:55.784054 Mounting [0;1;39mKernel Debug File System[0m...
750 11:14:55.832673 Starting [0;1;39mLoad Kernel Module configfs[0m...
751 11:14:55.860316 Starting [0;1;39mLoad Kernel Module drm[0m...
752 11:14:55.920180 Starting [0;1;39mJournal Service[0m...
753 11:14:55.951920 Starting [0;1;39mLoad Kernel Modules[0m...
754 11:14:55.992185 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
755 11:14:56.043819 Starting [0;1;39mColdplug All udev Devices[0m...
756 11:14:56.132344 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
757 11:14:56.140774 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
758 11:14:56.156556 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
759 11:14:56.203767 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
760 11:14:56.255665 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
761 11:14:56.272989 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
762 11:14:56.347921 Mounting [0;1;39mKernel Configuration File System[0m...
763 11:14:56.477778 Starting [0;1;39mApply Kernel Variables[0m...
764 11:14:56.524565 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
765 11:14:56.597839 <47>[ 7.802062] systemd-journald[109]: SELinux enabled state cached to: disabled
766 11:14:56.599588 <47>[ 7.803697] systemd-journald[109]: Auditing in kernel turned off.
767 11:14:56.620124 <47>[ 7.824417] systemd-journald[109]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
768 11:14:56.667537 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
769 11:14:56.683212 <47>[ 7.887185] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
770 11:14:56.685824 <47>[ 7.889826] systemd-journald[109]: Fixed min_use=3.8M max_use=19.3M max_size=2.4M min_size=512.0K keep_free=9.6M n_max_files=100
771 11:14:56.692244 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
772 11:14:56.693320 <47>[ 7.897483] systemd-journald[109]: Reserving 333 entries in field hash table.
773 11:14:56.695404 See 'systemctl status systemd-remount-fs.service' for details.
774 11:14:56.726581 <47>[ 7.930955] systemd-journald[109]: Reserving 4408 entries in data hash table.
775 11:14:56.728488 <47>[ 7.932876] systemd-journald[109]: Vacuuming...
776 11:14:56.729435 <47>[ 7.933636] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
777 11:14:56.729842 <47>[ 7.934230] systemd-journald[109]: Flushing /dev/kmsg...
778 11:14:56.732293 Starting [0;1;39mLoad/Save Random Seed[0m...
779 11:14:56.792111 Starting [0;1;39mCreate System Users[0m...
780 11:14:56.927395 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
781 11:14:57.092356 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
782 11:14:57.136390 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
783 11:14:57.254037 <47>[ 8.458304] systemd-journald[109]: systemd-journald running as PID 109 for the system.
784 11:14:57.267827 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
785 11:14:57.282745 <47>[ 8.487082] systemd-journald[109]: Sent READY=1 notification.
786 11:14:57.283126 <47>[ 8.487485] systemd-journald[109]: Sent WATCHDOG=1 notification.
787 11:14:57.313388 <47>[ 8.517494] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
788 11:14:57.324240 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
789 11:14:57.350860 <47>[ 8.555133] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
790 11:14:57.362893 <47>[ 8.567057] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
791 11:14:57.374639 <47>[ 8.578821] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
792 11:14:57.391345 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
793 11:14:57.393027 <47>[ 8.597122] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
794 11:14:57.403640 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
795 11:14:57.407468 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
796 11:14:57.408986 <47>[ 8.613075] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
797 11:14:57.420438 <47>[ 8.624569] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
798 11:14:57.438559 <47>[ 8.642674] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
799 11:14:57.456967 <47>[ 8.661001] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
800 11:14:57.458475 <47>[ 8.662600] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
801 11:14:57.471343 <47>[ 8.675670] systemd-journald[109]: n/a: New incoming connection.
802 11:14:57.471999 <47>[ 8.676209] systemd-journald[109]: varlink-20: varlink: setting state idle-server
803 11:14:57.487471 <47>[ 8.691586] systemd-journald[109]: varlink-20: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
804 11:14:57.489357 <47>[ 8.693442] systemd-journald[109]: varlink-20: varlink: changing state idle-server → processing-method
805 11:14:57.489665 <46>[ 8.693848] systemd-journald[109]: Received client request to flush runtime journal.
806 11:14:57.490168 <47>[ 8.694322] systemd-journald[109]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
807 11:14:57.496379 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
808 11:14:57.512678 <47>[ 8.717055] systemd-journald[109]: Vacuuming...
809 11:14:57.513536 <47>[ 8.717601] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
810 11:14:57.515193 <47>[ 8.719331] systemd-journald[109]: varlink-20: Sending message: {\"parameters\":{}}
811 11:14:57.515415 <47>[ 8.719600] systemd-journald[109]: varlink-20: varlink: changing state processing-method → processed-method
812 11:14:57.515694 <47>[ 8.719998] systemd-journald[109]: varlink-20: varlink: changing state processed-method → idle-server
813 11:14:57.535332 <47>[ 8.739350] systemd-journald[109]: varlink-20: varlink: changing state idle-server → pending-disconnect
814 11:14:57.535588 <47>[ 8.739747] systemd-journald[109]: varlink-20: varlink: changing state pending-disconnect → processing-disconnect
815 11:14:57.535964 <47>[ 8.740059] systemd-journald[109]: varlink-20: varlink: changing state processing-disconnect → disconnected
816 11:14:57.537580 <47>[ 8.741845] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
817 11:14:57.548240 <47>[ 8.752345] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
818 11:14:57.552218 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
819 11:14:57.567200 <47>[ 8.771312] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
820 11:14:57.569257 <47>[ 8.773483] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
821 11:14:57.587862 <47>[ 8.791958] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
822 11:14:57.624430 Starting [0;1;39mCreate Volatile Files and Directories[0m...
823 11:14:57.647088 <47>[ 8.851097] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
824 11:14:58.060501 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
825 11:14:58.136994 Starting [0;1;39mNetwork Service[0m...
826 11:14:58.175968 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
827 11:14:58.181334 <47>[ 9.385401] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
828 11:14:58.256991 Starting [0;1;39mNetwork Time Synchronization[0m...
829 11:14:58.301679 <47>[ 9.505767] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
830 11:14:58.328384 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
831 11:14:58.336783 <47>[ 9.540957] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
832 11:14:58.717494 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
833 11:14:59.652186 <47>[ 10.856067] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3307 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
834 11:14:59.652989 <47>[ 10.856796] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
835 11:14:59.653159 <47>[ 10.857284] systemd-journald[109]: Rotating...
836 11:14:59.654258 <47>[ 10.858220] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
837 11:14:59.668107 <47>[ 10.872159] systemd-journald[109]: Reserving 333 entries in field hash table.
838 11:14:59.697576 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
839 11:14:59.709126 <47>[ 10.913185] systemd-journald[109]: Reserving 4408 entries in data hash table.
840 11:14:59.740278 <47>[ 10.944558] systemd-journald[109]: Vacuuming...
841 11:14:59.742347 <47>[ 10.946420] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
842 11:14:59.804369 Starting [0;1;39mNetwork Name Resolution[0m...
843 11:14:59.826845 <47>[ 11.031113] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
844 11:15:00.149936 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
845 11:15:00.152495 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
846 11:15:00.155380 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
847 11:15:00.703888 <47>[ 11.908102] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
848 11:15:01.804802 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
849 11:15:01.814106 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
850 11:15:01.843015 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
851 11:15:01.856617 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
852 11:15:01.861336 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
853 11:15:01.867273 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
854 11:15:01.897465 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
855 11:15:01.898232 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
856 11:15:01.907297 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
857 11:15:01.968854 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
858 11:15:01.977497 <47>[ 13.181551] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
859 11:15:02.116125 <47>[ 13.320081] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
860 11:15:02.117066 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
861 11:15:02.297176 Starting [0;1;39mUser Login Management[0m...
862 11:15:02.315930 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
863 11:15:02.321352 <47>[ 13.525428] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
864 11:15:02.346518 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
865 11:15:02.351755 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
866 11:15:02.432475 Starting [0;1;39mPermit User Sessions[0m...
867 11:15:02.456234 <47>[ 13.660245] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
868 11:15:02.719864 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
869 11:15:02.805817 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
870 11:15:03.020475 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
871 11:15:03.491656 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
872 11:15:05.771186 [[0m[0;31m* [0m] A start job is running for /dev/ttyAMA0 (10s / 1min 30s)
873 11:15:06.238428 M[K[[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
874 11:15:06.325259 [K[[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
875 11:15:06.349377 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
876 11:15:06.369114 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
877 11:15:06.379895 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
878 11:15:06.450407 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
879 11:15:06.456641 <47>[ 17.660714] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
880 11:15:06.684458 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
881 11:15:06.741334 <6>[ 17.945568] virtio_net virtio0 enp0s1: renamed from eth0
882 11:15:06.782786 <47>[ 17.987041] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
883 11:15:06.795148 <47>[ 17.999120] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
884 11:15:06.869305
885 11:15:06.869913 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
886 11:15:06.870081
887 11:15:06.870244 debian-bullseye-arm64 login: root (automatic login)
888 11:15:06.890721
889 11:15:07.263838 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023 aarch64
890 11:15:07.264699
891 11:15:07.264908 The programs included with the Debian GNU/Linux system are free software;
892 11:15:07.265464 the exact distribution terms for each program are described in the
893 11:15:07.265681 individual files in /usr/share/doc/*/copyright.
894 11:15:07.265865
895 11:15:07.266035 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
896 11:15:07.266206 permitted by applicable law.
897 11:15:07.748123 <47>[ 18.952198] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
898 11:15:07.814400 <47>[ 19.018435] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3307 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
899 11:15:07.826902 <47>[ 19.031001] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
900 11:15:07.827067 <47>[ 19.031459] systemd-journald[109]: Rotating...
901 11:15:07.828869 <47>[ 19.033120] systemd-journald[109]: Reserving 333 entries in field hash table.
902 11:15:07.853893 <47>[ 19.057947] systemd-journald[109]: Reserving 4408 entries in data hash table.
903 11:15:07.873460 <47>[ 19.077536] systemd-journald[109]: Vacuuming...
904 11:15:07.885942 <47>[ 19.090041] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
905 11:15:08.085514 <47>[ 19.289691] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
906 11:15:09.953487 <47>[ 21.157443] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
907 11:15:10.326144 Matched prompt #10: / #
909 11:15:10.326627 Setting prompt string to ['/ #']
910 11:15:10.326781 end: 2.2.1 login-action (duration 00:00:22) [common]
912 11:15:10.327099 end: 2.2 auto-login-action (duration 00:00:24) [common]
913 11:15:10.327199 start: 2.3 expect-shell-connection (timeout 00:04:35) [common]
914 11:15:10.327276 Setting prompt string to ['/ #']
915 11:15:10.327342 Forcing a shell prompt, looking for ['/ #']
917 11:15:10.377793 / #
918 11:15:10.378080 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
919 11:15:10.378209 Waiting using forced prompt support (timeout 00:02:30)
920 11:15:10.379829
921 11:15:10.384745 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
922 11:15:10.384902 start: 2.4 export-device-env (timeout 00:04:35) [common]
923 11:15:10.385007 end: 2.4 export-device-env (duration 00:00:00) [common]
924 11:15:10.385100 end: 2 boot-image-retry (duration 00:00:25) [common]
925 11:15:10.385193 start: 3 lava-test-retry (timeout 00:08:51) [common]
926 11:15:10.385282 start: 3.1 lava-test-shell (timeout 00:08:51) [common]
927 11:15:10.385359 Using namespace: common
929 11:15:10.486110 / # #
930 11:15:10.486455 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
931 11:15:10.487131 #
933 11:15:10.594277 / # mkdir /lava-562648
934 11:15:10.594927 mkdir /lava-562648
936 11:15:10.721703 / # mount /dev/disk/by-uuid/2625da29-ca49-4816-9b95-0596a4404973 -t ext2 /lava-562648
937 11:15:10.722711 mount /dev/disk/by-uuid/2625da29-ca49-4816-9b95-0596a4404973 -t ext2 /lava-562648
938 11:15:10.758426 <4>[ 21.962502] ext2 filesystem being mounted at /lava-562648 supports timestamps until 2038 (0x7fffffff)
940 11:15:10.891728 / # ls -la /lava-562648/bin/lava-test-runner
941 11:15:10.892412 ls -la /lava-562648/bin/lava-test-runner
942 11:15:10.931261 -rwxr-xr-x 1 root root 1039 Jun 5 11:14 /lava-562648/bin/lava-test-runner
943 11:15:10.943034 Using /lava-562648
945 11:15:11.044011 / # export SHELL=/bin/sh
946 11:15:11.045173 export SHELL=/bin/sh
948 11:15:11.150627 / # . /lava-562648/environment
949 11:15:11.151774 . /lava-562648/environment
951 11:15:11.259711 / # /lava-562648/bin/lava-test-runner /lava-562648/0
952 11:15:11.260119 Test shell timeout: 10s (minimum of the action and connection timeout)
953 11:15:11.260860 /lava-562648/bin/lava-test-runner /lava-562648/0
954 11:15:11.386795 + export TESTRUN_ID=0_timesync-off
955 11:15:11.387040 + cd /lava-562648/0/tests/0_timesync-off
956 11:15:11.389021 + cat uuid
957 11:15:11.397283 + UUID=562648_1.1.3.1
958 11:15:11.397422 + set +x
959 11:15:11.398213 <LAVA_SIGNAL_STARTRUN 0_timesync-off 562648_1.1.3.1>
960 11:15:11.398338 + systemctl stop systemd-timesyncd
961 11:15:11.398608 Received signal: <STARTRUN> 0_timesync-off 562648_1.1.3.1
962 11:15:11.398692 Starting test lava.0_timesync-off (562648_1.1.3.1)
963 11:15:11.398802 Skipping test definition patterns.
964 11:15:11.660526 + set +x
965 11:15:11.660790 <LAVA_SIGNAL_ENDRUN 0_timesync-off 562648_1.1.3.1>
966 11:15:11.661077 Received signal: <ENDRUN> 0_timesync-off 562648_1.1.3.1
967 11:15:11.661204 Ending use of test pattern.
968 11:15:11.661297 Ending test lava.0_timesync-off (562648_1.1.3.1), duration 0.26
970 11:15:11.706014 + export TESTRUN_ID=1_kselftest-arm64_qemu
971 11:15:11.706462 + cd /lava-562648/0/tests/1_kselftest-arm64_qemu
972 11:15:11.708485 + cat uuid
973 11:15:11.717728 + UUID=562648_1.1.3.5
974 11:15:11.718016 + set +x
975 11:15:11.718348 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 562648_1.1.3.5>
976 11:15:11.718439 + cd ./automated/linux/kselftest/
977 11:15:11.718691 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 562648_1.1.3.5
978 11:15:11.718788 Starting test lava.1_kselftest-arm64_qemu (562648_1.1.3.5)
979 11:15:11.718906 Skipping test definition patterns.
980 11:15:11.723541 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip -e -p /opt/kselftests/mainline/ -n 1 -i 1
981 11:15:11.824599 INFO: install_deps skipped
982 11:15:11.866386 --2023-06-05 11:15:11-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
983 11:15:12.020010 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
984 11:15:12.231901 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
985 11:15:12.428066 HTTP request sent, awaiting response... 200 OK
986 11:15:12.431707 Length: 2714204 (2.6M) [application/octet-stream]
987 11:15:12.433471 Saving to: 'kselftest.tar.xz'
988 11:15:12.435228
989 11:15:13.685605 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 150KB/s kselftest.tar.xz 8%[> ] 219.84K 317KB/s kselftest.tar.xz 33%[=====> ] 886.09K 992KB/s kselftest.tar.xz 62%[===========> ] 1.63M 1.49MB/s kselftest.tar.xz 100%[===================>] 2.59M 2.07MB/s in 1.2s
990 11:15:13.685909
991 11:15:13.688080 2023-06-05 11:15:13 (2.07 MB/s) - 'kselftest.tar.xz' saved [2714204/2714204]
992 11:15:13.688231
993 11:15:16.663211 skiplist:
994 11:15:16.663665 ========================================
995 11:15:16.663848 ========================================
996 11:15:16.716078 arm64:tags_test
997 11:15:16.716384 arm64:run_tags_test.sh
998 11:15:16.716580 arm64:fake_sigreturn_bad_magic
999 11:15:16.717010 arm64:fake_sigreturn_bad_size
1000 11:15:16.717188 arm64:fake_sigreturn_bad_size_for_magic0
1001 11:15:16.717385 arm64:fake_sigreturn_duplicated_fpsimd
1002 11:15:16.717575 arm64:fake_sigreturn_misaligned_sp
1003 11:15:16.717762 arm64:fake_sigreturn_missing_fpsimd
1004 11:15:16.717914 arm64:fake_sigreturn_sme_change_vl
1005 11:15:16.718058 arm64:fake_sigreturn_sve_change_vl
1006 11:15:16.718202 arm64:mangle_pstate_invalid_compat_toggle
1007 11:15:16.718388 arm64:mangle_pstate_invalid_daif_bits
1008 11:15:16.718526 arm64:mangle_pstate_invalid_mode_el1h
1009 11:15:16.718669 arm64:mangle_pstate_invalid_mode_el1t
1010 11:15:16.718811 arm64:mangle_pstate_invalid_mode_el2h
1011 11:15:16.718956 arm64:mangle_pstate_invalid_mode_el2t
1012 11:15:16.719096 arm64:mangle_pstate_invalid_mode_el3h
1013 11:15:16.719236 arm64:mangle_pstate_invalid_mode_el3t
1014 11:15:16.719377 arm64:sme_trap_no_sm
1015 11:15:16.719518 arm64:sme_trap_non_streaming
1016 11:15:16.719658 arm64:sme_trap_za
1017 11:15:16.719796 arm64:sme_vl
1018 11:15:16.719939 arm64:ssve_regs
1019 11:15:16.720079 arm64:sve_regs
1020 11:15:16.720225 arm64:sve_vl
1021 11:15:16.720365 arm64:za_no_regs
1022 11:15:16.720505 arm64:za_regs
1023 11:15:16.720643 arm64:pac
1024 11:15:16.720785 arm64:fp-stress
1025 11:15:16.720939 arm64:sve-ptrace
1026 11:15:16.721082 arm64:sve-probe-vls
1027 11:15:16.721221 arm64:vec-syscfg
1028 11:15:16.721360 arm64:za-fork
1029 11:15:16.721500 arm64:za-ptrace
1030 11:15:16.721639 arm64:check_buffer_fill
1031 11:15:16.721790 arm64:check_child_memory
1032 11:15:16.721930 arm64:check_gcr_el1_cswitch
1033 11:15:16.722069 arm64:check_ksm_options
1034 11:15:16.722207 arm64:check_mmap_options
1035 11:15:16.722346 arm64:check_prctl
1036 11:15:16.722523 arm64:check_tags_inclusion
1037 11:15:16.722656 arm64:check_user_mem
1038 11:15:16.722796 arm64:btitest
1039 11:15:16.722935 arm64:nobtitest
1040 11:15:16.723075 arm64:hwcap
1041 11:15:16.723213 arm64:ptrace
1042 11:15:16.723351 arm64:syscall-abi
1043 11:15:16.723490 arm64:tpidr2
1044 11:15:16.730587 ============== Tests to run ===============
1045 11:15:16.735172 arm64:tags_test
1046 11:15:16.735583 arm64:run_tags_test.sh
1047 11:15:16.735793 arm64:fake_sigreturn_bad_magic
1048 11:15:16.735970 arm64:fake_sigreturn_bad_size
1049 11:15:16.736144 arm64:fake_sigreturn_bad_size_for_magic0
1050 11:15:16.736353 arm64:fake_sigreturn_duplicated_fpsimd
1051 11:15:16.736500 arm64:fake_sigreturn_misaligned_sp
1052 11:15:16.736648 arm64:fake_sigreturn_missing_fpsimd
1053 11:15:16.736802 arm64:fake_sigreturn_sme_change_vl
1054 11:15:16.737012 arm64:fake_sigreturn_sve_change_vl
1055 11:15:16.737225 arm64:mangle_pstate_invalid_compat_toggle
1056 11:15:16.737398 arm64:mangle_pstate_invalid_daif_bits
1057 11:15:16.737593 arm64:mangle_pstate_invalid_mode_el1h
1058 11:15:16.737810 arm64:mangle_pstate_invalid_mode_el1t
1059 11:15:16.737981 arm64:mangle_pstate_invalid_mode_el2h
1060 11:15:16.738168 arm64:mangle_pstate_invalid_mode_el2t
1061 11:15:16.738318 arm64:mangle_pstate_invalid_mode_el3h
1062 11:15:16.738461 arm64:mangle_pstate_invalid_mode_el3t
1063 11:15:16.738602 arm64:sme_trap_no_sm
1064 11:15:16.738742 arm64:sme_trap_non_streaming
1065 11:15:16.738880 arm64:sme_trap_za
1066 11:15:16.739019 arm64:sme_vl
1067 11:15:16.739156 arm64:ssve_regs
1068 11:15:16.739293 arm64:sve_regs
1069 11:15:16.739431 arm64:sve_vl
1070 11:15:16.739569 arm64:za_no_regs
1071 11:15:16.739719 arm64:za_regs
1072 11:15:16.739864 arm64:pac
1073 11:15:16.740003 arm64:fp-stress
1074 11:15:16.740158 arm64:sve-ptrace
1075 11:15:16.740310 arm64:sve-probe-vls
1076 11:15:16.740428 arm64:vec-syscfg
1077 11:15:16.740542 arm64:za-fork
1078 11:15:16.740655 arm64:za-ptrace
1079 11:15:16.740767 arm64:check_buffer_fill
1080 11:15:16.740890 arm64:check_child_memory
1081 11:15:16.741002 arm64:check_gcr_el1_cswitch
1082 11:15:16.741112 arm64:check_ksm_options
1083 11:15:16.741222 arm64:check_mmap_options
1084 11:15:16.741333 arm64:check_prctl
1085 11:15:16.741444 arm64:check_tags_inclusion
1086 11:15:16.741555 arm64:check_user_mem
1087 11:15:16.741708 arm64:btitest
1088 11:15:16.741831 arm64:nobtitest
1089 11:15:16.741947 arm64:hwcap
1090 11:15:16.742060 arm64:ptrace
1091 11:15:16.742172 arm64:syscall-abi
1092 11:15:16.742285 arm64:tpidr2
1093 11:15:16.742397 ===========End Tests to run ===============
1094 11:15:17.665304 <12>[ 28.869558] kselftest: Running tests in arm64
1095 11:15:17.692780 TAP version 13
1096 11:15:17.709844 1..48
1097 11:15:17.755180 # selftests: arm64: tags_test
1098 11:15:17.806667 ok 1 selftests: arm64: tags_test
1099 11:15:17.852675 # selftests: arm64: run_tags_test.sh
1100 11:15:17.901781 # --------------------
1101 11:15:17.902059 # running tags test
1102 11:15:17.902412 # --------------------
1103 11:15:17.902547 # [PASS]
1104 11:15:17.909928 ok 2 selftests: arm64: run_tags_test.sh
1105 11:15:17.955122 # selftests: arm64: fake_sigreturn_bad_magic
1106 11:15:18.003297 # Registered handlers for all signals.
1107 11:15:18.003576 # Detected MINSTKSIGSZ:10000
1108 11:15:18.003712 # Testcase initialized.
1109 11:15:18.003871 # uc context validated.
1110 11:15:18.004025 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1111 11:15:18.004153 # Handled SIG_COPYCTX
1112 11:15:18.004278 # Available space:3536
1113 11:15:18.004402 # Using badly built context - ERR: BAD MAGIC !
1114 11:15:18.004526 # SIG_OK -- SP:0xFFFFCE485490 si_addr@:0xffffce485490 si_code:2 token@:0xffffce484230 offset:-4704
1115 11:15:18.004650 # ==>> completed. PASS(1)
1116 11:15:18.004797 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1117 11:15:18.004926 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCE484230
1118 11:15:18.011747 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1119 11:15:18.055031 # selftests: arm64: fake_sigreturn_bad_size
1120 11:15:18.103063 # Registered handlers for all signals.
1121 11:15:18.103654 # Detected MINSTKSIGSZ:10000
1122 11:15:18.103875 # Testcase initialized.
1123 11:15:18.104079 # uc context validated.
1124 11:15:18.104272 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1125 11:15:18.104475 # Handled SIG_COPYCTX
1126 11:15:18.104652 # Available space:3536
1127 11:15:18.104798 # uc context validated.
1128 11:15:18.104979 # Using badly built context - ERR: Bad size for esr_context
1129 11:15:18.105113 # SIG_OK -- SP:0xFFFFCEFA0730 si_addr@:0xffffcefa0730 si_code:2 token@:0xffffcef9f4d0 offset:-4704
1130 11:15:18.105256 # ==>> completed. PASS(1)
1131 11:15:18.105396 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1132 11:15:18.105538 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCEF9F4D0
1133 11:15:18.112236 ok 4 selftests: arm64: fake_sigreturn_bad_size
1134 11:15:18.156743 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1135 11:15:18.204790 # Registered handlers for all signals.
1136 11:15:18.205072 # Detected MINSTKSIGSZ:10000
1137 11:15:18.205239 # Testcase initialized.
1138 11:15:18.205396 # uc context validated.
1139 11:15:18.205532 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1140 11:15:18.205662 # Handled SIG_COPYCTX
1141 11:15:18.205818 # Available space:3536
1142 11:15:18.205938 # Using badly built context - ERR: Bad size for terminator
1143 11:15:18.206054 # SIG_OK -- SP:0xFFFFE0EEF570 si_addr@:0xffffe0eef570 si_code:2 token@:0xffffe0eee310 offset:-4704
1144 11:15:18.206173 # ==>> completed. PASS(1)
1145 11:15:18.206291 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1146 11:15:18.206403 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE0EEE310
1147 11:15:18.212817 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1148 11:15:18.256554 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1149 11:15:18.302731 # Registered handlers for all signals.
1150 11:15:18.302827 # Detected MINSTKSIGSZ:10000
1151 11:15:18.302909 # Testcase initialized.
1152 11:15:18.303003 # uc context validated.
1153 11:15:18.303085 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1154 11:15:18.303164 # Handled SIG_COPYCTX
1155 11:15:18.303257 # Available space:3536
1156 11:15:18.303337 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1157 11:15:18.303437 # SIG_OK -- SP:0xFFFFCC56FA70 si_addr@:0xffffcc56fa70 si_code:2 token@:0xffffcc56e810 offset:-4704
1158 11:15:18.303708 # ==>> completed. PASS(1)
1159 11:15:18.303976 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1160 11:15:18.304060 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCC56E810
1161 11:15:18.312613 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1162 11:15:18.356247 # selftests: arm64: fake_sigreturn_misaligned_sp
1163 11:15:18.403829 # Registered handlers for all signals.
1164 11:15:18.404029 # Detected MINSTKSIGSZ:10000
1165 11:15:18.404482 # Testcase initialized.
1166 11:15:18.404674 # uc context validated.
1167 11:15:18.404814 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1168 11:15:18.404936 # Handled SIG_COPYCTX
1169 11:15:18.405052 # SIG_OK -- SP:0xFFFFEE493433 si_addr@:0xffffee493433 si_code:2 token@:0xffffee493433 offset:0
1170 11:15:18.405167 # ==>> completed. PASS(1)
1171 11:15:18.405302 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1172 11:15:18.405419 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEE493433
1173 11:15:18.412390 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1174 11:15:18.456094 # selftests: arm64: fake_sigreturn_missing_fpsimd
1175 11:15:18.504145 # Registered handlers for all signals.
1176 11:15:18.504599 # Detected MINSTKSIGSZ:10000
1177 11:15:18.504789 # Testcase initialized.
1178 11:15:18.504945 # uc context validated.
1179 11:15:18.505104 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1180 11:15:18.505253 # Handled SIG_COPYCTX
1181 11:15:18.505370 # Mangling template header. Spare space:4096
1182 11:15:18.505508 # Using badly built context - ERR: Missing FPSIMD
1183 11:15:18.505625 # SIG_OK -- SP:0xFFFFEB2F8280 si_addr@:0xffffeb2f8280 si_code:2 token@:0xffffeb2f7020 offset:-4704
1184 11:15:18.505756 # ==>> completed. PASS(1)
1185 11:15:18.505870 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1186 11:15:18.505982 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEB2F7020
1187 11:15:18.512816 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1188 11:15:18.556162 # selftests: arm64: fake_sigreturn_sme_change_vl
1189 11:15:18.602193 # Registered handlers for all signals.
1190 11:15:18.602373 # Detected MINSTKSIGSZ:10000
1191 11:15:18.602537 # Required Features: [ SME ] supported
1192 11:15:18.602915 # Incompatible Features: [] absent
1193 11:15:18.603087 # Testcase initialized.
1194 11:15:18.603244 # uc context validated.
1195 11:15:18.603362 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1196 11:15:18.603475 # Handled SIG_COPYCTX
1197 11:15:18.603587 # Attempting to change VL from 16 to 256
1198 11:15:18.603699 # SIG_OK -- SP:0xFFFFE900AF50 si_addr@:0xffffe900af50 si_code:2 token@:0xffffe9009cf0 offset:-4704
1199 11:15:18.603837 # ==>> completed. PASS(1)
1200 11:15:18.603955 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1201 11:15:18.604070 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE9009CF0
1202 11:15:18.612052 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1203 11:15:18.655786 # selftests: arm64: fake_sigreturn_sve_change_vl
1204 11:15:18.703794 # Registered handlers for all signals.
1205 11:15:18.703964 # Detected MINSTKSIGSZ:10000
1206 11:15:18.704365 # Required Features: [ SVE ] supported
1207 11:15:18.704558 # Incompatible Features: [] absent
1208 11:15:18.704691 # Testcase initialized.
1209 11:15:18.704811 # uc context validated.
1210 11:15:18.704934 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1211 11:15:18.705051 # Handled SIG_COPYCTX
1212 11:15:18.705192 # Attempting to change VL from 16 to 256
1213 11:15:18.705313 # SIG_OK -- SP:0xFFFFCDAD4960 si_addr@:0xffffcdad4960 si_code:2 token@:0xffffcdad3700 offset:-4704
1214 11:15:18.705430 # ==>> completed. PASS(1)
1215 11:15:18.705545 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1216 11:15:18.705679 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCDAD3700
1217 11:15:18.712488 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1218 11:15:18.756195 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1219 11:15:18.801962 # Registered handlers for all signals.
1220 11:15:18.802352 # Detected MINSTKSIGSZ:10000
1221 11:15:18.802455 # Testcase initialized.
1222 11:15:18.802537 # uc context validated.
1223 11:15:18.802615 # Handled SIG_TRIG
1224 11:15:18.802692 # SIG_OK -- SP:0xFFFFED8A4E40 si_addr@:0xffffed8a4e40 si_code:2 token@:(nil) offset:-281474667007552
1225 11:15:18.802972 # ==>> completed. PASS(1)
1226 11:15:18.803068 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1227 11:15:18.810606 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1228 11:15:18.855736 # selftests: arm64: mangle_pstate_invalid_daif_bits
1229 11:15:18.901170 # Registered handlers for all signals.
1230 11:15:18.901554 # Detected MINSTKSIGSZ:10000
1231 11:15:18.901701 # Testcase initialized.
1232 11:15:18.902888 # uc context validated.
1233 11:15:18.903322 # Handled SIG_TRIG
1234 11:15:18.903473 # SIG_OK -- SP:0xFFFFD0F64EA0 si_addr@:0xffffd0f64ea0 si_code:2 token@:(nil) offset:-281474187546272
1235 11:15:18.903600 # ==>> completed. PASS(1)
1236 11:15:18.903740 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1237 11:15:18.910067 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1238 11:15:18.953775 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1239 11:15:19.001799 # Registered handlers for all signals.
1240 11:15:19.001957 # Detected MINSTKSIGSZ:10000
1241 11:15:19.002036 # Testcase initialized.
1242 11:15:19.002112 # uc context validated.
1243 11:15:19.002211 # Handled SIG_TRIG
1244 11:15:19.002290 # SIG_OK -- SP:0xFFFFE9268970 si_addr@:0xffffe9268970 si_code:2 token@:(nil) offset:-281474593360240
1245 11:15:19.002370 # ==>> completed. PASS(1)
1246 11:15:19.002461 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1247 11:15:19.010044 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1248 11:15:19.056236 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1249 11:15:19.101765 # Registered handlers for all signals.
1250 11:15:19.101922 # Detected MINSTKSIGSZ:10000
1251 11:15:19.102042 # Testcase initialized.
1252 11:15:19.102387 # uc context validated.
1253 11:15:19.102537 # Handled SIG_TRIG
1254 11:15:19.102653 # SIG_OK -- SP:0xFFFFEE953530 si_addr@:0xffffee953530 si_code:2 token@:(nil) offset:-281474684499248
1255 11:15:19.102769 # ==>> completed. PASS(1)
1256 11:15:19.102882 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1257 11:15:19.110884 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1258 11:15:19.155258 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1259 11:15:19.201385 # Registered handlers for all signals.
1260 11:15:19.201703 # Detected MINSTKSIGSZ:10000
1261 11:15:19.201803 # Testcase initialized.
1262 11:15:19.201886 # uc context validated.
1263 11:15:19.201965 # Handled SIG_TRIG
1264 11:15:19.202059 # SIG_OK -- SP:0xFFFFE12AD430 si_addr@:0xffffe12ad430 si_code:2 token@:(nil) offset:-281474459423792
1265 11:15:19.202141 # ==>> completed. PASS(1)
1266 11:15:19.202218 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1267 11:15:19.209912 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1268 11:15:19.253586 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1269 11:15:19.299518 # Registered handlers for all signals.
1270 11:15:19.299759 # Detected MINSTKSIGSZ:10000
1271 11:15:19.299956 # Testcase initialized.
1272 11:15:19.300143 # uc context validated.
1273 11:15:19.300352 # Handled SIG_TRIG
1274 11:15:19.300492 # SIG_OK -- SP:0xFFFFDB50CBF0 si_addr@:0xffffdb50cbf0 si_code:2 token@:(nil) offset:-281474361248752
1275 11:15:19.300636 # ==>> completed. PASS(1)
1276 11:15:19.300775 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1277 11:15:19.307331 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1278 11:15:19.350727 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1279 11:15:19.398387 # Registered handlers for all signals.
1280 11:15:19.398518 # Detected MINSTKSIGSZ:10000
1281 11:15:19.398603 # Testcase initialized.
1282 11:15:19.398864 # uc context validated.
1283 11:15:19.398965 # Handled SIG_TRIG
1284 11:15:19.399044 # SIG_OK -- SP:0xFFFFF3EBD080 si_addr@:0xfffff3ebd080 si_code:2 token@:(nil) offset:-281474774061184
1285 11:15:19.399123 # ==>> completed. PASS(1)
1286 11:15:19.399213 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1287 11:15:19.405499 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1288 11:15:19.448574 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1289 11:15:19.494975 # Registered handlers for all signals.
1290 11:15:19.495470 # Detected MINSTKSIGSZ:10000
1291 11:15:19.495648 # Testcase initialized.
1292 11:15:19.495782 # uc context validated.
1293 11:15:19.495906 # Handled SIG_TRIG
1294 11:15:19.496029 # SIG_OK -- SP:0xFFFFD3A123D0 si_addr@:0xffffd3a123d0 si_code:2 token@:(nil) offset:-281474232296400
1295 11:15:19.496151 # ==>> completed. PASS(1)
1296 11:15:19.496296 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1297 11:15:19.502915 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1298 11:15:19.546381 # selftests: arm64: sme_trap_no_sm
1299 11:15:19.658844 # Registered handlers for all signals.
1300 11:15:19.659060 # Detected MINSTKSIGSZ:10000
1301 11:15:19.659259 # Required Features: [ SME ] supported
1302 11:15:19.659412 # Incompatible Features: [] absent
1303 11:15:19.659534 # Testcase initialized.
1304 11:15:19.659857 # SIG_OK -- SP:0xFFFFD9CA1040 si_addr@:0xaaaad75e2514 si_code:1 token@:(nil) offset:-187650734433556
1305 11:15:19.659980 # ==>> completed. PASS(1)
1306 11:15:19.660092 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1307 11:15:19.677689 ok 19 selftests: arm64: sme_trap_no_sm
1308 11:15:19.764194 # selftests: arm64: sme_trap_non_streaming
1309 11:15:19.822373 # Registered handlers for all signals.
1310 11:15:19.822823 # Detected MINSTKSIGSZ:10000
1311 11:15:19.823015 # Required Features: [] NOT supported
1312 11:15:19.823185 # Incompatible Features: [] supported
1313 11:15:19.823362 # ==>> completed. SKIP.
1314 11:15:19.823498 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1315 11:15:19.831138 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1316 11:15:19.879214 # selftests: arm64: sme_trap_za
1317 11:15:19.927434 # Registered handlers for all signals.
1318 11:15:19.927627 # Detected MINSTKSIGSZ:10000
1319 11:15:19.927776 # Testcase initialized.
1320 11:15:19.928104 # SIG_OK -- SP:0xFFFFC1E03640 si_addr@:0xaaaade602510 si_code:1 token@:(nil) offset:-187650852005136
1321 11:15:19.928232 # ==>> completed. PASS(1)
1322 11:15:19.928349 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1323 11:15:19.935405 ok 21 selftests: arm64: sme_trap_za
1324 11:15:19.980401 # selftests: arm64: sme_vl
1325 11:15:20.031564 # Registered handlers for all signals.
1326 11:15:20.032079 # Detected MINSTKSIGSZ:10000
1327 11:15:20.032272 # Required Features: [ SME ] supported
1328 11:15:20.032447 # Incompatible Features: [] absent
1329 11:15:20.032592 # Testcase initialized.
1330 11:15:20.032757 # uc context validated.
1331 11:15:20.034784 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1332 11:15:20.034884 # Handled SIG_COPYCTX
1333 11:15:20.034964 # got expected VL 32
1334 11:15:20.035041 # ==>> completed. PASS(1)
1335 11:15:20.035311 # # SME VL :: Check that we get the right SME VL reported
1336 11:15:20.041719 ok 22 selftests: arm64: sme_vl
1337 11:15:20.086512 # selftests: arm64: ssve_regs
1338 11:15:20.267475 # Registered handlers for all signals.
1339 11:15:20.267891 # Detected MINSTKSIGSZ:10000
1340 11:15:20.268040 # Required Features: [ SME FA64 ] supported
1341 11:15:20.270894 # Incompatible Features: [] absent
1342 11:15:20.271295 # Testcase initialized.
1343 11:15:20.271486 # Testing VL 256
1344 11:15:20.271699 # Validating EXTRA...
1345 11:15:20.271850 # uc context validated.
1346 11:15:20.271998 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1347 11:15:20.272122 # Handled SIG_COPYCTX
1348 11:15:20.272240 # Got expected size 8752 and VL 256
1349 11:15:20.272355 # Testing VL 128
1350 11:15:20.278202 # Validating EXTRA...
1351 11:15:20.278425 # uc context validated.
1352 11:15:20.278729 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1353 11:15:20.278834 # Handled SIG_COPYCTX
1354 11:15:20.278920 # Got expected size 4384 and VL 128
1355 11:15:20.279003 # Testing VL 64
1356 11:15:20.279085 # uc context validated.
1357 11:15:20.279188 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1358 11:15:20.279274 # Handled SIG_COPYCTX
1359 11:15:20.279358 # Got expected size 2208 and VL 64
1360 11:15:20.279441 # Testing VL 32
1361 11:15:20.279524 # uc context validated.
1362 11:15:20.279608 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1363 11:15:20.279720 # Handled SIG_COPYCTX
1364 11:15:20.279811 # Got expected size 1120 and VL 32
1365 11:15:20.279900 # Testing VL 16
1366 11:15:20.279988 # uc context validated.
1367 11:15:20.280088 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1368 11:15:20.280191 # Handled SIG_COPYCTX
1369 11:15:20.280290 # Got expected size 576 and VL 16
1370 11:15:20.280374 # ==>> completed. PASS(1)
1371 11:15:20.280668 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1372 11:15:20.280789 ok 23 selftests: arm64: ssve_regs
1373 11:15:20.325876 # selftests: arm64: sve_regs
1374 11:15:20.766914 # Registered handlers for all signals.
1375 11:15:20.767176 # Detected MINSTKSIGSZ:10000
1376 11:15:20.767484 # Required Features: [ SVE ] supported
1377 11:15:20.767589 # Incompatible Features: [] absent
1378 11:15:20.767682 # Testcase initialized.
1379 11:15:20.768948 # Testing VL 256
1380 11:15:20.769057 # Validating EXTRA...
1381 11:15:20.769347 # uc context validated.
1382 11:15:20.769452 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1383 11:15:20.769543 # Handled SIG_COPYCTX
1384 11:15:20.769627 # Got expected size 8752 and VL 256
1385 11:15:20.769720 # Testing VL 240
1386 11:15:20.769819 # Validating EXTRA...
1387 11:15:20.769907 # uc context validated.
1388 11:15:20.769990 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1389 11:15:20.770074 # Handled SIG_COPYCTX
1390 11:15:20.770173 # Got expected size 8208 and VL 240
1391 11:15:20.770260 # Testing VL 224
1392 11:15:20.770343 # Validating EXTRA...
1393 11:15:20.770427 # uc context validated.
1394 11:15:20.770526 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1395 11:15:20.770617 # Handled SIG_COPYCTX
1396 11:15:20.770698 # Got expected size 7664 and VL 224
1397 11:15:20.770782 # Testing VL 208
1398 11:15:20.770881 # Validating EXTRA...
1399 11:15:20.770968 # uc context validated.
1400 11:15:20.771055 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1401 11:15:20.771159 # Handled SIG_COPYCTX
1402 11:15:20.771248 # Got expected size 7120 and VL 208
1403 11:15:20.771333 # Testing VL 192
1404 11:15:20.777835 # Validating EXTRA...
1405 11:15:20.777974 # uc context validated.
1406 11:15:20.778255 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1407 11:15:20.778347 # Handled SIG_COPYCTX
1408 11:15:20.778434 # Got expected size 6576 and VL 192
1409 11:15:20.778519 # Testing VL 176
1410 11:15:20.778602 # Validating EXTRA...
1411 11:15:20.778702 # uc context validated.
1412 11:15:20.778788 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1413 11:15:20.778871 # Handled SIG_COPYCTX
1414 11:15:20.778955 # Got expected size 6032 and VL 176
1415 11:15:20.779056 # Testing VL 160
1416 11:15:20.779142 # Validating EXTRA...
1417 11:15:20.779229 # uc context validated.
1418 11:15:20.779315 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1419 11:15:20.779404 # Handled SIG_COPYCTX
1420 11:15:20.779695 # Got expected size 5488 and VL 160
1421 11:15:20.779786 # Testing VL 144
1422 11:15:20.779871 # Validating EXTRA...
1423 11:15:20.779956 # uc context validated.
1424 11:15:20.780054 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1425 11:15:20.780140 # Handled SIG_COPYCTX
1426 11:15:20.780224 # Got expected size 4944 and VL 144
1427 11:15:20.780304 # Testing VL 128
1428 11:15:20.780403 # Validating EXTRA...
1429 11:15:20.780488 # uc context validated.
1430 11:15:20.780571 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1431 11:15:20.780671 # Handled SIG_COPYCTX
1432 11:15:20.780757 # Got expected size 4384 and VL 128
1433 11:15:20.780838 # Testing VL 112
1434 11:15:20.780936 # Validating EXTRA...
1435 11:15:20.781022 # uc context validated.
1436 11:15:20.781122 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1437 11:15:20.781209 # Handled SIG_COPYCTX
1438 11:15:20.781307 # Got expected size 3840 and VL 112
1439 11:15:20.781392 # Testing VL 96
1440 11:15:20.781478 # uc context validated.
1441 11:15:20.781577 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1442 11:15:20.781684 # Handled SIG_COPYCTX
1443 11:15:20.781785 # Got expected size 3296 and VL 96
1444 11:15:20.781885 # Testing VL 80
1445 11:15:20.781971 # uc context validated.
1446 11:15:20.782069 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1447 11:15:20.782156 # Handled SIG_COPYCTX
1448 11:15:20.782255 # Got expected size 2752 and VL 80
1449 11:15:20.782353 # Testing VL 64
1450 11:15:20.782452 # uc context validated.
1451 11:15:20.782735 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1452 11:15:20.782826 # Handled SIG_COPYCTX
1453 11:15:20.782912 # Got expected size 2208 and VL 64
1454 11:15:20.782996 # Testing VL 48
1455 11:15:20.783101 # uc context validated.
1456 11:15:20.783191 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1457 11:15:20.783278 # Handled SIG_COPYCTX
1458 11:15:20.783363 # Got expected size 1664 and VL 48
1459 11:15:20.790041 # Testing VL 32
1460 11:15:20.790236 # uc context validated.
1461 11:15:20.790325 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1462 11:15:20.790622 # Handled SIG_COPYCTX
1463 11:15:20.790723 # Got expected size 1120 and VL 32
1464 11:15:20.790811 # Testing VL 16
1465 11:15:20.790897 # uc context validated.
1466 11:15:20.790983 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1467 11:15:20.791071 # Handled SIG_COPYCTX
1468 11:15:20.791175 # Got expected size 576 and VL 16
1469 11:15:20.791265 # ==>> completed. PASS(1)
1470 11:15:20.791353 # # SVE registers :: Check that we get the right SVE registers reported
1471 11:15:20.791886 ok 24 selftests: arm64: sve_regs
1472 11:15:20.846286 # selftests: arm64: sve_vl
1473 11:15:20.899520 # Registered handlers for all signals.
1474 11:15:20.899753 # Detected MINSTKSIGSZ:10000
1475 11:15:20.899846 # Required Features: [ SVE ] supported
1476 11:15:20.899951 # Incompatible Features: [] absent
1477 11:15:20.900040 # Testcase initialized.
1478 11:15:20.900126 # uc context validated.
1479 11:15:20.900213 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1480 11:15:20.900301 # Handled SIG_COPYCTX
1481 11:15:20.900388 # got expected VL 64
1482 11:15:20.900488 # ==>> completed. PASS(1)
1483 11:15:20.900577 # # SVE VL :: Check that we get the right SVE VL reported
1484 11:15:20.908895 ok 25 selftests: arm64: sve_vl
1485 11:15:20.954786 # selftests: arm64: za_no_regs
1486 11:15:21.012742 # Registered handlers for all signals.
1487 11:15:21.013333 # Detected MINSTKSIGSZ:10000
1488 11:15:21.013524 # Required Features: [ SME ] supported
1489 11:15:21.013717 # Incompatible Features: [] absent
1490 11:15:21.013888 # Testcase initialized.
1491 11:15:21.014055 # Testing VL 256
1492 11:15:21.014220 # uc context validated.
1493 11:15:21.014384 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1494 11:15:21.014548 # Handled SIG_COPYCTX
1495 11:15:21.014703 # Got expected size 16 and VL 256
1496 11:15:21.014874 # Testing VL 128
1497 11:15:21.015001 # uc context validated.
1498 11:15:21.015118 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1499 11:15:21.015236 # Handled SIG_COPYCTX
1500 11:15:21.015351 # Got expected size 16 and VL 128
1501 11:15:21.015468 # Testing VL 64
1502 11:15:21.015584 # uc context validated.
1503 11:15:21.015699 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1504 11:15:21.015816 # Handled SIG_COPYCTX
1505 11:15:21.015931 # Got expected size 16 and VL 64
1506 11:15:21.016047 # Testing VL 32
1507 11:15:21.016162 # uc context validated.
1508 11:15:21.016278 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1509 11:15:21.016393 # Handled SIG_COPYCTX
1510 11:15:21.016507 # Got expected size 16 and VL 32
1511 11:15:21.016622 # Testing VL 16
1512 11:15:21.016737 # uc context validated.
1513 11:15:21.016852 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1514 11:15:21.016970 # Handled SIG_COPYCTX
1515 11:15:21.022137 # Got expected size 16 and VL 16
1516 11:15:21.022317 # ==>> completed. PASS(1)
1517 11:15:21.022665 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1518 11:15:21.022839 ok 26 selftests: arm64: za_no_regs
1519 11:15:21.113976 # selftests: arm64: za_regs
1520 11:15:21.290986 # Registered handlers for all signals.
1521 11:15:21.291520 # Detected MINSTKSIGSZ:10000
1522 11:15:21.291632 # Required Features: [ SME ] supported
1523 11:15:21.291725 # Incompatible Features: [] absent
1524 11:15:21.291812 # Testcase initialized.
1525 11:15:21.291896 # Testing VL 256
1526 11:15:21.291983 # Validating EXTRA...
1527 11:15:21.292065 # uc context validated.
1528 11:15:21.292149 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1529 11:15:21.292252 # Handled SIG_COPYCTX
1530 11:15:21.292339 # Got expected size 65552 and VL 256
1531 11:15:21.292421 # Testing VL 128
1532 11:15:21.292504 # Validating EXTRA...
1533 11:15:21.292586 # uc context validated.
1534 11:15:21.292669 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1535 11:15:21.292754 # Handled SIG_COPYCTX
1536 11:15:21.292838 # Got expected size 16400 and VL 128
1537 11:15:21.292937 # Testing VL 64
1538 11:15:21.293024 # Validating EXTRA...
1539 11:15:21.293106 # uc context validated.
1540 11:15:21.293189 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1541 11:15:21.293273 # Handled SIG_COPYCTX
1542 11:15:21.293354 # Got expected size 4112 and VL 64
1543 11:15:21.293434 # Testing VL 32
1544 11:15:21.293517 # uc context validated.
1545 11:15:21.293617 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1546 11:15:21.293714 # Handled SIG_COPYCTX
1547 11:15:21.293796 # Got expected size 1040 and VL 32
1548 11:15:21.293880 # Testing VL 16
1549 11:15:21.293964 # uc context validated.
1550 11:15:21.294049 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1551 11:15:21.294136 # Handled SIG_COPYCTX
1552 11:15:21.294239 # Got expected size 272 and VL 16
1553 11:15:21.294328 # ==>> completed. PASS(1)
1554 11:15:21.294412 # # ZA register :: Check that we get the right ZA registers reported
1555 11:15:21.303473 ok 27 selftests: arm64: za_regs
1556 11:15:21.346962 # selftests: arm64: pac
1557 11:15:21.609091 # TAP version 13
1558 11:15:21.609432 # 1..7
1559 11:15:21.610118 # # Starting 7 tests from 1 test cases.
1560 11:15:21.610295 # # RUN global.corrupt_pac ...
1561 11:15:21.610469 # # OK global.corrupt_pac
1562 11:15:21.610621 # ok 1 global.corrupt_pac
1563 11:15:21.610767 # # RUN global.pac_instructions_not_nop ...
1564 11:15:21.610912 # # OK global.pac_instructions_not_nop
1565 11:15:21.611056 # ok 2 global.pac_instructions_not_nop
1566 11:15:21.611202 # # RUN global.pac_instructions_not_nop_generic ...
1567 11:15:21.611346 # # OK global.pac_instructions_not_nop_generic
1568 11:15:21.617708 # ok 3 global.pac_instructions_not_nop_generic
1569 11:15:21.618122 # # RUN global.single_thread_different_keys ...
1570 11:15:21.618213 # # OK global.single_thread_different_keys
1571 11:15:21.618286 # ok 4 global.single_thread_different_keys
1572 11:15:21.619313 # # RUN global.exec_changed_keys ...
1573 11:15:21.619746 # # OK global.exec_changed_keys
1574 11:15:21.619854 # ok 5 global.exec_changed_keys
1575 11:15:21.619943 # # RUN global.context_switch_keep_keys ...
1576 11:15:21.620045 # # OK global.context_switch_keep_keys
1577 11:15:21.620132 # ok 6 global.context_switch_keep_keys
1578 11:15:21.620237 # # RUN global.context_switch_keep_keys_generic ...
1579 11:15:21.620578 # # OK global.context_switch_keep_keys_generic
1580 11:15:21.620682 # ok 7 global.context_switch_keep_keys_generic
1581 11:15:21.620784 # # PASSED: 7 / 7 tests passed.
1582 11:15:21.620876 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1583 11:15:21.621180 ok 28 selftests: arm64: pac
1584 11:15:21.668076 # selftests: arm64: fp-stress
1585 11:15:39.709192 # TAP version 13
1586 11:15:39.709431 # 1..27
1587 11:15:39.709525 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1588 11:15:39.709815 # # Will run for 10s
1589 11:15:39.709925 # # Started FPSIMD-0-0
1590 11:15:39.710017 # # Started SVE-VL-256-0
1591 11:15:39.710104 # # Started SVE-VL-240-0
1592 11:15:39.710190 # # Started SVE-VL-224-0
1593 11:15:39.710275 # # Started SVE-VL-208-0
1594 11:15:39.710361 # # Started SVE-VL-192-0
1595 11:15:39.710446 # # Started SVE-VL-176-0
1596 11:15:39.710529 # # Started SVE-VL-160-0
1597 11:15:39.710613 # # Started SVE-VL-144-0
1598 11:15:39.710714 # # Started SVE-VL-128-0
1599 11:15:39.710996 # # Started SVE-VL-112-0
1600 11:15:39.711090 # # Started SVE-VL-96-0
1601 11:15:39.711176 # # Started SVE-VL-80-0
1602 11:15:39.711260 # # Started SVE-VL-64-0
1603 11:15:39.711343 # # Started SVE-VL-48-0
1604 11:15:39.711427 # # Started SVE-VL-32-0
1605 11:15:39.711509 # # Started SVE-VL-16-0
1606 11:15:39.711591 # # Started SSVE-VL-256-0
1607 11:15:39.711677 # # Started ZA-VL-256-0
1608 11:15:39.711761 # # Started SSVE-VL-128-0
1609 11:15:39.711846 # # Started ZA-VL-128-0
1610 11:15:39.714832 # # Started SSVE-VL-64-0
1611 11:15:39.715230 # # Started ZA-VL-64-0
1612 11:15:39.715334 # # Started SSVE-VL-32-0
1613 11:15:39.715443 # # Started ZA-VL-32-0
1614 11:15:39.715738 # # SVE-VL-256-0: Vector length: 2048 bits
1615 11:15:39.715845 # # SVE-VL-256-0: PID: 912
1616 11:15:39.715988 # # SVE-VL-208-0: Vector length: 1664 bits
1617 11:15:39.716083 # # SVE-VL-208-0: PID: 915
1618 11:15:39.716183 # # FPSIMD-0-0: Vector length: 128 bits
1619 11:15:39.716286 # # FPSIMD-0-0: PID: 911
1620 11:15:39.716397 # # SVE-VL-240-0: Vector length: 1920 bits
1621 11:15:39.716498 # # SVE-VL-240-0: PID: 913
1622 11:15:39.716600 # # SVE-VL-176-0: Vector length: 1408 bits
1623 11:15:39.716915 # # SVE-VL-176-0: PID: 917
1624 11:15:39.717023 # # Started SSVE-VL-16-0
1625 11:15:39.717475 # # SVE-VL-112-0: Vector length: 896 bits
1626 11:15:39.717573 # # SVE-VL-112-0: PID: 921
1627 11:15:39.717667 # # SVE-VL-96-0: Vector length: 768 bits
1628 11:15:39.717768 # # SVE-VL-96-0: PID: 922
1629 11:15:39.717865 # # SVE-VL-224-0: Vector length: 1792 bits
1630 11:15:39.717954 # # SVE-VL-224-0: PID: 914
1631 11:15:39.718059 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1632 11:15:39.718152 # # SSVE-VL-256-0: PID: 928
1633 11:15:39.718239 # # SVE-VL-80-0: Vector length: 640 bits
1634 11:15:39.718319 # # SVE-VL-80-0: PID: 923
1635 11:15:39.718394 # # Started ZA-VL-16-0
1636 11:15:39.718470 # # SVE-VL-64-0: Vector length: 512 bits
1637 11:15:39.718562 # # SVE-VL-64-0: PID: 924
1638 11:15:39.718641 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1639 11:15:39.718718 # # SVE-VL-128-0: Vector length: 1024 bits
1640 11:15:39.718802 # # SVE-VL-128-0: PID: 920
1641 11:15:39.718884 # # SVE-VL-192-0: Vector length: 1536 bits
1642 11:15:39.718985 # # SVE-VL-192-0: PID: 916
1643 11:15:39.719064 # # SVE-VL-160-0: Vector length: 1280 bits
1644 11:15:39.719141 # # SVE-VL-160-0: PID: 918
1645 11:15:39.720882 # # SVE-VL-32-0: Vector length: 256 bits
1646 11:15:39.721141 # # SVE-VL-32-0: PID: 926
1647 11:15:39.721237 # # SVE-VL-48-0: Vector length: 384 bits
1648 11:15:39.721316 # # SVE-VL-48-0: PID: 925
1649 11:15:39.721405 # # SSVE-VL-128-0: PID: 930
1650 11:15:39.721489 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1651 11:15:39.721587 # # SSVE-VL-16-0: PID: 936
1652 11:15:39.721849 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1653 11:15:39.721958 # # ZA-VL-32-0: PID: 935
1654 11:15:39.722103 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1655 11:15:39.722205 # # SSVE-VL-64-0: PID: 932
1656 11:15:39.722300 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1657 11:15:39.722399 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1658 11:15:39.722490 # # SSVE-VL-32-0: PID: 934
1659 11:15:39.722582 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1660 11:15:39.722671 # # SVE-VL-144-0: Vector length: 1152 bits
1661 11:15:39.722765 # # SVE-VL-144-0: PID: 919
1662 11:15:39.768258 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1663 11:15:39.768593 # # ZA-VL-128-0: PID: 931
1664 11:15:39.768779 # # ZA-VL-256-0: PID: 929
1665 11:15:39.769210 # # ZA-VL-64-0: PID: 933
1666 11:15:39.769318 # # SVE-VL-16-0: Vector length: 128 bits
1667 11:15:39.769413 # # SVE-VL-16-0: PID: 927
1668 11:15:39.769502 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1669 11:15:39.769591 # # ZA-VL-16-0: PID: 937
1670 11:15:39.769685 # # Finishing up...
1671 11:15:39.769772 # ok 1 FPSIMD-0-0
1672 11:15:39.769859 # ok 2 SVE-VL-256-0
1673 11:15:39.769946 # ok 3 SVE-VL-240-0
1674 11:15:39.770033 # ok 4 SVE-VL-224-0
1675 11:15:39.770118 # ok 5 SVE-VL-208-0
1676 11:15:39.770204 # ok 6 SVE-VL-192-0
1677 11:15:39.770287 # ok 7 SVE-VL-176-0
1678 11:15:39.770391 # ok 8 SVE-VL-160-0
1679 11:15:39.770479 # ok 9 SVE-VL-144-0
1680 11:15:39.770565 # ok 10 SVE-VL-128-0
1681 11:15:39.770648 # ok 11 SVE-VL-112-0
1682 11:15:39.770730 # ok 12 SVE-VL-96-0
1683 11:15:39.770813 # ok 13 SVE-VL-80-0
1684 11:15:39.770895 # ok 14 SVE-VL-64-0
1685 11:15:39.770979 # ok 15 SVE-VL-48-0
1686 11:15:39.771062 # ok 16 SVE-VL-32-0
1687 11:15:39.771143 # ok 17 SVE-VL-16-0
1688 11:15:39.771227 # ok 18 SSVE-VL-256-0
1689 11:15:39.771307 # ok 19 ZA-VL-256-0
1690 11:15:39.771390 # ok 20 SSVE-VL-128-0
1691 11:15:39.771472 # ok 21 ZA-VL-128-0
1692 11:15:39.771554 # ok 22 SSVE-VL-64-0
1693 11:15:39.771636 # ok 23 ZA-VL-64-0
1694 11:15:39.771717 # ok 24 SSVE-VL-32-0
1695 11:15:39.771816 # ok 25 ZA-VL-32-0
1696 11:15:39.771901 # ok 26 SSVE-VL-16-0
1697 11:15:39.771981 # ok 27 ZA-VL-16-0
1698 11:15:39.772062 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=3761, signals=9
1699 11:15:39.793042 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=2294, signals=9
1700 11:15:39.793576 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=808, signals=9
1701 11:15:39.793775 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=4887, signals=9
1702 11:15:39.793954 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=257, signals=9
1703 11:15:39.794105 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=1886, signals=9
1704 11:15:39.794287 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=3325, signals=9
1705 11:15:39.794425 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=7278, signals=9
1706 11:15:39.794569 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=6382, signals=9
1707 11:15:39.794724 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=3543, signals=9
1708 11:15:39.808813 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=4613, signals=9
1709 11:15:39.809084 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=4022, signals=9
1710 11:15:39.809257 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=5766, signals=9
1711 11:15:39.809414 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=3135, signals=9
1712 11:15:39.809578 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=2886, signals=9
1713 11:15:39.809799 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=11018, signals=9
1714 11:15:39.809991 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=3180, signals=9
1715 11:15:39.810128 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=11840, signals=9
1716 11:15:39.810303 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=7572, signals=9
1717 11:15:39.810485 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=1452, signals=9
1718 11:15:39.810665 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=10626, signals=9
1719 11:15:39.810938 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=4046, signals=9
1720 11:15:39.811092 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=6794, signals=9
1721 11:15:39.811216 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=4722, signals=9
1722 11:15:39.811380 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=13496, signals=9
1723 11:15:39.811516 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=8456, signals=9
1724 11:15:39.813470 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=3177, signals=9
1725 11:15:39.813680 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1726 11:15:39.813854 ok 29 selftests: arm64: fp-stress
1727 11:15:39.861350 # selftests: arm64: sve-ptrace
1728 11:15:39.942815 # TAP version 13
1729 11:15:39.943106 # 1..4104
1730 11:15:39.943453 # # Parent is 954, child is 955
1731 11:15:39.943564 # ok 1 SVE FPSIMD set via SVE: 0
1732 11:15:39.943655 # ok 2 SVE get_fpsimd() gave same state
1733 11:15:39.943739 # ok 3 SVE SVE_PT_VL_INHERIT set
1734 11:15:39.943827 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1735 11:15:39.943913 # ok 5 Set SVE VL 16
1736 11:15:39.943999 # ok 6 Set and get SVE data for VL 16
1737 11:15:39.944102 # ok 7 Set and get FPSIMD data for SVE VL 16
1738 11:15:39.944190 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1739 11:15:39.944275 # ok 9 Set SVE VL 32
1740 11:15:39.944359 # ok 10 Set and get SVE data for VL 32
1741 11:15:39.944443 # ok 11 Set and get FPSIMD data for SVE VL 32
1742 11:15:39.944527 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1743 11:15:39.944613 # ok 13 Set SVE VL 48
1744 11:15:39.944713 # ok 14 Set and get SVE data for VL 48
1745 11:15:39.944800 # ok 15 Set and get FPSIMD data for SVE VL 48
1746 11:15:39.944884 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1747 11:15:39.944970 # ok 17 Set SVE VL 64
1748 11:15:39.945074 # ok 18 Set and get SVE data for VL 64
1749 11:15:39.945162 # ok 19 Set and get FPSIMD data for SVE VL 64
1750 11:15:39.945246 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1751 11:15:39.945332 # ok 21 Set SVE VL 80
1752 11:15:39.945432 # ok 22 Set and get SVE data for VL 80
1753 11:15:39.945520 # ok 23 Set and get FPSIMD data for SVE VL 80
1754 11:15:39.945606 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1755 11:15:39.945715 # ok 25 Set SVE VL 96
1756 11:15:39.945804 # ok 26 Set and get SVE data for VL 96
1757 11:15:39.945889 # ok 27 Set and get FPSIMD data for SVE VL 96
1758 11:15:39.945990 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1759 11:15:39.946076 # ok 29 Set SVE VL 112
1760 11:15:39.946175 # ok 30 Set and get SVE data for VL 112
1761 11:15:39.946263 # ok 31 Set and get FPSIMD data for SVE VL 112
1762 11:15:39.946363 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1763 11:15:39.946467 # ok 33 Set SVE VL 128
1764 11:15:39.946568 # ok 34 Set and get SVE data for VL 128
1765 11:15:39.946894 # ok 35 Set and get FPSIMD data for SVE VL 128
1766 11:15:39.947057 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1767 11:15:39.948648 # ok 37 Set SVE VL 144
1768 11:15:39.949046 # ok 38 Set and get SVE data for VL 144
1769 11:15:39.949183 # ok 39 Set and get FPSIMD data for SVE VL 144
1770 11:15:39.949304 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1771 11:15:39.949456 # ok 41 Set SVE VL 160
1772 11:15:39.949590 # ok 42 Set and get SVE data for VL 160
1773 11:15:39.949781 # ok 43 Set and get FPSIMD data for SVE VL 160
1774 11:15:39.949927 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1775 11:15:39.950047 # ok 45 Set SVE VL 176
1776 11:15:39.950164 # ok 46 Set and get SVE data for VL 176
1777 11:15:39.950282 # ok 47 Set and get FPSIMD data for SVE VL 176
1778 11:15:39.950398 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1779 11:15:39.950515 # ok 49 Set SVE VL 192
1780 11:15:39.950630 # ok 50 Set and get SVE data for VL 192
1781 11:15:39.950808 # ok 51 Set and get FPSIMD data for SVE VL 192
1782 11:15:39.950982 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1783 11:15:39.951107 # ok 53 Set SVE VL 208
1784 11:15:39.951223 # ok 54 Set and get SVE data for VL 208
1785 11:15:39.951338 # ok 55 Set and get FPSIMD data for SVE VL 208
1786 11:15:39.951454 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1787 11:15:39.951568 # ok 57 Set SVE VL 224
1788 11:15:39.951682 # ok 58 Set and get SVE data for VL 224
1789 11:15:39.951850 # ok 59 Set and get FPSIMD data for SVE VL 224
1790 11:15:39.951975 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1791 11:15:39.952129 # ok 61 Set SVE VL 240
1792 11:15:39.952257 # ok 62 Set and get SVE data for VL 240
1793 11:15:39.952373 # ok 63 Set and get FPSIMD data for SVE VL 240
1794 11:15:39.952488 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1795 11:15:39.952604 # ok 65 Set SVE VL 256
1796 11:15:39.952746 # ok 66 Set and get SVE data for VL 256
1797 11:15:39.952927 # ok 67 Set and get FPSIMD data for SVE VL 256
1798 11:15:39.953053 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1799 11:15:39.953215 # ok 69 Set SVE VL 272
1800 11:15:39.953396 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1801 11:15:39.953550 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1802 11:15:39.953749 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1803 11:15:39.953932 # ok 73 Set SVE VL 288
1804 11:15:39.954077 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1805 11:15:39.954194 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1806 11:15:39.954309 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1807 11:15:39.954423 # ok 77 Set SVE VL 304
1808 11:15:39.954536 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1809 11:15:39.954653 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1810 11:15:39.954767 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1811 11:15:39.954882 # ok 81 Set SVE VL 320
1812 11:15:39.954994 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1813 11:15:39.955108 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1814 11:15:39.955220 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1815 11:15:39.955332 # ok 85 Set SVE VL 336
1816 11:15:39.955670 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1817 11:15:39.955796 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1818 11:15:39.955915 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1819 11:15:39.956029 # ok 89 Set SVE VL 352
1820 11:15:39.956142 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1821 11:15:39.956257 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1822 11:15:39.956371 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1823 11:15:39.956485 # ok 93 Set SVE VL 368
1824 11:15:39.956598 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1825 11:15:39.956711 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1826 11:15:39.956823 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1827 11:15:39.956936 # ok 97 Set SVE VL 384
1828 11:15:39.957048 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1829 11:15:39.957161 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1830 11:15:39.957278 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1831 11:15:39.957391 # ok 101 Set SVE VL 400
1832 11:15:39.957503 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1833 11:15:39.957616 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1834 11:15:39.957740 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1835 11:15:39.957854 # ok 105 Set SVE VL 416
1836 11:15:39.957967 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1837 11:15:39.958080 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1838 11:15:39.958193 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1839 11:15:39.958306 # ok 109 Set SVE VL 432
1840 11:15:39.963666 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1841 11:15:39.963795 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1842 11:15:39.964115 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1843 11:15:39.964241 # ok 113 Set SVE VL 448
1844 11:15:39.964417 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1845 11:15:39.964591 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1846 11:15:39.964767 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1847 11:15:39.964931 # ok 117 Set SVE VL 464
1848 11:15:39.965127 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1849 11:15:39.965298 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1850 11:15:39.965466 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1851 11:15:39.965637 # ok 121 Set SVE VL 480
1852 11:15:39.965822 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1853 11:15:39.965996 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1854 11:15:39.966181 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1855 11:15:39.966374 # ok 125 Set SVE VL 496
1856 11:15:39.966548 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1857 11:15:39.966720 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1858 11:15:39.966954 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1859 11:15:39.967096 # ok 129 Set SVE VL 512
1860 11:15:39.967212 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1861 11:15:39.967326 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1862 11:15:39.967438 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1863 11:15:39.967550 # ok 133 Set SVE VL 528
1864 11:15:39.967662 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1865 11:15:39.967773 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1866 11:15:39.967885 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1867 11:15:39.967999 # ok 137 Set SVE VL 544
1868 11:15:39.968110 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1869 11:15:39.968222 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1870 11:15:39.968333 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1871 11:15:39.968445 # ok 141 Set SVE VL 560
1872 11:15:39.968558 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1873 11:15:39.968670 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1874 11:15:39.968782 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1875 11:15:39.968894 # ok 145 Set SVE VL 576
1876 11:15:39.969005 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1877 11:15:39.969118 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1878 11:15:39.972102 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1879 11:15:39.972303 # ok 149 Set SVE VL 592
1880 11:15:39.972727 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1881 11:15:39.972834 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1882 11:15:39.972930 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1883 11:15:39.973017 # ok 153 Set SVE VL 608
1884 11:15:39.973102 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1885 11:15:39.973202 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1886 11:15:39.973302 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1887 11:15:39.973403 # ok 157 Set SVE VL 624
1888 11:15:39.973489 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1889 11:15:39.973587 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1890 11:15:39.973696 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1891 11:15:39.973783 # ok 161 Set SVE VL 640
1892 11:15:39.973880 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1893 11:15:39.973979 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1894 11:15:39.974271 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1895 11:15:39.974364 # ok 165 Set SVE VL 656
1896 11:15:39.974466 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1897 11:15:39.974555 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1898 11:15:39.974659 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1899 11:15:39.974777 # ok 169 Set SVE VL 672
1900 11:15:39.975285 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1901 11:15:39.975593 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1902 11:15:39.975698 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1903 11:15:39.975785 # ok 173 Set SVE VL 688
1904 11:15:39.975879 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1905 11:15:39.975963 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1906 11:15:39.976042 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1907 11:15:39.976142 # ok 177 Set SVE VL 704
1908 11:15:39.976221 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1909 11:15:39.976297 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1910 11:15:39.976386 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1911 11:15:39.976464 # ok 181 Set SVE VL 720
1912 11:15:39.976555 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1913 11:15:39.976641 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1914 11:15:39.976735 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1915 11:15:39.977079 # ok 185 Set SVE VL 736
1916 11:15:39.977182 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1917 11:15:39.977262 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1918 11:15:39.977339 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1919 11:15:39.977416 # ok 189 Set SVE VL 752
1920 11:15:39.977513 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1921 11:15:39.977596 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1922 11:15:39.977681 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1923 11:15:39.977760 # ok 193 Set SVE VL 768
1924 11:15:39.977857 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1925 11:15:39.977940 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1926 11:15:39.978032 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1927 11:15:39.978113 # ok 197 Set SVE VL 784
1928 11:15:39.978465 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1929 11:15:39.978806 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1930 11:15:39.978964 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1931 11:15:39.986981 # ok 201 Set SVE VL 800
1932 11:15:39.987401 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1933 11:15:39.987573 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1934 11:15:39.987736 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1935 11:15:39.987885 # ok 205 Set SVE VL 816
1936 11:15:39.988057 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1937 11:15:39.988224 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1938 11:15:39.988397 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1939 11:15:39.988542 # ok 209 Set SVE VL 832
1940 11:15:39.988685 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1941 11:15:39.988828 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1942 11:15:39.988971 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1943 11:15:39.989112 # ok 213 Set SVE VL 848
1944 11:15:39.989253 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1945 11:15:39.989448 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1946 11:15:39.989585 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1947 11:15:39.989741 # ok 217 Set SVE VL 864
1948 11:15:39.989883 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1949 11:15:39.990028 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1950 11:15:39.990169 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1951 11:15:39.990311 # ok 221 Set SVE VL 880
1952 11:15:39.990452 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1953 11:15:39.990593 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1954 11:15:39.990737 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1955 11:15:39.990878 # ok 225 Set SVE VL 896
1956 11:15:39.991021 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1957 11:15:39.991162 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1958 11:15:39.991303 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1959 11:15:39.991443 # ok 229 Set SVE VL 912
1960 11:15:39.991583 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1961 11:15:39.991766 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1962 11:15:39.991900 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1963 11:15:39.992047 # ok 233 Set SVE VL 928
1964 11:15:39.992188 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1965 11:15:39.992329 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1966 11:15:39.992470 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1967 11:15:39.992611 # ok 237 Set SVE VL 944
1968 11:15:39.992753 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1969 11:15:39.992895 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1970 11:15:39.993040 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1971 11:15:39.993182 # ok 241 Set SVE VL 960
1972 11:15:39.993324 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1973 11:15:39.993466 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1974 11:15:39.993606 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1975 11:15:39.993760 # ok 245 Set SVE VL 976
1976 11:15:39.998002 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1977 11:15:39.998165 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1978 11:15:39.998334 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1979 11:15:39.998491 # ok 249 Set SVE VL 992
1980 11:15:39.998642 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1981 11:15:39.998803 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1982 11:15:39.998925 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1983 11:15:39.999068 # ok 253 Set SVE VL 1008
1984 11:15:39.999245 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1985 11:15:39.999390 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1986 11:15:39.999571 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1987 11:15:39.999707 # ok 257 Set SVE VL 1024
1988 11:15:39.999849 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1989 11:15:39.999993 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1990 11:15:40.000135 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1991 11:15:40.000275 # ok 261 Set SVE VL 1040
1992 11:15:40.000416 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1993 11:15:40.000598 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1994 11:15:40.000732 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1995 11:15:40.000874 # ok 265 Set SVE VL 1056
1996 11:15:40.001016 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1997 11:15:40.001157 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1998 11:15:40.001297 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1999 11:15:40.001439 # ok 269 Set SVE VL 1072
2000 11:15:40.001580 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
2001 11:15:40.001736 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
2002 11:15:40.001879 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2003 11:15:40.002021 # ok 273 Set SVE VL 1088
2004 11:15:40.002162 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2005 11:15:40.002304 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2006 11:15:40.002445 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2007 11:15:40.002625 # ok 277 Set SVE VL 1104
2008 11:15:40.002762 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2009 11:15:40.002903 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2010 11:15:40.003047 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2011 11:15:40.003189 # ok 281 Set SVE VL 1120
2012 11:15:40.003329 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2013 11:15:40.003469 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2014 11:15:40.003611 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2015 11:15:40.003753 # ok 285 Set SVE VL 1136
2016 11:15:40.003894 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2017 11:15:40.004035 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2018 11:15:40.004176 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2019 11:15:40.004318 # ok 289 Set SVE VL 1152
2020 11:15:40.004675 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2021 11:15:40.004813 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2022 11:15:40.004958 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2023 11:15:40.005102 # ok 293 Set SVE VL 1168
2024 11:15:40.005243 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2025 11:15:40.005384 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2026 11:15:40.005526 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2027 11:15:40.005679 # ok 297 Set SVE VL 1184
2028 11:15:40.005823 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2029 11:15:40.005964 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2030 11:15:40.006106 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2031 11:15:40.006248 # ok 301 Set SVE VL 1200
2032 11:15:40.006390 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2033 11:15:40.006530 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2034 11:15:40.011170 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2035 11:15:40.011378 # ok 305 Set SVE VL 1216
2036 11:15:40.011749 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2037 11:15:40.011856 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2038 11:15:40.011944 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2039 11:15:40.012028 # ok 309 Set SVE VL 1232
2040 11:15:40.012111 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2041 11:15:40.012193 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2042 11:15:40.012293 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2043 11:15:40.012379 # ok 313 Set SVE VL 1248
2044 11:15:40.012462 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2045 11:15:40.012546 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2046 11:15:40.012643 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2047 11:15:40.012728 # ok 317 Set SVE VL 1264
2048 11:15:40.012822 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2049 11:15:40.012922 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2050 11:15:40.013012 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2051 11:15:40.013110 # ok 321 Set SVE VL 1280
2052 11:15:40.013208 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2053 11:15:40.013304 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2054 11:15:40.013630 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2055 11:15:40.013784 # ok 325 Set SVE VL 1296
2056 11:15:40.014076 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2057 11:15:40.014180 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2058 11:15:40.014271 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2059 11:15:40.014351 # ok 329 Set SVE VL 1312
2060 11:15:40.014442 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2061 11:15:40.014521 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2062 11:15:40.014597 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2063 11:15:40.014689 # ok 333 Set SVE VL 1328
2064 11:15:40.014787 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2065 11:15:40.015069 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2066 11:15:40.015168 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2067 11:15:40.018915 # ok 337 Set SVE VL 1344
2068 11:15:40.019252 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2069 11:15:40.019448 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2070 11:15:40.019647 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2071 11:15:40.019845 # ok 341 Set SVE VL 1360
2072 11:15:40.020046 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2073 11:15:40.020227 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2074 11:15:40.020420 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2075 11:15:40.020590 # ok 345 Set SVE VL 1376
2076 11:15:40.020750 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2077 11:15:40.020896 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2078 11:15:40.021057 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2079 11:15:40.021216 # ok 349 Set SVE VL 1392
2080 11:15:40.021351 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2081 11:15:40.021558 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2082 11:15:40.021819 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2083 11:15:40.022019 # ok 353 Set SVE VL 1408
2084 11:15:40.022193 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2085 11:15:40.022368 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2086 11:15:40.022523 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2087 11:15:40.022684 # ok 357 Set SVE VL 1424
2088 11:15:40.022830 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2089 11:15:40.022949 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2090 11:15:40.023064 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2091 11:15:40.023177 # ok 361 Set SVE VL 1440
2092 11:15:40.023288 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2093 11:15:40.023400 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2094 11:15:40.023511 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2095 11:15:40.023622 # ok 365 Set SVE VL 1456
2096 11:15:40.023761 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2097 11:15:40.023879 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2098 11:15:40.023993 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2099 11:15:40.024106 # ok 369 Set SVE VL 1472
2100 11:15:40.024217 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2101 11:15:40.024328 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2102 11:15:40.024438 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2103 11:15:40.024549 # ok 373 Set SVE VL 1488
2104 11:15:40.024660 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2105 11:15:40.026921 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2106 11:15:40.027231 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2107 11:15:40.027334 # ok 377 Set SVE VL 1504
2108 11:15:40.027427 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2109 11:15:40.027510 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2110 11:15:40.027588 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2111 11:15:40.027688 # ok 381 Set SVE VL 1520
2112 11:15:40.027801 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2113 11:15:40.027896 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2114 11:15:40.027988 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2115 11:15:40.028094 # ok 385 Set SVE VL 1536
2116 11:15:40.028187 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2117 11:15:40.029373 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2118 11:15:40.029478 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2119 11:15:40.029572 # ok 389 Set SVE VL 1552
2120 11:15:40.029689 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2121 11:15:40.029785 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2122 11:15:40.029877 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2123 11:15:40.029988 # ok 393 Set SVE VL 1568
2124 11:15:40.030080 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2125 11:15:40.030166 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2126 11:15:40.030261 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2127 11:15:40.030339 # ok 397 Set SVE VL 1584
2128 11:15:40.030415 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2129 11:15:40.030491 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2130 11:15:40.030567 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2131 11:15:40.030659 # ok 401 Set SVE VL 1600
2132 11:15:40.030745 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2133 11:15:40.030836 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2134 11:15:40.030918 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2135 11:15:40.031011 # ok 405 Set SVE VL 1616
2136 11:15:40.031095 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2137 11:15:40.031184 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2138 11:15:40.031274 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2139 11:15:40.031365 # ok 409 Set SVE VL 1632
2140 11:15:40.031453 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2141 11:15:40.031556 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2142 11:15:40.031648 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2143 11:15:40.031748 # ok 413 Set SVE VL 1648
2144 11:15:40.031831 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2145 11:15:40.031919 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2146 11:15:40.032381 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2147 11:15:40.032490 # ok 417 Set SVE VL 1664
2148 11:15:40.032580 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2149 11:15:40.032662 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2150 11:15:40.032743 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2151 11:15:40.032824 # ok 421 Set SVE VL 1680
2152 11:15:40.032918 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2153 11:15:40.032997 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2154 11:15:40.033076 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2155 11:15:40.033162 # ok 425 Set SVE VL 1696
2156 11:15:40.033249 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2157 11:15:40.033355 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2158 11:15:40.033446 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2159 11:15:40.033525 # ok 429 Set SVE VL 1712
2160 11:15:40.033600 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2161 11:15:40.033681 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2162 11:15:40.033782 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2163 11:15:40.033862 # ok 433 Set SVE VL 1728
2164 11:15:40.033940 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2165 11:15:40.034026 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2166 11:15:40.034115 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2167 11:15:40.034220 # ok 437 Set SVE VL 1744
2168 11:15:40.034312 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2169 11:15:40.034402 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2170 11:15:40.034489 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2171 11:15:40.034584 # ok 441 Set SVE VL 1760
2172 11:15:40.034664 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2173 11:15:40.034762 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2174 11:15:40.034844 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2175 11:15:40.034919 # ok 445 Set SVE VL 1776
2176 11:15:40.042954 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2177 11:15:40.043159 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2178 11:15:40.043556 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2179 11:15:40.043774 # ok 449 Set SVE VL 1792
2180 11:15:40.043942 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2181 11:15:40.044098 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2182 11:15:40.044216 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2183 11:15:40.044357 # ok 453 Set SVE VL 1808
2184 11:15:40.044476 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2185 11:15:40.044589 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2186 11:15:40.044723 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2187 11:15:40.044873 # ok 457 Set SVE VL 1824
2188 11:15:40.044989 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2189 11:15:40.045141 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2190 11:15:40.045271 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2191 11:15:40.045416 # ok 461 Set SVE VL 1840
2192 11:15:40.045537 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2193 11:15:40.045665 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2194 11:15:40.045828 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2195 11:15:40.045999 # ok 465 Set SVE VL 1856
2196 11:15:40.046158 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2197 11:15:40.046276 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2198 11:15:40.046389 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2199 11:15:40.046502 # ok 469 Set SVE VL 1872
2200 11:15:40.046644 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2201 11:15:40.046812 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2202 11:15:40.046940 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2203 11:15:40.047056 # ok 473 Set SVE VL 1888
2204 11:15:40.047169 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2205 11:15:40.047281 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2206 11:15:40.047394 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2207 11:15:40.047506 # ok 477 Set SVE VL 1904
2208 11:15:40.047618 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2209 11:15:40.047746 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2210 11:15:40.047889 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2211 11:15:40.051148 # ok 481 Set SVE VL 1920
2212 11:15:40.051346 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2213 11:15:40.051541 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2214 11:15:40.051711 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2215 11:15:40.051867 # ok 485 Set SVE VL 1936
2216 11:15:40.052056 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2217 11:15:40.052223 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2218 11:15:40.052385 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2219 11:15:40.052549 # ok 489 Set SVE VL 1952
2220 11:15:40.052711 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2221 11:15:40.052872 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2222 11:15:40.053067 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2223 11:15:40.053235 # ok 493 Set SVE VL 1968
2224 11:15:40.053395 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2225 11:15:40.053556 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2226 11:15:40.053738 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2227 11:15:40.053906 # ok 497 Set SVE VL 1984
2228 11:15:40.054076 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2229 11:15:40.054242 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2230 11:15:40.054405 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2231 11:15:40.054610 # ok 501 Set SVE VL 2000
2232 11:15:40.054774 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2233 11:15:40.054897 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2234 11:15:40.055017 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2235 11:15:40.055144 # ok 505 Set SVE VL 2016
2236 11:15:40.055328 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2237 11:15:40.055486 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2238 11:15:40.055613 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2239 11:15:40.055731 # ok 509 Set SVE VL 2032
2240 11:15:40.055847 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2241 11:15:40.055963 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2242 11:15:40.056082 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2243 11:15:40.056198 # ok 513 Set SVE VL 2048
2244 11:15:40.056313 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2245 11:15:40.056429 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2246 11:15:40.056545 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2247 11:15:40.056662 # ok 517 Set SVE VL 2064
2248 11:15:40.056803 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2249 11:15:40.059635 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2250 11:15:40.060080 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2251 11:15:40.060271 # ok 521 Set SVE VL 2080
2252 11:15:40.060421 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2253 11:15:40.060593 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2254 11:15:40.060810 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2255 11:15:40.060970 # ok 525 Set SVE VL 2096
2256 11:15:40.061115 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2257 11:15:40.061258 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2258 11:15:40.061401 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2259 11:15:40.061544 # ok 529 Set SVE VL 2112
2260 11:15:40.061711 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2261 11:15:40.061897 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2262 11:15:40.062019 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2263 11:15:40.062135 # ok 533 Set SVE VL 2128
2264 11:15:40.062249 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2265 11:15:40.062363 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2266 11:15:40.062476 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2267 11:15:40.062589 # ok 537 Set SVE VL 2144
2268 11:15:40.062709 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2269 11:15:40.062836 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2270 11:15:40.062950 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2271 11:15:40.063062 # ok 541 Set SVE VL 2160
2272 11:15:40.063177 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2273 11:15:40.063289 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2274 11:15:40.063428 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2275 11:15:40.063546 # ok 545 Set SVE VL 2176
2276 11:15:40.063658 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2277 11:15:40.063791 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2278 11:15:40.063907 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2279 11:15:40.064019 # ok 549 Set SVE VL 2192
2280 11:15:40.064134 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2281 11:15:40.064247 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2282 11:15:40.064359 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2283 11:15:40.066917 # ok 553 Set SVE VL 2208
2284 11:15:40.067104 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2285 11:15:40.067478 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2286 11:15:40.067661 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2287 11:15:40.067835 # ok 557 Set SVE VL 2224
2288 11:15:40.067996 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2289 11:15:40.068128 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2290 11:15:40.068275 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2291 11:15:40.068438 # ok 561 Set SVE VL 2240
2292 11:15:40.068599 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2293 11:15:40.068751 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2294 11:15:40.068870 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2295 11:15:40.068983 # ok 565 Set SVE VL 2256
2296 11:15:40.069101 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2297 11:15:40.069214 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2298 11:15:40.069353 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2299 11:15:40.069472 # ok 569 Set SVE VL 2272
2300 11:15:40.069586 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2301 11:15:40.069762 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2302 11:15:40.069959 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2303 11:15:40.070146 # ok 573 Set SVE VL 2288
2304 11:15:40.074778 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2305 11:15:40.074962 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2306 11:15:40.075153 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2307 11:15:40.075306 # ok 577 Set SVE VL 2304
2308 11:15:40.075470 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2309 11:15:40.075633 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2310 11:15:40.075790 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2311 11:15:40.075939 # ok 581 Set SVE VL 2320
2312 11:15:40.076095 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2313 11:15:40.076256 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2314 11:15:40.076448 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2315 11:15:40.076612 # ok 585 Set SVE VL 2336
2316 11:15:40.076766 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2317 11:15:40.076919 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2318 11:15:40.077073 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2319 11:15:40.077227 # ok 589 Set SVE VL 2352
2320 11:15:40.077381 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2321 11:15:40.077523 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2322 11:15:40.077660 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2323 11:15:40.077860 # ok 593 Set SVE VL 2368
2324 11:15:40.078035 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2325 11:15:40.078260 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2326 11:15:40.078441 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2327 11:15:40.078626 # ok 597 Set SVE VL 2384
2328 11:15:40.078809 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2329 11:15:40.078975 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2330 11:15:40.079177 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2331 11:15:40.079353 # ok 601 Set SVE VL 2400
2332 11:15:40.079513 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2333 11:15:40.079671 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2334 11:15:40.079828 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2335 11:15:40.079984 # ok 605 Set SVE VL 2416
2336 11:15:40.080138 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2337 11:15:40.080294 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2338 11:15:40.080450 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2339 11:15:40.080640 # ok 609 Set SVE VL 2432
2340 11:15:40.080808 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2341 11:15:40.080967 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2342 11:15:40.081125 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2343 11:15:40.081347 # ok 613 Set SVE VL 2448
2344 11:15:40.081524 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2345 11:15:40.081696 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2346 11:15:40.081862 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2347 11:15:40.082022 # ok 617 Set SVE VL 2464
2348 11:15:40.082401 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2349 11:15:40.082512 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2350 11:15:40.082596 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2351 11:15:40.082829 # ok 621 Set SVE VL 2480
2352 11:15:40.082919 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2353 11:15:40.083004 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2354 11:15:40.083081 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2355 11:15:40.083162 # ok 625 Set SVE VL 2496
2356 11:15:40.083238 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2357 11:15:40.083316 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2358 11:15:40.083396 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2359 11:15:40.083470 # ok 629 Set SVE VL 2512
2360 11:15:40.083557 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2361 11:15:40.083637 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2362 11:15:40.083720 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2363 11:15:40.083801 # ok 633 Set SVE VL 2528
2364 11:15:40.083877 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2365 11:15:40.083952 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2366 11:15:40.084034 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2367 11:15:40.084118 # ok 637 Set SVE VL 2544
2368 11:15:40.084196 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2369 11:15:40.084272 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2370 11:15:40.084348 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2371 11:15:40.084425 # ok 641 Set SVE VL 2560
2372 11:15:40.084508 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2373 11:15:40.084586 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2374 11:15:40.084663 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2375 11:15:40.084745 # ok 645 Set SVE VL 2576
2376 11:15:40.084823 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2377 11:15:40.084899 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2378 11:15:40.084981 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2379 11:15:40.085062 # ok 649 Set SVE VL 2592
2380 11:15:40.085142 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2381 11:15:40.085217 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2382 11:15:40.085293 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2383 11:15:40.085372 # ok 653 Set SVE VL 2608
2384 11:15:40.085453 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2385 11:15:40.085530 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2386 11:15:40.085605 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2387 11:15:40.085709 # ok 657 Set SVE VL 2624
2388 11:15:40.085795 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2389 11:15:40.085879 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2390 11:15:40.085958 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2391 11:15:40.086034 # ok 661 Set SVE VL 2640
2392 11:15:40.086309 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2393 11:15:40.086395 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2394 11:15:40.086475 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2395 11:15:40.086553 # ok 665 Set SVE VL 2656
2396 11:15:40.086636 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2397 11:15:40.086719 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2398 11:15:40.086804 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2399 11:15:40.086882 # ok 669 Set SVE VL 2672
2400 11:15:40.086959 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2401 11:15:40.087037 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2402 11:15:40.087120 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2403 11:15:40.087202 # ok 673 Set SVE VL 2688
2404 11:15:40.087279 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2405 11:15:40.087356 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2406 11:15:40.087433 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2407 11:15:40.087512 # ok 677 Set SVE VL 2704
2408 11:15:40.087596 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2409 11:15:40.087674 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2410 11:15:40.087757 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2411 11:15:40.087836 # ok 681 Set SVE VL 2720
2412 11:15:40.087912 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2413 11:15:40.087994 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2414 11:15:40.088078 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2415 11:15:40.088161 # ok 685 Set SVE VL 2736
2416 11:15:40.088237 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2417 11:15:40.088314 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2418 11:15:40.088392 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2419 11:15:40.088477 # ok 689 Set SVE VL 2752
2420 11:15:40.088555 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2421 11:15:40.088633 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2422 11:15:40.088711 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2423 11:15:40.088795 # ok 693 Set SVE VL 2768
2424 11:15:40.088872 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2425 11:15:40.088954 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2426 11:15:40.089037 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2427 11:15:40.089114 # ok 697 Set SVE VL 2784
2428 11:15:40.089190 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2429 11:15:40.089268 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2430 11:15:40.089363 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2431 11:15:40.089444 # ok 701 Set SVE VL 2800
2432 11:15:40.089523 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2433 11:15:40.089604 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2434 11:15:40.089696 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2435 11:15:40.089780 # ok 705 Set SVE VL 2816
2436 11:15:40.090063 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2437 11:15:40.090151 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2438 11:15:40.090236 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2439 11:15:40.090320 # ok 709 Set SVE VL 2832
2440 11:15:40.090399 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2441 11:15:40.090476 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2442 11:15:40.090554 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2443 11:15:40.090630 # ok 713 Set SVE VL 2848
2444 11:15:40.090710 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2445 11:15:40.090796 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2446 11:15:40.090884 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2447 11:15:40.090974 # ok 717 Set SVE VL 2864
2448 11:15:40.091064 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2449 11:15:40.091149 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2450 11:15:40.091236 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2451 11:15:40.091314 # ok 721 Set SVE VL 2880
2452 11:15:40.091391 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2453 11:15:40.091470 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2454 11:15:40.091556 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2455 11:15:40.091635 # ok 725 Set SVE VL 2896
2456 11:15:40.091714 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2457 11:15:40.091800 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2458 11:15:40.091879 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2459 11:15:40.091957 # ok 729 Set SVE VL 2912
2460 11:15:40.092045 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2461 11:15:40.092125 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2462 11:15:40.092203 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2463 11:15:40.092280 # ok 733 Set SVE VL 2928
2464 11:15:40.092358 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2465 11:15:40.092442 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2466 11:15:40.092523 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2467 11:15:40.092601 # ok 737 Set SVE VL 2944
2468 11:15:40.092679 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2469 11:15:40.092765 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2470 11:15:40.092866 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2471 11:15:40.092958 # ok 741 Set SVE VL 2960
2472 11:15:40.093038 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2473 11:15:40.093116 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2474 11:15:40.093194 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2475 11:15:40.093272 # ok 745 Set SVE VL 2976
2476 11:15:40.093356 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2477 11:15:40.093437 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2478 11:15:40.093515 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2479 11:15:40.093790 # ok 749 Set SVE VL 2992
2480 11:15:40.093885 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2481 11:15:40.093965 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2482 11:15:40.094044 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2483 11:15:40.094122 # ok 753 Set SVE VL 3008
2484 11:15:40.094206 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2485 11:15:40.094287 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2486 11:15:40.094367 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2487 11:15:40.094444 # ok 757 Set SVE VL 3024
2488 11:15:40.094521 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2489 11:15:40.094598 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2490 11:15:40.094683 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2491 11:15:40.098307 # ok 761 Set SVE VL 3040
2492 11:15:40.098406 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2493 11:15:40.098493 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2494 11:15:40.098589 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2495 11:15:40.098669 # ok 765 Set SVE VL 3056
2496 11:15:40.098766 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2497 11:15:40.099043 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2498 11:15:40.099129 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2499 11:15:40.099212 # ok 769 Set SVE VL 3072
2500 11:15:40.099311 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2501 11:15:40.099392 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2502 11:15:40.099470 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2503 11:15:40.099563 # ok 773 Set SVE VL 3088
2504 11:15:40.099648 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2505 11:15:40.099749 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2506 11:15:40.099832 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2507 11:15:40.099910 # ok 777 Set SVE VL 3104
2508 11:15:40.100003 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2509 11:15:40.100084 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2510 11:15:40.100171 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2511 11:15:40.100266 # ok 781 Set SVE VL 3120
2512 11:15:40.100346 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2513 11:15:40.100438 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2514 11:15:40.100522 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2515 11:15:40.100608 # ok 785 Set SVE VL 3136
2516 11:15:40.100702 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2517 11:15:40.100787 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2518 11:15:40.100879 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2519 11:15:40.100963 # ok 789 Set SVE VL 3152
2520 11:15:40.101061 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2521 11:15:40.101142 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2522 11:15:40.101241 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2523 11:15:40.101322 # ok 793 Set SVE VL 3168
2524 11:15:40.101421 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2525 11:15:40.101505 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2526 11:15:40.101596 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2527 11:15:40.101684 # ok 797 Set SVE VL 3184
2528 11:15:40.101769 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2529 11:15:40.101870 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2530 11:15:40.101954 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2531 11:15:40.102047 # ok 801 Set SVE VL 3200
2532 11:15:40.102127 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2533 11:15:40.102206 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2534 11:15:40.102306 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2535 11:15:40.102390 # ok 805 Set SVE VL 3216
2536 11:15:40.102469 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2537 11:15:40.102559 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2538 11:15:40.102656 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2539 11:15:40.102746 # ok 809 Set SVE VL 3232
2540 11:15:40.102827 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2541 11:15:40.103103 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2542 11:15:40.103191 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2543 11:15:40.103285 # ok 813 Set SVE VL 3248
2544 11:15:40.103365 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2545 11:15:40.103445 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2546 11:15:40.103530 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2547 11:15:40.103628 # ok 817 Set SVE VL 3264
2548 11:15:40.103710 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2549 11:15:40.103792 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2550 11:15:40.103871 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2551 11:15:40.103972 # ok 821 Set SVE VL 3280
2552 11:15:40.104057 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2553 11:15:40.104136 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2554 11:15:40.104216 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2555 11:15:40.104310 # ok 825 Set SVE VL 3296
2556 11:15:40.104389 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2557 11:15:40.104470 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2558 11:15:40.104554 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2559 11:15:40.104647 # ok 829 Set SVE VL 3312
2560 11:15:40.104730 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2561 11:15:40.104810 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2562 11:15:40.104902 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2563 11:15:40.104981 # ok 833 Set SVE VL 3328
2564 11:15:40.105060 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2565 11:15:40.105151 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2566 11:15:40.105232 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2567 11:15:40.105319 # ok 837 Set SVE VL 3344
2568 11:15:40.105413 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2569 11:15:40.105492 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2570 11:15:40.105569 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2571 11:15:40.105651 # ok 841 Set SVE VL 3360
2572 11:15:40.105749 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2573 11:15:40.105832 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2574 11:15:40.105911 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2575 11:15:40.106003 # ok 845 Set SVE VL 3376
2576 11:15:40.106090 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2577 11:15:40.106170 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2578 11:15:40.106262 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2579 11:15:40.106342 # ok 849 Set SVE VL 3392
2580 11:15:40.106419 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2581 11:15:40.106509 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2582 11:15:40.106589 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2583 11:15:40.106680 # ok 853 Set SVE VL 3408
2584 11:15:40.106764 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2585 11:15:40.107084 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2586 11:15:40.107272 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2587 11:15:40.107437 # ok 857 Set SVE VL 3424
2588 11:15:40.107579 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2589 11:15:40.107729 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2590 11:15:40.107856 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2591 11:15:40.108004 # ok 861 Set SVE VL 3440
2592 11:15:40.108147 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2593 11:15:40.108302 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2594 11:15:40.108459 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2595 11:15:40.108612 # ok 865 Set SVE VL 3456
2596 11:15:40.108776 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2597 11:15:40.108910 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2598 11:15:40.109056 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2599 11:15:40.109192 # ok 869 Set SVE VL 3472
2600 11:15:40.109319 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2601 11:15:40.109442 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2602 11:15:40.109577 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2603 11:15:40.109731 # ok 873 Set SVE VL 3488
2604 11:15:40.109864 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2605 11:15:40.110027 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2606 11:15:40.110178 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2607 11:15:40.110330 # ok 877 Set SVE VL 3504
2608 11:15:40.110488 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2609 11:15:40.110660 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2610 11:15:40.110851 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2611 11:15:40.111017 # ok 881 Set SVE VL 3520
2612 11:15:40.111163 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2613 11:15:40.111305 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2614 11:15:40.111439 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2615 11:15:40.111578 # ok 885 Set SVE VL 3536
2616 11:15:40.111760 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2617 11:15:40.111905 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2618 11:15:40.112040 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2619 11:15:40.112182 # ok 889 Set SVE VL 3552
2620 11:15:40.112321 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2621 11:15:40.112442 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2622 11:15:40.112557 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2623 11:15:40.112674 # ok 893 Set SVE VL 3568
2624 11:15:40.112796 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2625 11:15:40.112918 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2626 11:15:40.113039 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2627 11:15:40.113184 # ok 897 Set SVE VL 3584
2628 11:15:40.113349 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2629 11:15:40.113746 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2630 11:15:40.113928 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2631 11:15:40.114091 # ok 901 Set SVE VL 3600
2632 11:15:40.114247 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2633 11:15:40.114374 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2634 11:15:40.114498 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2635 11:15:40.114618 # ok 905 Set SVE VL 3616
2636 11:15:40.114767 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2637 11:15:40.114917 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2638 11:15:40.115075 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2639 11:15:40.115265 # ok 909 Set SVE VL 3632
2640 11:15:40.115469 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2641 11:15:40.115671 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2642 11:15:40.115815 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2643 11:15:40.115983 # ok 913 Set SVE VL 3648
2644 11:15:40.116160 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2645 11:15:40.116356 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2646 11:15:40.116568 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2647 11:15:40.116709 # ok 917 Set SVE VL 3664
2648 11:15:40.116818 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2649 11:15:40.116908 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2650 11:15:40.116997 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2651 11:15:40.117087 # ok 921 Set SVE VL 3680
2652 11:15:40.117178 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2653 11:15:40.117274 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2654 11:15:40.117378 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2655 11:15:40.117489 # ok 925 Set SVE VL 3696
2656 11:15:40.117579 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2657 11:15:40.117674 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2658 11:15:40.117760 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2659 11:15:40.117847 # ok 929 Set SVE VL 3712
2660 11:15:40.117931 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2661 11:15:40.118015 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2662 11:15:40.118102 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2663 11:15:40.118191 # ok 933 Set SVE VL 3728
2664 11:15:40.118276 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2665 11:15:40.118361 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2666 11:15:40.118445 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2667 11:15:40.118529 # ok 937 Set SVE VL 3744
2668 11:15:40.118631 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2669 11:15:40.118764 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2670 11:15:40.118861 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2671 11:15:40.118948 # ok 941 Set SVE VL 3760
2672 11:15:40.119236 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2673 11:15:40.119330 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2674 11:15:40.119418 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2675 11:15:40.119504 # ok 945 Set SVE VL 3776
2676 11:15:40.119589 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2677 11:15:40.119674 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2678 11:15:40.121916 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2679 11:15:40.122058 # ok 949 Set SVE VL 3792
2680 11:15:40.122382 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2681 11:15:40.122482 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2682 11:15:40.122582 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2683 11:15:40.122728 # ok 953 Set SVE VL 3808
2684 11:15:40.122815 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2685 11:15:40.122957 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2686 11:15:40.123065 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2687 11:15:40.123383 # ok 957 Set SVE VL 3824
2688 11:15:40.123482 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2689 11:15:40.123562 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2690 11:15:40.123639 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2691 11:15:40.123764 # ok 961 Set SVE VL 3840
2692 11:15:40.123880 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2693 11:15:40.123973 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2694 11:15:40.124054 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2695 11:15:40.124135 # ok 965 Set SVE VL 3856
2696 11:15:40.124210 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2697 11:15:40.124286 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2698 11:15:40.124383 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2699 11:15:40.124466 # ok 969 Set SVE VL 3872
2700 11:15:40.124542 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2701 11:15:40.124618 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2702 11:15:40.124708 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2703 11:15:40.124796 # ok 973 Set SVE VL 3888
2704 11:15:40.124882 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2705 11:15:40.124977 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2706 11:15:40.125056 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2707 11:15:40.125144 # ok 977 Set SVE VL 3904
2708 11:15:40.125236 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2709 11:15:40.125603 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2710 11:15:40.125705 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2711 11:15:40.125795 # ok 981 Set SVE VL 3920
2712 11:15:40.126114 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2713 11:15:40.126252 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2714 11:15:40.126342 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2715 11:15:40.126420 # ok 985 Set SVE VL 3936
2716 11:15:40.126513 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2717 11:15:40.126599 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2718 11:15:40.126680 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2719 11:15:40.126764 # ok 989 Set SVE VL 3952
2720 11:15:40.126859 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2721 11:15:40.126950 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2722 11:15:40.127029 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2723 11:15:40.127128 # ok 993 Set SVE VL 3968
2724 11:15:40.127221 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2725 11:15:40.127519 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2726 11:15:40.127691 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2727 11:15:40.127793 # ok 997 Set SVE VL 3984
2728 11:15:40.127874 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2729 11:15:40.127971 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2730 11:15:40.128053 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2731 11:15:40.128145 # ok 1001 Set SVE VL 4000
2732 11:15:40.128235 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2733 11:15:40.128328 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2734 11:15:40.128425 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2735 11:15:40.128517 # ok 1005 Set SVE VL 4016
2736 11:15:40.128606 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2737 11:15:40.128893 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2738 11:15:40.129005 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2739 11:15:40.129115 # ok 1009 Set SVE VL 4032
2740 11:15:40.129245 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2741 11:15:40.129384 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2742 11:15:40.129513 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2743 11:15:40.129656 # ok 1013 Set SVE VL 4048
2744 11:15:40.129776 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2745 11:15:40.129880 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2746 11:15:40.130158 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2747 11:15:40.130247 # ok 1017 Set SVE VL 4064
2748 11:15:40.130320 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2749 11:15:40.130606 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2750 11:15:40.130690 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2751 11:15:40.130778 # ok 1021 Set SVE VL 4080
2752 11:15:40.130852 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2753 11:15:40.130927 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2754 11:15:40.130989 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2755 11:15:40.131076 # ok 1025 Set SVE VL 4096
2756 11:15:40.131159 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2757 11:15:40.131428 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2758 11:15:40.131541 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2759 11:15:40.131648 # ok 1029 Set SVE VL 4112
2760 11:15:40.131771 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2761 11:15:40.131864 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2762 11:15:40.131950 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2763 11:15:40.132014 # ok 1033 Set SVE VL 4128
2764 11:15:40.132092 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2765 11:15:40.132162 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2766 11:15:40.132444 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2767 11:15:40.132541 # ok 1037 Set SVE VL 4144
2768 11:15:40.132629 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2769 11:15:40.132731 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2770 11:15:40.132812 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2771 11:15:40.132886 # ok 1041 Set SVE VL 4160
2772 11:15:40.132968 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2773 11:15:40.133053 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2774 11:15:40.133141 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2775 11:15:40.133222 # ok 1045 Set SVE VL 4176
2776 11:15:40.133496 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2777 11:15:40.133582 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2778 11:15:40.133675 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2779 11:15:40.133768 # ok 1049 Set SVE VL 4192
2780 11:15:40.134044 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2781 11:15:40.134149 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2782 11:15:40.134227 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2783 11:15:40.134329 # ok 1053 Set SVE VL 4208
2784 11:15:40.134421 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2785 11:15:40.134521 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2786 11:15:40.134617 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2787 11:15:40.134717 # ok 1057 Set SVE VL 4224
2788 11:15:40.135006 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2789 11:15:40.135105 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2790 11:15:40.135203 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2791 11:15:40.135307 # ok 1061 Set SVE VL 4240
2792 11:15:40.135410 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2793 11:15:40.135500 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2794 11:15:40.135597 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2795 11:15:40.135679 # ok 1065 Set SVE VL 4256
2796 11:15:40.135782 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2797 11:15:40.135905 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2798 11:15:40.136213 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2799 11:15:40.136329 # ok 1069 Set SVE VL 4272
2800 11:15:40.136403 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2801 11:15:40.136484 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2802 11:15:40.136556 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2803 11:15:40.136640 # ok 1073 Set SVE VL 4288
2804 11:15:40.136711 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2805 11:15:40.136798 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2806 11:15:40.136868 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2807 11:15:40.136961 # ok 1077 Set SVE VL 4304
2808 11:15:40.137047 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2809 11:15:40.137121 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2810 11:15:40.137197 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2811 11:15:40.137280 # ok 1081 Set SVE VL 4320
2812 11:15:40.137372 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2813 11:15:40.137452 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2814 11:15:40.137546 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2815 11:15:40.137628 # ok 1085 Set SVE VL 4336
2816 11:15:40.137724 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2817 11:15:40.138027 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2818 11:15:40.138116 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2819 11:15:40.138205 # ok 1089 Set SVE VL 4352
2820 11:15:40.138511 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2821 11:15:40.138593 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2822 11:15:40.138656 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2823 11:15:40.138941 # ok 1093 Set SVE VL 4368
2824 11:15:40.139037 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2825 11:15:40.139119 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2826 11:15:40.139210 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2827 11:15:40.139292 # ok 1097 Set SVE VL 4384
2828 11:15:40.139555 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2829 11:15:40.139665 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2830 11:15:40.139773 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2831 11:15:40.139878 # ok 1101 Set SVE VL 4400
2832 11:15:40.139986 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2833 11:15:40.140080 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2834 11:15:40.140163 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2835 11:15:40.140275 # ok 1105 Set SVE VL 4416
2836 11:15:40.140365 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2837 11:15:40.140458 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2838 11:15:40.140565 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2839 11:15:40.140669 # ok 1109 Set SVE VL 4432
2840 11:15:40.140778 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2841 11:15:40.140863 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2842 11:15:40.140956 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2843 11:15:40.141037 # ok 1113 Set SVE VL 4448
2844 11:15:40.141115 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2845 11:15:40.141209 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2846 11:15:40.141482 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2847 11:15:40.141595 # ok 1117 Set SVE VL 4464
2848 11:15:40.141708 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2849 11:15:40.141814 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2850 11:15:40.141920 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2851 11:15:40.142018 # ok 1121 Set SVE VL 4480
2852 11:15:40.142130 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2853 11:15:40.142236 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2854 11:15:40.142356 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2855 11:15:40.142432 # ok 1125 Set SVE VL 4496
2856 11:15:40.142494 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2857 11:15:40.142554 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2858 11:15:40.142635 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2859 11:15:40.142709 # ok 1129 Set SVE VL 4512
2860 11:15:40.142771 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2861 11:15:40.142830 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2862 11:15:40.146658 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2863 11:15:40.146768 # ok 1133 Set SVE VL 4528
2864 11:15:40.147059 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2865 11:15:40.147167 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2866 11:15:40.147253 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2867 11:15:40.147351 # ok 1137 Set SVE VL 4544
2868 11:15:40.147637 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2869 11:15:40.147730 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2870 11:15:40.147828 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2871 11:15:40.147913 # ok 1141 Set SVE VL 4560
2872 11:15:40.148012 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2873 11:15:40.148292 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2874 11:15:40.148402 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2875 11:15:40.148493 # ok 1145 Set SVE VL 4576
2876 11:15:40.148594 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2877 11:15:40.148693 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2878 11:15:40.148794 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2879 11:15:40.148894 # ok 1149 Set SVE VL 4592
2880 11:15:40.148995 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2881 11:15:40.149318 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2882 11:15:40.149425 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2883 11:15:40.149528 # ok 1153 Set SVE VL 4608
2884 11:15:40.149616 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2885 11:15:40.149935 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2886 11:15:40.150050 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2887 11:15:40.150148 # ok 1157 Set SVE VL 4624
2888 11:15:40.150218 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2889 11:15:40.150522 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2890 11:15:40.150611 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2891 11:15:40.150694 # ok 1161 Set SVE VL 4640
2892 11:15:40.150801 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2893 11:15:40.150881 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2894 11:15:40.151149 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2895 11:15:40.151254 # ok 1165 Set SVE VL 4656
2896 11:15:40.151382 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2897 11:15:40.151527 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2898 11:15:40.151648 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2899 11:15:40.151776 # ok 1169 Set SVE VL 4672
2900 11:15:40.151915 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2901 11:15:40.152036 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2902 11:15:40.152157 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2903 11:15:40.152280 # ok 1173 Set SVE VL 4688
2904 11:15:40.152388 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2905 11:15:40.152472 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2906 11:15:40.152554 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2907 11:15:40.152633 # ok 1177 Set SVE VL 4704
2908 11:15:40.152721 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2909 11:15:40.152810 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2910 11:15:40.152919 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2911 11:15:40.153029 # ok 1181 Set SVE VL 4720
2912 11:15:40.153152 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2913 11:15:40.153260 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2914 11:15:40.153348 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2915 11:15:40.153428 # ok 1185 Set SVE VL 4736
2916 11:15:40.153530 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2917 11:15:40.153615 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2918 11:15:40.153709 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2919 11:15:40.153794 # ok 1189 Set SVE VL 4752
2920 11:15:40.154092 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2921 11:15:40.154183 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2922 11:15:40.154272 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2923 11:15:40.154353 # ok 1193 Set SVE VL 4768
2924 11:15:40.154432 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2925 11:15:40.154526 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2926 11:15:40.154616 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2927 11:15:40.154701 # ok 1197 Set SVE VL 4784
2928 11:15:40.154785 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2929 11:15:40.154888 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2930 11:15:40.154977 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2931 11:15:40.155064 # ok 1201 Set SVE VL 4800
2932 11:15:40.155161 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2933 11:15:40.155247 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2934 11:15:40.155339 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2935 11:15:40.155422 # ok 1205 Set SVE VL 4816
2936 11:15:40.155522 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2937 11:15:40.155608 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2938 11:15:40.155690 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2939 11:15:40.155773 # ok 1209 Set SVE VL 4832
2940 11:15:40.155871 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2941 11:15:40.155957 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2942 11:15:40.156042 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2943 11:15:40.156125 # ok 1213 Set SVE VL 4848
2944 11:15:40.156223 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2945 11:15:40.156308 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2946 11:15:40.156392 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2947 11:15:40.156474 # ok 1217 Set SVE VL 4864
2948 11:15:40.156558 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2949 11:15:40.156658 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2950 11:15:40.156745 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2951 11:15:40.156829 # ok 1221 Set SVE VL 4880
2952 11:15:40.156913 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2953 11:15:40.156996 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2954 11:15:40.157094 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2955 11:15:40.157183 # ok 1225 Set SVE VL 4896
2956 11:15:40.157267 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2957 11:15:40.157351 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2958 11:15:40.157435 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2959 11:15:40.157534 # ok 1229 Set SVE VL 4912
2960 11:15:40.157619 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2961 11:15:40.157714 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2962 11:15:40.157798 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2963 11:15:40.158083 # ok 1233 Set SVE VL 4928
2964 11:15:40.158186 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2965 11:15:40.158304 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2966 11:15:40.158417 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2967 11:15:40.158517 # ok 1237 Set SVE VL 4944
2968 11:15:40.158615 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2969 11:15:40.158709 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2970 11:15:40.158804 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2971 11:15:40.158887 # ok 1241 Set SVE VL 4960
2972 11:15:40.158985 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2973 11:15:40.159073 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2974 11:15:40.159161 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2975 11:15:40.159236 # ok 1245 Set SVE VL 4976
2976 11:15:40.159313 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2977 11:15:40.159413 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2978 11:15:40.159497 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2979 11:15:40.159581 # ok 1249 Set SVE VL 4992
2980 11:15:40.159684 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2981 11:15:40.159795 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2982 11:15:40.159890 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2983 11:15:40.159979 # ok 1253 Set SVE VL 5008
2984 11:15:40.160064 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2985 11:15:40.160174 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2986 11:15:40.160265 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2987 11:15:40.160353 # ok 1257 Set SVE VL 5024
2988 11:15:40.160438 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2989 11:15:40.160524 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2990 11:15:40.160612 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2991 11:15:40.160703 # ok 1261 Set SVE VL 5040
2992 11:15:40.160829 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2993 11:15:40.160935 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2994 11:15:40.161033 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2995 11:15:40.161123 # ok 1265 Set SVE VL 5056
2996 11:15:40.161204 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2997 11:15:40.161308 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2998 11:15:40.161395 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2999 11:15:40.161480 # ok 1269 Set SVE VL 5072
3000 11:15:40.161565 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
3001 11:15:40.161671 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
3002 11:15:40.161759 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3003 11:15:40.161844 # ok 1273 Set SVE VL 5088
3004 11:15:40.161941 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3005 11:15:40.162028 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3006 11:15:40.162312 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3007 11:15:40.162414 # ok 1277 Set SVE VL 5104
3008 11:15:40.162501 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3009 11:15:40.162597 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3010 11:15:40.162698 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3011 11:15:40.162784 # ok 1281 Set SVE VL 5120
3012 11:15:40.163929 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3013 11:15:40.164028 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3014 11:15:40.164107 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3015 11:15:40.164184 # ok 1285 Set SVE VL 5136
3016 11:15:40.164261 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3017 11:15:40.164352 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3018 11:15:40.164431 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3019 11:15:40.164509 # ok 1289 Set SVE VL 5152
3020 11:15:40.164584 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3021 11:15:40.164660 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3022 11:15:40.164763 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3023 11:15:40.164849 # ok 1293 Set SVE VL 5168
3024 11:15:40.164926 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3025 11:15:40.165002 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3026 11:15:40.165077 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3027 11:15:40.165156 # ok 1297 Set SVE VL 5184
3028 11:15:40.165238 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3029 11:15:40.165318 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3030 11:15:40.165393 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3031 11:15:40.165468 # ok 1301 Set SVE VL 5200
3032 11:15:40.165544 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3033 11:15:40.165643 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3034 11:15:40.165730 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3035 11:15:40.165810 # ok 1305 Set SVE VL 5216
3036 11:15:40.165895 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3037 11:15:40.165973 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3038 11:15:40.166049 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3039 11:15:40.166124 # ok 1309 Set SVE VL 5232
3040 11:15:40.166199 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3041 11:15:40.166304 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3042 11:15:40.166385 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3043 11:15:40.166461 # ok 1313 Set SVE VL 5248
3044 11:15:40.166536 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3045 11:15:40.181889 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3046 11:15:40.182135 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3047 11:15:40.182437 # ok 1317 Set SVE VL 5264
3048 11:15:40.182538 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3049 11:15:40.182632 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3050 11:15:40.182717 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3051 11:15:40.182800 # ok 1321 Set SVE VL 5280
3052 11:15:40.182899 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3053 11:15:40.182985 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3054 11:15:40.183911 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3055 11:15:40.184031 # ok 1325 Set SVE VL 5296
3056 11:15:40.184118 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3057 11:15:40.184413 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3058 11:15:40.184515 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3059 11:15:40.184616 # ok 1329 Set SVE VL 5312
3060 11:15:40.184734 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3061 11:15:40.184848 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3062 11:15:40.185137 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3063 11:15:40.185235 # ok 1333 Set SVE VL 5328
3064 11:15:40.185322 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3065 11:15:40.185425 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3066 11:15:40.185514 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3067 11:15:40.185612 # ok 1337 Set SVE VL 5344
3068 11:15:40.185720 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3069 11:15:40.185822 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3070 11:15:40.186120 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3071 11:15:40.186214 # ok 1341 Set SVE VL 5360
3072 11:15:40.186511 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3073 11:15:40.186614 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3074 11:15:40.186700 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3075 11:15:40.186801 # ok 1345 Set SVE VL 5376
3076 11:15:40.186888 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3077 11:15:40.187528 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3078 11:15:40.187838 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3079 11:15:40.187957 # ok 1349 Set SVE VL 5392
3080 11:15:40.188050 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3081 11:15:40.188129 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3082 11:15:40.188412 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3083 11:15:40.188510 # ok 1353 Set SVE VL 5408
3084 11:15:40.188589 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3085 11:15:40.188916 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3086 11:15:40.189111 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3087 11:15:40.189283 # ok 1357 Set SVE VL 5424
3088 11:15:40.189450 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3089 11:15:40.189614 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3090 11:15:40.190054 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3091 11:15:40.190210 # ok 1361 Set SVE VL 5440
3092 11:15:40.190330 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3093 11:15:40.190447 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3094 11:15:40.190561 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3095 11:15:40.190684 # ok 1365 Set SVE VL 5456
3096 11:15:40.190851 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3097 11:15:40.190973 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3098 11:15:40.191089 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3099 11:15:40.191468 # ok 1369 Set SVE VL 5472
3100 11:15:40.191565 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3101 11:15:40.191644 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3102 11:15:40.191724 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3103 11:15:40.191811 # ok 1373 Set SVE VL 5488
3104 11:15:40.191890 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3105 11:15:40.191965 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3106 11:15:40.192040 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3107 11:15:40.192115 # ok 1377 Set SVE VL 5504
3108 11:15:40.192190 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3109 11:15:40.192272 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3110 11:15:40.192551 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3111 11:15:40.192651 # ok 1381 Set SVE VL 5520
3112 11:15:40.192737 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3113 11:15:40.192820 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3114 11:15:40.192899 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3115 11:15:40.192976 # ok 1385 Set SVE VL 5536
3116 11:15:40.193051 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3117 11:15:40.193128 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3118 11:15:40.193211 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3119 11:15:40.193291 # ok 1389 Set SVE VL 5552
3120 11:15:40.193369 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3121 11:15:40.193448 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3122 11:15:40.193523 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3123 11:15:40.193619 # ok 1393 Set SVE VL 5568
3124 11:15:40.193714 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3125 11:15:40.193801 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3126 11:15:40.193878 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3127 11:15:40.193957 # ok 1397 Set SVE VL 5584
3128 11:15:40.194032 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3129 11:15:40.194108 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3130 11:15:40.194188 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3131 11:15:40.194271 # ok 1401 Set SVE VL 5600
3132 11:15:40.194350 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3133 11:15:40.194429 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3134 11:15:40.194522 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3135 11:15:40.194605 # ok 1405 Set SVE VL 5616
3136 11:15:40.194682 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3137 11:15:40.194769 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3138 11:15:40.194851 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3139 11:15:40.194928 # ok 1409 Set SVE VL 5632
3140 11:15:40.195003 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3141 11:15:40.195095 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3142 11:15:40.195174 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3143 11:15:40.195258 # ok 1413 Set SVE VL 5648
3144 11:15:40.195336 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3145 11:15:40.195419 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3146 11:15:40.195508 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3147 11:15:40.195587 # ok 1417 Set SVE VL 5664
3148 11:15:40.195665 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3149 11:15:40.195781 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3150 11:15:40.195886 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3151 11:15:40.195966 # ok 1421 Set SVE VL 5680
3152 11:15:40.196055 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3153 11:15:40.196331 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3154 11:15:40.196431 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3155 11:15:40.196527 # ok 1425 Set SVE VL 5696
3156 11:15:40.196605 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3157 11:15:40.196896 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3158 11:15:40.196992 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3159 11:15:40.197070 # ok 1429 Set SVE VL 5712
3160 11:15:40.197168 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3161 11:15:40.197249 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3162 11:15:40.197337 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3163 11:15:40.219059 # ok 1433 Set SVE VL 5728
3164 11:15:40.219205 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3165 11:15:40.219285 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3166 11:15:40.219355 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3167 11:15:40.219419 # ok 1437 Set SVE VL 5744
3168 11:15:40.219479 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3169 11:15:40.219538 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3170 11:15:40.219596 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3171 11:15:40.219656 # ok 1441 Set SVE VL 5760
3172 11:15:40.219724 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3173 11:15:40.219819 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3174 11:15:40.219901 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3175 11:15:40.219969 # ok 1445 Set SVE VL 5776
3176 11:15:40.220050 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3177 11:15:40.220136 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3178 11:15:40.220213 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3179 11:15:40.220299 # ok 1449 Set SVE VL 5792
3180 11:15:40.220390 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3181 11:15:40.220473 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3182 11:15:40.220557 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3183 11:15:40.220640 # ok 1453 Set SVE VL 5808
3184 11:15:40.220724 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3185 11:15:40.220809 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3186 11:15:40.220894 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3187 11:15:40.220973 # ok 1457 Set SVE VL 5824
3188 11:15:40.221053 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3189 11:15:40.221132 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3190 11:15:40.221213 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3191 11:15:40.221298 # ok 1461 Set SVE VL 5840
3192 11:15:40.221386 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3193 11:15:40.221475 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3194 11:15:40.221560 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3195 11:15:40.221653 # ok 1465 Set SVE VL 5856
3196 11:15:40.221738 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3197 11:15:40.221823 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3198 11:15:40.221907 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3199 11:15:40.221987 # ok 1469 Set SVE VL 5872
3200 11:15:40.222303 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3201 11:15:40.222391 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3202 11:15:40.222452 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3203 11:15:40.222519 # ok 1473 Set SVE VL 5888
3204 11:15:40.222637 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3205 11:15:40.222713 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3206 11:15:40.222778 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3207 11:15:40.222848 # ok 1477 Set SVE VL 5904
3208 11:15:40.222919 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3209 11:15:40.222987 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3210 11:15:40.223046 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3211 11:15:40.223104 # ok 1481 Set SVE VL 5920
3212 11:15:40.223161 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3213 11:15:40.223219 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3214 11:15:40.223276 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3215 11:15:40.223334 # ok 1485 Set SVE VL 5936
3216 11:15:40.223391 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3217 11:15:40.223449 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3218 11:15:40.223506 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3219 11:15:40.223564 # ok 1489 Set SVE VL 5952
3220 11:15:40.223622 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3221 11:15:40.223679 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3222 11:15:40.223737 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3223 11:15:40.223795 # ok 1493 Set SVE VL 5968
3224 11:15:40.223853 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3225 11:15:40.223911 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3226 11:15:40.223968 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3227 11:15:40.224026 # ok 1497 Set SVE VL 5984
3228 11:15:40.224084 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3229 11:15:40.224142 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3230 11:15:40.224199 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3231 11:15:40.224256 # ok 1501 Set SVE VL 6000
3232 11:15:40.224314 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3233 11:15:40.224373 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3234 11:15:40.224433 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3235 11:15:40.224491 # ok 1505 Set SVE VL 6016
3236 11:15:40.224549 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3237 11:15:40.224606 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3238 11:15:40.224664 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3239 11:15:40.224722 # ok 1509 Set SVE VL 6032
3240 11:15:40.224779 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3241 11:15:40.224836 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3242 11:15:40.224893 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3243 11:15:40.225163 # ok 1513 Set SVE VL 6048
3244 11:15:40.225245 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3245 11:15:40.225307 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3246 11:15:40.225367 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3247 11:15:40.225427 # ok 1517 Set SVE VL 6064
3248 11:15:40.225486 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3249 11:15:40.225545 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3250 11:15:40.225604 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3251 11:15:40.225674 # ok 1521 Set SVE VL 6080
3252 11:15:40.225736 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3253 11:15:40.225795 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3254 11:15:40.225853 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3255 11:15:40.225913 # ok 1525 Set SVE VL 6096
3256 11:15:40.225972 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3257 11:15:40.226030 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3258 11:15:40.226089 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3259 11:15:40.226148 # ok 1529 Set SVE VL 6112
3260 11:15:40.226206 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3261 11:15:40.226265 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3262 11:15:40.226324 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3263 11:15:40.226409 # ok 1533 Set SVE VL 6128
3264 11:15:40.226504 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3265 11:15:40.226596 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3266 11:15:40.226716 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3267 11:15:40.226798 # ok 1537 Set SVE VL 6144
3268 11:15:40.226859 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3269 11:15:40.226927 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3270 11:15:40.227031 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3271 11:15:40.227139 # ok 1541 Set SVE VL 6160
3272 11:15:40.227234 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3273 11:15:40.227334 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3274 11:15:40.227473 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3275 11:15:40.227605 # ok 1545 Set SVE VL 6176
3276 11:15:40.227725 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3277 11:15:40.227838 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3278 11:15:40.227929 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3279 11:15:40.228049 # ok 1549 Set SVE VL 6192
3280 11:15:40.228156 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3281 11:15:40.228271 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3282 11:15:40.228362 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3283 11:15:40.228445 # ok 1553 Set SVE VL 6208
3284 11:15:40.228528 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3285 11:15:40.228609 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3286 11:15:40.229185 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3287 11:15:40.229285 # ok 1557 Set SVE VL 6224
3288 11:15:40.229383 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3289 11:15:40.229468 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3290 11:15:40.229541 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3291 11:15:40.229617 # ok 1561 Set SVE VL 6240
3292 11:15:40.229716 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3293 11:15:40.229826 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3294 11:15:40.229931 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3295 11:15:40.230029 # ok 1565 Set SVE VL 6256
3296 11:15:40.230124 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3297 11:15:40.230222 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3298 11:15:40.230316 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3299 11:15:40.230406 # ok 1569 Set SVE VL 6272
3300 11:15:40.230488 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3301 11:15:40.230569 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3302 11:15:40.230704 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3303 11:15:40.230802 # ok 1573 Set SVE VL 6288
3304 11:15:40.230900 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3305 11:15:40.230984 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3306 11:15:40.231068 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3307 11:15:40.231154 # ok 1577 Set SVE VL 6304
3308 11:15:40.231238 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3309 11:15:40.231323 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3310 11:15:40.231412 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3311 11:15:40.231497 # ok 1581 Set SVE VL 6320
3312 11:15:40.231581 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3313 11:15:40.231666 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3314 11:15:40.231753 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3315 11:15:40.231840 # ok 1585 Set SVE VL 6336
3316 11:15:40.231926 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3317 11:15:40.232007 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3318 11:15:40.232086 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3319 11:15:40.232156 # ok 1589 Set SVE VL 6352
3320 11:15:40.232232 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3321 11:15:40.232305 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3322 11:15:40.232375 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3323 11:15:40.232455 # ok 1593 Set SVE VL 6368
3324 11:15:40.232536 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3325 11:15:40.232616 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3326 11:15:40.232701 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3327 11:15:40.232781 # ok 1597 Set SVE VL 6384
3328 11:15:40.232862 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3329 11:15:40.233158 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3330 11:15:40.233264 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3331 11:15:40.233353 # ok 1601 Set SVE VL 6400
3332 11:15:40.233439 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3333 11:15:40.233526 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3334 11:15:40.233613 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3335 11:15:40.233829 # ok 1605 Set SVE VL 6416
3336 11:15:40.233928 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3337 11:15:40.234015 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3338 11:15:40.234102 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3339 11:15:40.234188 # ok 1609 Set SVE VL 6432
3340 11:15:40.234273 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3341 11:15:40.234360 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3342 11:15:40.234450 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3343 11:15:40.234532 # ok 1613 Set SVE VL 6448
3344 11:15:40.234810 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3345 11:15:40.234905 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3346 11:15:40.234992 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3347 11:15:40.235075 # ok 1617 Set SVE VL 6464
3348 11:15:40.235159 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3349 11:15:40.235245 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3350 11:15:40.235330 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3351 11:15:40.235420 # ok 1621 Set SVE VL 6480
3352 11:15:40.235503 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3353 11:15:40.235584 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3354 11:15:40.235666 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3355 11:15:40.235749 # ok 1625 Set SVE VL 6496
3356 11:15:40.235832 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3357 11:15:40.235915 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3358 11:15:40.235997 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3359 11:15:40.236081 # ok 1629 Set SVE VL 6512
3360 11:15:40.236164 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3361 11:15:40.236249 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3362 11:15:40.236331 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3363 11:15:40.236417 # ok 1633 Set SVE VL 6528
3364 11:15:40.236500 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3365 11:15:40.236583 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3366 11:15:40.236666 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3367 11:15:40.236747 # ok 1637 Set SVE VL 6544
3368 11:15:40.236828 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3369 11:15:40.236910 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3370 11:15:40.236992 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3371 11:15:40.237078 # ok 1641 Set SVE VL 6560
3372 11:15:40.237634 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3373 11:15:40.237744 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3374 11:15:40.237832 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3375 11:15:40.237918 # ok 1645 Set SVE VL 6576
3376 11:15:40.238003 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3377 11:15:40.238089 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3378 11:15:40.238176 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3379 11:15:40.238263 # ok 1649 Set SVE VL 6592
3380 11:15:40.238347 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3381 11:15:40.238434 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3382 11:15:40.238519 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3383 11:15:40.238602 # ok 1653 Set SVE VL 6608
3384 11:15:40.238683 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3385 11:15:40.238770 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3386 11:15:40.238857 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3387 11:15:40.238942 # ok 1657 Set SVE VL 6624
3388 11:15:40.239023 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3389 11:15:40.239106 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3390 11:15:40.239188 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3391 11:15:40.239271 # ok 1661 Set SVE VL 6640
3392 11:15:40.239353 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3393 11:15:40.239436 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3394 11:15:40.239521 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3395 11:15:40.239604 # ok 1665 Set SVE VL 6656
3396 11:15:40.239687 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3397 11:15:40.239768 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3398 11:15:40.239851 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3399 11:15:40.239933 # ok 1669 Set SVE VL 6672
3400 11:15:40.240014 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3401 11:15:40.240096 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3402 11:15:40.240177 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3403 11:15:40.240260 # ok 1673 Set SVE VL 6688
3404 11:15:40.240342 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3405 11:15:40.240430 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3406 11:15:40.240512 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3407 11:15:40.240594 # ok 1677 Set SVE VL 6704
3408 11:15:40.240675 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3409 11:15:40.240758 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3410 11:15:40.240840 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3411 11:15:40.240922 # ok 1681 Set SVE VL 6720
3412 11:15:40.241006 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3413 11:15:40.241091 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3414 11:15:40.242011 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3415 11:15:40.242116 # ok 1685 Set SVE VL 6736
3416 11:15:40.242204 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3417 11:15:40.242288 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3418 11:15:40.242374 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3419 11:15:40.242460 # ok 1689 Set SVE VL 6752
3420 11:15:40.242545 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3421 11:15:40.242648 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3422 11:15:40.242739 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3423 11:15:40.242826 # ok 1693 Set SVE VL 6768
3424 11:15:40.242910 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3425 11:15:40.242994 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3426 11:15:40.243079 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3427 11:15:40.243163 # ok 1697 Set SVE VL 6784
3428 11:15:40.243247 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3429 11:15:40.243330 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3430 11:15:40.243420 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3431 11:15:40.243508 # ok 1701 Set SVE VL 6800
3432 11:15:40.243594 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3433 11:15:40.243680 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3434 11:15:40.243761 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3435 11:15:40.243846 # ok 1705 Set SVE VL 6816
3436 11:15:40.243928 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3437 11:15:40.244014 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3438 11:15:40.244097 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3439 11:15:40.244183 # ok 1709 Set SVE VL 6832
3440 11:15:40.244267 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3441 11:15:40.244353 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3442 11:15:40.244438 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3443 11:15:40.244523 # ok 1713 Set SVE VL 6848
3444 11:15:40.244608 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3445 11:15:40.244693 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3446 11:15:40.244777 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3447 11:15:40.244861 # ok 1717 Set SVE VL 6864
3448 11:15:40.244945 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3449 11:15:40.245030 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3450 11:15:40.245117 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3451 11:15:40.245203 # ok 1721 Set SVE VL 6880
3452 11:15:40.245287 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3453 11:15:40.245372 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3454 11:15:40.245455 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3455 11:15:40.245540 # ok 1725 Set SVE VL 6896
3456 11:15:40.245623 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3457 11:15:40.246543 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3458 11:15:40.246648 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3459 11:15:40.246741 # ok 1729 Set SVE VL 6912
3460 11:15:40.246828 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3461 11:15:40.246914 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3462 11:15:40.246999 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3463 11:15:40.247086 # ok 1733 Set SVE VL 6928
3464 11:15:40.247174 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3465 11:15:40.247258 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3466 11:15:40.247340 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3467 11:15:40.247423 # ok 1737 Set SVE VL 6944
3468 11:15:40.247506 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3469 11:15:40.247588 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3470 11:15:40.247670 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3471 11:15:40.247752 # ok 1741 Set SVE VL 6960
3472 11:15:40.247834 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3473 11:15:40.247915 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3474 11:15:40.247995 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3475 11:15:40.248076 # ok 1745 Set SVE VL 6976
3476 11:15:40.248157 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3477 11:15:40.248237 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3478 11:15:40.248320 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3479 11:15:40.248403 # ok 1749 Set SVE VL 6992
3480 11:15:40.248486 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3481 11:15:40.248567 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3482 11:15:40.248649 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3483 11:15:40.248733 # ok 1753 Set SVE VL 7008
3484 11:15:40.248817 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3485 11:15:40.248899 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3486 11:15:40.248981 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3487 11:15:40.249064 # ok 1757 Set SVE VL 7024
3488 11:15:40.249144 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3489 11:15:40.249226 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3490 11:15:40.249306 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3491 11:15:40.249389 # ok 1761 Set SVE VL 7040
3492 11:15:40.249473 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3493 11:15:40.249555 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3494 11:15:40.249638 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3495 11:15:40.250251 # ok 1765 Set SVE VL 7056
3496 11:15:40.250341 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3497 11:15:40.250428 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3498 11:15:40.250515 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3499 11:15:40.250601 # ok 1769 Set SVE VL 7072
3500 11:15:40.250900 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3501 11:15:40.251007 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3502 11:15:40.251094 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3503 11:15:40.251176 # ok 1773 Set SVE VL 7088
3504 11:15:40.251257 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3505 11:15:40.251337 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3506 11:15:40.251417 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3507 11:15:40.251502 # ok 1777 Set SVE VL 7104
3508 11:15:40.251587 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3509 11:15:40.251669 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3510 11:15:40.251749 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3511 11:15:40.251829 # ok 1781 Set SVE VL 7120
3512 11:15:40.251909 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3513 11:15:40.251996 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3514 11:15:40.252081 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3515 11:15:40.252166 # ok 1785 Set SVE VL 7136
3516 11:15:40.252254 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3517 11:15:40.252341 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3518 11:15:40.252428 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3519 11:15:40.252516 # ok 1789 Set SVE VL 7152
3520 11:15:40.252602 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3521 11:15:40.252687 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3522 11:15:40.252772 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3523 11:15:40.252862 # ok 1793 Set SVE VL 7168
3524 11:15:40.252948 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3525 11:15:40.253032 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3526 11:15:40.253118 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3527 11:15:40.253201 # ok 1797 Set SVE VL 7184
3528 11:15:40.253284 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3529 11:15:40.253365 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3530 11:15:40.253448 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3531 11:15:40.253533 # ok 1801 Set SVE VL 7200
3532 11:15:40.253616 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3533 11:15:40.253707 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3534 11:15:40.253789 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3535 11:15:40.253871 # ok 1805 Set SVE VL 7216
3536 11:15:40.253954 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3537 11:15:40.254038 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3538 11:15:40.254119 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3539 11:15:40.254201 # ok 1809 Set SVE VL 7232
3540 11:15:40.254281 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3541 11:15:40.254363 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3542 11:15:40.254696 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3543 11:15:40.254804 # ok 1813 Set SVE VL 7248
3544 11:15:40.254896 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3545 11:15:40.254983 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3546 11:15:40.255061 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3547 11:15:40.255136 # ok 1817 Set SVE VL 7264
3548 11:15:40.255211 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3549 11:15:40.255285 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3550 11:15:40.255360 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3551 11:15:40.255440 # ok 1821 Set SVE VL 7280
3552 11:15:40.255525 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3553 11:15:40.255613 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3554 11:15:40.255694 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3555 11:15:40.255779 # ok 1825 Set SVE VL 7296
3556 11:15:40.255855 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3557 11:15:40.255930 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3558 11:15:40.256007 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3559 11:15:40.256082 # ok 1829 Set SVE VL 7312
3560 11:15:40.256163 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3561 11:15:40.256250 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3562 11:15:40.256339 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3563 11:15:40.256427 # ok 1833 Set SVE VL 7328
3564 11:15:40.256506 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3565 11:15:40.256582 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3566 11:15:40.256656 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3567 11:15:40.256734 # ok 1837 Set SVE VL 7344
3568 11:15:40.256818 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3569 11:15:40.257336 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3570 11:15:40.257429 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3571 11:15:40.257506 # ok 1841 Set SVE VL 7360
3572 11:15:40.257582 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3573 11:15:40.257664 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3574 11:15:40.257747 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3575 11:15:40.257829 # ok 1845 Set SVE VL 7376
3576 11:15:40.257914 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3577 11:15:40.257991 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3578 11:15:40.258066 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3579 11:15:40.258140 # ok 1849 Set SVE VL 7392
3580 11:15:40.258214 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3581 11:15:40.258289 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3582 11:15:40.258370 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3583 11:15:40.258449 # ok 1853 Set SVE VL 7408
3584 11:15:40.258524 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3585 11:15:40.258801 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3586 11:15:40.258917 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3587 11:15:40.259026 # ok 1857 Set SVE VL 7424
3588 11:15:40.259119 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3589 11:15:40.259201 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3590 11:15:40.259281 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3591 11:15:40.259361 # ok 1861 Set SVE VL 7440
3592 11:15:40.259430 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3593 11:15:40.259508 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3594 11:15:40.259593 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3595 11:15:40.259679 # ok 1865 Set SVE VL 7456
3596 11:15:40.259762 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3597 11:15:40.259840 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3598 11:15:40.259916 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3599 11:15:40.259989 # ok 1869 Set SVE VL 7472
3600 11:15:40.260065 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3601 11:15:40.260144 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3602 11:15:40.260224 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3603 11:15:40.260303 # ok 1873 Set SVE VL 7488
3604 11:15:40.260374 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3605 11:15:40.260447 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3606 11:15:40.260517 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3607 11:15:40.260588 # ok 1877 Set SVE VL 7504
3608 11:15:40.260661 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3609 11:15:40.260726 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3610 11:15:40.260786 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3611 11:15:40.260849 # ok 1881 Set SVE VL 7520
3612 11:15:40.260925 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3613 11:15:40.261003 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3614 11:15:40.261081 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3615 11:15:40.261149 # ok 1885 Set SVE VL 7536
3616 11:15:40.261218 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3617 11:15:40.261282 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3618 11:15:40.261359 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3619 11:15:40.261438 # ok 1889 Set SVE VL 7552
3620 11:15:40.261512 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3621 11:15:40.261580 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3622 11:15:40.269663 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3623 11:15:40.269841 # ok 1893 Set SVE VL 7568
3624 11:15:40.269931 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3625 11:15:40.270012 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3626 11:15:40.270083 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3627 11:15:40.270167 # ok 1897 Set SVE VL 7584
3628 11:15:40.270474 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3629 11:15:40.270577 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3630 11:15:40.270651 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3631 11:15:40.270722 # ok 1901 Set SVE VL 7600
3632 11:15:40.270801 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3633 11:15:40.270877 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3634 11:15:40.270956 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3635 11:15:40.271026 # ok 1905 Set SVE VL 7616
3636 11:15:40.271097 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3637 11:15:40.271164 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3638 11:15:40.271246 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3639 11:15:40.271332 # ok 1909 Set SVE VL 7632
3640 11:15:40.271419 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3641 11:15:40.271540 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3642 11:15:40.271655 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3643 11:15:40.271765 # ok 1913 Set SVE VL 7648
3644 11:15:40.271863 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3645 11:15:40.271943 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3646 11:15:40.272023 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3647 11:15:40.272100 # ok 1917 Set SVE VL 7664
3648 11:15:40.272178 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3649 11:15:40.272261 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3650 11:15:40.272345 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3651 11:15:40.272430 # ok 1921 Set SVE VL 7680
3652 11:15:40.272516 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3653 11:15:40.272605 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3654 11:15:40.272693 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3655 11:15:40.272780 # ok 1925 Set SVE VL 7696
3656 11:15:40.272866 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3657 11:15:40.272951 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3658 11:15:40.273035 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3659 11:15:40.273115 # ok 1929 Set SVE VL 7712
3660 11:15:40.273192 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3661 11:15:40.273263 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3662 11:15:40.273342 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3663 11:15:40.273421 # ok 1933 Set SVE VL 7728
3664 11:15:40.273508 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3665 11:15:40.273583 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3666 11:15:40.273673 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3667 11:15:40.273756 # ok 1937 Set SVE VL 7744
3668 11:15:40.273833 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3669 11:15:40.273908 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3670 11:15:40.273984 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3671 11:15:40.274270 # ok 1941 Set SVE VL 7760
3672 11:15:40.274370 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3673 11:15:40.274451 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3674 11:15:40.274538 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3675 11:15:40.274609 # ok 1945 Set SVE VL 7776
3676 11:15:40.274689 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3677 11:15:40.274785 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3678 11:15:40.274873 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3679 11:15:40.274959 # ok 1949 Set SVE VL 7792
3680 11:15:40.275044 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3681 11:15:40.275130 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3682 11:15:40.275214 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3683 11:15:40.275299 # ok 1953 Set SVE VL 7808
3684 11:15:40.275380 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3685 11:15:40.275462 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3686 11:15:40.275542 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3687 11:15:40.275628 # ok 1957 Set SVE VL 7824
3688 11:15:40.275712 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3689 11:15:40.275797 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3690 11:15:40.275883 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3691 11:15:40.275969 # ok 1961 Set SVE VL 7840
3692 11:15:40.276055 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3693 11:15:40.276140 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3694 11:15:40.276226 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3695 11:15:40.276311 # ok 1965 Set SVE VL 7856
3696 11:15:40.276394 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3697 11:15:40.276478 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3698 11:15:40.276563 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3699 11:15:40.276649 # ok 1969 Set SVE VL 7872
3700 11:15:40.276735 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3701 11:15:40.276820 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3702 11:15:40.276906 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3703 11:15:40.276990 # ok 1973 Set SVE VL 7888
3704 11:15:40.277069 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3705 11:15:40.277148 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3706 11:15:40.277226 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3707 11:15:40.277304 # ok 1977 Set SVE VL 7904
3708 11:15:40.277384 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3709 11:15:40.277463 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3710 11:15:40.277542 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3711 11:15:40.277622 # ok 1981 Set SVE VL 7920
3712 11:15:40.277714 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3713 11:15:40.277798 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3714 11:15:40.278088 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3715 11:15:40.278182 # ok 1985 Set SVE VL 7936
3716 11:15:40.278271 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3717 11:15:40.278352 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3718 11:15:40.278430 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3719 11:15:40.278509 # ok 1989 Set SVE VL 7952
3720 11:15:40.278588 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3721 11:15:40.278668 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3722 11:15:40.278746 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3723 11:15:40.278824 # ok 1993 Set SVE VL 7968
3724 11:15:40.278903 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3725 11:15:40.278983 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3726 11:15:40.279068 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3727 11:15:40.279152 # ok 1997 Set SVE VL 7984
3728 11:15:40.279234 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3729 11:15:40.279319 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3730 11:15:40.279408 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3731 11:15:40.279494 # ok 2001 Set SVE VL 8000
3732 11:15:40.279580 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3733 11:15:40.279664 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3734 11:15:40.279749 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3735 11:15:40.279833 # ok 2005 Set SVE VL 8016
3736 11:15:40.279919 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3737 11:15:40.280004 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3738 11:15:40.280088 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3739 11:15:40.280174 # ok 2009 Set SVE VL 8032
3740 11:15:40.280259 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3741 11:15:40.280345 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3742 11:15:40.280431 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3743 11:15:40.280512 # ok 2013 Set SVE VL 8048
3744 11:15:40.280596 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3745 11:15:40.280678 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3746 11:15:40.280764 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3747 11:15:40.280850 # ok 2017 Set SVE VL 8064
3748 11:15:40.280936 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3749 11:15:40.281023 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3750 11:15:40.281108 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3751 11:15:40.281195 # ok 2021 Set SVE VL 8080
3752 11:15:40.281279 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3753 11:15:40.281361 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3754 11:15:40.281445 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3755 11:15:40.281528 # ok 2025 Set SVE VL 8096
3756 11:15:40.281615 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3757 11:15:40.281916 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3758 11:15:40.282019 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3759 11:15:40.282107 # ok 2029 Set SVE VL 8112
3760 11:15:40.282192 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3761 11:15:40.282277 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3762 11:15:40.282364 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3763 11:15:40.282451 # ok 2033 Set SVE VL 8128
3764 11:15:40.282539 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3765 11:15:40.282627 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3766 11:15:40.282714 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3767 11:15:40.282799 # ok 2037 Set SVE VL 8144
3768 11:15:40.282884 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3769 11:15:40.282970 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3770 11:15:40.283057 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3771 11:15:40.283143 # ok 2041 Set SVE VL 8160
3772 11:15:40.283230 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3773 11:15:40.283315 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3774 11:15:40.283400 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3775 11:15:40.283487 # ok 2045 Set SVE VL 8176
3776 11:15:40.283572 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3777 11:15:40.283658 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3778 11:15:40.283742 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3779 11:15:40.283827 # ok 2049 Set SVE VL 8192
3780 11:15:40.283914 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3781 11:15:40.284000 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3782 11:15:40.284087 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3783 11:15:40.284173 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3784 11:15:40.284258 # ok 2054 Streaming SVE get_fpsimd() gave same state
3785 11:15:40.284339 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3786 11:15:40.284423 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3787 11:15:40.284507 # ok 2057 Set Streaming SVE VL 16
3788 11:15:40.284589 # ok 2058 Set and get Streaming SVE data for VL 16
3789 11:15:40.284670 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3790 11:15:40.284751 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3791 11:15:40.284853 # ok 2061 Set Streaming SVE VL 32
3792 11:15:40.284939 # ok 2062 Set and get Streaming SVE data for VL 32
3793 11:15:40.285025 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3794 11:15:40.285110 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3795 11:15:40.285195 # ok 2065 Set Streaming SVE VL 48
3796 11:15:40.285280 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3797 11:15:40.285562 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3798 11:15:40.285659 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3799 11:15:40.285746 # ok 2069 Set Streaming SVE VL 64
3800 11:15:40.285831 # ok 2070 Set and get Streaming SVE data for VL 64
3801 11:15:40.285918 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3802 11:15:40.286001 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3803 11:15:40.286083 # ok 2073 Set Streaming SVE VL 80
3804 11:15:40.286166 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3805 11:15:40.286248 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3806 11:15:40.286331 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3807 11:15:40.286413 # ok 2077 Set Streaming SVE VL 96
3808 11:15:40.286494 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3809 11:15:40.286576 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3810 11:15:40.286655 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3811 11:15:40.286740 # ok 2081 Set Streaming SVE VL 112
3812 11:15:40.286826 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3813 11:15:40.286910 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3814 11:15:40.287012 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3815 11:15:40.287096 # ok 2085 Set Streaming SVE VL 128
3816 11:15:40.287180 # ok 2086 Set and get Streaming SVE data for VL 128
3817 11:15:40.287263 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3818 11:15:40.287347 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3819 11:15:40.287428 # ok 2089 Set Streaming SVE VL 144
3820 11:15:40.287513 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3821 11:15:40.287605 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3822 11:15:40.287708 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3823 11:15:40.287794 # ok 2093 Set Streaming SVE VL 160
3824 11:15:40.287876 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3825 11:15:40.287960 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3826 11:15:40.288058 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3827 11:15:40.288145 # ok 2097 Set Streaming SVE VL 176
3828 11:15:40.288229 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3829 11:15:40.288328 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3830 11:15:40.288427 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3831 11:15:40.288523 # ok 2101 Set Streaming SVE VL 192
3832 11:15:40.289038 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3833 11:15:40.289139 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3834 11:15:40.289224 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3835 11:15:40.289308 # ok 2105 Set Streaming SVE VL 208
3836 11:15:40.289403 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3837 11:15:40.289490 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3838 11:15:40.289588 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3839 11:15:40.289898 # ok 2109 Set Streaming SVE VL 224
3840 11:15:40.290000 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3841 11:15:40.290097 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3842 11:15:40.290204 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3843 11:15:40.290313 # ok 2113 Set Streaming SVE VL 240
3844 11:15:40.290611 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3845 11:15:40.290749 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3846 11:15:40.291062 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3847 11:15:40.291163 # ok 2117 Set Streaming SVE VL 256
3848 11:15:40.291264 # ok 2118 Set and get Streaming SVE data for VL 256
3849 11:15:40.291365 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3850 11:15:40.291659 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3851 11:15:40.291762 # ok 2121 Set Streaming SVE VL 272
3852 11:15:40.291861 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3853 11:15:40.291961 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3854 11:15:40.292278 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3855 11:15:40.292381 # ok 2125 Set Streaming SVE VL 288
3856 11:15:40.292479 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3857 11:15:40.292579 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3858 11:15:40.292865 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3859 11:15:40.292955 # ok 2129 Set Streaming SVE VL 304
3860 11:15:40.293052 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3861 11:15:40.293150 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3862 11:15:40.293435 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3863 11:15:40.293528 # ok 2133 Set Streaming SVE VL 320
3864 11:15:40.293632 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3865 11:15:40.293742 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3866 11:15:40.294044 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3867 11:15:40.294144 # ok 2137 Set Streaming SVE VL 336
3868 11:15:40.294243 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3869 11:15:40.294343 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3870 11:15:40.294627 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3871 11:15:40.294722 # ok 2141 Set Streaming SVE VL 352
3872 11:15:40.294826 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3873 11:15:40.294936 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3874 11:15:40.295280 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3875 11:15:40.295382 # ok 2145 Set Streaming SVE VL 368
3876 11:15:40.295484 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3877 11:15:40.295588 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3878 11:15:40.295696 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3879 11:15:40.295797 # ok 2149 Set Streaming SVE VL 384
3880 11:15:40.296093 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3881 11:15:40.296222 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3882 11:15:40.296324 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3883 11:15:40.296424 # ok 2153 Set Streaming SVE VL 400
3884 11:15:40.296720 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3885 11:15:40.296831 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3886 11:15:40.297125 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3887 11:15:40.297224 # ok 2157 Set Streaming SVE VL 416
3888 11:15:40.297323 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3889 11:15:40.297424 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3890 11:15:40.297693 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3891 11:15:40.297786 # ok 2161 Set Streaming SVE VL 432
3892 11:15:40.297884 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3893 11:15:40.298260 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3894 11:15:40.298466 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3895 11:15:40.298607 # ok 2165 Set Streaming SVE VL 448
3896 11:15:40.298698 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3897 11:15:40.299044 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3898 11:15:40.299144 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3899 11:15:40.299229 # ok 2169 Set Streaming SVE VL 464
3900 11:15:40.299327 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3901 11:15:40.299424 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3902 11:15:40.299537 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3903 11:15:40.299638 # ok 2173 Set Streaming SVE VL 480
3904 11:15:40.299941 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3905 11:15:40.300054 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3906 11:15:40.300155 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3907 11:15:40.300252 # ok 2177 Set Streaming SVE VL 496
3908 11:15:40.300543 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3909 11:15:40.300651 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3910 11:15:40.300753 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3911 11:15:40.300853 # ok 2181 Set Streaming SVE VL 512
3912 11:15:40.301141 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3913 11:15:40.301248 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3914 11:15:40.301351 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3915 11:15:40.301451 # ok 2185 Set Streaming SVE VL 528
3916 11:15:40.301736 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3917 11:15:40.301827 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3918 11:15:40.301926 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3919 11:15:40.302010 # ok 2189 Set Streaming SVE VL 544
3920 11:15:40.302107 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3921 11:15:40.302399 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3922 11:15:40.302513 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3923 11:15:40.302599 # ok 2193 Set Streaming SVE VL 560
3924 11:15:40.302904 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3925 11:15:40.303018 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3926 11:15:40.303126 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3927 11:15:40.303425 # ok 2197 Set Streaming SVE VL 576
3928 11:15:40.303539 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3929 11:15:40.303641 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3930 11:15:40.303926 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3931 11:15:40.304017 # ok 2201 Set Streaming SVE VL 592
3932 11:15:40.304113 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3933 11:15:40.305448 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3934 11:15:40.305566 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3935 11:15:40.305664 # ok 2205 Set Streaming SVE VL 608
3936 11:15:40.305767 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3937 11:15:40.306064 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3938 11:15:40.306179 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3939 11:15:40.306279 # ok 2209 Set Streaming SVE VL 624
3940 11:15:40.306377 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3941 11:15:40.306698 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3942 11:15:40.306997 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3943 11:15:40.307111 # ok 2213 Set Streaming SVE VL 640
3944 11:15:40.307212 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3945 11:15:40.307511 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3946 11:15:40.307624 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3947 11:15:40.307722 # ok 2217 Set Streaming SVE VL 656
3948 11:15:40.308005 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3949 11:15:40.308099 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3950 11:15:40.308200 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3951 11:15:40.308300 # ok 2221 Set Streaming SVE VL 672
3952 11:15:40.308402 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3953 11:15:40.308699 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3954 11:15:40.308813 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3955 11:15:40.308913 # ok 2225 Set Streaming SVE VL 688
3956 11:15:40.309225 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3957 11:15:40.309328 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3958 11:15:40.309431 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3959 11:15:40.309532 # ok 2229 Set Streaming SVE VL 704
3960 11:15:40.309637 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3961 11:15:40.309948 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3962 11:15:40.310046 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3963 11:15:40.310135 # ok 2233 Set Streaming SVE VL 720
3964 11:15:40.310226 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3965 11:15:40.310525 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3966 11:15:40.310637 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3967 11:15:40.310950 # ok 2237 Set Streaming SVE VL 736
3968 11:15:40.311032 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3969 11:15:40.311294 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3970 11:15:40.311397 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3971 11:15:40.311501 # ok 2241 Set Streaming SVE VL 752
3972 11:15:40.311608 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3973 11:15:40.311908 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3974 11:15:40.312018 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3975 11:15:40.312140 # ok 2245 Set Streaming SVE VL 768
3976 11:15:40.312247 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3977 11:15:40.312370 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3978 11:15:40.312475 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3979 11:15:40.312595 # ok 2249 Set Streaming SVE VL 784
3980 11:15:40.312701 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3981 11:15:40.312828 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3982 11:15:40.312940 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3983 11:15:40.313061 # ok 2253 Set Streaming SVE VL 800
3984 11:15:40.313179 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3985 11:15:40.313283 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3986 11:15:40.313403 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3987 11:15:40.313511 # ok 2257 Set Streaming SVE VL 816
3988 11:15:40.313632 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3989 11:15:40.313740 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3990 11:15:40.314055 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3991 11:15:40.314162 # ok 2261 Set Streaming SVE VL 832
3992 11:15:40.314264 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3993 11:15:40.314367 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3994 11:15:40.314449 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3995 11:15:40.314520 # ok 2265 Set Streaming SVE VL 848
3996 11:15:40.314625 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3997 11:15:40.314930 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3998 11:15:40.315013 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3999 11:15:40.315109 # ok 2269 Set Streaming SVE VL 864
4000 11:15:40.315193 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
4001 11:15:40.315287 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
4002 11:15:40.315385 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4003 11:15:40.315482 # ok 2273 Set Streaming SVE VL 880
4004 11:15:40.315581 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4005 11:15:40.315675 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4006 11:15:40.316046 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4007 11:15:40.316130 # ok 2277 Set Streaming SVE VL 896
4008 11:15:40.316203 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4009 11:15:40.316275 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4010 11:15:40.316352 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4011 11:15:40.316623 # ok 2281 Set Streaming SVE VL 912
4012 11:15:40.316716 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4013 11:15:40.316809 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4014 11:15:40.317077 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4015 11:15:40.317159 # ok 2285 Set Streaming SVE VL 928
4016 11:15:40.317238 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4017 11:15:40.317335 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4018 11:15:40.317652 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4019 11:15:40.317752 # ok 2289 Set Streaming SVE VL 944
4020 11:15:40.317848 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4021 11:15:40.317943 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4022 11:15:40.318038 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4023 11:15:40.318134 # ok 2293 Set Streaming SVE VL 960
4024 11:15:40.318231 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4025 11:15:40.318337 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4026 11:15:40.320515 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4027 11:15:40.320613 # ok 2297 Set Streaming SVE VL 976
4028 11:15:40.320731 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4029 11:15:40.320843 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4030 11:15:40.320946 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4031 11:15:40.321045 # ok 2301 Set Streaming SVE VL 992
4032 11:15:40.321147 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4033 11:15:40.321245 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4034 11:15:40.321331 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4035 11:15:40.321415 # ok 2305 Set Streaming SVE VL 1008
4036 11:15:40.321498 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4037 11:15:40.321583 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4038 11:15:40.321677 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4039 11:15:40.321787 # ok 2309 Set Streaming SVE VL 1024
4040 11:15:40.321881 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4041 11:15:40.321965 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4042 11:15:40.322265 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4043 11:15:40.322364 # ok 2313 Set Streaming SVE VL 1040
4044 11:15:40.322447 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4045 11:15:40.322533 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4046 11:15:40.322645 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4047 11:15:40.322750 # ok 2317 Set Streaming SVE VL 1056
4048 11:15:40.322858 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4049 11:15:40.322962 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4050 11:15:40.323062 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4051 11:15:40.323151 # ok 2321 Set Streaming SVE VL 1072
4052 11:15:40.323236 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4053 11:15:40.323318 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4054 11:15:40.323419 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4055 11:15:40.323513 # ok 2325 Set Streaming SVE VL 1088
4056 11:15:40.323608 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4057 11:15:40.323727 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4058 11:15:40.323833 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4059 11:15:40.323925 # ok 2329 Set Streaming SVE VL 1104
4060 11:15:40.324040 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4061 11:15:40.324167 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4062 11:15:40.324283 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4063 11:15:40.324390 # ok 2333 Set Streaming SVE VL 1120
4064 11:15:40.324502 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4065 11:15:40.324588 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4066 11:15:40.324668 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4067 11:15:40.324748 # ok 2337 Set Streaming SVE VL 1136
4068 11:15:40.324828 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4069 11:15:40.324908 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4070 11:15:40.325004 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4071 11:15:40.325084 # ok 2341 Set Streaming SVE VL 1152
4072 11:15:40.325163 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4073 11:15:40.325240 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4074 11:15:40.325331 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4075 11:15:40.325412 # ok 2345 Set Streaming SVE VL 1168
4076 11:15:40.325490 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4077 11:15:40.325580 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4078 11:15:40.325884 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4079 11:15:40.325991 # ok 2349 Set Streaming SVE VL 1184
4080 11:15:40.326093 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4081 11:15:40.326376 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4082 11:15:40.326479 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4083 11:15:40.326573 # ok 2353 Set Streaming SVE VL 1200
4084 11:15:40.328075 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4085 11:15:40.328174 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4086 11:15:40.328269 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4087 11:15:40.328357 # ok 2357 Set Streaming SVE VL 1216
4088 11:15:40.328599 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4089 11:15:40.328709 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4090 11:15:40.328799 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4091 11:15:40.328872 # ok 2361 Set Streaming SVE VL 1232
4092 11:15:40.329132 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4093 11:15:40.329224 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4094 11:15:40.329300 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4095 11:15:40.329374 # ok 2365 Set Streaming SVE VL 1248
4096 11:15:40.329616 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4097 11:15:40.329696 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4098 11:15:40.329776 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4099 11:15:40.329881 # ok 2369 Set Streaming SVE VL 1264
4100 11:15:40.329989 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4101 11:15:40.330078 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4102 11:15:40.330184 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4103 11:15:40.330288 # ok 2373 Set Streaming SVE VL 1280
4104 11:15:40.330382 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4105 11:15:40.330675 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4106 11:15:40.330987 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4107 11:15:40.331285 # ok 2377 Set Streaming SVE VL 1296
4108 11:15:40.331387 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4109 11:15:40.331494 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4110 11:15:40.331611 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4111 11:15:40.331912 # ok 2381 Set Streaming SVE VL 1312
4112 11:15:40.332007 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4113 11:15:40.332118 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4114 11:15:40.332205 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4115 11:15:40.332292 # ok 2385 Set Streaming SVE VL 1328
4116 11:15:40.332557 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4117 11:15:40.332646 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4118 11:15:40.332927 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4119 11:15:40.333000 # ok 2389 Set Streaming SVE VL 1344
4120 11:15:40.333090 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4121 11:15:40.333354 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4122 11:15:40.333439 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4123 11:15:40.333678 # ok 2393 Set Streaming SVE VL 1360
4124 11:15:40.333762 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4125 11:15:40.334026 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4126 11:15:40.334109 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4127 11:15:40.334205 # ok 2397 Set Streaming SVE VL 1376
4128 11:15:40.334520 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4129 11:15:40.334608 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4130 11:15:40.334905 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4131 11:15:40.335012 # ok 2401 Set Streaming SVE VL 1392
4132 11:15:40.335111 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4133 11:15:40.335209 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4134 11:15:40.335495 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4135 11:15:40.335588 # ok 2405 Set Streaming SVE VL 1408
4136 11:15:40.335688 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4137 11:15:40.335789 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4138 11:15:40.336076 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4139 11:15:40.336192 # ok 2409 Set Streaming SVE VL 1424
4140 11:15:40.336463 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4141 11:15:40.336591 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4142 11:15:40.336708 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4143 11:15:40.336814 # ok 2413 Set Streaming SVE VL 1440
4144 11:15:40.336918 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4145 11:15:40.337022 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4146 11:15:40.337315 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4147 11:15:40.337404 # ok 2417 Set Streaming SVE VL 1456
4148 11:15:40.337513 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4149 11:15:40.337623 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4150 11:15:40.337943 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4151 11:15:40.338045 # ok 2421 Set Streaming SVE VL 1472
4152 11:15:40.338150 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4153 11:15:40.338487 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4154 11:15:40.338599 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4155 11:15:40.338727 # ok 2425 Set Streaming SVE VL 1488
4156 11:15:40.338852 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4157 11:15:40.338971 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4158 11:15:40.339288 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4159 11:15:40.339388 # ok 2429 Set Streaming SVE VL 1504
4160 11:15:40.339486 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4161 11:15:40.339617 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4162 11:15:40.339747 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4163 11:15:40.339869 # ok 2433 Set Streaming SVE VL 1520
4164 11:15:40.339992 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4165 11:15:40.340334 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4166 11:15:40.340433 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4167 11:15:40.340538 # ok 2437 Set Streaming SVE VL 1536
4168 11:15:40.340638 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4169 11:15:40.340956 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4170 11:15:40.341081 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4171 11:15:40.341207 # ok 2441 Set Streaming SVE VL 1552
4172 11:15:40.341296 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4173 11:15:40.341579 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4174 11:15:40.341684 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4175 11:15:40.341783 # ok 2445 Set Streaming SVE VL 1568
4176 11:15:40.341879 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4177 11:15:40.342179 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4178 11:15:40.342291 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4179 11:15:40.342391 # ok 2449 Set Streaming SVE VL 1584
4180 11:15:40.342487 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4181 11:15:40.342876 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4182 11:15:40.343013 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4183 11:15:40.343106 # ok 2453 Set Streaming SVE VL 1600
4184 11:15:40.343203 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4185 11:15:40.343478 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4186 11:15:40.343784 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4187 11:15:40.343880 # ok 2457 Set Streaming SVE VL 1616
4188 11:15:40.343986 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4189 11:15:40.344117 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4190 11:15:40.344216 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4191 11:15:40.344343 # ok 2461 Set Streaming SVE VL 1632
4192 11:15:40.344436 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4193 11:15:40.344528 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4194 11:15:40.344616 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4195 11:15:40.344719 # ok 2465 Set Streaming SVE VL 1648
4196 11:15:40.345145 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4197 11:15:40.345257 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4198 11:15:40.345349 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4199 11:15:40.345450 # ok 2469 Set Streaming SVE VL 1664
4200 11:15:40.345546 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4201 11:15:40.345847 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4202 11:15:40.345943 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4203 11:15:40.346038 # ok 2473 Set Streaming SVE VL 1680
4204 11:15:40.346204 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4205 11:15:40.346344 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4206 11:15:40.346645 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4207 11:15:40.346772 # ok 2477 Set Streaming SVE VL 1696
4208 11:15:40.346881 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4209 11:15:40.347192 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4210 11:15:40.347307 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4211 11:15:40.347395 # ok 2481 Set Streaming SVE VL 1712
4212 11:15:40.347500 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4213 11:15:40.347647 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4214 11:15:40.347960 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4215 11:15:40.348055 # ok 2485 Set Streaming SVE VL 1728
4216 11:15:40.348152 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4217 11:15:40.348421 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4218 11:15:40.348522 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4219 11:15:40.348595 # ok 2489 Set Streaming SVE VL 1744
4220 11:15:40.348705 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4221 11:15:40.349011 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4222 11:15:40.349120 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4223 11:15:40.349209 # ok 2493 Set Streaming SVE VL 1760
4224 11:15:40.349490 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4225 11:15:40.349584 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4226 11:15:40.349693 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4227 11:15:40.349810 # ok 2497 Set Streaming SVE VL 1776
4228 11:15:40.350107 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4229 11:15:40.350198 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4230 11:15:40.350319 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4231 11:15:40.350430 # ok 2501 Set Streaming SVE VL 1792
4232 11:15:40.350555 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4233 11:15:40.350868 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4234 11:15:40.352664 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4235 11:15:40.352797 # ok 2505 Set Streaming SVE VL 1808
4236 11:15:40.352921 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4237 11:15:40.353260 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4238 11:15:40.353419 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4239 11:15:40.353549 # ok 2509 Set Streaming SVE VL 1824
4240 11:15:40.353871 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4241 11:15:40.353973 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4242 11:15:40.354074 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4243 11:15:40.354165 # ok 2513 Set Streaming SVE VL 1840
4244 11:15:40.354261 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4245 11:15:40.354350 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4246 11:15:40.354609 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4247 11:15:40.354925 # ok 2517 Set Streaming SVE VL 1856
4248 11:15:40.355227 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4249 11:15:40.355522 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4250 11:15:40.355615 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4251 11:15:40.355762 # ok 2521 Set Streaming SVE VL 1872
4252 11:15:40.355870 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4253 11:15:40.356169 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4254 11:15:40.356269 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4255 11:15:40.356368 # ok 2525 Set Streaming SVE VL 1888
4256 11:15:40.356667 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4257 11:15:40.356784 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4258 11:15:40.356898 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4259 11:15:40.357003 # ok 2529 Set Streaming SVE VL 1904
4260 11:15:40.357164 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4261 11:15:40.357277 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4262 11:15:40.357375 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4263 11:15:40.357671 # ok 2533 Set Streaming SVE VL 1920
4264 11:15:40.357769 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4265 11:15:40.357891 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4266 11:15:40.358201 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4267 11:15:40.358301 # ok 2537 Set Streaming SVE VL 1936
4268 11:15:40.358413 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4269 11:15:40.358501 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4270 11:15:40.358823 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4271 11:15:40.358940 # ok 2541 Set Streaming SVE VL 1952
4272 11:15:40.359041 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4273 11:15:40.359144 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4274 11:15:40.359410 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4275 11:15:40.359509 # ok 2545 Set Streaming SVE VL 1968
4276 11:15:40.359792 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4277 11:15:40.359888 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4278 11:15:40.359990 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4279 11:15:40.360074 # ok 2549 Set Streaming SVE VL 1984
4280 11:15:40.360172 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4281 11:15:40.360473 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4282 11:15:40.360576 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4283 11:15:40.360655 # ok 2553 Set Streaming SVE VL 2000
4284 11:15:40.360922 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4285 11:15:40.361169 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4286 11:15:40.361235 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4287 11:15:40.361308 # ok 2557 Set Streaming SVE VL 2016
4288 11:15:40.361380 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4289 11:15:40.361627 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4290 11:15:40.361712 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4291 11:15:40.361980 # ok 2561 Set Streaming SVE VL 2032
4292 11:15:40.362048 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4293 11:15:40.362294 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4294 11:15:40.362370 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4295 11:15:40.362630 # ok 2565 Set Streaming SVE VL 2048
4296 11:15:40.362728 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4297 11:15:40.363015 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4298 11:15:40.363289 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4299 11:15:40.363363 # ok 2569 Set Streaming SVE VL 2064
4300 11:15:40.363607 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4301 11:15:40.363672 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4302 11:15:40.363919 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4303 11:15:40.363983 # ok 2573 Set Streaming SVE VL 2080
4304 11:15:40.364226 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4305 11:15:40.364300 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4306 11:15:40.364543 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4307 11:15:40.364607 # ok 2577 Set Streaming SVE VL 2096
4308 11:15:40.364866 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4309 11:15:40.364971 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4310 11:15:40.365068 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4311 11:15:40.365169 # ok 2581 Set Streaming SVE VL 2112
4312 11:15:40.365366 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4313 11:15:40.365482 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4314 11:15:40.365782 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4315 11:15:40.365912 # ok 2585 Set Streaming SVE VL 2128
4316 11:15:40.366226 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4317 11:15:40.366326 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4318 11:15:40.366435 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4319 11:15:40.366543 # ok 2589 Set Streaming SVE VL 2144
4320 11:15:40.366665 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4321 11:15:40.366982 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4322 11:15:40.367105 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4323 11:15:40.367214 # ok 2593 Set Streaming SVE VL 2160
4324 11:15:40.367514 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4325 11:15:40.367628 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4326 11:15:40.367743 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4327 11:15:40.367843 # ok 2597 Set Streaming SVE VL 2176
4328 11:15:40.368173 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4329 11:15:40.368279 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4330 11:15:40.368403 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4331 11:15:40.368492 # ok 2601 Set Streaming SVE VL 2192
4332 11:15:40.368593 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4333 11:15:40.368692 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4334 11:15:40.368991 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4335 11:15:40.369095 # ok 2605 Set Streaming SVE VL 2208
4336 11:15:40.369192 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4337 11:15:40.369372 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4338 11:15:40.369483 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4339 11:15:40.369577 # ok 2609 Set Streaming SVE VL 2224
4340 11:15:40.369870 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4341 11:15:40.369978 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4342 11:15:40.370075 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4343 11:15:40.370171 # ok 2613 Set Streaming SVE VL 2240
4344 11:15:40.370539 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4345 11:15:40.370658 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4346 11:15:40.370982 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4347 11:15:40.371064 # ok 2617 Set Streaming SVE VL 2256
4348 11:15:40.371321 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4349 11:15:40.371421 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4350 11:15:40.371510 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4351 11:15:40.371578 # ok 2621 Set Streaming SVE VL 2272
4352 11:15:40.371663 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4353 11:15:40.371966 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4354 11:15:40.372081 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4355 11:15:40.372196 # ok 2625 Set Streaming SVE VL 2288
4356 11:15:40.372293 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4357 11:15:40.372402 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4358 11:15:40.372759 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4359 11:15:40.372875 # ok 2629 Set Streaming SVE VL 2304
4360 11:15:40.372995 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4361 11:15:40.373088 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4362 11:15:40.373421 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4363 11:15:40.373526 # ok 2633 Set Streaming SVE VL 2320
4364 11:15:40.373657 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4365 11:15:40.373776 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4366 11:15:40.373895 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4367 11:15:40.373999 # ok 2637 Set Streaming SVE VL 2336
4368 11:15:40.374106 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4369 11:15:40.374473 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4370 11:15:40.374585 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4371 11:15:40.374714 # ok 2641 Set Streaming SVE VL 2352
4372 11:15:40.375013 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4373 11:15:40.375127 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4374 11:15:40.375244 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4375 11:15:40.375325 # ok 2645 Set Streaming SVE VL 2368
4376 11:15:40.375419 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4377 11:15:40.375511 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4378 11:15:40.375652 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4379 11:15:40.375943 # ok 2649 Set Streaming SVE VL 2384
4380 11:15:40.376013 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4381 11:15:40.376261 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4382 11:15:40.376337 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4383 11:15:40.378176 # ok 2653 Set Streaming SVE VL 2400
4384 11:15:40.378285 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4385 11:15:40.378378 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4386 11:15:40.378663 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4387 11:15:40.378755 # ok 2657 Set Streaming SVE VL 2416
4388 11:15:40.379000 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4389 11:15:40.379262 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4390 11:15:40.379339 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4391 11:15:40.379587 # ok 2661 Set Streaming SVE VL 2432
4392 11:15:40.379662 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4393 11:15:40.379975 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4394 11:15:40.380067 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4395 11:15:40.380179 # ok 2665 Set Streaming SVE VL 2448
4396 11:15:40.380278 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4397 11:15:40.380367 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4398 11:15:40.380667 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4399 11:15:40.380824 # ok 2669 Set Streaming SVE VL 2464
4400 11:15:40.380951 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4401 11:15:40.381060 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4402 11:15:40.381188 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4403 11:15:40.381281 # ok 2673 Set Streaming SVE VL 2480
4404 11:15:40.381372 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4405 11:15:40.381476 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4406 11:15:40.381763 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4407 11:15:40.381882 # ok 2677 Set Streaming SVE VL 2496
4408 11:15:40.381996 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4409 11:15:40.382117 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4410 11:15:40.382443 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4411 11:15:40.382583 # ok 2681 Set Streaming SVE VL 2512
4412 11:15:40.382731 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4413 11:15:40.382847 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4414 11:15:40.383176 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4415 11:15:40.383285 # ok 2685 Set Streaming SVE VL 2528
4416 11:15:40.383387 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4417 11:15:40.383488 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4418 11:15:40.383784 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4419 11:15:40.383885 # ok 2689 Set Streaming SVE VL 2544
4420 11:15:40.384010 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4421 11:15:40.384123 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4422 11:15:40.384224 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4423 11:15:40.384327 # ok 2693 Set Streaming SVE VL 2560
4424 11:15:40.384524 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4425 11:15:40.384844 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4426 11:15:40.384945 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4427 11:15:40.385043 # ok 2697 Set Streaming SVE VL 2576
4428 11:15:40.385141 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4429 11:15:40.385438 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4430 11:15:40.385539 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4431 11:15:40.385634 # ok 2701 Set Streaming SVE VL 2592
4432 11:15:40.385763 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4433 11:15:40.385880 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4434 11:15:40.386176 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4435 11:15:40.386276 # ok 2705 Set Streaming SVE VL 2608
4436 11:15:40.386403 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4437 11:15:40.386512 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4438 11:15:40.386652 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4439 11:15:40.386965 # ok 2709 Set Streaming SVE VL 2624
4440 11:15:40.387080 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4441 11:15:40.387171 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4442 11:15:40.387272 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4443 11:15:40.387375 # ok 2713 Set Streaming SVE VL 2640
4444 11:15:40.387672 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4445 11:15:40.387781 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4446 11:15:40.387918 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4447 11:15:40.388060 # ok 2717 Set Streaming SVE VL 2656
4448 11:15:40.388157 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4449 11:15:40.388261 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4450 11:15:40.388551 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4451 11:15:40.388655 # ok 2721 Set Streaming SVE VL 2672
4452 11:15:40.388764 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4453 11:15:40.388868 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4454 11:15:40.389145 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4455 11:15:40.389244 # ok 2725 Set Streaming SVE VL 2688
4456 11:15:40.389323 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4457 11:15:40.389591 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4458 11:15:40.389700 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4459 11:15:40.389830 # ok 2729 Set Streaming SVE VL 2704
4460 11:15:40.389956 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4461 11:15:40.390092 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4462 11:15:40.390413 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4463 11:15:40.390504 # ok 2733 Set Streaming SVE VL 2720
4464 11:15:40.390611 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4465 11:15:40.390928 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4466 11:15:40.391063 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4467 11:15:40.391188 # ok 2737 Set Streaming SVE VL 2736
4468 11:15:40.391284 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4469 11:15:40.391396 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4470 11:15:40.391605 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4471 11:15:40.391728 # ok 2741 Set Streaming SVE VL 2752
4472 11:15:40.391839 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4473 11:15:40.391956 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4474 11:15:40.392276 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4475 11:15:40.392365 # ok 2745 Set Streaming SVE VL 2768
4476 11:15:40.392454 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4477 11:15:40.392548 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4478 11:15:40.392913 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4479 11:15:40.393006 # ok 2749 Set Streaming SVE VL 2784
4480 11:15:40.393092 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4481 11:15:40.393190 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4482 11:15:40.393465 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4483 11:15:40.393546 # ok 2753 Set Streaming SVE VL 2800
4484 11:15:40.393638 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4485 11:15:40.393759 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4486 11:15:40.394046 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4487 11:15:40.394131 # ok 2757 Set Streaming SVE VL 2816
4488 11:15:40.394237 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4489 11:15:40.394350 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4490 11:15:40.394646 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4491 11:15:40.394761 # ok 2761 Set Streaming SVE VL 2832
4492 11:15:40.394882 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4493 11:15:40.395204 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4494 11:15:40.395305 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4495 11:15:40.395382 # ok 2765 Set Streaming SVE VL 2848
4496 11:15:40.395477 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4497 11:15:40.395775 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4498 11:15:40.395885 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4499 11:15:40.395988 # ok 2769 Set Streaming SVE VL 2864
4500 11:15:40.396271 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4501 11:15:40.396367 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4502 11:15:40.396482 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4503 11:15:40.396586 # ok 2773 Set Streaming SVE VL 2880
4504 11:15:40.396691 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4505 11:15:40.396895 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4506 11:15:40.397201 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4507 11:15:40.397297 # ok 2777 Set Streaming SVE VL 2896
4508 11:15:40.397413 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4509 11:15:40.397509 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4510 11:15:40.397641 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4511 11:15:40.397826 # ok 2781 Set Streaming SVE VL 2912
4512 11:15:40.397955 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4513 11:15:40.398249 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4514 11:15:40.398353 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4515 11:15:40.398470 # ok 2785 Set Streaming SVE VL 2928
4516 11:15:40.398572 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4517 11:15:40.398851 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4518 11:15:40.398964 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4519 11:15:40.399065 # ok 2789 Set Streaming SVE VL 2944
4520 11:15:40.399390 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4521 11:15:40.399687 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4522 11:15:40.399798 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4523 11:15:40.399873 # ok 2793 Set Streaming SVE VL 2960
4524 11:15:40.399988 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4525 11:15:40.400079 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4526 11:15:40.400361 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4527 11:15:40.400463 # ok 2797 Set Streaming SVE VL 2976
4528 11:15:40.400595 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4529 11:15:40.400716 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4530 11:15:40.400843 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4531 11:15:40.401134 # ok 2801 Set Streaming SVE VL 2992
4532 11:15:40.401217 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4533 11:15:40.411789 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4534 11:15:40.412225 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4535 11:15:40.412330 # ok 2805 Set Streaming SVE VL 3008
4536 11:15:40.412411 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4537 11:15:40.412490 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4538 11:15:40.412583 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4539 11:15:40.412682 # ok 2809 Set Streaming SVE VL 3024
4540 11:15:40.412769 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4541 11:15:40.412862 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4542 11:15:40.413110 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4543 11:15:40.413232 # ok 2813 Set Streaming SVE VL 3040
4544 11:15:40.413314 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4545 11:15:40.413404 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4546 11:15:40.413697 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4547 11:15:40.413807 # ok 2817 Set Streaming SVE VL 3056
4548 11:15:40.413903 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4549 11:15:40.413996 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4550 11:15:40.414289 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4551 11:15:40.414394 # ok 2821 Set Streaming SVE VL 3072
4552 11:15:40.414496 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4553 11:15:40.414594 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4554 11:15:40.419043 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4555 11:15:40.419405 # ok 2825 Set Streaming SVE VL 3088
4556 11:15:40.419508 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4557 11:15:40.419598 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4558 11:15:40.419694 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4559 11:15:40.419781 # ok 2829 Set Streaming SVE VL 3104
4560 11:15:40.419876 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4561 11:15:40.419959 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4562 11:15:40.420064 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4563 11:15:40.420164 # ok 2833 Set Streaming SVE VL 3120
4564 11:15:40.420457 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4565 11:15:40.420577 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4566 11:15:40.420970 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4567 11:15:40.421074 # ok 2837 Set Streaming SVE VL 3136
4568 11:15:40.421153 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4569 11:15:40.421233 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4570 11:15:40.421524 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4571 11:15:40.421624 # ok 2841 Set Streaming SVE VL 3152
4572 11:15:40.421716 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4573 11:15:40.421812 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4574 11:15:40.421895 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4575 11:15:40.421992 # ok 2845 Set Streaming SVE VL 3168
4576 11:15:40.422070 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4577 11:15:40.422158 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4578 11:15:40.422445 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4579 11:15:40.422553 # ok 2849 Set Streaming SVE VL 3184
4580 11:15:40.422646 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4581 11:15:40.422741 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4582 11:15:40.423169 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4583 11:15:40.423271 # ok 2853 Set Streaming SVE VL 3200
4584 11:15:40.423351 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4585 11:15:40.427124 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4586 11:15:40.432885 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4587 11:15:40.433065 # ok 2857 Set Streaming SVE VL 3216
4588 11:15:40.433133 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4589 11:15:40.433196 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4590 11:15:40.433257 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4591 11:15:40.433317 # ok 2861 Set Streaming SVE VL 3232
4592 11:15:40.433378 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4593 11:15:40.433438 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4594 11:15:40.433498 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4595 11:15:40.433558 # ok 2865 Set Streaming SVE VL 3248
4596 11:15:40.433617 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4597 11:15:40.433689 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4598 11:15:40.433750 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4599 11:15:40.433810 # ok 2869 Set Streaming SVE VL 3264
4600 11:15:40.433870 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4601 11:15:40.433930 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4602 11:15:40.433990 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4603 11:15:40.434049 # ok 2873 Set Streaming SVE VL 3280
4604 11:15:40.434110 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4605 11:15:40.434170 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4606 11:15:40.434230 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4607 11:15:40.434290 # ok 2877 Set Streaming SVE VL 3296
4608 11:15:40.434349 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4609 11:15:40.434408 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4610 11:15:40.434468 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4611 11:15:40.434527 # ok 2881 Set Streaming SVE VL 3312
4612 11:15:40.434586 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4613 11:15:40.434645 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4614 11:15:40.434705 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4615 11:15:40.434764 # ok 2885 Set Streaming SVE VL 3328
4616 11:15:40.434823 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4617 11:15:40.434883 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4618 11:15:40.434942 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4619 11:15:40.435002 # ok 2889 Set Streaming SVE VL 3344
4620 11:15:40.435063 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4621 11:15:40.435320 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4622 11:15:40.435407 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4623 11:15:40.435474 # ok 2893 Set Streaming SVE VL 3360
4624 11:15:40.435535 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4625 11:15:40.435884 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4626 11:15:40.436140 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4627 11:15:40.436232 # ok 2897 Set Streaming SVE VL 3376
4628 11:15:40.436351 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4629 11:15:40.436456 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4630 11:15:40.436751 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4631 11:15:40.436832 # ok 2901 Set Streaming SVE VL 3392
4632 11:15:40.436912 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4633 11:15:40.437189 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4634 11:15:40.437280 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4635 11:15:40.437606 # ok 2905 Set Streaming SVE VL 3408
4636 11:15:40.437703 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4637 11:15:40.437795 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4638 11:15:40.437892 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4639 11:15:40.437983 # ok 2909 Set Streaming SVE VL 3424
4640 11:15:40.438062 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4641 11:15:40.438351 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4642 11:15:40.438463 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4643 11:15:40.438542 # ok 2913 Set Streaming SVE VL 3440
4644 11:15:40.441161 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4645 11:15:40.441480 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4646 11:15:40.441578 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4647 11:15:40.441714 # ok 2917 Set Streaming SVE VL 3456
4648 11:15:40.441821 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4649 11:15:40.441929 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4650 11:15:40.442054 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4651 11:15:40.442175 # ok 2921 Set Streaming SVE VL 3472
4652 11:15:40.442298 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4653 11:15:40.442430 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4654 11:15:40.442548 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4655 11:15:40.443061 # ok 2925 Set Streaming SVE VL 3488
4656 11:15:40.443163 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4657 11:15:40.443265 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4658 11:15:40.443377 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4659 11:15:40.443650 # ok 2929 Set Streaming SVE VL 3504
4660 11:15:40.443768 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4661 11:15:40.444035 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4662 11:15:40.444171 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4663 11:15:40.444288 # ok 2933 Set Streaming SVE VL 3520
4664 11:15:40.444402 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4665 11:15:40.444515 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4666 11:15:40.444814 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4667 11:15:40.444902 # ok 2937 Set Streaming SVE VL 3536
4668 11:15:40.444985 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4669 11:15:40.445250 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4670 11:15:40.445327 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4671 11:15:40.445410 # ok 2941 Set Streaming SVE VL 3552
4672 11:15:40.445674 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4673 11:15:40.445939 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4674 11:15:40.446020 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4675 11:15:40.446111 # ok 2945 Set Streaming SVE VL 3568
4676 11:15:40.446188 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4677 11:15:40.446286 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4678 11:15:40.446570 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4679 11:15:40.446660 # ok 2949 Set Streaming SVE VL 3584
4680 11:15:40.453355 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4681 11:15:40.453684 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4682 11:15:40.454067 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4683 11:15:40.454319 # ok 2953 Set Streaming SVE VL 3600
4684 11:15:40.454399 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4685 11:15:40.454663 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4686 11:15:40.455042 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4687 11:15:40.455477 # ok 2957 Set Streaming SVE VL 3616
4688 11:15:40.455548 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4689 11:15:40.455611 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4690 11:15:40.455686 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4691 11:15:40.455763 # ok 2961 Set Streaming SVE VL 3632
4692 11:15:40.456016 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4693 11:15:40.456097 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4694 11:15:40.456349 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4695 11:15:40.456418 # ok 2965 Set Streaming SVE VL 3648
4696 11:15:40.456494 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4697 11:15:40.456746 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4698 11:15:40.456999 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4699 11:15:40.457069 # ok 2969 Set Streaming SVE VL 3664
4700 11:15:40.457145 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4701 11:15:40.457396 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4702 11:15:40.457464 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4703 11:15:40.457682 # ok 2973 Set Streaming SVE VL 3680
4704 11:15:40.457761 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4705 11:15:40.457842 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4706 11:15:40.458096 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4707 11:15:40.458173 # ok 2977 Set Streaming SVE VL 3696
4708 11:15:40.458247 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4709 11:15:40.458496 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4710 11:15:40.460646 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4711 11:15:40.460917 # ok 2981 Set Streaming SVE VL 3712
4712 11:15:40.461022 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4713 11:15:40.461129 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4714 11:15:40.461231 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4715 11:15:40.461347 # ok 2985 Set Streaming SVE VL 3728
4716 11:15:40.461643 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4717 11:15:40.461752 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4718 11:15:40.461844 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4719 11:15:40.462086 # ok 2989 Set Streaming SVE VL 3744
4720 11:15:40.462199 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4721 11:15:40.462484 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4722 11:15:40.462581 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4723 11:15:40.464747 # ok 2993 Set Streaming SVE VL 3760
4724 11:15:40.465031 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4725 11:15:40.465127 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4726 11:15:40.465255 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4727 11:15:40.465357 # ok 2997 Set Streaming SVE VL 3776
4728 11:15:40.466017 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4729 11:15:40.466111 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4730 11:15:40.466193 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4731 11:15:40.466267 # ok 3001 Set Streaming SVE VL 3792
4732 11:15:40.466327 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4733 11:15:40.466398 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4734 11:15:40.466459 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4735 11:15:40.466539 # ok 3005 Set Streaming SVE VL 3808
4736 11:15:40.471141 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4737 11:15:40.471430 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4738 11:15:40.471532 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4739 11:15:40.471603 # ok 3009 Set Streaming SVE VL 3824
4740 11:15:40.471693 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4741 11:15:40.471963 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4742 11:15:40.472210 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4743 11:15:40.472310 # ok 3013 Set Streaming SVE VL 3840
4744 11:15:40.472405 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4745 11:15:40.472498 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4746 11:15:40.472579 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4747 11:15:40.472665 # ok 3017 Set Streaming SVE VL 3856
4748 11:15:40.472793 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4749 11:15:40.472901 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4750 11:15:40.473214 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4751 11:15:40.473312 # ok 3021 Set Streaming SVE VL 3872
4752 11:15:40.473409 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4753 11:15:40.473505 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4754 11:15:40.473601 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4755 11:15:40.473708 # ok 3025 Set Streaming SVE VL 3888
4756 11:15:40.473796 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4757 11:15:40.474098 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4758 11:15:40.474407 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4759 11:15:40.474532 # ok 3029 Set Streaming SVE VL 3904
4760 11:15:40.474629 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4761 11:15:40.474739 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4762 11:15:40.484193 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4763 11:15:40.484404 # ok 3033 Set Streaming SVE VL 3920
4764 11:15:40.484665 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4765 11:15:40.484769 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4766 11:15:40.484852 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4767 11:15:40.484947 # ok 3037 Set Streaming SVE VL 3936
4768 11:15:40.485028 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4769 11:15:40.485306 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4770 11:15:40.485406 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4771 11:15:40.485497 # ok 3041 Set Streaming SVE VL 3952
4772 11:15:40.485590 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4773 11:15:40.485672 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4774 11:15:40.485952 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4775 11:15:40.486051 # ok 3045 Set Streaming SVE VL 3968
4776 11:15:40.486345 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4777 11:15:40.486440 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4778 11:15:40.486534 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4779 11:15:40.486614 # ok 3049 Set Streaming SVE VL 3984
4780 11:15:40.486691 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4781 11:15:40.494852 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4782 11:15:40.495203 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4783 11:15:40.495288 # ok 3053 Set Streaming SVE VL 4000
4784 11:15:40.495373 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4785 11:15:40.495455 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4786 11:15:40.495716 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4787 11:15:40.495804 # ok 3057 Set Streaming SVE VL 4016
4788 11:15:40.495885 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4789 11:15:40.495966 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4790 11:15:40.496067 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4791 11:15:40.496194 # ok 3061 Set Streaming SVE VL 4032
4792 11:15:40.496326 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4793 11:15:40.496624 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4794 11:15:40.496719 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4795 11:15:40.497005 # ok 3065 Set Streaming SVE VL 4048
4796 11:15:40.497109 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4797 11:15:40.497228 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4798 11:15:40.497342 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4799 11:15:40.497644 # ok 3069 Set Streaming SVE VL 4064
4800 11:15:40.497758 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4801 11:15:40.497859 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4802 11:15:40.497971 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4803 11:15:40.498070 # ok 3073 Set Streaming SVE VL 4080
4804 11:15:40.498161 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4805 11:15:40.498442 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4806 11:15:40.498567 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4807 11:15:40.507383 # ok 3077 Set Streaming SVE VL 4096
4808 11:15:40.507693 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4809 11:15:40.507793 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4810 11:15:40.507893 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4811 11:15:40.507974 # ok 3081 Set Streaming SVE VL 4112
4812 11:15:40.508071 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4813 11:15:40.508161 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4814 11:15:40.508449 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4815 11:15:40.508549 # ok 3085 Set Streaming SVE VL 4128
4816 11:15:40.508641 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4817 11:15:40.508746 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4818 11:15:40.508836 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4819 11:15:40.508928 # ok 3089 Set Streaming SVE VL 4144
4820 11:15:40.509201 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4821 11:15:40.509317 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4822 11:15:40.509426 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4823 11:15:40.509534 # ok 3093 Set Streaming SVE VL 4160
4824 11:15:40.509810 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4825 11:15:40.509906 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4826 11:15:40.510167 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4827 11:15:40.510239 # ok 3097 Set Streaming SVE VL 4176
4828 11:15:40.510500 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4829 11:15:40.510590 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4830 11:15:40.513353 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4831 11:15:40.513657 # ok 3101 Set Streaming SVE VL 4192
4832 11:15:40.513983 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4833 11:15:40.514233 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4834 11:15:40.514488 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4835 11:15:40.514561 # ok 3105 Set Streaming SVE VL 4208
4836 11:15:40.519657 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4837 11:15:40.519928 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4838 11:15:40.520028 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4839 11:15:40.520109 # ok 3109 Set Streaming SVE VL 4224
4840 11:15:40.520190 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4841 11:15:40.520444 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4842 11:15:40.520540 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4843 11:15:40.520821 # ok 3113 Set Streaming SVE VL 4240
4844 11:15:40.520914 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4845 11:15:40.521028 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4846 11:15:40.521141 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4847 11:15:40.521238 # ok 3117 Set Streaming SVE VL 4256
4848 11:15:40.521349 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4849 11:15:40.521456 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4850 11:15:40.521541 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4851 11:15:40.521634 # ok 3121 Set Streaming SVE VL 4272
4852 11:15:40.521739 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4853 11:15:40.522087 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4854 11:15:40.522182 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4855 11:15:40.522300 # ok 3125 Set Streaming SVE VL 4288
4856 11:15:40.522389 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4857 11:15:40.522503 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4858 11:15:40.527289 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4859 11:15:40.527574 # ok 3129 Set Streaming SVE VL 4304
4860 11:15:40.527673 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4861 11:15:40.527768 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4862 11:15:40.527865 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4863 11:15:40.527958 # ok 3133 Set Streaming SVE VL 4320
4864 11:15:40.528050 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4865 11:15:40.528340 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4866 11:15:40.528449 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4867 11:15:40.528560 # ok 3137 Set Streaming SVE VL 4336
4868 11:15:40.528647 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4869 11:15:40.528766 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4870 11:15:40.528880 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4871 11:15:40.528986 # ok 3141 Set Streaming SVE VL 4352
4872 11:15:40.529102 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4873 11:15:40.529213 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4874 11:15:40.529511 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4875 11:15:40.529615 # ok 3145 Set Streaming SVE VL 4368
4876 11:15:40.529737 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4877 11:15:40.529840 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4878 11:15:40.529948 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4879 11:15:40.530029 # ok 3149 Set Streaming SVE VL 4384
4880 11:15:40.530120 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4881 11:15:40.530227 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4882 11:15:40.530339 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4883 11:15:40.530434 # ok 3153 Set Streaming SVE VL 4400
4884 11:15:40.533249 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4885 11:15:40.533559 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4886 11:15:40.533689 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4887 11:15:40.533819 # ok 3157 Set Streaming SVE VL 4416
4888 11:15:40.533913 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4889 11:15:40.534026 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4890 11:15:40.534139 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4891 11:15:40.534227 # ok 3161 Set Streaming SVE VL 4432
4892 11:15:40.534317 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4893 11:15:40.534591 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4894 11:15:40.536351 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4895 11:15:40.536662 # ok 3165 Set Streaming SVE VL 4448
4896 11:15:40.536769 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4897 11:15:40.536885 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4898 11:15:40.537163 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4899 11:15:40.537251 # ok 3169 Set Streaming SVE VL 4464
4900 11:15:40.537348 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4901 11:15:40.537457 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4902 11:15:40.537530 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4903 11:15:40.537620 # ok 3173 Set Streaming SVE VL 4480
4904 11:15:40.537899 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4905 11:15:40.537978 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4906 11:15:40.538069 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4907 11:15:40.538153 # ok 3177 Set Streaming SVE VL 4496
4908 11:15:40.538238 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4909 11:15:40.538521 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4910 11:15:40.540722 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4911 11:15:40.540984 # ok 3181 Set Streaming SVE VL 4512
4912 11:15:40.541063 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4913 11:15:40.541168 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4914 11:15:40.541428 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4915 11:15:40.541499 # ok 3185 Set Streaming SVE VL 4528
4916 11:15:40.541576 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4917 11:15:40.541837 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4918 11:15:40.541908 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4919 11:15:40.542018 # ok 3189 Set Streaming SVE VL 4544
4920 11:15:40.542135 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4921 11:15:40.542441 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4922 11:15:40.542541 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4923 11:15:40.542632 # ok 3193 Set Streaming SVE VL 4560
4924 11:15:40.544273 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4925 11:15:40.544633 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4926 11:15:40.544782 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4927 11:15:40.544937 # ok 3197 Set Streaming SVE VL 4576
4928 11:15:40.545119 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4929 11:15:40.545259 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4930 11:15:40.545390 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4931 11:15:40.545535 # ok 3201 Set Streaming SVE VL 4592
4932 11:15:40.545668 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4933 11:15:40.545793 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4934 11:15:40.545932 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4935 11:15:40.546056 # ok 3205 Set Streaming SVE VL 4608
4936 11:15:40.546164 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4937 11:15:40.546298 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4938 11:15:40.546420 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4939 11:15:40.546560 # ok 3209 Set Streaming SVE VL 4624
4940 11:15:40.546682 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4941 11:15:40.549930 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4942 11:15:40.550191 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4943 11:15:40.550277 # ok 3213 Set Streaming SVE VL 4640
4944 11:15:40.550381 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4945 11:15:40.550658 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4946 11:15:40.551266 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4947 11:15:40.551358 # ok 3217 Set Streaming SVE VL 4656
4948 11:15:40.551424 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4949 11:15:40.551674 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4950 11:15:40.551746 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4951 11:15:40.551810 # ok 3221 Set Streaming SVE VL 4672
4952 11:15:40.551885 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4953 11:15:40.552137 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4954 11:15:40.552207 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4955 11:15:40.552283 # ok 3225 Set Streaming SVE VL 4688
4956 11:15:40.552535 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4957 11:15:40.552614 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4958 11:15:40.552867 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4959 11:15:40.552935 # ok 3229 Set Streaming SVE VL 4704
4960 11:15:40.553015 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4961 11:15:40.553266 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4962 11:15:40.553348 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4963 11:15:40.553598 # ok 3233 Set Streaming SVE VL 4720
4964 11:15:40.553678 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4965 11:15:40.553754 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4966 11:15:40.554003 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4967 11:15:40.554254 # ok 3237 Set Streaming SVE VL 4736
4968 11:15:40.554322 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4969 11:15:40.554396 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4970 11:15:40.554654 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4971 11:15:40.560215 # ok 3241 Set Streaming SVE VL 4752
4972 11:15:40.560478 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4973 11:15:40.560565 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4974 11:15:40.560677 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4975 11:15:40.560767 # ok 3245 Set Streaming SVE VL 4768
4976 11:15:40.560876 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4977 11:15:40.560987 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4978 11:15:40.561097 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4979 11:15:40.561210 # ok 3249 Set Streaming SVE VL 4784
4980 11:15:40.561528 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4981 11:15:40.561611 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4982 11:15:40.562226 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4983 11:15:40.562331 # ok 3253 Set Streaming SVE VL 4800
4984 11:15:40.562442 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4985 11:15:40.562560 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4986 11:15:40.566931 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4987 11:15:40.567018 # ok 3257 Set Streaming SVE VL 4816
4988 11:15:40.567279 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4989 11:15:40.567383 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4990 11:15:40.567480 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4991 11:15:40.567556 # ok 3261 Set Streaming SVE VL 4832
4992 11:15:40.567636 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4993 11:15:40.567920 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4994 11:15:40.568017 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4995 11:15:40.568102 # ok 3265 Set Streaming SVE VL 4848
4996 11:15:40.568183 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4997 11:15:40.568484 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4998 11:15:40.568636 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4999 11:15:40.568780 # ok 3269 Set Streaming SVE VL 4864
5000 11:15:40.568923 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
5001 11:15:40.569042 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
5002 11:15:40.569175 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5003 11:15:40.569291 # ok 3273 Set Streaming SVE VL 4880
5004 11:15:40.569454 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5005 11:15:40.569595 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5006 11:15:40.569759 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5007 11:15:40.569862 # ok 3277 Set Streaming SVE VL 4896
5008 11:15:40.569989 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5009 11:15:40.570132 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5010 11:15:40.570296 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5011 11:15:40.570453 # ok 3281 Set Streaming SVE VL 4912
5012 11:15:40.570631 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5013 11:15:40.570745 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5014 11:15:40.579091 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5015 11:15:40.579312 # ok 3285 Set Streaming SVE VL 4928
5016 11:15:40.579611 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5017 11:15:40.579714 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5018 11:15:40.579799 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5019 11:15:40.579897 # ok 3289 Set Streaming SVE VL 4944
5020 11:15:40.579984 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5021 11:15:40.580062 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5022 11:15:40.580153 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5023 11:15:40.580232 # ok 3293 Set Streaming SVE VL 4960
5024 11:15:40.580324 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5025 11:15:40.580424 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5026 11:15:40.580519 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5027 11:15:40.580616 # ok 3297 Set Streaming SVE VL 4976
5028 11:15:40.580918 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5029 11:15:40.581024 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5030 11:15:40.581144 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5031 11:15:40.581249 # ok 3301 Set Streaming SVE VL 4992
5032 11:15:40.581546 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5033 11:15:40.581671 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5034 11:15:40.582000 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5035 11:15:40.582103 # ok 3305 Set Streaming SVE VL 5008
5036 11:15:40.582203 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5037 11:15:40.582303 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5038 11:15:40.582508 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5039 11:15:40.582628 # ok 3309 Set Streaming SVE VL 5024
5040 11:15:40.594383 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5041 11:15:40.594650 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5042 11:15:40.594801 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5043 11:15:40.595180 # ok 3313 Set Streaming SVE VL 5040
5044 11:15:40.595405 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5045 11:15:40.595600 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5046 11:15:40.595796 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5047 11:15:40.595962 # ok 3317 Set Streaming SVE VL 5056
5048 11:15:40.596151 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5049 11:15:40.596319 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5050 11:15:40.596511 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5051 11:15:40.596678 # ok 3321 Set Streaming SVE VL 5072
5052 11:15:40.596842 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5053 11:15:40.597019 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5054 11:15:40.597164 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5055 11:15:40.597291 # ok 3325 Set Streaming SVE VL 5088
5056 11:15:40.597417 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5057 11:15:40.597570 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5058 11:15:40.597728 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5059 11:15:40.597934 # ok 3329 Set Streaming SVE VL 5104
5060 11:15:40.598121 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5061 11:15:40.598342 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5062 11:15:40.598481 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5063 11:15:40.598625 # ok 3333 Set Streaming SVE VL 5120
5064 11:15:40.598766 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5065 11:15:40.598906 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5066 11:15:40.599080 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5067 11:15:40.599218 # ok 3337 Set Streaming SVE VL 5136
5068 11:15:40.606355 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5069 11:15:40.606834 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5070 11:15:40.608097 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5071 11:15:40.608476 # ok 3341 Set Streaming SVE VL 5152
5072 11:15:40.608582 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5073 11:15:40.608666 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5074 11:15:40.608750 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5075 11:15:40.608849 # ok 3345 Set Streaming SVE VL 5168
5076 11:15:40.608928 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5077 11:15:40.609004 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5078 11:15:40.609093 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5079 11:15:40.609171 # ok 3349 Set Streaming SVE VL 5184
5080 11:15:40.609260 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5081 11:15:40.609359 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5082 11:15:40.609453 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5083 11:15:40.609542 # ok 3353 Set Streaming SVE VL 5200
5084 11:15:40.609633 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5085 11:15:40.609734 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5086 11:15:40.609830 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5087 11:15:40.609920 # ok 3357 Set Streaming SVE VL 5216
5088 11:15:40.610191 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5089 11:15:40.610277 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5090 11:15:40.610370 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5091 11:15:40.610657 # ok 3361 Set Streaming SVE VL 5232
5092 11:15:40.610761 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5093 11:15:40.611385 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5094 11:15:40.612111 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5095 11:15:40.612213 # ok 3365 Set Streaming SVE VL 5248
5096 11:15:40.612305 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5097 11:15:40.612586 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5098 11:15:40.612693 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5099 11:15:40.612780 # ok 3369 Set Streaming SVE VL 5264
5100 11:15:40.612872 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5101 11:15:40.612950 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5102 11:15:40.613041 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5103 11:15:40.613134 # ok 3373 Set Streaming SVE VL 5280
5104 11:15:40.613211 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5105 11:15:40.613304 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5106 11:15:40.613410 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5107 11:15:40.613502 # ok 3377 Set Streaming SVE VL 5296
5108 11:15:40.613817 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5109 11:15:40.613918 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5110 11:15:40.614216 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5111 11:15:40.614324 # ok 3381 Set Streaming SVE VL 5312
5112 11:15:40.614411 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5113 11:15:40.614514 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5114 11:15:40.614619 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5115 11:15:40.619326 # ok 3385 Set Streaming SVE VL 5328
5116 11:15:40.619749 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5117 11:15:40.619852 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5118 11:15:40.619944 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5119 11:15:40.620026 # ok 3389 Set Streaming SVE VL 5344
5120 11:15:40.620120 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5121 11:15:40.620213 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5122 11:15:40.620302 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5123 11:15:40.620394 # ok 3393 Set Streaming SVE VL 5360
5124 11:15:40.620491 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5125 11:15:40.620785 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5126 11:15:40.620886 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5127 11:15:40.620983 # ok 3397 Set Streaming SVE VL 5376
5128 11:15:40.621061 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5129 11:15:40.621150 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5130 11:15:40.621445 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5131 11:15:40.621545 # ok 3401 Set Streaming SVE VL 5392
5132 11:15:40.622045 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5133 11:15:40.622237 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5134 11:15:40.622393 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5135 11:15:40.622519 # ok 3405 Set Streaming SVE VL 5408
5136 11:15:40.622662 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5137 11:15:40.622803 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5138 11:15:40.636686 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5139 11:15:40.637002 # ok 3409 Set Streaming SVE VL 5424
5140 11:15:40.637434 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5141 11:15:40.637622 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5142 11:15:40.637794 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5143 11:15:40.637943 # ok 3413 Set Streaming SVE VL 5440
5144 11:15:40.638141 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5145 11:15:40.638284 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5146 11:15:40.638427 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5147 11:15:40.638571 # ok 3417 Set Streaming SVE VL 5456
5148 11:15:40.638713 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5149 11:15:40.638855 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5150 11:15:40.638996 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5151 11:15:40.639171 # ok 3421 Set Streaming SVE VL 5472
5152 11:15:40.639311 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5153 11:15:40.642924 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5154 11:15:40.643260 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5155 11:15:40.643442 # ok 3425 Set Streaming SVE VL 5488
5156 11:15:40.643637 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5157 11:15:40.643798 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5158 11:15:40.643985 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5159 11:15:40.644143 # ok 3429 Set Streaming SVE VL 5504
5160 11:15:40.644397 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5161 11:15:40.644630 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5162 11:15:40.644830 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5163 11:15:40.645024 # ok 3433 Set Streaming SVE VL 5520
5164 11:15:40.645232 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5165 11:15:40.645409 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5166 11:15:40.645566 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5167 11:15:40.645765 # ok 3437 Set Streaming SVE VL 5536
5168 11:15:40.645974 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5169 11:15:40.646204 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5170 11:15:40.646355 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5171 11:15:40.646497 # ok 3441 Set Streaming SVE VL 5552
5172 11:15:40.646628 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5173 11:15:40.646744 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5174 11:15:40.646858 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5175 11:15:40.646995 # ok 3445 Set Streaming SVE VL 5568
5176 11:15:40.647112 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5177 11:15:40.651162 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5178 11:15:40.651608 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5179 11:15:40.651789 # ok 3449 Set Streaming SVE VL 5584
5180 11:15:40.652016 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5181 11:15:40.652293 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5182 11:15:40.652487 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5183 11:15:40.652720 # ok 3453 Set Streaming SVE VL 5600
5184 11:15:40.652932 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5185 11:15:40.653082 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5186 11:15:40.653245 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5187 11:15:40.653439 # ok 3457 Set Streaming SVE VL 5616
5188 11:15:40.653592 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5189 11:15:40.653760 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5190 11:15:40.653900 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5191 11:15:40.654047 # ok 3461 Set Streaming SVE VL 5632
5192 11:15:40.654199 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5193 11:15:40.654399 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5194 11:15:40.654582 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5195 11:15:40.654710 # ok 3465 Set Streaming SVE VL 5648
5196 11:15:40.654826 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5197 11:15:40.654940 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5198 11:15:40.655053 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5199 11:15:40.655167 # ok 3469 Set Streaming SVE VL 5664
5200 11:15:40.655281 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5201 11:15:40.657187 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5202 11:15:40.657621 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5203 11:15:40.657820 # ok 3473 Set Streaming SVE VL 5680
5204 11:15:40.658012 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5205 11:15:40.658211 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5206 11:15:40.658365 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5207 11:15:40.658528 # ok 3477 Set Streaming SVE VL 5696
5208 11:15:40.658671 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5209 11:15:40.658814 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5210 11:15:40.658934 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5211 11:15:40.660734 # ok 3481 Set Streaming SVE VL 5712
5212 11:15:40.661200 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5213 11:15:40.661485 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5214 11:15:40.661712 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5215 11:15:40.661923 # ok 3485 Set Streaming SVE VL 5728
5216 11:15:40.662113 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5217 11:15:40.662327 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5218 11:15:40.662534 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5219 11:15:40.662681 # ok 3489 Set Streaming SVE VL 5744
5220 11:15:40.662799 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5221 11:15:40.662913 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5222 11:15:40.663028 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5223 11:15:40.663142 # ok 3493 Set Streaming SVE VL 5760
5224 11:15:40.665381 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5225 11:15:40.665812 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5226 11:15:40.666001 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5227 11:15:40.666176 # ok 3497 Set Streaming SVE VL 5776
5228 11:15:40.666385 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5229 11:15:40.666553 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5230 11:15:40.666684 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5231 11:15:40.666802 # ok 3501 Set Streaming SVE VL 5792
5232 11:15:40.666959 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5233 11:15:40.667138 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5234 11:15:40.667390 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5235 11:15:40.667577 # ok 3505 Set Streaming SVE VL 5808
5236 11:15:40.667767 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5237 11:15:40.667987 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5238 11:15:40.668165 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5239 11:15:40.668338 # ok 3509 Set Streaming SVE VL 5824
5240 11:15:40.668501 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5241 11:15:40.668695 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5242 11:15:40.668858 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5243 11:15:40.669021 # ok 3513 Set Streaming SVE VL 5840
5244 11:15:40.669180 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5245 11:15:40.669367 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5246 11:15:40.669527 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5247 11:15:40.670074 # ok 3517 Set Streaming SVE VL 5856
5248 11:15:40.670270 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5249 11:15:40.670480 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5250 11:15:40.670707 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5251 11:15:40.670844 # ok 3521 Set Streaming SVE VL 5872
5252 11:15:40.670963 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5253 11:15:40.671079 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5254 11:15:40.671192 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5255 11:15:40.671310 # ok 3525 Set Streaming SVE VL 5888
5256 11:15:40.671424 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5257 11:15:40.671538 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5258 11:15:40.675068 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5259 11:15:40.675507 # ok 3529 Set Streaming SVE VL 5904
5260 11:15:40.675658 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5261 11:15:40.675812 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5262 11:15:40.675963 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5263 11:15:40.676111 # ok 3533 Set Streaming SVE VL 5920
5264 11:15:40.676486 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5265 11:15:40.676659 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5266 11:15:40.677037 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5267 11:15:40.677210 # ok 3537 Set Streaming SVE VL 5936
5268 11:15:40.677591 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5269 11:15:40.677802 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5270 11:15:40.678007 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5271 11:15:40.678181 # ok 3541 Set Streaming SVE VL 5952
5272 11:15:40.678383 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5273 11:15:40.678623 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5274 11:15:40.678795 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5275 11:15:40.683098 # ok 3545 Set Streaming SVE VL 5968
5276 11:15:40.683433 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5277 11:15:40.683523 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5278 11:15:40.683641 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5279 11:15:40.683736 # ok 3549 Set Streaming SVE VL 5984
5280 11:15:40.683841 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5281 11:15:40.684588 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5282 11:15:40.684685 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5283 11:15:40.684784 # ok 3553 Set Streaming SVE VL 6000
5284 11:15:40.684886 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5285 11:15:40.685180 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5286 11:15:40.685289 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5287 11:15:40.685383 # ok 3557 Set Streaming SVE VL 6016
5288 11:15:40.685474 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5289 11:15:40.685779 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5290 11:15:40.685886 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5291 11:15:40.685969 # ok 3561 Set Streaming SVE VL 6032
5292 11:15:40.686061 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5293 11:15:40.686167 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5294 11:15:40.686474 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5295 11:15:40.686574 # ok 3565 Set Streaming SVE VL 6048
5296 11:15:40.690156 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5297 11:15:40.690466 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5298 11:15:40.690551 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5299 11:15:40.690626 # ok 3569 Set Streaming SVE VL 6064
5300 11:15:40.693450 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5301 11:15:40.693713 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5302 11:15:40.693900 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5303 11:15:40.694098 # ok 3573 Set Streaming SVE VL 6080
5304 11:15:40.694279 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5305 11:15:40.694439 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5306 11:15:40.694586 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5307 11:15:40.694714 # ok 3577 Set Streaming SVE VL 6096
5308 11:15:40.694830 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5309 11:15:40.695189 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5310 11:15:40.695408 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5311 11:15:40.695600 # ok 3581 Set Streaming SVE VL 6112
5312 11:15:40.695746 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5313 11:15:40.695914 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5314 11:15:40.696085 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5315 11:15:40.696241 # ok 3585 Set Streaming SVE VL 6128
5316 11:15:40.696398 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5317 11:15:40.696589 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5318 11:15:40.696755 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5319 11:15:40.696918 # ok 3589 Set Streaming SVE VL 6144
5320 11:15:40.697108 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5321 11:15:40.697270 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5322 11:15:40.697425 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5323 11:15:40.697584 # ok 3593 Set Streaming SVE VL 6160
5324 11:15:40.697788 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5325 11:15:40.697945 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5326 11:15:40.698102 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5327 11:15:40.698260 # ok 3597 Set Streaming SVE VL 6176
5328 11:15:40.698413 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5329 11:15:40.698587 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5330 11:15:40.698711 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5331 11:15:40.698827 # ok 3601 Set Streaming SVE VL 6192
5332 11:15:40.698941 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5333 11:15:40.699056 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5334 11:15:40.702925 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5335 11:15:40.703356 # ok 3605 Set Streaming SVE VL 6208
5336 11:15:40.703513 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5337 11:15:40.703681 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5338 11:15:40.703865 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5339 11:15:40.703991 # ok 3609 Set Streaming SVE VL 6224
5340 11:15:40.704117 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5341 11:15:40.704268 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5342 11:15:40.704455 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5343 11:15:40.704642 # ok 3613 Set Streaming SVE VL 6240
5344 11:15:40.704894 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5345 11:15:40.705122 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5346 11:15:40.705382 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5347 11:15:40.705566 # ok 3617 Set Streaming SVE VL 6256
5348 11:15:40.705730 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5349 11:15:40.705874 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5350 11:15:40.706074 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5351 11:15:40.706264 # ok 3621 Set Streaming SVE VL 6272
5352 11:15:40.706437 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5353 11:15:40.706601 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5354 11:15:40.706725 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5355 11:15:40.706841 # ok 3625 Set Streaming SVE VL 6288
5356 11:15:40.706955 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5357 11:15:40.707071 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5358 11:15:40.707185 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5359 11:15:40.707298 # ok 3629 Set Streaming SVE VL 6304
5360 11:15:40.723308 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5361 11:15:40.723785 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5362 11:15:40.723894 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5363 11:15:40.723984 # ok 3633 Set Streaming SVE VL 6320
5364 11:15:40.724068 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5365 11:15:40.724168 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5366 11:15:40.724253 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5367 11:15:40.724354 # ok 3637 Set Streaming SVE VL 6336
5368 11:15:40.724438 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5369 11:15:40.724535 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5370 11:15:40.724831 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5371 11:15:40.724948 # ok 3641 Set Streaming SVE VL 6352
5372 11:15:40.725035 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5373 11:15:40.725384 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5374 11:15:40.725489 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5375 11:15:40.725590 # ok 3645 Set Streaming SVE VL 6368
5376 11:15:40.725698 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5377 11:15:40.726002 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5378 11:15:40.726120 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5379 11:15:40.726220 # ok 3649 Set Streaming SVE VL 6384
5380 11:15:40.726517 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5381 11:15:40.734819 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5382 11:15:40.735204 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5383 11:15:40.735311 # ok 3653 Set Streaming SVE VL 6400
5384 11:15:40.735397 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5385 11:15:40.735485 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5386 11:15:40.735787 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5387 11:15:40.735888 # ok 3657 Set Streaming SVE VL 6416
5388 11:15:40.735968 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5389 11:15:40.736060 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5390 11:15:40.736144 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5391 11:15:40.736246 # ok 3661 Set Streaming SVE VL 6432
5392 11:15:40.736326 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5393 11:15:40.736422 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5394 11:15:40.736737 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5395 11:15:40.736950 # ok 3665 Set Streaming SVE VL 6448
5396 11:15:40.737099 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5397 11:15:40.737264 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5398 11:15:40.737408 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5399 11:15:40.737570 # ok 3669 Set Streaming SVE VL 6464
5400 11:15:40.737767 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5401 11:15:40.737937 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5402 11:15:40.738102 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5403 11:15:40.738346 # ok 3673 Set Streaming SVE VL 6480
5404 11:15:40.738532 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5405 11:15:40.738668 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5406 11:15:40.738782 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5407 11:15:40.738895 # ok 3677 Set Streaming SVE VL 6496
5408 11:15:40.739030 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5409 11:15:40.745058 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5410 11:15:40.745404 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5411 11:15:40.745508 # ok 3681 Set Streaming SVE VL 6512
5412 11:15:40.745612 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5413 11:15:40.745721 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5414 11:15:40.746026 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5415 11:15:40.746132 # ok 3685 Set Streaming SVE VL 6528
5416 11:15:40.746232 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5417 11:15:40.746335 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5418 11:15:40.749792 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5419 11:15:40.749925 # ok 3689 Set Streaming SVE VL 6544
5420 11:15:40.750214 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5421 11:15:40.750321 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5422 11:15:40.750426 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5423 11:15:40.750713 # ok 3693 Set Streaming SVE VL 6560
5424 11:15:40.751428 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5425 11:15:40.751736 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5426 11:15:40.751842 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5427 11:15:40.751945 # ok 3697 Set Streaming SVE VL 6576
5428 11:15:40.752036 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5429 11:15:40.752167 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5430 11:15:40.752795 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5431 11:15:40.753238 # ok 3701 Set Streaming SVE VL 6592
5432 11:15:40.753436 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5433 11:15:40.753603 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5434 11:15:40.753806 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5435 11:15:40.753970 # ok 3705 Set Streaming SVE VL 6608
5436 11:15:40.754125 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5437 11:15:40.754298 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5438 11:15:40.754449 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5439 11:15:40.754578 # ok 3709 Set Streaming SVE VL 6624
5440 11:15:40.754718 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5441 11:15:40.754837 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5442 11:15:40.758904 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5443 11:15:40.759062 # ok 3713 Set Streaming SVE VL 6640
5444 11:15:40.759355 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5445 11:15:40.759456 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5446 11:15:40.759537 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5447 11:15:40.759629 # ok 3717 Set Streaming SVE VL 6656
5448 11:15:40.759709 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5449 11:15:40.759809 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5450 11:15:40.759912 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5451 11:15:40.759998 # ok 3721 Set Streaming SVE VL 6672
5452 11:15:40.760088 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5453 11:15:40.760182 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5454 11:15:40.760476 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5455 11:15:40.760589 # ok 3725 Set Streaming SVE VL 6688
5456 11:15:40.760677 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5457 11:15:40.760776 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5458 11:15:40.761065 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5459 11:15:40.761164 # ok 3729 Set Streaming SVE VL 6704
5460 11:15:40.761244 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5461 11:15:40.761338 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5462 11:15:40.761434 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5463 11:15:40.761532 # ok 3733 Set Streaming SVE VL 6720
5464 11:15:40.762017 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5465 11:15:40.762119 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5466 11:15:40.762201 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5467 11:15:40.762286 # ok 3737 Set Streaming SVE VL 6736
5468 11:15:40.762567 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5469 11:15:40.762667 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5470 11:15:40.762752 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5471 11:15:40.762832 # ok 3741 Set Streaming SVE VL 6752
5472 11:15:40.766287 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5473 11:15:40.766584 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5474 11:15:40.766669 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5475 11:15:40.769550 # ok 3745 Set Streaming SVE VL 6768
5476 11:15:40.769841 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5477 11:15:40.769953 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5478 11:15:40.770075 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5479 11:15:40.770192 # ok 3749 Set Streaming SVE VL 6784
5480 11:15:40.770484 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5481 11:15:40.770567 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5482 11:15:40.771202 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5483 11:15:40.771493 # ok 3753 Set Streaming SVE VL 6800
5484 11:15:40.771593 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5485 11:15:40.771688 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5486 11:15:40.771995 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5487 11:15:40.772152 # ok 3757 Set Streaming SVE VL 6816
5488 11:15:40.772307 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5489 11:15:40.772466 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5490 11:15:40.772590 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5491 11:15:40.772708 # ok 3761 Set Streaming SVE VL 6832
5492 11:15:40.772841 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5493 11:15:40.773017 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5494 11:15:40.773162 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5495 11:15:40.773283 # ok 3765 Set Streaming SVE VL 6848
5496 11:15:40.773423 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5497 11:15:40.773546 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5498 11:15:40.773682 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5499 11:15:40.773864 # ok 3769 Set Streaming SVE VL 6864
5500 11:15:40.774020 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5501 11:15:40.774185 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5502 11:15:40.774372 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5503 11:15:40.774536 # ok 3773 Set Streaming SVE VL 6880
5504 11:15:40.774657 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5505 11:15:40.774774 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5506 11:15:40.774912 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5507 11:15:40.776922 # ok 3777 Set Streaming SVE VL 6896
5508 11:15:40.777297 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5509 11:15:40.777433 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5510 11:15:40.777588 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5511 11:15:40.777796 # ok 3781 Set Streaming SVE VL 6912
5512 11:15:40.777967 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5513 11:15:40.778135 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5514 11:15:40.778331 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5515 11:15:40.778520 # ok 3785 Set Streaming SVE VL 6928
5516 11:15:40.778703 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5517 11:15:40.778876 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5518 11:15:40.779078 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5519 11:15:40.779250 # ok 3789 Set Streaming SVE VL 6944
5520 11:15:40.782960 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5521 11:15:40.783081 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5522 11:15:40.783365 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5523 11:15:40.783474 # ok 3793 Set Streaming SVE VL 6960
5524 11:15:40.783577 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5525 11:15:40.783677 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5526 11:15:40.783777 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5527 11:15:40.783880 # ok 3797 Set Streaming SVE VL 6976
5528 11:15:40.784234 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5529 11:15:40.784338 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5530 11:15:40.784443 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5531 11:15:40.784546 # ok 3801 Set Streaming SVE VL 6992
5532 11:15:40.784649 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5533 11:15:40.784977 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5534 11:15:40.785104 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5535 11:15:40.785192 # ok 3805 Set Streaming SVE VL 7008
5536 11:15:40.785488 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5537 11:15:40.785590 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5538 11:15:40.785696 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5539 11:15:40.785802 # ok 3809 Set Streaming SVE VL 7024
5540 11:15:40.786098 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5541 11:15:40.786215 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5542 11:15:40.786313 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5543 11:15:40.786597 # ok 3813 Set Streaming SVE VL 7040
5544 11:15:40.791797 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5545 11:15:40.792122 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5546 11:15:40.792221 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5547 11:15:40.792307 # ok 3817 Set Streaming SVE VL 7056
5548 11:15:40.792427 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5549 11:15:40.792526 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5550 11:15:40.792636 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5551 11:15:40.792737 # ok 3821 Set Streaming SVE VL 7072
5552 11:15:40.792844 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5553 11:15:40.792943 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5554 11:15:40.793243 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5555 11:15:40.793337 # ok 3825 Set Streaming SVE VL 7088
5556 11:15:40.793446 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5557 11:15:40.793550 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5558 11:15:40.793682 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5559 11:15:40.793811 # ok 3829 Set Streaming SVE VL 7104
5560 11:15:40.793922 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5561 11:15:40.794012 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5562 11:15:40.794282 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5563 11:15:40.794374 # ok 3833 Set Streaming SVE VL 7120
5564 11:15:40.794473 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5565 11:15:40.794564 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5566 11:15:40.799626 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5567 11:15:40.799771 # ok 3837 Set Streaming SVE VL 7136
5568 11:15:40.800029 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5569 11:15:40.800790 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5570 11:15:40.800902 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5571 11:15:40.801011 # ok 3841 Set Streaming SVE VL 7152
5572 11:15:40.801106 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5573 11:15:40.801219 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5574 11:15:40.801315 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5575 11:15:40.801383 # ok 3845 Set Streaming SVE VL 7168
5576 11:15:40.801443 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5577 11:15:40.801690 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5578 11:15:40.801771 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5579 11:15:40.801835 # ok 3849 Set Streaming SVE VL 7184
5580 11:15:40.801954 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5581 11:15:40.802284 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5582 11:15:40.802391 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5583 11:15:40.802499 # ok 3853 Set Streaming SVE VL 7200
5584 11:15:40.811036 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5585 11:15:40.811425 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5586 11:15:40.811550 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5587 11:15:40.811753 # ok 3857 Set Streaming SVE VL 7216
5588 11:15:40.811955 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5589 11:15:40.812143 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5590 11:15:40.812319 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5591 11:15:40.812528 # ok 3861 Set Streaming SVE VL 7232
5592 11:15:40.812690 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5593 11:15:40.812847 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5594 11:15:40.813002 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5595 11:15:40.813185 # ok 3865 Set Streaming SVE VL 7248
5596 11:15:40.813344 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5597 11:15:40.813499 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5598 11:15:40.813673 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5599 11:15:40.813834 # ok 3869 Set Streaming SVE VL 7264
5600 11:15:40.814022 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5601 11:15:40.814186 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5602 11:15:40.814345 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5603 11:15:40.814502 # ok 3873 Set Streaming SVE VL 7280
5604 11:15:40.814661 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5605 11:15:40.814817 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5606 11:15:40.815002 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5607 11:15:40.815163 # ok 3877 Set Streaming SVE VL 7296
5608 11:15:40.815320 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5609 11:15:40.821444 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5610 11:15:40.822168 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5611 11:15:40.822369 # ok 3881 Set Streaming SVE VL 7312
5612 11:15:40.822531 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5613 11:15:40.822691 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5614 11:15:40.822877 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5615 11:15:40.823038 # ok 3885 Set Streaming SVE VL 7328
5616 11:15:40.823195 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5617 11:15:40.831231 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5618 11:15:40.831898 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5619 11:15:40.832105 # ok 3889 Set Streaming SVE VL 7344
5620 11:15:40.832274 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5621 11:15:40.832434 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5622 11:15:40.832590 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5623 11:15:40.832780 # ok 3893 Set Streaming SVE VL 7360
5624 11:15:40.832950 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5625 11:15:40.833116 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5626 11:15:40.833273 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5627 11:15:40.833440 # ok 3897 Set Streaming SVE VL 7376
5628 11:15:40.833597 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5629 11:15:40.833798 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5630 11:15:40.833953 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5631 11:15:40.834112 # ok 3901 Set Streaming SVE VL 7392
5632 11:15:40.834275 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5633 11:15:40.834440 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5634 11:15:40.834600 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5635 11:15:40.834722 # ok 3905 Set Streaming SVE VL 7408
5636 11:15:40.834837 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5637 11:15:40.834953 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5638 11:15:40.835068 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5639 11:15:40.835183 # ok 3909 Set Streaming SVE VL 7424
5640 11:15:40.838987 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5641 11:15:40.839436 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5642 11:15:40.839643 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5643 11:15:40.839842 # ok 3913 Set Streaming SVE VL 7440
5644 11:15:40.840078 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5645 11:15:40.840252 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5646 11:15:40.840413 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5647 11:15:40.840548 # ok 3917 Set Streaming SVE VL 7456
5648 11:15:40.840688 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5649 11:15:40.840872 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5650 11:15:40.841043 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5651 11:15:40.841254 # ok 3921 Set Streaming SVE VL 7472
5652 11:15:40.841437 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5653 11:15:40.841602 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5654 11:15:40.841833 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5655 11:15:40.841997 # ok 3925 Set Streaming SVE VL 7488
5656 11:15:40.842156 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5657 11:15:40.842319 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5658 11:15:40.842472 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5659 11:15:40.842614 # ok 3929 Set Streaming SVE VL 7504
5660 11:15:40.842759 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5661 11:15:40.842880 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5662 11:15:40.842995 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5663 11:15:40.843110 # ok 3933 Set Streaming SVE VL 7520
5664 11:15:40.846439 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5665 11:15:40.847138 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5666 11:15:40.847610 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5667 11:15:40.847810 # ok 3937 Set Streaming SVE VL 7536
5668 11:15:40.847994 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5669 11:15:40.848242 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5670 11:15:40.848427 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5671 11:15:40.848658 # ok 3941 Set Streaming SVE VL 7552
5672 11:15:40.848836 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5673 11:15:40.849313 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5674 11:15:40.849511 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5675 11:15:40.849691 # ok 3945 Set Streaming SVE VL 7568
5676 11:15:40.849855 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5677 11:15:40.850016 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5678 11:15:40.850178 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5679 11:15:40.850339 # ok 3949 Set Streaming SVE VL 7584
5680 11:15:40.850533 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5681 11:15:40.850696 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5682 11:15:40.850816 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5683 11:15:40.850930 # ok 3953 Set Streaming SVE VL 7600
5684 11:15:40.851042 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5685 11:15:40.851154 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5686 11:15:40.851267 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5687 11:15:40.851379 # ok 3957 Set Streaming SVE VL 7616
5688 11:15:40.851490 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5689 11:15:40.851601 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5690 11:15:40.851713 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5691 11:15:40.852148 # ok 3961 Set Streaming SVE VL 7632
5692 11:15:40.852412 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5693 11:15:40.852610 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5694 11:15:40.852819 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5695 11:15:40.853292 # ok 3965 Set Streaming SVE VL 7648
5696 11:15:40.853425 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5697 11:15:40.853517 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5698 11:15:40.853602 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5699 11:15:40.853698 # ok 3969 Set Streaming SVE VL 7664
5700 11:15:40.853789 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5701 11:15:40.853891 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5702 11:15:40.853977 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5703 11:15:40.854059 # ok 3973 Set Streaming SVE VL 7680
5704 11:15:40.854141 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5705 11:15:40.854240 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5706 11:15:40.854325 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5707 11:15:40.854433 # ok 3977 Set Streaming SVE VL 7696
5708 11:15:40.854764 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5709 11:15:40.855111 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5710 11:15:40.855210 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5711 11:15:40.855294 # ok 3981 Set Streaming SVE VL 7712
5712 11:15:40.855579 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5713 11:15:40.855678 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5714 11:15:40.855761 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5715 11:15:40.855859 # ok 3985 Set Streaming SVE VL 7728
5716 11:15:40.855944 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5717 11:15:40.856242 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5718 11:15:40.856341 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5719 11:15:40.856437 # ok 3989 Set Streaming SVE VL 7744
5720 11:15:40.856517 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5721 11:15:40.856607 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5722 11:15:40.856952 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5723 11:15:40.857130 # ok 3993 Set Streaming SVE VL 7760
5724 11:15:40.857295 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5725 11:15:40.857416 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5726 11:15:40.857595 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5727 11:15:40.857758 # ok 3997 Set Streaming SVE VL 7776
5728 11:15:40.857956 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5729 11:15:40.858093 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5730 11:15:40.882698 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5731 11:15:40.887201 # ok 4001 Set Streaming SVE VL 7792
5732 11:15:40.887376 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5733 11:15:40.887482 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5734 11:15:40.887586 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5735 11:15:40.887937 # ok 4005 Set Streaming SVE VL 7808
5736 11:15:40.888030 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5737 11:15:40.888115 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5738 11:15:40.888392 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5739 11:15:40.888494 # ok 4009 Set Streaming SVE VL 7824
5740 11:15:40.888579 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5741 11:15:40.888685 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5742 11:15:40.888785 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5743 11:15:40.888884 # ok 4013 Set Streaming SVE VL 7840
5744 11:15:40.889173 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5745 11:15:40.889277 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5746 11:15:40.889574 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5747 11:15:40.889718 # ok 4017 Set Streaming SVE VL 7856
5748 11:15:40.890013 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5749 11:15:40.890118 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5750 11:15:40.890203 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5751 11:15:40.890302 # ok 4021 Set Streaming SVE VL 7872
5752 11:15:40.890389 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5753 11:15:40.895201 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5754 11:15:40.895541 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5755 11:15:40.895634 # ok 4025 Set Streaming SVE VL 7888
5756 11:15:40.895743 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5757 11:15:40.895832 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5758 11:15:40.895931 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5759 11:15:40.896017 # ok 4029 Set Streaming SVE VL 7904
5760 11:15:40.896116 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5761 11:15:40.896457 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5762 11:15:40.896897 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5763 11:15:40.896997 # ok 4033 Set Streaming SVE VL 7920
5764 11:15:40.897100 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5765 11:15:40.897189 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5766 11:15:40.897273 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5767 11:15:40.897359 # ok 4037 Set Streaming SVE VL 7936
5768 11:15:40.897458 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5769 11:15:40.897559 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5770 11:15:40.897668 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5771 11:15:40.897770 # ok 4041 Set Streaming SVE VL 7952
5772 11:15:40.898077 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5773 11:15:40.898197 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5774 11:15:40.898485 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5775 11:15:40.898587 # ok 4045 Set Streaming SVE VL 7968
5776 11:15:40.903153 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5777 11:15:40.903574 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5778 11:15:40.903683 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5779 11:15:40.903778 # ok 4049 Set Streaming SVE VL 7984
5780 11:15:40.903901 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5781 11:15:40.904007 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5782 11:15:40.904105 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5783 11:15:40.904212 # ok 4053 Set Streaming SVE VL 8000
5784 11:15:40.904330 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5785 11:15:40.904430 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5786 11:15:40.904524 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5787 11:15:40.904628 # ok 4057 Set Streaming SVE VL 8016
5788 11:15:40.904725 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5789 11:15:40.904823 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5790 11:15:40.904922 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5791 11:15:40.904990 # ok 4061 Set Streaming SVE VL 8032
5792 11:15:40.905272 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5793 11:15:40.905375 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5794 11:15:40.905474 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5795 11:15:40.905573 # ok 4065 Set Streaming SVE VL 8048
5796 11:15:40.905664 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5797 11:15:40.905758 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5798 11:15:40.906048 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5799 11:15:40.906149 # ok 4069 Set Streaming SVE VL 8064
5800 11:15:40.906230 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5801 11:15:40.906321 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5802 11:15:40.906413 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5803 11:15:40.915024 # ok 4073 Set Streaming SVE VL 8080
5804 11:15:40.915328 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5805 11:15:40.915446 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5806 11:15:40.915556 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5807 11:15:40.915694 # ok 4077 Set Streaming SVE VL 8096
5808 11:15:40.915809 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5809 11:15:40.915937 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5810 11:15:40.916034 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5811 11:15:40.916161 # ok 4081 Set Streaming SVE VL 8112
5812 11:15:40.916267 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5813 11:15:40.916402 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5814 11:15:40.916500 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5815 11:15:40.916599 # ok 4085 Set Streaming SVE VL 8128
5816 11:15:40.916728 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5817 11:15:40.916837 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5818 11:15:40.916946 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5819 11:15:40.917075 # ok 4089 Set Streaming SVE VL 8144
5820 11:15:40.917172 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5821 11:15:40.917271 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5822 11:15:40.917407 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5823 11:15:40.917523 # ok 4093 Set Streaming SVE VL 8160
5824 11:15:40.917680 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5825 11:15:40.917781 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5826 11:15:40.917910 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5827 11:15:40.918014 # ok 4097 Set Streaming SVE VL 8176
5828 11:15:40.918129 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5829 11:15:40.918253 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5830 11:15:40.918348 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5831 11:15:40.918437 # ok 4101 Set Streaming SVE VL 8192
5832 11:15:40.918522 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5833 11:15:40.923130 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5834 11:15:40.923408 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5835 11:15:40.923506 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5836 11:15:40.923577 ok 30 selftests: arm64: sve-ptrace
5837 11:15:40.923692 # selftests: arm64: sve-probe-vls
5838 11:15:40.923797 # TAP version 13
5839 11:15:40.923907 # 1..2
5840 11:15:40.923989 # ok 1 Enumerated 16 vector lengths
5841 11:15:40.924064 # ok 2 All vector lengths valid
5842 11:15:40.924162 # # 16
5843 11:15:40.924263 # # 32
5844 11:15:40.924367 # # 48
5845 11:15:40.924471 # # 64
5846 11:15:40.924566 # # 80
5847 11:15:40.924655 # # 96
5848 11:15:40.924764 # # 112
5849 11:15:40.924838 # # 128
5850 11:15:40.924900 # # 144
5851 11:15:40.924961 # # 160
5852 11:15:40.925021 # # 176
5853 11:15:40.925080 # # 192
5854 11:15:40.925139 # # 208
5855 11:15:40.925199 # # 224
5856 11:15:40.925257 # # 240
5857 11:15:40.925317 # # 256
5858 11:15:40.925376 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5859 11:15:40.925436 ok 31 selftests: arm64: sve-probe-vls
5860 11:15:40.925496 # selftests: arm64: vec-syscfg
5861 11:15:41.276050 # TAP version 13
5862 11:15:41.276454 # 1..20
5863 11:15:41.276620 # ok 1 SVE default vector length 64
5864 11:15:41.276827 # ok 2 SVE minimum vector length 16
5865 11:15:41.277028 # ok 3 SVE maximum vector length 256
5866 11:15:41.277235 # ok 4 SVE current VL is 64
5867 11:15:41.277410 # ok 5 SVE set VL 64 and have VL 64
5868 11:15:41.277598 # ok 6 SVE prctl() set min/max
5869 11:15:41.277805 # ok 7 SVE vector length used default
5870 11:15:41.278003 # ok 8 SVE vector length was inherited
5871 11:15:41.278157 # ok 9 SVE vector length set on exec
5872 11:15:41.278275 # ok 10 SVE prctl() set all VLs, 0 errors
5873 11:15:41.278388 # ok 11 SME default vector length 32
5874 11:15:41.278529 # ok 12 SME minimum vector length 16
5875 11:15:41.278647 # ok 13 SME maximum vector length 256
5876 11:15:41.278760 # ok 14 SME current VL is 32
5877 11:15:41.278872 # ok 15 SME set VL 32 and have VL 32
5878 11:15:41.278983 # ok 16 SME prctl() set min/max
5879 11:15:41.279094 # ok 17 SME vector length used default
5880 11:15:41.279205 # ok 18 SME vector length was inherited
5881 11:15:41.279316 # ok 19 SME vector length set on exec
5882 11:15:41.279427 # ok 20 SME prctl() set all VLs, 0 errors
5883 11:15:41.279538 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5884 11:15:41.290346 ok 32 selftests: arm64: vec-syscfg
5885 11:15:41.375422 # selftests: arm64: za-fork
5886 11:15:41.739876 # TAP version 13
5887 11:15:41.740417 # 1..1
5888 11:15:41.740571 # # PID: 1018
5889 11:15:41.740697 # ok 1 fork_test
5890 11:15:41.740817 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5891 11:15:41.764075 ok 33 selftests: arm64: za-fork
5892 11:15:41.909866 # selftests: arm64: za-ptrace
5893 11:15:42.045775 # TAP version 13
5894 11:15:42.046126 # 1..1536
5895 11:15:42.046318 # # Parent is 1036, child is 1037
5896 11:15:42.046753 # ok 1 Set VL 16
5897 11:15:42.046970 # ok 2 Disabled ZA for VL 16
5898 11:15:42.047156 # ok 3 Data match for VL 16
5899 11:15:42.047336 # ok 4 Set VL 32
5900 11:15:42.047515 # ok 5 Disabled ZA for VL 32
5901 11:15:42.047696 # ok 6 Data match for VL 32
5902 11:15:42.047919 # ok 7 Set VL 48
5903 11:15:42.048113 # ok 8 # SKIP Disabled ZA for VL 48
5904 11:15:42.048297 # ok 9 # SKIP Get and set data for VL 48
5905 11:15:42.048465 # ok 10 Set VL 64
5906 11:15:42.048646 # ok 11 Disabled ZA for VL 64
5907 11:15:42.048833 # ok 12 Data match for VL 64
5908 11:15:42.049047 # ok 13 Set VL 80
5909 11:15:42.049224 # ok 14 # SKIP Disabled ZA for VL 80
5910 11:15:42.049400 # ok 15 # SKIP Get and set data for VL 80
5911 11:15:42.049577 # ok 16 Set VL 96
5912 11:15:42.049767 # ok 17 # SKIP Disabled ZA for VL 96
5913 11:15:42.049954 # ok 18 # SKIP Get and set data for VL 96
5914 11:15:42.050155 # ok 19 Set VL 112
5915 11:15:42.050338 # ok 20 # SKIP Disabled ZA for VL 112
5916 11:15:42.050533 # ok 21 # SKIP Get and set data for VL 112
5917 11:15:42.050719 # ok 22 Set VL 128
5918 11:15:42.050881 # ok 23 Disabled ZA for VL 128
5919 11:15:42.051043 # ok 24 Data match for VL 128
5920 11:15:42.051195 # ok 25 Set VL 144
5921 11:15:42.051350 # ok 26 # SKIP Disabled ZA for VL 144
5922 11:15:42.051546 # ok 27 # SKIP Get and set data for VL 144
5923 11:15:42.051709 # ok 28 Set VL 160
5924 11:15:42.051867 # ok 29 # SKIP Disabled ZA for VL 160
5925 11:15:42.052015 # ok 30 # SKIP Get and set data for VL 160
5926 11:15:42.052159 # ok 31 Set VL 176
5927 11:15:42.052308 # ok 32 # SKIP Disabled ZA for VL 176
5928 11:15:42.052452 # ok 33 # SKIP Get and set data for VL 176
5929 11:15:42.052595 # ok 34 Set VL 192
5930 11:15:42.052737 # ok 35 # SKIP Disabled ZA for VL 192
5931 11:15:42.052881 # ok 36 # SKIP Get and set data for VL 192
5932 11:15:42.053026 # ok 37 Set VL 208
5933 11:15:42.053170 # ok 38 # SKIP Disabled ZA for VL 208
5934 11:15:42.054587 # ok 39 # SKIP Get and set data for VL 208
5935 11:15:42.055054 # ok 40 Set VL 224
5936 11:15:42.055249 # ok 41 # SKIP Disabled ZA for VL 224
5937 11:15:42.055406 # ok 42 # SKIP Get and set data for VL 224
5938 11:15:42.055541 # ok 43 Set VL 240
5939 11:15:42.055666 # ok 44 # SKIP Disabled ZA for VL 240
5940 11:15:42.055883 # ok 45 # SKIP Get and set data for VL 240
5941 11:15:42.056044 # ok 46 Set VL 256
5942 11:15:42.056190 # ok 47 Disabled ZA for VL 256
5943 11:15:42.056333 # ok 48 Data match for VL 256
5944 11:15:42.056476 # ok 49 Set VL 272
5945 11:15:42.056619 # ok 50 # SKIP Disabled ZA for VL 272
5946 11:15:42.056806 # ok 51 # SKIP Get and set data for VL 272
5947 11:15:42.056979 # ok 52 Set VL 288
5948 11:15:42.057122 # ok 53 # SKIP Disabled ZA for VL 288
5949 11:15:42.057303 # ok 54 # SKIP Get and set data for VL 288
5950 11:15:42.057487 # ok 55 Set VL 304
5951 11:15:42.057674 # ok 56 # SKIP Disabled ZA for VL 304
5952 11:15:42.057859 # ok 57 # SKIP Get and set data for VL 304
5953 11:15:42.058046 # ok 58 Set VL 320
5954 11:15:42.058197 # ok 59 # SKIP Disabled ZA for VL 320
5955 11:15:42.058320 # ok 60 # SKIP Get and set data for VL 320
5956 11:15:42.058436 # ok 61 Set VL 336
5957 11:15:42.058551 # ok 62 # SKIP Disabled ZA for VL 336
5958 11:15:42.058666 # ok 63 # SKIP Get and set data for VL 336
5959 11:15:42.058862 # ok 64 Set VL 352
5960 11:15:42.058991 # ok 65 # SKIP Disabled ZA for VL 352
5961 11:15:42.059108 # ok 66 # SKIP Get and set data for VL 352
5962 11:15:42.059222 # ok 67 Set VL 368
5963 11:15:42.059337 # ok 68 # SKIP Disabled ZA for VL 368
5964 11:15:42.059451 # ok 69 # SKIP Get and set data for VL 368
5965 11:15:42.059564 # ok 70 Set VL 384
5966 11:15:42.059680 # ok 71 # SKIP Disabled ZA for VL 384
5967 11:15:42.059809 # ok 72 # SKIP Get and set data for VL 384
5968 11:15:42.059922 # ok 73 Set VL 400
5969 11:15:42.060034 # ok 74 # SKIP Disabled ZA for VL 400
5970 11:15:42.065567 # ok 75 # SKIP Get and set data for VL 400
5971 11:15:42.066054 # ok 76 Set VL 416
5972 11:15:42.066225 # ok 77 # SKIP Disabled ZA for VL 416
5973 11:15:42.066386 # ok 78 # SKIP Get and set data for VL 416
5974 11:15:42.066517 # ok 79 Set VL 432
5975 11:15:42.066645 # ok 80 # SKIP Disabled ZA for VL 432
5976 11:15:42.066865 # ok 81 # SKIP Get and set data for VL 432
5977 11:15:42.067036 # ok 82 Set VL 448
5978 11:15:42.067251 # ok 83 # SKIP Disabled ZA for VL 448
5979 11:15:42.067414 # ok 84 # SKIP Get and set data for VL 448
5980 11:15:42.067565 # ok 85 Set VL 464
5981 11:15:42.067718 # ok 86 # SKIP Disabled ZA for VL 464
5982 11:15:42.067879 # ok 87 # SKIP Get and set data for VL 464
5983 11:15:42.068003 # ok 88 Set VL 480
5984 11:15:42.068118 # ok 89 # SKIP Disabled ZA for VL 480
5985 11:15:42.068294 # ok 90 # SKIP Get and set data for VL 480
5986 11:15:42.068458 # ok 91 Set VL 496
5987 11:15:42.068615 # ok 92 # SKIP Disabled ZA for VL 496
5988 11:15:42.068778 # ok 93 # SKIP Get and set data for VL 496
5989 11:15:42.068951 # ok 94 Set VL 512
5990 11:15:42.069112 # ok 95 # SKIP Disabled ZA for VL 512
5991 11:15:42.069261 # ok 96 # SKIP Get and set data for VL 512
5992 11:15:42.069410 # ok 97 Set VL 528
5993 11:15:42.069612 # ok 98 # SKIP Disabled ZA for VL 528
5994 11:15:42.069832 # ok 99 # SKIP Get and set data for VL 528
5995 11:15:42.070028 # ok 100 Set VL 544
5996 11:15:42.070211 # ok 101 # SKIP Disabled ZA for VL 544
5997 11:15:42.070387 # ok 102 # SKIP Get and set data for VL 544
5998 11:15:42.070530 # ok 103 Set VL 560
5999 11:15:42.070672 # ok 104 # SKIP Disabled ZA for VL 560
6000 11:15:42.070813 # ok 105 # SKIP Get and set data for VL 560
6001 11:15:42.070954 # ok 106 Set VL 576
6002 11:15:42.071136 # ok 107 # SKIP Disabled ZA for VL 576
6003 11:15:42.071274 # ok 108 # SKIP Get and set data for VL 576
6004 11:15:42.071417 # ok 109 Set VL 592
6005 11:15:42.071559 # ok 110 # SKIP Disabled ZA for VL 592
6006 11:15:42.071702 # ok 111 # SKIP Get and set data for VL 592
6007 11:15:42.071843 # ok 112 Set VL 608
6008 11:15:42.073314 # ok 113 # SKIP Disabled ZA for VL 608
6009 11:15:42.073618 # ok 114 # SKIP Get and set data for VL 608
6010 11:15:42.073732 # ok 115 Set VL 624
6011 11:15:42.073815 # ok 116 # SKIP Disabled ZA for VL 624
6012 11:15:42.073907 # ok 117 # SKIP Get and set data for VL 624
6013 11:15:42.073988 # ok 118 Set VL 640
6014 11:15:42.074069 # ok 119 # SKIP Disabled ZA for VL 640
6015 11:15:42.074160 # ok 120 # SKIP Get and set data for VL 640
6016 11:15:42.074240 # ok 121 Set VL 656
6017 11:15:42.074560 # ok 122 # SKIP Disabled ZA for VL 656
6018 11:15:42.074699 # ok 123 # SKIP Get and set data for VL 656
6019 11:15:42.074995 # ok 124 Set VL 672
6020 11:15:42.088239 # ok 125 # SKIP Disabled ZA for VL 672
6021 11:15:42.088340 # ok 126 # SKIP Get and set data for VL 672
6022 11:15:42.088435 # ok 127 Set VL 688
6023 11:15:42.088514 # ok 128 # SKIP Disabled ZA for VL 688
6024 11:15:42.088604 # ok 129 # SKIP Get and set data for VL 688
6025 11:15:42.088685 # ok 130 Set VL 704
6026 11:15:42.088762 # ok 131 # SKIP Disabled ZA for VL 704
6027 11:15:42.088853 # ok 132 # SKIP Get and set data for VL 704
6028 11:15:42.088931 # ok 133 Set VL 720
6029 11:15:42.089006 # ok 134 # SKIP Disabled ZA for VL 720
6030 11:15:42.089104 # ok 135 # SKIP Get and set data for VL 720
6031 11:15:42.089183 # ok 136 Set VL 736
6032 11:15:42.089260 # ok 137 # SKIP Disabled ZA for VL 736
6033 11:15:42.089352 # ok 138 # SKIP Get and set data for VL 736
6034 11:15:42.089433 # ok 139 Set VL 752
6035 11:15:42.089513 # ok 140 # SKIP Disabled ZA for VL 752
6036 11:15:42.089604 # ok 141 # SKIP Get and set data for VL 752
6037 11:15:42.089692 # ok 142 Set VL 768
6038 11:15:42.089769 # ok 143 # SKIP Disabled ZA for VL 768
6039 11:15:42.089847 # ok 144 # SKIP Get and set data for VL 768
6040 11:15:42.089938 # ok 145 Set VL 784
6041 11:15:42.090019 # ok 146 # SKIP Disabled ZA for VL 784
6042 11:15:42.090096 # ok 147 # SKIP Get and set data for VL 784
6043 11:15:42.090187 # ok 148 Set VL 800
6044 11:15:42.090265 # ok 149 # SKIP Disabled ZA for VL 800
6045 11:15:42.093652 # ok 150 # SKIP Get and set data for VL 800
6046 11:15:42.093754 # ok 151 Set VL 816
6047 11:15:42.094033 # ok 152 # SKIP Disabled ZA for VL 816
6048 11:15:42.094132 # ok 153 # SKIP Get and set data for VL 816
6049 11:15:42.094213 # ok 154 Set VL 832
6050 11:15:42.094291 # ok 155 # SKIP Disabled ZA for VL 832
6051 11:15:42.094381 # ok 156 # SKIP Get and set data for VL 832
6052 11:15:42.094660 # ok 157 Set VL 848
6053 11:15:42.094785 # ok 158 # SKIP Disabled ZA for VL 848
6054 11:15:42.094888 # ok 159 # SKIP Get and set data for VL 848
6055 11:15:42.094973 # ok 160 Set VL 864
6056 11:15:42.095054 # ok 161 # SKIP Disabled ZA for VL 864
6057 11:15:42.095146 # ok 162 # SKIP Get and set data for VL 864
6058 11:15:42.095227 # ok 163 Set VL 880
6059 11:15:42.095305 # ok 164 # SKIP Disabled ZA for VL 880
6060 11:15:42.095398 # ok 165 # SKIP Get and set data for VL 880
6061 11:15:42.095477 # ok 166 Set VL 896
6062 11:15:42.095554 # ok 167 # SKIP Disabled ZA for VL 896
6063 11:15:42.095643 # ok 168 # SKIP Get and set data for VL 896
6064 11:15:42.095721 # ok 169 Set VL 912
6065 11:15:42.095797 # ok 170 # SKIP Disabled ZA for VL 912
6066 11:15:42.095886 # ok 171 # SKIP Get and set data for VL 912
6067 11:15:42.095977 # ok 172 Set VL 928
6068 11:15:42.096055 # ok 173 # SKIP Disabled ZA for VL 928
6069 11:15:42.096145 # ok 174 # SKIP Get and set data for VL 928
6070 11:15:42.096223 # ok 175 Set VL 944
6071 11:15:42.096311 # ok 176 # SKIP Disabled ZA for VL 944
6072 11:15:42.096402 # ok 177 # SKIP Get and set data for VL 944
6073 11:15:42.096480 # ok 178 Set VL 960
6074 11:15:42.096569 # ok 179 # SKIP Disabled ZA for VL 960
6075 11:15:42.096647 # ok 180 # SKIP Get and set data for VL 960
6076 11:15:42.096737 # ok 181 Set VL 976
6077 11:15:42.096815 # ok 182 # SKIP Disabled ZA for VL 976
6078 11:15:42.096904 # ok 183 # SKIP Get and set data for VL 976
6079 11:15:42.096987 # ok 184 Set VL 992
6080 11:15:42.097076 # ok 185 # SKIP Disabled ZA for VL 992
6081 11:15:42.097166 # ok 186 # SKIP Get and set data for VL 992
6082 11:15:42.097256 # ok 187 Set VL 1008
6083 11:15:42.097335 # ok 188 # SKIP Disabled ZA for VL 1008
6084 11:15:42.097424 # ok 189 # SKIP Get and set data for VL 1008
6085 11:15:42.097515 # ok 190 Set VL 1024
6086 11:15:42.097594 # ok 191 # SKIP Disabled ZA for VL 1024
6087 11:15:42.097693 # ok 192 # SKIP Get and set data for VL 1024
6088 11:15:42.097774 # ok 193 Set VL 1040
6089 11:15:42.097863 # ok 194 # SKIP Disabled ZA for VL 1040
6090 11:15:42.098387 # ok 195 # SKIP Get and set data for VL 1040
6091 11:15:42.098487 # ok 196 Set VL 1056
6092 11:15:42.098567 # ok 197 # SKIP Disabled ZA for VL 1056
6093 11:15:42.098645 # ok 198 # SKIP Get and set data for VL 1056
6094 11:15:42.098723 # ok 199 Set VL 1072
6095 11:15:42.098800 # ok 200 # SKIP Disabled ZA for VL 1072
6096 11:15:42.098877 # ok 201 # SKIP Get and set data for VL 1072
6097 11:15:42.104361 # ok 202 Set VL 1088
6098 11:15:42.104466 # ok 203 # SKIP Disabled ZA for VL 1088
6099 11:15:42.104548 # ok 204 # SKIP Get and set data for VL 1088
6100 11:15:42.104640 # ok 205 Set VL 1104
6101 11:15:42.104723 # ok 206 # SKIP Disabled ZA for VL 1104
6102 11:15:42.104800 # ok 207 # SKIP Get and set data for VL 1104
6103 11:15:42.104892 # ok 208 Set VL 1120
6104 11:15:42.104973 # ok 209 # SKIP Disabled ZA for VL 1120
6105 11:15:42.105067 # ok 210 # SKIP Get and set data for VL 1120
6106 11:15:42.105147 # ok 211 Set VL 1136
6107 11:15:42.105237 # ok 212 # SKIP Disabled ZA for VL 1136
6108 11:15:42.105317 # ok 213 # SKIP Get and set data for VL 1136
6109 11:15:42.105407 # ok 214 Set VL 1152
6110 11:15:42.105487 # ok 215 # SKIP Disabled ZA for VL 1152
6111 11:15:42.105578 # ok 216 # SKIP Get and set data for VL 1152
6112 11:15:42.105667 # ok 217 Set VL 1168
6113 11:15:42.105759 # ok 218 # SKIP Disabled ZA for VL 1168
6114 11:15:42.105838 # ok 219 # SKIP Get and set data for VL 1168
6115 11:15:42.105926 # ok 220 Set VL 1184
6116 11:15:42.106005 # ok 221 # SKIP Disabled ZA for VL 1184
6117 11:15:42.106099 # ok 222 # SKIP Get and set data for VL 1184
6118 11:15:42.106177 # ok 223 Set VL 1200
6119 11:15:42.106513 # ok 224 # SKIP Disabled ZA for VL 1200
6120 11:15:42.106807 # ok 225 # SKIP Get and set data for VL 1200
6121 11:15:42.106905 # ok 226 Set VL 1216
6122 11:15:42.106986 # ok 227 # SKIP Disabled ZA for VL 1216
6123 11:15:42.107078 # ok 228 # SKIP Get and set data for VL 1216
6124 11:15:42.107161 # ok 229 Set VL 1232
6125 11:15:42.107252 # ok 230 # SKIP Disabled ZA for VL 1232
6126 11:15:42.107330 # ok 231 # SKIP Get and set data for VL 1232
6127 11:15:42.107406 # ok 232 Set VL 1248
6128 11:15:42.107481 # ok 233 # SKIP Disabled ZA for VL 1248
6129 11:15:42.107571 # ok 234 # SKIP Get and set data for VL 1248
6130 11:15:42.107650 # ok 235 Set VL 1264
6131 11:15:42.107730 # ok 236 # SKIP Disabled ZA for VL 1264
6132 11:15:42.107819 # ok 237 # SKIP Get and set data for VL 1264
6133 11:15:42.107898 # ok 238 Set VL 1280
6134 11:15:42.107987 # ok 239 # SKIP Disabled ZA for VL 1280
6135 11:15:42.108065 # ok 240 # SKIP Get and set data for VL 1280
6136 11:15:42.108155 # ok 241 Set VL 1296
6137 11:15:42.108232 # ok 242 # SKIP Disabled ZA for VL 1296
6138 11:15:42.108320 # ok 243 # SKIP Get and set data for VL 1296
6139 11:15:42.108667 # ok 244 Set VL 1312
6140 11:15:42.108767 # ok 245 # SKIP Disabled ZA for VL 1312
6141 11:15:42.108846 # ok 246 # SKIP Get and set data for VL 1312
6142 11:15:42.108922 # ok 247 Set VL 1328
6143 11:15:42.109012 # ok 248 # SKIP Disabled ZA for VL 1328
6144 11:15:42.109090 # ok 249 # SKIP Get and set data for VL 1328
6145 11:15:42.109166 # ok 250 Set VL 1344
6146 11:15:42.109255 # ok 251 # SKIP Disabled ZA for VL 1344
6147 11:15:42.109333 # ok 252 # SKIP Get and set data for VL 1344
6148 11:15:42.109422 # ok 253 Set VL 1360
6149 11:15:42.109500 # ok 254 # SKIP Disabled ZA for VL 1360
6150 11:15:42.109588 # ok 255 # SKIP Get and set data for VL 1360
6151 11:15:42.109674 # ok 256 Set VL 1376
6152 11:15:42.109751 # ok 257 # SKIP Disabled ZA for VL 1376
6153 11:15:42.109840 # ok 258 # SKIP Get and set data for VL 1376
6154 11:15:42.109919 # ok 259 Set VL 1392
6155 11:15:42.109998 # ok 260 # SKIP Disabled ZA for VL 1392
6156 11:15:42.110090 # ok 261 # SKIP Get and set data for VL 1392
6157 11:15:42.110168 # ok 262 Set VL 1408
6158 11:15:42.120508 # ok 263 # SKIP Disabled ZA for VL 1408
6159 11:15:42.120805 # ok 264 # SKIP Get and set data for VL 1408
6160 11:15:42.120904 # ok 265 Set VL 1424
6161 11:15:42.120985 # ok 266 # SKIP Disabled ZA for VL 1424
6162 11:15:42.121080 # ok 267 # SKIP Get and set data for VL 1424
6163 11:15:42.121161 # ok 268 Set VL 1440
6164 11:15:42.121239 # ok 269 # SKIP Disabled ZA for VL 1440
6165 11:15:42.121331 # ok 270 # SKIP Get and set data for VL 1440
6166 11:15:42.121411 # ok 271 Set VL 1456
6167 11:15:42.121684 # ok 272 # SKIP Disabled ZA for VL 1456
6168 11:15:42.121768 # ok 273 # SKIP Get and set data for VL 1456
6169 11:15:42.121846 # ok 274 Set VL 1472
6170 11:15:42.121923 # ok 275 # SKIP Disabled ZA for VL 1472
6171 11:15:42.122017 # ok 276 # SKIP Get and set data for VL 1472
6172 11:15:42.122098 # ok 277 Set VL 1488
6173 11:15:42.122188 # ok 278 # SKIP Disabled ZA for VL 1488
6174 11:15:42.122706 # ok 279 # SKIP Get and set data for VL 1488
6175 11:15:42.122972 # ok 280 Set VL 1504
6176 11:15:42.123055 # ok 281 # SKIP Disabled ZA for VL 1504
6177 11:15:42.123134 # ok 282 # SKIP Get and set data for VL 1504
6178 11:15:42.123227 # ok 283 Set VL 1520
6179 11:15:42.123306 # ok 284 # SKIP Disabled ZA for VL 1520
6180 11:15:42.123397 # ok 285 # SKIP Get and set data for VL 1520
6181 11:15:42.123477 # ok 286 Set VL 1536
6182 11:15:42.123568 # ok 287 # SKIP Disabled ZA for VL 1536
6183 11:15:42.123646 # ok 288 # SKIP Get and set data for VL 1536
6184 11:15:42.123736 # ok 289 Set VL 1552
6185 11:15:42.123816 # ok 290 # SKIP Disabled ZA for VL 1552
6186 11:15:42.123922 # ok 291 # SKIP Get and set data for VL 1552
6187 11:15:42.124005 # ok 292 Set VL 1568
6188 11:15:42.124107 # ok 293 # SKIP Disabled ZA for VL 1568
6189 11:15:42.124199 # ok 294 # SKIP Get and set data for VL 1568
6190 11:15:42.124290 # ok 295 Set VL 1584
6191 11:15:42.124381 # ok 296 # SKIP Disabled ZA for VL 1584
6192 11:15:42.124472 # ok 297 # SKIP Get and set data for VL 1584
6193 11:15:42.124740 # ok 298 Set VL 1600
6194 11:15:42.124821 # ok 299 # SKIP Disabled ZA for VL 1600
6195 11:15:42.124911 # ok 300 # SKIP Get and set data for VL 1600
6196 11:15:42.124990 # ok 301 Set VL 1616
6197 11:15:42.125078 # ok 302 # SKIP Disabled ZA for VL 1616
6198 11:15:42.125405 # ok 303 # SKIP Get and set data for VL 1616
6199 11:15:42.125614 # ok 304 Set VL 1632
6200 11:15:42.125910 # ok 305 # SKIP Disabled ZA for VL 1632
6201 11:15:42.126161 # ok 306 # SKIP Get and set data for VL 1632
6202 11:15:42.126323 # ok 307 Set VL 1648
6203 11:15:42.126467 # ok 308 # SKIP Disabled ZA for VL 1648
6204 11:15:42.126609 # ok 309 # SKIP Get and set data for VL 1648
6205 11:15:42.126765 # ok 310 Set VL 1664
6206 11:15:42.126906 # ok 311 # SKIP Disabled ZA for VL 1664
6207 11:15:42.127048 # ok 312 # SKIP Get and set data for VL 1664
6208 11:15:42.139839 # ok 313 Set VL 1680
6209 11:15:42.140139 # ok 314 # SKIP Disabled ZA for VL 1680
6210 11:15:42.140554 # ok 315 # SKIP Get and set data for VL 1680
6211 11:15:42.140754 # ok 316 Set VL 1696
6212 11:15:42.140966 # ok 317 # SKIP Disabled ZA for VL 1696
6213 11:15:42.141176 # ok 318 # SKIP Get and set data for VL 1696
6214 11:15:42.141359 # ok 319 Set VL 1712
6215 11:15:42.141533 # ok 320 # SKIP Disabled ZA for VL 1712
6216 11:15:42.141730 # ok 321 # SKIP Get and set data for VL 1712
6217 11:15:42.141974 # ok 322 Set VL 1728
6218 11:15:42.142150 # ok 323 # SKIP Disabled ZA for VL 1728
6219 11:15:42.142322 # ok 324 # SKIP Get and set data for VL 1728
6220 11:15:42.142467 # ok 325 Set VL 1744
6221 11:15:42.142607 # ok 326 # SKIP Disabled ZA for VL 1744
6222 11:15:42.142748 # ok 327 # SKIP Get and set data for VL 1744
6223 11:15:42.142888 # ok 328 Set VL 1760
6224 11:15:42.143028 # ok 329 # SKIP Disabled ZA for VL 1760
6225 11:15:42.143173 # ok 330 # SKIP Get and set data for VL 1760
6226 11:15:42.143314 # ok 331 Set VL 1776
6227 11:15:42.143454 # ok 332 # SKIP Disabled ZA for VL 1776
6228 11:15:42.143595 # ok 333 # SKIP Get and set data for VL 1776
6229 11:15:42.143736 # ok 334 Set VL 1792
6230 11:15:42.143876 # ok 335 # SKIP Disabled ZA for VL 1792
6231 11:15:42.144052 # ok 336 # SKIP Get and set data for VL 1792
6232 11:15:42.144191 # ok 337 Set VL 1808
6233 11:15:42.159849 # ok 338 # SKIP Disabled ZA for VL 1808
6234 11:15:42.160184 # ok 339 # SKIP Get and set data for VL 1808
6235 11:15:42.160643 # ok 340 Set VL 1824
6236 11:15:42.160844 # ok 341 # SKIP Disabled ZA for VL 1824
6237 11:15:42.161058 # ok 342 # SKIP Get and set data for VL 1824
6238 11:15:42.161248 # ok 343 Set VL 1840
6239 11:15:42.161416 # ok 344 # SKIP Disabled ZA for VL 1840
6240 11:15:42.161620 # ok 345 # SKIP Get and set data for VL 1840
6241 11:15:42.161786 # ok 346 Set VL 1856
6242 11:15:42.161908 # ok 347 # SKIP Disabled ZA for VL 1856
6243 11:15:42.162024 # ok 348 # SKIP Get and set data for VL 1856
6244 11:15:42.162141 # ok 349 Set VL 1872
6245 11:15:42.162254 # ok 350 # SKIP Disabled ZA for VL 1872
6246 11:15:42.162368 # ok 351 # SKIP Get and set data for VL 1872
6247 11:15:42.162481 # ok 352 Set VL 1888
6248 11:15:42.162593 # ok 353 # SKIP Disabled ZA for VL 1888
6249 11:15:42.162707 # ok 354 # SKIP Get and set data for VL 1888
6250 11:15:42.162821 # ok 355 Set VL 1904
6251 11:15:42.162959 # ok 356 # SKIP Disabled ZA for VL 1904
6252 11:15:42.163080 # ok 357 # SKIP Get and set data for VL 1904
6253 11:15:42.163194 # ok 358 Set VL 1920
6254 11:15:42.209182 # ok 359 # SKIP Disabled ZA for VL 1920
6255 11:15:42.209487 # ok 360 # SKIP Get and set data for VL 1920
6256 11:15:42.209668 # ok 361 Set VL 1936
6257 11:15:42.209836 # ok 362 # SKIP Disabled ZA for VL 1936
6258 11:15:42.210024 # ok 363 # SKIP Get and set data for VL 1936
6259 11:15:42.210153 # ok 364 Set VL 1952
6260 11:15:42.210268 # ok 365 # SKIP Disabled ZA for VL 1952
6261 11:15:42.210382 # ok 366 # SKIP Get and set data for VL 1952
6262 11:15:42.210495 # ok 367 Set VL 1968
6263 11:15:42.210609 # ok 368 # SKIP Disabled ZA for VL 1968
6264 11:15:42.210721 # ok 369 # SKIP Get and set data for VL 1968
6265 11:15:42.210845 # ok 370 Set VL 1984
6266 11:15:42.211016 # ok 371 # SKIP Disabled ZA for VL 1984
6267 11:15:42.211196 # ok 372 # SKIP Get and set data for VL 1984
6268 11:15:42.228718 # ok 373 Set VL 2000
6269 11:15:42.229177 # ok 374 # SKIP Disabled ZA for VL 2000
6270 11:15:42.229282 # ok 375 # SKIP Get and set data for VL 2000
6271 11:15:42.229373 # ok 376 Set VL 2016
6272 11:15:42.229460 # ok 377 # SKIP Disabled ZA for VL 2016
6273 11:15:42.229545 # ok 378 # SKIP Get and set data for VL 2016
6274 11:15:42.229632 # ok 379 Set VL 2032
6275 11:15:42.229741 # ok 380 # SKIP Disabled ZA for VL 2032
6276 11:15:42.229828 # ok 381 # SKIP Get and set data for VL 2032
6277 11:15:42.229913 # ok 382 Set VL 2048
6278 11:15:42.229998 # ok 383 # SKIP Disabled ZA for VL 2048
6279 11:15:42.230079 # ok 384 # SKIP Get and set data for VL 2048
6280 11:15:42.230172 # ok 385 Set VL 2064
6281 11:15:42.230249 # ok 386 # SKIP Disabled ZA for VL 2064
6282 11:15:42.230323 # ok 387 # SKIP Get and set data for VL 2064
6283 11:15:42.230395 # ok 388 Set VL 2080
6284 11:15:42.241351 # ok 389 # SKIP Disabled ZA for VL 2080
6285 11:15:42.241800 # ok 390 # SKIP Get and set data for VL 2080
6286 11:15:42.241897 # ok 391 Set VL 2096
6287 11:15:42.241985 # ok 392 # SKIP Disabled ZA for VL 2096
6288 11:15:42.242067 # ok 393 # SKIP Get and set data for VL 2096
6289 11:15:42.242150 # ok 394 Set VL 2112
6290 11:15:42.242232 # ok 395 # SKIP Disabled ZA for VL 2112
6291 11:15:42.242306 # ok 396 # SKIP Get and set data for VL 2112
6292 11:15:42.242396 # ok 397 Set VL 2128
6293 11:15:42.242470 # ok 398 # SKIP Disabled ZA for VL 2128
6294 11:15:42.242544 # ok 399 # SKIP Get and set data for VL 2128
6295 11:15:42.249490 # ok 400 Set VL 2144
6296 11:15:42.249955 # ok 401 # SKIP Disabled ZA for VL 2144
6297 11:15:42.250058 # ok 402 # SKIP Get and set data for VL 2144
6298 11:15:42.250142 # ok 403 Set VL 2160
6299 11:15:42.250219 # ok 404 # SKIP Disabled ZA for VL 2160
6300 11:15:42.250310 # ok 405 # SKIP Get and set data for VL 2160
6301 11:15:42.250386 # ok 406 Set VL 2176
6302 11:15:42.251553 # ok 407 # SKIP Disabled ZA for VL 2176
6303 11:15:42.251855 # ok 408 # SKIP Get and set data for VL 2176
6304 11:15:42.252012 # ok 409 Set VL 2192
6305 11:15:42.252195 # ok 410 # SKIP Disabled ZA for VL 2192
6306 11:15:42.252335 # ok 411 # SKIP Get and set data for VL 2192
6307 11:15:42.252477 # ok 412 Set VL 2208
6308 11:15:42.252619 # ok 413 # SKIP Disabled ZA for VL 2208
6309 11:15:42.252799 # ok 414 # SKIP Get and set data for VL 2208
6310 11:15:42.252978 # ok 415 Set VL 2224
6311 11:15:42.253164 # ok 416 # SKIP Disabled ZA for VL 2224
6312 11:15:42.253300 # ok 417 # SKIP Get and set data for VL 2224
6313 11:15:42.253441 # ok 418 Set VL 2240
6314 11:15:42.253582 # ok 419 # SKIP Disabled ZA for VL 2240
6315 11:15:42.253740 # ok 420 # SKIP Get and set data for VL 2240
6316 11:15:42.253883 # ok 421 Set VL 2256
6317 11:15:42.254061 # ok 422 # SKIP Disabled ZA for VL 2256
6318 11:15:42.254232 # ok 423 # SKIP Get and set data for VL 2256
6319 11:15:42.254379 # ok 424 Set VL 2272
6320 11:15:42.254518 # ok 425 # SKIP Disabled ZA for VL 2272
6321 11:15:42.254660 # ok 426 # SKIP Get and set data for VL 2272
6322 11:15:42.254800 # ok 427 Set VL 2288
6323 11:15:42.254978 # ok 428 # SKIP Disabled ZA for VL 2288
6324 11:15:42.255112 # ok 429 # SKIP Get and set data for VL 2288
6325 11:15:42.255253 # ok 430 Set VL 2304
6326 11:15:42.255396 # ok 431 # SKIP Disabled ZA for VL 2304
6327 11:15:42.255538 # ok 432 # SKIP Get and set data for VL 2304
6328 11:15:42.255677 # ok 433 Set VL 2320
6329 11:15:42.255817 # ok 434 # SKIP Disabled ZA for VL 2320
6330 11:15:42.255957 # ok 435 # SKIP Get and set data for VL 2320
6331 11:15:42.256097 # ok 436 Set VL 2336
6332 11:15:42.256237 # ok 437 # SKIP Disabled ZA for VL 2336
6333 11:15:42.256379 # ok 438 # SKIP Get and set data for VL 2336
6334 11:15:42.256519 # ok 439 Set VL 2352
6335 11:15:42.259242 # ok 440 # SKIP Disabled ZA for VL 2352
6336 11:15:42.259618 # ok 441 # SKIP Get and set data for VL 2352
6337 11:15:42.259729 # ok 442 Set VL 2368
6338 11:15:42.259827 # ok 443 # SKIP Disabled ZA for VL 2368
6339 11:15:42.259921 # ok 444 # SKIP Get and set data for VL 2368
6340 11:15:42.260014 # ok 445 Set VL 2384
6341 11:15:42.260098 # ok 446 # SKIP Disabled ZA for VL 2384
6342 11:15:42.260196 # ok 447 # SKIP Get and set data for VL 2384
6343 11:15:42.260287 # ok 448 Set VL 2400
6344 11:15:42.260376 # ok 449 # SKIP Disabled ZA for VL 2400
6345 11:15:42.260462 # ok 450 # SKIP Get and set data for VL 2400
6346 11:15:42.260542 # ok 451 Set VL 2416
6347 11:15:42.260618 # ok 452 # SKIP Disabled ZA for VL 2416
6348 11:15:42.260717 # ok 453 # SKIP Get and set data for VL 2416
6349 11:15:42.260808 # ok 454 Set VL 2432
6350 11:15:42.260899 # ok 455 # SKIP Disabled ZA for VL 2432
6351 11:15:42.260990 # ok 456 # SKIP Get and set data for VL 2432
6352 11:15:42.261081 # ok 457 Set VL 2448
6353 11:15:42.261171 # ok 458 # SKIP Disabled ZA for VL 2448
6354 11:15:42.261253 # ok 459 # SKIP Get and set data for VL 2448
6355 11:15:42.261350 # ok 460 Set VL 2464
6356 11:15:42.261431 # ok 461 # SKIP Disabled ZA for VL 2464
6357 11:15:42.261508 # ok 462 # SKIP Get and set data for VL 2464
6358 11:15:42.261592 # ok 463 Set VL 2480
6359 11:15:42.261689 # ok 464 # SKIP Disabled ZA for VL 2480
6360 11:15:42.261785 # ok 465 # SKIP Get and set data for VL 2480
6361 11:15:42.261878 # ok 466 Set VL 2496
6362 11:15:42.261969 # ok 467 # SKIP Disabled ZA for VL 2496
6363 11:15:42.262059 # ok 468 # SKIP Get and set data for VL 2496
6364 11:15:42.262152 # ok 469 Set VL 2512
6365 11:15:42.262243 # ok 470 # SKIP Disabled ZA for VL 2512
6366 11:15:42.262352 # ok 471 # SKIP Get and set data for VL 2512
6367 11:15:42.262435 # ok 472 Set VL 2528
6368 11:15:42.262512 # ok 473 # SKIP Disabled ZA for VL 2528
6369 11:15:42.262589 # ok 474 # SKIP Get and set data for VL 2528
6370 11:15:42.262667 # ok 475 Set VL 2544
6371 11:15:42.262752 # ok 476 # SKIP Disabled ZA for VL 2544
6372 11:15:42.262833 # ok 477 # SKIP Get and set data for VL 2544
6373 11:15:42.262916 # ok 478 Set VL 2560
6374 11:15:42.263009 # ok 479 # SKIP Disabled ZA for VL 2560
6375 11:15:42.263102 # ok 480 # SKIP Get and set data for VL 2560
6376 11:15:42.267404 # ok 481 Set VL 2576
6377 11:15:42.267853 # ok 482 # SKIP Disabled ZA for VL 2576
6378 11:15:42.267956 # ok 483 # SKIP Get and set data for VL 2576
6379 11:15:42.268039 # ok 484 Set VL 2592
6380 11:15:42.268120 # ok 485 # SKIP Disabled ZA for VL 2592
6381 11:15:42.268225 # ok 486 # SKIP Get and set data for VL 2592
6382 11:15:42.268512 # ok 487 Set VL 2608
6383 11:15:42.268619 # ok 488 # SKIP Disabled ZA for VL 2608
6384 11:15:42.268770 # ok 489 # SKIP Get and set data for VL 2608
6385 11:15:42.268861 # ok 490 Set VL 2624
6386 11:15:42.268939 # ok 491 # SKIP Disabled ZA for VL 2624
6387 11:15:42.269020 # ok 492 # SKIP Get and set data for VL 2624
6388 11:15:42.269102 # ok 493 Set VL 2640
6389 11:15:42.269196 # ok 494 # SKIP Disabled ZA for VL 2640
6390 11:15:42.269280 # ok 495 # SKIP Get and set data for VL 2640
6391 11:15:42.269356 # ok 496 Set VL 2656
6392 11:15:42.269432 # ok 497 # SKIP Disabled ZA for VL 2656
6393 11:15:42.269513 # ok 498 # SKIP Get and set data for VL 2656
6394 11:15:42.269594 # ok 499 Set VL 2672
6395 11:15:42.269682 # ok 500 # SKIP Disabled ZA for VL 2672
6396 11:15:42.269782 # ok 501 # SKIP Get and set data for VL 2672
6397 11:15:42.269862 # ok 502 Set VL 2688
6398 11:15:42.269939 # ok 503 # SKIP Disabled ZA for VL 2688
6399 11:15:42.270022 # ok 504 # SKIP Get and set data for VL 2688
6400 11:15:42.270331 # ok 505 Set VL 2704
6401 11:15:42.270486 # ok 506 # SKIP Disabled ZA for VL 2704
6402 11:15:42.270606 # ok 507 # SKIP Get and set data for VL 2704
6403 11:15:42.270777 # ok 508 Set VL 2720
6404 11:15:42.275829 # ok 509 # SKIP Disabled ZA for VL 2720
6405 11:15:42.276436 # ok 510 # SKIP Get and set data for VL 2720
6406 11:15:42.276597 # ok 511 Set VL 2736
6407 11:15:42.276785 # ok 512 # SKIP Disabled ZA for VL 2736
6408 11:15:42.276976 # ok 513 # SKIP Get and set data for VL 2736
6409 11:15:42.277197 # ok 514 Set VL 2752
6410 11:15:42.277317 # ok 515 # SKIP Disabled ZA for VL 2752
6411 11:15:42.277410 # ok 516 # SKIP Get and set data for VL 2752
6412 11:15:42.277504 # ok 517 Set VL 2768
6413 11:15:42.277594 # ok 518 # SKIP Disabled ZA for VL 2768
6414 11:15:42.277712 # ok 519 # SKIP Get and set data for VL 2768
6415 11:15:42.277840 # ok 520 Set VL 2784
6416 11:15:42.277942 # ok 521 # SKIP Disabled ZA for VL 2784
6417 11:15:42.278074 # ok 522 # SKIP Get and set data for VL 2784
6418 11:15:42.278201 # ok 523 Set VL 2800
6419 11:15:42.278311 # ok 524 # SKIP Disabled ZA for VL 2800
6420 11:15:42.278430 # ok 525 # SKIP Get and set data for VL 2800
6421 11:15:42.278525 # ok 526 Set VL 2816
6422 11:15:42.278618 # ok 527 # SKIP Disabled ZA for VL 2816
6423 11:15:42.278738 # ok 528 # SKIP Get and set data for VL 2816
6424 11:15:42.278858 # ok 529 Set VL 2832
6425 11:15:42.278953 # ok 530 # SKIP Disabled ZA for VL 2832
6426 11:15:42.279047 # ok 531 # SKIP Get and set data for VL 2832
6427 11:15:42.279167 # ok 532 Set VL 2848
6428 11:15:42.279330 # ok 533 # SKIP Disabled ZA for VL 2848
6429 11:15:42.279473 # ok 534 # SKIP Get and set data for VL 2848
6430 11:15:42.279603 # ok 535 Set VL 2864
6431 11:15:42.279764 # ok 536 # SKIP Disabled ZA for VL 2864
6432 11:15:42.279927 # ok 537 # SKIP Get and set data for VL 2864
6433 11:15:42.280066 # ok 538 Set VL 2880
6434 11:15:42.280201 # ok 539 # SKIP Disabled ZA for VL 2880
6435 11:15:42.280335 # ok 540 # SKIP Get and set data for VL 2880
6436 11:15:42.280502 # ok 541 Set VL 2896
6437 11:15:42.280645 # ok 542 # SKIP Disabled ZA for VL 2896
6438 11:15:42.280809 # ok 543 # SKIP Get and set data for VL 2896
6439 11:15:42.280944 # ok 544 Set VL 2912
6440 11:15:42.281077 # ok 545 # SKIP Disabled ZA for VL 2912
6441 11:15:42.281243 # ok 546 # SKIP Get and set data for VL 2912
6442 11:15:42.281373 # ok 547 Set VL 2928
6443 11:15:42.281505 # ok 548 # SKIP Disabled ZA for VL 2928
6444 11:15:42.281641 # ok 549 # SKIP Get and set data for VL 2928
6445 11:15:42.281823 # ok 550 Set VL 2944
6446 11:15:42.281971 # ok 551 # SKIP Disabled ZA for VL 2944
6447 11:15:42.282141 # ok 552 # SKIP Get and set data for VL 2944
6448 11:15:42.282292 # ok 553 Set VL 2960
6449 11:15:42.282433 # ok 554 # SKIP Disabled ZA for VL 2960
6450 11:15:42.282572 # ok 555 # SKIP Get and set data for VL 2960
6451 11:15:42.282711 # ok 556 Set VL 2976
6452 11:15:42.282849 # ok 557 # SKIP Disabled ZA for VL 2976
6453 11:15:42.282994 # ok 558 # SKIP Get and set data for VL 2976
6454 11:15:42.291656 # ok 559 Set VL 2992
6455 11:15:42.292190 # ok 560 # SKIP Disabled ZA for VL 2992
6456 11:15:42.292350 # ok 561 # SKIP Get and set data for VL 2992
6457 11:15:42.292488 # ok 562 Set VL 3008
6458 11:15:42.292618 # ok 563 # SKIP Disabled ZA for VL 3008
6459 11:15:42.292750 # ok 564 # SKIP Get and set data for VL 3008
6460 11:15:42.292850 # ok 565 Set VL 3024
6461 11:15:42.292962 # ok 566 # SKIP Disabled ZA for VL 3024
6462 11:15:42.293054 # ok 567 # SKIP Get and set data for VL 3024
6463 11:15:42.293143 # ok 568 Set VL 3040
6464 11:15:42.293231 # ok 569 # SKIP Disabled ZA for VL 3040
6465 11:15:42.293321 # ok 570 # SKIP Get and set data for VL 3040
6466 11:15:42.293410 # ok 571 Set VL 3056
6467 11:15:42.293497 # ok 572 # SKIP Disabled ZA for VL 3056
6468 11:15:42.293584 # ok 573 # SKIP Get and set data for VL 3056
6469 11:15:42.293698 # ok 574 Set VL 3072
6470 11:15:42.293840 # ok 575 # SKIP Disabled ZA for VL 3072
6471 11:15:42.293935 # ok 576 # SKIP Get and set data for VL 3072
6472 11:15:42.294094 # ok 577 Set VL 3088
6473 11:15:42.294239 # ok 578 # SKIP Disabled ZA for VL 3088
6474 11:15:42.294358 # ok 579 # SKIP Get and set data for VL 3088
6475 11:15:42.294449 # ok 580 Set VL 3104
6476 11:15:42.294536 # ok 581 # SKIP Disabled ZA for VL 3104
6477 11:15:42.294645 # ok 582 # SKIP Get and set data for VL 3104
6478 11:15:42.294792 # ok 583 Set VL 3120
6479 11:15:42.297632 # ok 584 # SKIP Disabled ZA for VL 3120
6480 11:15:42.298018 # ok 585 # SKIP Get and set data for VL 3120
6481 11:15:42.298104 # ok 586 Set VL 3136
6482 11:15:42.298194 # ok 587 # SKIP Disabled ZA for VL 3136
6483 11:15:42.307938 # ok 588 # SKIP Get and set data for VL 3136
6484 11:15:42.308363 # ok 589 Set VL 3152
6485 11:15:42.309403 # ok 590 # SKIP Disabled ZA for VL 3152
6486 11:15:42.309703 # ok 591 # SKIP Get and set data for VL 3152
6487 11:15:42.309812 # ok 592 Set VL 3168
6488 11:15:42.309918 # ok 593 # SKIP Disabled ZA for VL 3168
6489 11:15:42.310002 # ok 594 # SKIP Get and set data for VL 3168
6490 11:15:42.310081 # ok 595 Set VL 3184
6491 11:15:42.310176 # ok 596 # SKIP Disabled ZA for VL 3184
6492 11:15:42.316890 # ok 597 # SKIP Get and set data for VL 3184
6493 11:15:42.317325 # ok 598 Set VL 3200
6494 11:15:42.317417 # ok 599 # SKIP Disabled ZA for VL 3200
6495 11:15:42.317500 # ok 600 # SKIP Get and set data for VL 3200
6496 11:15:42.317587 # ok 601 Set VL 3216
6497 11:15:42.317678 # ok 602 # SKIP Disabled ZA for VL 3216
6498 11:15:42.317783 # ok 603 # SKIP Get and set data for VL 3216
6499 11:15:42.317866 # ok 604 Set VL 3232
6500 11:15:42.317945 # ok 605 # SKIP Disabled ZA for VL 3232
6501 11:15:42.318023 # ok 606 # SKIP Get and set data for VL 3232
6502 11:15:42.318101 # ok 607 Set VL 3248
6503 11:15:42.318178 # ok 608 # SKIP Disabled ZA for VL 3248
6504 11:15:42.318271 # ok 609 # SKIP Get and set data for VL 3248
6505 11:15:42.318352 # ok 610 Set VL 3264
6506 11:15:42.318433 # ok 611 # SKIP Disabled ZA for VL 3264
6507 11:15:42.318515 # ok 612 # SKIP Get and set data for VL 3264
6508 11:15:42.318602 # ok 613 Set VL 3280
6509 11:15:42.318876 # ok 614 # SKIP Disabled ZA for VL 3280
6510 11:15:42.318965 # ok 615 # SKIP Get and set data for VL 3280
6511 11:15:42.319044 # ok 616 Set VL 3296
6512 11:15:42.319138 # ok 617 # SKIP Disabled ZA for VL 3296
6513 11:15:42.319219 # ok 618 # SKIP Get and set data for VL 3296
6514 11:15:42.319306 # ok 619 Set VL 3312
6515 11:15:42.319387 # ok 620 # SKIP Disabled ZA for VL 3312
6516 11:15:42.319654 # ok 621 # SKIP Get and set data for VL 3312
6517 11:15:42.319743 # ok 622 Set VL 3328
6518 11:15:42.319824 # ok 623 # SKIP Disabled ZA for VL 3328
6519 11:15:42.319920 # ok 624 # SKIP Get and set data for VL 3328
6520 11:15:42.320007 # ok 625 Set VL 3344
6521 11:15:42.320087 # ok 626 # SKIP Disabled ZA for VL 3344
6522 11:15:42.320164 # ok 627 # SKIP Get and set data for VL 3344
6523 11:15:42.320241 # ok 628 Set VL 3360
6524 11:15:42.320320 # ok 629 # SKIP Disabled ZA for VL 3360
6525 11:15:42.320398 # ok 630 # SKIP Get and set data for VL 3360
6526 11:15:42.320492 # ok 631 Set VL 3376
6527 11:15:42.320574 # ok 632 # SKIP Disabled ZA for VL 3376
6528 11:15:42.320654 # ok 633 # SKIP Get and set data for VL 3376
6529 11:15:42.320742 # ok 634 Set VL 3392
6530 11:15:42.320832 # ok 635 # SKIP Disabled ZA for VL 3392
6531 11:15:42.320924 # ok 636 # SKIP Get and set data for VL 3392
6532 11:15:42.321032 # ok 637 Set VL 3408
6533 11:15:42.321113 # ok 638 # SKIP Disabled ZA for VL 3408
6534 11:15:42.321190 # ok 639 # SKIP Get and set data for VL 3408
6535 11:15:42.321266 # ok 640 Set VL 3424
6536 11:15:42.321344 # ok 641 # SKIP Disabled ZA for VL 3424
6537 11:15:42.321420 # ok 642 # SKIP Get and set data for VL 3424
6538 11:15:42.321496 # ok 643 Set VL 3440
6539 11:15:42.321572 # ok 644 # SKIP Disabled ZA for VL 3440
6540 11:15:42.321657 # ok 645 # SKIP Get and set data for VL 3440
6541 11:15:42.321745 # ok 646 Set VL 3456
6542 11:15:42.321855 # ok 647 # SKIP Disabled ZA for VL 3456
6543 11:15:42.321936 # ok 648 # SKIP Get and set data for VL 3456
6544 11:15:42.322013 # ok 649 Set VL 3472
6545 11:15:42.322089 # ok 650 # SKIP Disabled ZA for VL 3472
6546 11:15:42.322166 # ok 651 # SKIP Get and set data for VL 3472
6547 11:15:42.322243 # ok 652 Set VL 3488
6548 11:15:42.322319 # ok 653 # SKIP Disabled ZA for VL 3488
6549 11:15:42.322394 # ok 654 # SKIP Get and set data for VL 3488
6550 11:15:42.322475 # ok 655 Set VL 3504
6551 11:15:42.322559 # ok 656 # SKIP Disabled ZA for VL 3504
6552 11:15:42.322637 # ok 657 # SKIP Get and set data for VL 3504
6553 11:15:42.322719 # ok 658 Set VL 3520
6554 11:15:42.322816 # ok 659 # SKIP Disabled ZA for VL 3520
6555 11:15:42.322896 # ok 660 # SKIP Get and set data for VL 3520
6556 11:15:42.322972 # ok 661 Set VL 3536
6557 11:15:42.327351 # ok 662 # SKIP Disabled ZA for VL 3536
6558 11:15:42.327557 # ok 663 # SKIP Get and set data for VL 3536
6559 11:15:42.327645 # ok 664 Set VL 3552
6560 11:15:42.327730 # ok 665 # SKIP Disabled ZA for VL 3552
6561 11:15:42.327834 # ok 666 # SKIP Get and set data for VL 3552
6562 11:15:42.327914 # ok 667 Set VL 3568
6563 11:15:42.327992 # ok 668 # SKIP Disabled ZA for VL 3568
6564 11:15:42.328071 # ok 669 # SKIP Get and set data for VL 3568
6565 11:15:42.328149 # ok 670 Set VL 3584
6566 11:15:42.328241 # ok 671 # SKIP Disabled ZA for VL 3584
6567 11:15:42.328328 # ok 672 # SKIP Get and set data for VL 3584
6568 11:15:42.328415 # ok 673 Set VL 3600
6569 11:15:42.328493 # ok 674 # SKIP Disabled ZA for VL 3600
6570 11:15:42.328590 # ok 675 # SKIP Get and set data for VL 3600
6571 11:15:42.328672 # ok 676 Set VL 3616
6572 11:15:42.328755 # ok 677 # SKIP Disabled ZA for VL 3616
6573 11:15:42.328833 # ok 678 # SKIP Get and set data for VL 3616
6574 11:15:42.328910 # ok 679 Set VL 3632
6575 11:15:42.328985 # ok 680 # SKIP Disabled ZA for VL 3632
6576 11:15:42.329077 # ok 681 # SKIP Get and set data for VL 3632
6577 11:15:42.329162 # ok 682 Set VL 3648
6578 11:15:42.329242 # ok 683 # SKIP Disabled ZA for VL 3648
6579 11:15:42.329319 # ok 684 # SKIP Get and set data for VL 3648
6580 11:15:42.329400 # ok 685 Set VL 3664
6581 11:15:42.329491 # ok 686 # SKIP Disabled ZA for VL 3664
6582 11:15:42.329570 # ok 687 # SKIP Get and set data for VL 3664
6583 11:15:42.329655 # ok 688 Set VL 3680
6584 11:15:42.329738 # ok 689 # SKIP Disabled ZA for VL 3680
6585 11:15:42.329821 # ok 690 # SKIP Get and set data for VL 3680
6586 11:15:42.329903 # ok 691 Set VL 3696
6587 11:15:42.330002 # ok 692 # SKIP Disabled ZA for VL 3696
6588 11:15:42.330093 # ok 693 # SKIP Get and set data for VL 3696
6589 11:15:42.330174 # ok 694 Set VL 3712
6590 11:15:42.330250 # ok 695 # SKIP Disabled ZA for VL 3712
6591 11:15:42.335589 # ok 696 # SKIP Get and set data for VL 3712
6592 11:15:42.336054 # ok 697 Set VL 3728
6593 11:15:42.336140 # ok 698 # SKIP Disabled ZA for VL 3728
6594 11:15:42.336221 # ok 699 # SKIP Get and set data for VL 3728
6595 11:15:42.336310 # ok 700 Set VL 3744
6596 11:15:42.336404 # ok 701 # SKIP Disabled ZA for VL 3744
6597 11:15:42.336512 # ok 702 # SKIP Get and set data for VL 3744
6598 11:15:42.336607 # ok 703 Set VL 3760
6599 11:15:42.336719 # ok 704 # SKIP Disabled ZA for VL 3760
6600 11:15:42.336823 # ok 705 # SKIP Get and set data for VL 3760
6601 11:15:42.336914 # ok 706 Set VL 3776
6602 11:15:42.337031 # ok 707 # SKIP Disabled ZA for VL 3776
6603 11:15:42.337128 # ok 708 # SKIP Get and set data for VL 3776
6604 11:15:42.337219 # ok 709 Set VL 3792
6605 11:15:42.337318 # ok 710 # SKIP Disabled ZA for VL 3792
6606 11:15:42.337406 # ok 711 # SKIP Get and set data for VL 3792
6607 11:15:42.337508 # ok 712 Set VL 3808
6608 11:15:42.337616 # ok 713 # SKIP Disabled ZA for VL 3808
6609 11:15:42.337757 # ok 714 # SKIP Get and set data for VL 3808
6610 11:15:42.337850 # ok 715 Set VL 3824
6611 11:15:42.337941 # ok 716 # SKIP Disabled ZA for VL 3824
6612 11:15:42.338048 # ok 717 # SKIP Get and set data for VL 3824
6613 11:15:42.338123 # ok 718 Set VL 3840
6614 11:15:42.338185 # ok 719 # SKIP Disabled ZA for VL 3840
6615 11:15:42.338260 # ok 720 # SKIP Get and set data for VL 3840
6616 11:15:42.338323 # ok 721 Set VL 3856
6617 11:15:42.338396 # ok 722 # SKIP Disabled ZA for VL 3856
6618 11:15:42.338468 # ok 723 # SKIP Get and set data for VL 3856
6619 11:15:42.338529 # ok 724 Set VL 3872
6620 11:15:42.338763 # ok 725 # SKIP Disabled ZA for VL 3872
6621 11:15:42.338899 # ok 726 # SKIP Get and set data for VL 3872
6622 11:15:42.338992 # ok 727 Set VL 3888
6623 11:15:42.339095 # ok 728 # SKIP Disabled ZA for VL 3888
6624 11:15:42.339193 # ok 729 # SKIP Get and set data for VL 3888
6625 11:15:42.339297 # ok 730 Set VL 3904
6626 11:15:42.339394 # ok 731 # SKIP Disabled ZA for VL 3904
6627 11:15:42.339470 # ok 732 # SKIP Get and set data for VL 3904
6628 11:15:42.339557 # ok 733 Set VL 3920
6629 11:15:42.339622 # ok 734 # SKIP Disabled ZA for VL 3920
6630 11:15:42.339726 # ok 735 # SKIP Get and set data for VL 3920
6631 11:15:42.339824 # ok 736 Set VL 3936
6632 11:15:42.339931 # ok 737 # SKIP Disabled ZA for VL 3936
6633 11:15:42.340004 # ok 738 # SKIP Get and set data for VL 3936
6634 11:15:42.340105 # ok 739 Set VL 3952
6635 11:15:42.340187 # ok 740 # SKIP Disabled ZA for VL 3952
6636 11:15:42.340265 # ok 741 # SKIP Get and set data for VL 3952
6637 11:15:42.340331 # ok 742 Set VL 3968
6638 11:15:42.340393 # ok 743 # SKIP Disabled ZA for VL 3968
6639 11:15:42.340466 # ok 744 # SKIP Get and set data for VL 3968
6640 11:15:42.340530 # ok 745 Set VL 3984
6641 11:15:42.340603 # ok 746 # SKIP Disabled ZA for VL 3984
6642 11:15:42.340669 # ok 747 # SKIP Get and set data for VL 3984
6643 11:15:42.340765 # ok 748 Set VL 4000
6644 11:15:42.340858 # ok 749 # SKIP Disabled ZA for VL 4000
6645 11:15:42.340924 # ok 750 # SKIP Get and set data for VL 4000
6646 11:15:42.340987 # ok 751 Set VL 4016
6647 11:15:42.341047 # ok 752 # SKIP Disabled ZA for VL 4016
6648 11:15:42.341122 # ok 753 # SKIP Get and set data for VL 4016
6649 11:15:42.341188 # ok 754 Set VL 4032
6650 11:15:42.341251 # ok 755 # SKIP Disabled ZA for VL 4032
6651 11:15:42.341312 # ok 756 # SKIP Get and set data for VL 4032
6652 11:15:42.341386 # ok 757 Set VL 4048
6653 11:15:42.341452 # ok 758 # SKIP Disabled ZA for VL 4048
6654 11:15:42.341514 # ok 759 # SKIP Get and set data for VL 4048
6655 11:15:42.341587 # ok 760 Set VL 4064
6656 11:15:42.341658 # ok 761 # SKIP Disabled ZA for VL 4064
6657 11:15:42.341751 # ok 762 # SKIP Get and set data for VL 4064
6658 11:15:42.341845 # ok 763 Set VL 4080
6659 11:15:42.341933 # ok 764 # SKIP Disabled ZA for VL 4080
6660 11:15:42.342020 # ok 765 # SKIP Get and set data for VL 4080
6661 11:15:42.342091 # ok 766 Set VL 4096
6662 11:15:42.342189 # ok 767 # SKIP Disabled ZA for VL 4096
6663 11:15:42.342258 # ok 768 # SKIP Get and set data for VL 4096
6664 11:15:42.342320 # ok 769 Set VL 4112
6665 11:15:42.348898 # ok 770 # SKIP Disabled ZA for VL 4112
6666 11:15:42.349120 # ok 771 # SKIP Get and set data for VL 4112
6667 11:15:42.349193 # ok 772 Set VL 4128
6668 11:15:42.349474 # ok 773 # SKIP Disabled ZA for VL 4128
6669 11:15:42.349582 # ok 774 # SKIP Get and set data for VL 4128
6670 11:15:42.349681 # ok 775 Set VL 4144
6671 11:15:42.349767 # ok 776 # SKIP Disabled ZA for VL 4144
6672 11:15:42.349855 # ok 777 # SKIP Get and set data for VL 4144
6673 11:15:42.349939 # ok 778 Set VL 4160
6674 11:15:42.350020 # ok 779 # SKIP Disabled ZA for VL 4160
6675 11:15:42.350112 # ok 780 # SKIP Get and set data for VL 4160
6676 11:15:42.350188 # ok 781 Set VL 4176
6677 11:15:42.350259 # ok 782 # SKIP Disabled ZA for VL 4176
6678 11:15:42.350330 # ok 783 # SKIP Get and set data for VL 4176
6679 11:15:42.350404 # ok 784 Set VL 4192
6680 11:15:42.355643 # ok 785 # SKIP Disabled ZA for VL 4192
6681 11:15:42.356114 # ok 786 # SKIP Get and set data for VL 4192
6682 11:15:42.356218 # ok 787 Set VL 4208
6683 11:15:42.356300 # ok 788 # SKIP Disabled ZA for VL 4208
6684 11:15:42.356377 # ok 789 # SKIP Get and set data for VL 4208
6685 11:15:42.356453 # ok 790 Set VL 4224
6686 11:15:42.356529 # ok 791 # SKIP Disabled ZA for VL 4224
6687 11:15:42.356621 # ok 792 # SKIP Get and set data for VL 4224
6688 11:15:42.356768 # ok 793 Set VL 4240
6689 11:15:42.356862 # ok 794 # SKIP Disabled ZA for VL 4240
6690 11:15:42.356947 # ok 795 # SKIP Get and set data for VL 4240
6691 11:15:42.357028 # ok 796 Set VL 4256
6692 11:15:42.357123 # ok 797 # SKIP Disabled ZA for VL 4256
6693 11:15:42.357200 # ok 798 # SKIP Get and set data for VL 4256
6694 11:15:42.357276 # ok 799 Set VL 4272
6695 11:15:42.357351 # ok 800 # SKIP Disabled ZA for VL 4272
6696 11:15:42.357440 # ok 801 # SKIP Get and set data for VL 4272
6697 11:15:42.357517 # ok 802 Set VL 4288
6698 11:15:42.357594 # ok 803 # SKIP Disabled ZA for VL 4288
6699 11:15:42.357717 # ok 804 # SKIP Get and set data for VL 4288
6700 11:15:42.357815 # ok 805 Set VL 4304
6701 11:15:42.357911 # ok 806 # SKIP Disabled ZA for VL 4304
6702 11:15:42.357997 # ok 807 # SKIP Get and set data for VL 4304
6703 11:15:42.358072 # ok 808 Set VL 4320
6704 11:15:42.358162 # ok 809 # SKIP Disabled ZA for VL 4320
6705 11:15:42.358238 # ok 810 # SKIP Get and set data for VL 4320
6706 11:15:42.358314 # ok 811 Set VL 4336
6707 11:15:42.363175 # ok 812 # SKIP Disabled ZA for VL 4336
6708 11:15:42.363589 # ok 813 # SKIP Get and set data for VL 4336
6709 11:15:42.363679 # ok 814 Set VL 4352
6710 11:15:42.363765 # ok 815 # SKIP Disabled ZA for VL 4352
6711 11:15:42.363843 # ok 816 # SKIP Get and set data for VL 4352
6712 11:15:42.363919 # ok 817 Set VL 4368
6713 11:15:42.363996 # ok 818 # SKIP Disabled ZA for VL 4368
6714 11:15:42.364089 # ok 819 # SKIP Get and set data for VL 4368
6715 11:15:42.364172 # ok 820 Set VL 4384
6716 11:15:42.364250 # ok 821 # SKIP Disabled ZA for VL 4384
6717 11:15:42.364826 # ok 822 # SKIP Get and set data for VL 4384
6718 11:15:42.365133 # ok 823 Set VL 4400
6719 11:15:42.365230 # ok 824 # SKIP Disabled ZA for VL 4400
6720 11:15:42.365309 # ok 825 # SKIP Get and set data for VL 4400
6721 11:15:42.365398 # ok 826 Set VL 4416
6722 11:15:42.365475 # ok 827 # SKIP Disabled ZA for VL 4416
6723 11:15:42.365564 # ok 828 # SKIP Get and set data for VL 4416
6724 11:15:42.365641 # ok 829 Set VL 4432
6725 11:15:42.365751 # ok 830 # SKIP Disabled ZA for VL 4432
6726 11:15:42.365832 # ok 831 # SKIP Get and set data for VL 4432
6727 11:15:42.365932 # ok 832 Set VL 4448
6728 11:15:42.366030 # ok 833 # SKIP Disabled ZA for VL 4448
6729 11:15:42.375363 # ok 834 # SKIP Get and set data for VL 4448
6730 11:15:42.375589 # ok 835 Set VL 4464
6731 11:15:42.375897 # ok 836 # SKIP Disabled ZA for VL 4464
6732 11:15:42.375995 # ok 837 # SKIP Get and set data for VL 4464
6733 11:15:42.376074 # ok 838 Set VL 4480
6734 11:15:42.376151 # ok 839 # SKIP Disabled ZA for VL 4480
6735 11:15:42.376229 # ok 840 # SKIP Get and set data for VL 4480
6736 11:15:42.376305 # ok 841 Set VL 4496
6737 11:15:42.376394 # ok 842 # SKIP Disabled ZA for VL 4496
6738 11:15:42.376476 # ok 843 # SKIP Get and set data for VL 4496
6739 11:15:42.376558 # ok 844 Set VL 4512
6740 11:15:42.376634 # ok 845 # SKIP Disabled ZA for VL 4512
6741 11:15:42.376709 # ok 846 # SKIP Get and set data for VL 4512
6742 11:15:42.376810 # ok 847 Set VL 4528
6743 11:15:42.376889 # ok 848 # SKIP Disabled ZA for VL 4528
6744 11:15:42.376965 # ok 849 # SKIP Get and set data for VL 4528
6745 11:15:42.377039 # ok 850 Set VL 4544
6746 11:15:42.377128 # ok 851 # SKIP Disabled ZA for VL 4544
6747 11:15:42.377205 # ok 852 # SKIP Get and set data for VL 4544
6748 11:15:42.377282 # ok 853 Set VL 4560
6749 11:15:42.377365 # ok 854 # SKIP Disabled ZA for VL 4560
6750 11:15:42.377464 # ok 855 # SKIP Get and set data for VL 4560
6751 11:15:42.377544 # ok 856 Set VL 4576
6752 11:15:42.377619 # ok 857 # SKIP Disabled ZA for VL 4576
6753 11:15:42.377721 # ok 858 # SKIP Get and set data for VL 4576
6754 11:15:42.377806 # ok 859 Set VL 4592
6755 11:15:42.377895 # ok 860 # SKIP Disabled ZA for VL 4592
6756 11:15:42.377973 # ok 861 # SKIP Get and set data for VL 4592
6757 11:15:42.378062 # ok 862 Set VL 4608
6758 11:15:42.389155 # ok 863 # SKIP Disabled ZA for VL 4608
6759 11:15:42.389399 # ok 864 # SKIP Get and set data for VL 4608
6760 11:15:42.389710 # ok 865 Set VL 4624
6761 11:15:42.389809 # ok 866 # SKIP Disabled ZA for VL 4624
6762 11:15:42.389887 # ok 867 # SKIP Get and set data for VL 4624
6763 11:15:42.389976 # ok 868 Set VL 4640
6764 11:15:42.390055 # ok 869 # SKIP Disabled ZA for VL 4640
6765 11:15:42.390314 # ok 870 # SKIP Get and set data for VL 4640
6766 11:15:42.390395 # ok 871 Set VL 4656
6767 11:15:42.390480 # ok 872 # SKIP Disabled ZA for VL 4656
6768 11:15:42.390550 # ok 873 # SKIP Get and set data for VL 4656
6769 11:15:42.398853 # ok 874 Set VL 4672
6770 11:15:42.399095 # ok 875 # SKIP Disabled ZA for VL 4672
6771 11:15:42.399410 # ok 876 # SKIP Get and set data for VL 4672
6772 11:15:42.399509 # ok 877 Set VL 4688
6773 11:15:42.399586 # ok 878 # SKIP Disabled ZA for VL 4688
6774 11:15:42.399654 # ok 879 # SKIP Get and set data for VL 4688
6775 11:15:42.399730 # ok 880 Set VL 4704
6776 11:15:42.399809 # ok 881 # SKIP Disabled ZA for VL 4704
6777 11:15:42.399909 # ok 882 # SKIP Get and set data for VL 4704
6778 11:15:42.399983 # ok 883 Set VL 4720
6779 11:15:42.400061 # ok 884 # SKIP Disabled ZA for VL 4720
6780 11:15:42.400140 # ok 885 # SKIP Get and set data for VL 4720
6781 11:15:42.400218 # ok 886 Set VL 4736
6782 11:15:42.400309 # ok 887 # SKIP Disabled ZA for VL 4736
6783 11:15:42.400397 # ok 888 # SKIP Get and set data for VL 4736
6784 11:15:42.400499 # ok 889 Set VL 4752
6785 11:15:42.400579 # ok 890 # SKIP Disabled ZA for VL 4752
6786 11:15:42.400680 # ok 891 # SKIP Get and set data for VL 4752
6787 11:15:42.400759 # ok 892 Set VL 4768
6788 11:15:42.400834 # ok 893 # SKIP Disabled ZA for VL 4768
6789 11:15:42.400910 # ok 894 # SKIP Get and set data for VL 4768
6790 11:15:42.401004 # ok 895 Set VL 4784
6791 11:15:42.401105 # ok 896 # SKIP Disabled ZA for VL 4784
6792 11:15:42.401186 # ok 897 # SKIP Get and set data for VL 4784
6793 11:15:42.401256 # ok 898 Set VL 4800
6794 11:15:42.401335 # ok 899 # SKIP Disabled ZA for VL 4800
6795 11:15:42.401414 # ok 900 # SKIP Get and set data for VL 4800
6796 11:15:42.401509 # ok 901 Set VL 4816
6797 11:15:42.401590 # ok 902 # SKIP Disabled ZA for VL 4816
6798 11:15:42.401678 # ok 903 # SKIP Get and set data for VL 4816
6799 11:15:42.401753 # ok 904 Set VL 4832
6800 11:15:42.401829 # ok 905 # SKIP Disabled ZA for VL 4832
6801 11:15:42.401915 # ok 906 # SKIP Get and set data for VL 4832
6802 11:15:42.402023 # ok 907 Set VL 4848
6803 11:15:42.402111 # ok 908 # SKIP Disabled ZA for VL 4848
6804 11:15:42.402192 # ok 909 # SKIP Get and set data for VL 4848
6805 11:15:42.402257 # ok 910 Set VL 4864
6806 11:15:42.415334 # ok 911 # SKIP Disabled ZA for VL 4864
6807 11:15:42.415582 # ok 912 # SKIP Get and set data for VL 4864
6808 11:15:42.415938 # ok 913 Set VL 4880
6809 11:15:42.416060 # ok 914 # SKIP Disabled ZA for VL 4880
6810 11:15:42.416194 # ok 915 # SKIP Get and set data for VL 4880
6811 11:15:42.416317 # ok 916 Set VL 4896
6812 11:15:42.416414 # ok 917 # SKIP Disabled ZA for VL 4896
6813 11:15:42.416492 # ok 918 # SKIP Get and set data for VL 4896
6814 11:15:42.416567 # ok 919 Set VL 4912
6815 11:15:42.416660 # ok 920 # SKIP Disabled ZA for VL 4912
6816 11:15:42.416746 # ok 921 # SKIP Get and set data for VL 4912
6817 11:15:42.416825 # ok 922 Set VL 4928
6818 11:15:42.416900 # ok 923 # SKIP Disabled ZA for VL 4928
6819 11:15:42.416975 # ok 924 # SKIP Get and set data for VL 4928
6820 11:15:42.417052 # ok 925 Set VL 4944
6821 11:15:42.417134 # ok 926 # SKIP Disabled ZA for VL 4944
6822 11:15:42.417235 # ok 927 # SKIP Get and set data for VL 4944
6823 11:15:42.417314 # ok 928 Set VL 4960
6824 11:15:42.417388 # ok 929 # SKIP Disabled ZA for VL 4960
6825 11:15:42.417463 # ok 930 # SKIP Get and set data for VL 4960
6826 11:15:42.417538 # ok 931 Set VL 4976
6827 11:15:42.417612 # ok 932 # SKIP Disabled ZA for VL 4976
6828 11:15:42.417696 # ok 933 # SKIP Get and set data for VL 4976
6829 11:15:42.417780 # ok 934 Set VL 4992
6830 11:15:42.417875 # ok 935 # SKIP Disabled ZA for VL 4992
6831 11:15:42.417959 # ok 936 # SKIP Get and set data for VL 4992
6832 11:15:42.418043 # ok 937 Set VL 5008
6833 11:15:42.418127 # ok 938 # SKIP Disabled ZA for VL 5008
6834 11:15:42.418203 # ok 939 # SKIP Get and set data for VL 5008
6835 11:15:42.418278 # ok 940 Set VL 5024
6836 11:15:42.418367 # ok 941 # SKIP Disabled ZA for VL 5024
6837 11:15:42.431290 # ok 942 # SKIP Get and set data for VL 5024
6838 11:15:42.431537 # ok 943 Set VL 5040
6839 11:15:42.431835 # ok 944 # SKIP Disabled ZA for VL 5040
6840 11:15:42.431940 # ok 945 # SKIP Get and set data for VL 5040
6841 11:15:42.432021 # ok 946 Set VL 5056
6842 11:15:42.432097 # ok 947 # SKIP Disabled ZA for VL 5056
6843 11:15:42.432173 # ok 948 # SKIP Get and set data for VL 5056
6844 11:15:42.432251 # ok 949 Set VL 5072
6845 11:15:42.432344 # ok 950 # SKIP Disabled ZA for VL 5072
6846 11:15:42.432422 # ok 951 # SKIP Get and set data for VL 5072
6847 11:15:42.432498 # ok 952 Set VL 5088
6848 11:15:42.432579 # ok 953 # SKIP Disabled ZA for VL 5088
6849 11:15:42.432688 # ok 954 # SKIP Get and set data for VL 5088
6850 11:15:42.432791 # ok 955 Set VL 5104
6851 11:15:42.432868 # ok 956 # SKIP Disabled ZA for VL 5104
6852 11:15:42.432962 # ok 957 # SKIP Get and set data for VL 5104
6853 11:15:42.433041 # ok 958 Set VL 5120
6854 11:15:42.433115 # ok 959 # SKIP Disabled ZA for VL 5120
6855 11:15:42.433192 # ok 960 # SKIP Get and set data for VL 5120
6856 11:15:42.433268 # ok 961 Set VL 5136
6857 11:15:42.433342 # ok 962 # SKIP Disabled ZA for VL 5136
6858 11:15:42.433417 # ok 963 # SKIP Get and set data for VL 5136
6859 11:15:42.433495 # ok 964 Set VL 5152
6860 11:15:42.433603 # ok 965 # SKIP Disabled ZA for VL 5152
6861 11:15:42.433693 # ok 966 # SKIP Get and set data for VL 5152
6862 11:15:42.433776 # ok 967 Set VL 5168
6863 11:15:42.433853 # ok 968 # SKIP Disabled ZA for VL 5168
6864 11:15:42.433928 # ok 969 # SKIP Get and set data for VL 5168
6865 11:15:42.434003 # ok 970 Set VL 5184
6866 11:15:42.434093 # ok 971 # SKIP Disabled ZA for VL 5184
6867 11:15:42.434170 # ok 972 # SKIP Get and set data for VL 5184
6868 11:15:42.434246 # ok 973 Set VL 5200
6869 11:15:42.434329 # ok 974 # SKIP Disabled ZA for VL 5200
6870 11:15:42.444465 # ok 975 # SKIP Get and set data for VL 5200
6871 11:15:42.444697 # ok 976 Set VL 5216
6872 11:15:42.444807 # ok 977 # SKIP Disabled ZA for VL 5216
6873 11:15:42.444896 # ok 978 # SKIP Get and set data for VL 5216
6874 11:15:42.444981 # ok 979 Set VL 5232
6875 11:15:42.445066 # ok 980 # SKIP Disabled ZA for VL 5232
6876 11:15:42.445150 # ok 981 # SKIP Get and set data for VL 5232
6877 11:15:42.445251 # ok 982 Set VL 5248
6878 11:15:42.445339 # ok 983 # SKIP Disabled ZA for VL 5248
6879 11:15:42.445425 # ok 984 # SKIP Get and set data for VL 5248
6880 11:15:42.445507 # ok 985 Set VL 5264
6881 11:15:42.445606 # ok 986 # SKIP Disabled ZA for VL 5264
6882 11:15:42.445702 # ok 987 # SKIP Get and set data for VL 5264
6883 11:15:42.445789 # ok 988 Set VL 5280
6884 11:15:42.445872 # ok 989 # SKIP Disabled ZA for VL 5280
6885 11:15:42.445968 # ok 990 # SKIP Get and set data for VL 5280
6886 11:15:42.446053 # ok 991 Set VL 5296
6887 11:15:42.446131 # ok 992 # SKIP Disabled ZA for VL 5296
6888 11:15:42.446220 # ok 993 # SKIP Get and set data for VL 5296
6889 11:15:42.449447 # ok 994 Set VL 5312
6890 11:15:42.449861 # ok 995 # SKIP Disabled ZA for VL 5312
6891 11:15:42.449962 # ok 996 # SKIP Get and set data for VL 5312
6892 11:15:42.450061 # ok 997 Set VL 5328
6893 11:15:42.450139 # ok 998 # SKIP Disabled ZA for VL 5328
6894 11:15:42.450212 # ok 999 # SKIP Get and set data for VL 5328
6895 11:15:42.453264 # ok 1000 Set VL 5344
6896 11:15:42.453629 # ok 1001 # SKIP Disabled ZA for VL 5344
6897 11:15:42.453743 # ok 1002 # SKIP Get and set data for VL 5344
6898 11:15:42.453832 # ok 1003 Set VL 5360
6899 11:15:42.453933 # ok 1004 # SKIP Disabled ZA for VL 5360
6900 11:15:42.454018 # ok 1005 # SKIP Get and set data for VL 5360
6901 11:15:42.454095 # ok 1006 Set VL 5376
6902 11:15:42.463395 # ok 1007 # SKIP Disabled ZA for VL 5376
6903 11:15:42.463863 # ok 1008 # SKIP Get and set data for VL 5376
6904 11:15:42.463970 # ok 1009 Set VL 5392
6905 11:15:42.464059 # ok 1010 # SKIP Disabled ZA for VL 5392
6906 11:15:42.464146 # ok 1011 # SKIP Get and set data for VL 5392
6907 11:15:42.464248 # ok 1012 Set VL 5408
6908 11:15:42.464336 # ok 1013 # SKIP Disabled ZA for VL 5408
6909 11:15:42.464422 # ok 1014 # SKIP Get and set data for VL 5408
6910 11:15:42.464507 # ok 1015 Set VL 5424
6911 11:15:42.464803 # ok 1016 # SKIP Disabled ZA for VL 5424
6912 11:15:42.464909 # ok 1017 # SKIP Get and set data for VL 5424
6913 11:15:42.464997 # ok 1018 Set VL 5440
6914 11:15:42.465083 # ok 1019 # SKIP Disabled ZA for VL 5440
6915 11:15:42.465186 # ok 1020 # SKIP Get and set data for VL 5440
6916 11:15:42.465273 # ok 1021 Set VL 5456
6917 11:15:42.465374 # ok 1022 # SKIP Disabled ZA for VL 5456
6918 11:15:42.465462 # ok 1023 # SKIP Get and set data for VL 5456
6919 11:15:42.465549 # ok 1024 Set VL 5472
6920 11:15:42.465636 # ok 1025 # SKIP Disabled ZA for VL 5472
6921 11:15:42.465748 # ok 1026 # SKIP Get and set data for VL 5472
6922 11:15:42.465837 # ok 1027 Set VL 5488
6923 11:15:42.465921 # ok 1028 # SKIP Disabled ZA for VL 5488
6924 11:15:42.466017 # ok 1029 # SKIP Get and set data for VL 5488
6925 11:15:42.466099 # ok 1030 Set VL 5504
6926 11:15:42.471452 # ok 1031 # SKIP Disabled ZA for VL 5504
6927 11:15:42.472003 # ok 1032 # SKIP Get and set data for VL 5504
6928 11:15:42.472110 # ok 1033 Set VL 5520
6929 11:15:42.472201 # ok 1034 # SKIP Disabled ZA for VL 5520
6930 11:15:42.472280 # ok 1035 # SKIP Get and set data for VL 5520
6931 11:15:42.472356 # ok 1036 Set VL 5536
6932 11:15:42.472432 # ok 1037 # SKIP Disabled ZA for VL 5536
6933 11:15:42.472508 # ok 1038 # SKIP Get and set data for VL 5536
6934 11:15:42.472600 # ok 1039 Set VL 5552
6935 11:15:42.472683 # ok 1040 # SKIP Disabled ZA for VL 5552
6936 11:15:42.472768 # ok 1041 # SKIP Get and set data for VL 5552
6937 11:15:42.472845 # ok 1042 Set VL 5568
6938 11:15:42.472921 # ok 1043 # SKIP Disabled ZA for VL 5568
6939 11:15:42.473003 # ok 1044 # SKIP Get and set data for VL 5568
6940 11:15:42.473087 # ok 1045 Set VL 5584
6941 11:15:42.473180 # ok 1046 # SKIP Disabled ZA for VL 5584
6942 11:15:42.473258 # ok 1047 # SKIP Get and set data for VL 5584
6943 11:15:42.473336 # ok 1048 Set VL 5600
6944 11:15:42.473410 # ok 1049 # SKIP Disabled ZA for VL 5600
6945 11:15:42.473486 # ok 1050 # SKIP Get and set data for VL 5600
6946 11:15:42.473562 # ok 1051 Set VL 5616
6947 11:15:42.473660 # ok 1052 # SKIP Disabled ZA for VL 5616
6948 11:15:42.479714 # ok 1053 # SKIP Get and set data for VL 5616
6949 11:15:42.479944 # ok 1054 Set VL 5632
6950 11:15:42.480272 # ok 1055 # SKIP Disabled ZA for VL 5632
6951 11:15:42.480373 # ok 1056 # SKIP Get and set data for VL 5632
6952 11:15:42.480453 # ok 1057 Set VL 5648
6953 11:15:42.480528 # ok 1058 # SKIP Disabled ZA for VL 5648
6954 11:15:42.480605 # ok 1059 # SKIP Get and set data for VL 5648
6955 11:15:42.480680 # ok 1060 Set VL 5664
6956 11:15:42.480778 # ok 1061 # SKIP Disabled ZA for VL 5664
6957 11:15:42.480861 # ok 1062 # SKIP Get and set data for VL 5664
6958 11:15:42.480936 # ok 1063 Set VL 5680
6959 11:15:42.481014 # ok 1064 # SKIP Disabled ZA for VL 5680
6960 11:15:42.481111 # ok 1065 # SKIP Get and set data for VL 5680
6961 11:15:42.481198 # ok 1066 Set VL 5696
6962 11:15:42.481274 # ok 1067 # SKIP Disabled ZA for VL 5696
6963 11:15:42.481363 # ok 1068 # SKIP Get and set data for VL 5696
6964 11:15:42.481440 # ok 1069 Set VL 5712
6965 11:15:42.481516 # ok 1070 # SKIP Disabled ZA for VL 5712
6966 11:15:42.481606 # ok 1071 # SKIP Get and set data for VL 5712
6967 11:15:42.481698 # ok 1072 Set VL 5728
6968 11:15:42.481798 # ok 1073 # SKIP Disabled ZA for VL 5728
6969 11:15:42.481892 # ok 1074 # SKIP Get and set data for VL 5728
6970 11:15:42.481980 # ok 1075 Set VL 5744
6971 11:15:42.482073 # ok 1076 # SKIP Disabled ZA for VL 5744
6972 11:15:42.487560 # ok 1077 # SKIP Get and set data for VL 5744
6973 11:15:42.488123 # ok 1078 Set VL 5760
6974 11:15:42.488324 # ok 1079 # SKIP Disabled ZA for VL 5760
6975 11:15:42.488516 # ok 1080 # SKIP Get and set data for VL 5760
6976 11:15:42.488718 # ok 1081 Set VL 5776
6977 11:15:42.488881 # ok 1082 # SKIP Disabled ZA for VL 5776
6978 11:15:42.489062 # ok 1083 # SKIP Get and set data for VL 5776
6979 11:15:42.489234 # ok 1084 Set VL 5792
6980 11:15:42.489397 # ok 1085 # SKIP Disabled ZA for VL 5792
6981 11:15:42.489556 # ok 1086 # SKIP Get and set data for VL 5792
6982 11:15:42.489735 # ok 1087 Set VL 5808
6983 11:15:42.489902 # ok 1088 # SKIP Disabled ZA for VL 5808
6984 11:15:42.490064 # ok 1089 # SKIP Get and set data for VL 5808
6985 11:15:42.490188 # ok 1090 Set VL 5824
6986 11:15:42.490302 # ok 1091 # SKIP Disabled ZA for VL 5824
6987 11:15:42.490416 # ok 1092 # SKIP Get and set data for VL 5824
6988 11:15:42.490539 # ok 1093 Set VL 5840
6989 11:15:42.490736 # ok 1094 # SKIP Disabled ZA for VL 5840
6990 11:15:42.490912 # ok 1095 # SKIP Get and set data for VL 5840
6991 11:15:42.491097 # ok 1096 Set VL 5856
6992 11:15:42.491297 # ok 1097 # SKIP Disabled ZA for VL 5856
6993 11:15:42.491468 # ok 1098 # SKIP Get and set data for VL 5856
6994 11:15:42.491618 # ok 1099 Set VL 5872
6995 11:15:42.491764 # ok 1100 # SKIP Disabled ZA for VL 5872
6996 11:15:42.491900 # ok 1101 # SKIP Get and set data for VL 5872
6997 11:15:42.492041 # ok 1102 Set VL 5888
6998 11:15:42.492175 # ok 1103 # SKIP Disabled ZA for VL 5888
6999 11:15:42.492345 # ok 1104 # SKIP Get and set data for VL 5888
7000 11:15:42.492505 # ok 1105 Set VL 5904
7001 11:15:42.492642 # ok 1106 # SKIP Disabled ZA for VL 5904
7002 11:15:42.492833 # ok 1107 # SKIP Get and set data for VL 5904
7003 11:15:42.493017 # ok 1108 Set VL 5920
7004 11:15:42.493174 # ok 1109 # SKIP Disabled ZA for VL 5920
7005 11:15:42.493301 # ok 1110 # SKIP Get and set data for VL 5920
7006 11:15:42.493457 # ok 1111 Set VL 5936
7007 11:15:42.493608 # ok 1112 # SKIP Disabled ZA for VL 5936
7008 11:15:42.494525 # ok 1113 # SKIP Get and set data for VL 5936
7009 11:15:42.494660 # ok 1114 Set VL 5952
7010 11:15:42.494777 # ok 1115 # SKIP Disabled ZA for VL 5952
7011 11:15:42.494893 # ok 1116 # SKIP Get and set data for VL 5952
7012 11:15:42.495011 # ok 1117 Set VL 5968
7013 11:15:42.495147 # ok 1118 # SKIP Disabled ZA for VL 5968
7014 11:15:42.495340 # ok 1119 # SKIP Get and set data for VL 5968
7015 11:15:42.495496 # ok 1120 Set VL 5984
7016 11:15:42.495685 # ok 1121 # SKIP Disabled ZA for VL 5984
7017 11:15:42.495842 # ok 1122 # SKIP Get and set data for VL 5984
7018 11:15:42.496007 # ok 1123 Set VL 6000
7019 11:15:42.496169 # ok 1124 # SKIP Disabled ZA for VL 6000
7020 11:15:42.496331 # ok 1125 # SKIP Get and set data for VL 6000
7021 11:15:42.496494 # ok 1126 Set VL 6016
7022 11:15:42.496651 # ok 1127 # SKIP Disabled ZA for VL 6016
7023 11:15:42.496817 # ok 1128 # SKIP Get and set data for VL 6016
7024 11:15:42.496979 # ok 1129 Set VL 6032
7025 11:15:42.497384 # ok 1130 # SKIP Disabled ZA for VL 6032
7026 11:15:42.497560 # ok 1131 # SKIP Get and set data for VL 6032
7027 11:15:42.497740 # ok 1132 Set VL 6048
7028 11:15:42.497907 # ok 1133 # SKIP Disabled ZA for VL 6048
7029 11:15:42.498070 # ok 1134 # SKIP Get and set data for VL 6048
7030 11:15:42.498231 # ok 1135 Set VL 6064
7031 11:15:42.498390 # ok 1136 # SKIP Disabled ZA for VL 6064
7032 11:15:42.498554 # ok 1137 # SKIP Get and set data for VL 6064
7033 11:15:42.498716 # ok 1138 Set VL 6080
7034 11:15:42.501523 # ok 1139 # SKIP Disabled ZA for VL 6080
7035 11:15:42.501948 # ok 1140 # SKIP Get and set data for VL 6080
7036 11:15:42.502046 # ok 1141 Set VL 6096
7037 11:15:42.502125 # ok 1142 # SKIP Disabled ZA for VL 6096
7038 11:15:42.502214 # ok 1143 # SKIP Get and set data for VL 6096
7039 11:15:42.502290 # ok 1144 Set VL 6112
7040 11:15:42.507910 # ok 1145 # SKIP Disabled ZA for VL 6112
7041 11:15:42.508149 # ok 1146 # SKIP Get and set data for VL 6112
7042 11:15:42.508453 # ok 1147 Set VL 6128
7043 11:15:42.508556 # ok 1148 # SKIP Disabled ZA for VL 6128
7044 11:15:42.508645 # ok 1149 # SKIP Get and set data for VL 6128
7045 11:15:42.508734 # ok 1150 Set VL 6144
7046 11:15:42.508834 # ok 1151 # SKIP Disabled ZA for VL 6144
7047 11:15:42.508918 # ok 1152 # SKIP Get and set data for VL 6144
7048 11:15:42.509001 # ok 1153 Set VL 6160
7049 11:15:42.509085 # ok 1154 # SKIP Disabled ZA for VL 6160
7050 11:15:42.509170 # ok 1155 # SKIP Get and set data for VL 6160
7051 11:15:42.509271 # ok 1156 Set VL 6176
7052 11:15:42.509358 # ok 1157 # SKIP Disabled ZA for VL 6176
7053 11:15:42.509443 # ok 1158 # SKIP Get and set data for VL 6176
7054 11:15:42.509529 # ok 1159 Set VL 6192
7055 11:15:42.509630 # ok 1160 # SKIP Disabled ZA for VL 6192
7056 11:15:42.509734 # ok 1161 # SKIP Get and set data for VL 6192
7057 11:15:42.509820 # ok 1162 Set VL 6208
7058 11:15:42.509917 # ok 1163 # SKIP Disabled ZA for VL 6208
7059 11:15:42.509997 # ok 1164 # SKIP Get and set data for VL 6208
7060 11:15:42.514222 # ok 1165 Set VL 6224
7061 11:15:42.515327 # ok 1166 # SKIP Disabled ZA for VL 6224
7062 11:15:42.515525 # ok 1167 # SKIP Get and set data for VL 6224
7063 11:15:42.515718 # ok 1168 Set VL 6240
7064 11:15:42.515932 # ok 1169 # SKIP Disabled ZA for VL 6240
7065 11:15:42.516102 # ok 1170 # SKIP Get and set data for VL 6240
7066 11:15:42.516274 # ok 1171 Set VL 6256
7067 11:15:42.516420 # ok 1172 # SKIP Disabled ZA for VL 6256
7068 11:15:42.516563 # ok 1173 # SKIP Get and set data for VL 6256
7069 11:15:42.516726 # ok 1174 Set VL 6272
7070 11:15:42.516901 # ok 1175 # SKIP Disabled ZA for VL 6272
7071 11:15:42.517087 # ok 1176 # SKIP Get and set data for VL 6272
7072 11:15:42.517225 # ok 1177 Set VL 6288
7073 11:15:42.517369 # ok 1178 # SKIP Disabled ZA for VL 6288
7074 11:15:42.517513 # ok 1179 # SKIP Get and set data for VL 6288
7075 11:15:42.517668 # ok 1180 Set VL 6304
7076 11:15:42.517815 # ok 1181 # SKIP Disabled ZA for VL 6304
7077 11:15:42.517956 # ok 1182 # SKIP Get and set data for VL 6304
7078 11:15:42.518099 # ok 1183 Set VL 6320
7079 11:15:42.518240 # ok 1184 # SKIP Disabled ZA for VL 6320
7080 11:15:42.518382 # ok 1185 # SKIP Get and set data for VL 6320
7081 11:15:42.518522 # ok 1186 Set VL 6336
7082 11:15:42.518662 # ok 1187 # SKIP Disabled ZA for VL 6336
7083 11:15:42.518806 # ok 1188 # SKIP Get and set data for VL 6336
7084 11:15:42.518947 # ok 1189 Set VL 6352
7085 11:15:42.519129 # ok 1190 # SKIP Disabled ZA for VL 6352
7086 11:15:42.519261 # ok 1191 # SKIP Get and set data for VL 6352
7087 11:15:42.519402 # ok 1192 Set VL 6368
7088 11:15:42.519541 # ok 1193 # SKIP Disabled ZA for VL 6368
7089 11:15:42.519682 # ok 1194 # SKIP Get and set data for VL 6368
7090 11:15:42.519828 # ok 1195 Set VL 6384
7091 11:15:42.519969 # ok 1196 # SKIP Disabled ZA for VL 6384
7092 11:15:42.520111 # ok 1197 # SKIP Get and set data for VL 6384
7093 11:15:42.520252 # ok 1198 Set VL 6400
7094 11:15:42.520393 # ok 1199 # SKIP Disabled ZA for VL 6400
7095 11:15:42.520532 # ok 1200 # SKIP Get and set data for VL 6400
7096 11:15:42.520674 # ok 1201 Set VL 6416
7097 11:15:42.520813 # ok 1202 # SKIP Disabled ZA for VL 6416
7098 11:15:42.520956 # ok 1203 # SKIP Get and set data for VL 6416
7099 11:15:42.521097 # ok 1204 Set VL 6432
7100 11:15:42.522859 # ok 1205 # SKIP Disabled ZA for VL 6432
7101 11:15:42.523224 # ok 1206 # SKIP Get and set data for VL 6432
7102 11:15:42.523362 # ok 1207 Set VL 6448
7103 11:15:42.523507 # ok 1208 # SKIP Disabled ZA for VL 6448
7104 11:15:42.523650 # ok 1209 # SKIP Get and set data for VL 6448
7105 11:15:42.523826 # ok 1210 Set VL 6464
7106 11:15:42.523963 # ok 1211 # SKIP Disabled ZA for VL 6464
7107 11:15:42.524106 # ok 1212 # SKIP Get and set data for VL 6464
7108 11:15:42.524289 # ok 1213 Set VL 6480
7109 11:15:42.524495 # ok 1214 # SKIP Disabled ZA for VL 6480
7110 11:15:42.524682 # ok 1215 # SKIP Get and set data for VL 6480
7111 11:15:42.524842 # ok 1216 Set VL 6496
7112 11:15:42.524994 # ok 1217 # SKIP Disabled ZA for VL 6496
7113 11:15:42.525134 # ok 1218 # SKIP Get and set data for VL 6496
7114 11:15:42.525300 # ok 1219 Set VL 6512
7115 11:15:42.525441 # ok 1220 # SKIP Disabled ZA for VL 6512
7116 11:15:42.525616 # ok 1221 # SKIP Get and set data for VL 6512
7117 11:15:42.525825 # ok 1222 Set VL 6528
7118 11:15:42.525986 # ok 1223 # SKIP Disabled ZA for VL 6528
7119 11:15:42.526109 # ok 1224 # SKIP Get and set data for VL 6528
7120 11:15:42.526226 # ok 1225 Set VL 6544
7121 11:15:42.526341 # ok 1226 # SKIP Disabled ZA for VL 6544
7122 11:15:42.526459 # ok 1227 # SKIP Get and set data for VL 6544
7123 11:15:42.526575 # ok 1228 Set VL 6560
7124 11:15:42.526689 # ok 1229 # SKIP Disabled ZA for VL 6560
7125 11:15:42.526808 # ok 1230 # SKIP Get and set data for VL 6560
7126 11:15:42.526923 # ok 1231 Set VL 6576
7127 11:15:42.527038 # ok 1232 # SKIP Disabled ZA for VL 6576
7128 11:15:42.527154 # ok 1233 # SKIP Get and set data for VL 6576
7129 11:15:42.527271 # ok 1234 Set VL 6592
7130 11:15:42.527385 # ok 1235 # SKIP Disabled ZA for VL 6592
7131 11:15:42.527534 # ok 1236 # SKIP Get and set data for VL 6592
7132 11:15:42.527659 # ok 1237 Set VL 6608
7133 11:15:42.527779 # ok 1238 # SKIP Disabled ZA for VL 6608
7134 11:15:42.527895 # ok 1239 # SKIP Get and set data for VL 6608
7135 11:15:42.528011 # ok 1240 Set VL 6624
7136 11:15:42.528126 # ok 1241 # SKIP Disabled ZA for VL 6624
7137 11:15:42.528241 # ok 1242 # SKIP Get and set data for VL 6624
7138 11:15:42.528355 # ok 1243 Set VL 6640
7139 11:15:42.535513 # ok 1244 # SKIP Disabled ZA for VL 6640
7140 11:15:42.535728 # ok 1245 # SKIP Get and set data for VL 6640
7141 11:15:42.535839 # ok 1246 Set VL 6656
7142 11:15:42.535920 # ok 1247 # SKIP Disabled ZA for VL 6656
7143 11:15:42.535998 # ok 1248 # SKIP Get and set data for VL 6656
7144 11:15:42.536078 # ok 1249 Set VL 6672
7145 11:15:42.536155 # ok 1250 # SKIP Disabled ZA for VL 6672
7146 11:15:42.536250 # ok 1251 # SKIP Get and set data for VL 6672
7147 11:15:42.536339 # ok 1252 Set VL 6688
7148 11:15:42.536418 # ok 1253 # SKIP Disabled ZA for VL 6688
7149 11:15:42.536492 # ok 1254 # SKIP Get and set data for VL 6688
7150 11:15:42.536567 # ok 1255 Set VL 6704
7151 11:15:42.536657 # ok 1256 # SKIP Disabled ZA for VL 6704
7152 11:15:42.536742 # ok 1257 # SKIP Get and set data for VL 6704
7153 11:15:42.536820 # ok 1258 Set VL 6720
7154 11:15:42.536895 # ok 1259 # SKIP Disabled ZA for VL 6720
7155 11:15:42.536985 # ok 1260 # SKIP Get and set data for VL 6720
7156 11:15:42.537064 # ok 1261 Set VL 6736
7157 11:15:42.537146 # ok 1262 # SKIP Disabled ZA for VL 6736
7158 11:15:42.537229 # ok 1263 # SKIP Get and set data for VL 6736
7159 11:15:42.537307 # ok 1264 Set VL 6752
7160 11:15:42.537399 # ok 1265 # SKIP Disabled ZA for VL 6752
7161 11:15:42.537477 # ok 1266 # SKIP Get and set data for VL 6752
7162 11:15:42.537551 # ok 1267 Set VL 6768
7163 11:15:42.537641 # ok 1268 # SKIP Disabled ZA for VL 6768
7164 11:15:42.537734 # ok 1269 # SKIP Get and set data for VL 6768
7165 11:15:42.537817 # ok 1270 Set VL 6784
7166 11:15:42.537908 # ok 1271 # SKIP Disabled ZA for VL 6784
7167 11:15:42.537993 # ok 1272 # SKIP Get and set data for VL 6784
7168 11:15:42.538070 # ok 1273 Set VL 6800
7169 11:15:42.538160 # ok 1274 # SKIP Disabled ZA for VL 6800
7170 11:15:42.543552 # ok 1275 # SKIP Get and set data for VL 6800
7171 11:15:42.543976 # ok 1276 Set VL 6816
7172 11:15:42.544071 # ok 1277 # SKIP Disabled ZA for VL 6816
7173 11:15:42.544749 # ok 1278 # SKIP Get and set data for VL 6816
7174 11:15:42.545050 # ok 1279 Set VL 6832
7175 11:15:42.545142 # ok 1280 # SKIP Disabled ZA for VL 6832
7176 11:15:42.545241 # ok 1281 # SKIP Get and set data for VL 6832
7177 11:15:42.545330 # ok 1282 Set VL 6848
7178 11:15:42.545417 # ok 1283 # SKIP Disabled ZA for VL 6848
7179 11:15:42.545519 # ok 1284 # SKIP Get and set data for VL 6848
7180 11:15:42.545606 # ok 1285 Set VL 6864
7181 11:15:42.545707 # ok 1286 # SKIP Disabled ZA for VL 6864
7182 11:15:42.545811 # ok 1287 # SKIP Get and set data for VL 6864
7183 11:15:42.545901 # ok 1288 Set VL 6880
7184 11:15:42.546000 # ok 1289 # SKIP Disabled ZA for VL 6880
7185 11:15:42.559172 # ok 1290 # SKIP Get and set data for VL 6880
7186 11:15:42.559521 # ok 1291 Set VL 6896
7187 11:15:42.559908 # ok 1292 # SKIP Disabled ZA for VL 6896
7188 11:15:42.560103 # ok 1293 # SKIP Get and set data for VL 6896
7189 11:15:42.560310 # ok 1294 Set VL 6912
7190 11:15:42.560479 # ok 1295 # SKIP Disabled ZA for VL 6912
7191 11:15:42.560638 # ok 1296 # SKIP Get and set data for VL 6912
7192 11:15:42.560848 # ok 1297 Set VL 6928
7193 11:15:42.561054 # ok 1298 # SKIP Disabled ZA for VL 6928
7194 11:15:42.561253 # ok 1299 # SKIP Get and set data for VL 6928
7195 11:15:42.561445 # ok 1300 Set VL 6944
7196 11:15:42.561626 # ok 1301 # SKIP Disabled ZA for VL 6944
7197 11:15:42.561833 # ok 1302 # SKIP Get and set data for VL 6944
7198 11:15:42.562034 # ok 1303 Set VL 6960
7199 11:15:42.562190 # ok 1304 # SKIP Disabled ZA for VL 6960
7200 11:15:42.562317 # ok 1305 # SKIP Get and set data for VL 6960
7201 11:15:42.562440 # ok 1306 Set VL 6976
7202 11:15:42.562562 # ok 1307 # SKIP Disabled ZA for VL 6976
7203 11:15:42.562702 # ok 1308 # SKIP Get and set data for VL 6976
7204 11:15:42.562883 # ok 1309 Set VL 6992
7205 11:15:42.563019 # ok 1310 # SKIP Disabled ZA for VL 6992
7206 11:15:42.563139 # ok 1311 # SKIP Get and set data for VL 6992
7207 11:15:42.563256 # ok 1312 Set VL 7008
7208 11:15:42.563375 # ok 1313 # SKIP Disabled ZA for VL 7008
7209 11:15:42.563490 # ok 1314 # SKIP Get and set data for VL 7008
7210 11:15:42.563636 # ok 1315 Set VL 7024
7211 11:15:42.563803 # ok 1316 # SKIP Disabled ZA for VL 7024
7212 11:15:42.563934 # ok 1317 # SKIP Get and set data for VL 7024
7213 11:15:42.564048 # ok 1318 Set VL 7040
7214 11:15:42.564162 # ok 1319 # SKIP Disabled ZA for VL 7040
7215 11:15:42.564276 # ok 1320 # SKIP Get and set data for VL 7040
7216 11:15:42.564391 # ok 1321 Set VL 7056
7217 11:15:42.571111 # ok 1322 # SKIP Disabled ZA for VL 7056
7218 11:15:42.571655 # ok 1323 # SKIP Get and set data for VL 7056
7219 11:15:42.571764 # ok 1324 Set VL 7072
7220 11:15:42.571848 # ok 1325 # SKIP Disabled ZA for VL 7072
7221 11:15:42.571928 # ok 1326 # SKIP Get and set data for VL 7072
7222 11:15:42.572006 # ok 1327 Set VL 7088
7223 11:15:42.572083 # ok 1328 # SKIP Disabled ZA for VL 7088
7224 11:15:42.572161 # ok 1329 # SKIP Get and set data for VL 7088
7225 11:15:42.572238 # ok 1330 Set VL 7104
7226 11:15:42.572331 # ok 1331 # SKIP Disabled ZA for VL 7104
7227 11:15:42.572411 # ok 1332 # SKIP Get and set data for VL 7104
7228 11:15:42.572488 # ok 1333 Set VL 7120
7229 11:15:42.572565 # ok 1334 # SKIP Disabled ZA for VL 7120
7230 11:15:42.572641 # ok 1335 # SKIP Get and set data for VL 7120
7231 11:15:42.572718 # ok 1336 Set VL 7136
7232 11:15:42.572794 # ok 1337 # SKIP Disabled ZA for VL 7136
7233 11:15:42.572886 # ok 1338 # SKIP Get and set data for VL 7136
7234 11:15:42.572965 # ok 1339 Set VL 7152
7235 11:15:42.573041 # ok 1340 # SKIP Disabled ZA for VL 7152
7236 11:15:42.573118 # ok 1341 # SKIP Get and set data for VL 7152
7237 11:15:42.573195 # ok 1342 Set VL 7168
7238 11:15:42.573271 # ok 1343 # SKIP Disabled ZA for VL 7168
7239 11:15:42.573347 # ok 1344 # SKIP Get and set data for VL 7168
7240 11:15:42.573440 # ok 1345 Set VL 7184
7241 11:15:42.573519 # ok 1346 # SKIP Disabled ZA for VL 7184
7242 11:15:42.573596 # ok 1347 # SKIP Get and set data for VL 7184
7243 11:15:42.573683 # ok 1348 Set VL 7200
7244 11:15:42.573761 # ok 1349 # SKIP Disabled ZA for VL 7200
7245 11:15:42.573837 # ok 1350 # SKIP Get and set data for VL 7200
7246 11:15:42.573914 # ok 1351 Set VL 7216
7247 11:15:42.574006 # ok 1352 # SKIP Disabled ZA for VL 7216
7248 11:15:42.574086 # ok 1353 # SKIP Get and set data for VL 7216
7249 11:15:42.574163 # ok 1354 Set VL 7232
7250 11:15:42.574240 # ok 1355 # SKIP Disabled ZA for VL 7232
7251 11:15:42.583361 # ok 1356 # SKIP Get and set data for VL 7232
7252 11:15:42.583556 # ok 1357 Set VL 7248
7253 11:15:42.583992 # ok 1358 # SKIP Disabled ZA for VL 7248
7254 11:15:42.584172 # ok 1359 # SKIP Get and set data for VL 7248
7255 11:15:42.584309 # ok 1360 Set VL 7264
7256 11:15:42.584438 # ok 1361 # SKIP Disabled ZA for VL 7264
7257 11:15:42.584586 # ok 1362 # SKIP Get and set data for VL 7264
7258 11:15:42.584728 # ok 1363 Set VL 7280
7259 11:15:42.584857 # ok 1364 # SKIP Disabled ZA for VL 7280
7260 11:15:42.585100 # ok 1365 # SKIP Get and set data for VL 7280
7261 11:15:42.585278 # ok 1366 Set VL 7296
7262 11:15:42.585432 # ok 1367 # SKIP Disabled ZA for VL 7296
7263 11:15:42.585587 # ok 1368 # SKIP Get and set data for VL 7296
7264 11:15:42.585758 # ok 1369 Set VL 7312
7265 11:15:42.585912 # ok 1370 # SKIP Disabled ZA for VL 7312
7266 11:15:42.586069 # ok 1371 # SKIP Get and set data for VL 7312
7267 11:15:42.586189 # ok 1372 Set VL 7328
7268 11:15:42.586302 # ok 1373 # SKIP Disabled ZA for VL 7328
7269 11:15:42.586416 # ok 1374 # SKIP Get and set data for VL 7328
7270 11:15:42.586529 # ok 1375 Set VL 7344
7271 11:15:42.586670 # ok 1376 # SKIP Disabled ZA for VL 7344
7272 11:15:42.586789 # ok 1377 # SKIP Get and set data for VL 7344
7273 11:15:42.586902 # ok 1378 Set VL 7360
7274 11:15:42.587014 # ok 1379 # SKIP Disabled ZA for VL 7360
7275 11:15:42.587127 # ok 1380 # SKIP Get and set data for VL 7360
7276 11:15:42.587237 # ok 1381 Set VL 7376
7277 11:15:42.587350 # ok 1382 # SKIP Disabled ZA for VL 7376
7278 11:15:42.587460 # ok 1383 # SKIP Get and set data for VL 7376
7279 11:15:42.587573 # ok 1384 Set VL 7392
7280 11:15:42.595011 # ok 1385 # SKIP Disabled ZA for VL 7392
7281 11:15:42.595431 # ok 1386 # SKIP Get and set data for VL 7392
7282 11:15:42.595656 # ok 1387 Set VL 7408
7283 11:15:42.595816 # ok 1388 # SKIP Disabled ZA for VL 7408
7284 11:15:42.595997 # ok 1389 # SKIP Get and set data for VL 7408
7285 11:15:42.596210 # ok 1390 Set VL 7424
7286 11:15:42.596457 # ok 1391 # SKIP Disabled ZA for VL 7424
7287 11:15:42.596665 # ok 1392 # SKIP Get and set data for VL 7424
7288 11:15:42.596868 # ok 1393 Set VL 7440
7289 11:15:42.597038 # ok 1394 # SKIP Disabled ZA for VL 7440
7290 11:15:42.597185 # ok 1395 # SKIP Get and set data for VL 7440
7291 11:15:42.597340 # ok 1396 Set VL 7456
7292 11:15:42.597537 # ok 1397 # SKIP Disabled ZA for VL 7456
7293 11:15:42.597759 # ok 1398 # SKIP Get and set data for VL 7456
7294 11:15:42.597928 # ok 1399 Set VL 7472
7295 11:15:42.598056 # ok 1400 # SKIP Disabled ZA for VL 7472
7296 11:15:42.598203 # ok 1401 # SKIP Get and set data for VL 7472
7297 11:15:42.598324 # ok 1402 Set VL 7488
7298 11:15:42.598439 # ok 1403 # SKIP Disabled ZA for VL 7488
7299 11:15:42.598552 # ok 1404 # SKIP Get and set data for VL 7488
7300 11:15:42.598665 # ok 1405 Set VL 7504
7301 11:15:42.598776 # ok 1406 # SKIP Disabled ZA for VL 7504
7302 11:15:42.598890 # ok 1407 # SKIP Get and set data for VL 7504
7303 11:15:42.599002 # ok 1408 Set VL 7520
7304 11:15:42.599114 # ok 1409 # SKIP Disabled ZA for VL 7520
7305 11:15:42.599227 # ok 1410 # SKIP Get and set data for VL 7520
7306 11:15:42.599341 # ok 1411 Set VL 7536
7307 11:15:42.599453 # ok 1412 # SKIP Disabled ZA for VL 7536
7308 11:15:42.599567 # ok 1413 # SKIP Get and set data for VL 7536
7309 11:15:42.599680 # ok 1414 Set VL 7552
7310 11:15:42.599793 # ok 1415 # SKIP Disabled ZA for VL 7552
7311 11:15:42.599906 # ok 1416 # SKIP Get and set data for VL 7552
7312 11:15:42.600018 # ok 1417 Set VL 7568
7313 11:15:42.600129 # ok 1418 # SKIP Disabled ZA for VL 7568
7314 11:15:42.607024 # ok 1419 # SKIP Get and set data for VL 7568
7315 11:15:42.607230 # ok 1420 Set VL 7584
7316 11:15:42.607662 # ok 1421 # SKIP Disabled ZA for VL 7584
7317 11:15:42.607859 # ok 1422 # SKIP Get and set data for VL 7584
7318 11:15:42.608032 # ok 1423 Set VL 7600
7319 11:15:42.608238 # ok 1424 # SKIP Disabled ZA for VL 7600
7320 11:15:42.608436 # ok 1425 # SKIP Get and set data for VL 7600
7321 11:15:42.608603 # ok 1426 Set VL 7616
7322 11:15:42.608755 # ok 1427 # SKIP Disabled ZA for VL 7616
7323 11:15:42.608928 # ok 1428 # SKIP Get and set data for VL 7616
7324 11:15:42.609086 # ok 1429 Set VL 7632
7325 11:15:42.609229 # ok 1430 # SKIP Disabled ZA for VL 7632
7326 11:15:42.609380 # ok 1431 # SKIP Get and set data for VL 7632
7327 11:15:42.609535 # ok 1432 Set VL 7648
7328 11:15:42.609695 # ok 1433 # SKIP Disabled ZA for VL 7648
7329 11:15:42.609880 # ok 1434 # SKIP Get and set data for VL 7648
7330 11:15:42.610056 # ok 1435 Set VL 7664
7331 11:15:42.610187 # ok 1436 # SKIP Disabled ZA for VL 7664
7332 11:15:42.610302 # ok 1437 # SKIP Get and set data for VL 7664
7333 11:15:42.610417 # ok 1438 Set VL 7680
7334 11:15:42.610531 # ok 1439 # SKIP Disabled ZA for VL 7680
7335 11:15:42.610645 # ok 1440 # SKIP Get and set data for VL 7680
7336 11:15:42.610759 # ok 1441 Set VL 7696
7337 11:15:42.610872 # ok 1442 # SKIP Disabled ZA for VL 7696
7338 11:15:42.610985 # ok 1443 # SKIP Get and set data for VL 7696
7339 11:15:42.611129 # ok 1444 Set VL 7712
7340 11:15:42.611252 # ok 1445 # SKIP Disabled ZA for VL 7712
7341 11:15:42.611366 # ok 1446 # SKIP Get and set data for VL 7712
7342 11:15:42.611482 # ok 1447 Set VL 7728
7343 11:15:42.611596 # ok 1448 # SKIP Disabled ZA for VL 7728
7344 11:15:42.611709 # ok 1449 # SKIP Get and set data for VL 7728
7345 11:15:42.611822 # ok 1450 Set VL 7744
7346 11:15:42.611933 # ok 1451 # SKIP Disabled ZA for VL 7744
7347 11:15:42.612044 # ok 1452 # SKIP Get and set data for VL 7744
7348 11:15:42.612157 # ok 1453 Set VL 7760
7349 11:15:42.612270 # ok 1454 # SKIP Disabled ZA for VL 7760
7350 11:15:42.615265 # ok 1455 # SKIP Get and set data for VL 7760
7351 11:15:42.615374 # ok 1456 Set VL 7776
7352 11:15:42.615651 # ok 1457 # SKIP Disabled ZA for VL 7776
7353 11:15:42.615751 # ok 1458 # SKIP Get and set data for VL 7776
7354 11:15:42.615831 # ok 1459 Set VL 7792
7355 11:15:42.615910 # ok 1460 # SKIP Disabled ZA for VL 7792
7356 11:15:42.616004 # ok 1461 # SKIP Get and set data for VL 7792
7357 11:15:42.616082 # ok 1462 Set VL 7808
7358 11:15:42.616158 # ok 1463 # SKIP Disabled ZA for VL 7808
7359 11:15:42.616234 # ok 1464 # SKIP Get and set data for VL 7808
7360 11:15:42.616324 # ok 1465 Set VL 7824
7361 11:15:42.616402 # ok 1466 # SKIP Disabled ZA for VL 7824
7362 11:15:42.616478 # ok 1467 # SKIP Get and set data for VL 7824
7363 11:15:42.616568 # ok 1468 Set VL 7840
7364 11:15:42.616646 # ok 1469 # SKIP Disabled ZA for VL 7840
7365 11:15:42.616722 # ok 1470 # SKIP Get and set data for VL 7840
7366 11:15:42.616811 # ok 1471 Set VL 7856
7367 11:15:42.616889 # ok 1472 # SKIP Disabled ZA for VL 7856
7368 11:15:42.616964 # ok 1473 # SKIP Get and set data for VL 7856
7369 11:15:42.617053 # ok 1474 Set VL 7872
7370 11:15:42.617132 # ok 1475 # SKIP Disabled ZA for VL 7872
7371 11:15:42.617208 # ok 1476 # SKIP Get and set data for VL 7872
7372 11:15:42.617284 # ok 1477 Set VL 7888
7373 11:15:42.617375 # ok 1478 # SKIP Disabled ZA for VL 7888
7374 11:15:42.617453 # ok 1479 # SKIP Get and set data for VL 7888
7375 11:15:42.617529 # ok 1480 Set VL 7904
7376 11:15:42.617619 # ok 1481 # SKIP Disabled ZA for VL 7904
7377 11:15:42.617706 # ok 1482 # SKIP Get and set data for VL 7904
7378 11:15:42.617783 # ok 1483 Set VL 7920
7379 11:15:42.617873 # ok 1484 # SKIP Disabled ZA for VL 7920
7380 11:15:42.617952 # ok 1485 # SKIP Get and set data for VL 7920
7381 11:15:42.618028 # ok 1486 Set VL 7936
7382 11:15:42.623352 # ok 1487 # SKIP Disabled ZA for VL 7936
7383 11:15:42.623805 # ok 1488 # SKIP Get and set data for VL 7936
7384 11:15:42.624005 # ok 1489 Set VL 7952
7385 11:15:42.624166 # ok 1490 # SKIP Disabled ZA for VL 7952
7386 11:15:42.624327 # ok 1491 # SKIP Get and set data for VL 7952
7387 11:15:42.624497 # ok 1492 Set VL 7968
7388 11:15:42.624708 # ok 1493 # SKIP Disabled ZA for VL 7968
7389 11:15:42.624848 # ok 1494 # SKIP Get and set data for VL 7968
7390 11:15:42.624969 # ok 1495 Set VL 7984
7391 11:15:42.625083 # ok 1496 # SKIP Disabled ZA for VL 7984
7392 11:15:42.625196 # ok 1497 # SKIP Get and set data for VL 7984
7393 11:15:42.625309 # ok 1498 Set VL 8000
7394 11:15:42.625471 # ok 1499 # SKIP Disabled ZA for VL 8000
7395 11:15:42.625665 # ok 1500 # SKIP Get and set data for VL 8000
7396 11:15:42.625832 # ok 1501 Set VL 8016
7397 11:15:42.625975 # ok 1502 # SKIP Disabled ZA for VL 8016
7398 11:15:42.626121 # ok 1503 # SKIP Get and set data for VL 8016
7399 11:15:42.626244 # ok 1504 Set VL 8032
7400 11:15:42.626362 # ok 1505 # SKIP Disabled ZA for VL 8032
7401 11:15:42.626514 # ok 1506 # SKIP Get and set data for VL 8032
7402 11:15:42.626721 # ok 1507 Set VL 8048
7403 11:15:42.626934 # ok 1508 # SKIP Disabled ZA for VL 8048
7404 11:15:42.627195 # ok 1509 # SKIP Get and set data for VL 8048
7405 11:15:42.627413 # ok 1510 Set VL 8064
7406 11:15:42.627619 # ok 1511 # SKIP Disabled ZA for VL 8064
7407 11:15:42.627820 # ok 1512 # SKIP Get and set data for VL 8064
7408 11:15:42.627989 # ok 1513 Set VL 8080
7409 11:15:42.628164 # ok 1514 # SKIP Disabled ZA for VL 8080
7410 11:15:42.628333 # ok 1515 # SKIP Get and set data for VL 8080
7411 11:15:42.628545 # ok 1516 Set VL 8096
7412 11:15:42.628741 # ok 1517 # SKIP Disabled ZA for VL 8096
7413 11:15:42.628954 # ok 1518 # SKIP Get and set data for VL 8096
7414 11:15:42.629082 # ok 1519 Set VL 8112
7415 11:15:42.629197 # ok 1520 # SKIP Disabled ZA for VL 8112
7416 11:15:42.629310 # ok 1521 # SKIP Get and set data for VL 8112
7417 11:15:42.629424 # ok 1522 Set VL 8128
7418 11:15:42.629537 # ok 1523 # SKIP Disabled ZA for VL 8128
7419 11:15:42.629684 # ok 1524 # SKIP Get and set data for VL 8128
7420 11:15:42.629899 # ok 1525 Set VL 8144
7421 11:15:42.630083 # ok 1526 # SKIP Disabled ZA for VL 8144
7422 11:15:42.630233 # ok 1527 # SKIP Get and set data for VL 8144
7423 11:15:42.630376 # ok 1528 Set VL 8160
7424 11:15:42.630516 # ok 1529 # SKIP Disabled ZA for VL 8160
7425 11:15:42.630659 # ok 1530 # SKIP Get and set data for VL 8160
7426 11:15:42.630800 # ok 1531 Set VL 8176
7427 11:15:42.630942 # ok 1532 # SKIP Disabled ZA for VL 8176
7428 11:15:42.631083 # ok 1533 # SKIP Get and set data for VL 8176
7429 11:15:42.631224 # ok 1534 Set VL 8192
7430 11:15:42.631364 # ok 1535 # SKIP Disabled ZA for VL 8192
7431 11:15:42.631506 # ok 1536 # SKIP Get and set data for VL 8192
7432 11:15:42.631647 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7433 11:15:42.631790 ok 34 selftests: arm64: za-ptrace
7434 11:15:42.631931 # selftests: arm64: check_buffer_fill
7435 11:15:43.011991 # 1..20
7436 11:15:43.012451 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7437 11:15:43.012654 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7438 11:15:43.012854 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7439 11:15:43.013020 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7440 11:15:43.013215 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7441 11:15:43.013386 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7442 11:15:43.013560 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 11:15:43.013761 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7444 11:15:43.014000 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7445 11:15:43.017028 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7446 11:15:43.017438 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7447 11:15:43.017641 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7448 11:15:43.017853 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7449 11:15:43.023536 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7450 11:15:43.023978 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7451 11:15:43.024175 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7452 11:15:43.024393 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7453 11:15:43.024581 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7454 11:15:43.024836 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7455 11:15:43.025004 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7456 11:15:43.025183 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7457 11:15:43.041005 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7458 11:15:43.167427 # selftests: arm64: check_child_memory
7459 11:15:43.579911 # 1..12
7460 11:15:43.580257 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7461 11:15:43.580457 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7462 11:15:43.580894 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7463 11:15:43.581084 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7464 11:15:43.581255 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7465 11:15:43.581441 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7466 11:15:43.581643 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7467 11:15:43.581820 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7468 11:15:43.581940 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7469 11:15:43.587264 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7470 11:15:43.587701 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7471 11:15:43.587845 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7472 11:15:43.587989 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7473 11:15:43.604541 not ok 36 selftests: arm64: check_child_memory # exit=1
7474 11:15:43.703432 # selftests: arm64: check_gcr_el1_cswitch
7475 11:16:28.954141 <47>[ 100.156813] systemd-journald[109]: Sent WATCHDOG=1 notification.
7476 11:16:29.156416 <47>[ 100.360434] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3307 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
7477 11:16:29.156905 <47>[ 100.361009] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
7478 11:16:29.157110 <47>[ 100.361489] systemd-journald[109]: Rotating...
7479 11:16:29.183647 <47>[ 100.387585] systemd-journald[109]: Reserving 333 entries in field hash table.
7480 11:16:29.223288 <47>[ 100.427495] systemd-journald[109]: Reserving 4408 entries in data hash table.
7481 11:16:29.231011 <47>[ 100.435268] systemd-journald[109]: Vacuuming...
7482 11:16:29.233891 <47>[ 100.438028] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
7483 11:16:30.471983 # 1..1
7484 11:16:30.472316 # 1..1
7485 11:16:30.472497 # 1..1
7486 11:16:30.472651 # 1..1
7487 11:16:30.472814 # 1..1
7488 11:16:30.472965 # 1..1
7489 11:16:30.473161 # 1..1
7490 11:16:30.473320 # 1..1
7491 11:16:30.473463 # 1..1
7492 11:16:30.473607 # 1..1
7493 11:16:30.473783 # 1..1
7494 11:16:30.473925 # 1..1
7495 11:16:30.474041 # 1..1
7496 11:16:30.474154 # 1..1
7497 11:16:30.474268 # 1..1
7498 11:16:30.474379 # 1..1
7499 11:16:30.474490 # 1..1
7500 11:16:30.474601 # 1..1
7501 11:16:30.474712 # 1..1
7502 11:16:30.474824 # 1..1
7503 11:16:30.474934 # 1..1
7504 11:16:30.475044 # 1..1
7505 11:16:30.475156 # 1..1
7506 11:16:30.475269 # 1..1
7507 11:16:30.475618 # 1..1
7508 11:16:30.475744 # 1..1
7509 11:16:30.475858 # 1..1
7510 11:16:30.475972 # 1..1
7511 11:16:30.476085 # 1..1
7512 11:16:30.476199 # 1..1
7513 11:16:30.476310 # 1..1
7514 11:16:30.476422 # 1..1
7515 11:16:30.476533 # 1..1
7516 11:16:30.476646 # 1..1
7517 11:16:30.476760 # 1..1
7518 11:16:30.476872 # 1..1
7519 11:16:30.476983 # 1..1
7520 11:16:30.477095 # 1..1
7521 11:16:30.477206 # 1..1
7522 11:16:30.477318 # 1..1
7523 11:16:30.477432 # 1..1
7524 11:16:30.477543 # 1..1
7525 11:16:30.477672 # 1..1
7526 11:16:30.477786 # 1..1
7527 11:16:30.477897 # 1..1
7528 11:16:30.478007 # 1..1
7529 11:16:30.478116 # 1..1
7530 11:16:30.478226 # 1..1
7531 11:16:30.478336 # 1..1
7532 11:16:30.478445 # 1..1
7533 11:16:30.478555 # 1..1
7534 11:16:30.478665 # 1..1
7535 11:16:30.478777 # 1..1
7536 11:16:30.478886 # 1..1
7537 11:16:30.478996 # 1..1
7538 11:16:30.479105 # 1..1
7539 11:16:30.479215 # 1..1
7540 11:16:30.479325 # 1..1
7541 11:16:30.479434 # 1..1
7542 11:16:30.479545 # 1..1
7543 11:16:30.479655 # 1..1
7544 11:16:30.479767 # 1..1
7545 11:16:30.479877 # 1..1
7546 11:16:30.479987 # 1..1
7547 11:16:30.480097 # 1..1
7548 11:16:30.480207 # 1..1
7549 11:16:30.480316 # 1..1
7550 11:16:30.480427 # 1..1
7551 11:16:30.480537 # 1..1
7552 11:16:30.480647 # 1..1
7553 11:16:30.480761 # 1..1
7554 11:16:30.480870 # 1..1
7555 11:16:30.480980 # 1..1
7556 11:16:30.481089 # 1..1
7557 11:16:30.481200 # 1..1
7558 11:16:30.481309 # 1..1
7559 11:16:30.481418 # 1..1
7560 11:16:30.481527 # 1..1
7561 11:16:30.481637 # 1..1
7562 11:16:30.481757 # 1..1
7563 11:16:30.481867 # 1..1
7564 11:16:30.481977 # 1..1
7565 11:16:30.482088 # 1..1
7566 11:16:30.482198 # 1..1
7567 11:16:30.482309 # 1..1
7568 11:16:30.482419 # 1..1
7569 11:16:30.482529 # 1..1
7570 11:16:30.482644 # 1..1
7571 11:16:30.482753 # 1..1
7572 11:16:30.482865 # 1..1
7573 11:16:30.482975 # 1..1
7574 11:16:30.483085 # 1..1
7575 11:16:30.483194 # 1..1
7576 11:16:30.483306 # 1..1
7577 11:16:30.483420 # 1..1
7578 11:16:30.483534 # 1..1
7579 11:16:30.483644 # 1..1
7580 11:16:30.483758 # 1..1
7581 11:16:30.483874 # 1..1
7582 11:16:30.517059 # 1..1
7583 11:16:30.517294 # 1..1
7584 11:16:30.517387 # 1..1
7585 11:16:30.517476 # 1..1
7586 11:16:30.517563 # 1..1
7587 11:16:30.517666 # 1..1
7588 11:16:30.517753 # 1..1
7589 11:16:30.517842 # 1..1
7590 11:16:30.517920 # 1..1
7591 11:16:30.517995 # 1..1
7592 11:16:30.518068 # 1..1
7593 11:16:30.518140 # 1..1
7594 11:16:30.518211 # 1..1
7595 11:16:30.518286 # 1..1
7596 11:16:30.518358 # 1..1
7597 11:16:30.518430 # 1..1
7598 11:16:30.518501 # 1..1
7599 11:16:30.518574 # 1..1
7600 11:16:30.518646 # 1..1
7601 11:16:30.518720 # 1..1
7602 11:16:30.518999 # 1..1
7603 11:16:30.519088 # 1..1
7604 11:16:30.519163 # 1..1
7605 11:16:30.519237 # 1..1
7606 11:16:30.519318 # 1..1
7607 11:16:30.519398 # 1..1
7608 11:16:30.519472 # 1..1
7609 11:16:30.519548 # 1..1
7610 11:16:30.519623 # 1..1
7611 11:16:30.519700 # 1..1
7612 11:16:30.519779 # 1..1
7613 11:16:30.519856 # 1..1
7614 11:16:30.519934 # 1..1
7615 11:16:30.520011 # 1..1
7616 11:16:30.520087 # 1..1
7617 11:16:30.520161 # 1..1
7618 11:16:30.520236 # 1..1
7619 11:16:30.520311 # 1..1
7620 11:16:30.520384 # 1..1
7621 11:16:30.520463 # 1..1
7622 11:16:30.520539 # 1..1
7623 11:16:30.520617 # 1..1
7624 11:16:30.520691 # 1..1
7625 11:16:30.520768 # 1..1
7626 11:16:30.520848 # 1..1
7627 11:16:30.520924 # 1..1
7628 11:16:30.521002 # 1..1
7629 11:16:30.543675 # 1..1
7630 11:16:30.543994 # 1..1
7631 11:16:30.544173 # 1..1
7632 11:16:30.544333 # 1..1
7633 11:16:30.544493 # 1..1
7634 11:16:30.544631 # 1..1
7635 11:16:30.544767 # 1..1
7636 11:16:30.544904 # 1..1
7637 11:16:30.545374 # 1..1
7638 11:16:30.545567 # 1..1
7639 11:16:30.545745 # 1..1
7640 11:16:30.545894 # 1..1
7641 11:16:30.546016 # 1..1
7642 11:16:30.546136 # 1..1
7643 11:16:30.546252 # 1..1
7644 11:16:30.546369 # 1..1
7645 11:16:30.546485 # 1..1
7646 11:16:30.546603 # 1..1
7647 11:16:30.546717 # 1..1
7648 11:16:30.546834 # 1..1
7649 11:16:30.546948 # 1..1
7650 11:16:30.547064 # 1..1
7651 11:16:30.547178 # 1..1
7652 11:16:30.547295 # 1..1
7653 11:16:30.547410 # 1..1
7654 11:16:30.547527 # 1..1
7655 11:16:30.547641 # 1..1
7656 11:16:30.547756 # 1..1
7657 11:16:30.547874 # 1..1
7658 11:16:30.547983 # 1..1
7659 11:16:30.548098 # 1..1
7660 11:16:30.548207 # 1..1
7661 11:16:30.548315 # 1..1
7662 11:16:30.548427 # 1..1
7663 11:16:30.548538 # 1..1
7664 11:16:30.548647 # 1..1
7665 11:16:30.548757 # 1..1
7666 11:16:30.548868 # 1..1
7667 11:16:30.548976 # 1..1
7668 11:16:30.549084 # 1..1
7669 11:16:30.549199 # 1..1
7670 11:16:30.549308 # 1..1
7671 11:16:30.549416 # 1..1
7672 11:16:30.549525 # 1..1
7673 11:16:30.549633 # 1..1
7674 11:16:30.549858 # 1..1
7675 11:16:30.550046 # 1..1
7676 11:16:30.550225 # 1..1
7677 11:16:30.550403 # 1..1
7678 11:16:30.550588 # 1..1
7679 11:16:30.550765 # 1..1
7680 11:16:30.550945 # 1..1
7681 11:16:30.551117 # 1..1
7682 11:16:30.551256 # 1..1
7683 11:16:30.551395 # 1..1
7684 11:16:30.551534 # 1..1
7685 11:16:30.551672 # 1..1
7686 11:16:30.551810 # 1..1
7687 11:16:30.551948 # 1..1
7688 11:16:30.552087 # 1..1
7689 11:16:30.552223 # 1..1
7690 11:16:30.552360 # 1..1
7691 11:16:30.552497 # 1..1
7692 11:16:30.552635 # 1..1
7693 11:16:30.552772 # 1..1
7694 11:16:30.552911 # 1..1
7695 11:16:30.553049 # 1..1
7696 11:16:30.553185 # 1..1
7697 11:16:30.553323 # 1..1
7698 11:16:30.553461 # 1..1
7699 11:16:30.553598 # 1..1
7700 11:16:30.553747 # 1..1
7701 11:16:30.553886 # 1..1
7702 11:16:30.554028 # 1..1
7703 11:16:30.554167 # 1..1
7704 11:16:30.554308 # 1..1
7705 11:16:30.554446 # 1..1
7706 11:16:30.554584 # 1..1
7707 11:16:30.554722 # 1..1
7708 11:16:30.554902 # 1..1
7709 11:16:30.555034 # 1..1
7710 11:16:30.555174 # 1..1
7711 11:16:30.555314 # 1..1
7712 11:16:30.555452 # 1..1
7713 11:16:30.555590 # 1..1
7714 11:16:30.555726 # 1..1
7715 11:16:30.555864 # 1..1
7716 11:16:30.556003 # 1..1
7717 11:16:30.556141 # 1..1
7718 11:16:30.556279 # 1..1
7719 11:16:30.556417 # 1..1
7720 11:16:30.556555 # 1..1
7721 11:16:30.556693 # 1..1
7722 11:16:30.556830 # 1..1
7723 11:16:30.556968 # 1..1
7724 11:16:30.557107 # 1..1
7725 11:16:30.557246 # 1..1
7726 11:16:30.557384 # 1..1
7727 11:16:30.557522 # 1..1
7728 11:16:30.557668 # 1..1
7729 11:16:30.557810 # 1..1
7730 11:16:30.557953 # 1..1
7731 11:16:30.558091 # 1..1
7732 11:16:30.558231 # 1..1
7733 11:16:30.559148 # 1..1
7734 11:16:30.559352 # 1..1
7735 11:16:30.559538 # 1..1
7736 11:16:30.559699 # 1..1
7737 11:16:30.559873 # 1..1
7738 11:16:30.560408 # 1..1
7739 11:16:30.560583 # 1..1
7740 11:16:30.560738 # 1..1
7741 11:16:30.560902 # 1..1
7742 11:16:30.561043 # 1..1
7743 11:16:30.561201 # 1..1
7744 11:16:30.561395 # 1..1
7745 11:16:30.561585 # 1..1
7746 11:16:30.561751 # 1..1
7747 11:16:30.561919 # 1..1
7748 11:16:30.562065 # 1..1
7749 11:16:30.562182 # 1..1
7750 11:16:30.562296 # 1..1
7751 11:16:30.562409 # 1..1
7752 11:16:30.562523 # 1..1
7753 11:16:30.562636 # 1..1
7754 11:16:30.562748 # 1..1
7755 11:16:30.562860 # 1..1
7756 11:16:30.562972 # 1..1
7757 11:16:30.563085 # 1..1
7758 11:16:30.563197 # 1..1
7759 11:16:30.563309 # 1..1
7760 11:16:30.563422 # 1..1
7761 11:16:30.563536 # 1..1
7762 11:16:30.563648 # 1..1
7763 11:16:30.563760 # 1..1
7764 11:16:30.563875 # 1..1
7765 11:16:30.563987 # 1..1
7766 11:16:30.564099 # 1..1
7767 11:16:30.564211 # 1..1
7768 11:16:30.564323 # 1..1
7769 11:16:30.564435 # 1..1
7770 11:16:30.564547 # 1..1
7771 11:16:30.564660 # 1..1
7772 11:16:30.564773 # 1..1
7773 11:16:30.564886 # 1..1
7774 11:16:30.564998 # 1..1
7775 11:16:30.565111 # 1..1
7776 11:16:30.565223 # 1..1
7777 11:16:30.565336 # 1..1
7778 11:16:30.565447 # 1..1
7779 11:16:30.565561 # 1..1
7780 11:16:30.565685 # 1..1
7781 11:16:30.565798 # 1..1
7782 11:16:30.565911 # 1..1
7783 11:16:30.566024 # 1..1
7784 11:16:30.566137 # 1..1
7785 11:16:30.566250 # 1..1
7786 11:16:30.566395 # 1..1
7787 11:16:30.566515 # 1..1
7788 11:16:30.566630 # 1..1
7789 11:16:30.566742 # 1..1
7790 11:16:30.566859 # 1..1
7791 11:16:30.566972 # 1..1
7792 11:16:30.567084 # 1..1
7793 11:16:30.567198 # 1..1
7794 11:16:30.567311 # 1..1
7795 11:16:30.567424 # 1..1
7796 11:16:30.567535 # 1..1
7797 11:16:30.567648 # 1..1
7798 11:16:30.567761 # 1..1
7799 11:16:30.567874 # 1..1
7800 11:16:30.567986 # 1..1
7801 11:16:30.568098 # 1..1
7802 11:16:30.568211 # 1..1
7803 11:16:30.568322 # 1..1
7804 11:16:30.568435 # 1..1
7805 11:16:30.568545 # 1..1
7806 11:16:30.568658 # 1..1
7807 11:16:30.568771 # 1..1
7808 11:16:30.568884 # 1..1
7809 11:16:30.568996 # 1..1
7810 11:16:30.569109 # 1..1
7811 11:16:30.569220 # 1..1
7812 11:16:30.569333 # 1..1
7813 11:16:30.569446 # 1..1
7814 11:16:30.569558 # 1..1
7815 11:16:30.569682 # 1..1
7816 11:16:30.569795 # 1..1
7817 11:16:30.569907 # 1..1
7818 11:16:30.570017 # 1..1
7819 11:16:30.570126 # 1..1
7820 11:16:30.570236 # 1..1
7821 11:16:30.570345 # 1..1
7822 11:16:30.570456 # 1..1
7823 11:16:30.570566 # 1..1
7824 11:16:30.570676 # 1..1
7825 11:16:30.570786 # 1..1
7826 11:16:30.570896 # 1..1
7827 11:16:30.571006 # 1..1
7828 11:16:30.571117 # 1..1
7829 11:16:30.571226 # 1..1
7830 11:16:30.571336 # 1..1
7831 11:16:30.571446 # 1..1
7832 11:16:30.571557 # 1..1
7833 11:16:30.571666 # 1..1
7834 11:16:30.571776 # 1..1
7835 11:16:30.571886 # 1..1
7836 11:16:30.571996 # 1..1
7837 11:16:30.572104 # 1..1
7838 11:16:30.572215 # 1..1
7839 11:16:30.572325 # 1..1
7840 11:16:30.572435 # 1..1
7841 11:16:30.572544 # 1..1
7842 11:16:30.583342 # 1..1
7843 11:16:30.583519 # 1..1
7844 11:16:30.583719 # 1..1
7845 11:16:30.583906 # 1..1
7846 11:16:30.584068 # 1..1
7847 11:16:30.584274 # 1..1
7848 11:16:30.584452 # 1..1
7849 11:16:30.584810 # 1..1
7850 11:16:30.584916 # 1..1
7851 11:16:30.584993 # 1..1
7852 11:16:30.585065 # 1..1
7853 11:16:30.585135 # 1..1
7854 11:16:30.585205 # 1..1
7855 11:16:30.585275 # 1..1
7856 11:16:30.585345 # 1..1
7857 11:16:30.585414 # 1..1
7858 11:16:30.585484 # 1..1
7859 11:16:30.585553 # 1..1
7860 11:16:30.585622 # 1..1
7861 11:16:30.585700 # 1..1
7862 11:16:30.585769 # 1..1
7863 11:16:30.585839 # 1..1
7864 11:16:30.585914 # 1..1
7865 11:16:30.585982 # 1..1
7866 11:16:30.586052 # 1..1
7867 11:16:30.586121 # 1..1
7868 11:16:30.586190 # 1..1
7869 11:16:30.586259 # 1..1
7870 11:16:30.586326 # 1..1
7871 11:16:30.586394 # 1..1
7872 11:16:30.586462 # 1..1
7873 11:16:30.586531 # 1..1
7874 11:16:30.586600 # 1..1
7875 11:16:30.586668 # 1..1
7876 11:16:30.586737 # 1..1
7877 11:16:30.586806 # 1..1
7878 11:16:30.586875 # 1..1
7879 11:16:30.586943 # 1..1
7880 11:16:30.587012 # 1..1
7881 11:16:30.587081 # 1..1
7882 11:16:30.587149 # 1..1
7883 11:16:30.587218 # 1..1
7884 11:16:30.587288 # 1..1
7885 11:16:30.587357 # 1..1
7886 11:16:30.587427 # 1..1
7887 11:16:30.587495 # 1..1
7888 11:16:30.587564 # 1..1
7889 11:16:30.587633 # 1..1
7890 11:16:30.587702 # 1..1
7891 11:16:30.587772 # 1..1
7892 11:16:30.587841 # 1..1
7893 11:16:30.587910 # 1..1
7894 11:16:30.587980 # 1..1
7895 11:16:30.588049 # 1..1
7896 11:16:30.588117 # 1..1
7897 11:16:30.588185 # 1..1
7898 11:16:30.588254 # 1..1
7899 11:16:30.588324 # 1..1
7900 11:16:30.588394 # 1..1
7901 11:16:30.588467 # 1..1
7902 11:16:30.588537 # 1..1
7903 11:16:30.588607 # 1..1
7904 11:16:30.588677 # 1..1
7905 11:16:30.588749 # 1..1
7906 11:16:30.588819 # 1..1
7907 11:16:30.588894 # 1..1
7908 11:16:30.588982 # 1..1
7909 11:16:30.589055 # 1..1
7910 11:16:30.589126 # 1..1
7911 11:16:30.589195 # 1..1
7912 11:16:30.589264 # 1..1
7913 11:16:30.589334 # 1..1
7914 11:16:30.589403 # 1..1
7915 11:16:30.589474 # 1..1
7916 11:16:30.589543 # 1..1
7917 11:16:30.589612 # 1..1
7918 11:16:30.590505 # 1..1
7919 11:16:30.590587 # 1..1
7920 11:16:30.590659 # 1..1
7921 11:16:30.590731 # 1..1
7922 11:16:30.590800 # 1..1
7923 11:16:30.590869 # 1..1
7924 11:16:30.590939 # 1..1
7925 11:16:30.591010 # 1..1
7926 11:16:30.591081 # 1..1
7927 11:16:30.591150 # 1..1
7928 11:16:30.591221 # 1..1
7929 11:16:30.591292 # 1..1
7930 11:16:30.591362 # 1..1
7931 11:16:30.591433 # 1..1
7932 11:16:30.591503 # 1..1
7933 11:16:30.591573 # 1..1
7934 11:16:30.591642 # 1..1
7935 11:16:30.591712 # 1..1
7936 11:16:30.591783 # 1..1
7937 11:16:30.591853 # 1..1
7938 11:16:30.591931 # 1..1
7939 11:16:30.592002 # 1..1
7940 11:16:30.592071 # 1..1
7941 11:16:30.592142 # 1..1
7942 11:16:30.592211 # 1..1
7943 11:16:30.592279 # 1..1
7944 11:16:30.592349 # 1..1
7945 11:16:30.592419 # 1..1
7946 11:16:30.592490 # 1..1
7947 11:16:30.592560 # 1..1
7948 11:16:30.592630 # 1..1
7949 11:16:30.592702 # 1..1
7950 11:16:30.592773 # 1..1
7951 11:16:30.592844 # 1..1
7952 11:16:30.592914 # 1..1
7953 11:16:30.592984 # 1..1
7954 11:16:30.593054 # 1..1
7955 11:16:30.593125 # 1..1
7956 11:16:30.593195 # 1..1
7957 11:16:30.599104 # 1..1
7958 11:16:30.599202 # 1..1
7959 11:16:30.599278 # 1..1
7960 11:16:30.599351 # 1..1
7961 11:16:30.599425 # 1..1
7962 11:16:30.599687 # 1..1
7963 11:16:30.599766 # 1..1
7964 11:16:30.599839 # 1..1
7965 11:16:30.599916 # 1..1
7966 11:16:30.599988 # 1..1
7967 11:16:30.600060 # 1..1
7968 11:16:30.600132 # 1..1
7969 11:16:30.600205 # 1..1
7970 11:16:30.600276 # 1..1
7971 11:16:30.600348 # 1..1
7972 11:16:30.600421 # 1..1
7973 11:16:30.600494 # 1..1
7974 11:16:30.600566 # 1..1
7975 11:16:30.600638 # 1..1
7976 11:16:30.600710 # 1..1
7977 11:16:30.600782 # 1..1
7978 11:16:30.600854 # 1..1
7979 11:16:30.600931 # 1..1
7980 11:16:30.601003 # 1..1
7981 11:16:30.601075 # 1..1
7982 11:16:30.601147 # 1..1
7983 11:16:30.601218 # 1..1
7984 11:16:30.601307 # 1..1
7985 11:16:30.601381 # 1..1
7986 11:16:30.601452 # 1..1
7987 11:16:30.601524 # 1..1
7988 11:16:30.601595 # 1..1
7989 11:16:30.601675 # 1..1
7990 11:16:30.601748 # 1..1
7991 11:16:30.601820 # 1..1
7992 11:16:30.601893 # 1..1
7993 11:16:30.601965 # 1..1
7994 11:16:30.602037 # 1..1
7995 11:16:30.602108 # 1..1
7996 11:16:30.602180 # 1..1
7997 11:16:30.602251 # 1..1
7998 11:16:30.602323 # 1..1
7999 11:16:30.602395 # 1..1
8000 11:16:30.602466 # 1..1
8001 11:16:30.602539 # 1..1
8002 11:16:30.602611 # 1..1
8003 11:16:30.602683 # 1..1
8004 11:16:30.602754 # 1..1
8005 11:16:30.602825 # 1..1
8006 11:16:30.602897 # 1..1
8007 11:16:30.602970 # 1..1
8008 11:16:30.603042 # 1..1
8009 11:16:30.603118 # 1..1
8010 11:16:30.603191 # 1..1
8011 11:16:30.603264 # 1..1
8012 11:16:30.603336 # 1..1
8013 11:16:30.603408 # 1..1
8014 11:16:30.603480 # 1..1
8015 11:16:30.603552 # 1..1
8016 11:16:30.603625 # 1..1
8017 11:16:30.603697 # 1..1
8018 11:16:30.603769 # 1..1
8019 11:16:30.603841 # 1..1
8020 11:16:30.603913 # 1..1
8021 11:16:30.603985 # 1..1
8022 11:16:30.604057 # 1..1
8023 11:16:30.604128 # 1..1
8024 11:16:30.604201 # 1..1
8025 11:16:30.604273 # 1..1
8026 11:16:30.604346 # 1..1
8027 11:16:30.604418 # 1..1
8028 11:16:30.604491 # 1..1
8029 11:16:30.604563 # 1..1
8030 11:16:30.604635 # 1..1
8031 11:16:30.604708 # 1..1
8032 11:16:30.604795 # 1..1
8033 11:16:30.604870 # 1..1
8034 11:16:30.604946 # 1..1
8035 11:16:30.605019 # 1..1
8036 11:16:30.633948 #
8037 11:16:30.634632 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
8038 11:16:30.859604 # selftests: arm64: check_ksm_options
8039 11:16:31.188629 # 1..4
8040 11:16:31.188830 # # Invalid MTE synchronous exception caught!
8041 11:16:31.231831 not ok 38 selftests: arm64: check_ksm_options # exit=1
8042 11:16:31.515367 # selftests: arm64: check_mmap_options
8043 11:16:32.273997 # 1..22
8044 11:16:32.274211 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
8045 11:16:32.274293 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
8046 11:16:32.274782 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
8047 11:16:32.274892 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
8048 11:16:32.275213 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
8049 11:16:32.275654 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8050 11:16:32.275844 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
8051 11:16:32.275997 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8052 11:16:32.276157 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
8053 11:16:32.276547 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8054 11:16:32.276755 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
8055 11:16:32.276943 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8056 11:16:32.277137 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
8057 11:16:32.277330 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8058 11:16:32.277509 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
8059 11:16:32.277693 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8060 11:16:32.277898 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
8061 11:16:32.300040 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8062 11:16:32.300385 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
8063 11:16:32.300489 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8064 11:16:32.300588 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
8065 11:16:32.300884 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
8066 11:16:32.300975 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
8067 11:16:32.337077 not ok 39 selftests: arm64: check_mmap_options # exit=1
8068 11:16:32.609145 # selftests: arm64: check_prctl
8069 11:16:32.897421 # TAP version 13
8070 11:16:32.897645 # 1..5
8071 11:16:32.897735 # ok 1 check_basic_read
8072 11:16:32.897816 # ok 2 NONE
8073 11:16:32.897887 # ok 3 SYNC
8074 11:16:32.898163 # ok 4 ASYNC
8075 11:16:32.898246 # ok 5 SYNC+ASYNC
8076 11:16:32.898323 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8077 11:16:32.938897 ok 40 selftests: arm64: check_prctl
8078 11:16:33.220451 # selftests: arm64: check_tags_inclusion
8079 11:16:33.515790 # 1..4
8080 11:16:33.516102 # # Unexpected fault recorded for 0xc00ffff8b213000-0xc00ffff8b213050 in mode 1
8081 11:16:33.516203 # not ok 1 Check an included tag value with sync mode
8082 11:16:33.516301 # # Unexpected fault recorded for 0xe00ffff8b213000-0xe00ffff8b213050 in mode 1
8083 11:16:33.516385 # not ok 2 Check different included tags value with sync mode
8084 11:16:33.516482 # ok 3 Check none included tags value with sync mode
8085 11:16:33.516573 # # Unexpected fault recorded for 0x600ffff8b213000-0x600ffff8b213050 in mode 1
8086 11:16:33.516665 # not ok 4 Check all included tags value with sync mode
8087 11:16:33.516953 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
8088 11:16:33.563988 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
8089 11:16:33.696418 # selftests: arm64: check_user_mem
8090 11:16:42.141128 # 1..64
8091 11:16:42.141721 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8092 11:16:42.141833 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8093 11:16:42.141918 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8094 11:16:42.141994 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8095 11:16:42.143225 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8096 11:16:42.143671 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8097 11:16:42.143887 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8098 11:16:42.144100 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8099 11:16:42.144275 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8100 11:16:42.144732 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8101 11:16:42.144957 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8102 11:16:42.145190 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8103 11:16:42.145356 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8104 11:16:42.145522 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8105 11:16:42.145761 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8106 11:16:42.145925 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8107 11:16:42.151538 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8108 11:16:42.151836 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8109 11:16:42.152273 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8110 11:16:42.152490 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8111 11:16:42.152692 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8112 11:16:42.152958 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8113 11:16:42.153170 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8114 11:16:42.153349 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8115 11:16:42.153573 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8116 11:16:42.153788 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8117 11:16:42.154021 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8118 11:16:42.154167 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8119 11:16:42.154678 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8120 11:16:42.154894 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8121 11:16:42.155144 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8122 11:16:42.155387 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8123 11:16:42.155941 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8124 11:16:42.156148 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8125 11:16:42.156374 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8126 11:16:42.156610 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8127 11:16:42.156797 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8128 11:16:42.157013 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8129 11:16:42.157245 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8130 11:16:42.157427 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8131 11:16:42.157668 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8132 11:16:42.157860 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8133 11:16:42.157996 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8134 11:16:42.158140 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8135 11:16:42.163100 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8136 11:16:42.163243 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8137 11:16:42.163545 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8138 11:16:42.163661 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8139 11:16:42.164023 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8140 11:16:42.164255 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8141 11:16:42.164432 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8142 11:16:43.819579 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8143 11:16:43.820080 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8144 11:16:43.820189 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8145 11:16:43.820503 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8146 11:16:43.820603 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8147 11:16:43.820702 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8148 11:16:43.821112 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8149 11:16:43.821329 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8150 11:16:43.821538 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8151 11:16:43.821725 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8152 11:16:43.821880 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8153 11:16:43.822005 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8154 11:16:43.828633 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8155 11:16:43.828890 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
8156 11:16:43.843396 ok 42 selftests: arm64: check_user_mem
8157 11:16:43.932508 # selftests: arm64: btitest
8158 11:16:44.057675 # TAP version 13
8159 11:16:44.057973 # 1..18
8160 11:16:44.058108 # # HWCAP_PACA present
8161 11:16:44.058226 # # HWCAP2_BTI present
8162 11:16:44.058559 # # Test binary built for BTI
8163 11:16:44.064418 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
8164 11:16:44.064737 # ok 1 nohint_func/call_using_br_x0
8165 11:16:44.064960 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
8166 11:16:44.065111 # ok 2 nohint_func/call_using_br_x16
8167 11:16:44.065241 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
8168 11:16:44.065388 # ok 3 nohint_func/call_using_blr
8169 11:16:44.065587 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
8170 11:16:44.065759 # ok 4 bti_none_func/call_using_br_x0
8171 11:16:44.065902 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
8172 11:16:44.066022 # ok 5 bti_none_func/call_using_br_x16
8173 11:16:44.066164 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
8174 11:16:44.066286 # ok 6 bti_none_func/call_using_blr
8175 11:16:44.067800 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
8176 11:16:44.068205 # ok 7 bti_c_func/call_using_br_x0
8177 11:16:44.068366 # ok 8 bti_c_func/call_using_br_x16
8178 11:16:44.068515 # ok 9 bti_c_func/call_using_blr
8179 11:16:44.068696 # ok 10 bti_j_func/call_using_br_x0
8180 11:16:44.068858 # ok 11 bti_j_func/call_using_br_x16
8181 11:16:44.069022 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
8182 11:16:44.069213 # ok 12 bti_j_func/call_using_blr
8183 11:16:44.069376 # ok 13 bti_jc_func/call_using_br_x0
8184 11:16:44.069525 # ok 14 bti_jc_func/call_using_br_x16
8185 11:16:44.069682 # ok 15 bti_jc_func/call_using_blr
8186 11:16:44.069922 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
8187 11:16:44.070075 # ok 16 paciasp_func/call_using_br_x0
8188 11:16:44.070219 # ok 17 paciasp_func/call_using_br_x16
8189 11:16:44.070360 # ok 18 paciasp_func/call_using_blr
8190 11:16:44.081841 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8191 11:16:44.083928 ok 43 selftests: arm64: btitest
8192 11:16:44.176630 # selftests: arm64: nobtitest
8193 11:16:44.276821 # TAP version 13
8194 11:16:44.277147 # 1..18
8195 11:16:44.277343 # # HWCAP_PACA present
8196 11:16:44.277539 # # HWCAP2_BTI present
8197 11:16:44.277782 # # Test binary not built for BTI
8198 11:16:44.278168 # ok 1 nohint_func/call_using_br_x0
8199 11:16:44.278299 # ok 2 nohint_func/call_using_br_x16
8200 11:16:44.278417 # ok 3 nohint_func/call_using_blr
8201 11:16:44.278532 # ok 4 bti_none_func/call_using_br_x0
8202 11:16:44.278646 # ok 5 bti_none_func/call_using_br_x16
8203 11:16:44.278761 # ok 6 bti_none_func/call_using_blr
8204 11:16:44.278876 # ok 7 bti_c_func/call_using_br_x0
8205 11:16:44.278991 # ok 8 bti_c_func/call_using_br_x16
8206 11:16:44.279105 # ok 9 bti_c_func/call_using_blr
8207 11:16:44.279219 # ok 10 bti_j_func/call_using_br_x0
8208 11:16:44.279334 # ok 11 bti_j_func/call_using_br_x16
8209 11:16:44.280914 # ok 12 bti_j_func/call_using_blr
8210 11:16:44.281251 # ok 13 bti_jc_func/call_using_br_x0
8211 11:16:44.281365 # ok 14 bti_jc_func/call_using_br_x16
8212 11:16:44.281469 # ok 15 bti_jc_func/call_using_blr
8213 11:16:44.281552 # ok 16 paciasp_func/call_using_br_x0
8214 11:16:44.281632 # ok 17 paciasp_func/call_using_br_x16
8215 11:16:44.281730 # ok 18 paciasp_func/call_using_blr
8216 11:16:44.282003 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8217 11:16:44.301324 ok 44 selftests: arm64: nobtitest
8218 11:16:44.396493 # selftests: arm64: hwcap
8219 11:16:44.539771 # TAP version 13
8220 11:16:44.540011 # 1..28
8221 11:16:44.540103 # # RNG present
8222 11:16:44.540369 # ok 1 cpuinfo_match_RNG
8223 11:16:44.540474 # ok 2 sigill_RNG
8224 11:16:44.540561 # # SME present
8225 11:16:44.540648 # ok 3 cpuinfo_match_SME
8226 11:16:44.540732 # ok 4 sigill_SME
8227 11:16:44.540818 # # SVE present
8228 11:16:44.540901 # ok 5 cpuinfo_match_SVE
8229 11:16:44.540981 # ok 6 sigill_SVE
8230 11:16:44.541067 # # SVE 2 present
8231 11:16:44.541169 # ok 7 cpuinfo_match_SVE 2
8232 11:16:44.541256 # ok 8 sigill_SVE 2
8233 11:16:44.541339 # # SVE AES present
8234 11:16:44.541421 # ok 9 cpuinfo_match_SVE AES
8235 11:16:44.541502 # ok 10 sigill_SVE AES
8236 11:16:44.541584 # # SVE2 PMULL present
8237 11:16:44.541672 # ok 11 cpuinfo_match_SVE2 PMULL
8238 11:16:44.541755 # ok 12 sigill_SVE2 PMULL
8239 11:16:44.541834 # # SVE2 BITPERM present
8240 11:16:44.541927 # ok 13 cpuinfo_match_SVE2 BITPERM
8241 11:16:44.542006 # ok 14 sigill_SVE2 BITPERM
8242 11:16:44.542083 # # SVE2 SHA3 present
8243 11:16:44.542159 # ok 15 cpuinfo_match_SVE2 SHA3
8244 11:16:44.542235 # ok 16 sigill_SVE2 SHA3
8245 11:16:44.542311 # # SVE2 SM4 present
8246 11:16:44.551214 # ok 17 cpuinfo_match_SVE2 SM4
8247 11:16:44.551562 # ok 18 sigill_SVE2 SM4
8248 11:16:44.551765 # # SVE2 I8MM present
8249 11:16:44.552195 # ok 19 cpuinfo_match_SVE2 I8MM
8250 11:16:44.552391 # ok 20 sigill_SVE2 I8MM
8251 11:16:44.552535 # # SVE2 F32MM present
8252 11:16:44.552655 # ok 21 cpuinfo_match_SVE2 F32MM
8253 11:16:44.552771 # ok 22 sigill_SVE2 F32MM
8254 11:16:44.552885 # # SVE2 F64MM present
8255 11:16:44.553000 # ok 23 cpuinfo_match_SVE2 F64MM
8256 11:16:44.553114 # ok 24 sigill_SVE2 F64MM
8257 11:16:44.553227 # # SVE2 BF16 present
8258 11:16:44.553340 # ok 25 cpuinfo_match_SVE2 BF16
8259 11:16:44.553456 # ok 26 sigill_SVE2 BF16
8260 11:16:44.553596 # ok 27 cpuinfo_match_SVE2 EBF16
8261 11:16:44.553732 # ok 28 # SKIP sigill_SVE2 EBF16
8262 11:16:44.553850 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8263 11:16:44.571065 ok 45 selftests: arm64: hwcap
8264 11:16:44.709165 # selftests: arm64: ptrace
8265 11:16:44.847954 # TAP version 13
8266 11:16:44.848300 # 1..7
8267 11:16:44.848488 # # Parent is 4590, child is 4591
8268 11:16:44.848637 # ok 1 read_tpidr_one
8269 11:16:44.849009 # ok 2 write_tpidr_one
8270 11:16:44.849146 # ok 3 verify_tpidr_one
8271 11:16:44.849289 # ok 4 count_tpidrs
8272 11:16:44.849430 # ok 5 tpidr2_write
8273 11:16:44.849570 # ok 6 tpidr2_read
8274 11:16:44.849727 # ok 7 write_tpidr_only
8275 11:16:44.849868 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8276 11:16:44.868538 ok 46 selftests: arm64: ptrace
8277 11:16:44.957597 # selftests: arm64: syscall-abi
8278 11:16:47.547930 # TAP version 13
8279 11:16:47.548153 # 1..514
8280 11:16:47.548228 # # SME with FA64
8281 11:16:47.548523 # ok 1 getpid() FPSIMD
8282 11:16:47.548637 # ok 2 getpid() SVE VL 256
8283 11:16:47.548725 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8284 11:16:47.548799 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8285 11:16:47.548871 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8286 11:16:47.548942 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8287 11:16:47.549040 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8288 11:16:47.549128 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8289 11:16:47.549209 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8290 11:16:47.549289 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8291 11:16:47.549384 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8292 11:16:47.549466 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8293 11:16:47.549548 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8294 11:16:47.549643 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8295 11:16:47.549730 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8296 11:16:47.549807 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8297 11:16:47.549899 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8298 11:16:47.549981 # ok 18 getpid() SVE VL 240
8299 11:16:47.554583 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8300 11:16:47.554804 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8301 11:16:47.555020 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8302 11:16:47.555166 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8303 11:16:47.555314 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8304 11:16:47.555459 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8305 11:16:47.555636 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8306 11:16:47.555771 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8307 11:16:47.555913 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8308 11:16:47.556055 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8309 11:16:47.556196 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8310 11:16:47.556337 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8311 11:16:47.556515 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8312 11:16:47.556648 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8313 11:16:47.556789 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8314 11:16:47.556930 # ok 34 getpid() SVE VL 224
8315 11:16:47.557070 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8316 11:16:47.557260 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8317 11:16:47.557430 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8318 11:16:47.557574 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8319 11:16:47.557783 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8320 11:16:47.557931 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8321 11:16:47.558091 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8322 11:16:47.558224 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8323 11:16:47.558340 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8324 11:16:47.558467 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8325 11:16:47.558583 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8326 11:16:47.558703 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8327 11:16:47.558819 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8328 11:16:47.558932 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8329 11:16:47.562496 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8330 11:16:47.562692 # ok 50 getpid() SVE VL 208
8331 11:16:47.562900 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8332 11:16:47.563058 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8333 11:16:47.563201 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8334 11:16:47.563347 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8335 11:16:47.563527 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8336 11:16:47.563687 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8337 11:16:47.563823 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8338 11:16:47.564007 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8339 11:16:47.564196 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8340 11:16:47.564405 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8341 11:16:47.564582 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8342 11:16:47.564749 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8343 11:16:47.564915 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8344 11:16:47.565085 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8345 11:16:47.565257 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8346 11:16:47.565422 # ok 66 getpid() SVE VL 192
8347 11:16:47.565585 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8348 11:16:47.565772 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8349 11:16:47.565980 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8350 11:16:47.566132 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8351 11:16:47.566259 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8352 11:16:47.566383 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8353 11:16:47.566506 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8354 11:16:47.566630 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8355 11:16:47.566756 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8356 11:16:47.566887 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8357 11:16:47.567012 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8358 11:16:47.567135 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8359 11:16:47.567259 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8360 11:16:47.567382 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8361 11:16:47.567506 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8362 11:16:47.567633 # ok 82 getpid() SVE VL 176
8363 11:16:47.567760 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8364 11:16:47.570150 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8365 11:16:47.570674 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8366 11:16:47.570788 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8367 11:16:47.570885 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8368 11:16:47.570974 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8369 11:16:47.571059 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8370 11:16:47.571164 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8371 11:16:47.571252 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8372 11:16:47.571338 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8373 11:16:47.571425 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8374 11:16:47.571511 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8375 11:16:47.571614 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8376 11:16:47.571703 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8377 11:16:47.571788 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8378 11:16:47.571890 # ok 98 getpid() SVE VL 160
8379 11:16:50.033739 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8380 11:16:50.034086 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8381 11:16:50.034654 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8382 11:16:50.034874 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8383 11:16:50.035061 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8384 11:16:50.035276 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8385 11:16:50.035448 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8386 11:16:50.035606 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8387 11:16:50.035764 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8388 11:16:50.035919 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8389 11:16:50.036107 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8390 11:16:50.036266 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8391 11:16:50.036421 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8392 11:16:50.036576 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8393 11:16:50.036730 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8394 11:16:50.036884 # ok 114 getpid() SVE VL 144
8395 11:16:50.037037 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8396 11:16:50.037190 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8397 11:16:50.037342 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8398 11:16:50.037531 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8399 11:16:50.037701 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8400 11:16:50.037859 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8401 11:16:50.038012 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8402 11:16:50.038165 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8403 11:16:50.038318 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8404 11:16:50.038469 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8405 11:16:50.038611 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8406 11:16:50.038751 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8407 11:16:50.038908 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8408 11:16:50.039056 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8409 11:16:50.039229 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8410 11:16:50.039401 # ok 130 getpid() SVE VL 128
8411 11:16:50.039575 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8412 11:16:50.039739 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8413 11:16:50.039910 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8414 11:16:50.040113 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8415 11:16:50.040246 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8416 11:16:50.040358 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8417 11:16:50.042358 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8418 11:16:50.042668 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8419 11:16:50.042769 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8420 11:16:50.042878 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8421 11:16:50.042963 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8422 11:16:50.043061 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8423 11:16:50.043159 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8424 11:16:50.043266 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8425 11:16:50.043568 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8426 11:16:50.043668 # ok 146 getpid() SVE VL 112
8427 11:16:50.043768 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8428 11:16:50.043866 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8429 11:16:50.044224 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8430 11:16:50.044406 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8431 11:16:50.044570 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8432 11:16:50.044758 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8433 11:16:50.044921 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8434 11:16:50.045079 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8435 11:16:50.045242 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8436 11:16:50.045423 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8437 11:16:50.045609 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8438 11:16:50.045766 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8439 11:16:50.045888 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8440 11:16:50.046001 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8441 11:16:50.046118 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8442 11:16:50.046258 # ok 162 getpid() SVE VL 96
8443 11:16:50.046375 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8444 11:16:50.046488 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8445 11:16:50.046601 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8446 11:16:50.046712 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8447 11:16:50.050730 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8448 11:16:50.050937 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8449 11:16:50.051090 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8450 11:16:50.051310 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8451 11:16:50.051528 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8452 11:16:50.051743 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8453 11:16:50.053044 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8454 11:16:50.053206 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8455 11:16:50.053312 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8456 11:16:50.053399 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8457 11:16:50.053484 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8458 11:16:50.053567 # ok 178 getpid() SVE VL 80
8459 11:16:50.053667 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8460 11:16:50.053814 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8461 11:16:50.053938 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8462 11:16:50.054061 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8463 11:16:50.054183 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8464 11:16:50.054305 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8465 11:16:50.054427 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8466 11:16:50.054551 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8467 11:16:50.054674 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8468 11:16:50.054761 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8469 11:16:50.054823 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8470 11:16:50.054880 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8471 11:16:50.054937 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8472 11:16:50.054995 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8473 11:16:50.055053 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8474 11:16:50.055125 # ok 194 getpid() SVE VL 64
8475 11:16:50.055185 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8476 11:16:52.292232 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8477 11:16:52.292666 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8478 11:16:52.292770 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8479 11:16:52.292859 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8480 11:16:52.292946 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8481 11:16:52.293050 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8482 11:16:52.293135 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8483 11:16:52.293218 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8484 11:16:52.293318 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8485 11:16:52.293404 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8486 11:16:52.293502 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8487 11:16:52.293601 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8488 11:16:52.293715 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8489 11:16:52.293815 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8490 11:16:52.298007 # ok 210 getpid() SVE VL 48
8491 11:16:52.298313 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8492 11:16:52.298415 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8493 11:16:52.298501 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8494 11:16:52.298599 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8495 11:16:52.298682 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8496 11:16:52.298779 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8497 11:16:52.298864 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8498 11:16:52.298960 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8499 11:16:52.299062 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8500 11:16:52.299158 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8501 11:16:52.299457 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8502 11:16:52.299557 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8503 11:16:52.299655 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8504 11:16:52.299739 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8505 11:16:52.300080 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8506 11:16:52.300290 # ok 226 getpid() SVE VL 32
8507 11:16:52.300470 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8508 11:16:52.300687 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8509 11:16:52.300847 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8510 11:16:52.301036 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8511 11:16:52.301205 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8512 11:16:52.301365 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8513 11:16:52.301525 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8514 11:16:52.301959 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8515 11:16:52.302155 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8516 11:16:52.302322 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8517 11:16:52.302477 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8518 11:16:52.302625 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8519 11:16:52.302772 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8520 11:16:52.302918 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8521 11:16:52.303068 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8522 11:16:52.303214 # ok 242 getpid() SVE VL 16
8523 11:16:52.306149 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8524 11:16:52.306509 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8525 11:16:52.306647 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8526 11:16:52.307201 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8527 11:16:52.307374 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8528 11:16:52.307530 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8529 11:16:52.307676 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8530 11:16:52.308035 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8531 11:16:52.308184 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8532 11:16:52.308331 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8533 11:16:52.308475 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8534 11:16:52.308619 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8535 11:16:52.308766 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8536 11:16:52.308911 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8537 11:16:52.309318 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8538 11:16:52.309545 # ok 258 sched_yield() FPSIMD
8539 11:16:52.309805 # ok 259 sched_yield() SVE VL 256
8540 11:16:52.309999 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8541 11:16:52.310132 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8542 11:16:52.314007 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8543 11:16:52.314448 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8544 11:16:52.314637 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8545 11:16:52.314852 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8546 11:16:52.315055 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8547 11:16:52.315250 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8548 11:16:52.315451 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8549 11:16:52.315605 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8550 11:16:52.315740 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8551 11:16:52.315855 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8552 11:16:52.315969 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8553 11:16:52.316120 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8554 11:16:52.316278 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8555 11:16:52.316467 # ok 275 sched_yield() SVE VL 240
8556 11:16:52.316675 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8557 11:16:52.316860 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8558 11:16:52.317001 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8559 11:16:52.317115 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8560 11:16:52.317226 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8561 11:16:52.317337 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8562 11:16:52.317447 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8563 11:16:52.317557 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8564 11:16:52.317696 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8565 11:16:52.317847 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8566 11:16:52.317970 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8567 11:16:52.318082 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8568 11:16:52.318223 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8569 11:16:52.318340 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8570 11:16:54.335822 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8571 11:16:54.336174 # ok 291 sched_yield() SVE VL 224
8572 11:16:54.336398 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8573 11:16:54.336605 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8574 11:16:54.336802 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8575 11:16:54.336962 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8576 11:16:54.337186 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8577 11:16:54.337372 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8578 11:16:54.337543 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8579 11:16:54.337810 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8580 11:16:54.338017 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8581 11:16:54.338178 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8582 11:16:54.338320 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8583 11:16:54.338460 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8584 11:16:54.338638 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8585 11:16:54.338772 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8586 11:16:54.338914 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8587 11:16:54.339056 # ok 307 sched_yield() SVE VL 208
8588 11:16:54.339194 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8589 11:16:54.346271 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8590 11:16:54.346489 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8591 11:16:54.346724 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8592 11:16:54.346886 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8593 11:16:54.347014 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8594 11:16:54.347129 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8595 11:16:54.347267 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8596 11:16:54.347412 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8597 11:16:54.347552 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8598 11:16:54.347754 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8599 11:16:54.347959 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8600 11:16:54.348142 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8601 11:16:54.348272 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8602 11:16:54.348428 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8603 11:16:54.348569 # ok 323 sched_yield() SVE VL 192
8604 11:16:54.348744 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8605 11:16:54.348881 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8606 11:16:54.349001 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8607 11:16:54.349117 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8608 11:16:54.349275 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8609 11:16:54.349414 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8610 11:16:54.349532 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8611 11:16:54.349672 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8612 11:16:54.349877 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8613 11:16:54.350101 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8614 11:16:54.350270 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8615 11:16:54.350455 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8616 11:16:54.350667 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8617 11:16:54.350884 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8618 11:16:54.351143 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8619 11:16:54.351338 # ok 339 sched_yield() SVE VL 176
8620 11:16:54.351492 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8621 11:16:54.351655 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8622 11:16:54.351831 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8623 11:16:54.351979 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8624 11:16:54.352165 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8625 11:16:54.352392 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8626 11:16:54.352556 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8627 11:16:54.352700 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8628 11:16:54.352843 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8629 11:16:54.352994 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8630 11:16:54.353369 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8631 11:16:54.353569 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8632 11:16:54.353748 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8633 11:16:54.353872 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8634 11:16:54.353991 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8635 11:16:54.354106 # ok 355 sched_yield() SVE VL 160
8636 11:16:54.354220 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8637 11:16:54.354334 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8638 11:16:54.354447 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8639 11:16:54.354560 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8640 11:16:54.354672 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8641 11:16:54.354785 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8642 11:16:54.354897 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8643 11:16:54.355010 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8644 11:16:54.355124 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8645 11:16:54.355237 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8646 11:16:54.355350 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8647 11:16:54.355488 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8648 11:16:54.355607 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8649 11:16:54.355721 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8650 11:16:54.355835 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8651 11:16:54.355948 # ok 371 sched_yield() SVE VL 144
8652 11:16:54.358260 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8653 11:16:54.358607 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8654 11:16:54.358719 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8655 11:16:54.358814 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8656 11:16:54.358920 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8657 11:16:56.416339 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8658 11:16:56.421766 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8659 11:16:56.421939 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8660 11:16:56.422078 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8661 11:16:56.422209 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8662 11:16:56.422328 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8663 11:16:56.422442 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8664 11:16:56.422557 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8665 11:16:56.422679 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8666 11:16:56.422805 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8667 11:16:56.422926 # ok 387 sched_yield() SVE VL 128
8668 11:16:56.423050 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8669 11:16:56.423175 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8670 11:16:56.423294 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8671 11:16:56.423419 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8672 11:16:56.423538 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8673 11:16:56.423655 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8674 11:16:56.423783 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8675 11:16:56.423901 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8676 11:16:56.424027 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8677 11:16:56.424146 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8678 11:16:56.424261 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8679 11:16:56.424386 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8680 11:16:56.424507 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8681 11:16:56.424625 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8682 11:16:56.424754 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8683 11:16:56.424873 # ok 403 sched_yield() SVE VL 112
8684 11:16:56.424999 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8685 11:16:56.425127 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8686 11:16:56.425244 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8687 11:16:56.425371 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8688 11:16:56.425497 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8689 11:16:56.425612 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8690 11:16:56.425756 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8691 11:16:56.425888 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8692 11:16:56.426009 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8693 11:16:56.426134 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8694 11:16:56.426259 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8695 11:16:56.426374 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8696 11:16:56.426500 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8697 11:16:56.426621 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8698 11:16:56.426748 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8699 11:16:56.430146 # ok 419 sched_yield() SVE VL 96
8700 11:16:56.430904 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8701 11:16:56.431088 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8702 11:16:56.431263 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8703 11:16:56.431447 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8704 11:16:56.431610 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8705 11:16:56.431769 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8706 11:16:56.431912 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8707 11:16:56.432113 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8708 11:16:56.432260 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8709 11:16:56.432426 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8710 11:16:56.432572 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8711 11:16:56.432720 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8712 11:16:56.432886 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8713 11:16:56.433062 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8714 11:16:56.433234 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8715 11:16:56.433378 # ok 435 sched_yield() SVE VL 80
8716 11:16:56.433531 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8717 11:16:56.433710 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8718 11:16:56.433856 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8719 11:16:56.434024 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8720 11:16:56.434169 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8721 11:16:56.434321 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8722 11:16:56.434513 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8723 11:16:56.434664 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8724 11:16:56.434830 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8725 11:16:56.434973 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8726 11:16:56.435136 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8727 11:16:56.435284 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8728 11:16:56.435429 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8729 11:16:56.438130 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8730 11:16:56.438462 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8731 11:16:56.438569 # ok 451 sched_yield() SVE VL 64
8732 11:16:56.438673 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8733 11:16:56.438761 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8734 11:16:56.438860 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8735 11:16:56.438959 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8736 11:16:56.439067 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8737 11:16:56.439408 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8738 11:16:56.439517 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8739 11:16:56.439618 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8740 11:16:56.439969 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8741 11:16:56.440097 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8742 11:16:56.440183 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8743 11:16:56.440282 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8744 11:16:57.096464 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8745 11:16:57.096710 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8746 11:16:57.096801 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8747 11:16:57.097116 # ok 467 sched_yield() SVE VL 48
8748 11:16:57.097320 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8749 11:16:57.097490 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8750 11:16:57.097663 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8751 11:16:57.097805 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8752 11:16:57.097952 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8753 11:16:57.098071 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8754 11:16:57.098185 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8755 11:16:57.098299 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8756 11:16:57.098411 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8757 11:16:57.098524 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8758 11:16:57.098637 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8759 11:16:57.105429 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8760 11:16:57.105633 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8761 11:16:57.105797 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8762 11:16:57.105944 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8763 11:16:57.106066 # ok 483 sched_yield() SVE VL 32
8764 11:16:57.106182 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8765 11:16:57.106709 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8766 11:16:57.107086 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8767 11:16:57.107240 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8768 11:16:57.107370 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8769 11:16:57.107521 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8770 11:16:57.107663 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8771 11:16:57.107848 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8772 11:16:57.108046 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8773 11:16:57.108299 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8774 11:16:57.108477 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8775 11:16:57.108695 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8776 11:16:57.108881 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8777 11:16:57.109044 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8778 11:16:57.109206 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8779 11:16:57.109369 # ok 499 sched_yield() SVE VL 16
8780 11:16:57.109521 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8781 11:16:57.109697 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8782 11:16:57.109845 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8783 11:16:57.109975 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8784 11:16:57.110095 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8785 11:16:57.110210 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8786 11:16:57.110328 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8787 11:16:57.110443 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8788 11:16:57.110558 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8789 11:16:57.110673 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8790 11:16:57.110786 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8791 11:16:57.110901 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8792 11:16:57.111016 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8793 11:16:57.114083 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8794 11:16:57.114263 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8795 11:16:57.114613 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8796 11:16:57.114762 ok 47 selftests: arm64: syscall-abi
8797 11:16:57.156284 # selftests: arm64: tpidr2
8798 11:16:57.308797 # TAP version 13
8799 11:16:57.309115 # 1..5
8800 11:16:57.309314 # # PID: 4625
8801 11:16:57.309466 # ok 1 default_value
8802 11:16:57.309827 # ok 2 write_read
8803 11:16:57.309973 # ok 3 write_sleep_read
8804 11:16:57.310105 # ok 4 write_fork_read
8805 11:16:57.310233 # ok 5 write_clone_read
8806 11:16:57.310359 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8807 11:16:57.319115 ok 48 selftests: arm64: tpidr2
8808 11:16:57.797910 arm64_tags_test pass
8809 11:16:57.798349 arm64_run_tags_test_sh pass
8810 11:16:57.798774 arm64_fake_sigreturn_bad_magic pass
8811 11:16:57.798957 arm64_fake_sigreturn_bad_size pass
8812 11:16:57.799127 arm64_fake_sigreturn_bad_size_for_magic0 pass
8813 11:16:57.799355 arm64_fake_sigreturn_duplicated_fpsimd pass
8814 11:16:57.799619 arm64_fake_sigreturn_misaligned_sp pass
8815 11:16:57.799857 arm64_fake_sigreturn_missing_fpsimd pass
8816 11:16:57.800070 arm64_fake_sigreturn_sme_change_vl pass
8817 11:16:57.800312 arm64_fake_sigreturn_sve_change_vl pass
8818 11:16:57.800498 arm64_mangle_pstate_invalid_compat_toggle pass
8819 11:16:57.800691 arm64_mangle_pstate_invalid_daif_bits pass
8820 11:16:57.800876 arm64_mangle_pstate_invalid_mode_el1h pass
8821 11:16:57.801081 arm64_mangle_pstate_invalid_mode_el1t pass
8822 11:16:57.801264 arm64_mangle_pstate_invalid_mode_el2h pass
8823 11:16:57.801471 arm64_mangle_pstate_invalid_mode_el2t pass
8824 11:16:57.801667 arm64_mangle_pstate_invalid_mode_el3h pass
8825 11:16:57.801876 arm64_mangle_pstate_invalid_mode_el3t pass
8826 11:16:57.802060 arm64_sme_trap_no_sm pass
8827 11:16:57.802258 arm64_sme_trap_non_streaming skip
8828 11:16:57.802434 arm64_sme_trap_za pass
8829 11:16:57.802637 arm64_sme_vl pass
8830 11:16:57.802818 arm64_ssve_regs pass
8831 11:16:57.803020 arm64_sve_regs pass
8832 11:16:57.803204 arm64_sve_vl pass
8833 11:16:57.803404 arm64_za_no_regs pass
8834 11:16:57.803590 arm64_za_regs pass
8835 11:16:57.803789 arm64_pac_global_corrupt_pac pass
8836 11:16:57.803972 arm64_pac_global_pac_instructions_not_nop pass
8837 11:16:57.804247 arm64_pac_global_pac_instructions_not_nop_generic pass
8838 11:16:57.804442 arm64_pac_global_single_thread_different_keys pass
8839 11:16:57.804641 arm64_pac_global_exec_changed_keys pass
8840 11:16:57.804823 arm64_pac_global_context_switch_keep_keys pass
8841 11:16:57.805018 arm64_pac_global_context_switch_keep_keys_generic pass
8842 11:16:57.805207 arm64_pac pass
8843 11:16:57.805403 arm64_fp-stress_FPSIMD-0-0 pass
8844 11:16:57.805594 arm64_fp-stress_SVE-VL-256-0 pass
8845 11:16:57.806067 arm64_fp-stress_SVE-VL-240-0 pass
8846 11:16:57.806246 arm64_fp-stress_SVE-VL-224-0 pass
8847 11:16:57.806412 arm64_fp-stress_SVE-VL-208-0 pass
8848 11:16:57.806572 arm64_fp-stress_SVE-VL-192-0 pass
8849 11:16:57.806709 arm64_fp-stress_SVE-VL-176-0 pass
8850 11:16:57.806868 arm64_fp-stress_SVE-VL-160-0 pass
8851 11:16:57.807026 arm64_fp-stress_SVE-VL-144-0 pass
8852 11:16:57.807215 arm64_fp-stress_SVE-VL-128-0 pass
8853 11:16:57.807421 arm64_fp-stress_SVE-VL-112-0 pass
8854 11:16:57.807641 arm64_fp-stress_SVE-VL-96-0 pass
8855 11:16:57.807791 arm64_fp-stress_SVE-VL-80-0 pass
8856 11:16:57.807981 arm64_fp-stress_SVE-VL-64-0 pass
8857 11:16:57.808202 arm64_fp-stress_SVE-VL-48-0 pass
8858 11:16:57.808406 arm64_fp-stress_SVE-VL-32-0 pass
8859 11:16:57.808607 arm64_fp-stress_SVE-VL-16-0 pass
8860 11:16:57.808821 arm64_fp-stress_SSVE-VL-256-0 pass
8861 11:16:57.809020 arm64_fp-stress_ZA-VL-256-0 pass
8862 11:16:57.809197 arm64_fp-stress_SSVE-VL-128-0 pass
8863 11:16:57.809367 arm64_fp-stress_ZA-VL-128-0 pass
8864 11:16:57.809943 arm64_fp-stress_SSVE-VL-64-0 pass
8865 11:16:57.810101 arm64_fp-stress_ZA-VL-64-0 pass
8866 11:16:57.810224 arm64_fp-stress_SSVE-VL-32-0 pass
8867 11:16:57.810342 arm64_fp-stress_ZA-VL-32-0 pass
8868 11:16:57.810459 arm64_fp-stress_SSVE-VL-16-0 pass
8869 11:16:57.810574 arm64_fp-stress_ZA-VL-16-0 pass
8870 11:16:57.810689 arm64_fp-stress pass
8871 11:16:57.810804 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8872 11:16:57.810918 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8873 11:16:57.811034 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8874 11:16:57.811149 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8875 11:16:57.811265 arm64_sve-ptrace_Set_SVE_VL_16 pass
8876 11:16:57.811381 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8877 11:16:57.811496 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8878 11:16:57.811611 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8879 11:16:57.811725 arm64_sve-ptrace_Set_SVE_VL_32 pass
8880 11:16:57.811840 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8881 11:16:57.811955 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8882 11:16:57.812069 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8883 11:16:57.812182 arm64_sve-ptrace_Set_SVE_VL_48 pass
8884 11:16:57.812294 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8885 11:16:57.812405 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8886 11:16:57.812517 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8887 11:16:57.812630 arm64_sve-ptrace_Set_SVE_VL_64 pass
8888 11:16:57.812745 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8889 11:16:57.812859 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8890 11:16:57.812975 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8891 11:16:57.813089 arm64_sve-ptrace_Set_SVE_VL_80 pass
8892 11:16:57.814062 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8893 11:16:57.814299 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8894 11:16:57.814757 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8895 11:16:57.814968 arm64_sve-ptrace_Set_SVE_VL_96 pass
8896 11:16:57.815173 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8897 11:16:57.815393 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8898 11:16:57.815582 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8899 11:16:57.815769 arm64_sve-ptrace_Set_SVE_VL_112 pass
8900 11:16:57.816001 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8901 11:16:57.816211 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8902 11:16:57.816405 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8903 11:16:57.816627 arm64_sve-ptrace_Set_SVE_VL_128 pass
8904 11:16:57.816847 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8905 11:16:57.817048 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8906 11:16:57.817254 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8907 11:16:57.817423 arm64_sve-ptrace_Set_SVE_VL_144 pass
8908 11:16:57.817618 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8909 11:16:57.817853 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8910 11:16:57.818101 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8911 11:16:57.818257 arm64_sve-ptrace_Set_SVE_VL_160 pass
8912 11:16:57.818402 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8913 11:16:57.818544 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8914 11:16:57.818686 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8915 11:16:57.818825 arm64_sve-ptrace_Set_SVE_VL_176 pass
8916 11:16:57.818965 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8917 11:16:57.819102 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8918 11:16:57.819238 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8919 11:16:57.819374 arm64_sve-ptrace_Set_SVE_VL_192 pass
8920 11:16:57.819513 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8921 11:16:57.819652 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8922 11:16:57.819794 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8923 11:16:57.819934 arm64_sve-ptrace_Set_SVE_VL_208 pass
8924 11:16:57.820073 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8925 11:16:57.820213 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8926 11:16:57.822021 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8927 11:16:57.822231 arm64_sve-ptrace_Set_SVE_VL_224 pass
8928 11:16:57.822623 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8929 11:16:57.822809 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8930 11:16:57.823009 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8931 11:16:57.823193 arm64_sve-ptrace_Set_SVE_VL_240 pass
8932 11:16:57.823375 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8933 11:16:57.823608 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8934 11:16:57.823807 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8935 11:16:57.823976 arm64_sve-ptrace_Set_SVE_VL_256 pass
8936 11:16:57.824135 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8937 11:16:57.824296 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8938 11:16:57.824456 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8939 11:16:57.824614 arm64_sve-ptrace_Set_SVE_VL_272 pass
8940 11:16:57.824770 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8941 11:16:57.824932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8942 11:16:57.825085 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8943 11:16:57.825254 arm64_sve-ptrace_Set_SVE_VL_288 pass
8944 11:16:57.825493 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8945 11:16:57.826001 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8946 11:16:57.826153 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8947 11:16:57.826273 arm64_sve-ptrace_Set_SVE_VL_304 pass
8948 11:16:57.826389 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8949 11:16:57.826505 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8950 11:16:57.826619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8951 11:16:57.826734 arm64_sve-ptrace_Set_SVE_VL_320 pass
8952 11:16:57.826849 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8953 11:16:57.826965 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8954 11:16:57.827080 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8955 11:16:57.827195 arm64_sve-ptrace_Set_SVE_VL_336 pass
8956 11:16:57.827310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8957 11:16:57.827426 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8958 11:16:57.827542 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8959 11:16:57.827657 arm64_sve-ptrace_Set_SVE_VL_352 pass
8960 11:16:57.827772 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8961 11:16:57.827886 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8962 11:16:57.828029 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8963 11:16:57.828152 arm64_sve-ptrace_Set_SVE_VL_368 pass
8964 11:16:57.829977 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8965 11:16:57.830403 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8966 11:16:57.830570 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8967 11:16:57.830692 arm64_sve-ptrace_Set_SVE_VL_384 pass
8968 11:16:57.830813 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8969 11:16:57.830936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8970 11:16:57.831079 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8971 11:16:57.831205 arm64_sve-ptrace_Set_SVE_VL_400 pass
8972 11:16:57.831349 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8973 11:16:57.831498 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8974 11:16:57.831645 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8975 11:16:57.831824 arm64_sve-ptrace_Set_SVE_VL_416 pass
8976 11:16:57.831952 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8977 11:16:57.832069 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8978 11:16:57.832168 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8979 11:16:57.832289 arm64_sve-ptrace_Set_SVE_VL_432 pass
8980 11:16:57.832421 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
8981 11:16:57.832529 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
8982 11:16:57.832640 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
8983 11:16:57.832732 arm64_sve-ptrace_Set_SVE_VL_448 pass
8984 11:16:57.832850 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
8985 11:16:57.832962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
8986 11:16:57.845188 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
8987 11:16:57.845322 arm64_sve-ptrace_Set_SVE_VL_464 pass
8988 11:16:57.845670 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
8989 11:16:57.845860 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
8990 11:16:57.846050 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
8991 11:16:57.846229 arm64_sve-ptrace_Set_SVE_VL_480 pass
8992 11:16:57.846461 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
8993 11:16:57.846610 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
8994 11:16:57.846789 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
8995 11:16:57.846937 arm64_sve-ptrace_Set_SVE_VL_496 pass
8996 11:16:57.847059 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
8997 11:16:57.847251 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
8998 11:16:57.847418 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
8999 11:16:57.847581 arm64_sve-ptrace_Set_SVE_VL_512 pass
9000 11:16:57.847731 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
9001 11:16:57.847885 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
9002 11:16:57.848042 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
9003 11:16:57.848197 arm64_sve-ptrace_Set_SVE_VL_528 pass
9004 11:16:57.848333 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
9005 11:16:57.848488 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
9006 11:16:57.848627 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
9007 11:16:57.848797 arm64_sve-ptrace_Set_SVE_VL_544 pass
9008 11:16:57.848961 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
9009 11:16:57.849148 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
9010 11:16:57.849309 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
9011 11:16:57.849453 arm64_sve-ptrace_Set_SVE_VL_560 pass
9012 11:16:57.849603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
9013 11:16:57.849831 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
9014 11:16:57.850066 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
9015 11:16:57.850252 arm64_sve-ptrace_Set_SVE_VL_576 pass
9016 11:16:57.850394 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
9017 11:16:57.850534 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
9018 11:16:57.850674 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
9019 11:16:57.850813 arm64_sve-ptrace_Set_SVE_VL_592 pass
9020 11:16:57.850953 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
9021 11:16:57.851094 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
9022 11:16:57.851234 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
9023 11:16:57.851373 arm64_sve-ptrace_Set_SVE_VL_608 pass
9024 11:16:57.851511 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
9025 11:16:57.851651 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
9026 11:16:57.853933 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
9027 11:16:57.854344 arm64_sve-ptrace_Set_SVE_VL_624 pass
9028 11:16:57.854530 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
9029 11:16:57.854682 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
9030 11:16:57.854869 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
9031 11:16:57.855033 arm64_sve-ptrace_Set_SVE_VL_640 pass
9032 11:16:57.855188 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
9033 11:16:57.855342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
9034 11:16:57.855492 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
9035 11:16:57.855667 arm64_sve-ptrace_Set_SVE_VL_656 pass
9036 11:16:57.855820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
9037 11:16:57.855957 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
9038 11:16:57.856086 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
9039 11:16:57.856240 arm64_sve-ptrace_Set_SVE_VL_672 pass
9040 11:16:57.856363 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
9041 11:16:57.856484 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
9042 11:16:57.856598 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
9043 11:16:57.856742 arm64_sve-ptrace_Set_SVE_VL_688 pass
9044 11:16:57.856881 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
9045 11:16:57.857023 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
9046 11:16:57.857171 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
9047 11:16:57.857321 arm64_sve-ptrace_Set_SVE_VL_704 pass
9048 11:16:57.857465 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
9049 11:16:57.857622 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
9050 11:16:57.858216 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
9051 11:16:57.858386 arm64_sve-ptrace_Set_SVE_VL_720 pass
9052 11:16:57.858567 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
9053 11:16:57.858707 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
9054 11:16:57.858848 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
9055 11:16:57.858990 arm64_sve-ptrace_Set_SVE_VL_736 pass
9056 11:16:57.859131 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
9057 11:16:57.859271 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
9058 11:16:57.859410 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
9059 11:16:57.859550 arm64_sve-ptrace_Set_SVE_VL_752 pass
9060 11:16:57.859691 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
9061 11:16:57.861964 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
9062 11:16:57.862399 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
9063 11:16:57.862597 arm64_sve-ptrace_Set_SVE_VL_768 pass
9064 11:16:57.862768 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
9065 11:16:57.862912 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
9066 11:16:57.863122 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
9067 11:16:57.863309 arm64_sve-ptrace_Set_SVE_VL_784 pass
9068 11:16:57.863479 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
9069 11:16:57.863623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
9070 11:16:57.863772 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
9071 11:16:57.863961 arm64_sve-ptrace_Set_SVE_VL_800 pass
9072 11:16:57.864198 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
9073 11:16:57.864354 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
9074 11:16:57.864481 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
9075 11:16:57.864670 arm64_sve-ptrace_Set_SVE_VL_816 pass
9076 11:16:57.864820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
9077 11:16:57.865008 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
9078 11:16:57.865161 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
9079 11:16:57.865285 arm64_sve-ptrace_Set_SVE_VL_832 pass
9080 11:16:57.865408 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
9081 11:16:57.865528 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
9082 11:16:57.865694 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
9083 11:16:57.865819 arm64_sve-ptrace_Set_SVE_VL_848 pass
9084 11:16:57.865944 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
9085 11:16:57.866066 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
9086 11:16:57.866187 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
9087 11:16:57.866302 arm64_sve-ptrace_Set_SVE_VL_864 pass
9088 11:16:57.866416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
9089 11:16:57.866530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
9090 11:16:57.866644 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
9091 11:16:57.866759 arm64_sve-ptrace_Set_SVE_VL_880 pass
9092 11:16:57.866873 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
9093 11:16:57.866987 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
9094 11:16:57.867100 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
9095 11:16:57.867234 arm64_sve-ptrace_Set_SVE_VL_896 pass
9096 11:16:57.870092 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
9097 11:16:57.870526 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
9098 11:16:57.870739 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
9099 11:16:57.870886 arm64_sve-ptrace_Set_SVE_VL_912 pass
9100 11:16:57.871060 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
9101 11:16:57.871260 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
9102 11:16:57.871504 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
9103 11:16:57.871708 arm64_sve-ptrace_Set_SVE_VL_928 pass
9104 11:16:57.871871 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
9105 11:16:57.872028 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
9106 11:16:57.872155 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
9107 11:16:57.872331 arm64_sve-ptrace_Set_SVE_VL_944 pass
9108 11:16:57.872522 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
9109 11:16:57.872704 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
9110 11:16:57.872926 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
9111 11:16:57.873097 arm64_sve-ptrace_Set_SVE_VL_960 pass
9112 11:16:57.873246 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
9113 11:16:57.873477 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
9114 11:16:57.874067 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
9115 11:16:57.874219 arm64_sve-ptrace_Set_SVE_VL_976 pass
9116 11:16:57.874364 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
9117 11:16:57.874485 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
9118 11:16:57.877948 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
9119 11:16:57.878297 arm64_sve-ptrace_Set_SVE_VL_992 pass
9120 11:16:57.878478 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
9121 11:16:57.878655 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
9122 11:16:57.878877 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
9123 11:16:57.879054 arm64_sve-ptrace_Set_SVE_VL_1008 pass
9124 11:16:57.879215 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
9125 11:16:57.879379 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
9126 11:16:57.879539 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
9127 11:16:57.879733 arm64_sve-ptrace_Set_SVE_VL_1024 pass
9128 11:16:57.879897 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
9129 11:16:57.880058 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
9130 11:16:57.880217 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
9131 11:16:57.880375 arm64_sve-ptrace_Set_SVE_VL_1040 pass
9132 11:16:57.880534 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
9133 11:16:57.880696 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
9134 11:16:57.880858 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
9135 11:16:57.881010 arm64_sve-ptrace_Set_SVE_VL_1056 pass
9136 11:16:57.881207 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
9137 11:16:57.881340 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
9138 11:16:57.881455 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
9139 11:16:57.881581 arm64_sve-ptrace_Set_SVE_VL_1072 pass
9140 11:16:57.881767 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
9141 11:16:57.881904 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
9142 11:16:57.882020 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
9143 11:16:57.882133 arm64_sve-ptrace_Set_SVE_VL_1088 pass
9144 11:16:57.882249 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
9145 11:16:57.882363 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
9146 11:16:57.882476 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
9147 11:16:57.882588 arm64_sve-ptrace_Set_SVE_VL_1104 pass
9148 11:16:57.896447 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
9149 11:16:57.896914 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
9150 11:16:57.897091 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
9151 11:16:57.897312 arm64_sve-ptrace_Set_SVE_VL_1120 pass
9152 11:16:57.897524 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
9153 11:16:57.897721 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
9154 11:16:57.897861 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
9155 11:16:57.898039 arm64_sve-ptrace_Set_SVE_VL_1136 pass
9156 11:16:57.898237 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
9157 11:16:57.898408 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
9158 11:16:57.898566 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
9159 11:16:57.898730 arm64_sve-ptrace_Set_SVE_VL_1152 pass
9160 11:16:57.898952 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
9161 11:16:57.899132 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
9162 11:16:57.899335 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
9163 11:16:57.899525 arm64_sve-ptrace_Set_SVE_VL_1168 pass
9164 11:16:57.899695 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
9165 11:16:57.899830 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
9166 11:16:57.899964 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
9167 11:16:57.900113 arm64_sve-ptrace_Set_SVE_VL_1184 pass
9168 11:16:57.900281 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
9169 11:16:57.900440 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
9170 11:16:57.900635 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
9171 11:16:57.900792 arm64_sve-ptrace_Set_SVE_VL_1200 pass
9172 11:16:57.900983 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
9173 11:16:57.901163 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
9174 11:16:57.901356 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
9175 11:16:57.901539 arm64_sve-ptrace_Set_SVE_VL_1216 pass
9176 11:16:57.902159 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
9177 11:16:57.902330 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
9178 11:16:57.902472 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
9179 11:16:57.902612 arm64_sve-ptrace_Set_SVE_VL_1232 pass
9180 11:16:57.902753 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
9181 11:16:57.902892 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
9182 11:16:57.903031 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
9183 11:16:57.903169 arm64_sve-ptrace_Set_SVE_VL_1248 pass
9184 11:16:57.903304 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
9185 11:16:57.903474 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
9186 11:16:57.903608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
9187 11:16:57.903960 arm64_sve-ptrace_Set_SVE_VL_1264 pass
9188 11:16:57.904094 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
9189 11:16:57.904236 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
9190 11:16:57.904378 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
9191 11:16:57.904519 arm64_sve-ptrace_Set_SVE_VL_1280 pass
9192 11:16:57.904659 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
9193 11:16:57.904801 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
9194 11:16:57.905963 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
9195 11:16:57.906168 arm64_sve-ptrace_Set_SVE_VL_1296 pass
9196 11:16:57.906609 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
9197 11:16:57.906798 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
9198 11:16:57.906923 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
9199 11:16:57.907074 arm64_sve-ptrace_Set_SVE_VL_1312 pass
9200 11:16:57.907228 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
9201 11:16:57.907349 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
9202 11:16:57.907527 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
9203 11:16:57.907662 arm64_sve-ptrace_Set_SVE_VL_1328 pass
9204 11:16:57.907806 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
9205 11:16:57.907959 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
9206 11:16:57.908088 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
9207 11:16:57.908222 arm64_sve-ptrace_Set_SVE_VL_1344 pass
9208 11:16:57.908369 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
9209 11:16:57.908540 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
9210 11:16:57.908683 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
9211 11:16:57.908843 arm64_sve-ptrace_Set_SVE_VL_1360 pass
9212 11:16:57.909042 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
9213 11:16:57.909224 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
9214 11:16:57.909411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
9215 11:16:57.909564 arm64_sve-ptrace_Set_SVE_VL_1376 pass
9216 11:16:57.910174 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
9217 11:16:57.910343 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
9218 11:16:57.910469 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
9219 11:16:57.910587 arm64_sve-ptrace_Set_SVE_VL_1392 pass
9220 11:16:57.910702 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
9221 11:16:57.910818 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
9222 11:16:57.910931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
9223 11:16:57.911045 arm64_sve-ptrace_Set_SVE_VL_1408 pass
9224 11:16:57.911159 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
9225 11:16:57.911275 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9226 11:16:57.911389 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9227 11:16:57.911503 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9228 11:16:57.914174 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9229 11:16:57.914391 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9230 11:16:57.914621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9231 11:16:57.914805 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9232 11:16:57.914972 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9233 11:16:57.915136 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9234 11:16:57.915310 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9235 11:16:57.915570 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9236 11:16:57.915792 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9237 11:16:57.915990 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9238 11:16:57.916200 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9239 11:16:57.916410 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9240 11:16:57.916590 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9241 11:16:57.916762 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9242 11:16:57.916923 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9243 11:16:57.917063 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9244 11:16:57.917276 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9245 11:16:57.917435 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9246 11:16:57.917592 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9247 11:16:57.917797 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9248 11:16:57.917990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9249 11:16:57.918173 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9250 11:16:57.918363 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9251 11:16:57.918531 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9252 11:16:57.918675 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9253 11:16:57.918815 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9254 11:16:57.918955 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9255 11:16:57.919095 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9256 11:16:57.919235 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9257 11:16:57.919376 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9258 11:16:57.919516 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9259 11:16:57.919694 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9260 11:16:57.919828 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9261 11:16:57.919970 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9262 11:16:57.920111 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9263 11:16:57.920252 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9264 11:16:57.922063 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9265 11:16:57.922481 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9266 11:16:57.922655 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9267 11:16:57.922841 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9268 11:16:57.923028 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9269 11:16:57.923195 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9270 11:16:57.923394 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9271 11:16:57.923570 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9272 11:16:57.923777 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9273 11:16:57.924026 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9274 11:16:57.924213 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9275 11:16:57.924393 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9276 11:16:57.924567 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9277 11:16:57.924719 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9278 11:16:57.924852 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9279 11:16:57.924968 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9280 11:16:57.925119 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9281 11:16:57.925239 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9282 11:16:57.925343 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9283 11:16:57.925435 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9284 11:16:57.925525 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9285 11:16:57.925614 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9286 11:16:57.925759 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9287 11:16:57.925910 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9288 11:16:57.926049 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9289 11:16:57.926164 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9290 11:16:57.926303 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9291 11:16:57.926406 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9292 11:16:57.926515 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9293 11:16:57.926623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9294 11:16:57.926730 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9295 11:16:57.926816 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9296 11:16:57.930087 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9297 11:16:57.930265 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9298 11:16:57.930400 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9299 11:16:57.930543 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9300 11:16:57.930687 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9301 11:16:57.930803 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9302 11:16:57.930898 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9303 11:16:57.930997 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9304 11:16:57.931077 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9305 11:16:57.931144 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9306 11:16:57.931227 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9307 11:16:57.931293 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9308 11:16:57.945503 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9309 11:16:57.945831 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9310 11:16:57.946056 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9311 11:16:57.946225 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9312 11:16:57.946416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9313 11:16:57.946665 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9314 11:16:57.946875 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9315 11:16:57.947059 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9316 11:16:57.947302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9317 11:16:57.947463 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9318 11:16:57.947625 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9319 11:16:57.947801 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9320 11:16:57.947959 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9321 11:16:57.948100 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9322 11:16:57.948257 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9323 11:16:57.948416 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9324 11:16:57.948577 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9325 11:16:57.948773 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9326 11:16:57.948973 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9327 11:16:57.949158 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9328 11:16:57.949353 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9329 11:16:57.949555 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9330 11:16:57.949771 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9331 11:16:57.949970 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9332 11:16:57.950152 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9333 11:16:57.950335 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9334 11:16:57.950513 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9335 11:16:57.950654 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9336 11:16:57.950793 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9337 11:16:57.950938 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9338 11:16:57.951080 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9339 11:16:57.951260 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9340 11:16:57.951395 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9341 11:16:57.951538 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9342 11:16:57.951680 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9343 11:16:57.951822 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9344 11:16:57.951962 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9345 11:16:57.952102 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9346 11:16:57.952455 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9347 11:16:57.953958 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9348 11:16:57.954351 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9349 11:16:57.954465 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9350 11:16:57.954588 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9351 11:16:57.954732 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9352 11:16:57.954841 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9353 11:16:57.954929 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9354 11:16:57.955028 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9355 11:16:57.955138 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9356 11:16:57.955227 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9357 11:16:57.955313 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9358 11:16:57.955395 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9359 11:16:57.955499 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9360 11:16:57.955583 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9361 11:16:57.955701 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9362 11:16:57.955805 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9363 11:16:57.955887 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9364 11:16:57.956004 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9365 11:16:57.956101 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9366 11:16:57.956183 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9367 11:16:57.956279 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9368 11:16:57.956358 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9369 11:16:57.956446 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9370 11:16:57.956559 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9371 11:16:57.956652 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9372 11:16:57.956745 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9373 11:16:57.956835 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9374 11:16:57.956938 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9375 11:16:57.957037 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9376 11:16:57.957134 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9377 11:16:57.957202 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9378 11:16:57.957275 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9379 11:16:57.957591 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9380 11:16:57.957802 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9381 11:16:57.957934 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9382 11:16:57.958074 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9383 11:16:57.961901 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9384 11:16:57.962213 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9385 11:16:57.962321 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9386 11:16:57.962433 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9387 11:16:57.962544 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9388 11:16:57.962633 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9389 11:16:57.962936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9390 11:16:57.963045 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9391 11:16:57.963133 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9392 11:16:57.963235 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9393 11:16:57.963323 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9394 11:16:57.963413 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9395 11:16:57.963513 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9396 11:16:57.963601 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9397 11:16:57.963702 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9398 11:16:57.963806 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9399 11:16:57.963910 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9400 11:16:57.964014 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9401 11:16:57.964392 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9402 11:16:57.964572 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9403 11:16:57.964743 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9404 11:16:57.964935 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9405 11:16:57.965147 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9406 11:16:57.965339 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9407 11:16:57.965557 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9408 11:16:57.965765 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9409 11:16:57.965951 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9410 11:16:57.966076 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9411 11:16:57.966190 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9412 11:16:57.966302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9413 11:16:57.966413 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9414 11:16:57.966525 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9415 11:16:57.969944 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9416 11:16:57.970478 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9417 11:16:57.970672 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9418 11:16:57.970857 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9419 11:16:57.971009 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9420 11:16:57.971160 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9421 11:16:57.971308 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9422 11:16:57.971459 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9423 11:16:57.971626 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9424 11:16:57.971800 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9425 11:16:57.972015 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9426 11:16:57.972217 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9427 11:16:57.972373 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9428 11:16:57.972532 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9429 11:16:57.972729 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9430 11:16:57.972924 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9431 11:16:57.973144 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9432 11:16:57.973344 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9433 11:16:57.973516 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9434 11:16:57.973999 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9435 11:16:57.974178 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9436 11:16:57.974351 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9437 11:16:57.974502 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9438 11:16:57.974658 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9439 11:16:57.974820 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9440 11:16:57.974962 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9441 11:16:57.975130 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9442 11:16:57.975277 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9443 11:16:57.975433 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9444 11:16:57.975594 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9445 11:16:57.975777 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9446 11:16:57.975953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9447 11:16:57.976097 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9448 11:16:57.976264 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9449 11:16:57.976415 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9450 11:16:57.977963 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9451 11:16:57.978277 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9452 11:16:57.978387 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9453 11:16:57.978476 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9454 11:16:57.978577 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9455 11:16:57.978682 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9456 11:16:57.978772 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9457 11:16:57.979110 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9458 11:16:57.979319 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9459 11:16:57.979492 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9460 11:16:57.979693 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9461 11:16:57.979863 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9462 11:16:57.979997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9463 11:16:57.980122 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9464 11:16:57.980295 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9465 11:16:57.980434 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9466 11:16:57.980590 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9467 11:16:57.980719 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9468 11:16:57.995491 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9469 11:16:57.995985 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9470 11:16:57.996182 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9471 11:16:57.996348 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9472 11:16:57.996498 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9473 11:16:57.996667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9474 11:16:57.996845 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9475 11:16:57.997027 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9476 11:16:57.997165 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9477 11:16:57.997366 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9478 11:16:57.997561 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9479 11:16:57.997756 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9480 11:16:57.997921 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9481 11:16:57.998115 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9482 11:16:57.998259 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9483 11:16:57.998383 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9484 11:16:57.998515 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9485 11:16:57.998654 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9486 11:16:57.998789 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9487 11:16:57.998952 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9488 11:16:57.999105 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9489 11:16:57.999268 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9490 11:16:57.999468 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9491 11:16:57.999653 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9492 11:16:57.999805 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9493 11:16:57.999988 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9494 11:16:58.000127 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9495 11:16:58.000286 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9496 11:16:58.000450 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9497 11:16:58.000649 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9498 11:16:58.000791 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9499 11:16:58.000943 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9500 11:16:58.001096 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9501 11:16:58.001251 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9502 11:16:58.001401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9503 11:16:58.001548 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9504 11:16:58.002385 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9505 11:16:58.002548 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9506 11:16:58.002887 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9507 11:16:58.003012 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9508 11:16:58.003128 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9509 11:16:58.003240 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9510 11:16:58.003354 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9511 11:16:58.003466 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9512 11:16:58.003578 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9513 11:16:58.003690 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9514 11:16:58.003802 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9515 11:16:58.003915 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9516 11:16:58.004027 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9517 11:16:58.004139 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9518 11:16:58.004252 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9519 11:16:58.004364 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9520 11:16:58.004475 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9521 11:16:58.004587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9522 11:16:58.004699 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9523 11:16:58.006163 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9524 11:16:58.006357 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9525 11:16:58.006566 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9526 11:16:58.006748 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9527 11:16:58.006927 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9528 11:16:58.007122 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9529 11:16:58.007318 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9530 11:16:58.007505 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9531 11:16:58.007654 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9532 11:16:58.007796 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9533 11:16:58.007927 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9534 11:16:58.008108 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9535 11:16:58.008270 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9536 11:16:58.008421 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9537 11:16:58.008571 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9538 11:16:58.008711 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9539 11:16:58.008851 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9540 11:16:58.008970 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9541 11:16:58.009103 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9542 11:16:58.009297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9543 11:16:58.009483 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9544 11:16:58.009623 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9545 11:16:58.009815 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9546 11:16:58.009945 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9547 11:16:58.010061 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9548 11:16:58.010175 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9549 11:16:58.010292 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9550 11:16:58.010404 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9551 11:16:58.010516 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9552 11:16:58.010655 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9553 11:16:58.010775 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9554 11:16:58.010889 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9555 11:16:58.011003 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9556 11:16:58.013936 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9557 11:16:58.014265 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9558 11:16:58.014374 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9559 11:16:58.014469 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9560 11:16:58.014576 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9561 11:16:58.014668 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9562 11:16:58.014757 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9563 11:16:58.014860 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9564 11:16:58.014950 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9565 11:16:58.015038 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9566 11:16:58.015141 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9567 11:16:58.015231 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9568 11:16:58.015318 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9569 11:16:58.015423 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9570 11:16:58.015515 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9571 11:16:58.015622 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9572 11:16:58.015725 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9573 11:16:58.015829 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9574 11:16:58.015930 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9575 11:16:58.016087 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9576 11:16:58.016321 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9577 11:16:58.016559 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9578 11:16:58.016734 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9579 11:16:58.016885 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9580 11:16:58.017052 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9581 11:16:58.017181 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9582 11:16:58.017317 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9583 11:16:58.017452 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9584 11:16:58.017613 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9585 11:16:58.017848 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9586 11:16:58.017996 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9587 11:16:58.018114 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9588 11:16:58.018228 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9589 11:16:58.018341 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9590 11:16:58.022063 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9591 11:16:58.022263 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9592 11:16:58.022641 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9593 11:16:58.022833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9594 11:16:58.022974 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9595 11:16:58.023110 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9596 11:16:58.023282 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9597 11:16:58.023424 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9598 11:16:58.023527 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9599 11:16:58.023654 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9600 11:16:58.023801 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9601 11:16:58.023969 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9602 11:16:58.024106 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9603 11:16:58.024308 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9604 11:16:58.024452 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9605 11:16:58.024586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9606 11:16:58.024702 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9607 11:16:58.024805 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9608 11:16:58.024934 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9609 11:16:58.025049 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9610 11:16:58.025156 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9611 11:16:58.025311 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9612 11:16:58.025446 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9613 11:16:58.025569 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9614 11:16:58.025714 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9615 11:16:58.025855 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9616 11:16:58.025955 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9617 11:16:58.026046 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9618 11:16:58.026132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9619 11:16:58.026240 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9620 11:16:58.026332 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9621 11:16:58.026419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9622 11:16:58.033905 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9623 11:16:58.034318 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9624 11:16:58.034446 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9625 11:16:58.034538 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9626 11:16:58.034645 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9627 11:16:58.034764 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9628 11:16:58.045910 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9629 11:16:58.046311 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9630 11:16:58.046502 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9631 11:16:58.046684 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9632 11:16:58.046879 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9633 11:16:58.047092 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9634 11:16:58.047275 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9635 11:16:58.047474 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9636 11:16:58.047656 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9637 11:16:58.047815 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9638 11:16:58.047969 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9639 11:16:58.048122 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9640 11:16:58.048308 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9641 11:16:58.048493 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9642 11:16:58.048666 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9643 11:16:58.048830 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9644 11:16:58.049007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9645 11:16:58.049174 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9646 11:16:58.049332 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9647 11:16:58.049521 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9648 11:16:58.050022 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9649 11:16:58.050195 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9650 11:16:58.050338 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9651 11:16:58.050479 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9652 11:16:58.050620 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9653 11:16:58.050801 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9654 11:16:58.050938 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9655 11:16:58.051080 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9656 11:16:58.051219 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9657 11:16:58.051360 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9658 11:16:58.051501 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9659 11:16:58.051666 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9660 11:16:58.051828 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9661 11:16:58.052001 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9662 11:16:58.052172 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9663 11:16:58.052346 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9664 11:16:58.052506 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9665 11:16:58.053980 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9666 11:16:58.054435 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9667 11:16:58.054621 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9668 11:16:58.054790 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9669 11:16:58.055016 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9670 11:16:58.055241 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9671 11:16:58.055410 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9672 11:16:58.055569 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9673 11:16:58.055730 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9674 11:16:58.055887 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9675 11:16:58.056037 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9676 11:16:58.056191 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9677 11:16:58.056340 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9678 11:16:58.056565 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9679 11:16:58.056782 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9680 11:16:58.056988 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9681 11:16:58.057189 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9682 11:16:58.057350 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9683 11:16:58.057512 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9684 11:16:58.057709 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9685 11:16:58.057870 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9686 11:16:58.057987 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9687 11:16:58.058100 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9688 11:16:58.058244 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9689 11:16:58.058363 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9690 11:16:58.058476 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9691 11:16:58.058589 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9692 11:16:58.058703 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9693 11:16:58.058818 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9694 11:16:58.058931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9695 11:16:58.059044 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9696 11:16:58.059157 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9697 11:16:58.059269 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9698 11:16:58.061940 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9699 11:16:58.062377 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9700 11:16:58.062574 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9701 11:16:58.062734 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9702 11:16:58.062889 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9703 11:16:58.063073 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9704 11:16:58.063231 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9705 11:16:58.063385 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9706 11:16:58.063539 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9707 11:16:58.063693 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9708 11:16:58.063876 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9709 11:16:58.064034 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9710 11:16:58.064188 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9711 11:16:58.064342 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9712 11:16:58.064495 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9713 11:16:58.064649 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9714 11:16:58.064802 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9715 11:16:58.064979 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9716 11:16:58.065128 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9717 11:16:58.065827 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9718 11:16:58.065986 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9719 11:16:58.066128 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9720 11:16:58.066268 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9721 11:16:58.066419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9722 11:16:58.066589 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9723 11:16:58.066760 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9724 11:16:58.066938 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9725 11:16:58.067082 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9726 11:16:58.067253 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9727 11:16:58.067433 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9728 11:16:58.067606 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9729 11:16:58.067778 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9730 11:16:58.069965 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9731 11:16:58.070417 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9732 11:16:58.070611 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9733 11:16:58.070775 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9734 11:16:58.070923 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9735 11:16:58.071070 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9736 11:16:58.071257 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9737 11:16:58.071461 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9738 11:16:58.071666 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9739 11:16:58.071838 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9740 11:16:58.071970 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9741 11:16:58.072087 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9742 11:16:58.072229 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9743 11:16:58.072457 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9744 11:16:58.072643 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9745 11:16:58.072796 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9746 11:16:58.072930 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9747 11:16:58.073063 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9748 11:16:58.073185 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9749 11:16:58.073315 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9750 11:16:58.073433 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9751 11:16:58.073548 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9752 11:16:58.073681 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9753 11:16:58.073829 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9754 11:16:58.073948 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9755 11:16:58.074050 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9756 11:16:58.074136 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9757 11:16:58.074222 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9758 11:16:58.074308 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9759 11:16:58.074394 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9760 11:16:58.074480 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9761 11:16:58.074570 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9762 11:16:58.074655 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9763 11:16:58.074741 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9764 11:16:58.077967 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9765 11:16:58.078355 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9766 11:16:58.078484 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9767 11:16:58.078600 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9768 11:16:58.078737 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9769 11:16:58.078854 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9770 11:16:58.078989 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9771 11:16:58.079107 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9772 11:16:58.079224 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9773 11:16:58.079359 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9774 11:16:58.079476 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9775 11:16:58.079612 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9776 11:16:58.079730 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9777 11:16:58.079866 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9778 11:16:58.079983 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9779 11:16:58.080121 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9780 11:16:58.080246 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9781 11:16:58.080381 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9782 11:16:58.080499 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9783 11:16:58.080614 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9784 11:16:58.080749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9785 11:16:58.080868 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9786 11:16:58.081002 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9787 11:16:58.081123 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9788 11:16:58.096325 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9789 11:16:58.096904 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9790 11:16:58.097095 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9791 11:16:58.097261 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9792 11:16:58.097409 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9793 11:16:58.097551 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9794 11:16:58.097755 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9795 11:16:58.097929 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9796 11:16:58.098071 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9797 11:16:58.098250 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9798 11:16:58.098408 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9799 11:16:58.098593 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9800 11:16:58.098742 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9801 11:16:58.098960 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9802 11:16:58.099112 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9803 11:16:58.099256 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9804 11:16:58.099394 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9805 11:16:58.099581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9806 11:16:58.099766 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9807 11:16:58.099947 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9808 11:16:58.100187 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9809 11:16:58.100340 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9810 11:16:58.100461 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9811 11:16:58.100598 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9812 11:16:58.100734 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9813 11:16:58.101075 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9814 11:16:58.101217 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9815 11:16:58.101546 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9816 11:16:58.101701 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9817 11:16:58.106038 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9818 11:16:58.106404 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9819 11:16:58.106567 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9820 11:16:58.106706 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9821 11:16:58.107037 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9822 11:16:58.107179 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9823 11:16:58.107313 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9824 11:16:58.107448 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9825 11:16:58.107803 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9826 11:16:58.107946 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9827 11:16:58.108085 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9828 11:16:58.108301 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9829 11:16:58.108512 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9830 11:16:58.108721 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9831 11:16:58.108926 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9832 11:16:58.109153 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9833 11:16:58.109345 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9834 11:16:58.109536 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9835 11:16:58.109698 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9836 11:16:58.109856 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9837 11:16:58.109996 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9838 11:16:58.114248 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9839 11:16:58.114451 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9840 11:16:58.114613 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9841 11:16:58.114803 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9842 11:16:58.114969 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9843 11:16:58.115134 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9844 11:16:58.115293 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9845 11:16:58.115538 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9846 11:16:58.115809 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9847 11:16:58.116034 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9848 11:16:58.116262 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9849 11:16:58.116457 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9850 11:16:58.116646 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9851 11:16:58.116863 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9852 11:16:58.117046 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9853 11:16:58.117250 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9854 11:16:58.117446 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9855 11:16:58.117685 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9856 11:16:58.117866 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9857 11:16:58.118025 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9858 11:16:58.118155 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9859 11:16:58.118273 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9860 11:16:58.118391 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9861 11:16:58.118507 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9862 11:16:58.118622 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9863 11:16:58.118738 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9864 11:16:58.118853 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9865 11:16:58.118968 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9866 11:16:58.119082 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9867 11:16:58.119199 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9868 11:16:58.119314 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9869 11:16:58.119429 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9870 11:16:58.121926 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9871 11:16:58.122371 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9872 11:16:58.122573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9873 11:16:58.122734 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9874 11:16:58.122892 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9875 11:16:58.123068 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9876 11:16:58.123238 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9877 11:16:58.123438 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9878 11:16:58.123597 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9879 11:16:58.123758 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9880 11:16:58.123928 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9881 11:16:58.124136 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9882 11:16:58.124284 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9883 11:16:58.124444 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9884 11:16:58.124618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9885 11:16:58.124788 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9886 11:16:58.124918 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9887 11:16:58.125066 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9888 11:16:58.125197 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9889 11:16:58.125363 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9890 11:16:58.125494 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9891 11:16:58.125619 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9892 11:16:58.126021 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9893 11:16:58.126117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9894 11:16:58.126177 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9895 11:16:58.126236 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9896 11:16:58.126295 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9897 11:16:58.126354 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9898 11:16:58.126412 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9899 11:16:58.126471 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9900 11:16:58.126530 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9901 11:16:58.126603 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9902 11:16:58.126665 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9903 11:16:58.126724 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9904 11:16:58.129967 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9905 11:16:58.130278 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9906 11:16:58.130370 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9907 11:16:58.130462 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9908 11:16:58.130577 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9909 11:16:58.130661 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9910 11:16:58.130733 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9911 11:16:58.130818 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9912 11:16:58.130912 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9913 11:16:58.131028 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9914 11:16:58.131125 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9915 11:16:58.131396 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9916 11:16:58.131480 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9917 11:16:58.131571 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9918 11:16:58.131670 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9919 11:16:58.131760 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9920 11:16:58.132033 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9921 11:16:58.132117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9922 11:16:58.132207 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9923 11:16:58.132301 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9924 11:16:58.132575 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9925 11:16:58.132658 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9926 11:16:58.132734 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9927 11:16:58.132810 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9928 11:16:58.133076 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9929 11:16:58.133148 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9930 11:16:58.133229 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9931 11:16:58.133493 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9932 11:16:58.133590 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9933 11:16:58.133684 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9934 11:16:58.137947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9935 11:16:58.138239 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9936 11:16:58.138333 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9937 11:16:58.138448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9938 11:16:58.138533 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9939 11:16:58.138631 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9940 11:16:58.138710 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9941 11:16:58.138802 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9942 11:16:58.138893 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9943 11:16:58.138985 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9944 11:16:58.139266 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9945 11:16:58.139386 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9946 11:16:58.139502 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9947 11:16:58.139573 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9948 11:16:58.154024 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9949 11:16:58.154322 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9950 11:16:58.154425 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9951 11:16:58.154525 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9952 11:16:58.154623 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9953 11:16:58.154714 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9954 11:16:58.154805 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9955 11:16:58.154889 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9956 11:16:58.154976 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9957 11:16:58.155255 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9958 11:16:58.155350 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9959 11:16:58.155433 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9960 11:16:58.155548 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9961 11:16:58.155640 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9962 11:16:58.155765 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9963 11:16:58.155848 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9964 11:16:58.155949 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9965 11:16:58.156046 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9966 11:16:58.156178 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9967 11:16:58.156491 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9968 11:16:58.156594 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9969 11:16:58.156673 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9970 11:16:58.156953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9971 11:16:58.157050 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9972 11:16:58.157127 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9973 11:16:58.157211 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9974 11:16:58.157324 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9975 11:16:58.157414 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9976 11:16:58.157494 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9977 11:16:58.157591 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9978 11:16:58.157676 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9979 11:16:58.157746 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9980 11:16:58.157820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
9981 11:16:58.161924 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
9982 11:16:58.162205 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
9983 11:16:58.162303 arm64_sve-ptrace_Set_SVE_VL_4448 pass
9984 11:16:58.162414 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
9985 11:16:58.162533 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
9986 11:16:58.162631 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
9987 11:16:58.162736 arm64_sve-ptrace_Set_SVE_VL_4464 pass
9988 11:16:58.162838 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
9989 11:16:58.162939 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
9990 11:16:58.163036 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
9991 11:16:58.163130 arm64_sve-ptrace_Set_SVE_VL_4480 pass
9992 11:16:58.163419 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
9993 11:16:58.163516 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
9994 11:16:58.163616 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
9995 11:16:58.163696 arm64_sve-ptrace_Set_SVE_VL_4496 pass
9996 11:16:58.163804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
9997 11:16:58.163902 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
9998 11:16:58.163998 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
9999 11:16:58.164095 arm64_sve-ptrace_Set_SVE_VL_4512 pass
10000 11:16:58.164385 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
10001 11:16:58.164479 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
10002 11:16:58.164575 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
10003 11:16:58.164643 arm64_sve-ptrace_Set_SVE_VL_4528 pass
10004 11:16:58.164730 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
10005 11:16:58.164822 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
10006 11:16:58.164914 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
10007 11:16:58.165244 arm64_sve-ptrace_Set_SVE_VL_4544 pass
10008 11:16:58.165433 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
10009 11:16:58.165607 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
10010 11:16:58.165796 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
10011 11:16:58.165967 arm64_sve-ptrace_Set_SVE_VL_4560 pass
10012 11:16:58.166115 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
10013 11:16:58.166272 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
10014 11:16:58.170116 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
10015 11:16:58.170225 arm64_sve-ptrace_Set_SVE_VL_4576 pass
10016 11:16:58.170327 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
10017 11:16:58.170434 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
10018 11:16:58.170534 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
10019 11:16:58.170638 arm64_sve-ptrace_Set_SVE_VL_4592 pass
10020 11:16:58.170918 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
10021 11:16:58.171005 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
10022 11:16:58.171094 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
10023 11:16:58.171206 arm64_sve-ptrace_Set_SVE_VL_4608 pass
10024 11:16:58.171497 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
10025 11:16:58.171584 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
10026 11:16:58.171691 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
10027 11:16:58.171779 arm64_sve-ptrace_Set_SVE_VL_4624 pass
10028 11:16:58.171894 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
10029 11:16:58.171996 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
10030 11:16:58.172258 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
10031 11:16:58.172339 arm64_sve-ptrace_Set_SVE_VL_4640 pass
10032 11:16:58.172427 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
10033 11:16:58.172530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
10034 11:16:58.172635 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
10035 11:16:58.172936 arm64_sve-ptrace_Set_SVE_VL_4656 pass
10036 11:16:58.173042 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
10037 11:16:58.173139 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
10038 11:16:58.173233 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
10039 11:16:58.173315 arm64_sve-ptrace_Set_SVE_VL_4672 pass
10040 11:16:58.173407 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
10041 11:16:58.173704 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
10042 11:16:58.173792 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
10043 11:16:58.174055 arm64_sve-ptrace_Set_SVE_VL_4688 pass
10044 11:16:58.178079 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
10045 11:16:58.178184 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
10046 11:16:58.178481 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
10047 11:16:58.178587 arm64_sve-ptrace_Set_SVE_VL_4704 pass
10048 11:16:58.178681 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
10049 11:16:58.178775 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
10050 11:16:58.179094 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
10051 11:16:58.179278 arm64_sve-ptrace_Set_SVE_VL_4720 pass
10052 11:16:58.179549 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
10053 11:16:58.179744 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
10054 11:16:58.179944 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
10055 11:16:58.180098 arm64_sve-ptrace_Set_SVE_VL_4736 pass
10056 11:16:58.180300 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
10057 11:16:58.180517 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
10058 11:16:58.180713 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
10059 11:16:58.180865 arm64_sve-ptrace_Set_SVE_VL_4752 pass
10060 11:16:58.181003 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
10061 11:16:58.181135 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
10062 11:16:58.181315 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
10063 11:16:58.181467 arm64_sve-ptrace_Set_SVE_VL_4768 pass
10064 11:16:58.181604 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
10065 11:16:58.181755 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
10066 11:16:58.181879 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
10067 11:16:58.181993 arm64_sve-ptrace_Set_SVE_VL_4784 pass
10068 11:16:58.182138 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
10069 11:16:58.182261 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
10070 11:16:58.182375 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
10071 11:16:58.182491 arm64_sve-ptrace_Set_SVE_VL_4800 pass
10072 11:16:58.182605 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
10073 11:16:58.182719 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
10074 11:16:58.182832 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
10075 11:16:58.182946 arm64_sve-ptrace_Set_SVE_VL_4816 pass
10076 11:16:58.183059 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
10077 11:16:58.183173 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
10078 11:16:58.186017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
10079 11:16:58.186212 arm64_sve-ptrace_Set_SVE_VL_4832 pass
10080 11:16:58.186608 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
10081 11:16:58.186796 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
10082 11:16:58.186958 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
10083 11:16:58.187112 arm64_sve-ptrace_Set_SVE_VL_4848 pass
10084 11:16:58.187272 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
10085 11:16:58.187461 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
10086 11:16:58.187623 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
10087 11:16:58.187789 arm64_sve-ptrace_Set_SVE_VL_4864 pass
10088 11:16:58.188006 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
10089 11:16:58.188222 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
10090 11:16:58.188468 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
10091 11:16:58.188667 arm64_sve-ptrace_Set_SVE_VL_4880 pass
10092 11:16:58.188849 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
10093 11:16:58.189044 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
10094 11:16:58.189222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
10095 11:16:58.189344 arm64_sve-ptrace_Set_SVE_VL_4896 pass
10096 11:16:58.189460 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
10097 11:16:58.189603 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
10098 11:16:58.189793 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
10099 11:16:58.189986 arm64_sve-ptrace_Set_SVE_VL_4912 pass
10100 11:16:58.190131 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
10101 11:16:58.190275 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
10102 11:16:58.190416 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
10103 11:16:58.190557 arm64_sve-ptrace_Set_SVE_VL_4928 pass
10104 11:16:58.190733 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
10105 11:16:58.190868 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
10106 11:16:58.191010 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
10107 11:16:58.191152 arm64_sve-ptrace_Set_SVE_VL_4944 pass
10108 11:16:58.204308 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
10109 11:16:58.204727 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
10110 11:16:58.204934 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
10111 11:16:58.205126 arm64_sve-ptrace_Set_SVE_VL_4960 pass
10112 11:16:58.205267 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
10113 11:16:58.205455 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
10114 11:16:58.205623 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
10115 11:16:58.205790 arm64_sve-ptrace_Set_SVE_VL_4976 pass
10116 11:16:58.205925 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
10117 11:16:58.206067 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
10118 11:16:58.206209 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
10119 11:16:58.206338 arm64_sve-ptrace_Set_SVE_VL_4992 pass
10120 11:16:58.206510 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
10121 11:16:58.206637 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
10122 11:16:58.206765 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
10123 11:16:58.206898 arm64_sve-ptrace_Set_SVE_VL_5008 pass
10124 11:16:58.207045 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
10125 11:16:58.207207 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
10126 11:16:58.207359 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
10127 11:16:58.207556 arm64_sve-ptrace_Set_SVE_VL_5024 pass
10128 11:16:58.207697 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
10129 11:16:58.207821 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
10130 11:16:58.207963 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
10131 11:16:58.208107 arm64_sve-ptrace_Set_SVE_VL_5040 pass
10132 11:16:58.208252 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
10133 11:16:58.208382 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
10134 11:16:58.208518 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
10135 11:16:58.208668 arm64_sve-ptrace_Set_SVE_VL_5056 pass
10136 11:16:58.208821 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
10137 11:16:58.209013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
10138 11:16:58.209147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
10139 11:16:58.209321 arm64_sve-ptrace_Set_SVE_VL_5072 pass
10140 11:16:58.209491 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
10141 11:16:58.209643 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
10142 11:16:58.209885 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
10143 11:16:58.210072 arm64_sve-ptrace_Set_SVE_VL_5088 pass
10144 11:16:58.210251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
10145 11:16:58.210391 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
10146 11:16:58.210527 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
10147 11:16:58.210865 arm64_sve-ptrace_Set_SVE_VL_5104 pass
10148 11:16:58.210971 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
10149 11:16:58.211081 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
10150 11:16:58.211189 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
10151 11:16:58.211295 arm64_sve-ptrace_Set_SVE_VL_5120 pass
10152 11:16:58.211402 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
10153 11:16:58.211508 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
10154 11:16:58.213909 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
10155 11:16:58.214414 arm64_sve-ptrace_Set_SVE_VL_5136 pass
10156 11:16:58.214612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
10157 11:16:58.214803 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
10158 11:16:58.214978 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
10159 11:16:58.215148 arm64_sve-ptrace_Set_SVE_VL_5152 pass
10160 11:16:58.215331 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
10161 11:16:58.215482 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
10162 11:16:58.215653 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
10163 11:16:58.215838 arm64_sve-ptrace_Set_SVE_VL_5168 pass
10164 11:16:58.216012 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
10165 11:16:58.216193 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
10166 11:16:58.216397 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
10167 11:16:58.216613 arm64_sve-ptrace_Set_SVE_VL_5184 pass
10168 11:16:58.216849 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
10169 11:16:58.217029 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
10170 11:16:58.217192 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
10171 11:16:58.217352 arm64_sve-ptrace_Set_SVE_VL_5200 pass
10172 11:16:58.217509 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
10173 11:16:58.218062 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
10174 11:16:58.218209 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
10175 11:16:58.218326 arm64_sve-ptrace_Set_SVE_VL_5216 pass
10176 11:16:58.218439 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
10177 11:16:58.218552 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
10178 11:16:58.218662 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
10179 11:16:58.218774 arm64_sve-ptrace_Set_SVE_VL_5232 pass
10180 11:16:58.218885 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
10181 11:16:58.219028 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
10182 11:16:58.219146 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
10183 11:16:58.219260 arm64_sve-ptrace_Set_SVE_VL_5248 pass
10184 11:16:58.219378 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
10185 11:16:58.219491 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
10186 11:16:58.219604 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
10187 11:16:58.219717 arm64_sve-ptrace_Set_SVE_VL_5264 pass
10188 11:16:58.219829 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
10189 11:16:58.221961 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
10190 11:16:58.222331 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
10191 11:16:58.222434 arm64_sve-ptrace_Set_SVE_VL_5280 pass
10192 11:16:58.222517 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
10193 11:16:58.222610 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
10194 11:16:58.222693 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
10195 11:16:58.222772 arm64_sve-ptrace_Set_SVE_VL_5296 pass
10196 11:16:58.222863 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
10197 11:16:58.222942 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
10198 11:16:58.223032 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
10199 11:16:58.223243 arm64_sve-ptrace_Set_SVE_VL_5312 pass
10200 11:16:58.223345 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
10201 11:16:58.223439 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
10202 11:16:58.223518 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
10203 11:16:58.223607 arm64_sve-ptrace_Set_SVE_VL_5328 pass
10204 11:16:58.223686 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
10205 11:16:58.223777 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
10206 11:16:58.223871 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
10207 11:16:58.223962 arm64_sve-ptrace_Set_SVE_VL_5344 pass
10208 11:16:58.224250 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
10209 11:16:58.224351 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
10210 11:16:58.224445 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
10211 11:16:58.224524 arm64_sve-ptrace_Set_SVE_VL_5360 pass
10212 11:16:58.224613 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
10213 11:16:58.224900 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
10214 11:16:58.225002 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
10215 11:16:58.225096 arm64_sve-ptrace_Set_SVE_VL_5376 pass
10216 11:16:58.225176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
10217 11:16:58.225270 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
10218 11:16:58.225362 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
10219 11:16:58.225456 arm64_sve-ptrace_Set_SVE_VL_5392 pass
10220 11:16:58.225554 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
10221 11:16:58.225848 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
10222 11:16:58.230022 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
10223 11:16:58.230551 arm64_sve-ptrace_Set_SVE_VL_5408 pass
10224 11:16:58.230739 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
10225 11:16:58.230900 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10226 11:16:58.231035 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10227 11:16:58.231195 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10228 11:16:58.231347 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10229 11:16:58.231466 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10230 11:16:58.231581 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10231 11:16:58.231696 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10232 11:16:58.231818 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10233 11:16:58.232004 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10234 11:16:58.232240 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10235 11:16:58.232426 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10236 11:16:58.232590 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10237 11:16:58.232749 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10238 11:16:58.232895 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10239 11:16:58.233039 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10240 11:16:58.233181 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10241 11:16:58.233309 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10242 11:16:58.233455 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10243 11:16:58.233576 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10244 11:16:58.233742 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10245 11:16:58.233943 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10246 11:16:58.234127 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10247 11:16:58.234308 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10248 11:16:58.234490 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10249 11:16:58.234637 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10250 11:16:58.234778 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10251 11:16:58.234921 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10252 11:16:58.235098 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10253 11:16:58.235235 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10254 11:16:58.235378 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10255 11:16:58.237924 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10256 11:16:58.238234 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10257 11:16:58.238334 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10258 11:16:58.238436 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10259 11:16:58.238517 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10260 11:16:58.238610 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10261 11:16:58.238890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10262 11:16:58.238986 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10263 11:16:58.239079 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10264 11:16:58.239353 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10265 11:16:58.239438 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10266 11:16:58.239710 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10267 11:16:58.239794 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10268 11:16:58.254866 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10269 11:16:58.255169 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10270 11:16:58.255270 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10271 11:16:58.255364 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10272 11:16:58.255445 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10273 11:16:58.255539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10274 11:16:58.255631 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10275 11:16:58.255724 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10276 11:16:58.255816 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10277 11:16:58.256082 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10278 11:16:58.256183 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10279 11:16:58.256272 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10280 11:16:58.256364 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10281 11:16:58.256459 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10282 11:16:58.256551 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10283 11:16:58.256644 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10284 11:16:58.256730 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10285 11:16:58.257009 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10286 11:16:58.257117 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10287 11:16:58.257204 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10288 11:16:58.257299 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10289 11:16:58.257397 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10290 11:16:58.257478 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10291 11:16:58.257574 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10292 11:16:58.257873 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10293 11:16:58.261905 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10294 11:16:58.262222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10295 11:16:58.262323 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10296 11:16:58.262405 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10297 11:16:58.262500 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10298 11:16:58.262581 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10299 11:16:58.262672 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10300 11:16:58.262751 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10301 11:16:58.262841 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10302 11:16:58.262939 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10303 11:16:58.263030 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10304 11:16:58.263121 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10305 11:16:58.263212 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10306 11:16:58.263557 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10307 11:16:58.263748 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10308 11:16:58.263952 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10309 11:16:58.264118 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10310 11:16:58.264301 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10311 11:16:58.264486 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10312 11:16:58.264675 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10313 11:16:58.264835 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10314 11:16:58.264982 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10315 11:16:58.265150 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10316 11:16:58.265348 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10317 11:16:58.265524 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10318 11:16:58.265734 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10319 11:16:58.265894 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10320 11:16:58.266051 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10321 11:16:58.266173 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10322 11:16:58.266290 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10323 11:16:58.266407 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10324 11:16:58.266523 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10325 11:16:58.266637 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10326 11:16:58.266778 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10327 11:16:58.269913 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10328 11:16:58.270270 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10329 11:16:58.270383 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10330 11:16:58.270452 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10331 11:16:58.270533 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10332 11:16:58.270625 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10333 11:16:58.270901 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10334 11:16:58.271095 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10335 11:16:58.271305 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10336 11:16:58.271516 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10337 11:16:58.271686 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10338 11:16:58.271842 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10339 11:16:58.272009 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10340 11:16:58.272204 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10341 11:16:58.272499 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10342 11:16:58.272708 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10343 11:16:58.272928 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10344 11:16:58.273134 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10345 11:16:58.273344 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10346 11:16:58.273552 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10347 11:16:58.273785 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10348 11:16:58.273990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10349 11:16:58.274141 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10350 11:16:58.274324 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10351 11:16:58.274461 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10352 11:16:58.274603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10353 11:16:58.274743 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10354 11:16:58.274884 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10355 11:16:58.275024 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10356 11:16:58.275164 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10357 11:16:58.275304 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10358 11:16:58.275446 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10359 11:16:58.275585 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10360 11:16:58.275724 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10361 11:16:58.277920 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10362 11:16:58.278256 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10363 11:16:58.278461 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10364 11:16:58.278707 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10365 11:16:58.278906 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10366 11:16:58.279079 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10367 11:16:58.279270 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10368 11:16:58.279479 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10369 11:16:58.279629 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10370 11:16:58.279772 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10371 11:16:58.279923 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10372 11:16:58.280065 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10373 11:16:58.280213 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10374 11:16:58.280367 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10375 11:16:58.280504 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10376 11:16:58.280685 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10377 11:16:58.280902 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10378 11:16:58.281101 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10379 11:16:58.281284 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10380 11:16:58.281437 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10381 11:16:58.281591 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10382 11:16:58.282101 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10383 11:16:58.282232 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10384 11:16:58.282348 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10385 11:16:58.282462 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10386 11:16:58.282576 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10387 11:16:58.282720 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10388 11:16:58.282842 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10389 11:16:58.282958 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10390 11:16:58.283072 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10391 11:16:58.283186 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10392 11:16:58.283300 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10393 11:16:58.283413 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10394 11:16:58.283525 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10395 11:16:58.283638 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10396 11:16:58.285963 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10397 11:16:58.286372 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10398 11:16:58.286559 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10399 11:16:58.286748 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10400 11:16:58.286944 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10401 11:16:58.287086 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10402 11:16:58.287228 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10403 11:16:58.287380 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10404 11:16:58.287546 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10405 11:16:58.287722 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10406 11:16:58.287875 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10407 11:16:58.288018 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10408 11:16:58.288168 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10409 11:16:58.288304 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10410 11:16:58.288474 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10411 11:16:58.288637 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10412 11:16:58.288807 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10413 11:16:58.288950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10414 11:16:58.289092 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10415 11:16:58.289232 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10416 11:16:58.289429 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10417 11:16:58.289606 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10418 11:16:58.289771 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10419 11:16:58.289893 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10420 11:16:58.290007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10421 11:16:58.290120 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10422 11:16:58.290234 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10423 11:16:58.290347 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10424 11:16:58.290486 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10425 11:16:58.290605 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10426 11:16:58.290718 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10427 11:16:58.294133 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10428 11:16:58.305747 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10429 11:16:58.306134 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10430 11:16:58.306382 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10431 11:16:58.306579 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10432 11:16:58.306747 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10433 11:16:58.306879 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10434 11:16:58.307012 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10435 11:16:58.307160 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10436 11:16:58.307366 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10437 11:16:58.307554 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10438 11:16:58.307720 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10439 11:16:58.307891 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10440 11:16:58.308040 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10441 11:16:58.308253 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10442 11:16:58.308500 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10443 11:16:58.308672 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10444 11:16:58.308844 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10445 11:16:58.309008 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10446 11:16:58.309175 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10447 11:16:58.309371 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10448 11:16:58.309561 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10449 11:16:58.309765 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10450 11:16:58.309950 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10451 11:16:58.310120 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10452 11:16:58.310261 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10453 11:16:58.310440 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10454 11:16:58.310577 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10455 11:16:58.310718 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10456 11:16:58.310858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10457 11:16:58.310998 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10458 11:16:58.311137 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10459 11:16:58.311275 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10460 11:16:58.311416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10461 11:16:58.311556 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10462 11:16:58.311696 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10463 11:16:58.311835 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10464 11:16:58.313938 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10465 11:16:58.314452 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10466 11:16:58.314737 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10467 11:16:58.314925 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10468 11:16:58.315147 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10469 11:16:58.315365 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10470 11:16:58.315556 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10471 11:16:58.315764 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10472 11:16:58.315922 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10473 11:16:58.316082 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10474 11:16:58.316270 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10475 11:16:58.316431 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10476 11:16:58.316589 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10477 11:16:58.316783 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10478 11:16:58.317010 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10479 11:16:58.317249 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10480 11:16:58.317455 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10481 11:16:58.318019 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10482 11:16:58.318231 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10483 11:16:58.318407 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10484 11:16:58.318580 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10485 11:16:58.318755 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10486 11:16:58.318928 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10487 11:16:58.319109 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10488 11:16:58.319245 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10489 11:16:58.319489 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10490 11:16:58.319630 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10491 11:16:58.319800 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10492 11:16:58.319976 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10493 11:16:58.320151 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10494 11:16:58.320326 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10495 11:16:58.320499 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10496 11:16:58.320670 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10497 11:16:58.322049 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10498 11:16:58.322297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10499 11:16:58.322682 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10500 11:16:58.322786 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10501 11:16:58.322876 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10502 11:16:58.322962 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10503 11:16:58.323044 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10504 11:16:58.323150 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10505 11:16:58.323233 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10506 11:16:58.323313 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10507 11:16:58.323410 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10508 11:16:58.323490 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10509 11:16:58.323571 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10510 11:16:58.323669 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10511 11:16:58.323751 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10512 11:16:58.323830 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10513 11:16:58.323924 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10514 11:16:58.324015 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10515 11:16:58.324092 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10516 11:16:58.324187 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10517 11:16:58.324566 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10518 11:16:58.324665 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10519 11:16:58.324761 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10520 11:16:58.324840 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10521 11:16:58.324916 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10522 11:16:58.325006 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10523 11:16:58.325284 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10524 11:16:58.325382 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10525 11:16:58.325462 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10526 11:16:58.325552 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10527 11:16:58.325831 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10528 11:16:58.325929 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10529 11:16:58.326012 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10530 11:16:58.329959 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10531 11:16:58.330292 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10532 11:16:58.330393 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10533 11:16:58.330474 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10534 11:16:58.330572 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10535 11:16:58.330653 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10536 11:16:58.330735 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10537 11:16:58.330827 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10538 11:16:58.330906 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10539 11:16:58.330996 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10540 11:16:58.331280 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10541 11:16:58.331382 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10542 11:16:58.331485 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10543 11:16:58.331577 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10544 11:16:58.331662 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10545 11:16:58.331763 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10546 11:16:58.331848 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10547 11:16:58.331932 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10548 11:16:58.332034 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10549 11:16:58.332117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10550 11:16:58.332217 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10551 11:16:58.332317 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10552 11:16:58.332821 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10553 11:16:58.333030 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10554 11:16:58.333203 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10555 11:16:58.333367 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10556 11:16:58.333591 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10557 11:16:58.333807 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10558 11:16:58.333966 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10559 11:16:58.334095 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10560 11:16:58.334215 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10561 11:16:58.334344 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10562 11:16:58.334469 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10563 11:16:58.334614 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10564 11:16:58.337951 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10565 11:16:58.338426 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10566 11:16:58.338601 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10567 11:16:58.338732 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10568 11:16:58.338882 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10569 11:16:58.339011 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10570 11:16:58.339145 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10571 11:16:58.339281 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10572 11:16:58.339411 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10573 11:16:58.339565 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10574 11:16:58.339692 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10575 11:16:58.339817 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10576 11:16:58.339942 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10577 11:16:58.340066 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10578 11:16:58.340225 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10579 11:16:58.340355 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10580 11:16:58.340479 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10581 11:16:58.340599 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10582 11:16:58.340717 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10583 11:16:58.340859 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10584 11:16:58.340980 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10585 11:16:58.341103 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10586 11:16:58.341221 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10587 11:16:58.341335 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10588 11:16:58.356366 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10589 11:16:58.356804 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10590 11:16:58.356964 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10591 11:16:58.357127 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10592 11:16:58.357319 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10593 11:16:58.357487 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10594 11:16:58.357654 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10595 11:16:58.357805 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10596 11:16:58.357953 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10597 11:16:58.358141 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10598 11:16:58.358301 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10599 11:16:58.358454 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10600 11:16:58.358608 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10601 11:16:58.358791 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10602 11:16:58.358948 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10603 11:16:58.359139 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10604 11:16:58.359301 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10605 11:16:58.359456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10606 11:16:58.359598 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10607 11:16:58.359754 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10608 11:16:58.359903 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10609 11:16:58.360045 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10610 11:16:58.360220 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10611 11:16:58.360440 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10612 11:16:58.360597 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10613 11:16:58.360747 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10614 11:16:58.360895 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10615 11:16:58.361042 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10616 11:16:58.361189 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10617 11:16:58.361336 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10618 11:16:58.361483 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10619 11:16:58.361633 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10620 11:16:58.361793 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10621 11:16:58.361969 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10622 11:16:58.362124 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10623 11:16:58.362275 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10624 11:16:58.362423 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10625 11:16:58.362567 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10626 11:16:58.362889 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10627 11:16:58.363010 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10628 11:16:58.363123 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10629 11:16:58.363237 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10630 11:16:58.363349 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10631 11:16:58.365926 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10632 11:16:58.366237 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10633 11:16:58.366347 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10634 11:16:58.366470 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10635 11:16:58.366576 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10636 11:16:58.366686 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10637 11:16:58.366772 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10638 11:16:58.366871 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10639 11:16:58.366977 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10640 11:16:58.367054 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10641 11:16:58.367139 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10642 11:16:58.367480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10643 11:16:58.367562 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10644 11:16:58.367654 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10645 11:16:58.367747 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10646 11:16:58.367839 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10647 11:16:58.367923 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10648 11:16:58.368016 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10649 11:16:58.368098 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10650 11:16:58.368190 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10651 11:16:58.368311 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10652 11:16:58.368404 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10653 11:16:58.368495 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10654 11:16:58.368611 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10655 11:16:58.368696 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10656 11:16:58.368772 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10657 11:16:58.368867 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10658 11:16:58.368949 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10659 11:16:58.369043 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10660 11:16:58.369122 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10661 11:16:58.369208 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10662 11:16:58.369271 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10663 11:16:58.369339 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10664 11:16:58.369408 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10665 11:16:58.369685 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10666 11:16:58.369782 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10667 11:16:58.369877 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10668 11:16:58.374174 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10669 11:16:58.374366 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10670 11:16:58.374590 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10671 11:16:58.374764 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10672 11:16:58.374925 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10673 11:16:58.375101 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10674 11:16:58.375263 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10675 11:16:58.375420 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10676 11:16:58.375569 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10677 11:16:58.375780 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10678 11:16:58.375996 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10679 11:16:58.376170 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10680 11:16:58.376349 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10681 11:16:58.376546 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10682 11:16:58.376726 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10683 11:16:58.376912 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10684 11:16:58.377080 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10685 11:16:58.377282 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10686 11:16:58.377461 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10687 11:16:58.377677 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10688 11:16:58.377870 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10689 11:16:58.378056 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10690 11:16:58.378222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10691 11:16:58.378387 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10692 11:16:58.378560 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10693 11:16:58.378733 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10694 11:16:58.378905 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10695 11:16:58.379070 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10696 11:16:58.379274 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10697 11:16:58.379454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10698 11:16:58.379635 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10699 11:16:58.379813 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10700 11:16:58.379983 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10701 11:16:58.381952 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10702 11:16:58.382349 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10703 11:16:58.382445 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10704 11:16:58.382522 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10705 11:16:58.382612 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10706 11:16:58.382691 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10707 11:16:58.382770 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10708 11:16:58.382859 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10709 11:16:58.383137 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10710 11:16:58.383218 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10711 11:16:58.383306 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10712 11:16:58.383386 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10713 11:16:58.383479 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10714 11:16:58.383567 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10715 11:16:58.383659 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10716 11:16:58.383747 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10717 11:16:58.383966 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10718 11:16:58.384070 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10719 11:16:58.384356 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10720 11:16:58.384451 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10721 11:16:58.384560 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10722 11:16:58.384643 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10723 11:16:58.384731 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10724 11:16:58.384827 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10725 11:16:58.384918 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10726 11:16:58.385011 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10727 11:16:58.385103 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10728 11:16:58.385196 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10729 11:16:58.385286 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10730 11:16:58.385595 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10731 11:16:58.385690 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10732 11:16:58.385765 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10733 11:16:58.385857 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10734 11:16:58.390131 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10735 11:16:58.390293 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10736 11:16:58.390380 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10737 11:16:58.390481 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10738 11:16:58.390585 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10739 11:16:58.390691 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10740 11:16:58.390792 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10741 11:16:58.390895 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10742 11:16:58.391191 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10743 11:16:58.391277 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10744 11:16:58.391366 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10745 11:16:58.391454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10746 11:16:58.391711 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10747 11:16:58.391777 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10748 11:16:58.407087 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10749 11:16:58.407579 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10750 11:16:58.407673 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10751 11:16:58.407750 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10752 11:16:58.407825 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10753 11:16:58.407914 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10754 11:16:58.407994 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10755 11:16:58.408069 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10756 11:16:58.408157 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10757 11:16:58.408237 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10758 11:16:58.408324 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10759 11:16:58.408393 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10760 11:16:58.408500 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10761 11:16:58.408590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10762 11:16:58.408679 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10763 11:16:58.408939 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10764 11:16:58.409018 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10765 11:16:58.409096 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10766 11:16:58.409166 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10767 11:16:58.409440 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10768 11:16:58.409539 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10769 11:16:58.409631 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10770 11:16:58.409730 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10771 11:16:58.413973 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10772 11:16:58.414077 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10773 11:16:58.414383 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10774 11:16:58.414595 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10775 11:16:58.414808 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10776 11:16:58.414984 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10777 11:16:58.415138 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10778 11:16:58.415338 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10779 11:16:58.415515 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10780 11:16:58.415694 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10781 11:16:58.415866 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10782 11:16:58.416067 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10783 11:16:58.416244 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10784 11:16:58.416415 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10785 11:16:58.416587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10786 11:16:58.416761 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10787 11:16:58.416962 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10788 11:16:58.417138 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10789 11:16:58.417311 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10790 11:16:58.417482 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10791 11:16:58.417681 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10792 11:16:58.417858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10793 11:16:58.418031 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10794 11:16:58.418204 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10795 11:16:58.418411 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10796 11:16:58.418582 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10797 11:16:58.418758 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10798 11:16:58.418933 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10799 11:16:58.419106 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10800 11:16:58.419280 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10801 11:16:58.421947 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10802 11:16:58.422359 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10803 11:16:58.422524 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10804 11:16:58.422675 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10805 11:16:58.422858 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10806 11:16:58.423010 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10807 11:16:58.423163 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10808 11:16:58.423341 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10809 11:16:58.423496 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10810 11:16:58.423649 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10811 11:16:58.423823 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10812 11:16:58.423974 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10813 11:16:58.424150 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10814 11:16:58.424309 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10815 11:16:58.424488 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10816 11:16:58.424645 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10817 11:16:58.424823 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10818 11:16:58.424997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10819 11:16:58.425171 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10820 11:16:58.425344 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10821 11:16:58.425520 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10822 11:16:58.425716 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10823 11:16:58.425896 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10824 11:16:58.429999 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10825 11:16:58.430541 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10826 11:16:58.430730 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10827 11:16:58.430886 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10828 11:16:58.431039 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10829 11:16:58.431220 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10830 11:16:58.431375 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10831 11:16:58.431525 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10832 11:16:58.431674 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10833 11:16:58.431823 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10834 11:16:58.432000 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10835 11:16:58.432153 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10836 11:16:58.432299 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10837 11:16:58.432447 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10838 11:16:58.432598 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10839 11:16:58.432747 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10840 11:16:58.432926 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10841 11:16:58.433078 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10842 11:16:58.433228 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10843 11:16:58.433379 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10844 11:16:58.433526 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10845 11:16:58.433727 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10846 11:16:58.433917 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10847 11:16:58.434106 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10848 11:16:58.434264 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10849 11:16:58.434412 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10850 11:16:58.434561 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10851 11:16:58.434708 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10852 11:16:58.434856 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10853 11:16:58.438006 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10854 11:16:58.438465 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10855 11:16:58.438624 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10856 11:16:58.438777 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10857 11:16:58.438954 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10858 11:16:58.439106 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10859 11:16:58.439254 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10860 11:16:58.439403 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10861 11:16:58.439581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10862 11:16:58.439732 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10863 11:16:58.439878 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10864 11:16:58.440023 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10865 11:16:58.440169 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10866 11:16:58.440344 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10867 11:16:58.440493 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10868 11:16:58.440639 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10869 11:16:58.440786 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10870 11:16:58.440930 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10871 11:16:58.441074 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10872 11:16:58.441250 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10873 11:16:58.441399 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10874 11:16:58.441543 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10875 11:16:58.441700 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10876 11:16:58.441844 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10877 11:16:58.441987 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10878 11:16:58.442127 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10879 11:16:58.442296 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10880 11:16:58.442443 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10881 11:16:58.442587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10882 11:16:58.442736 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10883 11:16:58.446042 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10884 11:16:58.446522 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10885 11:16:58.446685 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10886 11:16:58.446836 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10887 11:16:58.446984 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10888 11:16:58.447162 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10889 11:16:58.447314 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10890 11:16:58.447462 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10891 11:16:58.447609 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10892 11:16:58.447756 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10893 11:16:58.447933 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10894 11:16:58.448086 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10895 11:16:58.448232 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10896 11:16:58.448378 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10897 11:16:58.448523 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10898 11:16:58.448666 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10899 11:16:58.448812 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10900 11:16:58.448990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10901 11:16:58.449139 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10902 11:16:58.449284 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10903 11:16:58.449429 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10904 11:16:58.449573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10905 11:16:58.449737 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10906 11:16:58.449887 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10907 11:16:58.450034 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10908 11:16:58.458168 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10909 11:16:58.458733 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10910 11:16:58.458931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10911 11:16:58.459112 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10912 11:16:58.459303 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10913 11:16:58.459458 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10914 11:16:58.459594 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10915 11:16:58.459747 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10916 11:16:58.459882 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10917 11:16:58.460029 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10918 11:16:58.460186 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10919 11:16:58.460371 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10920 11:16:58.460530 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10921 11:16:58.460689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10922 11:16:58.460820 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10923 11:16:58.461047 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10924 11:16:58.461259 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10925 11:16:58.461444 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10926 11:16:58.461610 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10927 11:16:58.461787 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10928 11:16:58.461908 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10929 11:16:58.462022 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10930 11:16:58.462134 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10931 11:16:58.462247 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10932 11:16:58.462387 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10933 11:16:58.462507 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10934 11:16:58.462622 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10935 11:16:58.462733 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10936 11:16:58.462849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10937 11:16:58.466010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10938 11:16:58.466259 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10939 11:16:58.466602 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10940 11:16:58.466704 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10941 11:16:58.466787 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10942 11:16:58.466880 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10943 11:16:58.466958 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10944 11:16:58.467033 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10945 11:16:58.467124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10946 11:16:58.467406 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10947 11:16:58.467504 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10948 11:16:58.467600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10949 11:16:58.467679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10950 11:16:58.467774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10951 11:16:58.468072 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10952 11:16:58.468172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10953 11:16:58.468265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10954 11:16:58.468358 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10955 11:16:58.468449 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10956 11:16:58.468756 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10957 11:16:58.468856 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10958 11:16:58.468951 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10959 11:16:58.469042 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10960 11:16:58.469350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10961 11:16:58.469466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10962 11:16:58.469557 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10963 11:16:58.469656 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10964 11:16:58.473974 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10965 11:16:58.474367 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10966 11:16:58.474454 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10967 11:16:58.474522 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10968 11:16:58.474601 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10969 11:16:58.474679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10970 11:16:58.474757 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10971 11:16:58.474849 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10972 11:16:58.474935 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10973 11:16:58.475207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10974 11:16:58.475329 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10975 11:16:58.475410 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10976 11:16:58.475487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10977 11:16:58.475748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10978 11:16:58.475942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10979 11:16:58.476121 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10980 11:16:58.476305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
10981 11:16:58.476476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
10982 11:16:58.476650 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
10983 11:16:58.476802 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
10984 11:16:58.476965 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
10985 11:16:58.477110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
10986 11:16:58.477266 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
10987 11:16:58.477411 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
10988 11:16:58.477569 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
10989 11:16:58.477731 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
10990 11:16:58.477897 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
10991 11:16:58.478015 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
10992 11:16:58.481924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
10993 11:16:58.482244 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
10994 11:16:58.482339 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
10995 11:16:58.482440 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
10996 11:16:58.482559 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
10997 11:16:58.482852 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
10998 11:16:58.482944 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
10999 11:16:58.483041 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
11000 11:16:58.483327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
11001 11:16:58.483419 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
11002 11:16:58.483519 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
11003 11:16:58.483619 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
11004 11:16:58.483923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
11005 11:16:58.484034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
11006 11:16:58.484141 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
11007 11:16:58.484224 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
11008 11:16:58.484316 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
11009 11:16:58.484611 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
11010 11:16:58.484730 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
11011 11:16:58.484822 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
11012 11:16:58.484934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
11013 11:16:58.485228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
11014 11:16:58.485340 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
11015 11:16:58.485429 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
11016 11:16:58.485531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
11017 11:16:58.485633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
11018 11:16:58.485928 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
11019 11:16:58.489912 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
11020 11:16:58.490230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
11021 11:16:58.490330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
11022 11:16:58.490416 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
11023 11:16:58.490515 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
11024 11:16:58.490600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
11025 11:16:58.490700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
11026 11:16:58.490993 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
11027 11:16:58.491071 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
11028 11:16:58.491143 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
11029 11:16:58.491214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
11030 11:16:58.491496 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
11031 11:16:58.491572 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
11032 11:16:58.491646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
11033 11:16:58.491763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
11034 11:16:58.492029 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
11035 11:16:58.492306 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
11036 11:16:58.492393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
11037 11:16:58.492507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
11038 11:16:58.492620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
11039 11:16:58.492721 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
11040 11:16:58.492811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
11041 11:16:58.492906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
11042 11:16:58.493010 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
11043 11:16:58.493119 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
11044 11:16:58.493222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
11045 11:16:58.505670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
11046 11:16:58.506159 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
11047 11:16:58.506329 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
11048 11:16:58.506459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
11049 11:16:58.506836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
11050 11:16:58.507050 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
11051 11:16:58.507229 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
11052 11:16:58.507380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
11053 11:16:58.507551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
11054 11:16:58.507714 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
11055 11:16:58.507913 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
11056 11:16:58.508079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
11057 11:16:58.508267 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
11058 11:16:58.508456 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
11059 11:16:58.508650 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
11060 11:16:58.508866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
11061 11:16:58.509070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
11062 11:16:58.509230 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
11063 11:16:58.509391 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
11064 11:16:58.509549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
11065 11:16:58.509750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
11066 11:16:58.509914 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
11067 11:16:58.510033 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
11068 11:16:58.510148 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
11069 11:16:58.510290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
11070 11:16:58.510411 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
11071 11:16:58.510525 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
11072 11:16:58.510638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
11073 11:16:58.513971 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
11074 11:16:58.514434 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
11075 11:16:58.514665 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
11076 11:16:58.514872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
11077 11:16:58.515101 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
11078 11:16:58.515278 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
11079 11:16:58.515443 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
11080 11:16:58.515606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
11081 11:16:58.515797 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
11082 11:16:58.515963 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
11083 11:16:58.516121 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
11084 11:16:58.516280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
11085 11:16:58.516445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
11086 11:16:58.516610 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
11087 11:16:58.516769 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
11088 11:16:58.516967 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
11089 11:16:58.517133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
11090 11:16:58.517296 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
11091 11:16:58.517461 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
11092 11:16:58.517624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
11093 11:16:58.518213 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
11094 11:16:58.518385 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
11095 11:16:58.518530 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
11096 11:16:58.518672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
11097 11:16:58.518814 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
11098 11:16:58.518996 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
11099 11:16:58.519133 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
11100 11:16:58.519275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
11101 11:16:58.519416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
11102 11:16:58.519557 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
11103 11:16:58.521935 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
11104 11:16:58.522381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
11105 11:16:58.522576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
11106 11:16:58.522743 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
11107 11:16:58.522965 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
11108 11:16:58.523151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
11109 11:16:58.523333 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
11110 11:16:58.523479 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
11111 11:16:58.523687 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
11112 11:16:58.523867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
11113 11:16:58.524028 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
11114 11:16:58.524237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
11115 11:16:58.524410 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
11116 11:16:58.524608 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
11117 11:16:58.524896 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
11118 11:16:58.525118 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
11119 11:16:58.525366 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
11120 11:16:58.525633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
11121 11:16:58.526174 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
11122 11:16:58.526345 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
11123 11:16:58.526521 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
11124 11:16:58.529912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
11125 11:16:58.530340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
11126 11:16:58.530504 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
11127 11:16:58.530664 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
11128 11:16:58.530853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
11129 11:16:58.531007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
11130 11:16:58.531162 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
11131 11:16:58.531317 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
11132 11:16:58.531500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
11133 11:16:58.531667 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
11134 11:16:58.531829 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
11135 11:16:58.531988 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
11136 11:16:58.532180 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
11137 11:16:58.532348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
11138 11:16:58.532510 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
11139 11:16:58.532668 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
11140 11:16:58.532826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
11141 11:16:58.533021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
11142 11:16:58.533187 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
11143 11:16:58.533349 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
11144 11:16:58.533502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
11145 11:16:58.534077 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
11146 11:16:58.534228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
11147 11:16:58.534375 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
11148 11:16:58.534495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
11149 11:16:58.534610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
11150 11:16:58.534722 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
11151 11:16:58.534834 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
11152 11:16:58.537904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
11153 11:16:58.538366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
11154 11:16:58.538480 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
11155 11:16:58.538570 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
11156 11:16:58.538674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
11157 11:16:58.538763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
11158 11:16:58.538864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
11159 11:16:58.538966 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
11160 11:16:58.539267 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
11161 11:16:58.539385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
11162 11:16:58.539488 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
11163 11:16:58.539587 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
11164 11:16:58.539884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
11165 11:16:58.540001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
11166 11:16:58.540346 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
11167 11:16:58.540554 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
11168 11:16:58.540733 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
11169 11:16:58.540862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
11170 11:16:58.540982 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
11171 11:16:58.541096 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
11172 11:16:58.541210 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
11173 11:16:58.541323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
11174 11:16:58.541428 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
11175 11:16:58.541536 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
11176 11:16:58.541624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
11177 11:16:58.541754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
11178 11:16:58.541843 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
11179 11:16:58.545889 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
11180 11:16:58.546181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
11181 11:16:58.555199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
11182 11:16:58.555484 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
11183 11:16:58.555602 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
11184 11:16:58.555704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
11185 11:16:58.555818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
11186 11:16:58.555914 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
11187 11:16:58.556006 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
11188 11:16:58.556099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
11189 11:16:58.556178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
11190 11:16:58.556475 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
11191 11:16:58.556582 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
11192 11:16:58.556688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
11193 11:16:58.556800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
11194 11:16:58.557104 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
11195 11:16:58.557204 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
11196 11:16:58.557305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
11197 11:16:58.557613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
11198 11:16:58.557742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
11199 11:16:58.557849 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
11200 11:16:58.558145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
11201 11:16:58.558237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
11202 11:16:58.558522 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
11203 11:16:58.558613 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
11204 11:16:58.558711 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
11205 11:16:58.558814 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
11206 11:16:58.559122 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
11207 11:16:58.559220 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
11208 11:16:58.559321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
11209 11:16:58.559417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
11210 11:16:58.559525 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
11211 11:16:58.559631 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
11212 11:16:58.559920 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
11213 11:16:58.559999 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
11214 11:16:58.560279 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
11215 11:16:58.560367 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
11216 11:16:58.560446 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
11217 11:16:58.560537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
11218 11:16:58.560616 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
11219 11:16:58.560702 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
11220 11:16:58.560792 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
11221 11:16:58.560870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
11222 11:16:58.560970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
11223 11:16:58.561239 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
11224 11:16:58.561326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
11225 11:16:58.561419 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11226 11:16:58.561598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11227 11:16:58.561718 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11228 11:16:58.565947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11229 11:16:58.566354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11230 11:16:58.566568 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11231 11:16:58.566747 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11232 11:16:58.566934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11233 11:16:58.567094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11234 11:16:58.567263 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11235 11:16:58.567424 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11236 11:16:58.567661 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11237 11:16:58.567842 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11238 11:16:58.568019 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11239 11:16:58.568192 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11240 11:16:58.568351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11241 11:16:58.568536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11242 11:16:58.568685 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11243 11:16:58.568808 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11244 11:16:58.568964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11245 11:16:58.569120 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11246 11:16:58.569267 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11247 11:16:58.569441 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11248 11:16:58.569591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11249 11:16:58.570072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11250 11:16:58.570206 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11251 11:16:58.570322 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11252 11:16:58.570436 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11253 11:16:58.570578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11254 11:16:58.570700 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11255 11:16:58.577906 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11256 11:16:58.578392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11257 11:16:58.578566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11258 11:16:58.578700 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11259 11:16:58.578872 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11260 11:16:58.579026 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11261 11:16:58.579174 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11262 11:16:58.579295 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11263 11:16:58.579459 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11264 11:16:58.579618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11265 11:16:58.579772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11266 11:16:58.579927 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11267 11:16:58.580097 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11268 11:16:58.580231 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11269 11:16:58.580370 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11270 11:16:58.580497 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11271 11:16:58.580618 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11272 11:16:58.580767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11273 11:16:58.580920 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11274 11:16:58.581071 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11275 11:16:58.581225 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11276 11:16:58.581377 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11277 11:16:58.581560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11278 11:16:58.582171 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11279 11:16:58.582306 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11280 11:16:58.582422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11281 11:16:58.582534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11282 11:16:58.582671 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11283 11:16:58.582788 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11284 11:16:58.582902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11285 11:16:58.585932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11286 11:16:58.586318 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11287 11:16:58.586486 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11288 11:16:58.586666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11289 11:16:58.586881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11290 11:16:58.587031 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11291 11:16:58.587158 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11292 11:16:58.587312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11293 11:16:58.587495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11294 11:16:58.587639 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11295 11:16:58.587821 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11296 11:16:58.587979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11297 11:16:58.588145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11298 11:16:58.588363 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11299 11:16:58.588550 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11300 11:16:58.588716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11301 11:16:58.588875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11302 11:16:58.589044 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11303 11:16:58.589204 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11304 11:16:58.589399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11305 11:16:58.589568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11306 11:16:58.589742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11307 11:16:58.589894 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11308 11:16:58.590013 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11309 11:16:58.590123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11310 11:16:58.590234 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11311 11:16:58.590368 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11312 11:16:58.590483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11313 11:16:58.590593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11314 11:16:58.593916 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11315 11:16:58.602898 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11316 11:16:58.603508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11317 11:16:58.603688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11318 11:16:58.603846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11319 11:16:58.604007 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11320 11:16:58.604194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11321 11:16:58.604359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11322 11:16:58.604518 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11323 11:16:58.604683 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11324 11:16:58.604844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11325 11:16:58.605004 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11326 11:16:58.605200 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11327 11:16:58.605370 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11328 11:16:58.605528 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11329 11:16:58.605697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11330 11:16:58.605831 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11331 11:16:58.605948 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11332 11:16:58.606060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11333 11:16:58.606172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11334 11:16:58.606311 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11335 11:16:58.606430 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11336 11:16:58.606543 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11337 11:16:58.606656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11338 11:16:58.609957 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11339 11:16:58.610352 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11340 11:16:58.610507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11341 11:16:58.610656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11342 11:16:58.610833 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11343 11:16:58.610971 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11344 11:16:58.611097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11345 11:16:58.611219 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11346 11:16:58.611358 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11347 11:16:58.611482 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11348 11:16:58.611599 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11349 11:16:58.611732 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11350 11:16:58.611939 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11351 11:16:58.612076 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11352 11:16:58.612216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11353 11:16:58.612354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11354 11:16:58.612495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11355 11:16:58.612636 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11356 11:16:58.612834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11357 11:16:58.613018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11358 11:16:58.613224 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11359 11:16:58.613396 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11360 11:16:58.613557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11361 11:16:58.613725 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11362 11:16:58.613846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11363 11:16:58.613990 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11364 11:16:58.614109 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11365 11:16:58.614224 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11366 11:16:58.614337 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11367 11:16:58.614448 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11368 11:16:58.614558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11369 11:16:58.617940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11370 11:16:58.618370 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11371 11:16:58.618558 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11372 11:16:58.618719 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11373 11:16:58.618921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11374 11:16:58.619090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11375 11:16:58.619254 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11376 11:16:58.619413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11377 11:16:58.619593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11378 11:16:58.619759 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11379 11:16:58.619919 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11380 11:16:58.620075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11381 11:16:58.620229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11382 11:16:58.620418 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11383 11:16:58.620579 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11384 11:16:58.620738 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11385 11:16:58.620891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11386 11:16:58.621048 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11387 11:16:58.621207 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11388 11:16:58.621363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11389 11:16:58.621560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11390 11:16:58.622097 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11391 11:16:58.622230 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11392 11:16:58.622347 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11393 11:16:58.622462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11394 11:16:58.622576 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11395 11:16:58.622688 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11396 11:16:58.622801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11397 11:16:58.622941 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11398 11:16:58.626042 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11399 11:16:58.626343 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11400 11:16:58.626443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11401 11:16:58.626543 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11402 11:16:58.626640 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11403 11:16:58.626925 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11404 11:16:58.627015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11405 11:16:58.627112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11406 11:16:58.627395 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11407 11:16:58.627484 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11408 11:16:58.627580 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11409 11:16:58.627676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11410 11:16:58.627957 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11411 11:16:58.628060 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11412 11:16:58.628157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11413 11:16:58.628435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11414 11:16:58.628537 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11415 11:16:58.628633 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11416 11:16:58.628914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11417 11:16:58.629002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11418 11:16:58.629103 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11419 11:16:58.629382 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11420 11:16:58.629470 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11421 11:16:58.629562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11422 11:16:58.629851 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11423 11:16:58.633972 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11424 11:16:58.634256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11425 11:16:58.634360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11426 11:16:58.634445 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11427 11:16:58.634542 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11428 11:16:58.634638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11429 11:16:58.634919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11430 11:16:58.635008 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11431 11:16:58.635110 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11432 11:16:58.635397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11433 11:16:58.635487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11434 11:16:58.635584 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11435 11:16:58.635865 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11436 11:16:58.635954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11437 11:16:58.636050 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11438 11:16:58.636330 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11439 11:16:58.636419 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11440 11:16:58.636514 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11441 11:16:58.636635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11442 11:16:58.636930 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11443 11:16:58.637041 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11444 11:16:58.637366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11445 11:16:58.637582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11446 11:16:58.637763 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11447 11:16:58.637922 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11448 11:16:58.638045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11449 11:16:58.651273 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11450 11:16:58.651752 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11451 11:16:58.651925 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11452 11:16:58.652056 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11453 11:16:58.652209 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11454 11:16:58.652338 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11455 11:16:58.652462 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11456 11:16:58.652589 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11457 11:16:58.652738 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11458 11:16:58.652873 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11459 11:16:58.653044 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11460 11:16:58.653187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11461 11:16:58.653332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11462 11:16:58.653555 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11463 11:16:58.653732 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11464 11:16:58.653873 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11465 11:16:58.654019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11466 11:16:58.654155 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11467 11:16:58.654301 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11468 11:16:58.654460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11469 11:16:58.654595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11470 11:16:58.654727 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11471 11:16:58.654926 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11472 11:16:58.655124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11473 11:16:58.655294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11474 11:16:58.655474 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11475 11:16:58.655606 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11476 11:16:58.655783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11477 11:16:58.655950 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11478 11:16:58.656096 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11479 11:16:58.656282 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11480 11:16:58.656462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11481 11:16:58.656625 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11482 11:16:58.657095 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11483 11:16:58.657288 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11484 11:16:58.657454 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11485 11:16:58.657611 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11486 11:16:58.657770 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11487 11:16:58.657922 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11488 11:16:58.658046 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11489 11:16:58.658164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11490 11:16:58.658278 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11491 11:16:58.658392 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11492 11:16:58.658506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11493 11:16:58.658646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11494 11:16:58.658765 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11495 11:16:58.658879 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11496 11:16:58.658992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11497 11:16:58.659106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11498 11:16:58.665948 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11499 11:16:58.666139 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11500 11:16:58.666531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11501 11:16:58.666722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11502 11:16:58.666880 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11503 11:16:58.667039 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11504 11:16:58.667217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11505 11:16:58.667362 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11506 11:16:58.667506 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11507 11:16:58.667671 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11508 11:16:58.667878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11509 11:16:58.668073 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11510 11:16:58.668242 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11511 11:16:58.668396 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11512 11:16:58.668554 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11513 11:16:58.668749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11514 11:16:58.668915 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11515 11:16:58.669077 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11516 11:16:58.669235 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11517 11:16:58.669398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11518 11:16:58.669560 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11519 11:16:58.670091 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11520 11:16:58.670230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11521 11:16:58.670347 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11522 11:16:58.670462 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11523 11:16:58.670576 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11524 11:16:58.670690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11525 11:16:58.670804 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11526 11:16:58.674111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11527 11:16:58.674280 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11528 11:16:58.674627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11529 11:16:58.674806 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11530 11:16:58.675009 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11531 11:16:58.675225 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11532 11:16:58.675441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11533 11:16:58.675632 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11534 11:16:58.675803 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11535 11:16:58.675958 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11536 11:16:58.676158 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11537 11:16:58.676320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11538 11:16:58.676485 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11539 11:16:58.676648 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11540 11:16:58.676843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11541 11:16:58.677028 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11542 11:16:58.677226 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11543 11:16:58.677401 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11544 11:16:58.677596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11545 11:16:58.678176 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11546 11:16:58.678304 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11547 11:16:58.678417 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11548 11:16:58.678529 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11549 11:16:58.678640 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11550 11:16:58.678751 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11551 11:16:58.678862 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11552 11:16:58.678972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11553 11:16:58.679109 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11554 11:16:58.681979 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11555 11:16:58.682415 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11556 11:16:58.682594 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11557 11:16:58.682741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11558 11:16:58.682922 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11559 11:16:58.683080 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11560 11:16:58.683239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11561 11:16:58.683396 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11562 11:16:58.683587 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11563 11:16:58.683753 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11564 11:16:58.683915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11565 11:16:58.684080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11566 11:16:58.684250 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11567 11:16:58.684451 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11568 11:16:58.684697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11569 11:16:58.684875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11570 11:16:58.685041 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11571 11:16:58.685208 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11572 11:16:58.685369 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11573 11:16:58.685536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11574 11:16:58.685718 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11575 11:16:58.685917 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11576 11:16:58.686128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11577 11:16:58.686263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11578 11:16:58.686401 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11579 11:16:58.686542 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11580 11:16:58.686681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11581 11:16:58.686820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11582 11:16:58.686959 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11583 11:16:58.698754 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11584 11:16:58.699186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11585 11:16:58.699346 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11586 11:16:58.699515 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11587 11:16:58.699706 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11588 11:16:58.699870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11589 11:16:58.700014 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11590 11:16:58.700161 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11591 11:16:58.700402 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11592 11:16:58.700582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11593 11:16:58.700748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11594 11:16:58.700915 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11595 11:16:58.701078 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11596 11:16:58.701274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11597 11:16:58.701444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11598 11:16:58.701605 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11599 11:16:58.701780 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11600 11:16:58.701922 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11601 11:16:58.702037 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11602 11:16:58.702178 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11603 11:16:58.702295 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11604 11:16:58.702406 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11605 11:16:58.705983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11606 11:16:58.706417 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11607 11:16:58.706598 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11608 11:16:58.706760 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11609 11:16:58.706949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11610 11:16:58.707119 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11611 11:16:58.707290 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11612 11:16:58.707447 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11613 11:16:58.707638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11614 11:16:58.707796 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11615 11:16:58.707957 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11616 11:16:58.708114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11617 11:16:58.708270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11618 11:16:58.708456 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11619 11:16:58.708592 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11620 11:16:58.708739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11621 11:16:58.708886 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11622 11:16:58.709065 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11623 11:16:58.709205 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11624 11:16:58.709350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11625 11:16:58.709499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11626 11:16:58.710013 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11627 11:16:58.710195 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11628 11:16:58.710316 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11629 11:16:58.710431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11630 11:16:58.710543 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11631 11:16:58.713994 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11632 11:16:58.714447 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11633 11:16:58.714670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11634 11:16:58.714867 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11635 11:16:58.715054 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11636 11:16:58.715262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11637 11:16:58.715422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11638 11:16:58.715583 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11639 11:16:58.715712 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11640 11:16:58.715835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11641 11:16:58.716011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11642 11:16:58.716166 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11643 11:16:58.716316 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11644 11:16:58.716475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11645 11:16:58.716671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11646 11:16:58.716907 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11647 11:16:58.717104 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11648 11:16:58.717315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11649 11:16:58.717510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11650 11:16:58.718067 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11651 11:16:58.718219 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11652 11:16:58.718338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11653 11:16:58.718453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11654 11:16:58.718600 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11655 11:16:58.718723 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11656 11:16:58.718839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11657 11:16:58.718954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11658 11:16:58.719069 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11659 11:16:58.719180 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11660 11:16:58.719293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11661 11:16:58.722211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11662 11:16:58.722419 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11663 11:16:58.722635 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11664 11:16:58.722859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11665 11:16:58.723036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11666 11:16:58.723256 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11667 11:16:58.723449 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11668 11:16:58.723581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11669 11:16:58.723767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11670 11:16:58.723893 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11671 11:16:58.724089 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11672 11:16:58.724336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11673 11:16:58.724525 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11674 11:16:58.724662 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11675 11:16:58.724816 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11676 11:16:58.724984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11677 11:16:58.725105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11678 11:16:58.725217 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11679 11:16:58.725328 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11680 11:16:58.725440 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11681 11:16:58.725561 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11682 11:16:58.725764 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11683 11:16:58.725991 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11684 11:16:58.726132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11685 11:16:58.726249 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11686 11:16:58.726361 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11687 11:16:58.726473 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11688 11:16:58.726586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11689 11:16:58.726722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11690 11:16:58.729949 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11691 11:16:58.730244 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11692 11:16:58.730342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11693 11:16:58.730441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11694 11:16:58.730770 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11695 11:16:58.730945 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11696 11:16:58.731074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11697 11:16:58.731264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11698 11:16:58.731424 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11699 11:16:58.731606 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11700 11:16:58.731765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11701 11:16:58.731930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11702 11:16:58.732087 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11703 11:16:58.732250 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11704 11:16:58.732434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11705 11:16:58.732600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11706 11:16:58.732766 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11707 11:16:58.732960 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11708 11:16:58.733124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11709 11:16:58.733285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11710 11:16:58.733473 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11711 11:16:58.733623 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11712 11:16:58.733792 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11713 11:16:58.733940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11714 11:16:58.734059 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11715 11:16:58.734172 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11716 11:16:58.737940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11717 11:16:58.748801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11718 11:16:58.749190 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11719 11:16:58.749331 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11720 11:16:58.749456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11721 11:16:58.749606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11722 11:16:58.749747 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11723 11:16:58.749859 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11724 11:16:58.749972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11725 11:16:58.750111 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11726 11:16:58.750211 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11727 11:16:58.750369 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11728 11:16:58.750494 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11729 11:16:58.750645 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11730 11:16:58.750798 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11731 11:16:58.750923 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11732 11:16:58.751030 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11733 11:16:58.751160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11734 11:16:58.751292 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11735 11:16:58.751399 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11736 11:16:58.751526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11737 11:16:58.751640 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11738 11:16:58.751776 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11739 11:16:58.751897 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11740 11:16:58.752002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11741 11:16:58.752162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11742 11:16:58.752270 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11743 11:16:58.752378 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11744 11:16:58.752506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11745 11:16:58.752635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11746 11:16:58.752758 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11747 11:16:58.752860 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11748 11:16:58.753173 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11749 11:16:58.753311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11750 11:16:58.753439 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11751 11:16:58.753575 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11752 11:16:58.753718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11753 11:16:58.753821 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11754 11:16:58.753923 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11755 11:16:58.757958 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11756 11:16:58.758295 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11757 11:16:58.758423 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11758 11:16:58.758547 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11759 11:16:58.758638 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11760 11:16:58.758705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11761 11:16:58.758783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11762 11:16:58.758853 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11763 11:16:58.758948 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11764 11:16:58.759038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11765 11:16:58.759289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11766 11:16:58.759374 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11767 11:16:58.759445 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11768 11:16:58.759752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11769 11:16:58.759946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11770 11:16:58.760142 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11771 11:16:58.760291 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11772 11:16:58.760432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11773 11:16:58.760792 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11774 11:16:58.760966 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11775 11:16:58.761090 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11776 11:16:58.761228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11777 11:16:58.761349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11778 11:16:58.761488 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11779 11:16:58.761608 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11780 11:16:58.761753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11781 11:16:58.761871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11782 11:16:58.761985 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11783 11:16:58.762123 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11784 11:16:58.762239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11785 11:16:58.765916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11786 11:16:58.766324 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11787 11:16:58.766517 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11788 11:16:58.766681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11789 11:16:58.766868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11790 11:16:58.767030 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11791 11:16:58.767187 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11792 11:16:58.767342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11793 11:16:58.767527 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11794 11:16:58.767693 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11795 11:16:58.767869 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11796 11:16:58.768009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11797 11:16:58.768147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11798 11:16:58.768297 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11799 11:16:58.768448 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11800 11:16:58.768633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11801 11:16:58.768796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11802 11:16:58.768957 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11803 11:16:58.769114 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11804 11:16:58.769273 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11805 11:16:58.769409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11806 11:16:58.769565 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11807 11:16:58.769718 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11808 11:16:58.769862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11809 11:16:58.769981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11810 11:16:58.770093 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11811 11:16:58.770204 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11812 11:16:58.770315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11813 11:16:58.770427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11814 11:16:58.770539 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11815 11:16:58.770649 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11816 11:16:58.770760 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11817 11:16:58.773962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11818 11:16:58.774343 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11819 11:16:58.774497 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11820 11:16:58.774630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11821 11:16:58.774812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11822 11:16:58.774957 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11823 11:16:58.775115 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11824 11:16:58.775276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11825 11:16:58.775435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11826 11:16:58.775588 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11827 11:16:58.775729 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11828 11:16:58.775893 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11829 11:16:58.776053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11830 11:16:58.776215 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11831 11:16:58.776369 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11832 11:16:58.776532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11833 11:16:58.776720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11834 11:16:58.776873 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11835 11:16:58.777007 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11836 11:16:58.777136 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11837 11:16:58.777299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11838 11:16:58.777444 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11839 11:16:58.777606 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11840 11:16:58.777800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11841 11:16:58.777924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11842 11:16:58.778038 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11843 11:16:58.778152 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11844 11:16:58.778265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11845 11:16:58.778383 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11846 11:16:58.778497 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11847 11:16:58.782010 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11848 11:16:58.782409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11849 11:16:58.782539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11850 11:16:58.782670 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11851 11:16:58.794949 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11852 11:16:58.795113 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11853 11:16:58.795479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11854 11:16:58.795637 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11855 11:16:58.795795 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11856 11:16:58.795946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11857 11:16:58.796129 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11858 11:16:58.796284 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11859 11:16:58.796437 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11860 11:16:58.796578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11861 11:16:58.796715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11862 11:16:58.796867 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11863 11:16:58.797050 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11864 11:16:58.797188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11865 11:16:58.797341 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11866 11:16:58.797496 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11867 11:16:58.797660 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11868 11:16:58.797788 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11869 11:16:58.797905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11870 11:16:58.798019 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11871 11:16:58.798159 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11872 11:16:58.798275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11873 11:16:58.798390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11874 11:16:58.798502 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11875 11:16:58.798614 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11876 11:16:58.798726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11877 11:16:58.802121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11878 11:16:58.802229 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11879 11:16:58.802328 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11880 11:16:58.802654 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11881 11:16:58.802753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11882 11:16:58.802856 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11883 11:16:58.803188 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11884 11:16:58.803394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11885 11:16:58.803660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11886 11:16:58.803847 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11887 11:16:58.804019 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11888 11:16:58.804216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11889 11:16:58.804444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11890 11:16:58.804645 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11891 11:16:58.804855 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11892 11:16:58.805030 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11893 11:16:58.805193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11894 11:16:58.805361 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11895 11:16:58.805575 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11896 11:16:58.805795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11897 11:16:58.805942 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11898 11:16:58.806059 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11899 11:16:58.806175 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11900 11:16:58.806313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11901 11:16:58.810126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11902 11:16:58.810267 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11903 11:16:58.810382 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11904 11:16:58.810689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11905 11:16:58.810800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11906 11:16:58.811092 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11907 11:16:58.811209 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11908 11:16:58.811320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11909 11:16:58.811618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11910 11:16:58.811717 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11911 11:16:58.811832 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11912 11:16:58.811934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11913 11:16:58.812232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11914 11:16:58.812368 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11915 11:16:58.812501 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11916 11:16:58.812791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11917 11:16:58.812901 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11918 11:16:58.813195 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11919 11:16:58.813300 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11920 11:16:58.813403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11921 11:16:58.813487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11922 11:16:58.813598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11923 11:16:58.813820 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11924 11:16:58.817943 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11925 11:16:58.818348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11926 11:16:58.818470 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11927 11:16:58.818594 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11928 11:16:58.818698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11929 11:16:58.818805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11930 11:16:58.818926 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11931 11:16:58.819036 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11932 11:16:58.819136 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11933 11:16:58.819239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11934 11:16:58.819529 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11935 11:16:58.819617 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11936 11:16:58.819722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11937 11:16:58.819834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11938 11:16:58.820128 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11939 11:16:58.820226 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11940 11:16:58.820350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11941 11:16:58.820429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11942 11:16:58.820514 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11943 11:16:58.820604 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11944 11:16:58.820697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11945 11:16:58.820967 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11946 11:16:58.821265 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11947 11:16:58.821362 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11948 11:16:58.821463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11949 11:16:58.821744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11950 11:16:58.821834 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11951 11:16:58.825939 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11952 11:16:58.826270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11953 11:16:58.826390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11954 11:16:58.826493 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11955 11:16:58.826582 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11956 11:16:58.826662 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11957 11:16:58.826945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11958 11:16:58.827056 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11959 11:16:58.827171 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11960 11:16:58.827267 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11961 11:16:58.827541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11962 11:16:58.827644 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11963 11:16:58.827753 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11964 11:16:58.828051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11965 11:16:58.828160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11966 11:16:58.828438 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11967 11:16:58.828520 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11968 11:16:58.828611 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11969 11:16:58.828707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11970 11:16:58.828998 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11971 11:16:58.829093 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11972 11:16:58.829193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11973 11:16:58.829549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11974 11:16:58.829746 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11975 11:16:58.829902 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11976 11:16:58.833992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11977 11:16:58.834528 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11978 11:16:58.834742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11979 11:16:58.834932 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11980 11:16:58.835129 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
11981 11:16:58.835256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
11982 11:16:58.835373 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
11983 11:16:58.835533 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
11984 11:16:58.835679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
11985 11:16:58.844381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
11986 11:16:58.844821 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
11987 11:16:58.845015 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
11988 11:16:58.845228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
11989 11:16:58.845496 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
11990 11:16:58.845689 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
11991 11:16:58.845871 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
11992 11:16:58.846042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
11993 11:16:58.846215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
11994 11:16:58.846381 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
11995 11:16:58.846591 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
11996 11:16:58.846775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
11997 11:16:58.846949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
11998 11:16:58.847117 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
11999 11:16:58.847294 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
12000 11:16:58.847460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
12001 11:16:58.847616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
12002 11:16:58.847769 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
12003 11:16:58.847917 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
12004 11:16:58.848111 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
12005 11:16:58.848283 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
12006 11:16:58.848462 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
12007 11:16:58.848635 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
12008 11:16:58.848805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
12009 11:16:58.849015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
12010 11:16:58.849192 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
12011 11:16:58.849374 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
12012 11:16:58.849550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
12013 11:16:58.849784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
12014 11:16:58.849997 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
12015 11:16:58.850145 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
12016 11:16:58.850292 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
12017 11:16:58.854016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
12018 11:16:58.854440 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
12019 11:16:58.854552 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
12020 11:16:58.854660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
12021 11:16:58.854777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
12022 11:16:58.854868 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
12023 11:16:58.854989 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
12024 11:16:58.855090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
12025 11:16:58.855212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
12026 11:16:58.855328 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
12027 11:16:58.855439 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
12028 11:16:58.855557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
12029 11:16:58.855865 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
12030 11:16:58.855980 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
12031 11:16:58.856075 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
12032 11:16:58.856258 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
12033 11:16:58.856364 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
12034 11:16:58.856665 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
12035 11:16:58.856779 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
12036 11:16:58.856888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
12037 11:16:58.856996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
12038 11:16:58.857297 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
12039 11:16:58.857395 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
12040 11:16:58.857523 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
12041 11:16:58.857642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
12042 11:16:58.861937 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
12043 11:16:58.862375 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
12044 11:16:58.862563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
12045 11:16:58.862730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
12046 11:16:58.862886 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
12047 11:16:58.863018 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
12048 11:16:58.863126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
12049 11:16:58.863263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
12050 11:16:58.863425 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
12051 11:16:58.863562 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
12052 11:16:58.863707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
12053 11:16:58.863875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
12054 11:16:58.864014 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
12055 11:16:58.864151 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
12056 11:16:58.864276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
12057 11:16:58.864437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
12058 11:16:58.864556 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
12059 11:16:58.864636 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
12060 11:16:58.864715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
12061 11:16:58.864811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
12062 11:16:58.864890 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
12063 11:16:58.864964 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
12064 11:16:58.865055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
12065 11:16:58.865148 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
12066 11:16:58.865244 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
12067 11:16:58.865339 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
12068 11:16:58.865637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
12069 11:16:58.865771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
12070 11:16:58.869934 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
12071 11:16:58.870232 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
12072 11:16:58.870325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
12073 11:16:58.870429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
12074 11:16:58.870720 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
12075 11:16:58.870810 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
12076 11:16:58.870911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
12077 11:16:58.871018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
12078 11:16:58.871315 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
12079 11:16:58.871425 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
12080 11:16:58.871705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
12081 11:16:58.871795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
12082 11:16:58.871894 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
12083 11:16:58.871994 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
12084 11:16:58.872272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
12085 11:16:58.872379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
12086 11:16:58.872654 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
12087 11:16:58.872758 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
12088 11:16:58.872849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
12089 11:16:58.873145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
12090 11:16:58.873243 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
12091 11:16:58.873345 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
12092 11:16:58.873445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
12093 11:16:58.873685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
12094 11:16:58.877902 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
12095 11:16:58.878205 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
12096 11:16:58.878312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
12097 11:16:58.878412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
12098 11:16:58.878513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
12099 11:16:58.878799 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
12100 11:16:58.878891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
12101 11:16:58.878991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
12102 11:16:58.879092 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
12103 11:16:58.879197 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
12104 11:16:58.879304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
12105 11:16:58.879601 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
12106 11:16:58.879716 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
12107 11:16:58.879819 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
12108 11:16:58.879919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
12109 11:16:58.880018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
12110 11:16:58.880370 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
12111 11:16:58.880476 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
12112 11:16:58.880589 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
12113 11:16:58.880708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
12114 11:16:58.880797 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
12115 11:16:58.880898 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
12116 11:16:58.880984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
12117 11:16:58.881082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
12118 11:16:58.881368 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
12119 11:16:58.894440 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
12120 11:16:58.894744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
12121 11:16:58.894850 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
12122 11:16:58.894955 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
12123 11:16:58.895045 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
12124 11:16:58.895147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
12125 11:16:58.895245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
12126 11:16:58.895551 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
12127 11:16:58.895662 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
12128 11:16:58.895769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
12129 11:16:58.895876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
12130 11:16:58.895984 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
12131 11:16:58.896084 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
12132 11:16:58.896277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
12133 11:16:58.896398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
12134 11:16:58.896700 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
12135 11:16:58.896805 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
12136 11:16:58.896905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
12137 11:16:58.896992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
12138 11:16:58.897292 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
12139 11:16:58.897489 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
12140 11:16:58.897701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
12141 11:16:58.897891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
12142 11:16:58.898064 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
12143 11:16:58.898241 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
12144 11:16:58.901986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
12145 11:16:58.902456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
12146 11:16:58.902617 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
12147 11:16:58.902742 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
12148 11:16:58.902861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
12149 11:16:58.903233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
12150 11:16:58.903455 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
12151 11:16:58.903626 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
12152 11:16:58.903801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
12153 11:16:58.903977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
12154 11:16:58.904245 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
12155 11:16:58.904444 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
12156 11:16:58.904653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
12157 11:16:58.904834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
12158 11:16:58.905007 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
12159 11:16:58.905205 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
12160 11:16:58.905415 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
12161 11:16:58.905624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
12162 11:16:58.905894 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
12163 11:16:58.906043 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
12164 11:16:58.906165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
12165 11:16:58.906284 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
12166 11:16:58.906402 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
12167 11:16:58.906520 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
12168 11:16:58.906637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
12169 11:16:58.906754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
12170 11:16:58.906873 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
12171 11:16:58.906990 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
12172 11:16:58.907107 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
12173 11:16:58.909961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
12174 11:16:58.910407 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
12175 11:16:58.910596 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
12176 11:16:58.910781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
12177 11:16:58.910997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
12178 11:16:58.911152 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
12179 11:16:58.911351 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
12180 11:16:58.911526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
12181 11:16:58.911704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
12182 11:16:58.911864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
12183 11:16:58.912039 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
12184 11:16:58.912228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
12185 11:16:58.912396 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
12186 11:16:58.912546 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
12187 11:16:58.912775 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
12188 11:16:58.912960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
12189 11:16:58.913172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
12190 11:16:58.913367 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
12191 11:16:58.913552 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
12192 11:16:58.913758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
12193 11:16:58.913903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
12194 11:16:58.914052 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
12195 11:16:58.914174 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
12196 11:16:58.914290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
12197 11:16:58.914405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
12198 11:16:58.914520 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
12199 11:16:58.914634 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
12200 11:16:58.914746 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
12201 11:16:58.914860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
12202 11:16:58.918169 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
12203 11:16:58.918398 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
12204 11:16:58.918621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
12205 11:16:58.918847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
12206 11:16:58.919024 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
12207 11:16:58.919194 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
12208 11:16:58.919387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
12209 11:16:58.919550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
12210 11:16:58.919678 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
12211 11:16:58.919788 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
12212 11:16:58.919945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
12213 11:16:58.920094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
12214 11:16:58.920262 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
12215 11:16:58.920411 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
12216 11:16:58.920600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
12217 11:16:58.920750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
12218 11:16:58.920899 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
12219 11:16:58.921059 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
12220 11:16:58.921216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
12221 11:16:58.921376 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
12222 11:16:58.921504 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
12223 11:16:58.921617 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
12224 11:16:58.922024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
12225 11:16:58.922123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12226 11:16:58.922212 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12227 11:16:58.922319 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12228 11:16:58.922412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12229 11:16:58.922500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12230 11:16:58.925903 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12231 11:16:58.926235 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12232 11:16:58.926443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12233 11:16:58.926617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12234 11:16:58.926818 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12235 11:16:58.926994 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12236 11:16:58.927163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12237 11:16:58.927322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12238 11:16:58.927558 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12239 11:16:58.927734 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12240 11:16:58.927888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12241 11:16:58.928042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12242 11:16:58.928221 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12243 11:16:58.928356 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12244 11:16:58.928503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12245 11:16:58.928657 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12246 11:16:58.928797 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12247 11:16:58.928932 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12248 11:16:58.929087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12249 11:16:58.929214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12250 11:16:58.929349 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12251 11:16:58.929465 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12252 11:16:58.929580 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12253 11:16:58.941978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12254 11:16:58.942437 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12255 11:16:58.942635 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12256 11:16:58.942797 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12257 11:16:58.942917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12258 11:16:58.943063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12259 11:16:58.943189 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12260 11:16:58.943315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12261 11:16:58.943444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12262 11:16:58.943597 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12263 11:16:58.943729 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12264 11:16:58.943852 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12265 11:16:58.944001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12266 11:16:58.944138 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12267 11:16:58.944308 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12268 11:16:58.944459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12269 11:16:58.944583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12270 11:16:58.944724 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12271 11:16:58.944864 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12272 11:16:58.945001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12273 11:16:58.945139 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12274 11:16:58.945478 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12275 11:16:58.945605 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12276 11:16:58.945759 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12277 11:16:58.945897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12278 11:16:58.950197 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12279 11:16:58.950410 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12280 11:16:58.950604 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12281 11:16:58.950747 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12282 11:16:58.950888 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12283 11:16:58.951073 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12284 11:16:58.951233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12285 11:16:58.951364 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12286 11:16:58.951513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12287 11:16:58.951643 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12288 11:16:58.951780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12289 11:16:58.951924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12290 11:16:58.952067 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12291 11:16:58.952218 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12292 11:16:58.952444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12293 11:16:58.952621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12294 11:16:58.952789 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12295 11:16:58.952951 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12296 11:16:58.953153 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12297 11:16:58.953324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12298 11:16:58.953502 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12299 11:16:58.954140 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12300 11:16:58.954290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12301 11:16:58.954437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12302 11:16:58.954561 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12303 11:16:58.954678 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12304 11:16:58.954796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12305 11:16:58.958000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12306 11:16:58.958188 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12307 11:16:58.958582 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12308 11:16:58.958801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12309 11:16:58.959038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12310 11:16:58.959252 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12311 11:16:58.959450 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12312 11:16:58.959702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12313 11:16:58.959897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12314 11:16:58.960072 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12315 11:16:58.960242 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12316 11:16:58.960430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12317 11:16:58.960626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12318 11:16:58.960798 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12319 11:16:58.960928 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12320 11:16:58.961087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12321 11:16:58.961217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12322 11:16:58.961382 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12323 11:16:58.961556 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12324 11:16:58.962179 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12325 11:16:58.962353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12326 11:16:58.962498 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12327 11:16:58.962639 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12328 11:16:58.962784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12329 11:16:58.962925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12330 11:16:58.963104 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12331 11:16:58.963241 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12332 11:16:58.963385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12333 11:16:58.963527 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12334 11:16:58.963669 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12335 11:16:58.965969 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12336 11:16:58.966455 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12337 11:16:58.966664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12338 11:16:58.966843 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12339 11:16:58.966995 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12340 11:16:58.967181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12341 11:16:58.967354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12342 11:16:58.967534 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12343 11:16:58.967690 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12344 11:16:58.967869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12345 11:16:58.968102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12346 11:16:58.968285 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12347 11:16:58.968444 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12348 11:16:58.968601 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12349 11:16:58.968751 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12350 11:16:58.968927 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12351 11:16:58.969108 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12352 11:16:58.969309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12353 11:16:58.969465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12354 11:16:58.969641 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12355 11:16:58.970281 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12356 11:16:58.970405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12357 11:16:58.970521 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12358 11:16:58.970637 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12359 11:16:58.970753 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12360 11:16:58.970869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12361 11:16:58.971012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12362 11:16:58.971133 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12363 11:16:58.971250 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12364 11:16:58.971366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12365 11:16:58.973962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12366 11:16:58.974457 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12367 11:16:58.974657 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12368 11:16:58.974859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12369 11:16:58.975065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12370 11:16:58.975207 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12371 11:16:58.975370 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12372 11:16:58.975568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12373 11:16:58.975823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12374 11:16:58.976000 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12375 11:16:58.976143 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12376 11:16:58.976307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12377 11:16:58.976447 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12378 11:16:58.976607 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12379 11:16:58.976781 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12380 11:16:58.976947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12381 11:16:58.977085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12382 11:16:58.977201 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12383 11:16:58.977368 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12384 11:16:58.977544 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12385 11:16:58.977684 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12386 11:16:58.977801 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12387 11:16:58.989552 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12388 11:16:58.989972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12389 11:16:58.990187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12390 11:16:58.990373 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12391 11:16:58.990557 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12392 11:16:58.990786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12393 11:16:58.990936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12394 11:16:58.991070 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12395 11:16:58.991256 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12396 11:16:58.991407 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12397 11:16:58.991562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12398 11:16:58.991727 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12399 11:16:58.991907 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12400 11:16:58.992073 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12401 11:16:58.992235 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12402 11:16:58.992372 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12403 11:16:58.992516 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12404 11:16:58.992689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12405 11:16:58.992834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12406 11:16:58.992989 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12407 11:16:58.993153 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12408 11:16:58.993314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12409 11:16:58.993507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12410 11:16:58.994013 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12411 11:16:58.994162 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12412 11:16:58.994283 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12413 11:16:58.994399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12414 11:16:58.994540 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12415 11:16:58.994664 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12416 11:16:58.994783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12417 11:16:58.997958 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12418 11:16:58.998415 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12419 11:16:58.998606 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12420 11:16:58.998768 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12421 11:16:58.998938 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12422 11:16:58.999089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12423 11:16:58.999247 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12424 11:16:58.999434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12425 11:16:58.999617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12426 11:16:58.999789 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12427 11:16:58.999976 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12428 11:16:59.000144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12429 11:16:59.000357 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12430 11:16:59.000551 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12431 11:16:59.000712 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12432 11:16:59.000867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12433 11:16:59.001008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12434 11:16:59.001171 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12435 11:16:59.001338 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12436 11:16:59.001502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12437 11:16:59.001667 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12438 11:16:59.001817 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12439 11:16:59.001937 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12440 11:16:59.002054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12441 11:16:59.002168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12442 11:16:59.002306 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12443 11:16:59.002424 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12444 11:16:59.002539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12445 11:16:59.005985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12446 11:16:59.006214 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12447 11:16:59.006666 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12448 11:16:59.006872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12449 11:16:59.007026 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12450 11:16:59.007190 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12451 11:16:59.007353 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12452 11:16:59.007531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12453 11:16:59.007706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12454 11:16:59.007857 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12455 11:16:59.008008 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12456 11:16:59.008178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12457 11:16:59.008328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12458 11:16:59.008517 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12459 11:16:59.008689 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12460 11:16:59.008834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12461 11:16:59.008995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12462 11:16:59.009157 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12463 11:16:59.009304 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12464 11:16:59.009470 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12465 11:16:59.010198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12466 11:16:59.010406 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12467 11:16:59.010577 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12468 11:16:59.010729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12469 11:16:59.010902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12470 11:16:59.011062 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12471 11:16:59.011210 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12472 11:16:59.011416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12473 11:16:59.013951 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12474 11:16:59.014368 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12475 11:16:59.014555 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12476 11:16:59.014721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12477 11:16:59.014924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12478 11:16:59.015079 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12479 11:16:59.015249 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12480 11:16:59.015434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12481 11:16:59.015588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12482 11:16:59.015760 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12483 11:16:59.015945 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12484 11:16:59.016106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12485 11:16:59.016275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12486 11:16:59.016424 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12487 11:16:59.016615 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12488 11:16:59.016782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12489 11:16:59.016928 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12490 11:16:59.017095 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12491 11:16:59.017286 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12492 11:16:59.017440 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12493 11:16:59.017610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12494 11:16:59.018318 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12495 11:16:59.018500 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12496 11:16:59.018706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12497 11:16:59.018866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12498 11:16:59.019031 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12499 11:16:59.019202 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12500 11:16:59.022201 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12501 11:16:59.022407 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12502 11:16:59.022594 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12503 11:16:59.022763 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12504 11:16:59.022931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12505 11:16:59.023106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12506 11:16:59.023281 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12507 11:16:59.023435 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12508 11:16:59.023617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12509 11:16:59.023791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12510 11:16:59.023941 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12511 11:16:59.024095 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12512 11:16:59.024299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12513 11:16:59.024452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12514 11:16:59.024616 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12515 11:16:59.024779 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12516 11:16:59.024927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12517 11:16:59.025126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12518 11:16:59.025293 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12519 11:16:59.025443 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12520 11:16:59.025610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12521 11:16:59.037766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12522 11:16:59.038276 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12523 11:16:59.038386 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12524 11:16:59.038498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12525 11:16:59.038623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12526 11:16:59.038714 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12527 11:16:59.038801 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12528 11:16:59.039103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12529 11:16:59.039209 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12530 11:16:59.039297 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12531 11:16:59.039402 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12532 11:16:59.039495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12533 11:16:59.039605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12534 11:16:59.039712 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12535 11:16:59.039819 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12536 11:16:59.040123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12537 11:16:59.040229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12538 11:16:59.040334 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12539 11:16:59.040438 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12540 11:16:59.040537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12541 11:16:59.040835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12542 11:16:59.040961 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12543 11:16:59.041064 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12544 11:16:59.041353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12545 11:16:59.041453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12546 11:16:59.041565 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12547 11:16:59.041681 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12548 11:16:59.041789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12549 11:16:59.046171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12550 11:16:59.046292 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12551 11:16:59.046392 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12552 11:16:59.046490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12553 11:16:59.046588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12554 11:16:59.046689 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12555 11:16:59.046996 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12556 11:16:59.047107 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12557 11:16:59.047195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12558 11:16:59.047301 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12559 11:16:59.047393 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12560 11:16:59.047502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12561 11:16:59.047595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12562 11:16:59.047699 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12563 11:16:59.047802 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12564 11:16:59.047902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12565 11:16:59.048188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12566 11:16:59.048308 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12567 11:16:59.048410 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12568 11:16:59.048509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12569 11:16:59.048820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12570 11:16:59.048927 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12571 11:16:59.049026 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12572 11:16:59.049112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12573 11:16:59.049209 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12574 11:16:59.049317 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12575 11:16:59.049426 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12576 11:16:59.049535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12577 11:16:59.049843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12578 11:16:59.050002 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12579 11:16:59.053982 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12580 11:16:59.054422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12581 11:16:59.054616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12582 11:16:59.054811 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12583 11:16:59.054990 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12584 11:16:59.055188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12585 11:16:59.055358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12586 11:16:59.055520 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12587 11:16:59.055651 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12588 11:16:59.055828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12589 11:16:59.055991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12590 11:16:59.056145 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12591 11:16:59.056308 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12592 11:16:59.056456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12593 11:16:59.056615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12594 11:16:59.056781 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12595 11:16:59.056951 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12596 11:16:59.057108 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12597 11:16:59.057258 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12598 11:16:59.057444 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12599 11:16:59.057592 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12600 11:16:59.057778 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12601 11:16:59.057902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12602 11:16:59.058023 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12603 11:16:59.058165 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12604 11:16:59.058288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12605 11:16:59.062022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12606 11:16:59.062485 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12607 11:16:59.062753 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12608 11:16:59.062943 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12609 11:16:59.063144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12610 11:16:59.063380 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12611 11:16:59.063604 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12612 11:16:59.063816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12613 11:16:59.063966 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12614 11:16:59.064134 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12615 11:16:59.064311 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12616 11:16:59.064452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12617 11:16:59.064581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12618 11:16:59.064685 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12619 11:16:59.064796 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12620 11:16:59.064916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12621 11:16:59.065031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12622 11:16:59.065177 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12623 11:16:59.065305 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12624 11:16:59.065451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12625 11:16:59.065592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12626 11:16:59.066059 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12627 11:16:59.066153 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12628 11:16:59.066220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12629 11:16:59.066281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12630 11:16:59.066356 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12631 11:16:59.066419 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12632 11:16:59.066479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12633 11:16:59.066538 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12634 11:16:59.069959 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12635 11:16:59.070281 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12636 11:16:59.070403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12637 11:16:59.070529 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12638 11:16:59.070671 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12639 11:16:59.070791 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12640 11:16:59.070901 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12641 11:16:59.070980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12642 11:16:59.071082 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12643 11:16:59.071160 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12644 11:16:59.071254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12645 11:16:59.071529 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12646 11:16:59.071614 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12647 11:16:59.071741 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12648 11:16:59.071849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12649 11:16:59.071960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12650 11:16:59.072258 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12651 11:16:59.072357 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12652 11:16:59.072483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12653 11:16:59.072605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12654 11:16:59.072709 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12655 11:16:59.086110 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12656 11:16:59.086556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12657 11:16:59.086749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12658 11:16:59.086958 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12659 11:16:59.087127 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12660 11:16:59.087340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12661 11:16:59.087503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12662 11:16:59.087657 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12663 11:16:59.087813 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12664 11:16:59.087970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12665 11:16:59.088167 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12666 11:16:59.088365 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12667 11:16:59.088544 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12668 11:16:59.088683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12669 11:16:59.088833 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12670 11:16:59.088991 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12671 11:16:59.089163 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12672 11:16:59.089298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12673 11:16:59.089431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12674 11:16:59.089559 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12675 11:16:59.089715 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12676 11:16:59.089849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12677 11:16:59.089966 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12678 11:16:59.090080 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12679 11:16:59.090220 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12680 11:16:59.090338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12681 11:16:59.090454 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12682 11:16:59.093937 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12683 11:16:59.094387 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12684 11:16:59.094575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12685 11:16:59.094721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12686 11:16:59.094897 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12687 11:16:59.095058 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12688 11:16:59.095198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12689 11:16:59.095349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12690 11:16:59.095526 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12691 11:16:59.095694 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12692 11:16:59.095876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12693 11:16:59.096064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12694 11:16:59.096266 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12695 11:16:59.096444 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12696 11:16:59.096619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12697 11:16:59.096794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12698 11:16:59.096967 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12699 11:16:59.097171 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12700 11:16:59.097348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12701 11:16:59.097526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12702 11:16:59.097719 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12703 11:16:59.097897 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12704 11:16:59.098076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12705 11:16:59.098278 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12706 11:16:59.098450 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12707 11:16:59.098629 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12708 11:16:59.098791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12709 11:16:59.098970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12710 11:16:59.102138 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12711 11:16:59.102355 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12712 11:16:59.102541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12713 11:16:59.102816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12714 11:16:59.103036 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12715 11:16:59.103223 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12716 11:16:59.103414 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12717 11:16:59.103618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12718 11:16:59.103756 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12719 11:16:59.103898 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12720 11:16:59.104019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12721 11:16:59.104175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12722 11:16:59.104365 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12723 11:16:59.104523 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12724 11:16:59.104662 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12725 11:16:59.104799 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12726 11:16:59.104952 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12727 11:16:59.105109 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12728 11:16:59.105265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12729 11:16:59.105417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12730 11:16:59.105537 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12731 11:16:59.105707 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12732 11:16:59.105834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12733 11:16:59.105950 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12734 11:16:59.109950 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12735 11:16:59.110231 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12736 11:16:59.110302 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12737 11:16:59.110376 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12738 11:16:59.110625 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12739 11:16:59.110877 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12740 11:16:59.110948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12741 11:16:59.111024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12742 11:16:59.111288 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12743 11:16:59.111540 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12744 11:16:59.111793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12745 11:16:59.111873 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12746 11:16:59.112122 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12747 11:16:59.112204 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12748 11:16:59.112455 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12749 11:16:59.112534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12750 11:16:59.112785 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12751 11:16:59.112853 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12752 11:16:59.113103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12753 11:16:59.113181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12754 11:16:59.113431 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12755 11:16:59.113509 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12756 11:16:59.113761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12757 11:16:59.117900 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12758 11:16:59.118180 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12759 11:16:59.118276 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12760 11:16:59.118552 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12761 11:16:59.118638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12762 11:16:59.118912 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12763 11:16:59.118990 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12764 11:16:59.119240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12765 11:16:59.119308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12766 11:16:59.119383 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12767 11:16:59.119633 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12768 11:16:59.119710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12769 11:16:59.119959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12770 11:16:59.120313 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12771 11:16:59.120392 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12772 11:16:59.120456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12773 11:16:59.120698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12774 11:16:59.120767 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12775 11:16:59.121009 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12776 11:16:59.121256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12777 11:16:59.121323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12778 11:16:59.121397 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12779 11:16:59.121473 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12780 11:16:59.121553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12781 11:16:59.121797 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12782 11:16:59.125946 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12783 11:16:59.126204 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12784 11:16:59.126274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12785 11:16:59.126523 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12786 11:16:59.126771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12787 11:16:59.126843 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12788 11:16:59.126916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12789 11:16:59.136462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12790 11:16:59.136753 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12791 11:16:59.136851 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12792 11:16:59.137119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12793 11:16:59.137199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12794 11:16:59.137274 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12795 11:16:59.137572 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12796 11:16:59.137750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12797 11:16:59.137916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12798 11:16:59.138089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12799 11:16:59.138260 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12800 11:16:59.138435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12801 11:16:59.138611 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12802 11:16:59.138742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12803 11:16:59.138882 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12804 11:16:59.139028 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12805 11:16:59.139174 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12806 11:16:59.139320 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12807 11:16:59.139463 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12808 11:16:59.139599 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12809 11:16:59.139736 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12810 11:16:59.140090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12811 11:16:59.140264 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12812 11:16:59.140411 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12813 11:16:59.140576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12814 11:16:59.140743 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12815 11:16:59.140914 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12816 11:16:59.141092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12817 11:16:59.141271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12818 11:16:59.141424 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12819 11:16:59.141589 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12820 11:16:59.141745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12821 11:16:59.141904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12822 11:16:59.142024 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12823 11:16:59.146172 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12824 11:16:59.146386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12825 11:16:59.146568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12826 11:16:59.146729 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12827 11:16:59.146910 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12828 11:16:59.147055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12829 11:16:59.147240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12830 11:16:59.147406 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12831 11:16:59.147586 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12832 11:16:59.147718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12833 11:16:59.147840 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12834 11:16:59.147984 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12835 11:16:59.148124 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12836 11:16:59.148282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12837 11:16:59.148472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12838 11:16:59.148637 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12839 11:16:59.148769 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12840 11:16:59.148926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12841 11:16:59.149054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12842 11:16:59.149181 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12843 11:16:59.149338 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12844 11:16:59.149478 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12845 11:16:59.149634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12846 11:16:59.149830 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12847 11:16:59.149954 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12848 11:16:59.150068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12849 11:16:59.150205 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12850 11:16:59.154204 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12851 11:16:59.154387 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12852 11:16:59.154528 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12853 11:16:59.154707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12854 11:16:59.154881 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12855 11:16:59.155048 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12856 11:16:59.155238 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12857 11:16:59.155399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12858 11:16:59.155593 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12859 11:16:59.155760 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12860 11:16:59.155914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12861 11:16:59.156097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12862 11:16:59.156286 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12863 11:16:59.156483 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12864 11:16:59.156705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12865 11:16:59.156875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12866 11:16:59.157034 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12867 11:16:59.157192 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12868 11:16:59.157382 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12869 11:16:59.157571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12870 11:16:59.157810 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12871 11:16:59.157997 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12872 11:16:59.158133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12873 11:16:59.158278 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12874 11:16:59.158398 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12875 11:16:59.158526 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12876 11:16:59.161963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12877 11:16:59.162271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12878 11:16:59.162359 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12879 11:16:59.162474 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12880 11:16:59.162562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12881 11:16:59.162657 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12882 11:16:59.162944 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12883 11:16:59.163038 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12884 11:16:59.163120 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12885 11:16:59.163388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12886 11:16:59.163512 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12887 11:16:59.163617 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12888 11:16:59.163719 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12889 11:16:59.164015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12890 11:16:59.164139 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12891 11:16:59.164229 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12892 11:16:59.164332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12893 11:16:59.164438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12894 11:16:59.164552 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12895 11:16:59.164661 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12896 11:16:59.164957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12897 11:16:59.165066 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12898 11:16:59.165165 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12899 11:16:59.165269 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12900 11:16:59.165590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12901 11:16:59.165694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12902 11:16:59.170005 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12903 11:16:59.170288 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12904 11:16:59.170371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12905 11:16:59.170459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12906 11:16:59.170552 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12907 11:16:59.170639 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12908 11:16:59.170899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12909 11:16:59.171165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12910 11:16:59.171253 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12911 11:16:59.171334 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12912 11:16:59.171613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12913 11:16:59.171707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12914 11:16:59.171787 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12915 11:16:59.172055 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12916 11:16:59.172136 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12917 11:16:59.172232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12918 11:16:59.172566 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12919 11:16:59.172734 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12920 11:16:59.172920 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12921 11:16:59.173056 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12922 11:16:59.173205 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12923 11:16:59.190107 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12924 11:16:59.190344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12925 11:16:59.190730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12926 11:16:59.190820 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12927 11:16:59.190911 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12928 11:16:59.191002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12929 11:16:59.191128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12930 11:16:59.191200 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12931 11:16:59.191289 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12932 11:16:59.191367 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12933 11:16:59.191463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12934 11:16:59.191733 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12935 11:16:59.191857 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12936 11:16:59.191948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12937 11:16:59.192055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12938 11:16:59.192359 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12939 11:16:59.192465 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12940 11:16:59.192570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12941 11:16:59.192659 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12942 11:16:59.192762 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12943 11:16:59.192867 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12944 11:16:59.193172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12945 11:16:59.193258 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12946 11:16:59.193346 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12947 11:16:59.193619 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12948 11:16:59.193713 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12949 11:16:59.197918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12950 11:16:59.198229 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12951 11:16:59.198315 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12952 11:16:59.198400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12953 11:16:59.198485 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12954 11:16:59.198750 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12955 11:16:59.198837 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12956 11:16:59.199089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12957 11:16:59.199353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12958 11:16:59.199618 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12959 11:16:59.199711 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12960 11:16:59.199965 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12961 11:16:59.200036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12962 11:16:59.200129 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12963 11:16:59.200220 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12964 11:16:59.200302 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12965 11:16:59.200556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12966 11:16:59.200801 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12967 11:16:59.200867 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12968 11:16:59.200938 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12969 11:16:59.201190 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12970 11:16:59.201289 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12971 11:16:59.201548 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12972 11:16:59.201633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12973 11:16:59.201752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12974 11:16:59.206117 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12975 11:16:59.206214 arm64_sve-ptrace pass
12976 11:16:59.206318 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12977 11:16:59.206427 arm64_sve-probe-vls_All_vector_lengths_valid pass
12978 11:16:59.206699 arm64_sve-probe-vls pass
12979 11:16:59.206799 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12980 11:16:59.206892 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
12981 11:16:59.206995 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
12982 11:16:59.207096 arm64_vec-syscfg_SVE_current_VL_is_64 pass
12983 11:16:59.207198 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
12984 11:16:59.207298 arm64_vec-syscfg_SVE_prctl_set_min_max pass
12985 11:16:59.207385 arm64_vec-syscfg_SVE_vector_length_used_default pass
12986 11:16:59.207691 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
12987 11:16:59.207866 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
12988 11:16:59.208073 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
12989 11:16:59.208277 arm64_vec-syscfg_SME_default_vector_length_32 pass
12990 11:16:59.208458 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
12991 11:16:59.208647 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
12992 11:16:59.208790 arm64_vec-syscfg_SME_current_VL_is_32 pass
12993 11:16:59.208963 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
12994 11:16:59.209191 arm64_vec-syscfg_SME_prctl_set_min_max pass
12995 11:16:59.209363 arm64_vec-syscfg_SME_vector_length_used_default pass
12996 11:16:59.209561 arm64_vec-syscfg_SME_vector_length_was_inherited pass
12997 11:16:59.209791 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
12998 11:16:59.209963 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
12999 11:16:59.210107 arm64_vec-syscfg pass
13000 11:16:59.210249 arm64_za-fork_fork_test pass
13001 11:16:59.210390 arm64_za-fork pass
13002 11:16:59.210530 arm64_za-ptrace_Set_VL_16 pass
13003 11:16:59.210671 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
13004 11:16:59.210811 arm64_za-ptrace_Data_match_for_VL_16 pass
13005 11:16:59.210952 arm64_za-ptrace_Set_VL_32 pass
13006 11:16:59.211091 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
13007 11:16:59.211264 arm64_za-ptrace_Data_match_for_VL_32 pass
13008 11:16:59.211401 arm64_za-ptrace_Set_VL_48 pass
13009 11:16:59.211543 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
13010 11:16:59.214124 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
13011 11:16:59.214223 arm64_za-ptrace_Set_VL_64 pass
13012 11:16:59.214321 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
13013 11:16:59.214407 arm64_za-ptrace_Data_match_for_VL_64 pass
13014 11:16:59.214501 arm64_za-ptrace_Set_VL_80 pass
13015 11:16:59.214588 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
13016 11:16:59.214665 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
13017 11:16:59.214728 arm64_za-ptrace_Set_VL_96 pass
13018 11:16:59.215033 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
13019 11:16:59.215223 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
13020 11:16:59.215447 arm64_za-ptrace_Set_VL_112 pass
13021 11:16:59.215663 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
13022 11:16:59.215836 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
13023 11:16:59.216077 arm64_za-ptrace_Set_VL_128 pass
13024 11:16:59.216244 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
13025 11:16:59.216379 arm64_za-ptrace_Data_match_for_VL_128 pass
13026 11:16:59.216486 arm64_za-ptrace_Set_VL_144 pass
13027 11:16:59.216609 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
13028 11:16:59.216732 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
13029 11:16:59.216858 arm64_za-ptrace_Set_VL_160 pass
13030 11:16:59.216977 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
13031 11:16:59.217097 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
13032 11:16:59.217218 arm64_za-ptrace_Set_VL_176 pass
13033 11:16:59.217333 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
13034 11:16:59.217483 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
13035 11:16:59.217602 arm64_za-ptrace_Set_VL_192 pass
13036 11:16:59.217754 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
13037 11:16:59.217871 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
13038 11:16:59.217959 arm64_za-ptrace_Set_VL_208 pass
13039 11:16:59.218044 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
13040 11:16:59.218128 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
13041 11:16:59.218212 arm64_za-ptrace_Set_VL_224 pass
13042 11:16:59.218288 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
13043 11:16:59.218348 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
13044 11:16:59.218405 arm64_za-ptrace_Set_VL_240 pass
13045 11:16:59.218462 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
13046 11:16:59.218520 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
13047 11:16:59.218578 arm64_za-ptrace_Set_VL_256 pass
13048 11:16:59.218635 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
13049 11:16:59.218707 arm64_za-ptrace_Data_match_for_VL_256 pass
13050 11:16:59.218768 arm64_za-ptrace_Set_VL_272 pass
13051 11:16:59.222002 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
13052 11:16:59.222521 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
13053 11:16:59.222628 arm64_za-ptrace_Set_VL_288 pass
13054 11:16:59.222719 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
13055 11:16:59.222803 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
13056 11:16:59.222888 arm64_za-ptrace_Set_VL_304 pass
13057 11:16:59.222971 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
13058 11:16:59.223071 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
13059 11:16:59.223157 arm64_za-ptrace_Set_VL_320 pass
13060 11:16:59.223240 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
13061 11:16:59.223337 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
13062 11:16:59.223422 arm64_za-ptrace_Set_VL_336 pass
13063 11:16:59.223520 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
13064 11:16:59.223604 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
13065 11:16:59.223888 arm64_za-ptrace_Set_VL_352 pass
13066 11:16:59.223989 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
13067 11:16:59.224072 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
13068 11:16:59.224168 arm64_za-ptrace_Set_VL_368 pass
13069 11:16:59.224251 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
13070 11:16:59.224347 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
13071 11:16:59.224429 arm64_za-ptrace_Set_VL_384 pass
13072 11:16:59.224523 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
13073 11:16:59.224816 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
13074 11:16:59.224916 arm64_za-ptrace_Set_VL_400 pass
13075 11:16:59.225015 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
13076 11:16:59.225113 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
13077 11:16:59.225216 arm64_za-ptrace_Set_VL_416 pass
13078 11:16:59.225311 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
13079 11:16:59.225538 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
13080 11:16:59.225661 arm64_za-ptrace_Set_VL_432 pass
13081 11:16:59.225763 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
13082 11:16:59.229897 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
13083 11:16:59.230274 arm64_za-ptrace_Set_VL_448 pass
13084 11:16:59.230473 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
13085 11:16:59.230658 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
13086 11:16:59.230879 arm64_za-ptrace_Set_VL_464 pass
13087 11:16:59.231085 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
13088 11:16:59.231272 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
13089 11:16:59.231402 arm64_za-ptrace_Set_VL_480 pass
13090 11:16:59.231522 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
13091 11:16:59.231673 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
13092 11:16:59.231791 arm64_za-ptrace_Set_VL_496 pass
13093 11:16:59.231903 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
13094 11:16:59.245248 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
13095 11:16:59.245447 arm64_za-ptrace_Set_VL_512 pass
13096 11:16:59.245830 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
13097 11:16:59.246034 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
13098 11:16:59.246211 arm64_za-ptrace_Set_VL_528 pass
13099 11:16:59.246352 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
13100 11:16:59.246544 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
13101 11:16:59.246699 arm64_za-ptrace_Set_VL_544 pass
13102 11:16:59.246846 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
13103 11:16:59.247009 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
13104 11:16:59.247148 arm64_za-ptrace_Set_VL_560 pass
13105 11:16:59.247305 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
13106 11:16:59.247490 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
13107 11:16:59.247643 arm64_za-ptrace_Set_VL_576 pass
13108 11:16:59.247803 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
13109 11:16:59.247940 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
13110 11:16:59.248102 arm64_za-ptrace_Set_VL_592 pass
13111 11:16:59.248250 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
13112 11:16:59.248394 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
13113 11:16:59.248556 arm64_za-ptrace_Set_VL_608 pass
13114 11:16:59.248731 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
13115 11:16:59.248900 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
13116 11:16:59.249044 arm64_za-ptrace_Set_VL_624 pass
13117 11:16:59.249195 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
13118 11:16:59.249354 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
13119 11:16:59.249493 arm64_za-ptrace_Set_VL_640 pass
13120 11:16:59.249669 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
13121 11:16:59.249819 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
13122 11:16:59.249967 arm64_za-ptrace_Set_VL_656 pass
13123 11:16:59.250133 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
13124 11:16:59.250276 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
13125 11:16:59.250441 arm64_za-ptrace_Set_VL_672 pass
13126 11:16:59.250588 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
13127 11:16:59.250775 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
13128 11:16:59.250936 arm64_za-ptrace_Set_VL_688 pass
13129 11:16:59.251080 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
13130 11:16:59.251251 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
13131 11:16:59.251394 arm64_za-ptrace_Set_VL_704 pass
13132 11:16:59.251554 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
13133 11:16:59.251707 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
13134 11:16:59.251850 arm64_za-ptrace_Set_VL_720 pass
13135 11:16:59.252012 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
13136 11:16:59.252151 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
13137 11:16:59.253928 arm64_za-ptrace_Set_VL_736 pass
13138 11:16:59.254336 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
13139 11:16:59.254531 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
13140 11:16:59.254729 arm64_za-ptrace_Set_VL_752 pass
13141 11:16:59.254895 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
13142 11:16:59.255093 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
13143 11:16:59.255281 arm64_za-ptrace_Set_VL_768 pass
13144 11:16:59.255502 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
13145 11:16:59.255713 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
13146 11:16:59.255933 arm64_za-ptrace_Set_VL_784 pass
13147 11:16:59.256135 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
13148 11:16:59.256308 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
13149 11:16:59.256540 arm64_za-ptrace_Set_VL_800 pass
13150 11:16:59.256753 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
13151 11:16:59.256946 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
13152 11:16:59.257129 arm64_za-ptrace_Set_VL_816 pass
13153 11:16:59.257291 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
13154 11:16:59.257467 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
13155 11:16:59.257915 arm64_za-ptrace_Set_VL_832 pass
13156 11:16:59.258065 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
13157 11:16:59.258183 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
13158 11:16:59.258301 arm64_za-ptrace_Set_VL_848 pass
13159 11:16:59.258415 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
13160 11:16:59.258529 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
13161 11:16:59.258642 arm64_za-ptrace_Set_VL_864 pass
13162 11:16:59.258755 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
13163 11:16:59.258897 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
13164 11:16:59.259020 arm64_za-ptrace_Set_VL_880 pass
13165 11:16:59.259134 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
13166 11:16:59.259250 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
13167 11:16:59.259362 arm64_za-ptrace_Set_VL_896 pass
13168 11:16:59.259476 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
13169 11:16:59.259588 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
13170 11:16:59.259701 arm64_za-ptrace_Set_VL_912 pass
13171 11:16:59.259813 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
13172 11:16:59.259926 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
13173 11:16:59.261911 arm64_za-ptrace_Set_VL_928 pass
13174 11:16:59.262320 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
13175 11:16:59.262424 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
13176 11:16:59.262511 arm64_za-ptrace_Set_VL_944 pass
13177 11:16:59.262594 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
13178 11:16:59.262691 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
13179 11:16:59.262775 arm64_za-ptrace_Set_VL_960 pass
13180 11:16:59.262858 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
13181 11:16:59.262954 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
13182 11:16:59.263038 arm64_za-ptrace_Set_VL_976 pass
13183 11:16:59.263134 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
13184 11:16:59.263218 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
13185 11:16:59.263314 arm64_za-ptrace_Set_VL_992 pass
13186 11:16:59.263411 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
13187 11:16:59.263763 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
13188 11:16:59.263864 arm64_za-ptrace_Set_VL_1008 pass
13189 11:16:59.264142 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
13190 11:16:59.264232 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
13191 11:16:59.264318 arm64_za-ptrace_Set_VL_1024 pass
13192 11:16:59.264401 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
13193 11:16:59.264499 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
13194 11:16:59.264584 arm64_za-ptrace_Set_VL_1040 pass
13195 11:16:59.264681 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
13196 11:16:59.264764 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
13197 11:16:59.264845 arm64_za-ptrace_Set_VL_1056 pass
13198 11:16:59.264941 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
13199 11:16:59.265025 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
13200 11:16:59.265120 arm64_za-ptrace_Set_VL_1072 pass
13201 11:16:59.265218 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
13202 11:16:59.265322 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
13203 11:16:59.265665 arm64_za-ptrace_Set_VL_1088 pass
13204 11:16:59.265839 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
13205 11:16:59.269942 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
13206 11:16:59.270348 arm64_za-ptrace_Set_VL_1104 pass
13207 11:16:59.270520 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
13208 11:16:59.270703 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
13209 11:16:59.270857 arm64_za-ptrace_Set_VL_1120 pass
13210 11:16:59.271013 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
13211 11:16:59.271143 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
13212 11:16:59.271271 arm64_za-ptrace_Set_VL_1136 pass
13213 11:16:59.271396 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
13214 11:16:59.271522 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
13215 11:16:59.271693 arm64_za-ptrace_Set_VL_1152 pass
13216 11:16:59.271862 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
13217 11:16:59.272040 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
13218 11:16:59.272302 arm64_za-ptrace_Set_VL_1168 pass
13219 11:16:59.272491 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
13220 11:16:59.272698 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
13221 11:16:59.272923 arm64_za-ptrace_Set_VL_1184 pass
13222 11:16:59.273147 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
13223 11:16:59.273338 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
13224 11:16:59.273539 arm64_za-ptrace_Set_VL_1200 pass
13225 11:16:59.273749 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13226 11:16:59.273915 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13227 11:16:59.274039 arm64_za-ptrace_Set_VL_1216 pass
13228 11:16:59.274152 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13229 11:16:59.274266 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13230 11:16:59.274408 arm64_za-ptrace_Set_VL_1232 pass
13231 11:16:59.274527 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13232 11:16:59.274639 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13233 11:16:59.274752 arm64_za-ptrace_Set_VL_1248 pass
13234 11:16:59.274862 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13235 11:16:59.274973 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13236 11:16:59.275083 arm64_za-ptrace_Set_VL_1264 pass
13237 11:16:59.275195 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13238 11:16:59.275310 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13239 11:16:59.275422 arm64_za-ptrace_Set_VL_1280 pass
13240 11:16:59.275533 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13241 11:16:59.275644 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13242 11:16:59.275756 arm64_za-ptrace_Set_VL_1296 pass
13243 11:16:59.277934 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13244 11:16:59.278354 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13245 11:16:59.278514 arm64_za-ptrace_Set_VL_1312 pass
13246 11:16:59.278660 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13247 11:16:59.278819 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13248 11:16:59.278938 arm64_za-ptrace_Set_VL_1328 pass
13249 11:16:59.279075 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13250 11:16:59.279194 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13251 11:16:59.279293 arm64_za-ptrace_Set_VL_1344 pass
13252 11:16:59.279374 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13253 11:16:59.279458 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13254 11:16:59.279544 arm64_za-ptrace_Set_VL_1360 pass
13255 11:16:59.279638 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13256 11:16:59.279719 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13257 11:16:59.279791 arm64_za-ptrace_Set_VL_1376 pass
13258 11:16:59.279867 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13259 11:16:59.279956 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13260 11:16:59.280050 arm64_za-ptrace_Set_VL_1392 pass
13261 11:16:59.280158 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13262 11:16:59.280283 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13263 11:16:59.280374 arm64_za-ptrace_Set_VL_1408 pass
13264 11:16:59.280461 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13265 11:16:59.280545 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13266 11:16:59.280639 arm64_za-ptrace_Set_VL_1424 pass
13267 11:16:59.280718 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13268 11:16:59.280786 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13269 11:16:59.280881 arm64_za-ptrace_Set_VL_1440 pass
13270 11:16:59.280981 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13271 11:16:59.281088 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13272 11:16:59.281179 arm64_za-ptrace_Set_VL_1456 pass
13273 11:16:59.281271 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13274 11:16:59.281370 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13275 11:16:59.281450 arm64_za-ptrace_Set_VL_1472 pass
13276 11:16:59.281544 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13277 11:16:59.282014 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13278 11:16:59.282093 arm64_za-ptrace_Set_VL_1488 pass
13279 11:16:59.285940 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13280 11:16:59.286319 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13281 11:16:59.286446 arm64_za-ptrace_Set_VL_1504 pass
13282 11:16:59.286583 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13283 11:16:59.286712 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13284 11:16:59.286847 arm64_za-ptrace_Set_VL_1520 pass
13285 11:16:59.286949 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13286 11:16:59.287075 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13287 11:16:59.287188 arm64_za-ptrace_Set_VL_1536 pass
13288 11:16:59.287278 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13289 11:16:59.300254 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13290 11:16:59.300460 arm64_za-ptrace_Set_VL_1552 pass
13291 11:16:59.300870 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13292 11:16:59.301056 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13293 11:16:59.301236 arm64_za-ptrace_Set_VL_1568 pass
13294 11:16:59.301434 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13295 11:16:59.301630 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13296 11:16:59.301822 arm64_za-ptrace_Set_VL_1584 pass
13297 11:16:59.301956 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13298 11:16:59.302086 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13299 11:16:59.302212 arm64_za-ptrace_Set_VL_1600 pass
13300 11:16:59.302333 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13301 11:16:59.302457 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13302 11:16:59.302582 arm64_za-ptrace_Set_VL_1616 pass
13303 11:16:59.302709 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13304 11:16:59.302836 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13305 11:16:59.302962 arm64_za-ptrace_Set_VL_1632 pass
13306 11:16:59.303116 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13307 11:16:59.303251 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13308 11:16:59.303379 arm64_za-ptrace_Set_VL_1648 pass
13309 11:16:59.303504 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13310 11:16:59.303629 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13311 11:16:59.303754 arm64_za-ptrace_Set_VL_1664 pass
13312 11:16:59.303878 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13313 11:16:59.304002 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13314 11:16:59.304151 arm64_za-ptrace_Set_VL_1680 pass
13315 11:16:59.304361 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13316 11:16:59.304559 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13317 11:16:59.304737 arm64_za-ptrace_Set_VL_1696 pass
13318 11:16:59.304907 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13319 11:16:59.305081 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13320 11:16:59.305273 arm64_za-ptrace_Set_VL_1712 pass
13321 11:16:59.305532 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13322 11:16:59.305759 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13323 11:16:59.305958 arm64_za-ptrace_Set_VL_1728 pass
13324 11:16:59.306103 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13325 11:16:59.306222 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13326 11:16:59.306339 arm64_za-ptrace_Set_VL_1744 pass
13327 11:16:59.306454 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13328 11:16:59.306568 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13329 11:16:59.306681 arm64_za-ptrace_Set_VL_1760 pass
13330 11:16:59.306795 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13331 11:16:59.306911 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13332 11:16:59.307025 arm64_za-ptrace_Set_VL_1776 pass
13333 11:16:59.307138 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13334 11:16:59.307252 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13335 11:16:59.307369 arm64_za-ptrace_Set_VL_1792 pass
13336 11:16:59.307695 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13337 11:16:59.307823 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13338 11:16:59.307939 arm64_za-ptrace_Set_VL_1808 pass
13339 11:16:59.308054 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13340 11:16:59.308169 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13341 11:16:59.308286 arm64_za-ptrace_Set_VL_1824 pass
13342 11:16:59.308403 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13343 11:16:59.308519 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13344 11:16:59.308632 arm64_za-ptrace_Set_VL_1840 pass
13345 11:16:59.308747 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13346 11:16:59.308860 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13347 11:16:59.308975 arm64_za-ptrace_Set_VL_1856 pass
13348 11:16:59.310011 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13349 11:16:59.310355 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13350 11:16:59.310446 arm64_za-ptrace_Set_VL_1872 pass
13351 11:16:59.310530 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13352 11:16:59.310628 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13353 11:16:59.310713 arm64_za-ptrace_Set_VL_1888 pass
13354 11:16:59.310993 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13355 11:16:59.311081 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13356 11:16:59.311166 arm64_za-ptrace_Set_VL_1904 pass
13357 11:16:59.311263 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13358 11:16:59.311347 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13359 11:16:59.311444 arm64_za-ptrace_Set_VL_1920 pass
13360 11:16:59.311530 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13361 11:16:59.311626 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13362 11:16:59.311710 arm64_za-ptrace_Set_VL_1936 pass
13363 11:16:59.311806 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13364 11:16:59.311904 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13365 11:16:59.311999 arm64_za-ptrace_Set_VL_1952 pass
13366 11:16:59.312095 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13367 11:16:59.312395 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13368 11:16:59.312495 arm64_za-ptrace_Set_VL_1968 pass
13369 11:16:59.312593 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13370 11:16:59.312690 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13371 11:16:59.312775 arm64_za-ptrace_Set_VL_1984 pass
13372 11:16:59.312871 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13373 11:16:59.312970 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13374 11:16:59.313067 arm64_za-ptrace_Set_VL_2000 pass
13375 11:16:59.313352 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13376 11:16:59.313448 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13377 11:16:59.313531 arm64_za-ptrace_Set_VL_2016 pass
13378 11:16:59.313630 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13379 11:16:59.313735 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13380 11:16:59.313835 arm64_za-ptrace_Set_VL_2032 pass
13381 11:16:59.317969 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13382 11:16:59.318322 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13383 11:16:59.318424 arm64_za-ptrace_Set_VL_2048 pass
13384 11:16:59.318514 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13385 11:16:59.318613 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13386 11:16:59.318697 arm64_za-ptrace_Set_VL_2064 pass
13387 11:16:59.318795 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13388 11:16:59.318881 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13389 11:16:59.319107 arm64_za-ptrace_Set_VL_2080 pass
13390 11:16:59.319206 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13391 11:16:59.319306 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13392 11:16:59.319399 arm64_za-ptrace_Set_VL_2096 pass
13393 11:16:59.319494 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13394 11:16:59.319592 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13395 11:16:59.319688 arm64_za-ptrace_Set_VL_2112 pass
13396 11:16:59.319979 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13397 11:16:59.320078 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13398 11:16:59.320178 arm64_za-ptrace_Set_VL_2128 pass
13399 11:16:59.320273 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13400 11:16:59.320370 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13401 11:16:59.320465 arm64_za-ptrace_Set_VL_2144 pass
13402 11:16:59.320800 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13403 11:16:59.321005 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13404 11:16:59.321201 arm64_za-ptrace_Set_VL_2160 pass
13405 11:16:59.321386 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13406 11:16:59.321566 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13407 11:16:59.321735 arm64_za-ptrace_Set_VL_2176 pass
13408 11:16:59.321905 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13409 11:16:59.322030 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13410 11:16:59.322145 arm64_za-ptrace_Set_VL_2192 pass
13411 11:16:59.322258 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13412 11:16:59.326044 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13413 11:16:59.326263 arm64_za-ptrace_Set_VL_2208 pass
13414 11:16:59.326503 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13415 11:16:59.326919 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13416 11:16:59.327084 arm64_za-ptrace_Set_VL_2224 pass
13417 11:16:59.327259 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13418 11:16:59.327461 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13419 11:16:59.327651 arm64_za-ptrace_Set_VL_2240 pass
13420 11:16:59.327843 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13421 11:16:59.328046 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13422 11:16:59.328244 arm64_za-ptrace_Set_VL_2256 pass
13423 11:16:59.328412 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13424 11:16:59.328588 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13425 11:16:59.328751 arm64_za-ptrace_Set_VL_2272 pass
13426 11:16:59.328900 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13427 11:16:59.329050 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13428 11:16:59.329196 arm64_za-ptrace_Set_VL_2288 pass
13429 11:16:59.329350 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13430 11:16:59.329524 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13431 11:16:59.329711 arm64_za-ptrace_Set_VL_2304 pass
13432 11:16:59.329913 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13433 11:16:59.330066 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13434 11:16:59.330207 arm64_za-ptrace_Set_VL_2320 pass
13435 11:16:59.330349 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13436 11:16:59.330491 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13437 11:16:59.330632 arm64_za-ptrace_Set_VL_2336 pass
13438 11:16:59.330772 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13439 11:16:59.330950 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13440 11:16:59.331086 arm64_za-ptrace_Set_VL_2352 pass
13441 11:16:59.331227 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13442 11:16:59.331370 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13443 11:16:59.331512 arm64_za-ptrace_Set_VL_2368 pass
13444 11:16:59.331652 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13445 11:16:59.331792 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13446 11:16:59.331934 arm64_za-ptrace_Set_VL_2384 pass
13447 11:16:59.332075 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13448 11:16:59.332216 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13449 11:16:59.332356 arm64_za-ptrace_Set_VL_2400 pass
13450 11:16:59.333933 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13451 11:16:59.334424 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13452 11:16:59.334643 arm64_za-ptrace_Set_VL_2416 pass
13453 11:16:59.334820 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13454 11:16:59.334979 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13455 11:16:59.335165 arm64_za-ptrace_Set_VL_2432 pass
13456 11:16:59.335418 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13457 11:16:59.335589 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13458 11:16:59.335767 arm64_za-ptrace_Set_VL_2448 pass
13459 11:16:59.335930 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13460 11:16:59.336094 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13461 11:16:59.336249 arm64_za-ptrace_Set_VL_2464 pass
13462 11:16:59.336397 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13463 11:16:59.336532 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13464 11:16:59.336629 arm64_za-ptrace_Set_VL_2480 pass
13465 11:16:59.336753 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13466 11:16:59.336890 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13467 11:16:59.337003 arm64_za-ptrace_Set_VL_2496 pass
13468 11:16:59.337091 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13469 11:16:59.337175 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13470 11:16:59.337262 arm64_za-ptrace_Set_VL_2512 pass
13471 11:16:59.337350 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13472 11:16:59.337439 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13473 11:16:59.337524 arm64_za-ptrace_Set_VL_2528 pass
13474 11:16:59.337609 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13475 11:16:59.337779 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13476 11:16:59.337924 arm64_za-ptrace_Set_VL_2544 pass
13477 11:16:59.338060 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13478 11:16:59.338196 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13479 11:16:59.338364 arm64_za-ptrace_Set_VL_2560 pass
13480 11:16:59.338451 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13481 11:16:59.338524 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13482 11:16:59.356641 arm64_za-ptrace_Set_VL_2576 pass
13483 11:16:59.357105 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13484 11:16:59.357304 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13485 11:16:59.357624 arm64_za-ptrace_Set_VL_2592 pass
13486 11:16:59.357822 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13487 11:16:59.358003 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13488 11:16:59.358179 arm64_za-ptrace_Set_VL_2608 pass
13489 11:16:59.358329 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13490 11:16:59.358494 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13491 11:16:59.358650 arm64_za-ptrace_Set_VL_2624 pass
13492 11:16:59.358797 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13493 11:16:59.358962 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13494 11:16:59.359102 arm64_za-ptrace_Set_VL_2640 pass
13495 11:16:59.359296 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13496 11:16:59.359448 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13497 11:16:59.359597 arm64_za-ptrace_Set_VL_2656 pass
13498 11:16:59.359759 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13499 11:16:59.359898 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13500 11:16:59.360059 arm64_za-ptrace_Set_VL_2672 pass
13501 11:16:59.360208 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13502 11:16:59.360351 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13503 11:16:59.360518 arm64_za-ptrace_Set_VL_2688 pass
13504 11:16:59.360657 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13505 11:16:59.360813 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13506 11:16:59.360965 arm64_za-ptrace_Set_VL_2704 pass
13507 11:16:59.361105 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13508 11:16:59.361269 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13509 11:16:59.361412 arm64_za-ptrace_Set_VL_2720 pass
13510 11:16:59.361623 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13511 11:16:59.362352 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13512 11:16:59.362525 arm64_za-ptrace_Set_VL_2736 pass
13513 11:16:59.362670 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13514 11:16:59.362838 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13515 11:16:59.362985 arm64_za-ptrace_Set_VL_2752 pass
13516 11:16:59.363138 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13517 11:16:59.363298 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13518 11:16:59.363442 arm64_za-ptrace_Set_VL_2768 pass
13519 11:16:59.363609 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13520 11:16:59.363754 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13521 11:16:59.363911 arm64_za-ptrace_Set_VL_2784 pass
13522 11:16:59.364069 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13523 11:16:59.364213 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13524 11:16:59.364380 arm64_za-ptrace_Set_VL_2800 pass
13525 11:16:59.364524 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13526 11:16:59.364679 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13527 11:16:59.365075 arm64_za-ptrace_Set_VL_2816 pass
13528 11:16:59.365242 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13529 11:16:59.365412 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13530 11:16:59.365565 arm64_za-ptrace_Set_VL_2832 pass
13531 11:16:59.365729 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13532 11:16:59.365895 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13533 11:16:59.366069 arm64_za-ptrace_Set_VL_2848 pass
13534 11:16:59.366242 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13535 11:16:59.366414 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13536 11:16:59.366585 arm64_za-ptrace_Set_VL_2864 pass
13537 11:16:59.366736 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13538 11:16:59.366919 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13539 11:16:59.367084 arm64_za-ptrace_Set_VL_2880 pass
13540 11:16:59.367230 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13541 11:16:59.367402 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13542 11:16:59.367548 arm64_za-ptrace_Set_VL_2896 pass
13543 11:16:59.367739 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13544 11:16:59.367892 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13545 11:16:59.368041 arm64_za-ptrace_Set_VL_2912 pass
13546 11:16:59.368201 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13547 11:16:59.368340 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13548 11:16:59.368505 arm64_za-ptrace_Set_VL_2928 pass
13549 11:16:59.368652 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13550 11:16:59.368833 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13551 11:16:59.368996 arm64_za-ptrace_Set_VL_2944 pass
13552 11:16:59.369136 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13553 11:16:59.369299 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13554 11:16:59.369444 arm64_za-ptrace_Set_VL_2960 pass
13555 11:16:59.369593 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13556 11:16:59.370214 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13557 11:16:59.370378 arm64_za-ptrace_Set_VL_2976 pass
13558 11:16:59.370549 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13559 11:16:59.370691 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13560 11:16:59.370856 arm64_za-ptrace_Set_VL_2992 pass
13561 11:16:59.371008 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13562 11:16:59.371153 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13563 11:16:59.371355 arm64_za-ptrace_Set_VL_3008 pass
13564 11:16:59.371507 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13565 11:16:59.371677 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13566 11:16:59.371824 arm64_za-ptrace_Set_VL_3024 pass
13567 11:16:59.371980 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13568 11:16:59.372139 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13569 11:16:59.372283 arm64_za-ptrace_Set_VL_3040 pass
13570 11:16:59.372454 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13571 11:16:59.372600 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13572 11:16:59.374187 arm64_za-ptrace_Set_VL_3056 pass
13573 11:16:59.374287 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13574 11:16:59.374392 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13575 11:16:59.374475 arm64_za-ptrace_Set_VL_3072 pass
13576 11:16:59.374573 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13577 11:16:59.374654 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13578 11:16:59.374760 arm64_za-ptrace_Set_VL_3088 pass
13579 11:16:59.374854 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13580 11:16:59.374955 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13581 11:16:59.375043 arm64_za-ptrace_Set_VL_3104 pass
13582 11:16:59.375145 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13583 11:16:59.375233 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13584 11:16:59.375338 arm64_za-ptrace_Set_VL_3120 pass
13585 11:16:59.375418 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13586 11:16:59.375529 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13587 11:16:59.375623 arm64_za-ptrace_Set_VL_3136 pass
13588 11:16:59.375978 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13589 11:16:59.376083 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13590 11:16:59.376168 arm64_za-ptrace_Set_VL_3152 pass
13591 11:16:59.376250 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13592 11:16:59.376367 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13593 11:16:59.376460 arm64_za-ptrace_Set_VL_3168 pass
13594 11:16:59.376543 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13595 11:16:59.376622 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13596 11:16:59.376712 arm64_za-ptrace_Set_VL_3184 pass
13597 11:16:59.376778 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13598 11:16:59.376841 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13599 11:16:59.376912 arm64_za-ptrace_Set_VL_3200 pass
13600 11:16:59.376975 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13601 11:16:59.377045 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13602 11:16:59.377107 arm64_za-ptrace_Set_VL_3216 pass
13603 11:16:59.377176 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13604 11:16:59.377462 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13605 11:16:59.377617 arm64_za-ptrace_Set_VL_3232 pass
13606 11:16:59.377753 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13607 11:16:59.377927 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13608 11:16:59.378106 arm64_za-ptrace_Set_VL_3248 pass
13609 11:16:59.378242 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13610 11:16:59.378384 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13611 11:16:59.378528 arm64_za-ptrace_Set_VL_3264 pass
13612 11:16:59.378668 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13613 11:16:59.382170 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13614 11:16:59.382335 arm64_za-ptrace_Set_VL_3280 pass
13615 11:16:59.382547 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13616 11:16:59.382777 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13617 11:16:59.382942 arm64_za-ptrace_Set_VL_3296 pass
13618 11:16:59.383091 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13619 11:16:59.383237 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13620 11:16:59.383371 arm64_za-ptrace_Set_VL_3312 pass
13621 11:16:59.383533 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13622 11:16:59.383671 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13623 11:16:59.383815 arm64_za-ptrace_Set_VL_3328 pass
13624 11:16:59.383935 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13625 11:16:59.384053 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13626 11:16:59.384179 arm64_za-ptrace_Set_VL_3344 pass
13627 11:16:59.384300 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13628 11:16:59.384419 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13629 11:16:59.384601 arm64_za-ptrace_Set_VL_3360 pass
13630 11:16:59.384762 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13631 11:16:59.384904 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13632 11:16:59.385057 arm64_za-ptrace_Set_VL_3376 pass
13633 11:16:59.385206 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13634 11:16:59.385349 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13635 11:16:59.385496 arm64_za-ptrace_Set_VL_3392 pass
13636 11:16:59.385635 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13637 11:16:59.385831 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13638 11:16:59.385967 arm64_za-ptrace_Set_VL_3408 pass
13639 11:16:59.386081 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13640 11:16:59.386196 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13641 11:16:59.386342 arm64_za-ptrace_Set_VL_3424 pass
13642 11:16:59.386464 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13643 11:16:59.386581 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13644 11:16:59.386695 arm64_za-ptrace_Set_VL_3440 pass
13645 11:16:59.386810 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13646 11:16:59.386923 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13647 11:16:59.387038 arm64_za-ptrace_Set_VL_3456 pass
13648 11:16:59.387151 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13649 11:16:59.387264 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13650 11:16:59.387377 arm64_za-ptrace_Set_VL_3472 pass
13651 11:16:59.387494 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13652 11:16:59.387606 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13653 11:16:59.387719 arm64_za-ptrace_Set_VL_3488 pass
13654 11:16:59.387832 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13655 11:16:59.389966 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13656 11:16:59.390403 arm64_za-ptrace_Set_VL_3504 pass
13657 11:16:59.390558 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13658 11:16:59.390774 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13659 11:16:59.390994 arm64_za-ptrace_Set_VL_3520 pass
13660 11:16:59.391212 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13661 11:16:59.391455 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13662 11:16:59.391648 arm64_za-ptrace_Set_VL_3536 pass
13663 11:16:59.391782 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13664 11:16:59.391897 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13665 11:16:59.392011 arm64_za-ptrace_Set_VL_3552 pass
13666 11:16:59.392159 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13667 11:16:59.392280 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13668 11:16:59.392393 arm64_za-ptrace_Set_VL_3568 pass
13669 11:16:59.392503 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13670 11:16:59.392613 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13671 11:16:59.392724 arm64_za-ptrace_Set_VL_3584 pass
13672 11:16:59.392835 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13673 11:16:59.392945 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13674 11:16:59.409675 arm64_za-ptrace_Set_VL_3600 pass
13675 11:16:59.409895 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13676 11:16:59.410075 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13677 11:16:59.410426 arm64_za-ptrace_Set_VL_3616 pass
13678 11:16:59.410506 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13679 11:16:59.410579 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13680 11:16:59.410668 arm64_za-ptrace_Set_VL_3632 pass
13681 11:16:59.410749 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13682 11:16:59.410836 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13683 11:16:59.410924 arm64_za-ptrace_Set_VL_3648 pass
13684 11:16:59.411001 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13685 11:16:59.411093 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13686 11:16:59.411184 arm64_za-ptrace_Set_VL_3664 pass
13687 11:16:59.411296 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13688 11:16:59.411372 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13689 11:16:59.411436 arm64_za-ptrace_Set_VL_3680 pass
13690 11:16:59.411534 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13691 11:16:59.411638 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13692 11:16:59.411723 arm64_za-ptrace_Set_VL_3696 pass
13693 11:16:59.411820 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13694 11:16:59.411903 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13695 11:16:59.411992 arm64_za-ptrace_Set_VL_3712 pass
13696 11:16:59.412089 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13697 11:16:59.412170 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13698 11:16:59.412233 arm64_za-ptrace_Set_VL_3728 pass
13699 11:16:59.412292 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13700 11:16:59.412381 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13701 11:16:59.412447 arm64_za-ptrace_Set_VL_3744 pass
13702 11:16:59.412508 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13703 11:16:59.412581 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13704 11:16:59.412641 arm64_za-ptrace_Set_VL_3760 pass
13705 11:16:59.412698 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13706 11:16:59.412756 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13707 11:16:59.412825 arm64_za-ptrace_Set_VL_3776 pass
13708 11:16:59.412886 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13709 11:16:59.412974 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13710 11:16:59.413040 arm64_za-ptrace_Set_VL_3792 pass
13711 11:16:59.413098 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13712 11:16:59.413165 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13713 11:16:59.413233 arm64_za-ptrace_Set_VL_3808 pass
13714 11:16:59.413301 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13715 11:16:59.413400 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13716 11:16:59.413516 arm64_za-ptrace_Set_VL_3824 pass
13717 11:16:59.413618 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13718 11:16:59.413746 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13719 11:16:59.413859 arm64_za-ptrace_Set_VL_3840 pass
13720 11:16:59.413970 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13721 11:16:59.417946 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13722 11:16:59.418251 arm64_za-ptrace_Set_VL_3856 pass
13723 11:16:59.418351 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13724 11:16:59.418435 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13725 11:16:59.418536 arm64_za-ptrace_Set_VL_3872 pass
13726 11:16:59.418621 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13727 11:16:59.418719 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13728 11:16:59.418805 arm64_za-ptrace_Set_VL_3888 pass
13729 11:16:59.418902 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13730 11:16:59.419197 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13731 11:16:59.419296 arm64_za-ptrace_Set_VL_3904 pass
13732 11:16:59.419379 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13733 11:16:59.419679 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13734 11:16:59.419778 arm64_za-ptrace_Set_VL_3920 pass
13735 11:16:59.419862 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13736 11:16:59.419943 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13737 11:16:59.420040 arm64_za-ptrace_Set_VL_3936 pass
13738 11:16:59.420124 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13739 11:16:59.420222 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13740 11:16:59.420307 arm64_za-ptrace_Set_VL_3952 pass
13741 11:16:59.420647 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13742 11:16:59.420860 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13743 11:16:59.421101 arm64_za-ptrace_Set_VL_3968 pass
13744 11:16:59.421348 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13745 11:16:59.421563 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13746 11:16:59.421788 arm64_za-ptrace_Set_VL_3984 pass
13747 11:16:59.421972 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13748 11:16:59.422132 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13749 11:16:59.422253 arm64_za-ptrace_Set_VL_4000 pass
13750 11:16:59.422368 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13751 11:16:59.422482 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13752 11:16:59.422594 arm64_za-ptrace_Set_VL_4016 pass
13753 11:16:59.422706 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13754 11:16:59.425969 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13755 11:16:59.426446 arm64_za-ptrace_Set_VL_4032 pass
13756 11:16:59.426644 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13757 11:16:59.426823 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13758 11:16:59.427013 arm64_za-ptrace_Set_VL_4048 pass
13759 11:16:59.427214 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13760 11:16:59.427382 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13761 11:16:59.427538 arm64_za-ptrace_Set_VL_4064 pass
13762 11:16:59.427687 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13763 11:16:59.427839 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13764 11:16:59.427997 arm64_za-ptrace_Set_VL_4080 pass
13765 11:16:59.428181 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13766 11:16:59.428333 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13767 11:16:59.428473 arm64_za-ptrace_Set_VL_4096 pass
13768 11:16:59.428673 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13769 11:16:59.428910 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13770 11:16:59.429109 arm64_za-ptrace_Set_VL_4112 pass
13771 11:16:59.429280 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13772 11:16:59.429444 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13773 11:16:59.429641 arm64_za-ptrace_Set_VL_4128 pass
13774 11:16:59.429833 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13775 11:16:59.429987 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13776 11:16:59.430104 arm64_za-ptrace_Set_VL_4144 pass
13777 11:16:59.430217 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13778 11:16:59.430329 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13779 11:16:59.430438 arm64_za-ptrace_Set_VL_4160 pass
13780 11:16:59.430548 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13781 11:16:59.430657 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13782 11:16:59.430766 arm64_za-ptrace_Set_VL_4176 pass
13783 11:16:59.430875 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13784 11:16:59.431009 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13785 11:16:59.433969 arm64_za-ptrace_Set_VL_4192 pass
13786 11:16:59.434406 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13787 11:16:59.434604 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13788 11:16:59.434799 arm64_za-ptrace_Set_VL_4208 pass
13789 11:16:59.434989 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13790 11:16:59.435257 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13791 11:16:59.435484 arm64_za-ptrace_Set_VL_4224 pass
13792 11:16:59.435677 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13793 11:16:59.435846 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13794 11:16:59.436010 arm64_za-ptrace_Set_VL_4240 pass
13795 11:16:59.436173 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13796 11:16:59.436342 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13797 11:16:59.436573 arm64_za-ptrace_Set_VL_4256 pass
13798 11:16:59.436772 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13799 11:16:59.436989 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13800 11:16:59.437195 arm64_za-ptrace_Set_VL_4272 pass
13801 11:16:59.437410 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13802 11:16:59.437624 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13803 11:16:59.437866 arm64_za-ptrace_Set_VL_4288 pass
13804 11:16:59.438002 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13805 11:16:59.438116 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13806 11:16:59.438230 arm64_za-ptrace_Set_VL_4304 pass
13807 11:16:59.438344 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13808 11:16:59.438484 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13809 11:16:59.438602 arm64_za-ptrace_Set_VL_4320 pass
13810 11:16:59.438712 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13811 11:16:59.438823 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13812 11:16:59.438933 arm64_za-ptrace_Set_VL_4336 pass
13813 11:16:59.439042 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13814 11:16:59.439151 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13815 11:16:59.439261 arm64_za-ptrace_Set_VL_4352 pass
13816 11:16:59.439371 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13817 11:16:59.439479 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13818 11:16:59.441968 arm64_za-ptrace_Set_VL_4368 pass
13819 11:16:59.442384 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13820 11:16:59.442576 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13821 11:16:59.442744 arm64_za-ptrace_Set_VL_4384 pass
13822 11:16:59.442905 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13823 11:16:59.443094 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13824 11:16:59.443249 arm64_za-ptrace_Set_VL_4400 pass
13825 11:16:59.443412 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13826 11:16:59.443577 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13827 11:16:59.443727 arm64_za-ptrace_Set_VL_4416 pass
13828 11:16:59.443878 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13829 11:16:59.444091 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13830 11:16:59.444283 arm64_za-ptrace_Set_VL_4432 pass
13831 11:16:59.444471 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13832 11:16:59.444672 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13833 11:16:59.444841 arm64_za-ptrace_Set_VL_4448 pass
13834 11:16:59.444995 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13835 11:16:59.445220 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13836 11:16:59.445438 arm64_za-ptrace_Set_VL_4464 pass
13837 11:16:59.445679 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13838 11:16:59.445885 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13839 11:16:59.446057 arm64_za-ptrace_Set_VL_4480 pass
13840 11:16:59.446180 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13841 11:16:59.446297 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13842 11:16:59.446410 arm64_za-ptrace_Set_VL_4496 pass
13843 11:16:59.446521 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13844 11:16:59.446636 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13845 11:16:59.446748 arm64_za-ptrace_Set_VL_4512 pass
13846 11:16:59.446858 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13847 11:16:59.446967 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13848 11:16:59.447077 arm64_za-ptrace_Set_VL_4528 pass
13849 11:16:59.447187 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13850 11:16:59.447296 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13851 11:16:59.447406 arm64_za-ptrace_Set_VL_4544 pass
13852 11:16:59.447515 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13853 11:16:59.447624 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13854 11:16:59.447734 arm64_za-ptrace_Set_VL_4560 pass
13855 11:16:59.447843 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13856 11:16:59.447953 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13857 11:16:59.449980 arm64_za-ptrace_Set_VL_4576 pass
13858 11:16:59.450156 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13859 11:16:59.450559 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13860 11:16:59.450659 arm64_za-ptrace_Set_VL_4592 pass
13861 11:16:59.450747 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13862 11:16:59.450831 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13863 11:16:59.450915 arm64_za-ptrace_Set_VL_4608 pass
13864 11:16:59.451011 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13865 11:16:59.451097 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13866 11:16:59.451379 arm64_za-ptrace_Set_VL_4624 pass
13867 11:16:59.465651 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13868 11:16:59.465983 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13869 11:16:59.466084 arm64_za-ptrace_Set_VL_4640 pass
13870 11:16:59.466416 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13871 11:16:59.466641 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13872 11:16:59.466904 arm64_za-ptrace_Set_VL_4656 pass
13873 11:16:59.467113 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13874 11:16:59.467293 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13875 11:16:59.467455 arm64_za-ptrace_Set_VL_4672 pass
13876 11:16:59.467616 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13877 11:16:59.467814 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13878 11:16:59.467981 arm64_za-ptrace_Set_VL_4688 pass
13879 11:16:59.468141 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13880 11:16:59.468303 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13881 11:16:59.468467 arm64_za-ptrace_Set_VL_4704 pass
13882 11:16:59.468623 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13883 11:16:59.468783 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13884 11:16:59.468931 arm64_za-ptrace_Set_VL_4720 pass
13885 11:16:59.469123 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13886 11:16:59.469294 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13887 11:16:59.469458 arm64_za-ptrace_Set_VL_4736 pass
13888 11:16:59.469612 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13889 11:16:59.469807 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13890 11:16:59.469944 arm64_za-ptrace_Set_VL_4752 pass
13891 11:16:59.470059 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13892 11:16:59.470172 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13893 11:16:59.470284 arm64_za-ptrace_Set_VL_4768 pass
13894 11:16:59.470393 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13895 11:16:59.470503 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13896 11:16:59.470614 arm64_za-ptrace_Set_VL_4784 pass
13897 11:16:59.470754 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13898 11:16:59.470872 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13899 11:16:59.470985 arm64_za-ptrace_Set_VL_4800 pass
13900 11:16:59.471097 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13901 11:16:59.471207 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13902 11:16:59.471319 arm64_za-ptrace_Set_VL_4816 pass
13903 11:16:59.474201 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13904 11:16:59.474393 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13905 11:16:59.474561 arm64_za-ptrace_Set_VL_4832 pass
13906 11:16:59.474748 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13907 11:16:59.474910 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13908 11:16:59.475067 arm64_za-ptrace_Set_VL_4848 pass
13909 11:16:59.475224 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13910 11:16:59.475414 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13911 11:16:59.475575 arm64_za-ptrace_Set_VL_4864 pass
13912 11:16:59.475739 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13913 11:16:59.475899 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13914 11:16:59.476055 arm64_za-ptrace_Set_VL_4880 pass
13915 11:16:59.476206 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13916 11:16:59.476395 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13917 11:16:59.476569 arm64_za-ptrace_Set_VL_4896 pass
13918 11:16:59.476732 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13919 11:16:59.476885 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13920 11:16:59.477022 arm64_za-ptrace_Set_VL_4912 pass
13921 11:16:59.477169 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13922 11:16:59.477331 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13923 11:16:59.477521 arm64_za-ptrace_Set_VL_4928 pass
13924 11:16:59.477753 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13925 11:16:59.477955 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13926 11:16:59.478083 arm64_za-ptrace_Set_VL_4944 pass
13927 11:16:59.478194 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13928 11:16:59.478304 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13929 11:16:59.478412 arm64_za-ptrace_Set_VL_4960 pass
13930 11:16:59.478522 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13931 11:16:59.478631 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13932 11:16:59.478741 arm64_za-ptrace_Set_VL_4976 pass
13933 11:16:59.478849 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13934 11:16:59.478957 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13935 11:16:59.479065 arm64_za-ptrace_Set_VL_4992 pass
13936 11:16:59.479173 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13937 11:16:59.479282 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13938 11:16:59.479389 arm64_za-ptrace_Set_VL_5008 pass
13939 11:16:59.481956 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13940 11:16:59.482438 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13941 11:16:59.482610 arm64_za-ptrace_Set_VL_5024 pass
13942 11:16:59.482759 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13943 11:16:59.482916 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13944 11:16:59.483105 arm64_za-ptrace_Set_VL_5040 pass
13945 11:16:59.483269 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13946 11:16:59.483408 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13947 11:16:59.483569 arm64_za-ptrace_Set_VL_5056 pass
13948 11:16:59.483730 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13949 11:16:59.483887 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13950 11:16:59.484065 arm64_za-ptrace_Set_VL_5072 pass
13951 11:16:59.484287 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13952 11:16:59.484459 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13953 11:16:59.484613 arm64_za-ptrace_Set_VL_5088 pass
13954 11:16:59.484755 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13955 11:16:59.484921 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13956 11:16:59.485118 arm64_za-ptrace_Set_VL_5104 pass
13957 11:16:59.485295 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13958 11:16:59.485498 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13959 11:16:59.485736 arm64_za-ptrace_Set_VL_5120 pass
13960 11:16:59.485921 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13961 11:16:59.486048 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13962 11:16:59.486162 arm64_za-ptrace_Set_VL_5136 pass
13963 11:16:59.486305 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13964 11:16:59.486423 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13965 11:16:59.486535 arm64_za-ptrace_Set_VL_5152 pass
13966 11:16:59.486645 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13967 11:16:59.486756 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13968 11:16:59.486867 arm64_za-ptrace_Set_VL_5168 pass
13969 11:16:59.486978 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13970 11:16:59.487087 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13971 11:16:59.487198 arm64_za-ptrace_Set_VL_5184 pass
13972 11:16:59.487307 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13973 11:16:59.487418 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13974 11:16:59.487527 arm64_za-ptrace_Set_VL_5200 pass
13975 11:16:59.487637 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13976 11:16:59.487752 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13977 11:16:59.489991 arm64_za-ptrace_Set_VL_5216 pass
13978 11:16:59.490417 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13979 11:16:59.490603 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13980 11:16:59.490776 arm64_za-ptrace_Set_VL_5232 pass
13981 11:16:59.490895 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
13982 11:16:59.491034 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
13983 11:16:59.491149 arm64_za-ptrace_Set_VL_5248 pass
13984 11:16:59.491266 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
13985 11:16:59.491403 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
13986 11:16:59.491539 arm64_za-ptrace_Set_VL_5264 pass
13987 11:16:59.491683 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
13988 11:16:59.491831 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
13989 11:16:59.491999 arm64_za-ptrace_Set_VL_5280 pass
13990 11:16:59.492146 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
13991 11:16:59.492282 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
13992 11:16:59.492419 arm64_za-ptrace_Set_VL_5296 pass
13993 11:16:59.492544 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
13994 11:16:59.492693 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
13995 11:16:59.492843 arm64_za-ptrace_Set_VL_5312 pass
13996 11:16:59.492994 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
13997 11:16:59.493148 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
13998 11:16:59.493302 arm64_za-ptrace_Set_VL_5328 pass
13999 11:16:59.493459 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
14000 11:16:59.493678 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
14001 11:16:59.493825 arm64_za-ptrace_Set_VL_5344 pass
14002 11:16:59.493938 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
14003 11:16:59.494047 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
14004 11:16:59.494156 arm64_za-ptrace_Set_VL_5360 pass
14005 11:16:59.494264 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
14006 11:16:59.494372 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
14007 11:16:59.494479 arm64_za-ptrace_Set_VL_5376 pass
14008 11:16:59.494587 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
14009 11:16:59.494698 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
14010 11:16:59.494805 arm64_za-ptrace_Set_VL_5392 pass
14011 11:16:59.494914 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
14012 11:16:59.495021 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
14013 11:16:59.495129 arm64_za-ptrace_Set_VL_5408 pass
14014 11:16:59.495236 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
14015 11:16:59.495344 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
14016 11:16:59.495452 arm64_za-ptrace_Set_VL_5424 pass
14017 11:16:59.495559 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
14018 11:16:59.495690 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
14019 11:16:59.497961 arm64_za-ptrace_Set_VL_5440 pass
14020 11:16:59.498384 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
14021 11:16:59.498567 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
14022 11:16:59.498713 arm64_za-ptrace_Set_VL_5456 pass
14023 11:16:59.498838 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
14024 11:16:59.498963 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
14025 11:16:59.499111 arm64_za-ptrace_Set_VL_5472 pass
14026 11:16:59.499258 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
14027 11:16:59.499422 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
14028 11:16:59.499586 arm64_za-ptrace_Set_VL_5488 pass
14029 11:16:59.499749 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
14030 11:16:59.499908 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
14031 11:16:59.500069 arm64_za-ptrace_Set_VL_5504 pass
14032 11:16:59.500226 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
14033 11:16:59.500417 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
14034 11:16:59.500573 arm64_za-ptrace_Set_VL_5520 pass
14035 11:16:59.500713 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
14036 11:16:59.500850 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
14037 11:16:59.500994 arm64_za-ptrace_Set_VL_5536 pass
14038 11:16:59.501135 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
14039 11:16:59.501290 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
14040 11:16:59.501447 arm64_za-ptrace_Set_VL_5552 pass
14041 11:16:59.501596 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
14042 11:16:59.501740 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
14043 11:16:59.501858 arm64_za-ptrace_Set_VL_5568 pass
14044 11:16:59.501970 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
14045 11:16:59.502111 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
14046 11:16:59.502230 arm64_za-ptrace_Set_VL_5584 pass
14047 11:16:59.502344 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
14048 11:16:59.502455 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
14049 11:16:59.502565 arm64_za-ptrace_Set_VL_5600 pass
14050 11:16:59.502674 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
14051 11:16:59.502787 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
14052 11:16:59.502897 arm64_za-ptrace_Set_VL_5616 pass
14053 11:16:59.503006 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
14054 11:16:59.503116 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
14055 11:16:59.503227 arm64_za-ptrace_Set_VL_5632 pass
14056 11:16:59.503336 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
14057 11:16:59.503446 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
14058 11:16:59.503555 arm64_za-ptrace_Set_VL_5648 pass
14059 11:16:59.518913 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
14060 11:16:59.519228 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
14061 11:16:59.519328 arm64_za-ptrace_Set_VL_5664 pass
14062 11:16:59.519413 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
14063 11:16:59.519513 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
14064 11:16:59.519597 arm64_za-ptrace_Set_VL_5680 pass
14065 11:16:59.519692 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
14066 11:16:59.519775 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
14067 11:16:59.519870 arm64_za-ptrace_Set_VL_5696 pass
14068 11:16:59.519964 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
14069 11:16:59.520255 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
14070 11:16:59.520351 arm64_za-ptrace_Set_VL_5712 pass
14071 11:16:59.520449 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
14072 11:16:59.520546 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
14073 11:16:59.520643 arm64_za-ptrace_Set_VL_5728 pass
14074 11:16:59.520742 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
14075 11:16:59.521036 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
14076 11:16:59.521134 arm64_za-ptrace_Set_VL_5744 pass
14077 11:16:59.521232 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
14078 11:16:59.521330 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
14079 11:16:59.521416 arm64_za-ptrace_Set_VL_5760 pass
14080 11:16:59.521727 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
14081 11:16:59.521825 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
14082 11:16:59.521914 arm64_za-ptrace_Set_VL_5776 pass
14083 11:16:59.525958 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
14084 11:16:59.526380 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
14085 11:16:59.526535 arm64_za-ptrace_Set_VL_5792 pass
14086 11:16:59.526687 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
14087 11:16:59.526800 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
14088 11:16:59.526918 arm64_za-ptrace_Set_VL_5808 pass
14089 11:16:59.527016 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
14090 11:16:59.527109 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
14091 11:16:59.527191 arm64_za-ptrace_Set_VL_5824 pass
14092 11:16:59.527268 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
14093 11:16:59.527354 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
14094 11:16:59.527424 arm64_za-ptrace_Set_VL_5840 pass
14095 11:16:59.527493 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
14096 11:16:59.527587 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
14097 11:16:59.527652 arm64_za-ptrace_Set_VL_5856 pass
14098 11:16:59.527732 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
14099 11:16:59.527828 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
14100 11:16:59.527910 arm64_za-ptrace_Set_VL_5872 pass
14101 11:16:59.527991 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
14102 11:16:59.528089 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
14103 11:16:59.528189 arm64_za-ptrace_Set_VL_5888 pass
14104 11:16:59.528269 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
14105 11:16:59.528361 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
14106 11:16:59.528448 arm64_za-ptrace_Set_VL_5904 pass
14107 11:16:59.528541 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
14108 11:16:59.528637 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
14109 11:16:59.528730 arm64_za-ptrace_Set_VL_5920 pass
14110 11:16:59.528818 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
14111 11:16:59.528930 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
14112 11:16:59.529041 arm64_za-ptrace_Set_VL_5936 pass
14113 11:16:59.529158 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
14114 11:16:59.529265 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
14115 11:16:59.529385 arm64_za-ptrace_Set_VL_5952 pass
14116 11:16:59.529474 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
14117 11:16:59.529570 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
14118 11:16:59.529681 arm64_za-ptrace_Set_VL_5968 pass
14119 11:16:59.529804 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
14120 11:16:59.533913 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
14121 11:16:59.534198 arm64_za-ptrace_Set_VL_5984 pass
14122 11:16:59.534286 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
14123 11:16:59.534409 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
14124 11:16:59.534521 arm64_za-ptrace_Set_VL_6000 pass
14125 11:16:59.534637 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
14126 11:16:59.534732 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
14127 11:16:59.534849 arm64_za-ptrace_Set_VL_6016 pass
14128 11:16:59.534936 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
14129 11:16:59.535022 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
14130 11:16:59.535112 arm64_za-ptrace_Set_VL_6032 pass
14131 11:16:59.535200 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
14132 11:16:59.535286 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
14133 11:16:59.535633 arm64_za-ptrace_Set_VL_6048 pass
14134 11:16:59.535755 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
14135 11:16:59.535852 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
14136 11:16:59.535963 arm64_za-ptrace_Set_VL_6064 pass
14137 11:16:59.536057 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
14138 11:16:59.536128 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
14139 11:16:59.536224 arm64_za-ptrace_Set_VL_6080 pass
14140 11:16:59.536307 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
14141 11:16:59.536401 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
14142 11:16:59.536496 arm64_za-ptrace_Set_VL_6096 pass
14143 11:16:59.536592 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
14144 11:16:59.536675 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
14145 11:16:59.536934 arm64_za-ptrace_Set_VL_6112 pass
14146 11:16:59.537023 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
14147 11:16:59.537105 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
14148 11:16:59.537191 arm64_za-ptrace_Set_VL_6128 pass
14149 11:16:59.537267 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
14150 11:16:59.537349 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
14151 11:16:59.537422 arm64_za-ptrace_Set_VL_6144 pass
14152 11:16:59.537501 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
14153 11:16:59.537761 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
14154 11:16:59.537831 arm64_za-ptrace_Set_VL_6160 pass
14155 11:16:59.537893 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
14156 11:16:59.537953 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
14157 11:16:59.541910 arm64_za-ptrace_Set_VL_6176 pass
14158 11:16:59.542197 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
14159 11:16:59.542278 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
14160 11:16:59.542367 arm64_za-ptrace_Set_VL_6192 pass
14161 11:16:59.542476 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
14162 11:16:59.542560 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
14163 11:16:59.542635 arm64_za-ptrace_Set_VL_6208 pass
14164 11:16:59.542724 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
14165 11:16:59.542800 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
14166 11:16:59.542873 arm64_za-ptrace_Set_VL_6224 pass
14167 11:16:59.542962 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
14168 11:16:59.543033 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
14169 11:16:59.543143 arm64_za-ptrace_Set_VL_6240 pass
14170 11:16:59.543224 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
14171 11:16:59.543314 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
14172 11:16:59.543393 arm64_za-ptrace_Set_VL_6256 pass
14173 11:16:59.543488 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
14174 11:16:59.543563 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
14175 11:16:59.543642 arm64_za-ptrace_Set_VL_6272 pass
14176 11:16:59.543712 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
14177 11:16:59.544022 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
14178 11:16:59.544216 arm64_za-ptrace_Set_VL_6288 pass
14179 11:16:59.544383 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
14180 11:16:59.544578 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
14181 11:16:59.544742 arm64_za-ptrace_Set_VL_6304 pass
14182 11:16:59.544869 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
14183 11:16:59.544984 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
14184 11:16:59.545105 arm64_za-ptrace_Set_VL_6320 pass
14185 11:16:59.545255 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
14186 11:16:59.545377 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
14187 11:16:59.545504 arm64_za-ptrace_Set_VL_6336 pass
14188 11:16:59.545623 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
14189 11:16:59.545757 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
14190 11:16:59.545858 arm64_za-ptrace_Set_VL_6352 pass
14191 11:16:59.545943 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
14192 11:16:59.546047 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
14193 11:16:59.546135 arm64_za-ptrace_Set_VL_6368 pass
14194 11:16:59.546220 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
14195 11:16:59.549900 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
14196 11:16:59.550203 arm64_za-ptrace_Set_VL_6384 pass
14197 11:16:59.550294 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
14198 11:16:59.550407 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
14199 11:16:59.550527 arm64_za-ptrace_Set_VL_6400 pass
14200 11:16:59.550652 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
14201 11:16:59.550752 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
14202 11:16:59.550858 arm64_za-ptrace_Set_VL_6416 pass
14203 11:16:59.550943 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
14204 11:16:59.551029 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
14205 11:16:59.551123 arm64_za-ptrace_Set_VL_6432 pass
14206 11:16:59.551200 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
14207 11:16:59.551287 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
14208 11:16:59.551368 arm64_za-ptrace_Set_VL_6448 pass
14209 11:16:59.551451 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
14210 11:16:59.551537 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
14211 11:16:59.551639 arm64_za-ptrace_Set_VL_6464 pass
14212 11:16:59.551740 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
14213 11:16:59.551844 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
14214 11:16:59.551946 arm64_za-ptrace_Set_VL_6480 pass
14215 11:16:59.552041 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
14216 11:16:59.552138 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
14217 11:16:59.552235 arm64_za-ptrace_Set_VL_6496 pass
14218 11:16:59.552330 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
14219 11:16:59.552641 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
14220 11:16:59.552743 arm64_za-ptrace_Set_VL_6512 pass
14221 11:16:59.553049 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
14222 11:16:59.553151 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
14223 11:16:59.553238 arm64_za-ptrace_Set_VL_6528 pass
14224 11:16:59.553337 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
14225 11:16:59.553427 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14226 11:16:59.553530 arm64_za-ptrace_Set_VL_6544 pass
14227 11:16:59.553626 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14228 11:16:59.553930 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14229 11:16:59.557964 arm64_za-ptrace_Set_VL_6560 pass
14230 11:16:59.558417 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14231 11:16:59.558609 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14232 11:16:59.558777 arm64_za-ptrace_Set_VL_6576 pass
14233 11:16:59.558960 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14234 11:16:59.559135 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14235 11:16:59.559316 arm64_za-ptrace_Set_VL_6592 pass
14236 11:16:59.559510 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14237 11:16:59.559746 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14238 11:16:59.559941 arm64_za-ptrace_Set_VL_6608 pass
14239 11:16:59.560105 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14240 11:16:59.560236 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14241 11:16:59.560350 arm64_za-ptrace_Set_VL_6624 pass
14242 11:16:59.560498 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14243 11:16:59.560619 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14244 11:16:59.560735 arm64_za-ptrace_Set_VL_6640 pass
14245 11:16:59.560859 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14246 11:16:59.560974 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14247 11:16:59.561087 arm64_za-ptrace_Set_VL_6656 pass
14248 11:16:59.561200 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14249 11:16:59.561311 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14250 11:16:59.561422 arm64_za-ptrace_Set_VL_6672 pass
14251 11:16:59.561556 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14252 11:16:59.574619 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14253 11:16:59.574820 arm64_za-ptrace_Set_VL_6688 pass
14254 11:16:59.575017 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14255 11:16:59.575185 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14256 11:16:59.575340 arm64_za-ptrace_Set_VL_6704 pass
14257 11:16:59.575512 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14258 11:16:59.575715 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14259 11:16:59.575872 arm64_za-ptrace_Set_VL_6720 pass
14260 11:16:59.576094 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14261 11:16:59.576306 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14262 11:16:59.576507 arm64_za-ptrace_Set_VL_6736 pass
14263 11:16:59.576660 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14264 11:16:59.576853 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14265 11:16:59.577025 arm64_za-ptrace_Set_VL_6752 pass
14266 11:16:59.577154 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14267 11:16:59.577289 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14268 11:16:59.577441 arm64_za-ptrace_Set_VL_6768 pass
14269 11:16:59.577598 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14270 11:16:59.577810 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14271 11:16:59.578007 arm64_za-ptrace_Set_VL_6784 pass
14272 11:16:59.578188 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14273 11:16:59.578370 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14274 11:16:59.578554 arm64_za-ptrace_Set_VL_6800 pass
14275 11:16:59.578690 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14276 11:16:59.578836 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14277 11:16:59.578978 arm64_za-ptrace_Set_VL_6816 pass
14278 11:16:59.579120 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14279 11:16:59.579261 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14280 11:16:59.579403 arm64_za-ptrace_Set_VL_6832 pass
14281 11:16:59.579544 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14282 11:16:59.581968 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14283 11:16:59.582266 arm64_za-ptrace_Set_VL_6848 pass
14284 11:16:59.582369 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14285 11:16:59.582453 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14286 11:16:59.582552 arm64_za-ptrace_Set_VL_6864 pass
14287 11:16:59.582638 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14288 11:16:59.582736 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14289 11:16:59.582823 arm64_za-ptrace_Set_VL_6880 pass
14290 11:16:59.582925 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14291 11:16:59.583024 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14292 11:16:59.583131 arm64_za-ptrace_Set_VL_6896 pass
14293 11:16:59.583229 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14294 11:16:59.583512 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14295 11:16:59.583611 arm64_za-ptrace_Set_VL_6912 pass
14296 11:16:59.583712 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14297 11:16:59.583798 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14298 11:16:59.583896 arm64_za-ptrace_Set_VL_6928 pass
14299 11:16:59.583993 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14300 11:16:59.584089 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14301 11:16:59.584380 arm64_za-ptrace_Set_VL_6944 pass
14302 11:16:59.584495 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14303 11:16:59.584594 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14304 11:16:59.584690 arm64_za-ptrace_Set_VL_6960 pass
14305 11:16:59.584786 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14306 11:16:59.585079 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14307 11:16:59.585187 arm64_za-ptrace_Set_VL_6976 pass
14308 11:16:59.585287 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14309 11:16:59.585385 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14310 11:16:59.585483 arm64_za-ptrace_Set_VL_6992 pass
14311 11:16:59.585773 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14312 11:16:59.585883 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14313 11:16:59.585988 arm64_za-ptrace_Set_VL_7008 pass
14314 11:16:59.590134 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14315 11:16:59.590250 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14316 11:16:59.590350 arm64_za-ptrace_Set_VL_7024 pass
14317 11:16:59.590436 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14318 11:16:59.590728 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14319 11:16:59.590845 arm64_za-ptrace_Set_VL_7040 pass
14320 11:16:59.590936 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14321 11:16:59.591034 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14322 11:16:59.591133 arm64_za-ptrace_Set_VL_7056 pass
14323 11:16:59.591219 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14324 11:16:59.591511 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14325 11:16:59.591612 arm64_za-ptrace_Set_VL_7072 pass
14326 11:16:59.591710 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14327 11:16:59.592002 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14328 11:16:59.592104 arm64_za-ptrace_Set_VL_7088 pass
14329 11:16:59.592192 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14330 11:16:59.592289 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14331 11:16:59.592371 arm64_za-ptrace_Set_VL_7104 pass
14332 11:16:59.592653 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14333 11:16:59.592756 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14334 11:16:59.592843 arm64_za-ptrace_Set_VL_7120 pass
14335 11:16:59.592944 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14336 11:16:59.593031 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14337 11:16:59.593116 arm64_za-ptrace_Set_VL_7136 pass
14338 11:16:59.593215 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14339 11:16:59.593300 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14340 11:16:59.593401 arm64_za-ptrace_Set_VL_7152 pass
14341 11:16:59.593485 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14342 11:16:59.593590 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14343 11:16:59.593697 arm64_za-ptrace_Set_VL_7168 pass
14344 11:16:59.597976 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14345 11:16:59.598485 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14346 11:16:59.598737 arm64_za-ptrace_Set_VL_7184 pass
14347 11:16:59.598950 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14348 11:16:59.599125 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14349 11:16:59.599318 arm64_za-ptrace_Set_VL_7200 pass
14350 11:16:59.599480 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14351 11:16:59.599643 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14352 11:16:59.599784 arm64_za-ptrace_Set_VL_7216 pass
14353 11:16:59.599934 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14354 11:16:59.600090 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14355 11:16:59.600247 arm64_za-ptrace_Set_VL_7232 pass
14356 11:16:59.600401 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14357 11:16:59.600553 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14358 11:16:59.600747 arm64_za-ptrace_Set_VL_7248 pass
14359 11:16:59.600912 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14360 11:16:59.601070 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14361 11:16:59.601229 arm64_za-ptrace_Set_VL_7264 pass
14362 11:16:59.601380 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14363 11:16:59.601539 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14364 11:16:59.602096 arm64_za-ptrace_Set_VL_7280 pass
14365 11:16:59.602237 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14366 11:16:59.602351 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14367 11:16:59.602463 arm64_za-ptrace_Set_VL_7296 pass
14368 11:16:59.602575 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14369 11:16:59.602686 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14370 11:16:59.602827 arm64_za-ptrace_Set_VL_7312 pass
14371 11:16:59.602949 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14372 11:16:59.603062 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14373 11:16:59.603176 arm64_za-ptrace_Set_VL_7328 pass
14374 11:16:59.603287 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14375 11:16:59.603398 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14376 11:16:59.603509 arm64_za-ptrace_Set_VL_7344 pass
14377 11:16:59.603619 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14378 11:16:59.603730 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14379 11:16:59.603841 arm64_za-ptrace_Set_VL_7360 pass
14380 11:16:59.603955 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14381 11:16:59.604066 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14382 11:16:59.605918 arm64_za-ptrace_Set_VL_7376 pass
14383 11:16:59.606210 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14384 11:16:59.606300 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14385 11:16:59.606384 arm64_za-ptrace_Set_VL_7392 pass
14386 11:16:59.606482 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14387 11:16:59.606565 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14388 11:16:59.606660 arm64_za-ptrace_Set_VL_7408 pass
14389 11:16:59.606756 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14390 11:16:59.606852 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14391 11:16:59.606959 arm64_za-ptrace_Set_VL_7424 pass
14392 11:16:59.607058 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14393 11:16:59.607345 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14394 11:16:59.607437 arm64_za-ptrace_Set_VL_7440 pass
14395 11:16:59.607523 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14396 11:16:59.607805 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14397 11:16:59.607896 arm64_za-ptrace_Set_VL_7456 pass
14398 11:16:59.607980 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14399 11:16:59.608063 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14400 11:16:59.608164 arm64_za-ptrace_Set_VL_7472 pass
14401 11:16:59.608248 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14402 11:16:59.608333 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14403 11:16:59.608430 arm64_za-ptrace_Set_VL_7488 pass
14404 11:16:59.608513 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14405 11:16:59.608610 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14406 11:16:59.608695 arm64_za-ptrace_Set_VL_7504 pass
14407 11:16:59.609026 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14408 11:16:59.609224 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14409 11:16:59.609394 arm64_za-ptrace_Set_VL_7520 pass
14410 11:16:59.609615 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14411 11:16:59.609825 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14412 11:16:59.609941 arm64_za-ptrace_Set_VL_7536 pass
14413 11:16:59.610029 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14414 11:16:59.610135 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14415 11:16:59.610227 arm64_za-ptrace_Set_VL_7552 pass
14416 11:16:59.613962 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14417 11:16:59.614369 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14418 11:16:59.614508 arm64_za-ptrace_Set_VL_7568 pass
14419 11:16:59.614617 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14420 11:16:59.614731 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14421 11:16:59.614878 arm64_za-ptrace_Set_VL_7584 pass
14422 11:16:59.615006 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14423 11:16:59.615119 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14424 11:16:59.615232 arm64_za-ptrace_Set_VL_7600 pass
14425 11:16:59.615348 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14426 11:16:59.615493 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14427 11:16:59.615624 arm64_za-ptrace_Set_VL_7616 pass
14428 11:16:59.615745 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14429 11:16:59.615870 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14430 11:16:59.615991 arm64_za-ptrace_Set_VL_7632 pass
14431 11:16:59.616110 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14432 11:16:59.616256 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14433 11:16:59.616375 arm64_za-ptrace_Set_VL_7648 pass
14434 11:16:59.616498 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14435 11:16:59.616617 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14436 11:16:59.616739 arm64_za-ptrace_Set_VL_7664 pass
14437 11:16:59.616840 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14438 11:16:59.616929 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14439 11:16:59.617036 arm64_za-ptrace_Set_VL_7680 pass
14440 11:16:59.617129 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14441 11:16:59.617231 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14442 11:16:59.617323 arm64_za-ptrace_Set_VL_7696 pass
14443 11:16:59.617409 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14444 11:16:59.640713 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14445 11:16:59.640923 arm64_za-ptrace_Set_VL_7712 pass
14446 11:16:59.641328 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14447 11:16:59.641432 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14448 11:16:59.641520 arm64_za-ptrace_Set_VL_7728 pass
14449 11:16:59.641607 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14450 11:16:59.641755 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14451 11:16:59.641854 arm64_za-ptrace_Set_VL_7744 pass
14452 11:16:59.641958 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14453 11:16:59.642044 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14454 11:16:59.642128 arm64_za-ptrace_Set_VL_7760 pass
14455 11:16:59.642226 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14456 11:16:59.642311 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14457 11:16:59.642406 arm64_za-ptrace_Set_VL_7776 pass
14458 11:16:59.642490 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14459 11:16:59.642596 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14460 11:16:59.642696 arm64_za-ptrace_Set_VL_7792 pass
14461 11:16:59.642793 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14462 11:16:59.643116 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14463 11:16:59.643356 arm64_za-ptrace_Set_VL_7808 pass
14464 11:16:59.643568 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14465 11:16:59.643747 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14466 11:16:59.643950 arm64_za-ptrace_Set_VL_7824 pass
14467 11:16:59.644113 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14468 11:16:59.644312 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14469 11:16:59.644462 arm64_za-ptrace_Set_VL_7840 pass
14470 11:16:59.644618 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14471 11:16:59.644764 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14472 11:16:59.644908 arm64_za-ptrace_Set_VL_7856 pass
14473 11:16:59.645061 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14474 11:16:59.645240 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14475 11:16:59.645392 arm64_za-ptrace_Set_VL_7872 pass
14476 11:16:59.645532 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14477 11:16:59.645687 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14478 11:16:59.645831 arm64_za-ptrace_Set_VL_7888 pass
14479 11:16:59.645959 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14480 11:16:59.646076 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14481 11:16:59.646218 arm64_za-ptrace_Set_VL_7904 pass
14482 11:16:59.646337 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14483 11:16:59.646460 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14484 11:16:59.646577 arm64_za-ptrace_Set_VL_7920 pass
14485 11:16:59.646691 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14486 11:16:59.646806 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14487 11:16:59.646921 arm64_za-ptrace_Set_VL_7936 pass
14488 11:16:59.650103 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14489 11:16:59.650531 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14490 11:16:59.650719 arm64_za-ptrace_Set_VL_7952 pass
14491 11:16:59.650913 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14492 11:16:59.651084 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14493 11:16:59.651228 arm64_za-ptrace_Set_VL_7968 pass
14494 11:16:59.651396 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14495 11:16:59.651561 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14496 11:16:59.651687 arm64_za-ptrace_Set_VL_7984 pass
14497 11:16:59.651819 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14498 11:16:59.651977 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14499 11:16:59.652165 arm64_za-ptrace_Set_VL_8000 pass
14500 11:16:59.652326 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14501 11:16:59.652514 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14502 11:16:59.652774 arm64_za-ptrace_Set_VL_8016 pass
14503 11:16:59.652958 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14504 11:16:59.653122 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14505 11:16:59.653277 arm64_za-ptrace_Set_VL_8032 pass
14506 11:16:59.653427 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14507 11:16:59.653585 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14508 11:16:59.654144 arm64_za-ptrace_Set_VL_8048 pass
14509 11:16:59.654277 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14510 11:16:59.654396 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14511 11:16:59.654513 arm64_za-ptrace_Set_VL_8064 pass
14512 11:16:59.654627 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14513 11:16:59.654741 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14514 11:16:59.654856 arm64_za-ptrace_Set_VL_8080 pass
14515 11:16:59.655002 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14516 11:16:59.655123 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14517 11:16:59.655239 arm64_za-ptrace_Set_VL_8096 pass
14518 11:16:59.655355 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14519 11:16:59.655471 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14520 11:16:59.655586 arm64_za-ptrace_Set_VL_8112 pass
14521 11:16:59.655700 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14522 11:16:59.655815 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14523 11:16:59.655928 arm64_za-ptrace_Set_VL_8128 pass
14524 11:16:59.657957 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14525 11:16:59.658423 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14526 11:16:59.658610 arm64_za-ptrace_Set_VL_8144 pass
14527 11:16:59.658764 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14528 11:16:59.658917 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14529 11:16:59.659120 arm64_za-ptrace_Set_VL_8160 pass
14530 11:16:59.659283 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14531 11:16:59.659431 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14532 11:16:59.659614 arm64_za-ptrace_Set_VL_8176 pass
14533 11:16:59.659782 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14534 11:16:59.659940 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14535 11:16:59.660108 arm64_za-ptrace_Set_VL_8192 pass
14536 11:16:59.660311 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14537 11:16:59.660461 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14538 11:16:59.660605 arm64_za-ptrace pass
14539 11:16:59.660741 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14540 11:16:59.660871 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14541 11:16:59.661061 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14542 11:16:59.661243 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14543 11:16:59.661436 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14544 11:16:59.661595 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14545 11:16:59.662198 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14546 11:16:59.662330 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14547 11:16:59.662474 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14548 11:16:59.662597 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14549 11:16:59.666035 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14550 11:16:59.666461 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14551 11:16:59.666630 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14552 11:16:59.666808 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14553 11:16:59.666995 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14554 11:16:59.667181 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14555 11:16:59.667590 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14556 11:16:59.667813 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14557 11:16:59.668014 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14558 11:16:59.668201 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14559 11:16:59.668353 arm64_check_buffer_fill fail
14560 11:16:59.668504 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14561 11:16:59.668693 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14562 11:16:59.668882 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14563 11:16:59.669303 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14564 11:16:59.669577 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14565 11:16:59.669804 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14566 11:16:59.673935 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14567 11:16:59.674386 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14568 11:16:59.674540 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14569 11:16:59.674899 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14570 11:16:59.675094 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14571 11:16:59.675243 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14572 11:16:59.675487 arm64_check_child_memory fail
14573 11:16:59.675685 arm64_check_gcr_el1_cswitch fail
14574 11:16:59.675868 arm64_check_ksm_options fail
14575 11:16:59.676041 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14576 11:16:59.676205 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14577 11:16:59.676382 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14578 11:16:59.676531 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14579 11:16:59.676701 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14580 11:16:59.683739 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14581 11:16:59.684154 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14582 11:16:59.684405 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14583 11:16:59.684623 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14584 11:16:59.684809 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14585 11:16:59.685030 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14586 11:16:59.685497 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14587 11:16:59.685728 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14588 11:16:59.686130 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14589 11:16:59.686374 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14590 11:16:59.686586 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14591 11:16:59.686783 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14592 11:16:59.686981 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14593 11:16:59.687452 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14594 11:16:59.687683 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14595 11:16:59.687930 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14596 11:16:59.688140 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14597 11:16:59.688324 arm64_check_mmap_options fail
14598 11:16:59.688571 arm64_check_prctl_check_basic_read pass
14599 11:16:59.688768 arm64_check_prctl_NONE pass
14600 11:16:59.688987 arm64_check_prctl_SYNC pass
14601 11:16:59.689180 arm64_check_prctl_ASYNC pass
14602 11:16:59.689340 arm64_check_prctl_SYNC_ASYNC pass
14603 11:16:59.689529 arm64_check_prctl pass
14604 11:16:59.689701 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14605 11:16:59.689850 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14606 11:16:59.689971 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14607 11:16:59.690091 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14608 11:16:59.690206 arm64_check_tags_inclusion fail
14609 11:16:59.690320 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14610 11:16:59.693975 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14611 11:16:59.694456 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14612 11:16:59.694656 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14613 11:16:59.694827 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14614 11:16:59.695011 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14615 11:16:59.695178 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14616 11:16:59.695359 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14617 11:16:59.695511 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14618 11:16:59.695702 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14619 11:16:59.695862 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14620 11:16:59.696047 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14621 11:16:59.696237 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14622 11:16:59.696371 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14623 11:16:59.696539 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14624 11:16:59.696700 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14625 11:16:59.696877 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14626 11:16:59.697075 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14627 11:16:59.697255 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14628 11:16:59.697513 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14629 11:16:59.697777 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14630 11:16:59.697964 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14631 11:16:59.701973 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14632 11:16:59.702398 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14633 11:16:59.702587 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14634 11:16:59.702779 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14635 11:16:59.702906 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14636 11:16:59.703044 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14637 11:16:59.703250 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14638 11:16:59.703428 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14639 11:16:59.703624 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14640 11:16:59.703808 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14641 11:16:59.703970 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14642 11:16:59.704151 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14643 11:16:59.704312 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14644 11:16:59.704462 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14645 11:16:59.704607 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14646 11:16:59.704987 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14647 11:16:59.705123 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14648 11:16:59.705235 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14649 11:16:59.705523 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14650 11:16:59.705625 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14651 11:16:59.710086 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14652 11:16:59.710518 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14653 11:16:59.710691 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14654 11:16:59.710853 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14655 11:16:59.711034 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14656 11:16:59.711169 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14657 11:16:59.711309 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14658 11:16:59.711440 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14659 11:16:59.711656 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14660 11:16:59.711865 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14661 11:16:59.712133 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14662 11:16:59.712379 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14663 11:16:59.712600 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14664 11:16:59.712796 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14665 11:16:59.712996 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14666 11:16:59.713255 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14667 11:16:59.713480 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14668 11:16:59.713761 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14669 11:16:59.713991 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14670 11:16:59.721965 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14671 11:16:59.736469 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14672 11:16:59.736855 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14673 11:16:59.737001 arm64_check_user_mem pass
14674 11:16:59.737133 arm64_btitest_nohint_func_call_using_br_x0 pass
14675 11:16:59.737322 arm64_btitest_nohint_func_call_using_br_x16 pass
14676 11:16:59.737500 arm64_btitest_nohint_func_call_using_blr pass
14677 11:16:59.737701 arm64_btitest_bti_none_func_call_using_br_x0 pass
14678 11:16:59.737882 arm64_btitest_bti_none_func_call_using_br_x16 pass
14679 11:16:59.738039 arm64_btitest_bti_none_func_call_using_blr pass
14680 11:16:59.738184 arm64_btitest_bti_c_func_call_using_br_x0 pass
14681 11:16:59.738343 arm64_btitest_bti_c_func_call_using_br_x16 pass
14682 11:16:59.738556 arm64_btitest_bti_c_func_call_using_blr pass
14683 11:16:59.738764 arm64_btitest_bti_j_func_call_using_br_x0 pass
14684 11:16:59.738970 arm64_btitest_bti_j_func_call_using_br_x16 pass
14685 11:16:59.739161 arm64_btitest_bti_j_func_call_using_blr pass
14686 11:16:59.739321 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14687 11:16:59.739507 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14688 11:16:59.739682 arm64_btitest_bti_jc_func_call_using_blr pass
14689 11:16:59.739848 arm64_btitest_paciasp_func_call_using_br_x0 pass
14690 11:16:59.740009 arm64_btitest_paciasp_func_call_using_br_x16 pass
14691 11:16:59.740199 arm64_btitest_paciasp_func_call_using_blr pass
14692 11:16:59.740417 arm64_btitest pass
14693 11:16:59.740592 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14694 11:16:59.740785 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14695 11:16:59.740970 arm64_nobtitest_nohint_func_call_using_blr pass
14696 11:16:59.741136 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14697 11:16:59.741284 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14698 11:16:59.741448 arm64_nobtitest_bti_none_func_call_using_blr pass
14699 11:16:59.741642 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14700 11:16:59.741835 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14701 11:16:59.741968 arm64_nobtitest_bti_c_func_call_using_blr pass
14702 11:16:59.742083 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14703 11:16:59.742196 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14704 11:16:59.742332 arm64_nobtitest_bti_j_func_call_using_blr pass
14705 11:16:59.742448 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14706 11:16:59.742559 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14707 11:16:59.742669 arm64_nobtitest_bti_jc_func_call_using_blr pass
14708 11:16:59.742778 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14709 11:16:59.742887 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14710 11:16:59.742995 arm64_nobtitest_paciasp_func_call_using_blr pass
14711 11:16:59.743104 arm64_nobtitest pass
14712 11:16:59.745953 arm64_hwcap_cpuinfo_match_RNG pass
14713 11:16:59.746507 arm64_hwcap_sigill_RNG pass
14714 11:16:59.746695 arm64_hwcap_cpuinfo_match_SME pass
14715 11:16:59.746878 arm64_hwcap_sigill_SME pass
14716 11:16:59.747050 arm64_hwcap_cpuinfo_match_SVE pass
14717 11:16:59.747242 arm64_hwcap_sigill_SVE pass
14718 11:16:59.747422 arm64_hwcap_cpuinfo_match_SVE_2 pass
14719 11:16:59.747578 arm64_hwcap_sigill_SVE_2 pass
14720 11:16:59.747789 arm64_hwcap_cpuinfo_match_SVE_AES pass
14721 11:16:59.747960 arm64_hwcap_sigill_SVE_AES pass
14722 11:16:59.748117 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14723 11:16:59.748278 arm64_hwcap_sigill_SVE2_PMULL pass
14724 11:16:59.748475 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14725 11:16:59.748651 arm64_hwcap_sigill_SVE2_BITPERM pass
14726 11:16:59.748874 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14727 11:16:59.749083 arm64_hwcap_sigill_SVE2_SHA3 pass
14728 11:16:59.749264 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14729 11:16:59.749445 arm64_hwcap_sigill_SVE2_SM4 pass
14730 11:16:59.749604 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14731 11:16:59.749776 arm64_hwcap_sigill_SVE2_I8MM pass
14732 11:16:59.749957 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14733 11:16:59.750117 arm64_hwcap_sigill_SVE2_F32MM pass
14734 11:16:59.750238 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14735 11:16:59.750353 arm64_hwcap_sigill_SVE2_F64MM pass
14736 11:16:59.750465 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14737 11:16:59.750577 arm64_hwcap_sigill_SVE2_BF16 pass
14738 11:16:59.750688 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14739 11:16:59.750801 arm64_hwcap_sigill_SVE2_EBF16 skip
14740 11:16:59.750913 arm64_hwcap pass
14741 11:16:59.751025 arm64_ptrace_read_tpidr_one pass
14742 11:16:59.751136 arm64_ptrace_write_tpidr_one pass
14743 11:16:59.751248 arm64_ptrace_verify_tpidr_one pass
14744 11:16:59.751359 arm64_ptrace_count_tpidrs pass
14745 11:16:59.751469 arm64_ptrace_tpidr2_write pass
14746 11:16:59.751580 arm64_ptrace_tpidr2_read pass
14747 11:16:59.751690 arm64_ptrace_write_tpidr_only pass
14748 11:16:59.751800 arm64_ptrace pass
14749 11:16:59.751911 arm64_syscall-abi_getpid_FPSIMD pass
14750 11:16:59.752020 arm64_syscall-abi_getpid_SVE_VL_256 pass
14751 11:16:59.752131 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14752 11:16:59.752246 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14753 11:16:59.754001 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14754 11:16:59.754639 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14755 11:16:59.754846 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14756 11:16:59.755054 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14757 11:16:59.755258 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14758 11:16:59.755458 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14759 11:16:59.755664 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14760 11:16:59.755817 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14761 11:16:59.755993 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14762 11:16:59.756201 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14763 11:16:59.756398 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14764 11:16:59.756562 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14765 11:16:59.756732 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14766 11:16:59.756960 arm64_syscall-abi_getpid_SVE_VL_240 pass
14767 11:16:59.757138 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14768 11:16:59.757306 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14769 11:16:59.757469 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14770 11:16:59.757631 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14771 11:16:59.757778 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14772 11:16:59.757894 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14773 11:16:59.758008 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14774 11:16:59.758121 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14775 11:16:59.758263 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14776 11:16:59.758379 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14777 11:16:59.758492 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14778 11:16:59.758604 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14779 11:16:59.758716 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14780 11:16:59.762025 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14781 11:16:59.762204 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14782 11:16:59.762654 arm64_syscall-abi_getpid_SVE_VL_224 pass
14783 11:16:59.762806 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14784 11:16:59.762940 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14785 11:16:59.763062 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14786 11:16:59.763211 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14787 11:16:59.763347 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14788 11:16:59.763479 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14789 11:16:59.763606 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14790 11:16:59.763758 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14791 11:16:59.763893 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14792 11:16:59.764029 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14793 11:16:59.764203 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14794 11:16:59.764384 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14795 11:16:59.764553 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14796 11:16:59.764729 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14797 11:16:59.764871 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14798 11:16:59.764999 arm64_syscall-abi_getpid_SVE_VL_208 pass
14799 11:16:59.765143 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14800 11:16:59.765287 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14801 11:16:59.765413 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14802 11:16:59.765537 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14803 11:16:59.765669 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14804 11:16:59.765795 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14805 11:16:59.765885 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14806 11:16:59.765976 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14807 11:16:59.766061 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14808 11:16:59.769977 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14809 11:16:59.770332 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14810 11:16:59.770468 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14811 11:16:59.770591 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14812 11:16:59.770737 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14813 11:16:59.770861 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14814 11:16:59.770981 arm64_syscall-abi_getpid_SVE_VL_192 pass
14815 11:16:59.771120 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14816 11:16:59.771242 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14817 11:16:59.771353 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14818 11:16:59.771490 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14819 11:16:59.771632 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14820 11:16:59.771755 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14821 11:16:59.771896 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14822 11:16:59.772020 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14823 11:16:59.772161 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14824 11:16:59.772306 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14825 11:16:59.772426 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14826 11:16:59.772564 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14827 11:16:59.772685 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14828 11:16:59.772829 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14829 11:16:59.772970 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14830 11:16:59.773116 arm64_syscall-abi_getpid_SVE_VL_176 pass
14831 11:16:59.773260 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14832 11:16:59.773406 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14833 11:16:59.773532 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14834 11:16:59.773681 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14835 11:16:59.773832 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14836 11:16:59.777982 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14837 11:16:59.778418 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14838 11:16:59.778598 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14839 11:16:59.778757 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14840 11:16:59.778972 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14841 11:16:59.788709 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14842 11:16:59.788940 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14843 11:16:59.789121 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14844 11:16:59.789436 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14845 11:16:59.789627 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14846 11:16:59.789811 arm64_syscall-abi_getpid_SVE_VL_160 pass
14847 11:16:59.789982 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14848 11:16:59.790178 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14849 11:16:59.790435 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14850 11:16:59.790662 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14851 11:16:59.790887 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14852 11:16:59.791119 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14853 11:16:59.791359 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14854 11:16:59.791595 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14855 11:16:59.791796 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14856 11:16:59.792006 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14857 11:16:59.792180 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14858 11:16:59.792349 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14859 11:16:59.792514 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14860 11:16:59.792680 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14861 11:16:59.792877 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14862 11:16:59.793093 arm64_syscall-abi_getpid_SVE_VL_144 pass
14863 11:16:59.793263 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14864 11:16:59.793424 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14865 11:16:59.793580 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14866 11:16:59.794263 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14867 11:16:59.794396 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14868 11:16:59.794513 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14869 11:16:59.794629 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14870 11:16:59.794772 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14871 11:16:59.794895 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14872 11:16:59.795010 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14873 11:16:59.795125 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14874 11:16:59.795241 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14875 11:16:59.797979 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14876 11:16:59.798422 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14877 11:16:59.798618 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14878 11:16:59.798835 arm64_syscall-abi_getpid_SVE_VL_128 pass
14879 11:16:59.799086 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14880 11:16:59.799296 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14881 11:16:59.799499 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14882 11:16:59.799708 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14883 11:16:59.799949 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14884 11:16:59.800135 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14885 11:16:59.800316 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14886 11:16:59.800469 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14887 11:16:59.800624 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14888 11:16:59.800779 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14889 11:16:59.800992 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14890 11:16:59.801183 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14891 11:16:59.801374 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14892 11:16:59.801542 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14893 11:16:59.802005 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14894 11:16:59.802146 arm64_syscall-abi_getpid_SVE_VL_112 pass
14895 11:16:59.802266 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14896 11:16:59.802380 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14897 11:16:59.802524 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14898 11:16:59.802645 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14899 11:16:59.802764 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14900 11:16:59.802879 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14901 11:16:59.802995 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14902 11:16:59.805944 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14903 11:16:59.806348 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14904 11:16:59.806474 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14905 11:16:59.806563 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14906 11:16:59.806660 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14907 11:16:59.806903 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14908 11:16:59.807025 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14909 11:16:59.807113 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14910 11:16:59.807210 arm64_syscall-abi_getpid_SVE_VL_96 pass
14911 11:16:59.807512 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14912 11:16:59.807613 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14913 11:16:59.807711 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14914 11:16:59.807812 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14915 11:16:59.808088 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14916 11:16:59.808192 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14917 11:16:59.808298 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14918 11:16:59.808679 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14919 11:16:59.808907 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14920 11:16:59.809110 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14921 11:16:59.809287 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14922 11:16:59.809496 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14923 11:16:59.809733 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14924 11:16:59.809893 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14925 11:16:59.810012 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14926 11:16:59.810122 arm64_syscall-abi_getpid_SVE_VL_80 pass
14927 11:16:59.810233 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14928 11:16:59.813939 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14929 11:16:59.814360 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14930 11:16:59.814712 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14931 11:16:59.814918 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14932 11:16:59.815129 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14933 11:16:59.815300 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14934 11:16:59.815483 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14935 11:16:59.815701 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14936 11:16:59.815901 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14937 11:16:59.816091 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14938 11:16:59.816272 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14939 11:16:59.816473 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14940 11:16:59.816642 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14941 11:16:59.816803 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14942 11:16:59.816969 arm64_syscall-abi_getpid_SVE_VL_64 pass
14943 11:16:59.817139 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14944 11:16:59.817364 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14945 11:16:59.817541 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14946 11:16:59.818096 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14947 11:16:59.818234 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14948 11:16:59.818381 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14949 11:16:59.818500 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14950 11:16:59.818613 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14951 11:16:59.818726 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14952 11:16:59.818838 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14953 11:16:59.818950 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14954 11:16:59.819062 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14955 11:16:59.819174 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14956 11:16:59.821998 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14957 11:16:59.822401 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14958 11:16:59.822509 arm64_syscall-abi_getpid_SVE_VL_48 pass
14959 11:16:59.822621 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14960 11:16:59.822734 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14961 11:16:59.822832 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14962 11:16:59.822928 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14963 11:16:59.823028 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14964 11:16:59.823116 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14965 11:16:59.823224 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14966 11:16:59.823337 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14967 11:16:59.823420 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14968 11:16:59.823510 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14969 11:16:59.823602 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14970 11:16:59.823687 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14971 11:16:59.823973 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14972 11:16:59.824088 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14973 11:16:59.824189 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14974 11:16:59.824512 arm64_syscall-abi_getpid_SVE_VL_32 pass
14975 11:16:59.824613 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14976 11:16:59.824711 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14977 11:16:59.825082 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14978 11:16:59.825315 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14979 11:16:59.825512 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14980 11:16:59.825684 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
14981 11:16:59.825835 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
14982 11:16:59.825960 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
14983 11:16:59.826096 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
14984 11:16:59.829998 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
14985 11:16:59.830700 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
14986 11:16:59.830855 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
14987 11:16:59.830998 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
14988 11:16:59.831130 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
14989 11:16:59.831263 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
14990 11:16:59.831366 arm64_syscall-abi_getpid_SVE_VL_16 pass
14991 11:16:59.831511 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
14992 11:16:59.831639 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
14993 11:16:59.840443 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
14994 11:16:59.840745 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
14995 11:16:59.840848 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
14996 11:16:59.840949 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
14997 11:16:59.841035 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
14998 11:16:59.841129 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
14999 11:16:59.841232 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
15000 11:16:59.841577 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
15001 11:16:59.841689 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
15002 11:16:59.841790 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
15003 11:16:59.841896 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
15004 11:16:59.842177 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
15005 11:16:59.842283 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
15006 11:16:59.842577 arm64_syscall-abi_sched_yield_FPSIMD pass
15007 11:16:59.842675 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
15008 11:16:59.842772 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
15009 11:16:59.842867 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
15010 11:16:59.842963 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
15011 11:16:59.843190 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
15012 11:16:59.843528 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
15013 11:16:59.843628 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
15014 11:16:59.843924 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
15015 11:16:59.844024 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
15016 11:16:59.844123 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
15017 11:16:59.844423 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
15018 11:16:59.844551 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
15019 11:16:59.844687 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
15020 11:16:59.844803 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
15021 11:16:59.844934 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
15022 11:16:59.845061 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
15023 11:16:59.845207 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
15024 11:16:59.845327 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
15025 11:16:59.845467 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
15026 11:16:59.845585 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
15027 11:16:59.845730 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
15028 11:16:59.845860 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
15029 11:16:59.849948 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
15030 11:16:59.850348 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
15031 11:16:59.850534 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
15032 11:16:59.850701 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
15033 11:16:59.850891 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
15034 11:16:59.851039 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
15035 11:16:59.851223 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
15036 11:16:59.851425 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
15037 11:16:59.851592 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
15038 11:16:59.851787 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
15039 11:16:59.851942 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
15040 11:16:59.852104 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
15041 11:16:59.852235 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
15042 11:16:59.852375 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
15043 11:16:59.852525 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
15044 11:16:59.852646 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
15045 11:16:59.852795 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
15046 11:16:59.852923 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
15047 11:16:59.853079 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
15048 11:16:59.853240 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
15049 11:16:59.853400 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
15050 11:16:59.853549 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
15051 11:16:59.854074 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
15052 11:16:59.854286 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
15053 11:16:59.854426 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
15054 11:16:59.854568 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
15055 11:16:59.854710 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
15056 11:16:59.854850 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
15057 11:16:59.854990 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
15058 11:16:59.855129 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
15059 11:16:59.855269 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
15060 11:16:59.855409 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
15061 11:16:59.857993 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
15062 11:16:59.858393 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
15063 11:16:59.858557 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
15064 11:16:59.858689 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
15065 11:16:59.858838 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
15066 11:16:59.858976 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
15067 11:16:59.859149 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
15068 11:16:59.859306 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
15069 11:16:59.859518 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
15070 11:16:59.859711 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
15071 11:16:59.859904 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
15072 11:16:59.860090 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
15073 11:16:59.860294 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
15074 11:16:59.860500 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
15075 11:16:59.860661 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
15076 11:16:59.860821 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
15077 11:16:59.860985 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
15078 11:16:59.861127 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
15079 11:16:59.861256 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
15080 11:16:59.861394 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
15081 11:16:59.861588 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
15082 11:16:59.861775 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
15083 11:16:59.861919 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
15084 11:16:59.862035 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
15085 11:16:59.862149 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
15086 11:16:59.862261 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
15087 11:16:59.862373 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
15088 11:16:59.862489 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
15089 11:16:59.862626 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
15090 11:16:59.865939 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
15091 11:16:59.866447 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
15092 11:16:59.866637 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
15093 11:16:59.866808 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
15094 11:16:59.867008 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
15095 11:16:59.867202 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
15096 11:16:59.867379 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
15097 11:16:59.867568 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
15098 11:16:59.867730 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
15099 11:16:59.867914 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
15100 11:16:59.868115 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
15101 11:16:59.868310 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
15102 11:16:59.868506 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
15103 11:16:59.868655 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
15104 11:16:59.868849 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
15105 11:16:59.869001 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
15106 11:16:59.869132 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
15107 11:16:59.869279 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
15108 11:16:59.869470 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
15109 11:16:59.869641 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
15110 11:16:59.870207 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
15111 11:16:59.870331 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
15112 11:16:59.870478 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
15113 11:16:59.870602 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
15114 11:16:59.873954 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
15115 11:16:59.874406 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
15116 11:16:59.874579 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
15117 11:16:59.874737 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
15118 11:16:59.874919 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
15119 11:16:59.875055 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
15120 11:16:59.875205 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
15121 11:16:59.875346 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
15122 11:16:59.875528 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
15123 11:16:59.875659 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
15124 11:16:59.875774 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
15125 11:16:59.875903 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
15126 11:16:59.876036 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
15127 11:16:59.876223 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
15128 11:16:59.876352 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
15129 11:16:59.876470 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
15130 11:16:59.876625 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
15131 11:16:59.876751 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
15132 11:16:59.876889 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
15133 11:16:59.887967 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
15134 11:16:59.888469 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
15135 11:16:59.888671 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
15136 11:16:59.888845 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
15137 11:16:59.889011 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
15138 11:16:59.889209 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
15139 11:16:59.889379 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
15140 11:16:59.889545 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
15141 11:16:59.889766 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
15142 11:16:59.889958 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
15143 11:16:59.890137 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
15144 11:16:59.890314 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
15145 11:16:59.890500 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
15146 11:16:59.890653 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
15147 11:16:59.891043 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
15148 11:16:59.891258 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
15149 11:16:59.891455 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
15150 11:16:59.891651 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
15151 11:16:59.891818 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
15152 11:16:59.892004 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
15153 11:16:59.892198 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
15154 11:16:59.892363 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
15155 11:16:59.892560 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
15156 11:16:59.892729 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
15157 11:16:59.892894 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
15158 11:16:59.893085 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
15159 11:16:59.893262 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
15160 11:16:59.893444 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
15161 11:16:59.893618 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
15162 11:16:59.893813 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
15163 11:16:59.893941 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
15164 11:16:59.894058 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
15165 11:16:59.894172 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
15166 11:16:59.897944 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
15167 11:16:59.898466 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
15168 11:16:59.898694 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
15169 11:16:59.898883 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
15170 11:16:59.899078 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
15171 11:16:59.899243 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
15172 11:16:59.899409 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
15173 11:16:59.899591 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
15174 11:16:59.899795 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
15175 11:16:59.899944 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
15176 11:16:59.900093 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
15177 11:16:59.900253 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
15178 11:16:59.900415 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
15179 11:16:59.900603 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
15180 11:16:59.900761 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
15181 11:16:59.900922 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
15182 11:16:59.901083 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
15183 11:16:59.901243 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
15184 11:16:59.901444 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
15185 11:16:59.901588 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
15186 11:16:59.902142 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
15187 11:16:59.902276 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
15188 11:16:59.902391 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
15189 11:16:59.902506 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
15190 11:16:59.902645 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
15191 11:16:59.902764 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
15192 11:16:59.906045 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
15193 11:16:59.906444 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
15194 11:16:59.906550 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
15195 11:16:59.906635 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
15196 11:16:59.906731 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
15197 11:16:59.906829 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
15198 11:16:59.906925 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
15199 11:16:59.907021 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
15200 11:16:59.907313 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
15201 11:16:59.907428 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
15202 11:16:59.907727 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
15203 11:16:59.907843 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
15204 11:16:59.907944 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
15205 11:16:59.908259 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
15206 11:16:59.908361 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
15207 11:16:59.908459 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
15208 11:16:59.908805 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
15209 11:16:59.909004 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
15210 11:16:59.909167 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
15211 11:16:59.909332 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
15212 11:16:59.909527 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
15213 11:16:59.909720 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
15214 11:16:59.909866 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
15215 11:16:59.909986 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
15216 11:16:59.910123 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
15217 11:16:59.913978 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
15218 11:16:59.914417 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
15219 11:16:59.914606 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
15220 11:16:59.914775 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
15221 11:16:59.914968 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
15222 11:16:59.915156 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
15223 11:16:59.915330 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
15224 11:16:59.915588 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
15225 11:16:59.915789 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15226 11:16:59.915967 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15227 11:16:59.916183 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15228 11:16:59.916389 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15229 11:16:59.916555 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15230 11:16:59.916696 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15231 11:16:59.916903 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15232 11:16:59.917089 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15233 11:16:59.917247 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15234 11:16:59.917402 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15235 11:16:59.917596 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15236 11:16:59.918117 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15237 11:16:59.918253 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15238 11:16:59.918372 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15239 11:16:59.918489 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15240 11:16:59.918610 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15241 11:16:59.921924 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15242 11:16:59.922209 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15243 11:16:59.922331 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15244 11:16:59.922419 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15245 11:16:59.922518 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15246 11:16:59.922810 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15247 11:16:59.922929 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15248 11:16:59.923028 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15249 11:16:59.923128 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15250 11:16:59.923399 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15251 11:16:59.923499 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15252 11:16:59.923598 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15253 11:16:59.923900 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15254 11:16:59.924097 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15255 11:16:59.924184 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15256 11:16:59.924486 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15257 11:16:59.924592 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15258 11:16:59.924689 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15259 11:16:59.924787 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15260 11:16:59.925134 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15261 11:16:59.925385 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15262 11:16:59.925531 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15263 11:16:59.925652 arm64_syscall-abi pass
15264 11:16:59.925740 arm64_tpidr2_default_value pass
15265 11:16:59.925830 arm64_tpidr2_write_read pass
15266 11:16:59.925935 arm64_tpidr2_write_sleep_read pass
15267 11:16:59.929941 arm64_tpidr2_write_fork_read pass
15268 11:16:59.930238 arm64_tpidr2_write_clone_read pass
15269 11:16:59.930336 arm64_tpidr2 pass
15270 11:16:59.940007 + ../../utils/send-to-lava.sh ./output/result.txt
15271 11:16:59.983049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15272 11:16:59.984088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15274 11:17:00.014859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15276 11:17:00.015372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15277 11:17:00.045753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15279 11:17:00.046205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15280 11:17:00.076181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15281 11:17:00.076634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15283 11:17:00.106575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15284 11:17:00.107007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15286 11:17:00.136775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15287 11:17:00.137254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15289 11:17:00.166970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15290 11:17:00.167438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15292 11:17:00.197197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15293 11:17:00.197561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15295 11:17:00.227145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15296 11:17:00.227537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15298 11:17:00.257300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15299 11:17:00.257685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15301 11:17:00.288065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15302 11:17:00.288536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15304 11:17:00.318578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15305 11:17:00.318993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15307 11:17:00.348276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15308 11:17:00.348678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15310 11:17:00.378556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15312 11:17:00.379038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15313 11:17:00.408217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15315 11:17:00.408756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15316 11:17:00.438414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15317 11:17:00.438801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15319 11:17:00.468045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15320 11:17:00.468426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15322 11:17:00.499343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15324 11:17:00.499927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15325 11:17:00.531750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15327 11:17:00.532088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15328 11:17:00.561942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15330 11:17:00.562287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15331 11:17:00.592206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15332 11:17:00.592679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15334 11:17:00.622064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15336 11:17:00.622736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15337 11:17:00.651993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15338 11:17:00.652433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15340 11:17:00.681671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15342 11:17:00.682188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15343 11:17:00.711689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15345 11:17:00.712139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15346 11:17:00.741547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15347 11:17:00.742040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15349 11:17:00.772314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15351 11:17:00.772939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15352 11:17:00.802684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15354 11:17:00.803286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15355 11:17:00.832945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15356 11:17:00.833409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15358 11:17:00.863358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15359 11:17:00.863772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15361 11:17:00.895465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15363 11:17:00.896026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15364 11:17:00.925872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15365 11:17:00.926322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15367 11:17:00.956261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15368 11:17:00.956698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15370 11:17:00.990457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15371 11:17:00.990873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15373 11:17:01.020423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15374 11:17:01.020868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15376 11:17:01.050708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15378 11:17:01.051236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15379 11:17:01.079636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15380 11:17:01.080145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15382 11:17:01.109803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15384 11:17:01.110375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15385 11:17:01.139188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15386 11:17:01.139635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15388 11:17:01.168934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15389 11:17:01.169412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15391 11:17:01.198740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15392 11:17:01.199202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15394 11:17:01.228489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15395 11:17:01.228857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15397 11:17:01.259102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15399 11:17:01.259608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15400 11:17:01.288788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15402 11:17:01.289347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15403 11:17:01.318844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15405 11:17:01.319385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15406 11:17:01.348143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15408 11:17:01.348685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15409 11:17:01.377506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15411 11:17:01.377955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15412 11:17:01.408394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15413 11:17:01.408743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15415 11:17:01.438402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15417 11:17:01.438841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15418 11:17:01.467657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15419 11:17:01.468018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15421 11:17:01.498888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15422 11:17:01.499335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15424 11:17:01.528603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15426 11:17:01.529079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15427 11:17:01.559121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15428 11:17:01.559604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15430 11:17:01.589105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15431 11:17:01.589584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15433 11:17:01.619437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15435 11:17:01.619997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15436 11:17:01.650945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15437 11:17:01.651405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15439 11:17:01.681771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15440 11:17:01.682244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15442 11:17:01.715099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15444 11:17:01.715641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15445 11:17:01.746997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15447 11:17:01.747445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15448 11:17:01.779529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15449 11:17:01.779969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15451 11:17:01.813564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15452 11:17:01.813992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15454 11:17:01.847283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15455 11:17:01.847758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15457 11:17:01.879489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15458 11:17:01.879964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15460 11:17:01.911522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15461 11:17:01.911920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15463 11:17:01.942527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15464 11:17:01.942988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15466 11:17:01.972523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15467 11:17:01.972991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15469 11:17:02.003103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15470 11:17:02.003632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15472 11:17:02.032851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15473 11:17:02.033314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15475 11:17:02.063097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15477 11:17:02.063678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15478 11:17:02.092986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15479 11:17:02.093383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15481 11:17:02.123119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15482 11:17:02.123710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15484 11:17:02.153115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15486 11:17:02.153738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15487 11:17:02.183165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15489 11:17:02.183731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15490 11:17:02.212918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15491 11:17:02.213378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15493 11:17:02.243824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15494 11:17:02.244288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15496 11:17:02.274750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15498 11:17:02.275176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15499 11:17:02.305683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15501 11:17:02.306215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15502 11:17:02.335826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15503 11:17:02.336290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15505 11:17:02.366946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15506 11:17:02.367402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15508 11:17:02.397012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15509 11:17:02.397476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15511 11:17:02.427302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15513 11:17:02.427870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15514 11:17:02.458170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15516 11:17:02.458555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15517 11:17:02.490848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15518 11:17:02.491310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15520 11:17:02.520737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15522 11:17:02.521183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15523 11:17:02.550707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15524 11:17:02.551117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15526 11:17:02.580565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15527 11:17:02.581015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15529 11:17:02.610188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15531 11:17:02.610722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15532 11:17:02.643466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15533 11:17:02.643900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15535 11:17:02.676364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15537 11:17:02.676749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15538 11:17:02.708053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15539 11:17:02.708354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15541 11:17:02.740645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15542 11:17:02.740985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15544 11:17:02.777500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15545 11:17:02.777917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15547 11:17:02.809956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15548 11:17:02.810354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15550 11:17:02.843190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15551 11:17:02.843655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15553 11:17:02.875241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15555 11:17:02.875863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15556 11:17:02.906959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15558 11:17:02.907575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15559 11:17:02.939104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15560 11:17:02.939550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15562 11:17:02.971451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15563 11:17:02.971855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15565 11:17:03.006509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15566 11:17:03.006927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15568 11:17:03.038699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15569 11:17:03.039116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15571 11:17:03.070855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15572 11:17:03.071154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15574 11:17:03.103168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15576 11:17:03.103474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15577 11:17:03.135058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15578 11:17:03.135346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15580 11:17:03.167065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15581 11:17:03.167434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15583 11:17:03.199278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15584 11:17:03.199620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15586 11:17:03.231931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15587 11:17:03.232269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15589 11:17:03.264789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15590 11:17:03.265133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15592 11:17:03.297371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15594 11:17:03.297815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15595 11:17:03.331216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15596 11:17:03.331676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15598 11:17:03.363525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15599 11:17:03.364006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15601 11:17:03.397528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15602 11:17:03.398080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15604 11:17:03.429545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15605 11:17:03.430088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15607 11:17:03.463842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15609 11:17:03.464392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15610 11:17:03.496699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15611 11:17:03.497148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15613 11:17:03.528369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15615 11:17:03.528836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15616 11:17:03.559504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15617 11:17:03.559975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15619 11:17:03.591210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15620 11:17:03.591658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15622 11:17:03.625510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15623 11:17:03.626012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15625 11:17:03.658734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15627 11:17:03.659367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15628 11:17:03.689769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15629 11:17:03.690229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15631 11:17:03.721301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15633 11:17:03.721925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15634 11:17:03.751887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15635 11:17:03.752376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15637 11:17:03.783865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15639 11:17:03.784512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15640 11:17:03.814962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15641 11:17:03.815420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15643 11:17:03.845510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15644 11:17:03.845934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15646 11:17:03.877704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15647 11:17:03.878089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15649 11:17:03.908786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15650 11:17:03.909143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15652 11:17:03.939496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15654 11:17:03.939944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15655 11:17:03.970219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15657 11:17:03.970676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15658 11:17:04.007038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15659 11:17:04.007446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15661 11:17:04.041864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15662 11:17:04.042201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15664 11:17:04.078836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15665 11:17:04.079146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15667 11:17:04.113055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15669 11:17:04.113374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15670 11:17:04.146932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15671 11:17:04.147337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15673 11:17:04.180097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15675 11:17:04.180590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15676 11:17:04.218421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15677 11:17:04.218989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15679 11:17:04.252446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15680 11:17:04.252878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15682 11:17:04.286821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15683 11:17:04.287128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15685 11:17:04.321515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15686 11:17:04.321811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15688 11:17:04.355911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15690 11:17:04.356553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15691 11:17:04.390107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15693 11:17:04.390545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15694 11:17:04.420955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15695 11:17:04.421286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15697 11:17:04.452760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15699 11:17:04.453086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15700 11:17:04.484433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15702 11:17:04.484753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15703 11:17:04.516064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15704 11:17:04.516524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15706 11:17:04.548513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15708 11:17:04.549067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15709 11:17:04.581161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15710 11:17:04.581615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15712 11:17:04.612697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15713 11:17:04.613152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15715 11:17:04.644907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15716 11:17:04.645307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15718 11:17:04.676345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15719 11:17:04.676695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15721 11:17:04.707221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15722 11:17:04.707567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15724 11:17:04.739122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15726 11:17:04.739571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15727 11:17:04.770940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15728 11:17:04.771314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15730 11:17:04.804152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15731 11:17:04.804504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15733 11:17:04.837165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15734 11:17:04.837573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15736 11:17:04.869340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15737 11:17:04.869751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15739 11:17:04.902566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15741 11:17:04.902943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15742 11:17:04.936232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15744 11:17:04.936720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15745 11:17:04.970749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15747 11:17:04.971207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15748 11:17:05.003976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15749 11:17:05.004371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15751 11:17:05.038058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15753 11:17:05.038614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15754 11:17:05.072065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15756 11:17:05.072590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15757 11:17:05.106893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15758 11:17:05.107255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15760 11:17:05.137152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15762 11:17:05.137621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15763 11:17:05.167346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15764 11:17:05.167739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15766 11:17:05.197711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15767 11:17:05.198099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15769 11:17:05.228043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15770 11:17:05.228466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15772 11:17:05.258377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15773 11:17:05.258764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15775 11:17:05.289505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15776 11:17:05.289954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15778 11:17:05.323093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15779 11:17:05.323481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15781 11:17:05.355347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15782 11:17:05.355726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15784 11:17:05.385656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15785 11:17:05.386087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15787 11:17:05.416434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15789 11:17:05.416889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15790 11:17:05.447043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15791 11:17:05.447560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15793 11:17:05.477643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15794 11:17:05.478061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15796 11:17:05.509176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15797 11:17:05.509522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15799 11:17:05.539358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15801 11:17:05.539733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15802 11:17:05.570568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15803 11:17:05.570974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15805 11:17:05.602213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15807 11:17:05.602769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15808 11:17:05.633067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15809 11:17:05.633542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15811 11:17:05.664030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15812 11:17:05.664536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15814 11:17:05.695446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15815 11:17:05.695899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15817 11:17:05.729309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15818 11:17:05.729789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15820 11:17:05.763403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15821 11:17:05.763862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15823 11:17:05.798357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15825 11:17:05.798962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15826 11:17:05.829632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15828 11:17:05.830188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15829 11:17:05.860976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15831 11:17:05.861430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15832 11:17:05.891711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15833 11:17:05.892141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15835 11:17:05.922959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15837 11:17:05.923449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15838 11:17:05.953146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15839 11:17:05.953463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15841 11:17:05.983862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15842 11:17:05.984275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15844 11:17:06.015823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15845 11:17:06.016187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15847 11:17:06.047790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15848 11:17:06.048150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15850 11:17:06.080227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15851 11:17:06.080650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15853 11:17:06.111952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15854 11:17:06.112362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15856 11:17:06.145504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15857 11:17:06.145978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15859 11:17:06.177840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15861 11:17:06.178562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15862 11:17:06.213785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15863 11:17:06.214206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15865 11:17:06.247882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15866 11:17:06.248298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15868 11:17:06.280556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15869 11:17:06.281005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15871 11:17:06.313439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15873 11:17:06.313871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15874 11:17:06.346096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15876 11:17:06.346561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15877 11:17:06.380561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15879 11:17:06.380993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15880 11:17:06.413766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15881 11:17:06.414194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15883 11:17:06.447811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15885 11:17:06.448265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15886 11:17:06.481704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15887 11:17:06.482145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15889 11:17:06.516413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15890 11:17:06.516805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15892 11:17:06.552637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15893 11:17:06.552973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15895 11:17:06.588026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15897 11:17:06.588491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15898 11:17:06.622136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15900 11:17:06.622609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15901 11:17:06.656780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15902 11:17:06.657194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15904 11:17:06.688288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15906 11:17:06.688809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15907 11:17:06.722462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15909 11:17:06.722884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15910 11:17:06.756703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15911 11:17:06.757194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15913 11:17:06.789260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15914 11:17:06.789751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15916 11:17:06.821412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15918 11:17:06.821976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15919 11:17:06.854574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15920 11:17:06.855032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15922 11:17:06.885211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15924 11:17:06.885842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15925 11:17:06.922479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15926 11:17:06.922948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15928 11:17:06.953414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15930 11:17:06.953875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15931 11:17:06.986903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15933 11:17:06.987461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15934 11:17:07.019406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15936 11:17:07.020039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15937 11:17:07.055053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15939 11:17:07.055693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15940 11:17:07.089670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15941 11:17:07.090189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15943 11:17:07.126742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15944 11:17:07.127242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15946 11:17:07.158705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15947 11:17:07.159081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15949 11:17:07.189676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15950 11:17:07.190068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15952 11:17:07.219668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15953 11:17:07.220134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15955 11:17:07.250422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15956 11:17:07.250881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15958 11:17:07.280277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15960 11:17:07.280818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15961 11:17:07.311099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15962 11:17:07.311577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15964 11:17:07.341138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15965 11:17:07.341611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15967 11:17:07.371263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15968 11:17:07.371722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15970 11:17:07.401529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15972 11:17:07.402093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15973 11:17:07.432775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15975 11:17:07.433323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15976 11:17:07.462982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15977 11:17:07.463433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15979 11:17:07.493315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
15981 11:17:07.493901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15982 11:17:07.524796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
15983 11:17:07.525243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
15985 11:17:07.554826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
15986 11:17:07.555250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
15988 11:17:07.584623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
15990 11:17:07.585043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
15991 11:17:07.614911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
15992 11:17:07.615307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
15994 11:17:07.645160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
15996 11:17:07.645743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
15997 11:17:07.676321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
15999 11:17:07.677042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
16000 11:17:07.706500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
16002 11:17:07.706916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
16003 11:17:07.735798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
16004 11:17:07.736219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
16006 11:17:07.765603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
16007 11:17:07.765888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
16009 11:17:07.795896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
16010 11:17:07.796372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
16012 11:17:07.826402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
16013 11:17:07.826876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
16015 11:17:07.857298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
16016 11:17:07.857775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
16018 11:17:07.888419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
16020 11:17:07.888961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
16021 11:17:07.924464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
16023 11:17:07.924908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
16024 11:17:07.956181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
16026 11:17:07.956737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
16027 11:17:07.987003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
16028 11:17:07.987346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
16030 11:17:08.017295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
16031 11:17:08.017627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
16033 11:17:08.047253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
16034 11:17:08.047592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
16036 11:17:08.077101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
16037 11:17:08.077448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
16039 11:17:08.106896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
16041 11:17:08.107322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
16042 11:17:08.136594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
16044 11:17:08.137042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
16045 11:17:08.167640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
16046 11:17:08.168109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
16048 11:17:08.198524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
16050 11:17:08.199115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
16051 11:17:08.228808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
16052 11:17:08.229217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
16054 11:17:08.258707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
16055 11:17:08.259061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
16057 11:17:08.288302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
16058 11:17:08.288649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
16060 11:17:08.318446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
16061 11:17:08.318893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
16063 11:17:08.349001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
16064 11:17:08.349434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
16066 11:17:08.379405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
16067 11:17:08.379844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
16069 11:17:08.411654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
16070 11:17:08.412008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
16072 11:17:08.442565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
16073 11:17:08.442835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
16075 11:17:08.473433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
16076 11:17:08.473796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
16078 11:17:08.504672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
16079 11:17:08.505083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
16081 11:17:08.535564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
16082 11:17:08.535954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
16084 11:17:08.565709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
16086 11:17:08.566145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
16087 11:17:08.596049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
16089 11:17:08.596471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
16090 11:17:08.627126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
16091 11:17:08.627514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
16093 11:17:08.658544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
16095 11:17:08.659080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
16096 11:17:08.688950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
16097 11:17:08.689411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
16099 11:17:08.719042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
16101 11:17:08.719553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
16102 11:17:08.749503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
16103 11:17:08.749907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
16105 11:17:08.779251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
16106 11:17:08.779649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
16108 11:17:08.811146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
16110 11:17:08.811677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
16111 11:17:08.841051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
16112 11:17:08.841460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
16114 11:17:08.870995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
16115 11:17:08.871426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
16117 11:17:08.901119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
16118 11:17:08.901557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
16120 11:17:08.930920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
16121 11:17:08.931335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
16123 11:17:08.960807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
16124 11:17:08.961229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
16126 11:17:08.990895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
16127 11:17:08.991298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
16129 11:17:09.022622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
16131 11:17:09.023156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
16132 11:17:09.053087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
16134 11:17:09.053657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
16135 11:17:09.083265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
16136 11:17:09.083623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
16138 11:17:09.113716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
16140 11:17:09.114237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
16141 11:17:09.144842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
16142 11:17:09.145246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
16144 11:17:09.175697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
16146 11:17:09.176226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
16147 11:17:09.205900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
16149 11:17:09.206440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
16150 11:17:09.236359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
16151 11:17:09.236809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
16153 11:17:09.266167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
16155 11:17:09.266409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
16156 11:17:09.295478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
16157 11:17:09.295820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
16159 11:17:09.325304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
16161 11:17:09.325867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
16162 11:17:09.354937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
16163 11:17:09.355286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
16165 11:17:09.385352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
16166 11:17:09.385697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
16168 11:17:09.414978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
16169 11:17:09.415323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
16171 11:17:09.444935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
16172 11:17:09.445278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
16174 11:17:09.474774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
16175 11:17:09.475186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
16177 11:17:09.504938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
16178 11:17:09.505384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
16180 11:17:09.536727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
16182 11:17:09.537283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
16183 11:17:09.566772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
16184 11:17:09.567213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
16186 11:17:09.596734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
16188 11:17:09.597287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
16189 11:17:09.626906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
16190 11:17:09.627350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
16192 11:17:09.658432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
16194 11:17:09.658978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
16195 11:17:09.689104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
16196 11:17:09.689466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
16198 11:17:09.719281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
16199 11:17:09.719638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
16201 11:17:09.749779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
16202 11:17:09.750140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
16204 11:17:09.779507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
16206 11:17:09.779919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
16207 11:17:09.809003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
16208 11:17:09.809359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
16210 11:17:09.838616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
16211 11:17:09.839078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
16213 11:17:09.869258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
16214 11:17:09.869652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
16216 11:17:09.901793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
16217 11:17:09.902154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
16219 11:17:09.932668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
16220 11:17:09.933029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
16222 11:17:09.962925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
16223 11:17:09.963176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
16225 11:17:09.993071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16226 11:17:09.993348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16228 11:17:10.023158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16230 11:17:10.023724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16231 11:17:10.055749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16232 11:17:10.056025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16234 11:17:10.087380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16235 11:17:10.087848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16237 11:17:10.117714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16238 11:17:10.118153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16240 11:17:10.148550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16242 11:17:10.149093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16243 11:17:10.179018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16244 11:17:10.179456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16246 11:17:10.209267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16247 11:17:10.209691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16249 11:17:10.239848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16250 11:17:10.240230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16252 11:17:10.269946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16254 11:17:10.270411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16255 11:17:10.301398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16257 11:17:10.301953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16258 11:17:10.333324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16259 11:17:10.333779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16261 11:17:10.363968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16262 11:17:10.364423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16264 11:17:10.395363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16266 11:17:10.395795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16267 11:17:10.425764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16269 11:17:10.426193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16270 11:17:10.455876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16271 11:17:10.456215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16273 11:17:10.486637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16274 11:17:10.487021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16276 11:17:10.517203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16278 11:17:10.517778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16279 11:17:10.547387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16280 11:17:10.547811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16282 11:17:10.578040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16284 11:17:10.578572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16285 11:17:10.608863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16286 11:17:10.609288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16288 11:17:10.640114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16290 11:17:10.640644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16291 11:17:10.670733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16293 11:17:10.671273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16294 11:17:10.700774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16295 11:17:10.701185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16297 11:17:10.730729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16298 11:17:10.731157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16300 11:17:10.760964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16301 11:17:10.761397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16303 11:17:10.792440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16304 11:17:10.792850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16306 11:17:10.823548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16308 11:17:10.824164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16309 11:17:10.853937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16311 11:17:10.854479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16312 11:17:10.884778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16313 11:17:10.885129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16315 11:17:10.915015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16317 11:17:10.915425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16318 11:17:10.944984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16319 11:17:10.945353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16321 11:17:10.975881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16322 11:17:10.976234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16324 11:17:11.006111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16326 11:17:11.006736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16327 11:17:11.036390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16328 11:17:11.036805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16330 11:17:11.067110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16331 11:17:11.067544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16333 11:17:11.097057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16335 11:17:11.097571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16336 11:17:11.127552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16337 11:17:11.128007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16339 11:17:11.157619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16340 11:17:11.157943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16342 11:17:11.188791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16343 11:17:11.189247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16345 11:17:11.219180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16346 11:17:11.219629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16348 11:17:11.249422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16349 11:17:11.249894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16351 11:17:11.280277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16353 11:17:11.280832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16354 11:17:11.311102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16356 11:17:11.311546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16357 11:17:11.341004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16358 11:17:11.341361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16360 11:17:11.371533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16362 11:17:11.371958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16363 11:17:11.402898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16364 11:17:11.403348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16366 11:17:11.434823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16368 11:17:11.435367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16369 11:17:11.468753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16371 11:17:11.469328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16372 11:17:11.499778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16374 11:17:11.500388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16375 11:17:11.531228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16377 11:17:11.531775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16378 11:17:11.568484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16379 11:17:11.568849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16381 11:17:11.598922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16383 11:17:11.599537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16384 11:17:11.629292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16385 11:17:11.629697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16387 11:17:11.660596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16388 11:17:11.660959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16390 11:17:11.691027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16391 11:17:11.691372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16393 11:17:11.721306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16394 11:17:11.721761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16396 11:17:11.752226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16397 11:17:11.752656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16399 11:17:11.782617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16400 11:17:11.782994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16402 11:17:11.812498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16403 11:17:11.812889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16405 11:17:11.842796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16406 11:17:11.843135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16408 11:17:11.872610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16409 11:17:11.872949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16411 11:17:11.902680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16412 11:17:11.903039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16414 11:17:11.932475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16416 11:17:11.932886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16417 11:17:11.962146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16419 11:17:11.962571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16420 11:17:11.992060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16421 11:17:11.992418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16423 11:17:12.022032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16424 11:17:12.022489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16426 11:17:12.053388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16427 11:17:12.053868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16429 11:17:12.084302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16430 11:17:12.084747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16432 11:17:12.114192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16433 11:17:12.114649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16435 11:17:12.144648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16436 11:17:12.145110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16438 11:17:12.175310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16440 11:17:12.175848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16441 11:17:12.206528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16442 11:17:12.206998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16444 11:17:12.236756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16445 11:17:12.237212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16447 11:17:12.267318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16448 11:17:12.267753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16450 11:17:12.297526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16451 11:17:12.297990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16453 11:17:12.328021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16454 11:17:12.328452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16456 11:17:12.358480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16457 11:17:12.358839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16459 11:17:12.388034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16461 11:17:12.388442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16462 11:17:12.418697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16463 11:17:12.419040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16465 11:17:12.448798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16467 11:17:12.449210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16468 11:17:12.478966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16469 11:17:12.479295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16471 11:17:12.509429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16473 11:17:12.509936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16474 11:17:12.539951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16475 11:17:12.540419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16477 11:17:12.571071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16478 11:17:12.571460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16480 11:17:12.602027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16482 11:17:12.602459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16483 11:17:12.632468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16484 11:17:12.632809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16486 11:17:12.663433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16487 11:17:12.663786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16489 11:17:12.693764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16490 11:17:12.694104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16492 11:17:12.723952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16493 11:17:12.724292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16495 11:17:12.754133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16497 11:17:12.754572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16498 11:17:12.783651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16499 11:17:12.783991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16501 11:17:12.813349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16502 11:17:12.813696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16504 11:17:12.843570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16505 11:17:12.843920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16507 11:17:12.874239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16509 11:17:12.874651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16510 11:17:12.904126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16511 11:17:12.904450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16513 11:17:12.933712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16514 11:17:12.934052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16516 11:17:12.963519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16517 11:17:12.963848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16519 11:17:12.993116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16520 11:17:12.993454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16522 11:17:13.024176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16524 11:17:13.024575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16525 11:17:13.054847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16527 11:17:13.055267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16528 11:17:13.084947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16530 11:17:13.085356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16531 11:17:13.115508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16532 11:17:13.115829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16534 11:17:13.145100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16536 11:17:13.145579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16537 11:17:13.175037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16539 11:17:13.175459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16540 11:17:13.204449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16541 11:17:13.204791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16543 11:17:13.234633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16544 11:17:13.234984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16546 11:17:13.264123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16547 11:17:13.264461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16549 11:17:13.293848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16550 11:17:13.294185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16552 11:17:13.324820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16553 11:17:13.325258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16555 11:17:13.354761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16556 11:17:13.355127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16558 11:17:13.384856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16559 11:17:13.385238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16561 11:17:13.415490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16562 11:17:13.415833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16564 11:17:13.444873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16565 11:17:13.445208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16567 11:17:13.475026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16568 11:17:13.475361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16570 11:17:13.504871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16571 11:17:13.505197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16573 11:17:13.535020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16574 11:17:13.535356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16576 11:17:13.566053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16578 11:17:13.566481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16579 11:17:13.597185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16580 11:17:13.597628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16582 11:17:13.627949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16584 11:17:13.628435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16585 11:17:13.657727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16587 11:17:13.658301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16588 11:17:13.689516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16590 11:17:13.690087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16591 11:17:13.720087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16592 11:17:13.720553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16594 11:17:13.750977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16595 11:17:13.751409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16597 11:17:13.782173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16599 11:17:13.782780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16600 11:17:13.813449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16601 11:17:13.813804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16603 11:17:13.844044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16604 11:17:13.844403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16606 11:17:13.875022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16607 11:17:13.875380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16609 11:17:13.905614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16610 11:17:13.906057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16612 11:17:13.936810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16614 11:17:13.937273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16615 11:17:13.967650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16616 11:17:13.967991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16618 11:17:13.999410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16619 11:17:13.999761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16621 11:17:14.030790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16623 11:17:14.031330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16624 11:17:14.063977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16625 11:17:14.064354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16627 11:17:14.096389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16628 11:17:14.096756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16630 11:17:14.129081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16631 11:17:14.129452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16633 11:17:14.163062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16635 11:17:14.163612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16636 11:17:14.195358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16637 11:17:14.195786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16639 11:17:14.229257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16641 11:17:14.229851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16642 11:17:14.267021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16643 11:17:14.267459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16645 11:17:14.304723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16646 11:17:14.305142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16648 11:17:14.338929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16650 11:17:14.339454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16651 11:17:14.369931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16653 11:17:14.370344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16654 11:17:14.400764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16655 11:17:14.401106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16657 11:17:14.431908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16658 11:17:14.432257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16660 11:17:14.462482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16661 11:17:14.462927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16663 11:17:14.492903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16664 11:17:14.493349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16666 11:17:14.523390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16667 11:17:14.523823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16669 11:17:14.554391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16670 11:17:14.554811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16672 11:17:14.584906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16674 11:17:14.585443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16675 11:17:14.615128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16676 11:17:14.615568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16678 11:17:14.646234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16680 11:17:14.646779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16681 11:17:14.676852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16682 11:17:14.677289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16684 11:17:14.707295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16685 11:17:14.707760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16687 11:17:14.737498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16688 11:17:14.737857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16690 11:17:14.767488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16691 11:17:14.767941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16693 11:17:14.798222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16695 11:17:14.798747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16696 11:17:14.829094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16697 11:17:14.829533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16699 11:17:14.859525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16700 11:17:14.859967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16702 11:17:14.890890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16704 11:17:14.891519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16705 11:17:14.921880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16707 11:17:14.922426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16708 11:17:14.952506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16709 11:17:14.952975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16711 11:17:14.983925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16712 11:17:14.984410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16714 11:17:15.015522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16715 11:17:15.015962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16717 11:17:15.046229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16719 11:17:15.046787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16720 11:17:15.076675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16722 11:17:15.077244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16723 11:17:15.112438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16725 11:17:15.113003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16726 11:17:15.144635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16727 11:17:15.145072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16729 11:17:15.176116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16731 11:17:15.176560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16732 11:17:15.206908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16733 11:17:15.207304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16735 11:17:15.237533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16736 11:17:15.237996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16738 11:17:15.268650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16739 11:17:15.269087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16741 11:17:15.299796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16743 11:17:15.300404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16744 11:17:15.330862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16745 11:17:15.331228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16747 11:17:15.361125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16748 11:17:15.361484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16750 11:17:15.391126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16751 11:17:15.391470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16753 11:17:15.422727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16755 11:17:15.423032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16756 11:17:15.452452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16757 11:17:15.452813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16759 11:17:15.484708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16761 11:17:15.485104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16762 11:17:15.515226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16764 11:17:15.515502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16765 11:17:15.545401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16766 11:17:15.545676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16768 11:17:15.576516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16770 11:17:15.577017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16771 11:17:15.608860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16773 11:17:15.609393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16774 11:17:15.640490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16775 11:17:15.640882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16777 11:17:15.672239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16778 11:17:15.672639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16780 11:17:15.703997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16781 11:17:15.704423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16783 11:17:15.737346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16784 11:17:15.737810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16786 11:17:15.771636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16787 11:17:15.772083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16789 11:17:15.803715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16790 11:17:15.804096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16792 11:17:15.835016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16794 11:17:15.835609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16795 11:17:15.866249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16797 11:17:15.866847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16798 11:17:15.899073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16799 11:17:15.899542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16801 11:17:15.929576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16802 11:17:15.929987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16804 11:17:15.959835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16806 11:17:15.960256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16807 11:17:15.990759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16808 11:17:15.991153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16810 11:17:16.021842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16812 11:17:16.022288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16813 11:17:16.053047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16815 11:17:16.053480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16816 11:17:16.084018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16818 11:17:16.084636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16819 11:17:16.113962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16820 11:17:16.114398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16822 11:17:16.143824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16823 11:17:16.144169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16825 11:17:16.173873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16826 11:17:16.174239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16828 11:17:16.204209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16829 11:17:16.204484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16831 11:17:16.235124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16833 11:17:16.235618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16834 11:17:16.265411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16835 11:17:16.265781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16837 11:17:16.295574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16838 11:17:16.295848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16840 11:17:16.326826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16841 11:17:16.327159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16843 11:17:16.360360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16844 11:17:16.360751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16846 11:17:16.392173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16847 11:17:16.392564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16849 11:17:16.423065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16851 11:17:16.423581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16852 11:17:16.456906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16853 11:17:16.457355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16855 11:17:16.487578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16856 11:17:16.487939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16858 11:17:16.518520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16859 11:17:16.518883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16861 11:17:16.548801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16862 11:17:16.549182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16864 11:17:16.581122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16865 11:17:16.581514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16867 11:17:16.611837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16868 11:17:16.612199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16870 11:17:16.642671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16872 11:17:16.642979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16873 11:17:16.673178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16874 11:17:16.673464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16876 11:17:16.703170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16877 11:17:16.703448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16879 11:17:16.733424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16880 11:17:16.733671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16882 11:17:16.803377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16884 11:17:16.803798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16885 11:17:16.869163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16886 11:17:16.869578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16888 11:17:16.910801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16889 11:17:16.911279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16891 11:17:16.943830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16892 11:17:16.944199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16894 11:17:16.976429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16896 11:17:16.976971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16897 11:17:17.023255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16898 11:17:17.023623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16900 11:17:17.071015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16902 11:17:17.071531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16903 11:17:17.102463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16904 11:17:17.102753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16906 11:17:17.133632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16907 11:17:17.134007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16909 11:17:17.164371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16910 11:17:17.164721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16912 11:17:17.198682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16914 11:17:17.199135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16915 11:17:17.228753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16917 11:17:17.229186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16918 11:17:17.259713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16919 11:17:17.260069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16921 11:17:17.290814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16922 11:17:17.291160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16924 11:17:17.321423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16926 11:17:17.321886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16927 11:17:17.351299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16928 11:17:17.351588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16930 11:17:17.382032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16932 11:17:17.382479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16933 11:17:17.415015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16934 11:17:17.415451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16936 11:17:17.447125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16937 11:17:17.447482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16939 11:17:17.478863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16940 11:17:17.479211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16942 11:17:17.509505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16943 11:17:17.509863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16945 11:17:17.540052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16947 11:17:17.540485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16948 11:17:17.570713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16949 11:17:17.571058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16951 11:17:17.601311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16953 11:17:17.601738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16954 11:17:17.632641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16955 11:17:17.633034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16957 11:17:17.664426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16958 11:17:17.664927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16960 11:17:17.695675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16962 11:17:17.696284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16963 11:17:17.726266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16965 11:17:17.726882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16966 11:17:17.756894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16967 11:17:17.757348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16969 11:17:17.788948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16970 11:17:17.789402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16972 11:17:17.822115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16974 11:17:17.822681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16975 11:17:17.853538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16976 11:17:17.853999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16978 11:17:17.884069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16979 11:17:17.884508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
16981 11:17:17.914822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
16982 11:17:17.915282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
16984 11:17:17.946904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
16986 11:17:17.947433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
16987 11:17:17.980153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
16989 11:17:17.980700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
16990 11:17:18.012772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
16991 11:17:18.013175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
16993 11:17:18.043491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
16995 11:17:18.044047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
16996 11:17:18.073331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
16997 11:17:18.073688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
16999 11:17:18.104305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
17000 11:17:18.104632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
17002 11:17:18.137641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
17003 11:17:18.138030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
17005 11:17:18.171235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
17006 11:17:18.171592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
17008 11:17:18.201658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
17010 11:17:18.202150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
17011 11:17:18.231655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
17012 11:17:18.232022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
17014 11:17:18.262103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
17016 11:17:18.262610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
17017 11:17:18.292181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
17018 11:17:18.292541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
17020 11:17:18.325084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
17022 11:17:18.325523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
17023 11:17:18.358497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
17024 11:17:18.358865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
17026 11:17:18.388353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
17027 11:17:18.388704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
17029 11:17:18.418937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
17030 11:17:18.419296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
17032 11:17:18.449360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
17034 11:17:18.449913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
17035 11:17:18.479776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
17037 11:17:18.480284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
17038 11:17:18.514391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
17039 11:17:18.514758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
17041 11:17:18.545917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
17043 11:17:18.546468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
17044 11:17:18.577333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
17046 11:17:18.577881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
17047 11:17:18.607718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
17048 11:17:18.608139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
17050 11:17:18.643185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
17051 11:17:18.643576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
17053 11:17:18.675383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
17055 11:17:18.675943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
17056 11:17:18.707908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
17058 11:17:18.708409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
17059 11:17:18.738861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
17060 11:17:18.739168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
17062 11:17:18.769845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
17063 11:17:18.770137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
17065 11:17:18.801586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
17066 11:17:18.801957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
17068 11:17:18.832518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
17070 11:17:18.833003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
17071 11:17:18.864837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
17073 11:17:18.865260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
17074 11:17:18.896547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
17075 11:17:18.896899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
17077 11:17:18.927709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
17078 11:17:18.928052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
17080 11:17:18.959834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
17082 11:17:18.960244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
17083 11:17:18.990569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
17084 11:17:18.990916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
17086 11:17:19.021147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
17087 11:17:19.021584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
17089 11:17:19.063674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
17090 11:17:19.064130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
17092 11:17:19.112902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
17093 11:17:19.113374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
17095 11:17:19.164209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
17096 11:17:19.164618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
17098 11:17:19.201149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
17099 11:17:19.201517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
17101 11:17:19.236526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
17103 11:17:19.237119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
17104 11:17:19.267312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
17106 11:17:19.267900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
17107 11:17:19.298963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
17108 11:17:19.299409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
17110 11:17:19.329602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
17111 11:17:19.330084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
17113 11:17:19.361402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
17114 11:17:19.361871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
17116 11:17:19.394239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
17118 11:17:19.394846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
17119 11:17:19.428754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
17120 11:17:19.429219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
17122 11:17:19.459579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
17123 11:17:19.460042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
17125 11:17:19.489766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
17126 11:17:19.490119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
17128 11:17:19.520492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
17130 11:17:19.521025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
17131 11:17:19.552670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
17132 11:17:19.553030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
17134 11:17:19.587062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
17135 11:17:19.587497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
17137 11:17:19.617846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
17138 11:17:19.618257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
17140 11:17:19.648060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
17142 11:17:19.648351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
17143 11:17:19.678474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
17145 11:17:19.678915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
17146 11:17:19.709093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
17148 11:17:19.709761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
17149 11:17:19.741428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
17151 11:17:19.742100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
17152 11:17:19.773528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
17153 11:17:19.774015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
17155 11:17:19.804620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
17156 11:17:19.805093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
17158 11:17:19.834949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
17159 11:17:19.835392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
17161 11:17:19.865728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
17162 11:17:19.866186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
17164 11:17:19.897189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
17165 11:17:19.897673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
17167 11:17:19.935359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
17169 11:17:19.935714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
17170 11:17:19.970154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
17172 11:17:19.970463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
17173 11:17:20.000236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
17174 11:17:20.000491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
17176 11:17:20.032545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
17177 11:17:20.032903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
17179 11:17:20.064999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
17180 11:17:20.065496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
17182 11:17:20.095983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
17183 11:17:20.096349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
17185 11:17:20.126626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
17186 11:17:20.126895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
17188 11:17:20.156572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
17190 11:17:20.157009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
17191 11:17:20.186740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
17192 11:17:20.187101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
17194 11:17:20.217412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
17195 11:17:20.217747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
17197 11:17:20.247559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
17198 11:17:20.247915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
17200 11:17:20.280087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
17201 11:17:20.280436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
17203 11:17:20.310695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
17204 11:17:20.311034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
17206 11:17:20.340751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
17207 11:17:20.341092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
17209 11:17:20.371202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
17210 11:17:20.371551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
17212 11:17:20.400970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
17214 11:17:20.401456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
17215 11:17:20.431808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
17216 11:17:20.432162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
17218 11:17:20.462956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
17219 11:17:20.463300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
17221 11:17:20.493132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
17222 11:17:20.493605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
17224 11:17:20.523752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
17225 11:17:20.524107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17227 11:17:20.554213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17229 11:17:20.554679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17230 11:17:20.586062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17232 11:17:20.586441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17233 11:17:20.620766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17234 11:17:20.621237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17236 11:17:20.651468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17238 11:17:20.651967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17239 11:17:20.681271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17240 11:17:20.681631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17242 11:17:20.711592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17243 11:17:20.712022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17245 11:17:20.741783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17246 11:17:20.742139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17248 11:17:20.772213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17249 11:17:20.772623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17251 11:17:20.803306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17252 11:17:20.803772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17254 11:17:20.833897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17255 11:17:20.834350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17257 11:17:20.864030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17258 11:17:20.864475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17260 11:17:20.893811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17261 11:17:20.894249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17263 11:17:20.924124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17264 11:17:20.924604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17266 11:17:20.956672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17267 11:17:20.957189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17269 11:17:20.988484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17270 11:17:20.988928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17272 11:17:21.020222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17274 11:17:21.020785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17275 11:17:21.051277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17276 11:17:21.051677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17278 11:17:21.082174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17280 11:17:21.082704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17281 11:17:21.113204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17282 11:17:21.113658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17284 11:17:21.144981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17286 11:17:21.145506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17287 11:17:21.176390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17288 11:17:21.176846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17290 11:17:21.207847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17291 11:17:21.208288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17293 11:17:21.239925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17294 11:17:21.240395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17296 11:17:21.272273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17297 11:17:21.272708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17299 11:17:21.305041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17301 11:17:21.305488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17302 11:17:21.337575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17304 11:17:21.338203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17305 11:17:21.368246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17306 11:17:21.368702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17308 11:17:21.398164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17310 11:17:21.398747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17311 11:17:21.428387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17313 11:17:21.428988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17314 11:17:21.458627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17315 11:17:21.459089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17317 11:17:21.489319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17318 11:17:21.489780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17320 11:17:21.520790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17321 11:17:21.521254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17323 11:17:21.552234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17324 11:17:21.552728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17326 11:17:21.584431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17327 11:17:21.584899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17329 11:17:21.615643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17330 11:17:21.616119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17332 11:17:21.646577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17334 11:17:21.647145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17335 11:17:21.679280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17336 11:17:21.679753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17338 11:17:21.715324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17340 11:17:21.715857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17341 11:17:21.745562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17343 11:17:21.746063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17344 11:17:21.776147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17345 11:17:21.776699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17347 11:17:21.806162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17349 11:17:21.806608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17350 11:17:21.837254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17351 11:17:21.837684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17353 11:17:21.868428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17354 11:17:21.868844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17356 11:17:21.899207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17357 11:17:21.899607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17359 11:17:21.930025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17361 11:17:21.930652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17362 11:17:21.960286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17363 11:17:21.960751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17365 11:17:21.991159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17367 11:17:21.991878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17368 11:17:22.024032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17369 11:17:22.024485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17371 11:17:22.055160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17372 11:17:22.055598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17374 11:17:22.086144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17376 11:17:22.086591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17377 11:17:22.118818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17378 11:17:22.119223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17380 11:17:22.150640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17381 11:17:22.151063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17383 11:17:22.183676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17384 11:17:22.184078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17386 11:17:22.215816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17388 11:17:22.216250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17389 11:17:22.245967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17391 11:17:22.246409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17392 11:17:22.276598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17394 11:17:22.277035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17395 11:17:22.307031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17396 11:17:22.307430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17398 11:17:22.337312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17399 11:17:22.337680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17401 11:17:22.368562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17402 11:17:22.369020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17404 11:17:22.399599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17406 11:17:22.400092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17407 11:17:22.429185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17408 11:17:22.429531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17410 11:17:22.458825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17412 11:17:22.459375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17413 11:17:22.488483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17414 11:17:22.488903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17416 11:17:22.519547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17417 11:17:22.519986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17419 11:17:22.550680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17420 11:17:22.551207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17422 11:17:22.581278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17423 11:17:22.581688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17425 11:17:22.611751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17426 11:17:22.612186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17428 11:17:22.641672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17429 11:17:22.642133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17431 11:17:22.672269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17432 11:17:22.672707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17434 11:17:22.702870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17435 11:17:22.703305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17437 11:17:22.733813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17438 11:17:22.734186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17440 11:17:22.768647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17441 11:17:22.769100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17443 11:17:22.798531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17444 11:17:22.798874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17446 11:17:22.828211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17447 11:17:22.828664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17449 11:17:22.858198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17451 11:17:22.858727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17452 11:17:22.888956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17454 11:17:22.889569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17455 11:17:22.919963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17456 11:17:22.920412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17458 11:17:22.950085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17460 11:17:22.950524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17461 11:17:22.980319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17462 11:17:22.980712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17464 11:17:23.011294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17465 11:17:23.011675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17467 11:17:23.041251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17469 11:17:23.041693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17470 11:17:23.073496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17471 11:17:23.073855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17473 11:17:23.106498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17474 11:17:23.106840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17476 11:17:23.136057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17477 11:17:23.136398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17479 11:17:23.165496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17481 11:17:23.165918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17482 11:17:23.196512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17483 11:17:23.196845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17485 11:17:23.228268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17486 11:17:23.228586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17488 11:17:23.261435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17489 11:17:23.261780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17491 11:17:23.292248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17492 11:17:23.292563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17494 11:17:23.322288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17495 11:17:23.322601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17497 11:17:23.356361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17498 11:17:23.356703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17500 11:17:23.389540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17501 11:17:23.389884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17503 11:17:23.428046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17504 11:17:23.428450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17506 11:17:23.460703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17507 11:17:23.461124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17509 11:17:23.491702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17510 11:17:23.492102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17512 11:17:23.523072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17513 11:17:23.523494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17515 11:17:23.553809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17517 11:17:23.554424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17518 11:17:23.586534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17519 11:17:23.587017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17521 11:17:23.617422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17522 11:17:23.617886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17524 11:17:23.647914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17525 11:17:23.648318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17527 11:17:23.679185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17528 11:17:23.679654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17530 11:17:23.709252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17531 11:17:23.709700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17533 11:17:23.739385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17534 11:17:23.739851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17536 11:17:23.770067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17538 11:17:23.770680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17539 11:17:23.800797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17540 11:17:23.801259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17542 11:17:23.831080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17543 11:17:23.831531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17545 11:17:23.861297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17546 11:17:23.861744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17548 11:17:23.891983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17550 11:17:23.892507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17551 11:17:23.922728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17552 11:17:23.923167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17554 11:17:23.952587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17555 11:17:23.953016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17557 11:17:23.983117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17559 11:17:23.983632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17560 11:17:24.015127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17562 11:17:24.015658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17563 11:17:24.045153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17564 11:17:24.045582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17566 11:17:24.075686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17568 11:17:24.076205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17569 11:17:24.105718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17570 11:17:24.106151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17572 11:17:24.135931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17573 11:17:24.136387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17575 11:17:24.167002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17576 11:17:24.167428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17578 11:17:24.197095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17579 11:17:24.197543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17581 11:17:24.227149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17583 11:17:24.227660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17584 11:17:24.257132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17586 11:17:24.257726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17587 11:17:24.287191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17588 11:17:24.287582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17590 11:17:24.317487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17592 11:17:24.317931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17593 11:17:24.347463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17594 11:17:24.347870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17596 11:17:24.377706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17598 11:17:24.378149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17599 11:17:24.407952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17600 11:17:24.408400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17602 11:17:24.437830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17603 11:17:24.438261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17605 11:17:24.468135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17606 11:17:24.468568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17608 11:17:24.499098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17610 11:17:24.499648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17611 11:17:24.528884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17613 11:17:24.529300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17614 11:17:24.558794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17615 11:17:24.559257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17617 11:17:24.588626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17619 11:17:24.589217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17620 11:17:24.618653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17622 11:17:24.619234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17623 11:17:24.648547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17624 11:17:24.648983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17626 11:17:24.678853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17627 11:17:24.679280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17629 11:17:24.708535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17630 11:17:24.708956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17632 11:17:24.739035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17633 11:17:24.739495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17635 11:17:24.768951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17636 11:17:24.769398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17638 11:17:24.798786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17639 11:17:24.799232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17641 11:17:24.829023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17643 11:17:24.829621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17644 11:17:24.859059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17646 11:17:24.859598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17647 11:17:24.888888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17648 11:17:24.889297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17650 11:17:24.918377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17652 11:17:24.918810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17653 11:17:24.947868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17654 11:17:24.948223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17656 11:17:24.978774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17658 11:17:24.979398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17659 11:17:25.011349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17660 11:17:25.011810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17662 11:17:25.042123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17664 11:17:25.042614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17665 11:17:25.071686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17667 11:17:25.072136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17668 11:17:25.102016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17670 11:17:25.102464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17671 11:17:25.132415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17672 11:17:25.132861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17674 11:17:25.163243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17675 11:17:25.163670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17677 11:17:25.193780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17678 11:17:25.194229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17680 11:17:25.223542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17681 11:17:25.224001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17683 11:17:25.253845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17684 11:17:25.254302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17686 11:17:25.284145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17687 11:17:25.284603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17689 11:17:25.314642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17691 11:17:25.315194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17692 11:17:25.344724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17693 11:17:25.345170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17695 11:17:25.374916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17696 11:17:25.375257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17698 11:17:25.405285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17699 11:17:25.405626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17701 11:17:25.435442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17702 11:17:25.435792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17704 11:17:25.465578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17706 11:17:25.466193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17707 11:17:25.495796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17708 11:17:25.496190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17710 11:17:25.525536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17711 11:17:25.525918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17713 11:17:25.555949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17715 11:17:25.556498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17716 11:17:25.585871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17718 11:17:25.586325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17719 11:17:25.615675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17720 11:17:25.616012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17722 11:17:25.645607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17723 11:17:25.646037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17725 11:17:25.675919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17726 11:17:25.676317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17728 11:17:25.706753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17729 11:17:25.707145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17731 11:17:25.736978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17733 11:17:25.737438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17734 11:17:25.766783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17736 11:17:25.767172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17737 11:17:25.795971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17738 11:17:25.796314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17740 11:17:25.825386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17742 11:17:25.825810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17743 11:17:25.855472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17744 11:17:25.855815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17746 11:17:25.885446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17747 11:17:25.885868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17749 11:17:25.916244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17751 11:17:25.916672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17752 11:17:25.946853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17753 11:17:25.947289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17755 11:17:25.976969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17756 11:17:25.977427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17758 11:17:26.006895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17760 11:17:26.007354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17761 11:17:26.036729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17762 11:17:26.037086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17764 11:17:26.066794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17765 11:17:26.067182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17767 11:17:26.096891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17769 11:17:26.097421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17770 11:17:26.127244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17771 11:17:26.127693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17773 11:17:26.157258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17775 11:17:26.157822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17776 11:17:26.187419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17777 11:17:26.187868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17779 11:17:26.218389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17780 11:17:26.218840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17782 11:17:26.248933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17784 11:17:26.249454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17785 11:17:26.279185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17787 11:17:26.279657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17788 11:17:26.308724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17790 11:17:26.309138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17791 11:17:26.338811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17793 11:17:26.339222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17794 11:17:26.368436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17795 11:17:26.368773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17797 11:17:26.398421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17798 11:17:26.398778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17800 11:17:26.428902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17801 11:17:26.429241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17803 11:17:26.458934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17804 11:17:26.459272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17806 11:17:26.489717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17807 11:17:26.490152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17809 11:17:26.519765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17810 11:17:26.520098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17812 11:17:26.549564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17813 11:17:26.549926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17815 11:17:26.579556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17817 11:17:26.579957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17818 11:17:26.609490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17819 11:17:26.609856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17821 11:17:26.639276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17822 11:17:26.639642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17824 11:17:26.669495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17826 11:17:26.669998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17827 11:17:26.699087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17828 11:17:26.699456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17830 11:17:26.728982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17831 11:17:26.729442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17833 11:17:26.759187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17834 11:17:26.759617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17836 11:17:26.788872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17838 11:17:26.789391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17839 11:17:26.819100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17841 11:17:26.819648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17842 11:17:26.849446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17843 11:17:26.849915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17845 11:17:26.879469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17846 11:17:26.879924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17848 11:17:26.910888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17849 11:17:26.911335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17851 11:17:26.941121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17852 11:17:26.941576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17854 11:17:26.971641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17855 11:17:26.972075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17857 11:17:27.001719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17859 11:17:27.002268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17860 11:17:27.031266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17861 11:17:27.031710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17863 11:17:27.061455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17865 11:17:27.061985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17866 11:17:27.092045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17867 11:17:27.092486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17869 11:17:27.122455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17870 11:17:27.122864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17872 11:17:27.152165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17873 11:17:27.152561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17875 11:17:27.181692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17876 11:17:27.182032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17878 11:17:27.211324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17879 11:17:27.211677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17881 11:17:27.241173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17882 11:17:27.241517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17884 11:17:27.270861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17885 11:17:27.271212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17887 11:17:27.300496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17888 11:17:27.300945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17890 11:17:27.331509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17891 11:17:27.331963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17893 11:17:27.361737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17894 11:17:27.362187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17896 11:17:27.392496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17897 11:17:27.392958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17899 11:17:27.427040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17900 11:17:27.427481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17902 11:17:27.457479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17903 11:17:27.457930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17905 11:17:27.488278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17906 11:17:27.488671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17908 11:17:27.519265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17909 11:17:27.519664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17911 11:17:27.550564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17912 11:17:27.551005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17914 11:17:27.580613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17915 11:17:27.580966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17917 11:17:27.610758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17918 11:17:27.611120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17920 11:17:27.641312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17922 11:17:27.641802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17923 11:17:27.671261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17924 11:17:27.671615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17926 11:17:27.701265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17927 11:17:27.701618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17929 11:17:27.731625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17930 11:17:27.731974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17932 11:17:27.761438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17933 11:17:27.761787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17935 11:17:27.791972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17936 11:17:27.792326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17938 11:17:27.822503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17939 11:17:27.822974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17941 11:17:27.853071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17942 11:17:27.853514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17944 11:17:27.883818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17946 11:17:27.884362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17947 11:17:27.914060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17949 11:17:27.914512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17950 11:17:27.944502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17951 11:17:27.944835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17953 11:17:27.975006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17954 11:17:27.975341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17956 11:17:28.005396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17957 11:17:28.005745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17959 11:17:28.035840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17960 11:17:28.036263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17962 11:17:28.066816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17963 11:17:28.067264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17965 11:17:28.097021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17966 11:17:28.097462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17968 11:17:28.127126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17970 11:17:28.127648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17971 11:17:28.157452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17972 11:17:28.157926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17974 11:17:28.188524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17975 11:17:28.188966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17977 11:17:28.218700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17978 11:17:28.219086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17980 11:17:28.249016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
17981 11:17:28.249435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
17983 11:17:28.279630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
17984 11:17:28.280020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
17986 11:17:28.310184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
17988 11:17:28.310611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
17989 11:17:28.340875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
17991 11:17:28.341297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
17992 11:17:28.371894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
17993 11:17:28.372294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
17995 11:17:28.402635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
17996 11:17:28.403023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
17998 11:17:28.433137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
17999 11:17:28.433577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
18001 11:17:28.464311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
18003 11:17:28.464926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
18004 11:17:28.494698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
18005 11:17:28.495087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
18007 11:17:28.525364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
18008 11:17:28.525802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
18010 11:17:28.555959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
18011 11:17:28.556397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
18013 11:17:28.586605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
18014 11:17:28.586992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
18016 11:17:28.617194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
18018 11:17:28.617717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
18019 11:17:28.647921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
18020 11:17:28.648352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
18022 11:17:28.678146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
18024 11:17:28.678558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
18025 11:17:28.708110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
18026 11:17:28.708455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
18028 11:17:28.738367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
18029 11:17:28.738707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
18031 11:17:28.768121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
18032 11:17:28.768468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
18034 11:17:28.798670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
18035 11:17:28.799006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
18037 11:17:28.829062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
18038 11:17:28.829405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
18040 11:17:28.860013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
18041 11:17:28.860350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
18043 11:17:28.890897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
18044 11:17:28.891228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
18046 11:17:28.921162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
18047 11:17:28.921498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
18049 11:17:28.953284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
18051 11:17:28.953850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
18052 11:17:28.984477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
18053 11:17:28.984892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
18055 11:17:29.014969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
18056 11:17:29.015426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
18058 11:17:29.046218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
18060 11:17:29.046767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
18061 11:17:29.077913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
18063 11:17:29.078456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
18064 11:17:29.108194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
18065 11:17:29.108642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
18067 11:17:29.139620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
18068 11:17:29.140059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
18070 11:17:29.171084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
18072 11:17:29.171604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
18073 11:17:29.202847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
18074 11:17:29.203315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
18076 11:17:29.233693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
18077 11:17:29.234005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
18079 11:17:29.265717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
18080 11:17:29.266084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
18082 11:17:29.296183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
18083 11:17:29.296511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
18085 11:17:29.327053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
18086 11:17:29.327501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
18088 11:17:29.359069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
18090 11:17:29.359628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
18091 11:17:29.389531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
18092 11:17:29.389974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
18094 11:17:29.420044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
18095 11:17:29.420492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
18097 11:17:29.450356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
18098 11:17:29.450722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
18100 11:17:29.480213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
18102 11:17:29.480682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
18103 11:17:29.511016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
18104 11:17:29.511368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
18106 11:17:29.541533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
18107 11:17:29.541891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
18109 11:17:29.571518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
18110 11:17:29.571869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
18112 11:17:29.602634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
18114 11:17:29.603106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
18115 11:17:29.632648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
18116 11:17:29.633004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
18118 11:17:29.662932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
18119 11:17:29.663283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
18121 11:17:29.693045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
18122 11:17:29.693511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
18124 11:17:29.723140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
18125 11:17:29.723512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
18127 11:17:29.753160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
18128 11:17:29.753517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
18130 11:17:29.783295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
18131 11:17:29.783651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
18133 11:17:29.813578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
18134 11:17:29.814058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
18136 11:17:29.844842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
18138 11:17:29.845456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
18139 11:17:29.875513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
18140 11:17:29.875974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
18142 11:17:29.905944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
18144 11:17:29.906499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
18145 11:17:29.936742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
18146 11:17:29.937186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
18148 11:17:29.967113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
18149 11:17:29.967540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
18151 11:17:29.997599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
18152 11:17:29.998064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
18154 11:17:30.032801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
18156 11:17:30.033314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
18157 11:17:30.063029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
18158 11:17:30.063365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
18160 11:17:30.092860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
18162 11:17:30.093277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
18163 11:17:30.122992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
18164 11:17:30.123327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
18166 11:17:30.152625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
18167 11:17:30.152960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
18169 11:17:30.182801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
18170 11:17:30.183130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
18172 11:17:30.212124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
18173 11:17:30.212457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
18175 11:17:30.242608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
18176 11:17:30.242941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
18178 11:17:30.272127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
18179 11:17:30.272459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
18181 11:17:30.302228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
18183 11:17:30.302667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
18184 11:17:30.332571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
18186 11:17:30.332975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
18187 11:17:30.362638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
18188 11:17:30.362975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
18190 11:17:30.391956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
18191 11:17:30.392287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
18193 11:17:30.421692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
18194 11:17:30.422024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
18196 11:17:30.451585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
18198 11:17:30.451980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
18199 11:17:30.481534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
18200 11:17:30.481896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
18202 11:17:30.511661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
18203 11:17:30.512011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
18205 11:17:30.541598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
18206 11:17:30.541975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
18208 11:17:30.571765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
18209 11:17:30.572121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
18211 11:17:30.601643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
18212 11:17:30.602137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
18214 11:17:30.631931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
18215 11:17:30.632401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
18217 11:17:30.662230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
18219 11:17:30.662791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
18220 11:17:30.691973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
18221 11:17:30.692439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
18223 11:17:30.721597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18224 11:17:30.722108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
18226 11:17:30.751430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18227 11:17:30.751891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18229 11:17:30.781319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18230 11:17:30.781783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18232 11:17:30.814866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18234 11:17:30.815432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18235 11:17:30.845277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18236 11:17:30.845693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18238 11:17:30.875284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18239 11:17:30.875712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18241 11:17:30.905180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18242 11:17:30.905599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18244 11:17:30.935114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18245 11:17:30.935532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18247 11:17:30.965631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18249 11:17:30.966313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18250 11:17:30.996764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18252 11:17:30.997180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18253 11:17:31.026787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18254 11:17:31.027129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18256 11:17:31.056742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18258 11:17:31.057264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18259 11:17:31.086779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18261 11:17:31.087191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18262 11:17:31.116535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18264 11:17:31.116958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18265 11:17:31.147070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18266 11:17:31.147495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18268 11:17:31.177747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18269 11:17:31.178072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18271 11:17:31.207581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18272 11:17:31.207978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18274 11:17:31.237810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18275 11:17:31.238211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18277 11:17:31.267857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18278 11:17:31.268217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18280 11:17:31.298735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18282 11:17:31.299206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18283 11:17:31.328973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18284 11:17:31.329428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18286 11:17:31.359812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18287 11:17:31.360281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18289 11:17:31.390697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18291 11:17:31.391146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18292 11:17:31.421468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18293 11:17:31.421965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18295 11:17:31.452287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18297 11:17:31.452813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18298 11:17:31.482990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18300 11:17:31.483519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18301 11:17:31.513406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18302 11:17:31.513858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18304 11:17:31.544460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18306 11:17:31.544980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18307 11:17:31.574722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18309 11:17:31.575241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18310 11:17:31.604670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18311 11:17:31.605094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18313 11:17:31.635030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18314 11:17:31.635460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18316 11:17:31.665350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18318 11:17:31.665894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18319 11:17:31.697274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18320 11:17:31.697677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18322 11:17:31.727987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18323 11:17:31.728436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18325 11:17:31.758594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18326 11:17:31.758933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18328 11:17:31.788866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18329 11:17:31.789189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18331 11:17:31.819178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18333 11:17:31.819748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18334 11:17:31.849659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18335 11:17:31.850089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18337 11:17:31.880020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18339 11:17:31.880557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18340 11:17:31.910191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18342 11:17:31.910703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18343 11:17:31.940263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18344 11:17:31.940696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18346 11:17:31.971505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18347 11:17:31.971956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18349 11:17:32.002402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18350 11:17:32.002863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18352 11:17:32.031930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18353 11:17:32.032311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18355 11:17:32.061917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18356 11:17:32.062373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18358 11:17:32.091622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18359 11:17:32.092034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18361 11:17:32.121523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18362 11:17:32.121970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18364 11:17:32.151562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18365 11:17:32.151994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18367 11:17:32.182074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18369 11:17:32.182543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18370 11:17:32.211894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18371 11:17:32.212238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18373 11:17:32.241554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18374 11:17:32.241931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18376 11:17:32.272119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18377 11:17:32.272458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18379 11:17:32.302032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18381 11:17:32.302460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18382 11:17:32.332546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18383 11:17:32.332887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18385 11:17:32.363120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18386 11:17:32.363439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18388 11:17:32.395358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18390 11:17:32.395806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18391 11:17:32.426888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18393 11:17:32.427311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18394 11:17:32.458224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18396 11:17:32.458672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18397 11:17:32.493161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18398 11:17:32.493619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18400 11:17:32.524904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18402 11:17:32.525464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18403 11:17:32.555583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18404 11:17:32.555987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18406 11:17:32.586889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18408 11:17:32.587317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18409 11:17:32.618842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18411 11:17:32.619278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18412 11:17:32.650821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18414 11:17:32.651374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18415 11:17:32.681426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18416 11:17:32.681848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18418 11:17:32.712641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18419 11:17:32.713067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18421 11:17:32.743212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18422 11:17:32.743608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18424 11:17:32.774585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18425 11:17:32.774995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18427 11:17:32.805701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18428 11:17:32.806120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18430 11:17:32.836664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18431 11:17:32.837044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18433 11:17:32.867845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18434 11:17:32.868246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18436 11:17:32.899357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18438 11:17:32.899884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18439 11:17:32.930234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18441 11:17:32.930684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18442 11:17:32.961407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18443 11:17:32.961858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18445 11:17:32.992994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18446 11:17:32.993421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18448 11:17:33.023325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18449 11:17:33.023803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18451 11:17:33.054155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18453 11:17:33.054686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18454 11:17:33.085317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18455 11:17:33.085767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18457 11:17:33.116174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18458 11:17:33.116579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18460 11:17:33.151162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18461 11:17:33.151645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18463 11:17:33.182939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18464 11:17:33.183386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18466 11:17:33.214203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18468 11:17:33.214745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18469 11:17:33.245694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18470 11:17:33.246032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18472 11:17:33.277236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18474 11:17:33.277953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18475 11:17:33.308633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18476 11:17:33.308997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18478 11:17:33.339262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18479 11:17:33.339598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18481 11:17:33.369938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18483 11:17:33.370339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18484 11:17:33.400288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18486 11:17:33.400711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18487 11:17:33.432063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18488 11:17:33.432407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18490 11:17:33.463787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18492 11:17:33.464506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18493 11:17:33.494686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18494 11:17:33.495048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18496 11:17:33.526845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18498 11:17:33.527278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18499 11:17:33.557826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18500 11:17:33.558271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18502 11:17:33.588855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18504 11:17:33.589399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18505 11:17:33.619253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18507 11:17:33.619762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18508 11:17:33.649307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18510 11:17:33.649834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18511 11:17:33.679953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18512 11:17:33.680363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18514 11:17:33.710479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18515 11:17:33.710902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18517 11:17:33.740755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18518 11:17:33.741202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18520 11:17:33.771451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18522 11:17:33.771974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18523 11:17:33.801787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18525 11:17:33.802301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18526 11:17:33.832686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18528 11:17:33.833240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18529 11:17:33.862934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18530 11:17:33.863326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18532 11:17:33.893327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18534 11:17:33.893816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18535 11:17:33.923208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18537 11:17:33.923651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18538 11:17:33.954237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18540 11:17:33.954675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18541 11:17:33.984366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18543 11:17:33.984794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18544 11:17:34.014701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18546 11:17:34.015242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18547 11:17:34.045048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18548 11:17:34.045482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18550 11:17:34.075249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18551 11:17:34.075676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18553 11:17:34.106550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18554 11:17:34.107004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18556 11:17:34.136384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18557 11:17:34.136791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18559 11:17:34.166886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18560 11:17:34.167292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18562 11:17:34.197112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18564 11:17:34.197629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18565 11:17:34.227564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18566 11:17:34.227998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18568 11:17:34.258663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18569 11:17:34.259080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18571 11:17:34.289714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18572 11:17:34.290080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18574 11:17:34.320003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18575 11:17:34.320274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18577 11:17:34.350483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18578 11:17:34.350824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18580 11:17:34.380513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18581 11:17:34.380866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18583 11:17:34.411286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18585 11:17:34.411857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18586 11:17:34.441715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18587 11:17:34.442123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18589 11:17:34.472887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18591 11:17:34.473502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18592 11:17:34.505686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18594 11:17:34.506265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18595 11:17:34.536347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18597 11:17:34.536910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18598 11:17:34.567356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18600 11:17:34.567889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18601 11:17:34.598488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18603 11:17:34.599034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18604 11:17:34.629046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18606 11:17:34.629619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18607 11:17:34.659884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18608 11:17:34.660337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18610 11:17:34.691251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18611 11:17:34.691706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18613 11:17:34.722565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18615 11:17:34.723001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18616 11:17:34.754634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18618 11:17:34.755195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18619 11:17:34.785215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18620 11:17:34.785690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18622 11:17:34.816181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18623 11:17:34.816660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18625 11:17:34.848535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18626 11:17:34.849002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18628 11:17:34.879699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18629 11:17:34.880149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18631 11:17:34.911915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18632 11:17:34.912284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18634 11:17:34.948388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18635 11:17:34.948806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18637 11:17:34.981925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18639 11:17:34.982372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18640 11:17:35.014920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18641 11:17:35.015389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18643 11:17:35.048840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18645 11:17:35.049228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18646 11:17:35.091081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18647 11:17:35.091495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18649 11:17:35.124999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18650 11:17:35.125342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18652 11:17:35.157055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18654 11:17:35.157493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18655 11:17:35.187892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18656 11:17:35.188235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18658 11:17:35.218825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18659 11:17:35.219162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18661 11:17:35.249454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18662 11:17:35.249943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18664 11:17:35.280629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18665 11:17:35.280981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18667 11:17:35.311885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18668 11:17:35.312231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18670 11:17:35.343132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18671 11:17:35.343474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18673 11:17:35.374400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18674 11:17:35.374742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18676 11:17:35.405371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18678 11:17:35.405847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18679 11:17:35.436840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18681 11:17:35.437456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18682 11:17:35.468370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18683 11:17:35.468823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18685 11:17:35.500442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18686 11:17:35.500799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18688 11:17:35.533053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18690 11:17:35.533604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18691 11:17:35.565141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18692 11:17:35.565588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18694 11:17:35.598554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18696 11:17:35.599018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18697 11:17:35.630504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18699 11:17:35.631058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18700 11:17:35.660813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18701 11:17:35.661163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18703 11:17:35.692634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18704 11:17:35.693048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18706 11:17:35.724344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18707 11:17:35.724779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18709 11:17:35.761035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18711 11:17:35.761594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18712 11:17:35.803502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18713 11:17:35.804009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18715 11:17:35.837496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18716 11:17:35.837874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18718 11:17:35.868336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18720 11:17:35.868882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18721 11:17:35.898929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18722 11:17:35.899371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18724 11:17:35.929921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18726 11:17:35.930400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18727 11:17:35.965781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18728 11:17:35.966129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18730 11:17:35.998873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18731 11:17:35.999266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18733 11:17:36.029500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18734 11:17:36.029973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18736 11:17:36.059936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18737 11:17:36.060381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18739 11:17:36.090610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18740 11:17:36.091056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18742 11:17:36.123042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18743 11:17:36.123509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18745 11:17:36.155064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18746 11:17:36.155533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18748 11:17:36.185900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18749 11:17:36.186314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18751 11:17:36.217592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18752 11:17:36.218153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18754 11:17:36.249257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18755 11:17:36.249692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18757 11:17:36.282903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18758 11:17:36.283419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18760 11:17:36.316358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18762 11:17:36.316784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18763 11:17:36.349234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18764 11:17:36.349624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18766 11:17:36.383140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18768 11:17:36.383554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18769 11:17:36.415388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18771 11:17:36.415942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18772 11:17:36.447111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18773 11:17:36.447587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18775 11:17:36.479001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18777 11:17:36.479418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18778 11:17:36.510647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18779 11:17:36.510937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18781 11:17:36.541457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18782 11:17:36.541824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18784 11:17:36.571947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18785 11:17:36.572296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18787 11:17:36.602248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18789 11:17:36.602661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18790 11:17:36.634064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18792 11:17:36.634610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18793 11:17:36.667169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18794 11:17:36.667631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18796 11:17:36.699079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18798 11:17:36.699633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18799 11:17:36.730186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18801 11:17:36.730728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18802 11:17:36.760665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18804 11:17:36.761094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18805 11:17:36.791620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18807 11:17:36.792239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18808 11:17:36.822758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18809 11:17:36.823238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18811 11:17:36.854251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18813 11:17:36.854871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18814 11:17:36.886428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18815 11:17:36.886904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18817 11:17:36.917399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18818 11:17:36.917868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18820 11:17:36.949181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18822 11:17:36.949750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18823 11:17:36.984336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18824 11:17:36.984789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18826 11:17:37.016849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18827 11:17:37.017319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18829 11:17:37.047363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18830 11:17:37.047802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18832 11:17:37.077713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18833 11:17:37.078116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18835 11:17:37.108959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18836 11:17:37.109370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18838 11:17:37.140771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18839 11:17:37.141195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18841 11:17:37.172986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18842 11:17:37.173413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18844 11:17:37.204061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18845 11:17:37.204537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18847 11:17:37.234958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18848 11:17:37.235399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18850 11:17:37.265478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18851 11:17:37.265941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18853 11:17:37.297335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18854 11:17:37.297824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18856 11:17:37.330982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18858 11:17:37.331539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18859 11:17:37.361743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18860 11:17:37.362185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18862 11:17:37.392448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18864 11:17:37.393041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18865 11:17:37.423140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18867 11:17:37.423738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18868 11:17:37.454949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18869 11:17:37.455380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18871 11:17:37.488244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18873 11:17:37.488892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18874 11:17:37.519771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18875 11:17:37.520249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18877 11:17:37.551139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18878 11:17:37.551582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18880 11:17:37.582592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18882 11:17:37.583175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18883 11:17:37.614279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18885 11:17:37.614820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18886 11:17:37.646157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18888 11:17:37.646807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18889 11:17:37.677922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18891 11:17:37.678374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18892 11:17:37.710233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18894 11:17:37.710661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18895 11:17:37.741652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18896 11:17:37.742065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18898 11:17:37.772676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18900 11:17:37.773281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18901 11:17:37.803665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18902 11:17:37.804144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18904 11:17:37.835319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18905 11:17:37.835789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18907 11:17:37.867215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18909 11:17:37.867760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18910 11:17:37.898980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18912 11:17:37.899499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18913 11:17:37.930780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18915 11:17:37.931218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18916 11:17:37.962536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18917 11:17:37.962947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18919 11:17:37.994850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18920 11:17:37.995257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18922 11:17:38.027576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18923 11:17:38.027864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18925 11:17:38.059055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18926 11:17:38.059338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18928 11:17:38.089461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18929 11:17:38.089738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18931 11:17:38.122267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18933 11:17:38.122813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18934 11:17:38.155216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18935 11:17:38.155664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18937 11:17:38.187150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18939 11:17:38.187689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18940 11:17:38.218036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18942 11:17:38.218606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18943 11:17:38.248859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18945 11:17:38.249300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18946 11:17:38.280130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18947 11:17:38.280563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18949 11:17:38.312932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18950 11:17:38.313398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18952 11:17:38.346844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18954 11:17:38.347399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18955 11:17:38.377720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18956 11:17:38.378172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18958 11:17:38.408631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18959 11:17:38.409082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18961 11:17:38.439557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18963 11:17:38.440117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18964 11:17:38.470911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18965 11:17:38.471390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18967 11:17:38.502574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18969 11:17:38.503195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18970 11:17:38.533388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18971 11:17:38.533680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18973 11:17:38.564135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18975 11:17:38.564445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18976 11:17:38.595824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18978 11:17:38.596103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18979 11:17:38.627895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18980 11:17:38.628268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
18982 11:17:38.659291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
18984 11:17:38.659718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
18985 11:17:38.693233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
18987 11:17:38.693534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
18988 11:17:38.726505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
18990 11:17:38.726796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
18991 11:17:38.757676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
18993 11:17:38.758000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
18994 11:17:38.789706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
18996 11:17:38.790135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
18997 11:17:38.823122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
18998 11:17:38.823516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
19000 11:17:38.855140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
19002 11:17:38.855500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
19003 11:17:38.885521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
19004 11:17:38.885800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
19006 11:17:38.916071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
19007 11:17:38.916358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
19009 11:17:38.947420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
19010 11:17:38.947827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
19012 11:17:38.978352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
19014 11:17:38.978986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
19015 11:17:39.010186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
19017 11:17:39.010728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
19018 11:17:39.042471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
19019 11:17:39.042927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
19021 11:17:39.074153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
19023 11:17:39.074790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
19024 11:17:39.106813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
19025 11:17:39.107318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
19027 11:17:39.142713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
19028 11:17:39.143174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
19030 11:17:39.174116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
19032 11:17:39.174717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
19033 11:17:39.206169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
19035 11:17:39.206727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
19036 11:17:39.237664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
19037 11:17:39.238082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
19039 11:17:39.269610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
19041 11:17:39.270074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
19042 11:17:39.303067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
19044 11:17:39.303504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
19045 11:17:39.335386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
19047 11:17:39.335962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
19048 11:17:39.369068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
19049 11:17:39.369472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
19051 11:17:39.399579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
19052 11:17:39.399994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
19054 11:17:39.430783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
19056 11:17:39.431338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
19057 11:17:39.462084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
19059 11:17:39.462774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
19060 11:17:39.493652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
19061 11:17:39.494081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
19063 11:17:39.525126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
19064 11:17:39.525503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
19066 11:17:39.555457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
19068 11:17:39.555755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
19069 11:17:39.585879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
19071 11:17:39.586338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
19072 11:17:39.616974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
19074 11:17:39.617405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
19075 11:17:39.649192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
19076 11:17:39.649669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
19078 11:17:39.681599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
19080 11:17:39.682176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
19081 11:17:39.712435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
19082 11:17:39.712877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
19084 11:17:39.743012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
19085 11:17:39.743455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
19087 11:17:39.773698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
19088 11:17:39.774157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
19090 11:17:39.805967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
19092 11:17:39.806529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
19093 11:17:39.838788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
19095 11:17:39.839463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
19096 11:17:39.870599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
19097 11:17:39.871045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
19099 11:17:39.901127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
19100 11:17:39.901610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
19102 11:17:39.931645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
19103 11:17:39.932025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
19105 11:17:39.962257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
19107 11:17:39.962672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
19108 11:17:39.992575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
19109 11:17:39.993065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
19111 11:17:40.023106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
19112 11:17:40.023568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
19114 11:17:40.054913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
19115 11:17:40.055373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
19117 11:17:40.086736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
19119 11:17:40.087327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
19120 11:17:40.117328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
19122 11:17:40.117908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
19123 11:17:40.150854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
19125 11:17:40.151453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
19126 11:17:40.185679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
19128 11:17:40.186251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
19129 11:17:40.215741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
19130 11:17:40.216138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
19132 11:17:40.246202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
19134 11:17:40.246624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
19135 11:17:40.277074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
19137 11:17:40.277510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
19138 11:17:40.309629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
19140 11:17:40.310202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
19141 11:17:40.342057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
19143 11:17:40.342658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
19144 11:17:40.373918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
19146 11:17:40.374478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
19147 11:17:40.404541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
19148 11:17:40.404936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
19150 11:17:40.435179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
19151 11:17:40.435635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
19153 11:17:40.468025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
19154 11:17:40.468493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
19156 11:17:40.501582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
19158 11:17:40.502240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
19159 11:17:40.536604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
19161 11:17:40.537303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
19162 11:17:40.568598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
19163 11:17:40.569073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
19165 11:17:40.599648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
19167 11:17:40.600255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
19168 11:17:40.650884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
19170 11:17:40.651450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
19171 11:17:40.704130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
19172 11:17:40.704629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
19174 11:17:40.739205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
19176 11:17:40.739836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
19177 11:17:40.771534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
19178 11:17:40.771943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
19180 11:17:40.803740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
19181 11:17:40.804146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
19183 11:17:40.837413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
19184 11:17:40.837873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
19186 11:17:40.873713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
19187 11:17:40.874120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
19189 11:17:40.905441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
19190 11:17:40.905871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
19192 11:17:40.936886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
19193 11:17:40.937288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
19195 11:17:40.967080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
19196 11:17:40.967422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
19198 11:17:40.997398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
19199 11:17:40.997743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
19201 11:17:41.028778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
19202 11:17:41.029242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
19204 11:17:41.059625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
19206 11:17:41.060151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
19207 11:17:41.091079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
19208 11:17:41.091533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
19210 11:17:41.123176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
19212 11:17:41.123724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
19213 11:17:41.154197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
19215 11:17:41.154638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
19216 11:17:41.185138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
19217 11:17:41.185525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
19219 11:17:41.215837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
19221 11:17:41.216384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
19222 11:17:41.246916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
19223 11:17:41.247366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
19225 11:17:41.278315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19227 11:17:41.278872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19228 11:17:41.309251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19229 11:17:41.309708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19231 11:17:41.340451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19232 11:17:41.340918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19234 11:17:41.372221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19235 11:17:41.372677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19237 11:17:41.403352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19238 11:17:41.403805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19240 11:17:41.434572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19241 11:17:41.435024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19243 11:17:41.464997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19244 11:17:41.465447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19246 11:17:41.495109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19247 11:17:41.495460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19249 11:17:41.525295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19250 11:17:41.525657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19252 11:17:41.555682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19253 11:17:41.556024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19255 11:17:41.585608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19256 11:17:41.585973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19258 11:17:41.615985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19259 11:17:41.616345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19261 11:17:41.646916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19262 11:17:41.647274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19264 11:17:41.677399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19265 11:17:41.677756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19267 11:17:41.711279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19268 11:17:41.711799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19270 11:17:41.744403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19272 11:17:41.744875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19273 11:17:41.776028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19275 11:17:41.776508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19276 11:17:41.806810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19277 11:17:41.807119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19279 11:17:41.838894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19281 11:17:41.839342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19282 11:17:41.869322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19283 11:17:41.869682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19285 11:17:41.899769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19286 11:17:41.900107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19288 11:17:41.930704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19289 11:17:41.931044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19291 11:17:41.961228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19292 11:17:41.961570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19294 11:17:41.991573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19296 11:17:41.992262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19297 11:17:42.021726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19299 11:17:42.022392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19300 11:17:42.051722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19302 11:17:42.052281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19303 11:17:42.082289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19304 11:17:42.082817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19306 11:17:42.113721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19307 11:17:42.114184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19309 11:17:42.144806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19311 11:17:42.145416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19312 11:17:42.174982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19313 11:17:42.175342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19315 11:17:42.205300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19316 11:17:42.205580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19318 11:17:42.235947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19319 11:17:42.236403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19321 11:17:42.266990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19323 11:17:42.267521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19324 11:17:42.297533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19326 11:17:42.298118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19327 11:17:42.328331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19328 11:17:42.328775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19330 11:17:42.359139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19332 11:17:42.359712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19333 11:17:42.389722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19334 11:17:42.390157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19336 11:17:42.420331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19337 11:17:42.420770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19339 11:17:42.450904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19340 11:17:42.451337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19342 11:17:42.481214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19343 11:17:42.481664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19345 11:17:42.511386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19347 11:17:42.511897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19348 11:17:42.541562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19350 11:17:42.542138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19351 11:17:42.572372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19352 11:17:42.572837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19354 11:17:42.602734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19355 11:17:42.603096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19357 11:17:42.633017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19358 11:17:42.633374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19360 11:17:42.663511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19361 11:17:42.663853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19363 11:17:42.693701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19364 11:17:42.694041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19366 11:17:42.723849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19367 11:17:42.724187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19369 11:17:42.754730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19370 11:17:42.755069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19372 11:17:42.785079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19373 11:17:42.785419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19375 11:17:42.815420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19376 11:17:42.815759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19378 11:17:42.845680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19379 11:17:42.846019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19381 11:17:42.876046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19382 11:17:42.876400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19384 11:17:42.907070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19386 11:17:42.907494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19387 11:17:42.937482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19388 11:17:42.937826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19390 11:17:42.968066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19391 11:17:42.968403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19393 11:17:42.998646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19394 11:17:42.998994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19396 11:17:43.029010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19398 11:17:43.029442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19399 11:17:43.059324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19401 11:17:43.059884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19402 11:17:43.090799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19404 11:17:43.091340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19405 11:17:43.121547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19407 11:17:43.122161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19408 11:17:43.152572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19409 11:17:43.153041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19411 11:17:43.183070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19413 11:17:43.183653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19414 11:17:43.213660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19416 11:17:43.214205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19417 11:17:43.245099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19418 11:17:43.245545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19420 11:17:43.275164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19421 11:17:43.275608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19423 11:17:43.305841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19424 11:17:43.306289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19426 11:17:43.337087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19427 11:17:43.337558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19429 11:17:43.371127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19430 11:17:43.371606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19432 11:17:43.407270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19434 11:17:43.407842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19435 11:17:43.443866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19436 11:17:43.444318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19438 11:17:43.479303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19439 11:17:43.479670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19441 11:17:43.513497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19442 11:17:43.513873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19444 11:17:43.546232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19446 11:17:43.546664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19447 11:17:43.579206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19448 11:17:43.579558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19450 11:17:43.612184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19451 11:17:43.612554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19453 11:17:43.645615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19455 11:17:43.646058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19456 11:17:43.678884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19458 11:17:43.679360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19459 11:17:43.711787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19460 11:17:43.712143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19462 11:17:43.745123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19463 11:17:43.745486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19465 11:17:43.776801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19466 11:17:43.777158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19468 11:17:43.806790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19470 11:17:43.807268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19471 11:17:43.836459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19472 11:17:43.836826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19474 11:17:43.867107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19476 11:17:43.867558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19477 11:17:43.897119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19478 11:17:43.897459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19480 11:17:43.927852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19481 11:17:43.928195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19483 11:17:43.958328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19484 11:17:43.958689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19486 11:17:43.988277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19488 11:17:43.988713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19489 11:17:44.017640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19490 11:17:44.018009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19492 11:17:44.047575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19493 11:17:44.047934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19495 11:17:44.077354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19496 11:17:44.077681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19498 11:17:44.107997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19499 11:17:44.108360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19501 11:17:44.138270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19502 11:17:44.138758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19504 11:17:44.167789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19505 11:17:44.168277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19507 11:17:44.197588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19508 11:17:44.198078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19510 11:17:44.227593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19512 11:17:44.228101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19513 11:17:44.259289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19515 11:17:44.259634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19516 11:17:44.289445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19517 11:17:44.289751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19519 11:17:44.319857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19521 11:17:44.320165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19522 11:17:44.349770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19523 11:17:44.350138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19525 11:17:44.380198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19526 11:17:44.380469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19528 11:17:44.410688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19529 11:17:44.411040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19531 11:17:44.440847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19532 11:17:44.441195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19534 11:17:44.471001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19535 11:17:44.471338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19537 11:17:44.500719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19538 11:17:44.501081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19540 11:17:44.530703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19541 11:17:44.531040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19543 11:17:44.560985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19545 11:17:44.561393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19546 11:17:44.591054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19547 11:17:44.591409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19549 11:17:44.621228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19550 11:17:44.621566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19552 11:17:44.651699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19554 11:17:44.652182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19555 11:17:44.682626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19557 11:17:44.683033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19558 11:17:44.712591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19559 11:17:44.712947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19561 11:17:44.743134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19562 11:17:44.743476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19564 11:17:44.772805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19565 11:17:44.773140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19567 11:17:44.802810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19568 11:17:44.803157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19570 11:17:44.832471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19571 11:17:44.832812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19573 11:17:44.862734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19574 11:17:44.863072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19576 11:17:44.893449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19578 11:17:44.893866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19579 11:17:44.923113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19581 11:17:44.923585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19582 11:17:44.953037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19584 11:17:44.953445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19585 11:17:44.982900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19586 11:17:44.983238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19588 11:17:45.012618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19589 11:17:45.012972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19591 11:17:45.043229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19592 11:17:45.043586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19594 11:17:45.074109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19596 11:17:45.074524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19597 11:17:45.104087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19598 11:17:45.104434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19600 11:17:45.133804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19601 11:17:45.134143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19603 11:17:45.163639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19604 11:17:45.163979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19606 11:17:45.193940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19607 11:17:45.194288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19609 11:17:45.224198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19610 11:17:45.224545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19612 11:17:45.253876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19613 11:17:45.254215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19615 11:17:45.283926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19616 11:17:45.284292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19618 11:17:45.314954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19620 11:17:45.315530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19621 11:17:45.344670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19623 11:17:45.345105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19624 11:17:45.375218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19625 11:17:45.375534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19627 11:17:45.405149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19628 11:17:45.405488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19630 11:17:45.435190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19631 11:17:45.435540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19633 11:17:45.465145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19635 11:17:45.465554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19636 11:17:45.495049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19637 11:17:45.495387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19639 11:17:45.525199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19641 11:17:45.525610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19642 11:17:45.554937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19643 11:17:45.555277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19645 11:17:45.585067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19647 11:17:45.585485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19648 11:17:45.615162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19650 11:17:45.615576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19651 11:17:45.645106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19652 11:17:45.645457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19654 11:17:45.675099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19655 11:17:45.675448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19657 11:17:45.705203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19658 11:17:45.705540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19660 11:17:45.735206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19661 11:17:45.735540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19663 11:17:45.765135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19664 11:17:45.765483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19666 11:17:45.795126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19667 11:17:45.795477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19669 11:17:45.825707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19670 11:17:45.826065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19672 11:17:45.856030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19674 11:17:45.856544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19675 11:17:45.886502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19676 11:17:45.886967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19678 11:17:45.916493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19679 11:17:45.916844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19681 11:17:45.946410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19683 11:17:45.946839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19684 11:17:45.975920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19686 11:17:45.976333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19687 11:17:46.005694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19688 11:17:46.006031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19690 11:17:46.036082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19691 11:17:46.036417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19693 11:17:46.065991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19694 11:17:46.066336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19696 11:17:46.096879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19697 11:17:46.097226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19699 11:17:46.127252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19700 11:17:46.127593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19702 11:17:46.157446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19703 11:17:46.157786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19705 11:17:46.187387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19706 11:17:46.187741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19708 11:17:46.217221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19710 11:17:46.217701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19711 11:17:46.247495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19712 11:17:46.247832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19714 11:17:46.277601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19715 11:17:46.277948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19717 11:17:46.307781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19718 11:17:46.308125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19720 11:17:46.338935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19722 11:17:46.339343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19723 11:17:46.371097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19725 11:17:46.371553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19726 11:17:46.401294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19727 11:17:46.401641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19729 11:17:46.432946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19730 11:17:46.433307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19732 11:17:46.463518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19734 11:17:46.463928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19735 11:17:46.493606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19736 11:17:46.493984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19738 11:17:46.523906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19740 11:17:46.524377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19741 11:17:46.553793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19743 11:17:46.554202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19744 11:17:46.584032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19745 11:17:46.584374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19747 11:17:46.613769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19748 11:17:46.614108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19750 11:17:46.644494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19752 11:17:46.644904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19753 11:17:46.675074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19754 11:17:46.675413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19756 11:17:46.706223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19758 11:17:46.706737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19759 11:17:46.737626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19760 11:17:46.738001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19762 11:17:46.768559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19763 11:17:46.769018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19765 11:17:46.799173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19766 11:17:46.799613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19768 11:17:46.830481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19769 11:17:46.830886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19771 11:17:46.861563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19772 11:17:46.861988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19774 11:17:46.892106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19776 11:17:46.892544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19777 11:17:46.922631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19779 11:17:46.923245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19780 11:17:46.952855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19781 11:17:46.953316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19783 11:17:46.983224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19784 11:17:46.983663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19786 11:17:47.013815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19787 11:17:47.014261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19789 11:17:47.044320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19790 11:17:47.044772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19792 11:17:47.075038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19794 11:17:47.075583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19795 11:17:47.105948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19797 11:17:47.106548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19798 11:17:47.138093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19800 11:17:47.138511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19801 11:17:47.168795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19802 11:17:47.169192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19804 11:17:47.199073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19805 11:17:47.199471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19807 11:17:47.229243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19808 11:17:47.229644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19810 11:17:47.260063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19811 11:17:47.260511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19813 11:17:47.289770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19814 11:17:47.290125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19816 11:17:47.319882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19817 11:17:47.320239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19819 11:17:47.349545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19820 11:17:47.349912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19822 11:17:47.379852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19823 11:17:47.380204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19825 11:17:47.409559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19826 11:17:47.409925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19828 11:17:47.439019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19829 11:17:47.439373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19831 11:17:47.469022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19832 11:17:47.469371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19834 11:17:47.498733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19835 11:17:47.499092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19837 11:17:47.528675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19838 11:17:47.529037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19840 11:17:47.559079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19841 11:17:47.559439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19843 11:17:47.588696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19844 11:17:47.589059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19846 11:17:47.618396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19847 11:17:47.618749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19849 11:17:47.648109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19850 11:17:47.648459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19852 11:17:47.677791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19853 11:17:47.678149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19855 11:17:47.707493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19856 11:17:47.707843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19858 11:17:47.752018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19859 11:17:47.752370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19861 11:17:47.782870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19862 11:17:47.783223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19864 11:17:47.813685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19865 11:17:47.814035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19867 11:17:47.844081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19868 11:17:47.844438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19870 11:17:47.875001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19871 11:17:47.875352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19873 11:17:47.905493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19874 11:17:47.905859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19876 11:17:47.935693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19877 11:17:47.936043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19879 11:17:47.967000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19880 11:17:47.967352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19882 11:17:47.997747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19883 11:17:47.998096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19885 11:17:48.027591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19886 11:17:48.027945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19888 11:17:48.057005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19889 11:17:48.057357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19891 11:17:48.086717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19892 11:17:48.087069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19894 11:17:48.116317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19895 11:17:48.116667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19897 11:17:48.146037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19899 11:17:48.146476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19900 11:17:48.175659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19901 11:17:48.176012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19903 11:17:48.205378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19904 11:17:48.205741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19906 11:17:48.235052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19907 11:17:48.235406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19909 11:17:48.264609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19910 11:17:48.264960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19912 11:17:48.294988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19913 11:17:48.295340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19915 11:17:48.324718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19916 11:17:48.325067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19918 11:17:48.354458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19919 11:17:48.354809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19921 11:17:48.384271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19922 11:17:48.384619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19924 11:17:48.414099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19926 11:17:48.414522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19927 11:17:48.443727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19928 11:17:48.444078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19930 11:17:48.473419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19931 11:17:48.473770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19933 11:17:48.503239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19934 11:17:48.503594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19936 11:17:48.533574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19937 11:17:48.533950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19939 11:17:48.563211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19940 11:17:48.563563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19942 11:17:48.593162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19943 11:17:48.593512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19945 11:17:48.623058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19947 11:17:48.623493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19948 11:17:48.652740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19949 11:17:48.653091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19951 11:17:48.683905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19952 11:17:48.684262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19954 11:17:48.716600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19955 11:17:48.716970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19957 11:17:48.749470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19958 11:17:48.749951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19960 11:17:48.780338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19961 11:17:48.780809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19963 11:17:48.810832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19964 11:17:48.811279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19966 11:17:48.840940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19967 11:17:48.841408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19969 11:17:48.871229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19970 11:17:48.871690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19972 11:17:48.901185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19973 11:17:48.901660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19975 11:17:48.931134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19976 11:17:48.931603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19978 11:17:48.962379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19979 11:17:48.962845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
19981 11:17:48.992352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
19982 11:17:48.992816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
19984 11:17:49.022835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
19986 11:17:49.023273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
19987 11:17:49.053231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
19988 11:17:49.053698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
19990 11:17:49.083214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
19991 11:17:49.083675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
19993 11:17:49.113181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
19994 11:17:49.113638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
19996 11:17:49.147079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
19997 11:17:49.147559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
19999 11:17:49.177790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
20000 11:17:49.178252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
20002 11:17:49.217390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
20003 11:17:49.217863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
20005 11:17:49.250148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
20007 11:17:49.250751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
20008 11:17:49.283548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
20009 11:17:49.284027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
20011 11:17:49.316455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
20013 11:17:49.316994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
20014 11:17:49.347076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
20015 11:17:49.347426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
20017 11:17:49.377850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
20018 11:17:49.378192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
20020 11:17:49.408013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
20021 11:17:49.408364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
20023 11:17:49.438159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
20025 11:17:49.438560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
20026 11:17:49.468220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
20027 11:17:49.468582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
20029 11:17:49.498830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
20030 11:17:49.499185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
20032 11:17:49.529892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
20033 11:17:49.530230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
20035 11:17:49.559994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
20036 11:17:49.560332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
20038 11:17:49.590606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
20039 11:17:49.590946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
20041 11:17:49.620152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
20042 11:17:49.620492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
20044 11:17:49.652042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
20046 11:17:49.652497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
20047 11:17:49.682608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
20048 11:17:49.682951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
20050 11:17:49.712403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
20051 11:17:49.712864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
20053 11:17:49.743042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
20055 11:17:49.743472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
20056 11:17:49.773974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
20058 11:17:49.774425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
20059 11:17:49.804788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
20060 11:17:49.805176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
20062 11:17:49.835165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
20063 11:17:49.835560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
20065 11:17:49.865719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
20066 11:17:49.866174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
20068 11:17:49.895766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
20069 11:17:49.896137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
20071 11:17:49.926152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
20073 11:17:49.926562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
20074 11:17:49.956600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
20075 11:17:49.956953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
20077 11:17:49.986924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
20078 11:17:49.987287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
20080 11:17:50.016657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
20081 11:17:50.016986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
20083 11:17:50.046899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
20084 11:17:50.047242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
20086 11:17:50.076849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
20087 11:17:50.077182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
20089 11:17:50.107119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
20090 11:17:50.107471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
20092 11:17:50.137084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
20093 11:17:50.137419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
20095 11:17:50.166566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
20096 11:17:50.166900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
20098 11:17:50.196116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
20099 11:17:50.196450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
20101 11:17:50.225686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
20102 11:17:50.226019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
20104 11:17:50.255653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
20105 11:17:50.255992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
20107 11:17:50.285337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
20108 11:17:50.285685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
20110 11:17:50.315219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
20112 11:17:50.315611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
20113 11:17:50.345388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
20114 11:17:50.345681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
20116 11:17:50.374839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
20117 11:17:50.375172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
20119 11:17:50.404449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
20120 11:17:50.404785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
20122 11:17:50.434681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
20123 11:17:50.435014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
20125 11:17:50.464661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
20126 11:17:50.464995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
20128 11:17:50.495289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
20129 11:17:50.495625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
20131 11:17:50.526574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
20132 11:17:50.527050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
20134 11:17:50.557723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
20135 11:17:50.558206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
20137 11:17:50.588342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
20138 11:17:50.588816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
20140 11:17:50.619030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
20141 11:17:50.619512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
20143 11:17:50.650126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
20144 11:17:50.650590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
20146 11:17:50.680421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
20147 11:17:50.680887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
20149 11:17:50.710544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
20150 11:17:50.711011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
20152 11:17:50.741088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
20153 11:17:50.741563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
20155 11:17:50.771323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
20156 11:17:50.771791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
20158 11:17:50.801586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
20159 11:17:50.802066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
20161 11:17:50.831752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
20162 11:17:50.832221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
20164 11:17:50.861673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
20165 11:17:50.862133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
20167 11:17:50.891826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
20168 11:17:50.892291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
20170 11:17:50.922767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
20171 11:17:50.923236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
20173 11:17:50.952938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
20174 11:17:50.953360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
20176 11:17:50.984929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
20177 11:17:50.985423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
20179 11:17:51.017003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
20181 11:17:51.017627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
20182 11:17:51.047067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
20183 11:17:51.047405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
20185 11:17:51.077381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
20186 11:17:51.077682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
20188 11:17:51.107387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
20189 11:17:51.107724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
20191 11:17:51.138871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
20193 11:17:51.139316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
20194 11:17:51.170448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
20195 11:17:51.170816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
20197 11:17:51.200492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
20198 11:17:51.200847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
20200 11:17:51.232276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
20201 11:17:51.232657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
20203 11:17:51.265711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
20204 11:17:51.266121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
20206 11:17:51.297610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
20207 11:17:51.298108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
20209 11:17:51.328745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
20210 11:17:51.329194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
20212 11:17:51.359368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
20213 11:17:51.359831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
20215 11:17:51.390237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
20217 11:17:51.390587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
20218 11:17:51.421112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
20219 11:17:51.421468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
20221 11:17:51.451222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
20223 11:17:51.451633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
20224 11:17:51.483160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
20225 11:17:51.483658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20227 11:17:51.513685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20229 11:17:51.514235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20230 11:17:51.544097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20231 11:17:51.544542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20233 11:17:51.574470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20234 11:17:51.574902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20236 11:17:51.604210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20237 11:17:51.604639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20239 11:17:51.634731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20240 11:17:51.635175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20242 11:17:51.664766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20243 11:17:51.665220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20245 11:17:51.695389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20246 11:17:51.695868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20248 11:17:51.726958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20250 11:17:51.727567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20251 11:17:51.757449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20252 11:17:51.757929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20254 11:17:51.788127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20255 11:17:51.788579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20257 11:17:51.818355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20258 11:17:51.818750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20260 11:17:51.848119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20261 11:17:51.848580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20263 11:17:51.878483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20264 11:17:51.878924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20266 11:17:51.909373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20268 11:17:51.909953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20269 11:17:51.939135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20270 11:17:51.939558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20272 11:17:51.969318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20274 11:17:51.969916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20275 11:17:51.999786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20276 11:17:52.000215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20278 11:17:52.029799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20280 11:17:52.030312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20281 11:17:52.060472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20282 11:17:52.060909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20284 11:17:52.090749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20285 11:17:52.091171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20287 11:17:52.121113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20288 11:17:52.121583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20290 11:17:52.150735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20291 11:17:52.151083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20293 11:17:52.180224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20294 11:17:52.180578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20296 11:17:52.209832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20297 11:17:52.210182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20299 11:17:52.239583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20300 11:17:52.240040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20302 11:17:52.269767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20303 11:17:52.270108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20305 11:17:52.299933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20307 11:17:52.300469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20308 11:17:52.329815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20309 11:17:52.330227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20311 11:17:52.359885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20313 11:17:52.360401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20314 11:17:52.389869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20315 11:17:52.390311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20317 11:17:52.419670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20318 11:17:52.420114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20320 11:17:52.450586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20321 11:17:52.451037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20323 11:17:52.480576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20324 11:17:52.481030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20326 11:17:52.510829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20327 11:17:52.511275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20329 11:17:52.540749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20330 11:17:52.541200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20332 11:17:52.571010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20333 11:17:52.571466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20335 11:17:52.600953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20336 11:17:52.601402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20338 11:17:52.631151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20339 11:17:52.631599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20341 11:17:52.661365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20342 11:17:52.661815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20344 11:17:52.692968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20345 11:17:52.693442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20347 11:17:52.723121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20348 11:17:52.723574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20350 11:17:52.753262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20351 11:17:52.753637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20353 11:17:52.783166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20354 11:17:52.783638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20356 11:17:52.813252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20358 11:17:52.813813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20359 11:17:52.864128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20360 11:17:52.864527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20362 11:17:52.897030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20363 11:17:52.897484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20365 11:17:52.927304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20367 11:17:52.927817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20368 11:17:52.957239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20369 11:17:52.957678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20371 11:17:52.987234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20372 11:17:52.987715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20374 11:17:53.017600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20375 11:17:53.018055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20377 11:17:53.048293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20378 11:17:53.048725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20380 11:17:53.078504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20381 11:17:53.078940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20383 11:17:53.108709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20384 11:17:53.109122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20386 11:17:53.138764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20387 11:17:53.139177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20389 11:17:53.168428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20390 11:17:53.168827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20392 11:17:53.197698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20394 11:17:53.198153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20395 11:17:53.227063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20396 11:17:53.227430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20398 11:17:53.256748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20399 11:17:53.257113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20401 11:17:53.286807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20402 11:17:53.287171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20404 11:17:53.315995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20405 11:17:53.316345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20407 11:17:53.345470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20408 11:17:53.345827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20410 11:17:53.375363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20411 11:17:53.375713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20413 11:17:53.405027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20414 11:17:53.405396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20416 11:17:53.435229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20417 11:17:53.435597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20419 11:17:53.464973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20420 11:17:53.465328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20422 11:17:53.494962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20423 11:17:53.495314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20425 11:17:53.524898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20426 11:17:53.525257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20428 11:17:53.554555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20429 11:17:53.554909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20431 11:17:53.584011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20432 11:17:53.584368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20434 11:17:53.613752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20435 11:17:53.614109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20437 11:17:53.643237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20439 11:17:53.643675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20440 11:17:53.673171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20441 11:17:53.673525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20443 11:17:53.703036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20444 11:17:53.703392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20446 11:17:53.733079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20448 11:17:53.733519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20449 11:17:53.762911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20450 11:17:53.763269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20452 11:17:53.792554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20453 11:17:53.792915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20455 11:17:53.822436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20456 11:17:53.822796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20458 11:17:53.852497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20459 11:17:53.852852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20461 11:17:53.882194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20463 11:17:53.882627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20464 11:17:53.911228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20465 11:17:53.911584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20467 11:17:53.941102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20468 11:17:53.941452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20470 11:17:53.970659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20471 11:17:53.971010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20473 11:17:54.000669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20474 11:17:54.001025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20476 11:17:54.030717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20477 11:17:54.031083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20479 11:17:54.059929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20481 11:17:54.060421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20482 11:17:54.089768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20483 11:17:54.090144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20485 11:17:54.120585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20486 11:17:54.120956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20488 11:17:54.150506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20489 11:17:54.151051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20491 11:17:54.179976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20492 11:17:54.180335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20494 11:17:54.209571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20495 11:17:54.209963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20497 11:17:54.239026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20498 11:17:54.239331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20500 11:17:54.268763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20501 11:17:54.269071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20503 11:17:54.298605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20505 11:17:54.298907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20506 11:17:54.328019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20507 11:17:54.328291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20509 11:17:54.358314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20511 11:17:54.358778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20512 11:17:54.390906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20513 11:17:54.391267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20515 11:17:54.420108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20516 11:17:54.420449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20518 11:17:54.449591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20520 11:17:54.450006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20521 11:17:54.479503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20523 11:17:54.479977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20524 11:17:54.509201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20526 11:17:54.509681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20527 11:17:54.539013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20528 11:17:54.539353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20530 11:17:54.569089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20531 11:17:54.569427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20533 11:17:54.598952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20534 11:17:54.599287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20536 11:17:54.629822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20538 11:17:54.630226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20539 11:17:54.659361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20540 11:17:54.659714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20542 11:17:54.688961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20543 11:17:54.689317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20545 11:17:54.718895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20547 11:17:54.719306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20548 11:17:54.748627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20549 11:17:54.748962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20551 11:17:54.778862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20552 11:17:54.779216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20554 11:17:54.809203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20555 11:17:54.809556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20557 11:17:54.839190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20559 11:17:54.839623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20560 11:17:54.868395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20561 11:17:54.868756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20563 11:17:54.898193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20565 11:17:54.898632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20566 11:17:54.927973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20567 11:17:54.928439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20569 11:17:54.958708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20570 11:17:54.959068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20572 11:17:54.990760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20573 11:17:54.991199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20575 11:17:55.022577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20576 11:17:55.022924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20578 11:17:55.053693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20579 11:17:55.054057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20581 11:17:55.085385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20582 11:17:55.085771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20584 11:17:55.117281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20585 11:17:55.117622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20587 11:17:55.149998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20589 11:17:55.150454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20590 11:17:55.185569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20591 11:17:55.185926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20593 11:17:55.217033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20594 11:17:55.217425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20596 11:17:55.246986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20597 11:17:55.247398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20599 11:17:55.281376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20600 11:17:55.281796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20602 11:17:55.320129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20603 11:17:55.320479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20605 11:17:55.350091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20607 11:17:55.350502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20608 11:17:55.380542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20609 11:17:55.380889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20611 11:17:55.410663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20612 11:17:55.410998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20614 11:17:55.440582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20615 11:17:55.440922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20617 11:17:55.470780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20619 11:17:55.471238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20620 11:17:55.500405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20621 11:17:55.500743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20623 11:17:55.530488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20624 11:17:55.530828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20626 11:17:55.560101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20628 11:17:55.560592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20629 11:17:55.589912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20630 11:17:55.590270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20632 11:17:55.620117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20634 11:17:55.620529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20635 11:17:55.650181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20637 11:17:55.650628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20638 11:17:55.680034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20639 11:17:55.680372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20641 11:17:55.709764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20642 11:17:55.710102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20644 11:17:55.740281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20646 11:17:55.740691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20647 11:17:55.769778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20649 11:17:55.770257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20650 11:17:55.800087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20651 11:17:55.800429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20653 11:17:55.829706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20654 11:17:55.830058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20656 11:17:55.859202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20658 11:17:55.859605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20659 11:17:55.888750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20660 11:17:55.889095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20662 11:17:55.919452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20663 11:17:55.919830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20665 11:17:55.949651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20666 11:17:55.949920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20668 11:17:55.979132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20669 11:17:55.979399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20671 11:17:56.008913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20672 11:17:56.009266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20674 11:17:56.039716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20675 11:17:56.040182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20677 11:17:56.073737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20679 11:17:56.074287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20680 11:17:56.103903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20682 11:17:56.104288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20683 11:17:56.134195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20685 11:17:56.134755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20686 11:17:56.164982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20687 11:17:56.165440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20689 11:17:56.195188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20690 11:17:56.195602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20692 11:17:56.225418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20693 11:17:56.225813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20695 11:17:56.255468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20696 11:17:56.255889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20698 11:17:56.285308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20699 11:17:56.285688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20701 11:17:56.315589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20702 11:17:56.316000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20704 11:17:56.346895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20706 11:17:56.347397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20707 11:17:56.377565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20709 11:17:56.378070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20710 11:17:56.408195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20711 11:17:56.408618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20713 11:17:56.438890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20715 11:17:56.439402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20716 11:17:56.469168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20718 11:17:56.469701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20719 11:17:56.500397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20721 11:17:56.500933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20722 11:17:56.531135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20723 11:17:56.531579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20725 11:17:56.561283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20726 11:17:56.561684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20728 11:17:56.592433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20729 11:17:56.592855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20731 11:17:56.624668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20732 11:17:56.625043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20734 11:17:56.655141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20735 11:17:56.655478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20737 11:17:56.685528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20739 11:17:56.685928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20740 11:17:56.716265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20742 11:17:56.716681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20743 11:17:56.746661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20745 11:17:56.747056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20746 11:17:56.777365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20748 11:17:56.777781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20749 11:17:56.807752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20750 11:17:56.808086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20752 11:17:56.838618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20753 11:17:56.838952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20755 11:17:56.868614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20756 11:17:56.868949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20758 11:17:56.898695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20760 11:17:56.899100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20761 11:17:56.929406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20762 11:17:56.929742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20764 11:17:56.959078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20765 11:17:56.959556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20767 11:17:56.989515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20769 11:17:56.990155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20770 11:17:57.020071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20772 11:17:57.020635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20773 11:17:57.050763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20774 11:17:57.051102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20776 11:17:57.080847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20777 11:17:57.081192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20779 11:17:57.111062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20780 11:17:57.111508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20782 11:17:57.141116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20784 11:17:57.141575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20785 11:17:57.171112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20786 11:17:57.171451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20788 11:17:57.201347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20789 11:17:57.201681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20791 11:17:57.231692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20792 11:17:57.232057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20794 11:17:57.262680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20795 11:17:57.263013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20797 11:17:57.294238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20799 11:17:57.294826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20800 11:17:57.327271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20801 11:17:57.327679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20803 11:17:57.358102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20805 11:17:57.358544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20806 11:17:57.389106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20807 11:17:57.389502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20809 11:17:57.420068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20811 11:17:57.420522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20812 11:17:57.451621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20814 11:17:57.452180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20815 11:17:57.483115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20816 11:17:57.483505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20818 11:17:57.513450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20819 11:17:57.513806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20821 11:17:57.543463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20822 11:17:57.543805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20824 11:17:57.574242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20826 11:17:57.574801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20827 11:17:57.607107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20829 11:17:57.607641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20830 11:17:57.637816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20831 11:17:57.638172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20833 11:17:57.667828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20834 11:17:57.668197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20836 11:17:57.697680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20837 11:17:57.698014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20839 11:17:57.727615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20840 11:17:57.727961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20842 11:17:57.758502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20843 11:17:57.758853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20845 11:17:57.788335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20846 11:17:57.788691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20848 11:17:57.818671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20849 11:17:57.819008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20851 11:17:57.849305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20852 11:17:57.849639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20854 11:17:57.879484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20855 11:17:57.879821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20857 11:17:57.910732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20858 11:17:57.911066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20860 11:17:57.941269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20861 11:17:57.941602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20863 11:17:57.997153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20865 11:17:57.997783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20866 11:17:58.027860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20867 11:17:58.028310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20869 11:17:58.058679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20870 11:17:58.059130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20872 11:17:58.088972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20873 11:17:58.089427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20875 11:17:58.119231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20876 11:17:58.119671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20878 11:17:58.150112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20880 11:17:58.150545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20881 11:17:58.181426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20883 11:17:58.181884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20884 11:17:58.211772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20886 11:17:58.212205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20887 11:17:58.242363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20889 11:17:58.242788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20890 11:17:58.273007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20892 11:17:58.273444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20893 11:17:58.303561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20895 11:17:58.304089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20896 11:17:58.334348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20897 11:17:58.334818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20899 11:17:58.364595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20901 11:17:58.365192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20902 11:17:58.395069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20903 11:17:58.395514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20905 11:17:58.426475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20906 11:17:58.426947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20908 11:17:58.455936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20909 11:17:58.456293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20911 11:17:58.485686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20912 11:17:58.486001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20914 11:17:58.518272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20916 11:17:58.518809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20917 11:17:58.549147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20919 11:17:58.549749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20920 11:17:58.580572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20922 11:17:58.580999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20923 11:17:58.611713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20924 11:17:58.612178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20926 11:17:58.642865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20927 11:17:58.643201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20929 11:17:58.674161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20931 11:17:58.674577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20932 11:17:58.704484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20933 11:17:58.704798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20935 11:17:58.735167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20936 11:17:58.735500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20938 11:17:58.765867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20939 11:17:58.766202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20941 11:17:58.798833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20942 11:17:58.799159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20944 11:17:58.829691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20946 11:17:58.830090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20947 11:17:58.860527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20949 11:17:58.860904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20950 11:17:58.891241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20951 11:17:58.891578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20953 11:17:58.924895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20954 11:17:58.925373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20956 11:17:58.956888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20958 11:17:58.957328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20959 11:17:58.988433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20960 11:17:58.988848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20962 11:17:59.020836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20964 11:17:59.021288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20965 11:17:59.057336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20967 11:17:59.057762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20968 11:17:59.088865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20969 11:17:59.089271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20971 11:17:59.120800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20972 11:17:59.121269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20974 11:17:59.152263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20975 11:17:59.152680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20977 11:17:59.185157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20978 11:17:59.185567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20980 11:17:59.218665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
20982 11:17:59.219098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
20983 11:17:59.251633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
20984 11:17:59.252091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
20986 11:17:59.286422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
20987 11:17:59.286792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
20989 11:17:59.321369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
20991 11:17:59.321787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
20992 11:17:59.354699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
20993 11:17:59.355170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
20995 11:17:59.386966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
20996 11:17:59.387449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
20998 11:17:59.418436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
20999 11:17:59.418912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
21001 11:17:59.450647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
21002 11:17:59.451004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
21004 11:17:59.483045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
21006 11:17:59.483468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
21007 11:17:59.515234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
21008 11:17:59.515696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
21010 11:17:59.546899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
21011 11:17:59.547282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
21013 11:17:59.577625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
21014 11:17:59.578108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
21016 11:17:59.608131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
21017 11:17:59.608580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
21019 11:17:59.639371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
21021 11:17:59.639919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
21022 11:17:59.671403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
21023 11:17:59.671866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
21025 11:17:59.703119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
21027 11:17:59.703583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
21028 11:17:59.733283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
21030 11:17:59.733730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
21031 11:17:59.763130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
21032 11:17:59.763474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
21034 11:17:59.793790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
21035 11:17:59.794154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
21037 11:17:59.825388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
21038 11:17:59.825757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
21040 11:17:59.855190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
21041 11:17:59.855549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
21043 11:17:59.885636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
21044 11:17:59.886102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
21046 11:17:59.916315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
21047 11:17:59.916746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
21049 11:17:59.947048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
21050 11:17:59.947496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
21052 11:17:59.977290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
21054 11:17:59.977822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
21055 11:18:00.007576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
21056 11:18:00.008007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
21058 11:18:00.037718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
21059 11:18:00.038142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
21061 11:18:00.069001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
21062 11:18:00.069389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
21064 11:18:00.099151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
21065 11:18:00.099503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
21067 11:18:00.129332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
21069 11:18:00.129794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
21070 11:18:00.160389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
21071 11:18:00.160784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
21073 11:18:00.191110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
21074 11:18:00.191475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
21076 11:18:00.225572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
21077 11:18:00.226028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
21079 11:18:00.258979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
21080 11:18:00.259388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
21082 11:18:00.290340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
21084 11:18:00.290941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
21085 11:18:00.321293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
21086 11:18:00.321820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
21088 11:18:00.356520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
21089 11:18:00.357037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
21091 11:18:00.388035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
21093 11:18:00.388407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
21094 11:18:00.418959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
21095 11:18:00.419340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
21097 11:18:00.449546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
21098 11:18:00.449936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
21100 11:18:00.483105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
21102 11:18:00.483521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
21103 11:18:00.515212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
21105 11:18:00.515701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
21106 11:18:00.547365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
21107 11:18:00.547755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
21109 11:18:00.579629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
21111 11:18:00.580106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
21112 11:18:00.611451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
21113 11:18:00.611867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
21115 11:18:00.642090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
21117 11:18:00.642525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
21118 11:18:00.672975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
21119 11:18:00.673384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
21121 11:18:00.704326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
21122 11:18:00.704775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
21124 11:18:00.734955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
21125 11:18:00.735393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
21127 11:18:00.765715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
21128 11:18:00.766170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
21130 11:18:00.796785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
21131 11:18:00.797245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
21133 11:18:00.827513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
21134 11:18:00.827972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
21136 11:18:00.858562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
21137 11:18:00.858962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
21139 11:18:00.889608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
21140 11:18:00.890030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
21142 11:18:00.919845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
21143 11:18:00.920125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
21145 11:18:00.950976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
21147 11:18:00.951261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
21148 11:18:00.981170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
21149 11:18:00.981450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
21151 11:18:01.011586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
21152 11:18:01.011863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
21154 11:18:01.041525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
21155 11:18:01.041926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
21157 11:18:01.071941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
21158 11:18:01.072295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
21160 11:18:01.102435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
21162 11:18:01.102853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
21163 11:18:01.132206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
21164 11:18:01.132555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
21166 11:18:01.162665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
21167 11:18:01.162945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
21169 11:18:01.193030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
21170 11:18:01.193311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
21172 11:18:01.223289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
21173 11:18:01.223559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
21175 11:18:01.253659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
21176 11:18:01.253938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
21178 11:18:01.284070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
21179 11:18:01.284351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
21181 11:18:01.314800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
21183 11:18:01.315421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
21184 11:18:01.346038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
21186 11:18:01.346590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
21187 11:18:01.376262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
21189 11:18:01.376775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
21190 11:18:01.406629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
21192 11:18:01.407048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
21193 11:18:01.437177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
21195 11:18:01.437593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
21196 11:18:01.467086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
21198 11:18:01.467501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
21199 11:18:01.497431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
21200 11:18:01.497770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
21202 11:18:01.527894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
21204 11:18:01.528401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
21205 11:18:01.554576 <47>[ 192.758955] systemd-journald[109]: Sent WATCHDOG=1 notification.
21206 11:18:01.564714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
21207 11:18:01.565051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
21209 11:18:01.595939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
21211 11:18:01.596342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
21212 11:18:01.626663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
21213 11:18:01.626998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
21215 11:18:01.657382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
21216 11:18:01.657728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
21218 11:18:01.687624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
21219 11:18:01.687906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
21221 11:18:01.719427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
21223 11:18:01.719779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
21224 11:18:01.750232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21226 11:18:01.750698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
21227 11:18:01.783315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21229 11:18:01.783798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21230 11:18:01.814746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21231 11:18:01.815155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21233 11:18:01.845750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21234 11:18:01.846223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21236 11:18:01.876756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21237 11:18:01.877221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21239 11:18:01.907170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21240 11:18:01.907635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21242 11:18:01.939177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21243 11:18:01.939638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21245 11:18:01.969467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21247 11:18:01.969918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21248 11:18:02.000078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21249 11:18:02.000520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21251 11:18:02.030699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21252 11:18:02.031147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21254 11:18:02.061994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21256 11:18:02.062539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21257 11:18:02.092406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21259 11:18:02.093019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21260 11:18:02.122955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21262 11:18:02.123486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21263 11:18:02.153431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21265 11:18:02.153974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21266 11:18:02.183681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21268 11:18:02.184092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21269 11:18:02.213926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21271 11:18:02.214367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21272 11:18:02.245122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21273 11:18:02.245523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21275 11:18:02.276944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21277 11:18:02.277495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21278 11:18:02.307614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21279 11:18:02.308046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21281 11:18:02.339013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21282 11:18:02.339450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21284 11:18:02.369249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21285 11:18:02.369696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21287 11:18:02.400028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21288 11:18:02.400426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21290 11:18:02.430005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21292 11:18:02.430284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21293 11:18:02.460576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21295 11:18:02.460845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21296 11:18:02.490933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21297 11:18:02.491204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21299 11:18:02.521328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21300 11:18:02.521774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21302 11:18:02.551819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21304 11:18:02.552319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21305 11:18:02.583106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21306 11:18:02.583463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21308 11:18:02.613832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21309 11:18:02.614178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21311 11:18:02.648995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21312 11:18:02.649431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21314 11:18:02.680343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21315 11:18:02.680710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21317 11:18:02.711048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21319 11:18:02.711547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21320 11:18:02.741041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21321 11:18:02.741405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21323 11:18:02.772359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21324 11:18:02.772704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21326 11:18:02.803031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21328 11:18:02.803463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21329 11:18:02.832960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21331 11:18:02.833452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21332 11:18:02.863624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21333 11:18:02.863901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21335 11:18:02.894239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21337 11:18:02.894644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21338 11:18:02.929468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21339 11:18:02.929840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21341 11:18:02.960614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21343 11:18:02.961155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21344 11:18:02.991772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21346 11:18:02.992317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21347 11:18:03.023039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21348 11:18:03.023479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21350 11:18:03.054662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21351 11:18:03.055117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21353 11:18:03.107535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21354 11:18:03.107894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21356 11:18:03.143775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21357 11:18:03.144137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21359 11:18:03.174529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21361 11:18:03.174963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21362 11:18:03.205748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21363 11:18:03.206169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21365 11:18:03.235748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21367 11:18:03.236165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21368 11:18:03.266311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21369 11:18:03.266727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21371 11:18:03.297065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21372 11:18:03.297484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21374 11:18:03.327460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21375 11:18:03.327873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21377 11:18:03.358940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21379 11:18:03.359374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21380 11:18:03.389812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21381 11:18:03.390264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21383 11:18:03.420678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21384 11:18:03.421162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21386 11:18:03.451022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21387 11:18:03.451441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21389 11:18:03.481677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21390 11:18:03.482089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21392 11:18:03.513040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21393 11:18:03.513511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21395 11:18:03.544077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21397 11:18:03.544609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21398 11:18:03.575138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21399 11:18:03.575566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21401 11:18:03.606663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21403 11:18:03.607117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21404 11:18:03.636917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21405 11:18:03.637326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21407 11:18:03.667654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21409 11:18:03.668193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21410 11:18:03.698373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21412 11:18:03.698915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21413 11:18:03.728762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21414 11:18:03.729203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21416 11:18:03.759750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21417 11:18:03.760190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21419 11:18:03.791312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21421 11:18:03.791748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21422 11:18:03.822372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21424 11:18:03.822811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21425 11:18:03.853040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21427 11:18:03.853470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21428 11:18:03.883537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21430 11:18:03.883969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21431 11:18:03.913784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21433 11:18:03.914320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21434 11:18:03.944945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21436 11:18:03.945481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21437 11:18:03.975405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21439 11:18:03.975970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21440 11:18:04.005361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21442 11:18:04.005946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21443 11:18:04.036391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21445 11:18:04.036922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21446 11:18:04.067002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21447 11:18:04.067432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21449 11:18:04.097060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21450 11:18:04.097500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21452 11:18:04.127552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21453 11:18:04.128017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21455 11:18:04.160436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21457 11:18:04.160976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21458 11:18:04.191408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21459 11:18:04.191841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21461 11:18:04.224254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21462 11:18:04.224697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21464 11:18:04.261717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21466 11:18:04.262176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21467 11:18:04.295830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21468 11:18:04.296251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21470 11:18:04.329394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21471 11:18:04.329791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21473 11:18:04.360712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21474 11:18:04.361067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21476 11:18:04.391582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21477 11:18:04.392049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21479 11:18:04.424197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21481 11:18:04.424823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21482 11:18:04.455517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21483 11:18:04.455964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21485 11:18:04.486455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21487 11:18:04.487053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21488 11:18:04.517801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21489 11:18:04.518167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21491 11:18:04.548395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21492 11:18:04.548772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21494 11:18:04.579103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21495 11:18:04.579542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21497 11:18:04.610241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21499 11:18:04.610728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21500 11:18:04.642699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21502 11:18:04.643446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21503 11:18:04.673459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21504 11:18:04.673903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21506 11:18:04.704539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21507 11:18:04.704984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21509 11:18:04.735177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21510 11:18:04.735623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21512 11:18:04.765601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21513 11:18:04.766098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21515 11:18:04.796799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21517 11:18:04.797268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21518 11:18:04.827058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21519 11:18:04.827414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21521 11:18:04.857344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21522 11:18:04.857808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21524 11:18:04.888000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21525 11:18:04.888440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21527 11:18:04.918851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21528 11:18:04.919208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21530 11:18:04.950636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21532 11:18:04.951144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21533 11:18:04.980964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21535 11:18:04.981416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21536 11:18:05.010991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21537 11:18:05.011387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21539 11:18:05.041399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21541 11:18:05.041944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21542 11:18:05.071527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21543 11:18:05.071970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21545 11:18:05.101421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21546 11:18:05.101813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21548 11:18:05.132195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21549 11:18:05.132576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21551 11:18:05.162704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21552 11:18:05.163086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21554 11:18:05.193145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21556 11:18:05.193586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21557 11:18:05.223402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21558 11:18:05.223752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21560 11:18:05.254034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21562 11:18:05.254514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21563 11:18:05.288402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21564 11:18:05.288783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21566 11:18:05.318990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21567 11:18:05.319351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21569 11:18:05.350401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21570 11:18:05.350771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21572 11:18:05.380764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21574 11:18:05.381324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21575 11:18:05.413351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21576 11:18:05.413816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21578 11:18:05.445727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21580 11:18:05.446288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21581 11:18:05.476962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21583 11:18:05.477498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21584 11:18:05.508076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21585 11:18:05.508482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21587 11:18:05.539170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21588 11:18:05.539572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21590 11:18:05.569857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21592 11:18:05.570412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21593 11:18:05.600788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21594 11:18:05.601240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21596 11:18:05.630733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21597 11:18:05.631197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21599 11:18:05.660331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21600 11:18:05.660690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21602 11:18:05.690996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21603 11:18:05.691351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21605 11:18:05.720683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21607 11:18:05.721093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21608 11:18:05.750791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21610 11:18:05.751234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21611 11:18:05.781957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21613 11:18:05.782401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21614 11:18:05.812257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21615 11:18:05.812653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21617 11:18:05.843048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21618 11:18:05.843495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21620 11:18:05.873096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21621 11:18:05.873547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21623 11:18:05.903717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21625 11:18:05.904147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21626 11:18:05.935080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21627 11:18:05.935481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21629 11:18:05.966574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21630 11:18:05.967001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21632 11:18:05.997590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21633 11:18:05.998009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21635 11:18:06.028404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21636 11:18:06.028817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21638 11:18:06.058656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21639 11:18:06.059023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21641 11:18:06.088898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21642 11:18:06.089251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21644 11:18:06.119069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21645 11:18:06.119412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21647 11:18:06.149331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21648 11:18:06.149685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21650 11:18:06.179857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21651 11:18:06.180197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21653 11:18:06.210790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21655 11:18:06.211227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21656 11:18:06.240756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21657 11:18:06.241276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21659 11:18:06.273699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21661 11:18:06.274105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21662 11:18:06.304125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21664 11:18:06.304519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21665 11:18:06.334995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21667 11:18:06.335546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21668 11:18:06.365053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21669 11:18:06.365457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21671 11:18:06.395892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21672 11:18:06.396344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21674 11:18:06.426781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21676 11:18:06.427303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21677 11:18:06.457205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21678 11:18:06.457662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21680 11:18:06.487256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21681 11:18:06.487615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21683 11:18:06.517673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21684 11:18:06.518061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21686 11:18:06.547636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21687 11:18:06.548021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21689 11:18:06.578696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21690 11:18:06.579033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21692 11:18:06.608958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21693 11:18:06.609304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21695 11:18:06.639483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21696 11:18:06.639832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21698 11:18:06.671490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21699 11:18:06.671948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21701 11:18:06.702589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21702 11:18:06.703053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21704 11:18:06.733171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21705 11:18:06.733611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21707 11:18:06.764103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21708 11:18:06.764560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21710 11:18:06.794658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21711 11:18:06.795108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21713 11:18:06.824907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21715 11:18:06.825437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21716 11:18:06.855776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21717 11:18:06.856177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21719 11:18:06.886883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21720 11:18:06.887317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21722 11:18:06.918787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21724 11:18:06.919431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21725 11:18:06.950103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21727 11:18:06.950692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21728 11:18:06.980954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21730 11:18:06.981511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21731 11:18:07.012206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21733 11:18:07.012765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21734 11:18:07.044571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21735 11:18:07.044982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21737 11:18:07.075006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21738 11:18:07.075423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21740 11:18:07.105739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21741 11:18:07.106194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21743 11:18:07.136088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21744 11:18:07.136571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21746 11:18:07.166733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21748 11:18:07.167252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21749 11:18:07.196855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21751 11:18:07.197420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21752 11:18:07.226974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21754 11:18:07.227427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21755 11:18:07.257047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21757 11:18:07.257624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21758 11:18:07.287169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21760 11:18:07.287788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21761 11:18:07.317575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21762 11:18:07.317991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21764 11:18:07.348305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21765 11:18:07.348710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21767 11:18:07.379110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21768 11:18:07.379563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21770 11:18:07.409460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21771 11:18:07.409933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21773 11:18:07.441515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21774 11:18:07.442002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21776 11:18:07.472700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21777 11:18:07.473139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21779 11:18:07.503086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21780 11:18:07.503562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21782 11:18:07.533192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21784 11:18:07.533734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21785 11:18:07.564412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21787 11:18:07.564918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21788 11:18:07.594226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21789 11:18:07.594646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21791 11:18:07.624329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21792 11:18:07.624725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21794 11:18:07.654938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21796 11:18:07.655401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21797 11:18:07.684858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21798 11:18:07.685262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21800 11:18:07.714826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21801 11:18:07.715267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21803 11:18:07.745272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21804 11:18:07.745687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21806 11:18:07.775461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21807 11:18:07.775887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21809 11:18:07.805508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21810 11:18:07.805973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21812 11:18:07.835941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21813 11:18:07.836408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21815 11:18:07.866806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21816 11:18:07.867264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21818 11:18:07.897815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21819 11:18:07.898227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21821 11:18:07.928932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21822 11:18:07.929326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21824 11:18:07.959545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21826 11:18:07.959975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21827 11:18:07.989919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21829 11:18:07.990520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21830 11:18:08.021046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21832 11:18:08.021568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21833 11:18:08.051542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21834 11:18:08.051991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21836 11:18:08.082693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21838 11:18:08.083239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21839 11:18:08.112977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21840 11:18:08.113387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21842 11:18:08.143754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21844 11:18:08.144306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21845 11:18:08.174135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21847 11:18:08.174668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21848 11:18:08.232128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21850 11:18:08.232667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21851 11:18:08.263237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21852 11:18:08.263693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21854 11:18:08.293454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21855 11:18:08.293905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21857 11:18:08.324684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21858 11:18:08.325142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21860 11:18:08.355008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21861 11:18:08.355476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21863 11:18:08.385540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21864 11:18:08.385999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21866 11:18:08.417077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21868 11:18:08.417624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21869 11:18:08.447102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21870 11:18:08.447458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21872 11:18:08.477243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21873 11:18:08.477588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21875 11:18:08.507686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21876 11:18:08.508028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21878 11:18:08.537560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21879 11:18:08.537946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21881 11:18:08.567957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21882 11:18:08.568297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21884 11:18:08.597983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21885 11:18:08.598404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21887 11:18:08.630613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21888 11:18:08.631160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21890 11:18:08.661199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21891 11:18:08.661707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21893 11:18:08.690830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21894 11:18:08.691367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21896 11:18:08.721364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21897 11:18:08.721781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21899 11:18:08.751989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21900 11:18:08.752463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21902 11:18:08.782439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21904 11:18:08.782960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21905 11:18:08.812424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21907 11:18:08.812948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21908 11:18:08.843132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21909 11:18:08.843556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21911 11:18:08.873003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21912 11:18:08.873436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21914 11:18:08.903960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21915 11:18:08.904404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21917 11:18:08.934697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21919 11:18:08.935198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21920 11:18:08.964635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21921 11:18:08.965051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21923 11:18:08.994809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21924 11:18:08.995243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21926 11:18:09.024923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21928 11:18:09.025496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21929 11:18:09.054889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21930 11:18:09.055352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21932 11:18:09.084283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21933 11:18:09.084743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21935 11:18:09.114265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21937 11:18:09.114635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21938 11:18:09.144379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21939 11:18:09.144834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21941 11:18:09.176626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21942 11:18:09.177112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21944 11:18:09.208634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21946 11:18:09.209177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21947 11:18:09.241285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21948 11:18:09.241750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21950 11:18:09.274690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21952 11:18:09.275223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21953 11:18:09.308073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21954 11:18:09.308541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21956 11:18:09.341171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21957 11:18:09.341638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21959 11:18:09.371486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21961 11:18:09.372006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21962 11:18:09.404293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21963 11:18:09.404840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21965 11:18:09.435159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21966 11:18:09.435621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21968 11:18:09.465805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21969 11:18:09.466258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21971 11:18:09.496237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21973 11:18:09.496863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21974 11:18:09.526114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21976 11:18:09.526677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21977 11:18:09.556484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21978 11:18:09.556832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21980 11:18:09.586877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
21981 11:18:09.587302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
21983 11:18:09.616891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
21984 11:18:09.617346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
21986 11:18:09.647917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
21988 11:18:09.648460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
21989 11:18:09.677790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
21990 11:18:09.678265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
21992 11:18:09.708033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
21993 11:18:09.708483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
21995 11:18:09.739907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
21997 11:18:09.740345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
21998 11:18:09.771433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
21999 11:18:09.771821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
22001 11:18:09.801564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
22002 11:18:09.802000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
22004 11:18:09.832656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
22006 11:18:09.833098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
22007 11:18:09.863355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
22009 11:18:09.863907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
22010 11:18:09.894660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
22012 11:18:09.895204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
22013 11:18:09.925140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
22015 11:18:09.925689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
22016 11:18:09.955863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
22017 11:18:09.956303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
22019 11:18:09.986418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
22020 11:18:09.986844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
22022 11:18:10.016681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
22023 11:18:10.017126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
22025 11:18:10.047125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
22027 11:18:10.047669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
22028 11:18:10.076924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
22029 11:18:10.077262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
22031 11:18:10.106970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
22032 11:18:10.107306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
22034 11:18:10.137992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
22036 11:18:10.138504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
22037 11:18:10.169019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
22039 11:18:10.169626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
22040 11:18:10.199182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
22042 11:18:10.199636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
22043 11:18:10.229808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
22045 11:18:10.230259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
22046 11:18:10.260986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
22047 11:18:10.261459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
22049 11:18:10.292877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
22050 11:18:10.293340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
22052 11:18:10.324179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
22053 11:18:10.324527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
22055 11:18:10.354638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
22056 11:18:10.354984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
22058 11:18:10.384335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
22059 11:18:10.384676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
22061 11:18:10.414448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
22062 11:18:10.414956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
22064 11:18:10.444899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
22065 11:18:10.445365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
22067 11:18:10.475345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
22068 11:18:10.475806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
22070 11:18:10.505768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
22071 11:18:10.506224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
22073 11:18:10.536848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
22074 11:18:10.537299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
22076 11:18:10.567233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
22078 11:18:10.567770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
22079 11:18:10.597379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
22081 11:18:10.597872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
22082 11:18:10.627148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
22083 11:18:10.627487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
22085 11:18:10.657844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
22086 11:18:10.658200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
22088 11:18:10.690174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
22090 11:18:10.690626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
22091 11:18:10.721530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
22092 11:18:10.721902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
22094 11:18:10.753175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
22095 11:18:10.753677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
22097 11:18:10.783985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
22099 11:18:10.784435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
22100 11:18:10.814218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
22102 11:18:10.814639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
22103 11:18:10.843984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
22104 11:18:10.844328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
22106 11:18:10.874868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
22107 11:18:10.875332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
22109 11:18:10.905705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
22110 11:18:10.906085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
22112 11:18:10.936195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
22113 11:18:10.936643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
22115 11:18:10.966989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
22116 11:18:10.967439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
22118 11:18:10.998023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
22120 11:18:10.998544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
22121 11:18:11.028112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
22122 11:18:11.028506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
22124 11:18:11.057778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
22125 11:18:11.058137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
22127 11:18:11.088020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
22128 11:18:11.088366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
22130 11:18:11.118626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
22131 11:18:11.118960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
22133 11:18:11.150816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
22135 11:18:11.151308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
22136 11:18:11.182662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
22137 11:18:11.183048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
22139 11:18:11.213605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
22141 11:18:11.214185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
22142 11:18:11.251465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
22143 11:18:11.251931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
22145 11:18:11.284027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
22147 11:18:11.284561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
22148 11:18:11.315406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
22149 11:18:11.315855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
22151 11:18:11.346742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
22152 11:18:11.347196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
22154 11:18:11.378033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
22156 11:18:11.378467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
22157 11:18:11.409145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
22158 11:18:11.409583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
22160 11:18:11.440079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
22162 11:18:11.440605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
22163 11:18:11.470994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
22164 11:18:11.471439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
22166 11:18:11.501700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
22167 11:18:11.502164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
22169 11:18:11.532618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
22171 11:18:11.533162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
22172 11:18:11.562855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
22173 11:18:11.563246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
22175 11:18:11.593767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
22176 11:18:11.594194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
22178 11:18:11.624259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
22179 11:18:11.624686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
22181 11:18:11.654823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
22182 11:18:11.655173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
22184 11:18:11.685327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
22185 11:18:11.685672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
22187 11:18:11.716109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
22188 11:18:11.716455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
22190 11:18:11.746638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
22192 11:18:11.747180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
22193 11:18:11.776404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
22194 11:18:11.776836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
22196 11:18:11.807492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
22197 11:18:11.807933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
22199 11:18:11.838598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
22200 11:18:11.839054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
22202 11:18:11.870065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
22204 11:18:11.870656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
22205 11:18:11.900682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
22207 11:18:11.901281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
22208 11:18:11.931993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
22209 11:18:11.932449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
22211 11:18:11.963099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
22212 11:18:11.963562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
22214 11:18:11.993909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
22216 11:18:11.994481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
22217 11:18:12.024937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
22219 11:18:12.025465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
22220 11:18:12.055485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
22221 11:18:12.055926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
22223 11:18:12.085835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22224 11:18:12.086270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
22226 11:18:12.116541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22227 11:18:12.116982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22229 11:18:12.147521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22230 11:18:12.147952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22232 11:18:12.178814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22233 11:18:12.179238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22235 11:18:12.208602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22236 11:18:12.208939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22238 11:18:12.241055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22240 11:18:12.241566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22241 11:18:12.271569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22242 11:18:12.271921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22244 11:18:12.302070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22246 11:18:12.302508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22247 11:18:12.332108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22248 11:18:12.332438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22250 11:18:12.363041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22252 11:18:12.363584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22253 11:18:12.392911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22254 11:18:12.393282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22256 11:18:12.423019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22258 11:18:12.423414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22259 11:18:12.453601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22260 11:18:12.453973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22262 11:18:12.484563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22263 11:18:12.484896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22265 11:18:12.515421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22267 11:18:12.515855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22268 11:18:12.546704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22270 11:18:12.547158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22271 11:18:12.577040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22272 11:18:12.577401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22274 11:18:12.607139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22275 11:18:12.607619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22277 11:18:12.637721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22278 11:18:12.638169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22280 11:18:12.668593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22282 11:18:12.669160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22283 11:18:12.700259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22284 11:18:12.700703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22286 11:18:12.731478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22287 11:18:12.731955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22289 11:18:12.762704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22291 11:18:12.763221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22292 11:18:12.793556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22293 11:18:12.794021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22295 11:18:12.825455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22297 11:18:12.825920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22298 11:18:12.859898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22299 11:18:12.860311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22301 11:18:12.891820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22302 11:18:12.892236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22304 11:18:12.923906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22305 11:18:12.924314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22307 11:18:12.955231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22308 11:18:12.955636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22310 11:18:12.988617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22311 11:18:12.989075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22313 11:18:13.021246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22315 11:18:13.021987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22316 11:18:13.053249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22317 11:18:13.053768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22319 11:18:13.086567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22320 11:18:13.087101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22322 11:18:13.118976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22324 11:18:13.119501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22325 11:18:13.151763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22327 11:18:13.152058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22328 11:18:13.184102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22329 11:18:13.184402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22331 11:18:13.214987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22332 11:18:13.215331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22334 11:18:13.245717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22335 11:18:13.246072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22337 11:18:13.278928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22338 11:18:13.279283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22340 11:18:13.311740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22341 11:18:13.312082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22343 11:18:13.365205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22344 11:18:13.365582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22346 11:18:13.405080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22347 11:18:13.405431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22349 11:18:13.435193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22350 11:18:13.435544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22352 11:18:13.465354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22354 11:18:13.465800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22355 11:18:13.495037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22356 11:18:13.495420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22358 11:18:13.525353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22360 11:18:13.525824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22361 11:18:13.555228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22362 11:18:13.555591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22364 11:18:13.585515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22366 11:18:13.585945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22367 11:18:13.615039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22368 11:18:13.615381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22370 11:18:13.644932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22371 11:18:13.645389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22373 11:18:13.675773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22374 11:18:13.676162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22376 11:18:13.705921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22378 11:18:13.706219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22379 11:18:13.736157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22380 11:18:13.736432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22382 11:18:13.766713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22384 11:18:13.767125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22385 11:18:13.796967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22386 11:18:13.797311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22388 11:18:13.827319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22389 11:18:13.827776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22391 11:18:13.857720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22392 11:18:13.858150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22394 11:18:13.889902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22395 11:18:13.890370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22397 11:18:13.920929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22399 11:18:13.921530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22400 11:18:13.951089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22401 11:18:13.951528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22403 11:18:13.981318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22404 11:18:13.981682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22406 11:18:14.012196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22407 11:18:14.012600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22409 11:18:14.043211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22410 11:18:14.043614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22412 11:18:14.074288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22414 11:18:14.074855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22415 11:18:14.105387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22417 11:18:14.105956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22418 11:18:14.136954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22419 11:18:14.137408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22421 11:18:14.167665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22422 11:18:14.168025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22424 11:18:14.209331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22426 11:18:14.209932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22427 11:18:14.247337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22428 11:18:14.247702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22430 11:18:14.278484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22431 11:18:14.278836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22433 11:18:14.309273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22434 11:18:14.309633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22436 11:18:14.340422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22438 11:18:14.340966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22439 11:18:14.371390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22440 11:18:14.371837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22442 11:18:14.403440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22444 11:18:14.404221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22445 11:18:14.435042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22446 11:18:14.435408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22448 11:18:14.465255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22449 11:18:14.465582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22451 11:18:14.495553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22453 11:18:14.495938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22454 11:18:14.525764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22455 11:18:14.526101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22457 11:18:14.557029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22459 11:18:14.557481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22460 11:18:14.587832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22461 11:18:14.588217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22463 11:18:14.618511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22465 11:18:14.619077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22466 11:18:14.648546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22467 11:18:14.648924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22469 11:18:14.678878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22470 11:18:14.679216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22472 11:18:14.708755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22473 11:18:14.709097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22475 11:18:14.739384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22476 11:18:14.739721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22478 11:18:14.769397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22479 11:18:14.769745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22481 11:18:14.800338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22482 11:18:14.800695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22484 11:18:14.831147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22486 11:18:14.831580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22487 11:18:14.862352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22488 11:18:14.862712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22490 11:18:14.893394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22492 11:18:14.893815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22493 11:18:14.923535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22494 11:18:14.923912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22496 11:18:14.955183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22497 11:18:14.955671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22499 11:18:14.989584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22500 11:18:14.990160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22502 11:18:15.021363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22503 11:18:15.021758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22505 11:18:15.052241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22506 11:18:15.052556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22508 11:18:15.083544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22509 11:18:15.084014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22511 11:18:15.114508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22512 11:18:15.115005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22514 11:18:15.149949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22516 11:18:15.150350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22517 11:18:15.180923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22518 11:18:15.181390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22520 11:18:15.211282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22521 11:18:15.211694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22523 11:18:15.242871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22524 11:18:15.243231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22526 11:18:15.274080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22528 11:18:15.274371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22529 11:18:15.304985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22531 11:18:15.305430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22532 11:18:15.335677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22533 11:18:15.336028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22535 11:18:15.366506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22536 11:18:15.366845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22538 11:18:15.399257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22539 11:18:15.399624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22541 11:18:15.433529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22542 11:18:15.433978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22544 11:18:15.466924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22545 11:18:15.467383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22547 11:18:15.499213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22549 11:18:15.499846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22550 11:18:15.531898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22551 11:18:15.532365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22553 11:18:15.565855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22554 11:18:15.566309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22556 11:18:15.597732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22557 11:18:15.598235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22559 11:18:15.630289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22561 11:18:15.630907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22562 11:18:15.662845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22563 11:18:15.663313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22565 11:18:15.694925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22567 11:18:15.695526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22568 11:18:15.727315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22570 11:18:15.727766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22571 11:18:15.760710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22572 11:18:15.761179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22574 11:18:15.793543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22575 11:18:15.794028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22577 11:18:15.825298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22578 11:18:15.825762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22580 11:18:15.855875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22581 11:18:15.856347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22583 11:18:15.886591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22584 11:18:15.887028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22586 11:18:15.917496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22587 11:18:15.917945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22589 11:18:15.948133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22591 11:18:15.948672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22592 11:18:15.978469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22593 11:18:15.978819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22595 11:18:16.008886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22596 11:18:16.009240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22598 11:18:16.040960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22599 11:18:16.041357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22601 11:18:16.071484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22603 11:18:16.071916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22604 11:18:16.102068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22606 11:18:16.102491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22607 11:18:16.132243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22608 11:18:16.132627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22610 11:18:16.164799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22611 11:18:16.165230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22613 11:18:16.196363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22614 11:18:16.196826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22616 11:18:16.227196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22617 11:18:16.227543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22619 11:18:16.257917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22620 11:18:16.258384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22622 11:18:16.289265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22623 11:18:16.289697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22625 11:18:16.320273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22626 11:18:16.320729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22628 11:18:16.350739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22629 11:18:16.351079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22631 11:18:16.380545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22632 11:18:16.380889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22634 11:18:16.412366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22635 11:18:16.412807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22637 11:18:16.444314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22639 11:18:16.444830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22640 11:18:16.475784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22641 11:18:16.476196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22643 11:18:16.509535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22644 11:18:16.509935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22646 11:18:16.547874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22648 11:18:16.548245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22649 11:18:16.579942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22651 11:18:16.580378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22652 11:18:16.611660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22654 11:18:16.612096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22655 11:18:16.642926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22656 11:18:16.643399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22658 11:18:16.672959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22659 11:18:16.673412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22661 11:18:16.703191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22662 11:18:16.703595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22664 11:18:16.733320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22665 11:18:16.733690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22667 11:18:16.764293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22668 11:18:16.764705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22670 11:18:16.795325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22671 11:18:16.795773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22673 11:18:16.826423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22674 11:18:16.826863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22676 11:18:16.856859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22677 11:18:16.857299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22679 11:18:16.887689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22680 11:18:16.888142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22682 11:18:16.919348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22684 11:18:16.919780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22685 11:18:16.949268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22687 11:18:16.949754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22688 11:18:16.980526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22689 11:18:16.980977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22691 11:18:17.013045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22692 11:18:17.013424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22694 11:18:17.046657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22695 11:18:17.047075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22697 11:18:17.079443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22698 11:18:17.079853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22700 11:18:17.112429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22701 11:18:17.112794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22703 11:18:17.144283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22704 11:18:17.144681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22706 11:18:17.177092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22707 11:18:17.177528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22709 11:18:17.208906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22710 11:18:17.209320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22712 11:18:17.242296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22713 11:18:17.242753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22715 11:18:17.272943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22716 11:18:17.273316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22718 11:18:17.305077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22719 11:18:17.305513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22721 11:18:17.336723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22722 11:18:17.337094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22724 11:18:17.368227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22725 11:18:17.368578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22727 11:18:17.402028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22729 11:18:17.402385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22730 11:18:17.433186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22731 11:18:17.433495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22733 11:18:17.464593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22734 11:18:17.464936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22736 11:18:17.495103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22737 11:18:17.495497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22739 11:18:17.531309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22741 11:18:17.531726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22742 11:18:17.562926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22743 11:18:17.563328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22745 11:18:17.595097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22746 11:18:17.595540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22748 11:18:17.626452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22749 11:18:17.626926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22751 11:18:17.657969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22753 11:18:17.658601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22754 11:18:17.689519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22755 11:18:17.690005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22757 11:18:17.720968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22758 11:18:17.721436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22760 11:18:17.751750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22761 11:18:17.752209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22763 11:18:17.783742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22764 11:18:17.784184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22766 11:18:17.815026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22767 11:18:17.815487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22769 11:18:17.845677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22770 11:18:17.846113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22772 11:18:17.877182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22773 11:18:17.877592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22775 11:18:17.908769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22776 11:18:17.909218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22778 11:18:17.940988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22779 11:18:17.941441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22781 11:18:17.972109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22783 11:18:17.972726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22784 11:18:18.003235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22786 11:18:18.003847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22787 11:18:18.034984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22788 11:18:18.035467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22790 11:18:18.066621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22791 11:18:18.067096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22793 11:18:18.097877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22794 11:18:18.098270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22796 11:18:18.130935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22797 11:18:18.131393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22799 11:18:18.163612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22800 11:18:18.164143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22802 11:18:18.196132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22803 11:18:18.196615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22805 11:18:18.228026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22807 11:18:18.228722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22808 11:18:18.265120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22809 11:18:18.265534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22811 11:18:18.301040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22812 11:18:18.301537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22814 11:18:18.334938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22815 11:18:18.335334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22817 11:18:18.368313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22818 11:18:18.368722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22820 11:18:18.401780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22821 11:18:18.402345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22823 11:18:18.443833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22825 11:18:18.444286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22826 11:18:18.511080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22827 11:18:18.511454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22829 11:18:18.546936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22830 11:18:18.547393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22832 11:18:18.580893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22833 11:18:18.581427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22835 11:18:18.615308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22836 11:18:18.615778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22838 11:18:18.648316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22839 11:18:18.648775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22841 11:18:18.681844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22842 11:18:18.682270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22844 11:18:18.714430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22845 11:18:18.714841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22847 11:18:18.745802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22849 11:18:18.746258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22850 11:18:18.777191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22851 11:18:18.777602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22853 11:18:18.808590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22854 11:18:18.809013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22856 11:18:18.841319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22858 11:18:18.841929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22859 11:18:18.875937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22861 11:18:18.876526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22862 11:18:18.907774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22863 11:18:18.908246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22865 11:18:18.946705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22866 11:18:18.947109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22868 11:18:18.979685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22869 11:18:18.979998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22871 11:18:19.012598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22872 11:18:19.012939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22874 11:18:19.046218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22876 11:18:19.046644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22877 11:18:19.079803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22878 11:18:19.080214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22880 11:18:19.114783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22882 11:18:19.115135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22883 11:18:19.150088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22885 11:18:19.150629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22886 11:18:19.184385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22887 11:18:19.184940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22889 11:18:19.217509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22890 11:18:19.218006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22892 11:18:19.251180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22893 11:18:19.251630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22895 11:18:19.282233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22897 11:18:19.282813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22898 11:18:19.313743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22899 11:18:19.314273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22901 11:18:19.345181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22902 11:18:19.345659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22904 11:18:19.376690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22905 11:18:19.377160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22907 11:18:19.407986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22908 11:18:19.408459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22910 11:18:19.440451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22911 11:18:19.440907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22913 11:18:19.472912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22914 11:18:19.473382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22916 11:18:19.504522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22917 11:18:19.504984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22919 11:18:19.535812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22920 11:18:19.536266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22922 11:18:19.568638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22923 11:18:19.569091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22925 11:18:19.600803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22926 11:18:19.601256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22928 11:18:19.634315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22930 11:18:19.634875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22931 11:18:19.666657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22932 11:18:19.667126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22934 11:18:19.698212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22936 11:18:19.698730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22937 11:18:19.730171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22939 11:18:19.730640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22940 11:18:19.761454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22941 11:18:19.761893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22943 11:18:19.792437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22944 11:18:19.792908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22946 11:18:19.824846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22947 11:18:19.825321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22949 11:18:19.856609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22951 11:18:19.857234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22952 11:18:19.887870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22953 11:18:19.888221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22955 11:18:19.919602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22956 11:18:19.919947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22958 11:18:19.950869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22959 11:18:19.951159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22961 11:18:19.981632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22962 11:18:19.981988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22964 11:18:20.012921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22965 11:18:20.013318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22967 11:18:20.044967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22968 11:18:20.045412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22970 11:18:20.077317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22971 11:18:20.077782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22973 11:18:20.108802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22974 11:18:20.109236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22976 11:18:20.140516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22977 11:18:20.140966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22979 11:18:20.172867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
22981 11:18:20.173437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22982 11:18:20.204395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
22983 11:18:20.204833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
22985 11:18:20.235878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
22987 11:18:20.236406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
22988 11:18:20.273463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
22989 11:18:20.273930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
22991 11:18:20.312014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
22992 11:18:20.312489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
22994 11:18:20.343623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
22995 11:18:20.344083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
22997 11:18:20.375199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
22999 11:18:20.375670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
23000 11:18:20.406434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
23002 11:18:20.406870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
23003 11:18:20.440333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
23005 11:18:20.440808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
23006 11:18:20.474136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
23008 11:18:20.474673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
23009 11:18:20.508814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
23011 11:18:20.509294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
23012 11:18:20.541395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
23013 11:18:20.541809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
23015 11:18:20.578202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
23017 11:18:20.578719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
23018 11:18:20.613158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
23019 11:18:20.613575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
23021 11:18:20.648061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
23022 11:18:20.648492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
23024 11:18:20.681221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
23026 11:18:20.681699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
23027 11:18:20.714763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
23029 11:18:20.715406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
23030 11:18:20.746662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
23031 11:18:20.747131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
23033 11:18:20.779242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
23034 11:18:20.779652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
23036 11:18:20.811217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
23037 11:18:20.811633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
23039 11:18:20.842729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
23040 11:18:20.843018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
23042 11:18:20.874795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
23043 11:18:20.875086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
23045 11:18:20.906814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
23046 11:18:20.907187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
23048 11:18:20.938638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
23049 11:18:20.939030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
23051 11:18:20.971302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
23053 11:18:20.971904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
23054 11:18:21.003011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
23055 11:18:21.003462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
23057 11:18:21.034670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
23058 11:18:21.035126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
23060 11:18:21.066824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
23061 11:18:21.067285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
23063 11:18:21.098604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
23064 11:18:21.099001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
23066 11:18:21.130904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
23067 11:18:21.131251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
23069 11:18:21.162363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
23070 11:18:21.162658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
23072 11:18:21.193996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
23074 11:18:21.194340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
23075 11:18:21.224672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
23076 11:18:21.225014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
23078 11:18:21.255619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
23080 11:18:21.256102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
23081 11:18:21.287152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
23083 11:18:21.287593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
23084 11:18:21.318400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
23085 11:18:21.318753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
23087 11:18:21.349495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
23088 11:18:21.349846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
23090 11:18:21.380875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
23091 11:18:21.381216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
23093 11:18:21.411366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
23094 11:18:21.411728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
23096 11:18:21.443026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
23098 11:18:21.443642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
23099 11:18:21.474066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
23101 11:18:21.474690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
23102 11:18:21.506931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
23104 11:18:21.507546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
23105 11:18:21.539035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
23107 11:18:21.539649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
23108 11:18:21.571163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
23109 11:18:21.571620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
23111 11:18:21.603186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
23112 11:18:21.603665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
23114 11:18:21.635263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
23116 11:18:21.635878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
23117 11:18:21.666825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
23119 11:18:21.667437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
23120 11:18:21.698853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
23122 11:18:21.699468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
23123 11:18:21.732285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
23124 11:18:21.732757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
23126 11:18:21.767205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
23127 11:18:21.767675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
23129 11:18:21.799653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
23130 11:18:21.800065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
23132 11:18:21.833704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
23134 11:18:21.834331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
23135 11:18:21.865314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
23136 11:18:21.865772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
23138 11:18:21.897485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
23139 11:18:21.897911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
23141 11:18:21.929468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
23142 11:18:21.929889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
23144 11:18:21.961189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
23145 11:18:21.961584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
23147 11:18:21.997145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
23148 11:18:21.997551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
23150 11:18:22.028918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
23151 11:18:22.029309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
23153 11:18:22.060054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
23154 11:18:22.060454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
23156 11:18:22.092090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
23157 11:18:22.092488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
23159 11:18:22.124235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
23160 11:18:22.124665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
23162 11:18:22.155607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
23163 11:18:22.155897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
23165 11:18:22.185711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
23166 11:18:22.186074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
23168 11:18:22.217498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
23169 11:18:22.217799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
23171 11:18:22.248544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
23172 11:18:22.248905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
23174 11:18:22.279314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
23175 11:18:22.279682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
23177 11:18:22.311072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
23178 11:18:22.311429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
23180 11:18:22.341802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
23181 11:18:22.342164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
23183 11:18:22.372242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
23184 11:18:22.372607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
23186 11:18:22.403276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
23187 11:18:22.403640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
23189 11:18:22.437613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
23190 11:18:22.438002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
23192 11:18:22.468632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
23193 11:18:22.468994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
23195 11:18:22.499016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
23196 11:18:22.499380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
23198 11:18:22.529835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
23199 11:18:22.530196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
23201 11:18:22.561074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
23202 11:18:22.561436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
23204 11:18:22.591905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
23205 11:18:22.592264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
23207 11:18:22.622638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
23209 11:18:22.623097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
23210 11:18:22.654232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
23212 11:18:22.654832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
23213 11:18:22.686347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
23214 11:18:22.686641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
23216 11:18:22.718669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
23217 11:18:22.719039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
23219 11:18:22.750153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
23221 11:18:22.750630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
23222 11:18:22.782397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
23223 11:18:22.782779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
23225 11:18:22.814744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23226 11:18:22.815122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23228 11:18:22.849024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23230 11:18:22.849602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23231 11:18:22.880333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23232 11:18:22.880710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23234 11:18:22.913331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23235 11:18:22.913797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23237 11:18:22.944990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23239 11:18:22.945456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23240 11:18:22.976624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23241 11:18:22.977023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23243 11:18:23.008708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23244 11:18:23.009111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23246 11:18:23.040031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23247 11:18:23.040434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23249 11:18:23.071348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23251 11:18:23.071788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23252 11:18:23.103066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23253 11:18:23.103482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23255 11:18:23.134614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23257 11:18:23.135042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23258 11:18:23.166727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23259 11:18:23.167108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23261 11:18:23.197700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23263 11:18:23.198102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23264 11:18:23.229103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23265 11:18:23.229527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23267 11:18:23.260788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23268 11:18:23.261169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23270 11:18:23.291911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23271 11:18:23.292296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23273 11:18:23.323205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23275 11:18:23.323762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23276 11:18:23.354814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23277 11:18:23.355286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23279 11:18:23.386910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23280 11:18:23.387324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23282 11:18:23.418843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23284 11:18:23.419289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23285 11:18:23.450423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23287 11:18:23.450866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23288 11:18:23.482392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23290 11:18:23.483022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23291 11:18:23.514886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23292 11:18:23.515360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23294 11:18:23.547213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23295 11:18:23.547672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23297 11:18:23.607299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23299 11:18:23.607852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23300 11:18:23.639211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23301 11:18:23.639638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23303 11:18:23.671807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23304 11:18:23.672222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23306 11:18:23.704904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23307 11:18:23.705325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23309 11:18:23.737642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23311 11:18:23.738038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23312 11:18:23.771156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23313 11:18:23.771450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23315 11:18:23.803743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23316 11:18:23.804125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23318 11:18:23.836961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23319 11:18:23.837327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23321 11:18:23.870581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23322 11:18:23.870917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23324 11:18:23.903262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23326 11:18:23.903696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23327 11:18:23.935290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23328 11:18:23.935664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23330 11:18:23.967241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23331 11:18:23.967650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23333 11:18:24.000500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23334 11:18:24.000925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23336 11:18:24.033037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23337 11:18:24.033335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23339 11:18:24.067051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23340 11:18:24.067341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23342 11:18:24.099283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23343 11:18:24.099690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23345 11:18:24.131798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23347 11:18:24.132249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23348 11:18:24.164840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23349 11:18:24.165256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23351 11:18:24.197219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23353 11:18:24.197681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23354 11:18:24.231177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23355 11:18:24.231659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23357 11:18:24.263264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23359 11:18:24.263825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23360 11:18:24.295173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23362 11:18:24.295903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23363 11:18:24.327235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23364 11:18:24.327702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23366 11:18:24.359112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23367 11:18:24.359545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23369 11:18:24.391276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23371 11:18:24.391719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23372 11:18:24.423298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23373 11:18:24.423711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23375 11:18:24.455383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23376 11:18:24.455843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23378 11:18:24.489560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23379 11:18:24.490048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23381 11:18:24.522502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23382 11:18:24.522857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23384 11:18:24.554118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23386 11:18:24.554578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23387 11:18:24.585627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23388 11:18:24.585918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23390 11:18:24.617147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23391 11:18:24.617504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23393 11:18:24.651188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23394 11:18:24.651544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23396 11:18:24.684575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23398 11:18:24.685004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23399 11:18:24.718217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23401 11:18:24.718532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23402 11:18:24.751321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23403 11:18:24.751617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23405 11:18:24.792588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23407 11:18:24.793106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23408 11:18:24.830254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23410 11:18:24.830778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23411 11:18:24.865620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23412 11:18:24.865994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23414 11:18:24.901043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23415 11:18:24.901350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23417 11:18:24.943971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23418 11:18:24.944383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23420 11:18:24.980900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23421 11:18:24.981375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23423 11:18:25.012775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23425 11:18:25.013506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23426 11:18:25.045090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23428 11:18:25.045544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23429 11:18:25.078834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23430 11:18:25.079385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23432 11:18:25.112397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23433 11:18:25.112940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23435 11:18:25.146868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23436 11:18:25.147279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23438 11:18:25.180689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23439 11:18:25.181093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23441 11:18:25.212705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23443 11:18:25.213148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23444 11:18:25.245659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23445 11:18:25.246052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23447 11:18:25.277446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23448 11:18:25.277741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23450 11:18:25.309522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23451 11:18:25.309837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23453 11:18:25.343914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23454 11:18:25.344233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23456 11:18:25.377035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23458 11:18:25.377395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23459 11:18:25.408496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23461 11:18:25.408944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23462 11:18:25.439549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23463 11:18:25.440023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23465 11:18:25.470487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23466 11:18:25.470961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23468 11:18:25.501413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23469 11:18:25.501898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23471 11:18:25.532328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23472 11:18:25.532775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23474 11:18:25.563808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23476 11:18:25.564266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23477 11:18:25.593912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23479 11:18:25.594301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23480 11:18:25.624181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23481 11:18:25.624543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23483 11:18:25.654999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23484 11:18:25.655293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23486 11:18:25.685701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23487 11:18:25.686066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23489 11:18:25.716845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23490 11:18:25.717134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23492 11:18:25.747729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23493 11:18:25.748170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23495 11:18:25.778653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23496 11:18:25.779052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23498 11:18:25.809895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23500 11:18:25.810313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23501 11:18:25.840409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23503 11:18:25.840839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23504 11:18:25.871284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23505 11:18:25.871696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23507 11:18:25.902290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23509 11:18:25.902626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23510 11:18:25.933467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23511 11:18:25.933837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23513 11:18:25.965511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23514 11:18:25.965804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23516 11:18:25.996348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23517 11:18:25.996697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23519 11:18:26.026903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23520 11:18:26.027264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23522 11:18:26.057856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23523 11:18:26.058241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23525 11:18:26.088983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23527 11:18:26.089427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23528 11:18:26.120014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23529 11:18:26.120401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23531 11:18:26.152474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23533 11:18:26.153052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23534 11:18:26.184360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23536 11:18:26.184907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23537 11:18:26.215308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23538 11:18:26.215779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23540 11:18:26.246555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23541 11:18:26.247017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23543 11:18:26.277497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23544 11:18:26.277994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23546 11:18:26.309727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23547 11:18:26.310181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23549 11:18:26.342930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23550 11:18:26.343416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23552 11:18:26.375045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23553 11:18:26.375530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23555 11:18:26.406735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23557 11:18:26.407364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23558 11:18:26.438631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23559 11:18:26.439076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23561 11:18:26.469735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23562 11:18:26.470180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23564 11:18:26.501898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23565 11:18:26.502272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23567 11:18:26.532758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23568 11:18:26.533228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23570 11:18:26.564117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23571 11:18:26.564521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23573 11:18:26.595332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23574 11:18:26.595731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23576 11:18:26.626977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23578 11:18:26.627514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23579 11:18:26.658125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23581 11:18:26.658652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23582 11:18:26.689713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23583 11:18:26.690080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23585 11:18:26.721658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23586 11:18:26.722159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23588 11:18:26.754118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23590 11:18:26.754749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23591 11:18:26.791846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23592 11:18:26.792227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23594 11:18:26.826977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23596 11:18:26.827438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23597 11:18:26.860496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23598 11:18:26.860913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23600 11:18:26.903713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23601 11:18:26.904106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23603 11:18:26.944702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23604 11:18:26.945173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23606 11:18:26.977774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23607 11:18:26.978252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23609 11:18:27.020715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23610 11:18:27.021140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23612 11:18:27.057231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23614 11:18:27.057844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23615 11:18:27.089423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23616 11:18:27.089849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23618 11:18:27.119547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23619 11:18:27.119959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23621 11:18:27.153320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23622 11:18:27.153746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23624 11:18:27.188136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23625 11:18:27.188515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23627 11:18:27.221640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23628 11:18:27.222037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23630 11:18:27.255563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23631 11:18:27.255976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23633 11:18:27.287460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23635 11:18:27.287918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23636 11:18:27.322603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23637 11:18:27.323092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23639 11:18:27.354690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23640 11:18:27.355159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23642 11:18:27.388280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23644 11:18:27.388688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23645 11:18:27.421153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23647 11:18:27.421546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23648 11:18:27.454123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23650 11:18:27.454469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23651 11:18:27.488484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23652 11:18:27.488842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23654 11:18:27.522591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23655 11:18:27.523025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23657 11:18:27.556925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23659 11:18:27.557503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23660 11:18:27.591662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23661 11:18:27.592140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23663 11:18:27.626316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23665 11:18:27.626909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23666 11:18:27.664253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23668 11:18:27.664798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23669 11:18:27.698633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23670 11:18:27.698985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23672 11:18:27.732152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23673 11:18:27.732558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23675 11:18:27.766850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23676 11:18:27.767261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23678 11:18:27.801256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23679 11:18:27.801669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23681 11:18:27.835988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23683 11:18:27.836422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23684 11:18:27.870614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23685 11:18:27.871096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23687 11:18:27.905746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23688 11:18:27.906101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23690 11:18:27.938126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23692 11:18:27.938481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23693 11:18:27.968602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23694 11:18:27.968978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23696 11:18:27.999343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23697 11:18:27.999692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23699 11:18:28.030698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23700 11:18:28.031173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23702 11:18:28.062132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23704 11:18:28.062690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23705 11:18:28.093080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23706 11:18:28.093532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23708 11:18:28.123994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23709 11:18:28.124422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23711 11:18:28.155692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23712 11:18:28.156178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23714 11:18:28.188105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23715 11:18:28.188530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23717 11:18:28.219352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23718 11:18:28.219828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23720 11:18:28.251164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23722 11:18:28.251733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23723 11:18:28.283345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23724 11:18:28.283817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23726 11:18:28.314591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23727 11:18:28.315039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23729 11:18:28.346537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23730 11:18:28.347049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23732 11:18:28.378429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23733 11:18:28.378811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23735 11:18:28.414154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23737 11:18:28.414686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23738 11:18:28.446542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23739 11:18:28.446898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23741 11:18:28.478054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23743 11:18:28.478469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23744 11:18:28.508139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23745 11:18:28.508502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23747 11:18:28.539468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23748 11:18:28.539824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23750 11:18:28.571517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23751 11:18:28.571965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23753 11:18:28.601598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23754 11:18:28.602063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23756 11:18:28.633636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23757 11:18:28.634093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23759 11:18:28.667617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23760 11:18:28.668092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23762 11:18:28.723775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23763 11:18:28.724270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23765 11:18:28.757802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23767 11:18:28.758456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23768 11:18:28.792294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23770 11:18:28.792909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23771 11:18:28.828070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23773 11:18:28.828609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23774 11:18:28.861581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23776 11:18:28.862152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23777 11:18:28.895961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23778 11:18:28.896423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23780 11:18:28.930593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23782 11:18:28.931154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23783 11:18:28.965220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23785 11:18:28.965836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23786 11:18:28.999359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23788 11:18:29.000017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23789 11:18:29.033384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23790 11:18:29.033824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23792 11:18:29.067205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23793 11:18:29.067679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23795 11:18:29.101389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23797 11:18:29.101870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23798 11:18:29.137596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23799 11:18:29.137960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23801 11:18:29.171127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23803 11:18:29.171487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23804 11:18:29.203045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23806 11:18:29.203591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23807 11:18:29.235757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23808 11:18:29.236225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23810 11:18:29.267242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23811 11:18:29.267682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23813 11:18:29.298763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23814 11:18:29.299175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23816 11:18:29.330352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23817 11:18:29.330821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23819 11:18:29.364639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23821 11:18:29.365061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23822 11:18:29.399443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23823 11:18:29.399819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23825 11:18:29.432487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23826 11:18:29.432888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23828 11:18:29.464308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23830 11:18:29.464778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23831 11:18:29.496012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23832 11:18:29.496493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23834 11:18:29.527838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23835 11:18:29.528288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23837 11:18:29.559259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23838 11:18:29.559697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23840 11:18:29.591098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23841 11:18:29.591517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23843 11:18:29.622217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23845 11:18:29.622721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23846 11:18:29.658976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23848 11:18:29.659507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23849 11:18:29.689545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23850 11:18:29.690007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23852 11:18:29.720883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23853 11:18:29.721363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23855 11:18:29.752355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23856 11:18:29.752802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23858 11:18:29.784640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23860 11:18:29.785248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23861 11:18:29.815122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23862 11:18:29.815558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23864 11:18:29.845963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23866 11:18:29.846581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23867 11:18:29.876834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23868 11:18:29.877326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23870 11:18:29.907831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23872 11:18:29.908298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23873 11:18:29.939504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23875 11:18:29.940040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23876 11:18:29.969716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23877 11:18:29.970150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23879 11:18:30.000637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23881 11:18:30.001170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23882 11:18:30.031115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23883 11:18:30.031570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23885 11:18:30.061402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23887 11:18:30.061938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23888 11:18:30.091791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23889 11:18:30.092220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23891 11:18:30.123328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23893 11:18:30.123954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23894 11:18:30.154209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23896 11:18:30.154855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23897 11:18:30.185702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23899 11:18:30.186249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23900 11:18:30.217561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23902 11:18:30.218138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23903 11:18:30.250728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23904 11:18:30.251219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23906 11:18:30.290988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23907 11:18:30.291465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23909 11:18:30.324429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23910 11:18:30.324808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23912 11:18:30.357184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23913 11:18:30.357523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23915 11:18:30.389792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23916 11:18:30.390143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23918 11:18:30.421354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23919 11:18:30.421694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23921 11:18:30.453484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23922 11:18:30.453935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23924 11:18:30.484241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23926 11:18:30.484682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23927 11:18:30.516369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23928 11:18:30.516781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23930 11:18:30.549798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23931 11:18:30.550221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23933 11:18:30.581539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23935 11:18:30.581989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23936 11:18:30.612328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23937 11:18:30.612731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23939 11:18:30.644110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23940 11:18:30.644565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23942 11:18:30.677737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23943 11:18:30.678214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23945 11:18:30.708837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23946 11:18:30.709189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23948 11:18:30.740586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23949 11:18:30.740941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23951 11:18:30.771259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23953 11:18:30.771683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23954 11:18:30.801368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23955 11:18:30.801693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23957 11:18:30.831562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23959 11:18:30.831979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23960 11:18:30.861678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23961 11:18:30.862020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23963 11:18:30.891672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23964 11:18:30.892016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23966 11:18:30.921769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23967 11:18:30.922114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23969 11:18:30.952505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23970 11:18:30.952839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23972 11:18:30.982738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23973 11:18:30.983080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23975 11:18:31.012737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23976 11:18:31.013086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23978 11:18:31.043083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23979 11:18:31.043431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
23981 11:18:31.072878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
23982 11:18:31.073217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
23984 11:18:31.102962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
23985 11:18:31.103310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
23987 11:18:31.135271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
23988 11:18:31.135662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
23990 11:18:31.169247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
23992 11:18:31.169768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
23993 11:18:31.200472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
23994 11:18:31.200811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
23996 11:18:31.233589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
23998 11:18:31.234097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
23999 11:18:31.264705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
24001 11:18:31.265131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
24002 11:18:31.295582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
24004 11:18:31.296312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
24005 11:18:31.326327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
24006 11:18:31.326720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
24008 11:18:31.360414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
24009 11:18:31.360923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
24011 11:18:31.396434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
24013 11:18:31.396848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
24014 11:18:31.430071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
24016 11:18:31.430529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
24017 11:18:31.461904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
24019 11:18:31.462490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
24020 11:18:31.493072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
24021 11:18:31.493529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
24023 11:18:31.524083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
24025 11:18:31.524561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
24026 11:18:31.557182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
24027 11:18:31.557598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
24029 11:18:31.588000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
24030 11:18:31.588403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
24032 11:18:31.619179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
24033 11:18:31.619571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
24035 11:18:31.650181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
24037 11:18:31.650689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
24038 11:18:31.680957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
24039 11:18:31.681281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
24041 11:18:31.711675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
24043 11:18:31.712089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
24044 11:18:31.742393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
24045 11:18:31.742733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
24047 11:18:31.773216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
24048 11:18:31.773552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
24050 11:18:31.804193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
24051 11:18:31.804528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
24053 11:18:31.834967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
24054 11:18:31.835305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
24056 11:18:31.865431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
24057 11:18:31.865917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
24059 11:18:31.896491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
24061 11:18:31.897127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
24062 11:18:31.927477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
24063 11:18:31.927861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
24065 11:18:31.959072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
24067 11:18:31.959481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
24068 11:18:31.989782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
24070 11:18:31.990184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
24071 11:18:32.020717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
24072 11:18:32.021052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
24074 11:18:32.051566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
24075 11:18:32.051901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
24077 11:18:32.082185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
24079 11:18:32.082615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
24080 11:18:32.112693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
24081 11:18:32.113043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
24083 11:18:32.143068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
24084 11:18:32.143418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
24086 11:18:32.172808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
24087 11:18:32.173157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
24089 11:18:32.203525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
24090 11:18:32.203883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
24092 11:18:32.233697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
24093 11:18:32.234035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
24095 11:18:32.264293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
24096 11:18:32.264645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
24098 11:18:32.294878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
24099 11:18:32.295232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
24101 11:18:32.325143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
24102 11:18:32.325481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
24104 11:18:32.356890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
24105 11:18:32.357235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
24107 11:18:32.388917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
24108 11:18:32.389254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
24110 11:18:32.420291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
24111 11:18:32.420690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
24113 11:18:32.451332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
24114 11:18:32.451672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
24116 11:18:32.481845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
24118 11:18:32.482230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
24119 11:18:32.512997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
24120 11:18:32.513318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
24122 11:18:32.544050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
24123 11:18:32.544380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
24125 11:18:32.574739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
24126 11:18:32.575093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
24128 11:18:32.604926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
24129 11:18:32.605306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
24131 11:18:32.635229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
24132 11:18:32.635567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
24134 11:18:32.667816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
24135 11:18:32.668249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
24137 11:18:32.698654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
24138 11:18:32.699087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
24140 11:18:32.729700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
24141 11:18:32.730109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
24143 11:18:32.760542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
24144 11:18:32.761005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
24146 11:18:32.790865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
24148 11:18:32.791296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
24149 11:18:32.821207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
24151 11:18:32.821772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
24152 11:18:32.851825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
24153 11:18:32.852284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
24155 11:18:32.882496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
24156 11:18:32.882941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
24158 11:18:32.913481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
24159 11:18:32.913936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
24161 11:18:32.944151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
24163 11:18:32.944627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
24164 11:18:32.974648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
24165 11:18:32.975023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
24167 11:18:33.004859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
24168 11:18:33.005296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
24170 11:18:33.035103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
24171 11:18:33.035431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
24173 11:18:33.065008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
24174 11:18:33.065336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
24176 11:18:33.095159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
24177 11:18:33.095483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
24179 11:18:33.125336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
24180 11:18:33.125678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
24182 11:18:33.155705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
24183 11:18:33.156087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
24185 11:18:33.186902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
24187 11:18:33.187347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
24188 11:18:33.217308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
24189 11:18:33.217747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
24191 11:18:33.247639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
24192 11:18:33.248002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
24194 11:18:33.277616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
24195 11:18:33.277970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
24197 11:18:33.307846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
24198 11:18:33.308198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
24200 11:18:33.338870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
24201 11:18:33.339222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
24203 11:18:33.371609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
24204 11:18:33.372003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
24206 11:18:33.402189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
24208 11:18:33.402761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
24209 11:18:33.432932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
24210 11:18:33.433371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
24212 11:18:33.463437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
24213 11:18:33.463857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
24215 11:18:33.494649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
24216 11:18:33.495046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
24218 11:18:33.526311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
24220 11:18:33.526749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
24221 11:18:33.557204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
24223 11:18:33.557640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
24224 11:18:33.587624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
24225 11:18:33.588012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24227 11:18:33.618220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24229 11:18:33.618643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24230 11:18:33.648998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24232 11:18:33.649430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24233 11:18:33.679350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24234 11:18:33.679745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24236 11:18:33.710084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24238 11:18:33.710512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24239 11:18:33.740543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24240 11:18:33.740938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24242 11:18:33.771188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24243 11:18:33.771589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24245 11:18:33.815364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24246 11:18:33.815815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24248 11:18:33.853922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24249 11:18:33.854340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24251 11:18:33.884816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24252 11:18:33.885256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24254 11:18:33.915520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24256 11:18:33.916143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24257 11:18:33.946708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24258 11:18:33.947080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24260 11:18:33.977030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24261 11:18:33.977388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24263 11:18:34.008078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24264 11:18:34.008517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24266 11:18:34.039700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24267 11:18:34.040132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24269 11:18:34.073810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24270 11:18:34.074203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24272 11:18:34.105054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24273 11:18:34.105417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24275 11:18:34.135573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24276 11:18:34.135932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24278 11:18:34.166292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24280 11:18:34.166901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24281 11:18:34.197139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24283 11:18:34.197674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24284 11:18:34.227061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24285 11:18:34.227381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24287 11:18:34.268428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24288 11:18:34.268788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24290 11:18:34.305022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24291 11:18:34.305500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24293 11:18:34.336150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24295 11:18:34.336711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24296 11:18:34.367034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24298 11:18:34.367555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24299 11:18:34.398973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24300 11:18:34.399341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24302 11:18:34.431045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24303 11:18:34.431305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24305 11:18:34.461589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24306 11:18:34.461876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24308 11:18:34.491918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24309 11:18:34.492256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24311 11:18:34.522589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24312 11:18:34.522924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24314 11:18:34.553379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24315 11:18:34.553679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24317 11:18:34.583291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24318 11:18:34.583631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24320 11:18:34.613549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24321 11:18:34.613903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24323 11:18:34.643820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24325 11:18:34.644219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24326 11:18:34.674368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24327 11:18:34.674729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24329 11:18:34.704124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24330 11:18:34.704481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24332 11:18:34.734072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24334 11:18:34.734523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24335 11:18:34.764956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24336 11:18:34.765295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24338 11:18:34.794914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24339 11:18:34.795254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24341 11:18:34.824765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24342 11:18:34.825101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24344 11:18:34.855170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24345 11:18:34.855512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24347 11:18:34.885306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24348 11:18:34.885626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24350 11:18:34.915656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24351 11:18:34.915975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24353 11:18:34.949533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24354 11:18:34.949896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24356 11:18:34.981722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24357 11:18:34.982175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24359 11:18:35.012562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24360 11:18:35.012968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24362 11:18:35.043212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24363 11:18:35.043657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24365 11:18:35.076365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24367 11:18:35.076942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24368 11:18:35.107907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24369 11:18:35.108353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24371 11:18:35.139218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24372 11:18:35.139658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24374 11:18:35.171282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24375 11:18:35.171727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24377 11:18:35.218475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24378 11:18:35.219237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24380 11:18:35.251154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24382 11:18:35.251606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24383 11:18:35.284010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24385 11:18:35.284462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24386 11:18:35.319182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24387 11:18:35.319606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24389 11:18:35.351400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24390 11:18:35.351840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24392 11:18:35.385384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24393 11:18:35.385798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24395 11:18:35.419026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24396 11:18:35.419440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24398 11:18:35.451407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24399 11:18:35.451784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24401 11:18:35.482399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24402 11:18:35.482774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24404 11:18:35.513382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24406 11:18:35.513945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24407 11:18:35.544642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24409 11:18:35.545219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24410 11:18:35.576008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24411 11:18:35.576478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24413 11:18:35.606604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24414 11:18:35.607052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24416 11:18:35.637009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24417 11:18:35.637452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24419 11:18:35.667743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24421 11:18:35.668297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24422 11:18:35.698201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24424 11:18:35.698771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24425 11:18:35.730209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24427 11:18:35.730761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24428 11:18:35.760835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24430 11:18:35.761273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24431 11:18:35.791280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24432 11:18:35.791668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24434 11:18:35.821883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24435 11:18:35.822336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24437 11:18:35.851799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24438 11:18:35.852153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24440 11:18:35.882407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24441 11:18:35.882747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24443 11:18:35.912594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24444 11:18:35.913054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24446 11:18:35.943258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24447 11:18:35.943700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24449 11:18:35.974734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24451 11:18:35.975341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24452 11:18:36.004840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24453 11:18:36.005301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24455 11:18:36.035531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24457 11:18:36.036052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24458 11:18:36.066107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24460 11:18:36.066582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24461 11:18:36.096567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24463 11:18:36.097002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24464 11:18:36.126997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24465 11:18:36.127361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24467 11:18:36.156990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24468 11:18:36.157339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24470 11:18:36.187246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24471 11:18:36.187603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24473 11:18:36.218522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24474 11:18:36.218857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24476 11:18:36.249042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24477 11:18:36.249406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24479 11:18:36.279005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24480 11:18:36.279329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24482 11:18:36.309464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24483 11:18:36.309793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24485 11:18:36.340960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24487 11:18:36.341474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24488 11:18:36.372980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24489 11:18:36.373460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24491 11:18:36.406416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24493 11:18:36.407091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24494 11:18:36.440165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24495 11:18:36.440547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24497 11:18:36.471224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24498 11:18:36.471500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24500 11:18:36.502530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24501 11:18:36.502924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24503 11:18:36.533113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24504 11:18:36.533471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24506 11:18:36.564587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24507 11:18:36.564976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24509 11:18:36.597405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24510 11:18:36.597893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24512 11:18:36.628612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24513 11:18:36.629003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24515 11:18:36.659240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24516 11:18:36.659616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24518 11:18:36.690507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24519 11:18:36.690873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24521 11:18:36.721182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24523 11:18:36.721608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24524 11:18:36.751917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24525 11:18:36.752374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24527 11:18:36.783744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24528 11:18:36.784204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24530 11:18:36.815152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24531 11:18:36.815521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24533 11:18:36.848731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24535 11:18:36.849161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24536 11:18:36.882563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24537 11:18:36.882934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24539 11:18:36.914966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24541 11:18:36.915545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24542 11:18:36.950959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24543 11:18:36.951372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24545 11:18:36.989483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24546 11:18:36.989863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24548 11:18:37.022912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24549 11:18:37.023293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24551 11:18:37.056617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24552 11:18:37.057001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24554 11:18:37.088787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24555 11:18:37.089339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24557 11:18:37.122246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24559 11:18:37.122803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24560 11:18:37.154859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24562 11:18:37.155306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24563 11:18:37.188701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24564 11:18:37.189119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24566 11:18:37.222670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24567 11:18:37.223052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24569 11:18:37.266484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24570 11:18:37.266824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24572 11:18:37.302771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24573 11:18:37.303151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24575 11:18:37.335955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24576 11:18:37.336363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24578 11:18:37.369437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24579 11:18:37.369933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24581 11:18:37.403074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24582 11:18:37.403483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24584 11:18:37.435770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24586 11:18:37.436159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24587 11:18:37.471127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24588 11:18:37.471588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24590 11:18:37.506872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24591 11:18:37.507384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24593 11:18:37.543373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24595 11:18:37.544016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24596 11:18:37.583603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24598 11:18:37.583991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24599 11:18:37.617444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24600 11:18:37.617902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24602 11:18:37.652411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24604 11:18:37.653013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24605 11:18:37.688995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24607 11:18:37.689448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24608 11:18:37.738873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24610 11:18:37.739342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24611 11:18:37.773694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24612 11:18:37.774124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24614 11:18:37.810268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24616 11:18:37.810731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24617 11:18:37.844427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24618 11:18:37.844871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24620 11:18:37.884798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24622 11:18:37.885416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24623 11:18:37.927128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24624 11:18:37.927686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24626 11:18:37.958980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24628 11:18:37.959625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24629 11:18:37.989975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24631 11:18:37.990723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24632 11:18:38.021330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24634 11:18:38.021892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24635 11:18:38.052695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24636 11:18:38.053116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24638 11:18:38.084178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24640 11:18:38.084619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24641 11:18:38.116751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24643 11:18:38.117189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24644 11:18:38.147995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24645 11:18:38.148417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24647 11:18:38.183008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24648 11:18:38.183391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24650 11:18:38.226271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24652 11:18:38.227014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24653 11:18:38.265270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24655 11:18:38.265884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24656 11:18:38.298177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24658 11:18:38.298751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24659 11:18:38.332191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24660 11:18:38.332735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24662 11:18:38.371367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24663 11:18:38.371813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24665 11:18:38.412151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24667 11:18:38.412715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24668 11:18:38.444599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24669 11:18:38.445084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24671 11:18:38.477694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24673 11:18:38.478416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24674 11:18:38.513709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24675 11:18:38.514181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24677 11:18:38.558734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24678 11:18:38.559175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24680 11:18:38.591355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24681 11:18:38.591873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24683 11:18:38.624409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24684 11:18:38.624844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24686 11:18:38.659395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24687 11:18:38.659811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24689 11:18:38.691583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24690 11:18:38.691925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24692 11:18:38.723493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24693 11:18:38.723855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24695 11:18:38.755030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24697 11:18:38.755507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24698 11:18:38.786998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24699 11:18:38.787348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24701 11:18:38.818989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24702 11:18:38.819361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24704 11:18:38.851011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24705 11:18:38.851297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24707 11:18:38.881739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24708 11:18:38.882223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24710 11:18:38.912559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24711 11:18:38.913021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24713 11:18:38.971395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24715 11:18:38.971848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24716 11:18:39.002459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24717 11:18:39.002856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24719 11:18:39.033574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24720 11:18:39.034079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24722 11:18:39.067389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24723 11:18:39.067845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24725 11:18:39.098487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24726 11:18:39.098944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24728 11:18:39.130473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24729 11:18:39.130943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24731 11:18:39.162239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24733 11:18:39.162866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24734 11:18:39.193326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24735 11:18:39.193790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24737 11:18:39.225669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24738 11:18:39.226138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24740 11:18:39.256873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24741 11:18:39.257329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24743 11:18:39.289911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24744 11:18:39.290360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24746 11:18:39.323075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24747 11:18:39.323471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24749 11:18:39.355141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24751 11:18:39.355690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24752 11:18:39.387849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24753 11:18:39.388227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24755 11:18:39.420510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24756 11:18:39.420906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24758 11:18:39.453180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24759 11:18:39.453502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24761 11:18:39.487127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24762 11:18:39.487534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24764 11:18:39.519320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24765 11:18:39.519750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24767 11:18:39.550907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24768 11:18:39.551203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24770 11:18:39.584711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24771 11:18:39.585088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24773 11:18:39.615526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24775 11:18:39.615989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24776 11:18:39.647124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24777 11:18:39.647474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24779 11:18:39.678866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24780 11:18:39.679203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24782 11:18:39.709769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24783 11:18:39.710133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24785 11:18:39.740999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24786 11:18:39.741439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24788 11:18:39.772343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24789 11:18:39.772720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24791 11:18:39.803608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24792 11:18:39.803999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24794 11:18:39.835580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24795 11:18:39.836100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24797 11:18:39.867890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24798 11:18:39.868300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24800 11:18:39.901064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24801 11:18:39.901580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24803 11:18:39.933463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24805 11:18:39.934209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24806 11:18:39.966458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24807 11:18:39.966991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24809 11:18:39.999348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24810 11:18:39.999832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24812 11:18:40.037064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24813 11:18:40.037588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24815 11:18:40.077477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24816 11:18:40.077974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24818 11:18:40.109725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24820 11:18:40.110350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24821 11:18:40.142068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24823 11:18:40.142716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24824 11:18:40.173939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24826 11:18:40.174562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24827 11:18:40.209427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24828 11:18:40.209920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24830 11:18:40.242158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24832 11:18:40.242810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24833 11:18:40.275310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24835 11:18:40.275977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24836 11:18:40.307344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24837 11:18:40.307789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24839 11:18:40.338956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24840 11:18:40.339425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24842 11:18:40.369616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24843 11:18:40.370079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24845 11:18:40.399734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24846 11:18:40.400186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24848 11:18:40.431070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24850 11:18:40.431615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24851 11:18:40.460988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24852 11:18:40.461487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24854 11:18:40.491602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24855 11:18:40.492131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24857 11:18:40.523119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24859 11:18:40.523744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24860 11:18:40.554493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24861 11:18:40.554959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24863 11:18:40.587868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24865 11:18:40.588494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24866 11:18:40.625986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24867 11:18:40.626476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24869 11:18:40.657066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24870 11:18:40.657529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24872 11:18:40.688573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24873 11:18:40.688999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24875 11:18:40.721548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24876 11:18:40.722033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24878 11:18:40.752827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24879 11:18:40.753241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24881 11:18:40.783623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24882 11:18:40.784022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24884 11:18:40.814960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24886 11:18:40.815386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24887 11:18:40.845493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24889 11:18:40.846053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24890 11:18:40.876443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24891 11:18:40.876880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24893 11:18:40.907755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24895 11:18:40.908284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24896 11:18:40.939145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24897 11:18:40.939552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24899 11:18:40.970785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24900 11:18:40.971236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24902 11:18:41.001717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24903 11:18:41.002168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24905 11:18:41.034118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24907 11:18:41.034503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24908 11:18:41.067052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24910 11:18:41.067657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24911 11:18:41.097340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24912 11:18:41.097689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24914 11:18:41.127918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24915 11:18:41.128361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24917 11:18:41.158722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24919 11:18:41.159268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24920 11:18:41.189495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24921 11:18:41.189961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24923 11:18:41.220567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24924 11:18:41.221018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24926 11:18:41.251707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24928 11:18:41.252238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24929 11:18:41.283185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24930 11:18:41.283643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24932 11:18:41.314269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24934 11:18:41.314707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24935 11:18:41.345419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24936 11:18:41.345846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24938 11:18:41.376212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24939 11:18:41.376663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24941 11:18:41.406848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24943 11:18:41.407404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24944 11:18:41.437806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24945 11:18:41.438254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24947 11:18:41.469063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24948 11:18:41.469474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24950 11:18:41.500268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24951 11:18:41.500721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24953 11:18:41.531750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24955 11:18:41.532197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24956 11:18:41.562861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24958 11:18:41.563402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24959 11:18:41.594152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24961 11:18:41.594685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24962 11:18:41.624853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24964 11:18:41.625286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24965 11:18:41.655958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24967 11:18:41.656561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24968 11:18:41.688594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24970 11:18:41.689033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24971 11:18:41.720733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24973 11:18:41.721051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24974 11:18:41.752114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24975 11:18:41.752610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24977 11:18:41.783023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24978 11:18:41.783346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24980 11:18:41.813808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
24982 11:18:41.814473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
24983 11:18:41.847056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
24984 11:18:41.847488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
24986 11:18:41.879809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
24987 11:18:41.880218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
24989 11:18:41.911508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
24991 11:18:41.911826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
24992 11:18:41.944162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
24993 11:18:41.944500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
24995 11:18:41.975187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
24996 11:18:41.975495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
24998 11:18:42.006323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
24999 11:18:42.006627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
25001 11:18:42.036885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
25003 11:18:42.037214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
25004 11:18:42.068595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
25005 11:18:42.069009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
25007 11:18:42.104946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
25008 11:18:42.105367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
25010 11:18:42.136578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
25011 11:18:42.136977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
25013 11:18:42.167246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
25014 11:18:42.167663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
25016 11:18:42.198760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
25017 11:18:42.199149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
25019 11:18:42.229018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
25020 11:18:42.229403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
25022 11:18:42.259922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
25023 11:18:42.260233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
25025 11:18:42.291208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
25026 11:18:42.291515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
25028 11:18:42.322074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
25030 11:18:42.322381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
25031 11:18:42.352830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
25032 11:18:42.353112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
25034 11:18:42.383251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
25035 11:18:42.383626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
25037 11:18:42.413691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
25039 11:18:42.414137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
25040 11:18:42.444563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
25041 11:18:42.444917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
25043 11:18:42.475456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
25044 11:18:42.475753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
25046 11:18:42.506523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
25047 11:18:42.506819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
25049 11:18:42.537680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
25050 11:18:42.537982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
25052 11:18:42.568783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
25053 11:18:42.569176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
25055 11:18:42.599288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
25056 11:18:42.599649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
25058 11:18:42.630803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
25059 11:18:42.631163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
25061 11:18:42.661264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
25062 11:18:42.661794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
25064 11:18:42.694512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
25065 11:18:42.694965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
25067 11:18:42.727054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
25068 11:18:42.727503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
25070 11:18:42.759138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
25071 11:18:42.759563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
25073 11:18:42.790797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
25074 11:18:42.791248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
25076 11:18:42.822586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
25077 11:18:42.823048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
25079 11:18:42.854256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
25081 11:18:42.854852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
25082 11:18:42.886873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
25083 11:18:42.887344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
25085 11:18:42.918419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
25087 11:18:42.918988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
25088 11:18:42.949421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
25089 11:18:42.949937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
25091 11:18:42.980939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
25092 11:18:42.981389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
25094 11:18:43.012081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
25095 11:18:43.012440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
25097 11:18:43.043703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
25098 11:18:43.044048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
25100 11:18:43.075160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
25101 11:18:43.075510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
25103 11:18:43.106999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
25104 11:18:43.107457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
25106 11:18:43.138584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
25107 11:18:43.138989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
25109 11:18:43.169580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
25110 11:18:43.169989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
25112 11:18:43.200764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
25113 11:18:43.201168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
25115 11:18:43.232247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
25116 11:18:43.232718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
25118 11:18:43.264153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
25119 11:18:43.264603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
25121 11:18:43.296202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
25123 11:18:43.296771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
25124 11:18:43.327897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
25126 11:18:43.328428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
25127 11:18:43.359377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
25128 11:18:43.359814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
25130 11:18:43.391847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
25131 11:18:43.392265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
25133 11:18:43.424713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
25135 11:18:43.425221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
25136 11:18:43.458987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
25137 11:18:43.459339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
25139 11:18:43.498462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
25140 11:18:43.498885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
25142 11:18:43.533713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
25143 11:18:43.534093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
25145 11:18:43.573799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
25146 11:18:43.574153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
25148 11:18:43.611493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
25149 11:18:43.611882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
25151 11:18:43.644765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
25153 11:18:43.645225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
25154 11:18:43.676564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
25155 11:18:43.676930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
25157 11:18:43.708077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
25159 11:18:43.708544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
25160 11:18:43.739722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
25161 11:18:43.740077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
25163 11:18:43.771600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
25165 11:18:43.772052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
25166 11:18:43.802984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
25167 11:18:43.803361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
25169 11:18:43.833317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
25171 11:18:43.833764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
25172 11:18:43.863871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
25173 11:18:43.864217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
25175 11:18:43.894433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
25176 11:18:43.894790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
25178 11:18:43.925962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
25180 11:18:43.926441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
25181 11:18:43.956313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
25182 11:18:43.956675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
25184 11:18:43.987076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
25185 11:18:43.987439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
25187 11:18:44.017584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
25188 11:18:44.017971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
25190 11:18:44.073626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
25191 11:18:44.074001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
25193 11:18:44.105301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
25194 11:18:44.105655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
25196 11:18:44.137393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
25197 11:18:44.137745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
25199 11:18:44.169618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
25201 11:18:44.170067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
25202 11:18:44.202762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
25203 11:18:44.203118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
25205 11:18:44.235283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
25206 11:18:44.235700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
25208 11:18:44.268149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
25209 11:18:44.268612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
25211 11:18:44.311956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
25213 11:18:44.312427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
25214 11:18:44.358838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
25216 11:18:44.359291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
25217 11:18:44.395521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
25218 11:18:44.395897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
25220 11:18:44.428424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
25221 11:18:44.428854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
25223 11:18:44.461211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
25225 11:18:44.461689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25226 11:18:44.493502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25227 11:18:44.493891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25229 11:18:44.526119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25231 11:18:44.526529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25232 11:18:44.560867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25234 11:18:44.561509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25235 11:18:44.592802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25236 11:18:44.593272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25238 11:18:44.624657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25240 11:18:44.625261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25241 11:18:44.656512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25242 11:18:44.656973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25244 11:18:44.688526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25245 11:18:44.688964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25247 11:18:44.720084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25248 11:18:44.720500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25250 11:18:44.751753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25251 11:18:44.752080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25253 11:18:44.783130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25254 11:18:44.783489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25256 11:18:44.814611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25257 11:18:44.815072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25259 11:18:44.847029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25260 11:18:44.847484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25262 11:18:44.877885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25263 11:18:44.878329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25265 11:18:44.908925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25267 11:18:44.909530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25268 11:18:44.939792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25269 11:18:44.940242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25271 11:18:44.970801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25272 11:18:44.971258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25274 11:18:45.002690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25275 11:18:45.003097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25277 11:18:45.033642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25279 11:18:45.034203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25280 11:18:45.064010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25281 11:18:45.064320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25283 11:18:45.094706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25284 11:18:45.095021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25286 11:18:45.125490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25287 11:18:45.125813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25289 11:18:45.156599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25291 11:18:45.157144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25292 11:18:45.187805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25293 11:18:45.188167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25295 11:18:45.219476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25296 11:18:45.219890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25298 11:18:45.251684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25299 11:18:45.252087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25301 11:18:45.283095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25302 11:18:45.283549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25304 11:18:45.314756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25305 11:18:45.315166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25307 11:18:45.345180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25308 11:18:45.345479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25310 11:18:45.376003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25311 11:18:45.376298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25313 11:18:45.407125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25314 11:18:45.407423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25316 11:18:45.437764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25317 11:18:45.438063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25319 11:18:45.468840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25320 11:18:45.469134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25322 11:18:45.501191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25323 11:18:45.501504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25325 11:18:45.531530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25327 11:18:45.531867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25328 11:18:45.562323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25329 11:18:45.562617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25331 11:18:45.592732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25332 11:18:45.593031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25334 11:18:45.623886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25335 11:18:45.624203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25337 11:18:45.655295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25338 11:18:45.655677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25340 11:18:45.685795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25342 11:18:45.686300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25343 11:18:45.716609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25344 11:18:45.716976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25346 11:18:45.747233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25347 11:18:45.747684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25349 11:18:45.777793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25351 11:18:45.778326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25352 11:18:45.808779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25353 11:18:45.809243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25355 11:18:45.840622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25356 11:18:45.841011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25358 11:18:45.871540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25359 11:18:45.871948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25361 11:18:45.901746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25363 11:18:45.902084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25364 11:18:45.932795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25365 11:18:45.933252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25367 11:18:45.963589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25368 11:18:45.964019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25370 11:18:45.995442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25371 11:18:45.995887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25373 11:18:46.026113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25375 11:18:46.026635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25376 11:18:46.059331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25377 11:18:46.059792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25379 11:18:46.092980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25381 11:18:46.093416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25382 11:18:46.124683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25384 11:18:46.125126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25385 11:18:46.155524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25386 11:18:46.155972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25388 11:18:46.186904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25389 11:18:46.187353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25391 11:18:46.217374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25392 11:18:46.217773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25394 11:18:46.248543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25395 11:18:46.248995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25397 11:18:46.279486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25399 11:18:46.280119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25400 11:18:46.310634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25402 11:18:46.311079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25403 11:18:46.341563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25404 11:18:46.342058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25406 11:18:46.374162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25408 11:18:46.374725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25409 11:18:46.406475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25410 11:18:46.406937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25412 11:18:46.437879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25413 11:18:46.438320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25415 11:18:46.469006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25416 11:18:46.469446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25418 11:18:46.500373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25419 11:18:46.500827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25421 11:18:46.531556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25423 11:18:46.532090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25424 11:18:46.562499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25425 11:18:46.562934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25427 11:18:46.592883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25428 11:18:46.593299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25430 11:18:46.624717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25431 11:18:46.625167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25433 11:18:46.656755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25434 11:18:46.657179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25436 11:18:46.688176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25437 11:18:46.688634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25439 11:18:46.719635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25440 11:18:46.720065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25442 11:18:46.751111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25443 11:18:46.751543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25445 11:18:46.782162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25447 11:18:46.782700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25448 11:18:46.814219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25450 11:18:46.814753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25451 11:18:46.846161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25453 11:18:46.846704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25454 11:18:46.877792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25455 11:18:46.878233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25457 11:18:46.909419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25458 11:18:46.909860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25460 11:18:46.940960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25461 11:18:46.941394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25463 11:18:46.972000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25464 11:18:46.972436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25466 11:18:47.004010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25467 11:18:47.004442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25469 11:18:47.035306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25470 11:18:47.035729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25472 11:18:47.066858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25473 11:18:47.067307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25475 11:18:47.098220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25477 11:18:47.098757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25478 11:18:47.129673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25479 11:18:47.130088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25481 11:18:47.161568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25483 11:18:47.162041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25484 11:18:47.192782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25485 11:18:47.193190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25487 11:18:47.224769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25488 11:18:47.225190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25490 11:18:47.257271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25491 11:18:47.257682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25493 11:18:47.297585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25494 11:18:47.298090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25496 11:18:47.330197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25498 11:18:47.330815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25499 11:18:47.362963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25500 11:18:47.363423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25502 11:18:47.394879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25504 11:18:47.395618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25505 11:18:47.426820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25506 11:18:47.427233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25508 11:18:47.458635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25509 11:18:47.459056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25511 11:18:47.489489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25512 11:18:47.489908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25514 11:18:47.520969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25516 11:18:47.521406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25517 11:18:47.551487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25518 11:18:47.551888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25520 11:18:47.583186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25521 11:18:47.583587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25523 11:18:47.614182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25525 11:18:47.614796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25526 11:18:47.645282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25527 11:18:47.645689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25529 11:18:47.676786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25530 11:18:47.677241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25532 11:18:47.708266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25533 11:18:47.708715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25535 11:18:47.740534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25536 11:18:47.740908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25538 11:18:47.771874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25539 11:18:47.772340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25541 11:18:47.805158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25542 11:18:47.805552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25544 11:18:47.837242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25545 11:18:47.837659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25547 11:18:47.870758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25549 11:18:47.871139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25550 11:18:47.903082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25551 11:18:47.903469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25553 11:18:47.935269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25554 11:18:47.935658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25556 11:18:47.967049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25557 11:18:47.967395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25559 11:18:47.997701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25560 11:18:47.998052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25562 11:18:48.030882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25563 11:18:48.031407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25565 11:18:48.062945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25566 11:18:48.063386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25568 11:18:48.096032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25569 11:18:48.096437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25571 11:18:48.127967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25572 11:18:48.128321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25574 11:18:48.159311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25575 11:18:48.159727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25577 11:18:48.190831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25578 11:18:48.191242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25580 11:18:48.222129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25582 11:18:48.222617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25583 11:18:48.253256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25584 11:18:48.253665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25586 11:18:48.285708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25587 11:18:48.286062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25589 11:18:48.319326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25590 11:18:48.319840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25592 11:18:48.350846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25593 11:18:48.351284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25595 11:18:48.381714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25596 11:18:48.382159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25598 11:18:48.414151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25600 11:18:48.414689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25601 11:18:48.447799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25603 11:18:48.448374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25604 11:18:48.479888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25605 11:18:48.480308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25607 11:18:48.515315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25608 11:18:48.515783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25610 11:18:48.546445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25611 11:18:48.546900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25613 11:18:48.577433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25615 11:18:48.577989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25616 11:18:48.608257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25617 11:18:48.608699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25619 11:18:48.639774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25620 11:18:48.640218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25622 11:18:48.671229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25623 11:18:48.671682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25625 11:18:48.703259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25626 11:18:48.703696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25628 11:18:48.734537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25629 11:18:48.734981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25631 11:18:48.765155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25632 11:18:48.765626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25634 11:18:48.796590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25635 11:18:48.797039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25637 11:18:48.827677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25639 11:18:48.828220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25640 11:18:48.858885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25642 11:18:48.859416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25643 11:18:48.891974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25644 11:18:48.892358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25646 11:18:48.923984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25647 11:18:48.924401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25649 11:18:48.955456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25651 11:18:48.955882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25652 11:18:48.987305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25653 11:18:48.987700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25655 11:18:49.019374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25656 11:18:49.019816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25658 11:18:49.051678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25660 11:18:49.052214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25661 11:18:49.083177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25663 11:18:49.083653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25664 11:18:49.115491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25665 11:18:49.115906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25667 11:18:49.147107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25669 11:18:49.147534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25670 11:18:49.215573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25672 11:18:49.216193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25673 11:18:49.246954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25675 11:18:49.247180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25676 11:18:49.277272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25677 11:18:49.277625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25679 11:18:49.319513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25680 11:18:49.319907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25682 11:18:49.353581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25683 11:18:49.353951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25685 11:18:49.388451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25686 11:18:49.388820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25688 11:18:49.439635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25690 11:18:49.440424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25691 11:18:49.473179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25693 11:18:49.473743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25694 11:18:49.504188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25695 11:18:49.504640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25697 11:18:49.536050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25698 11:18:49.536516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25700 11:18:49.567525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25701 11:18:49.567986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25703 11:18:49.598075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25705 11:18:49.598692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25706 11:18:49.629535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25707 11:18:49.630021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25709 11:18:49.660757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25710 11:18:49.661132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25712 11:18:49.691864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25713 11:18:49.692235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25715 11:18:49.723136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25717 11:18:49.723740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25718 11:18:49.755185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25719 11:18:49.755630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25721 11:18:49.786828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25722 11:18:49.787220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25724 11:18:49.817629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25725 11:18:49.818014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25727 11:18:49.848748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25728 11:18:49.849142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25730 11:18:49.880247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25731 11:18:49.880605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25733 11:18:49.912119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25734 11:18:49.912467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25736 11:18:49.945234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25738 11:18:49.945666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25739 11:18:49.979086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25740 11:18:49.979436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25742 11:18:50.012876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25743 11:18:50.013347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25745 11:18:50.047690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25746 11:18:50.048224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25748 11:18:50.082616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25749 11:18:50.083090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25751 11:18:50.117181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25752 11:18:50.117668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25754 11:18:50.151937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25755 11:18:50.152412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25757 11:18:50.186043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25759 11:18:50.186674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25760 11:18:50.220490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25761 11:18:50.220963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25763 11:18:50.254786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25764 11:18:50.255252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25766 11:18:50.289462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25767 11:18:50.289949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25769 11:18:50.324369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25771 11:18:50.325002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25772 11:18:50.358868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25773 11:18:50.359250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25775 11:18:50.392431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25776 11:18:50.392840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25778 11:18:50.426819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25779 11:18:50.427279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25781 11:18:50.461276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25782 11:18:50.461702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25784 11:18:50.496055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25785 11:18:50.496519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25787 11:18:50.527787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25788 11:18:50.528234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25790 11:18:50.559575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25791 11:18:50.560055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25793 11:18:50.592635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25794 11:18:50.593054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25796 11:18:50.628529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25798 11:18:50.629078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25799 11:18:50.659236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25800 11:18:50.659583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25802 11:18:50.689979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25804 11:18:50.690280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25805 11:18:50.722182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25807 11:18:50.722669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25808 11:18:50.752815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25809 11:18:50.753187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25811 11:18:50.783229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25812 11:18:50.783570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25814 11:18:50.813693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25815 11:18:50.814038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25817 11:18:50.844809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25818 11:18:50.845093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25820 11:18:50.875164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25821 11:18:50.875446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25823 11:18:50.905512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25824 11:18:50.905871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25826 11:18:50.936117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25827 11:18:50.936496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25829 11:18:50.966598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25830 11:18:50.966997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25832 11:18:50.999954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25833 11:18:51.000407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25835 11:18:51.031244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25837 11:18:51.031848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25838 11:18:51.062269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25840 11:18:51.062699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25841 11:18:51.092988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25842 11:18:51.093386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25844 11:18:51.124210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25845 11:18:51.124615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25847 11:18:51.155380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25848 11:18:51.155774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25850 11:18:51.188552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25851 11:18:51.188961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25853 11:18:51.221083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25854 11:18:51.221485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25856 11:18:51.251943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25857 11:18:51.252336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25859 11:18:51.283191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25861 11:18:51.283797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25862 11:18:51.313664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25863 11:18:51.314009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25865 11:18:51.343691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25866 11:18:51.343974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25868 11:18:51.373771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25869 11:18:51.374055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25871 11:18:51.404314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25872 11:18:51.404762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25874 11:18:51.435023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25875 11:18:51.435459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25877 11:18:51.466803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25878 11:18:51.467252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25880 11:18:51.499062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25881 11:18:51.499536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25883 11:18:51.531559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25884 11:18:51.531971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25886 11:18:51.563129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25887 11:18:51.563536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25889 11:18:51.610522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25891 11:18:51.611083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25892 11:18:51.641688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25893 11:18:51.642133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25895 11:18:51.673446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25896 11:18:51.673908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25898 11:18:51.705207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25899 11:18:51.705616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25901 11:18:51.736209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25902 11:18:51.736491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25904 11:18:51.767350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25905 11:18:51.767632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25907 11:18:51.800652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25908 11:18:51.801065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25910 11:18:51.832120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25911 11:18:51.832447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25913 11:18:51.863320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25914 11:18:51.863677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25916 11:18:51.894095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25918 11:18:51.894366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25919 11:18:51.925126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25920 11:18:51.925565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25922 11:18:51.956199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25923 11:18:51.956524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25925 11:18:51.987926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25926 11:18:51.988291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25928 11:18:52.021377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25929 11:18:52.021672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25931 11:18:52.053037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25932 11:18:52.053446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25934 11:18:52.084500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25935 11:18:52.084887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25937 11:18:52.115190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25938 11:18:52.115534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25940 11:18:52.146171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25942 11:18:52.146563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25943 11:18:52.177290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25944 11:18:52.177664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25946 11:18:52.209161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25947 11:18:52.209643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25949 11:18:52.240422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25950 11:18:52.240885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25952 11:18:52.272713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25953 11:18:52.273190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25955 11:18:52.305296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25957 11:18:52.305908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25958 11:18:52.336531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25959 11:18:52.336918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25961 11:18:52.367205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25962 11:18:52.367487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25964 11:18:52.398196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25966 11:18:52.398492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25967 11:18:52.428947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25968 11:18:52.429232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25970 11:18:52.459883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25971 11:18:52.460249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25973 11:18:52.491074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25974 11:18:52.491529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25976 11:18:52.524022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25977 11:18:52.524484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25979 11:18:52.555542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25980 11:18:52.556005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
25982 11:18:52.588450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
25983 11:18:52.588924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
25985 11:18:52.620760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
25987 11:18:52.621318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
25988 11:18:52.651900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
25989 11:18:52.652298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
25991 11:18:52.684580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
25993 11:18:52.685144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
25994 11:18:52.716216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
25995 11:18:52.716670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
25997 11:18:52.747136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
25998 11:18:52.747592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
26000 11:18:52.777924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
26002 11:18:52.778476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
26003 11:18:52.808934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
26004 11:18:52.809381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
26006 11:18:52.839858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
26007 11:18:52.840240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
26009 11:18:52.870578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
26011 11:18:52.871014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
26012 11:18:52.900718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
26013 11:18:52.901030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
26015 11:18:52.932534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
26016 11:18:52.932912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
26018 11:18:52.962886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
26019 11:18:52.963237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
26021 11:18:52.993696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
26022 11:18:52.994046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
26024 11:18:53.023973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
26025 11:18:53.024318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
26027 11:18:53.055574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
26028 11:18:53.055922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
26030 11:18:53.085911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
26031 11:18:53.086361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
26033 11:18:53.116836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
26035 11:18:53.117264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
26036 11:18:53.147724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
26037 11:18:53.148122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
26039 11:18:53.179907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
26040 11:18:53.180360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
26042 11:18:53.212517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
26043 11:18:53.212987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
26045 11:18:53.242966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
26046 11:18:53.243311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
26048 11:18:53.273726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
26049 11:18:53.274186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
26051 11:18:53.304615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
26053 11:18:53.305165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
26054 11:18:53.335214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
26055 11:18:53.335657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
26057 11:18:53.365719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
26059 11:18:53.366248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
26060 11:18:53.396010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
26061 11:18:53.396453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
26063 11:18:53.426647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
26064 11:18:53.427085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
26066 11:18:53.456861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
26067 11:18:53.457317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
26069 11:18:53.487329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
26071 11:18:53.487872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
26072 11:18:53.518777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
26074 11:18:53.519310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
26075 11:18:53.549488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
26076 11:18:53.549945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
26078 11:18:53.580092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
26079 11:18:53.580553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
26081 11:18:53.611102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
26082 11:18:53.611543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
26084 11:18:53.642192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
26086 11:18:53.642787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
26087 11:18:53.672879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
26088 11:18:53.673319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
26090 11:18:53.703078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
26091 11:18:53.703523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
26093 11:18:53.734452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
26094 11:18:53.734993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
26096 11:18:53.766560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
26097 11:18:53.767012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
26099 11:18:53.796986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
26101 11:18:53.797614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
26102 11:18:53.827197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
26104 11:18:53.827621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
26105 11:18:53.858070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
26107 11:18:53.858494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
26108 11:18:53.888224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
26109 11:18:53.888571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
26111 11:18:53.918842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
26112 11:18:53.919286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
26114 11:18:53.950628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
26116 11:18:53.951179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
26117 11:18:53.981320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
26118 11:18:53.981758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
26120 11:18:54.012164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
26121 11:18:54.012566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
26123 11:18:54.045252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
26125 11:18:54.045707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
26126 11:18:54.076338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
26127 11:18:54.076796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
26129 11:18:54.107067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
26130 11:18:54.107519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
26132 11:18:54.137600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
26133 11:18:54.138072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
26135 11:18:54.168250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
26136 11:18:54.168692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
26138 11:18:54.199106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
26139 11:18:54.199544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
26141 11:18:54.229329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
26142 11:18:54.229801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
26144 11:18:54.260907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
26145 11:18:54.261357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
26147 11:18:54.315589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
26149 11:18:54.316275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
26150 11:18:54.347956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
26152 11:18:54.348695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
26153 11:18:54.379037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
26155 11:18:54.379725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
26156 11:18:54.409811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
26157 11:18:54.410260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
26159 11:18:54.441303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
26160 11:18:54.441750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
26162 11:18:54.473400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
26163 11:18:54.473810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
26165 11:18:54.505336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
26166 11:18:54.505768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
26168 11:18:54.538618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
26170 11:18:54.539147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
26171 11:18:54.570896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
26173 11:18:54.571515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
26174 11:18:54.603045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
26175 11:18:54.603488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
26177 11:18:54.635251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
26179 11:18:54.635852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
26180 11:18:54.666891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
26181 11:18:54.667346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
26183 11:18:54.698581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
26184 11:18:54.699023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
26186 11:18:54.729574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
26187 11:18:54.730018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
26189 11:18:54.760618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
26191 11:18:54.761063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
26192 11:18:54.791737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
26194 11:18:54.792158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
26195 11:18:54.822809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
26196 11:18:54.823159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
26198 11:18:54.853384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
26199 11:18:54.853734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
26201 11:18:54.884424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
26202 11:18:54.884766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
26204 11:18:54.915367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
26205 11:18:54.915716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
26207 11:18:54.947665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
26209 11:18:54.948140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
26210 11:18:54.980682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
26211 11:18:54.980989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
26213 11:18:55.012432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
26214 11:18:55.012846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
26216 11:18:55.043355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
26217 11:18:55.043757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
26219 11:18:55.074948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
26220 11:18:55.075395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
26222 11:18:55.107813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26224 11:18:55.108368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
26225 11:18:55.139151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26227 11:18:55.139585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26228 11:18:55.170111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26230 11:18:55.170762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26231 11:18:55.203019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26232 11:18:55.203437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26234 11:18:55.234986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26235 11:18:55.235411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26237 11:18:55.266956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26239 11:18:55.267514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26240 11:18:55.299428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26242 11:18:55.299992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26243 11:18:55.331253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26244 11:18:55.331704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26246 11:18:55.362282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26248 11:18:55.362847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26249 11:18:55.392685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26250 11:18:55.393134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26252 11:18:55.423610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26253 11:18:55.424070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26255 11:18:55.455066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26257 11:18:55.455592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26258 11:18:55.485657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26259 11:18:55.486093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26261 11:18:55.517450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26262 11:18:55.517922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26264 11:18:55.550709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26265 11:18:55.551160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26267 11:18:55.583787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26268 11:18:55.584245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26270 11:18:55.616984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26271 11:18:55.617400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26273 11:18:55.652214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26274 11:18:55.652627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26276 11:18:55.686544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26277 11:18:55.686875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26279 11:18:55.722098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26281 11:18:55.722710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26282 11:18:55.755793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26283 11:18:55.756149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26285 11:18:55.789044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26286 11:18:55.789396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26288 11:18:55.823778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26290 11:18:55.824239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26291 11:18:55.856500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26292 11:18:55.856910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26294 11:18:55.889699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26295 11:18:55.890122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26297 11:18:55.923867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26298 11:18:55.924278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26300 11:18:55.957013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26301 11:18:55.957487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26303 11:18:55.991782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26304 11:18:55.992168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26306 11:18:56.025736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26307 11:18:56.025992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26309 11:18:56.059914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26310 11:18:56.060204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26312 11:18:56.093429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26313 11:18:56.093671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26315 11:18:56.127798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26316 11:18:56.128144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26318 11:18:56.161197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26319 11:18:56.161596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26321 11:18:56.194832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26323 11:18:56.195283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26324 11:18:56.228591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26325 11:18:56.229009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26327 11:18:56.261772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26328 11:18:56.262162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26330 11:18:56.295666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26331 11:18:56.296020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26333 11:18:56.328540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26334 11:18:56.328953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26336 11:18:56.361690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26337 11:18:56.362110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26339 11:18:56.395099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26340 11:18:56.395519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26342 11:18:56.428018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26343 11:18:56.428422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26345 11:18:56.460538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26346 11:18:56.460898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26348 11:18:56.493151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26349 11:18:56.493502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26351 11:18:56.526155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26353 11:18:56.526634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26354 11:18:56.559550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26356 11:18:56.560109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26357 11:18:56.592912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26359 11:18:56.593428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26360 11:18:56.626558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26362 11:18:56.627110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26363 11:18:56.661641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26365 11:18:56.662240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26366 11:18:56.695796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26367 11:18:56.696186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26369 11:18:56.730133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26371 11:18:56.730730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26372 11:18:56.763478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26373 11:18:56.763949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26375 11:18:56.797900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26376 11:18:56.798328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26378 11:18:56.831118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26379 11:18:56.831467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26381 11:18:56.863856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26382 11:18:56.864201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26384 11:18:56.897255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26385 11:18:56.897601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26387 11:18:56.929973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26389 11:18:56.930411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26390 11:18:56.963661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26391 11:18:56.964009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26393 11:18:56.997792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26394 11:18:56.998133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26396 11:18:57.031589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26397 11:18:57.031961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26399 11:18:57.065176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26400 11:18:57.065544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26402 11:18:57.099565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26403 11:18:57.099960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26405 11:18:57.133288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26406 11:18:57.133690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26408 11:18:57.165579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26409 11:18:57.165945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26411 11:18:57.198239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26413 11:18:57.198699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26414 11:18:57.230149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26416 11:18:57.230604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26417 11:18:57.261803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26419 11:18:57.262253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26420 11:18:57.293670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26422 11:18:57.294240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26423 11:18:57.329081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26424 11:18:57.329510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26426 11:18:57.362151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26428 11:18:57.362596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26429 11:18:57.394780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26431 11:18:57.395231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26432 11:18:57.427197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26433 11:18:57.427607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26435 11:18:57.461834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26436 11:18:57.462311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26438 11:18:57.494674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26440 11:18:57.495240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26441 11:18:57.526667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26442 11:18:57.527118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26444 11:18:57.559037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26445 11:18:57.559415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26447 11:18:57.591539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26448 11:18:57.591945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26450 11:18:57.625160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26451 11:18:57.625629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26453 11:18:57.664516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26455 11:18:57.665085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26456 11:18:57.697789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26457 11:18:57.698214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26459 11:18:57.731208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26460 11:18:57.731683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26462 11:18:57.763186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26463 11:18:57.763591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26465 11:18:57.795893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26466 11:18:57.796301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26468 11:18:57.828589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26469 11:18:57.828967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26471 11:18:57.859358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26472 11:18:57.859719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26474 11:18:57.890614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26476 11:18:57.891059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26477 11:18:57.921259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26478 11:18:57.921608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26480 11:18:57.951683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26481 11:18:57.952034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26483 11:18:57.982771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26485 11:18:57.983193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26486 11:18:58.013689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26487 11:18:58.013977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26489 11:18:58.044887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26490 11:18:58.045179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26492 11:18:58.075633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26493 11:18:58.075933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26495 11:18:58.107136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26496 11:18:58.107487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26498 11:18:58.138131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26500 11:18:58.138575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26501 11:18:58.171476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26503 11:18:58.171932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26504 11:18:58.206506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26506 11:18:58.206949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26507 11:18:58.240746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26508 11:18:58.241136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26510 11:18:58.274730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26511 11:18:58.275010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26513 11:18:58.307408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26514 11:18:58.307761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26516 11:18:58.343386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26517 11:18:58.343777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26519 11:18:58.375923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26520 11:18:58.376240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26522 11:18:58.409225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26523 11:18:58.409577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26525 11:18:58.441914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26526 11:18:58.442257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26528 11:18:58.474574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26530 11:18:58.475005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26531 11:18:58.507115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26532 11:18:58.507516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26534 11:18:58.540221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26535 11:18:58.540705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26537 11:18:58.573002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26539 11:18:58.573637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26540 11:18:58.605248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26541 11:18:58.605630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26543 11:18:58.638218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26545 11:18:58.638834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26546 11:18:58.675372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26547 11:18:58.675709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26549 11:18:58.710954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26550 11:18:58.711300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26552 11:18:58.745608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26553 11:18:58.746035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26555 11:18:58.782566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26556 11:18:58.783000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26558 11:18:58.819936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26559 11:18:58.820358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26561 11:18:58.855172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26563 11:18:58.855600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26564 11:18:58.888798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26565 11:18:58.889253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26567 11:18:58.922597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26568 11:18:58.923001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26570 11:18:58.959244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26571 11:18:58.959552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26573 11:18:58.994672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26574 11:18:58.995083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26576 11:18:59.028875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26577 11:18:59.029264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26579 11:18:59.062507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26580 11:18:59.062794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26582 11:18:59.095969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26583 11:18:59.096275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26585 11:18:59.131033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26586 11:18:59.131301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26588 11:18:59.167146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26589 11:18:59.167509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26591 11:18:59.203656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26592 11:18:59.203942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26594 11:18:59.235913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26595 11:18:59.236196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26597 11:18:59.269066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26598 11:18:59.269435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26600 11:18:59.300128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26601 11:18:59.300551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26603 11:18:59.332047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26604 11:18:59.332445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26606 11:18:59.372941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26607 11:18:59.373397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26609 11:18:59.460993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26610 11:18:59.461455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26612 11:18:59.506949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26614 11:18:59.507429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26615 11:18:59.538211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26617 11:18:59.538660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26618 11:18:59.570216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26620 11:18:59.570921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26621 11:18:59.601473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26622 11:18:59.601874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26624 11:18:59.632774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26625 11:18:59.633191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26627 11:18:59.665864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26628 11:18:59.666284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26630 11:18:59.697202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26631 11:18:59.697613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26633 11:18:59.733512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26634 11:18:59.734011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26636 11:18:59.763500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26637 11:18:59.763915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26639 11:18:59.795566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26640 11:18:59.796098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26642 11:18:59.826948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26643 11:18:59.827366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26645 11:18:59.858289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26647 11:18:59.858732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26648 11:18:59.889851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26649 11:18:59.890304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26651 11:18:59.921548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26652 11:18:59.921932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26654 11:18:59.953167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26655 11:18:59.953561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26657 11:18:59.987097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26658 11:18:59.987516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26660 11:19:00.019281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26662 11:19:00.019722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26663 11:19:00.051317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26665 11:19:00.051767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26666 11:19:00.084913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26667 11:19:00.085380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26669 11:19:00.116598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26670 11:19:00.117029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26672 11:19:00.148187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26673 11:19:00.148679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26675 11:19:00.183168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26676 11:19:00.183636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26678 11:19:00.216088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26680 11:19:00.216542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26681 11:19:00.248499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26682 11:19:00.248929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26684 11:19:00.279979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26685 11:19:00.280450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26687 11:19:00.313645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26688 11:19:00.314122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26690 11:19:00.347985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26692 11:19:00.348472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26693 11:19:00.381926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26695 11:19:00.382470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26696 11:19:00.415479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26697 11:19:00.415900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26699 11:19:00.453464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26701 11:19:00.454169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26702 11:19:00.495371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26703 11:19:00.495923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26705 11:19:00.528224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26706 11:19:00.528661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26708 11:19:00.563116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26710 11:19:00.563571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26711 11:19:00.597158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26712 11:19:00.597558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26714 11:19:00.637688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26715 11:19:00.638102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26717 11:19:00.670608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26718 11:19:00.670919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26720 11:19:00.705124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26722 11:19:00.705579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26723 11:19:00.739035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26724 11:19:00.739394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26726 11:19:00.773229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26727 11:19:00.773683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26729 11:19:00.806557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26730 11:19:00.806964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26732 11:19:00.838739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26733 11:19:00.839217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26735 11:19:00.872198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26736 11:19:00.872549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26738 11:19:00.905327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26740 11:19:00.905897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26741 11:19:00.937105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26742 11:19:00.937483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26744 11:19:00.968631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26745 11:19:00.969071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26747 11:19:01.001237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26748 11:19:01.001659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26750 11:19:01.034298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26752 11:19:01.034749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26753 11:19:01.068092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26755 11:19:01.068748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26756 11:19:01.101728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26758 11:19:01.102323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26759 11:19:01.134542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26760 11:19:01.135004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26762 11:19:01.166649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26764 11:19:01.167246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26765 11:19:01.199660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26767 11:19:01.200101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26768 11:19:01.232119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26769 11:19:01.232607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26771 11:19:01.264506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26772 11:19:01.265038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26774 11:19:01.298279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26776 11:19:01.298790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26777 11:19:01.331923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26779 11:19:01.332371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26780 11:19:01.364214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26781 11:19:01.364618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26783 11:19:01.395930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26784 11:19:01.396324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26786 11:19:01.427775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26787 11:19:01.428144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26789 11:19:01.460053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26790 11:19:01.460413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26792 11:19:01.492606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26793 11:19:01.492980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26795 11:19:01.527481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26796 11:19:01.527960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26798 11:19:01.560195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26799 11:19:01.560634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26801 11:19:01.592293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26803 11:19:01.592896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26804 11:19:01.624922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26806 11:19:01.625380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26807 11:19:01.658125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26809 11:19:01.658581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26810 11:19:01.691724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26811 11:19:01.692139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26813 11:19:01.724034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26815 11:19:01.724782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26816 11:19:01.758333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26818 11:19:01.758772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26819 11:19:01.791941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26821 11:19:01.792350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26822 11:19:01.824295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26823 11:19:01.824621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26825 11:19:01.857405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26826 11:19:01.857883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26828 11:19:01.891112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26829 11:19:01.891582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26831 11:19:01.925036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26832 11:19:01.925501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26834 11:19:01.967401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26835 11:19:01.967865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26837 11:19:02.004395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26838 11:19:02.004810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26840 11:19:02.039124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26842 11:19:02.039638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26843 11:19:02.073232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26845 11:19:02.073729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26846 11:19:02.106935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26847 11:19:02.107407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26849 11:19:02.139659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26851 11:19:02.140021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26852 11:19:02.176952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26853 11:19:02.177319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26855 11:19:02.218748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26856 11:19:02.219044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26858 11:19:02.251770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26859 11:19:02.252210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26861 11:19:02.283967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26862 11:19:02.284457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26864 11:19:02.316297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26865 11:19:02.316792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26867 11:19:02.350255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26869 11:19:02.350978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26870 11:19:02.383721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26871 11:19:02.384092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26873 11:19:02.417580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26875 11:19:02.418119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26876 11:19:02.451166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26877 11:19:02.451584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26879 11:19:02.485107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26880 11:19:02.485511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26882 11:19:02.518531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26883 11:19:02.518905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26885 11:19:02.551405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26887 11:19:02.551743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26888 11:19:02.584889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26889 11:19:02.585345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26891 11:19:02.618659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26892 11:19:02.619125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26894 11:19:02.659748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26895 11:19:02.660203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26897 11:19:02.693070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26898 11:19:02.693542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26900 11:19:02.725135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26901 11:19:02.725600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26903 11:19:02.757460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26904 11:19:02.757939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26906 11:19:02.797103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26907 11:19:02.797594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26909 11:19:02.835651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26910 11:19:02.836038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26912 11:19:02.868252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26914 11:19:02.868945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26915 11:19:02.900337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26917 11:19:02.901029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26918 11:19:02.942545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26919 11:19:02.943022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26921 11:19:02.975174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26922 11:19:02.975650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26924 11:19:03.008175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26925 11:19:03.008635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26927 11:19:03.040754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26928 11:19:03.041125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26930 11:19:03.072750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26931 11:19:03.073168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26933 11:19:03.105008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26935 11:19:03.105469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26936 11:19:03.137796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26937 11:19:03.138195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26939 11:19:03.169816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26940 11:19:03.170298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26942 11:19:03.200963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26943 11:19:03.201338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26945 11:19:03.232608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26947 11:19:03.233055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26948 11:19:03.263980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26950 11:19:03.264426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26951 11:19:03.295174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26952 11:19:03.295577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26954 11:19:03.326134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26956 11:19:03.326653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26957 11:19:03.356858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26958 11:19:03.357229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26960 11:19:03.388076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26961 11:19:03.388529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26963 11:19:03.420785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26965 11:19:03.421378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26966 11:19:03.456853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26968 11:19:03.457588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26969 11:19:03.491515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26971 11:19:03.491913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26972 11:19:03.526726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26974 11:19:03.527158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26975 11:19:03.561201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26977 11:19:03.561842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26978 11:19:03.595378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
26980 11:19:03.595899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26981 11:19:03.637198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
26982 11:19:03.637684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
26984 11:19:03.680553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
26985 11:19:03.681106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
26987 11:19:03.721130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
26989 11:19:03.721729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
26990 11:19:03.752925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
26991 11:19:03.753398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
26993 11:19:03.784816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
26994 11:19:03.785363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
26996 11:19:03.821782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
26997 11:19:03.822256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
26999 11:19:03.864653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
27001 11:19:03.865115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
27002 11:19:03.898895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
27004 11:19:03.899325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
27005 11:19:03.931279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
27006 11:19:03.931713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
27008 11:19:03.963228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
27010 11:19:03.963687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
27011 11:19:03.995709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
27012 11:19:03.996104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
27014 11:19:04.028140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
27015 11:19:04.028565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
27017 11:19:04.064477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
27018 11:19:04.064944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
27020 11:19:04.107333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
27022 11:19:04.107859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
27023 11:19:04.139657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
27025 11:19:04.140147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
27026 11:19:04.178968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
27027 11:19:04.179387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
27029 11:19:04.219614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
27031 11:19:04.220070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
27032 11:19:04.255703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
27034 11:19:04.256155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
27035 11:19:04.288097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
27036 11:19:04.288518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
27038 11:19:04.320279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
27039 11:19:04.320718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
27041 11:19:04.353569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
27043 11:19:04.354016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
27044 11:19:04.386719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
27045 11:19:04.387197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
27047 11:19:04.419607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
27049 11:19:04.420066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
27050 11:19:04.452600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
27052 11:19:04.453096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
27053 11:19:04.495911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
27054 11:19:04.496334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
27056 11:19:04.575621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
27057 11:19:04.576047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
27059 11:19:04.615217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
27060 11:19:04.615699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
27062 11:19:04.647682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
27063 11:19:04.648113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
27065 11:19:04.679664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
27066 11:19:04.680104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
27068 11:19:04.715613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
27069 11:19:04.716033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
27071 11:19:04.756431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
27072 11:19:04.756949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
27074 11:19:04.789719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
27075 11:19:04.790211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
27077 11:19:04.825330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
27078 11:19:04.825824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
27080 11:19:04.859252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
27081 11:19:04.859743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
27083 11:19:04.892089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
27084 11:19:04.892568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
27086 11:19:04.925586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
27087 11:19:04.926086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
27089 11:19:04.957730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
27090 11:19:04.958213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
27092 11:19:04.991009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
27094 11:19:04.991554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
27095 11:19:05.025115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
27096 11:19:05.025526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
27098 11:19:05.057711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
27100 11:19:05.058160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
27101 11:19:05.088880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
27103 11:19:05.089340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
27104 11:19:05.129013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
27105 11:19:05.129423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
27107 11:19:05.171191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
27108 11:19:05.171597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
27110 11:19:05.203021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
27111 11:19:05.203423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
27113 11:19:05.236845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
27114 11:19:05.237343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
27116 11:19:05.270729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
27117 11:19:05.271151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
27119 11:19:05.306262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
27121 11:19:05.306702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
27122 11:19:05.348933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
27124 11:19:05.349580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
27125 11:19:05.384653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
27127 11:19:05.385286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
27128 11:19:05.418990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
27130 11:19:05.419581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
27131 11:19:05.456716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
27132 11:19:05.457110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
27134 11:19:05.491824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
27135 11:19:05.492266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
27137 11:19:05.529382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
27139 11:19:05.529952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
27140 11:19:05.561786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
27141 11:19:05.562239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
27143 11:19:05.594403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
27144 11:19:05.594776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
27146 11:19:05.627364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
27147 11:19:05.627818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
27149 11:19:05.659649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
27150 11:19:05.660112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
27152 11:19:05.691990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
27153 11:19:05.692410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
27155 11:19:05.727631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
27157 11:19:05.728085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
27158 11:19:05.762935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
27159 11:19:05.763356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
27161 11:19:05.799278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
27163 11:19:05.799725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
27164 11:19:05.834319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
27166 11:19:05.834951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
27167 11:19:05.867288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
27168 11:19:05.867768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
27170 11:19:05.900823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
27171 11:19:05.901229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
27173 11:19:05.934198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
27175 11:19:05.934557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
27176 11:19:05.976097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
27178 11:19:05.976486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
27179 11:19:06.011337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
27180 11:19:06.011870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
27182 11:19:06.044306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
27183 11:19:06.044751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
27185 11:19:06.076722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
27186 11:19:06.077169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
27188 11:19:06.109825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
27190 11:19:06.110451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
27191 11:19:06.143415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
27192 11:19:06.143884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
27194 11:19:06.179360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
27195 11:19:06.179784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
27197 11:19:06.215514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
27198 11:19:06.215792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
27200 11:19:06.251603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
27201 11:19:06.251913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
27203 11:19:06.287141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
27204 11:19:06.287515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
27206 11:19:06.325700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
27208 11:19:06.326189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
27209 11:19:06.362837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
27210 11:19:06.363133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
27212 11:19:06.400228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
27213 11:19:06.400587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
27215 11:19:06.434132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
27217 11:19:06.434650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
27218 11:19:06.478595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
27220 11:19:06.479208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
27221 11:19:06.512308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
27223 11:19:06.512935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
27224 11:19:06.544715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27225 11:19:06.545192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27227 11:19:06.579683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27228 11:19:06.580135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27230 11:19:06.613706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27231 11:19:06.614131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27233 11:19:06.648437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27235 11:19:06.648903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27236 11:19:06.689424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27237 11:19:06.689855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27239 11:19:06.740076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27241 11:19:06.740739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27242 11:19:06.774986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27244 11:19:06.775444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27245 11:19:06.811228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27246 11:19:06.811650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27248 11:19:06.847361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27249 11:19:06.847798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27251 11:19:06.884626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27253 11:19:06.885098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27254 11:19:06.920599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27255 11:19:06.921020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27257 11:19:06.956158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27258 11:19:06.956580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27260 11:19:06.992257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27262 11:19:06.992907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27263 11:19:07.030262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27265 11:19:07.031021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27266 11:19:07.076370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27267 11:19:07.076741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27269 11:19:07.112624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27270 11:19:07.112999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27272 11:19:07.149246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27274 11:19:07.149811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27275 11:19:07.187187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27276 11:19:07.187672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27278 11:19:07.223323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27279 11:19:07.223785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27281 11:19:07.259322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27283 11:19:07.259708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27284 11:19:07.294710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27286 11:19:07.295169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27287 11:19:07.330445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27289 11:19:07.330909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27290 11:19:07.368556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27291 11:19:07.368980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27293 11:19:07.404611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27294 11:19:07.405035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27296 11:19:07.440208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27297 11:19:07.440691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27299 11:19:07.474551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27300 11:19:07.474907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27302 11:19:07.508680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27303 11:19:07.509074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27305 11:19:07.542916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27306 11:19:07.543286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27308 11:19:07.577479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27310 11:19:07.577918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27311 11:19:07.612775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27312 11:19:07.613133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27314 11:19:07.648862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27316 11:19:07.649291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27317 11:19:07.684588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27318 11:19:07.684940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27320 11:19:07.719556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27321 11:19:07.719914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27323 11:19:07.755300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27324 11:19:07.755700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27326 11:19:07.791438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27327 11:19:07.791816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27329 11:19:07.827871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27330 11:19:07.828223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27332 11:19:07.864311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27333 11:19:07.864666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27335 11:19:07.899919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27336 11:19:07.900337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27338 11:19:07.936262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27340 11:19:07.936716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27341 11:19:07.972891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27342 11:19:07.973323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27344 11:19:08.009119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27345 11:19:08.009494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27347 11:19:08.045194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27348 11:19:08.045540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27350 11:19:08.079975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27351 11:19:08.080320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27353 11:19:08.116365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27354 11:19:08.116709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27356 11:19:08.152412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27357 11:19:08.152834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27359 11:19:08.188405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27360 11:19:08.188826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27362 11:19:08.224072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27364 11:19:08.224548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27365 11:19:08.259491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27367 11:19:08.259965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27368 11:19:08.294927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27370 11:19:08.295400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27371 11:19:08.331255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27372 11:19:08.331635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27374 11:19:08.366959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27375 11:19:08.367320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27377 11:19:08.402102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27379 11:19:08.402581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27380 11:19:08.435499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27381 11:19:08.435796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27383 11:19:08.470522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27384 11:19:08.470808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27386 11:19:08.506604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27387 11:19:08.506968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27389 11:19:08.542293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27391 11:19:08.542752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27392 11:19:08.577336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27393 11:19:08.577691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27395 11:19:08.612507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27396 11:19:08.612891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27398 11:19:08.645564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27399 11:19:08.645939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27401 11:19:08.683102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27402 11:19:08.683455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27404 11:19:08.719917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27405 11:19:08.720263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27407 11:19:08.753119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27408 11:19:08.753477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27410 11:19:08.787276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27411 11:19:08.787619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27413 11:19:08.821026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27414 11:19:08.821369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27416 11:19:08.856074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27417 11:19:08.856431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27419 11:19:08.890716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27420 11:19:08.891076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27422 11:19:08.925309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27423 11:19:08.925684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27425 11:19:08.963204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27427 11:19:08.963726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27428 11:19:08.999414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27429 11:19:08.999853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27431 11:19:09.033710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27432 11:19:09.034073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27434 11:19:09.068624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27435 11:19:09.068983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27437 11:19:09.103127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27438 11:19:09.103475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27440 11:19:09.137105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27441 11:19:09.137451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27443 11:19:09.171955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27444 11:19:09.172313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27446 11:19:09.206768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27447 11:19:09.207127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27449 11:19:09.241463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27451 11:19:09.241892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27452 11:19:09.275911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27453 11:19:09.276268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27455 11:19:09.310785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27456 11:19:09.311075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27458 11:19:09.345831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27459 11:19:09.346121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27461 11:19:09.380037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27462 11:19:09.380383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27464 11:19:09.413143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27465 11:19:09.413605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27467 11:19:09.445308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27469 11:19:09.445675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27470 11:19:09.477047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27471 11:19:09.477351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27473 11:19:09.508224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27475 11:19:09.508534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27476 11:19:09.541362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27477 11:19:09.541679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27479 11:19:09.573400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27480 11:19:09.573749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27482 11:19:09.604879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27483 11:19:09.605170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27485 11:19:09.651955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27486 11:19:09.652300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27488 11:19:09.693703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27489 11:19:09.694045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27491 11:19:09.729010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27492 11:19:09.729357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27494 11:19:09.769626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27495 11:19:09.769985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27497 11:19:09.804669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27498 11:19:09.805027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27500 11:19:09.839394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27501 11:19:09.839736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27503 11:19:09.874538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27504 11:19:09.874885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27506 11:19:09.908864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27508 11:19:09.909294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27509 11:19:09.939897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27510 11:19:09.940245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27512 11:19:09.972338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27513 11:19:09.972688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27515 11:19:10.005635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27516 11:19:10.005986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27518 11:19:10.039468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27519 11:19:10.039822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27521 11:19:10.075190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27522 11:19:10.075531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27524 11:19:10.111298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27525 11:19:10.111685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27527 11:19:10.144683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27528 11:19:10.145053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27530 11:19:10.175753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27531 11:19:10.176040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27533 11:19:10.206478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27534 11:19:10.206762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27536 11:19:10.236445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27537 11:19:10.236805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27539 11:19:10.266972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27540 11:19:10.267258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27542 11:19:10.297246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27543 11:19:10.297608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27545 11:19:10.328771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27546 11:19:10.329136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27548 11:19:10.359248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27549 11:19:10.359595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27551 11:19:10.389580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27553 11:19:10.390035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27554 11:19:10.420108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27555 11:19:10.420437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27557 11:19:10.450474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27558 11:19:10.450821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27560 11:19:10.480857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27561 11:19:10.481139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27563 11:19:10.516999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27564 11:19:10.517468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27566 11:19:10.548157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27567 11:19:10.548587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27569 11:19:10.578596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27570 11:19:10.578884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27572 11:19:10.609073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27573 11:19:10.609442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27575 11:19:10.639609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27576 11:19:10.639972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27578 11:19:10.670848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27580 11:19:10.671339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27581 11:19:10.701452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27582 11:19:10.701817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27584 11:19:10.731699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27585 11:19:10.731984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27587 11:19:10.762321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27588 11:19:10.762683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27590 11:19:10.792469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27591 11:19:10.792832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27593 11:19:10.822939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27595 11:19:10.823238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27596 11:19:10.853323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27597 11:19:10.853678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27599 11:19:10.883658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27600 11:19:10.884037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27602 11:19:10.914649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27603 11:19:10.915020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27605 11:19:10.944812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27607 11:19:10.945245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27608 11:19:10.975352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27609 11:19:10.975709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27611 11:19:11.006091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27613 11:19:11.006579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27614 11:19:11.036299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27615 11:19:11.036656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27617 11:19:11.072944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27618 11:19:11.073352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27620 11:19:11.103790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27621 11:19:11.104140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27623 11:19:11.134842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27624 11:19:11.135214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27626 11:19:11.165567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27627 11:19:11.165923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27629 11:19:11.197687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27631 11:19:11.198246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27632 11:19:11.229707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27634 11:19:11.230290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27635 11:19:11.260485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27636 11:19:11.260832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27638 11:19:11.291460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27639 11:19:11.291805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27641 11:19:11.322768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27642 11:19:11.323112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27644 11:19:11.353515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27645 11:19:11.353979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27647 11:19:11.384540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27648 11:19:11.384985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27650 11:19:11.416585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27652 11:19:11.417040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27653 11:19:11.449635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27655 11:19:11.450113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27656 11:19:11.482873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27657 11:19:11.483349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27659 11:19:11.516392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27660 11:19:11.516808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27662 11:19:11.549473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27663 11:19:11.549974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27665 11:19:11.588903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27666 11:19:11.589417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27668 11:19:11.620898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27669 11:19:11.621311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27671 11:19:11.654972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27672 11:19:11.655337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27674 11:19:11.689295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27675 11:19:11.689785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27677 11:19:11.723294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27678 11:19:11.723663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27680 11:19:11.756705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27681 11:19:11.757070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27683 11:19:11.790912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27685 11:19:11.791413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27686 11:19:11.824669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27688 11:19:11.825103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27689 11:19:11.858259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27691 11:19:11.858769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27692 11:19:11.890931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27693 11:19:11.891330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27695 11:19:11.923344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27696 11:19:11.923813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27698 11:19:11.957027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27699 11:19:11.957480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27701 11:19:11.989155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27702 11:19:11.989567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27704 11:19:12.021280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27705 11:19:12.021681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27707 11:19:12.053671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27708 11:19:12.054127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27710 11:19:12.085574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27711 11:19:12.085996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27713 11:19:12.117829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27714 11:19:12.118243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27716 11:19:12.149555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27717 11:19:12.149971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27719 11:19:12.181488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27720 11:19:12.181904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27722 11:19:12.213575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27723 11:19:12.213986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27725 11:19:12.246225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27727 11:19:12.246665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27728 11:19:12.278514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27729 11:19:12.278990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27731 11:19:12.310972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27732 11:19:12.311451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27734 11:19:12.343227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27735 11:19:12.343696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27737 11:19:12.376095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27739 11:19:12.376537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27740 11:19:12.408541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27741 11:19:12.408948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27743 11:19:12.440786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27744 11:19:12.441250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27746 11:19:12.473143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27747 11:19:12.473599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27749 11:19:12.505217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27750 11:19:12.505621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27752 11:19:12.536894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27753 11:19:12.537331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27755 11:19:12.569045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27757 11:19:12.569481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27758 11:19:12.601299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27759 11:19:12.601756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27761 11:19:12.632740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27762 11:19:12.633081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27764 11:19:12.664163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27766 11:19:12.664583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27767 11:19:12.695577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27768 11:19:12.695937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27770 11:19:12.727682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27771 11:19:12.728027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27773 11:19:12.758614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27775 11:19:12.759058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27776 11:19:12.789246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27777 11:19:12.789698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27779 11:19:12.821207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27780 11:19:12.821663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27782 11:19:12.851927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27784 11:19:12.852387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27785 11:19:12.883178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27786 11:19:12.883560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27788 11:19:12.914706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27789 11:19:12.915122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27791 11:19:12.946289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27793 11:19:12.946731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27794 11:19:12.977575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27796 11:19:12.978035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27797 11:19:13.009035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27798 11:19:13.009445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27800 11:19:13.040625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27802 11:19:13.041241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27803 11:19:13.071817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27804 11:19:13.072276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27806 11:19:13.103577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27807 11:19:13.104036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27809 11:19:13.135897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27810 11:19:13.136367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27812 11:19:13.167551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27813 11:19:13.168024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27815 11:19:13.199046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27816 11:19:13.199479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27818 11:19:13.229665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27820 11:19:13.230135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27821 11:19:13.260659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27822 11:19:13.261012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27824 11:19:13.291450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27825 11:19:13.291794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27827 11:19:13.322561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27828 11:19:13.322908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27830 11:19:13.353784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27831 11:19:13.354140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27833 11:19:13.385695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27835 11:19:13.386150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27836 11:19:13.416671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27837 11:19:13.417040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27839 11:19:13.448034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27840 11:19:13.448385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27842 11:19:13.479184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27844 11:19:13.479624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27845 11:19:13.509678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27847 11:19:13.510106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27848 11:19:13.540531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27849 11:19:13.540871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27851 11:19:13.571698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27852 11:19:13.572032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27854 11:19:13.602867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27855 11:19:13.603165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27857 11:19:13.634158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27859 11:19:13.634595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27860 11:19:13.665237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27861 11:19:13.665703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27863 11:19:13.696852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27864 11:19:13.697308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27866 11:19:13.728500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27867 11:19:13.728950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27869 11:19:13.760252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27870 11:19:13.760655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27872 11:19:13.791798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27874 11:19:13.792336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27875 11:19:13.823095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27876 11:19:13.823539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27878 11:19:13.854658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27879 11:19:13.855114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27881 11:19:13.886228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27883 11:19:13.886667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27884 11:19:13.917705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27885 11:19:13.918118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27887 11:19:13.951936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27888 11:19:13.952342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27890 11:19:13.984629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27891 11:19:13.985044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27893 11:19:14.016215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27895 11:19:14.016575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27896 11:19:14.047419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27897 11:19:14.047852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27899 11:19:14.078885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27900 11:19:14.079289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27902 11:19:14.110269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27904 11:19:14.110705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27905 11:19:14.142944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27906 11:19:14.143401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27908 11:19:14.173674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27909 11:19:14.174019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27911 11:19:14.204844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27913 11:19:14.205279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27914 11:19:14.236229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27915 11:19:14.236687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27917 11:19:14.267722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27919 11:19:14.268338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27920 11:19:14.298991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27921 11:19:14.299394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27923 11:19:14.329633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27925 11:19:14.330140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27926 11:19:14.360020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27927 11:19:14.360378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27929 11:19:14.391556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27931 11:19:14.392006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27932 11:19:14.423364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27933 11:19:14.423783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27935 11:19:14.454626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27936 11:19:14.455043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27938 11:19:14.485794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27940 11:19:14.486238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27941 11:19:14.517326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27942 11:19:14.517731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27944 11:19:14.548674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27945 11:19:14.549122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27947 11:19:14.581113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27949 11:19:14.581475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27950 11:19:14.612377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27951 11:19:14.612672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27953 11:19:14.644233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27955 11:19:14.644654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27956 11:19:14.675291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27958 11:19:14.675710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27959 11:19:14.706731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27960 11:19:14.707072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27962 11:19:14.738444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27963 11:19:14.738803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27965 11:19:14.799313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27967 11:19:14.799749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27968 11:19:14.830799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27970 11:19:14.831245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27971 11:19:14.861949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27972 11:19:14.862404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27974 11:19:14.893054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27975 11:19:14.893453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27977 11:19:14.924854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
27979 11:19:14.925213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27980 11:19:14.955917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
27981 11:19:14.956325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
27983 11:19:14.987756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
27985 11:19:14.988297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
27986 11:19:15.019341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
27987 11:19:15.019742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
27989 11:19:15.050998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
27991 11:19:15.051432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
27992 11:19:15.082578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
27994 11:19:15.083018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
27995 11:19:15.113104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
27996 11:19:15.113560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
27998 11:19:15.144488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
28000 11:19:15.144916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
28001 11:19:15.177982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
28003 11:19:15.178568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
28004 11:19:15.211181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
28006 11:19:15.211731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
28007 11:19:15.243307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
28009 11:19:15.243867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
28010 11:19:15.275031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
28011 11:19:15.275505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
28013 11:19:15.308250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
28015 11:19:15.308616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
28016 11:19:15.341316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
28017 11:19:15.341756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
28019 11:19:15.375898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
28020 11:19:15.376307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
28022 11:19:15.407664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
28024 11:19:15.408097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
28025 11:19:15.441966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
28027 11:19:15.442409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
28028 11:19:15.473872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
28030 11:19:15.474317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
28031 11:19:15.507778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
28033 11:19:15.508229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
28034 11:19:15.540637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
28036 11:19:15.541081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
28037 11:19:15.572339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
28038 11:19:15.572731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
28040 11:19:15.603744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
28041 11:19:15.604127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
28043 11:19:15.635621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
28044 11:19:15.635992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
28046 11:19:15.667013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
28047 11:19:15.667367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
28049 11:19:15.698376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
28050 11:19:15.698731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
28052 11:19:15.729404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
28053 11:19:15.729853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
28055 11:19:15.761048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
28056 11:19:15.761423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
28058 11:19:15.792982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
28059 11:19:15.793272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
28061 11:19:15.824236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
28063 11:19:15.824669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
28064 11:19:15.856685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
28066 11:19:15.856988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
28067 11:19:15.887246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
28068 11:19:15.887596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
28070 11:19:15.917511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
28071 11:19:15.917871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
28073 11:19:15.947940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
28074 11:19:15.948295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
28076 11:19:15.978775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
28077 11:19:15.979185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
28079 11:19:16.010108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
28081 11:19:16.010653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
28082 11:19:16.042532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
28083 11:19:16.042983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
28085 11:19:16.074216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
28087 11:19:16.074657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
28088 11:19:16.105108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
28089 11:19:16.105504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
28091 11:19:16.136224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
28093 11:19:16.136672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
28094 11:19:16.167457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
28095 11:19:16.167861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
28097 11:19:16.200381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
28099 11:19:16.200900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
28100 11:19:16.231826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
28101 11:19:16.232185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
28103 11:19:16.263109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
28104 11:19:16.263518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
28106 11:19:16.294596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
28107 11:19:16.294986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
28109 11:19:16.325883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
28110 11:19:16.326307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
28112 11:19:16.360734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
28113 11:19:16.361160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
28115 11:19:16.392913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
28116 11:19:16.393303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
28118 11:19:16.425017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
28120 11:19:16.425672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
28121 11:19:16.457420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
28122 11:19:16.457840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
28124 11:19:16.489370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
28126 11:19:16.489821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
28127 11:19:16.520938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
28128 11:19:16.521340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
28130 11:19:16.552643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
28132 11:19:16.553195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
28133 11:19:16.585098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
28135 11:19:16.585661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
28136 11:19:16.616960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
28138 11:19:16.617389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
28139 11:19:16.649255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
28140 11:19:16.649614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
28142 11:19:16.682293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
28143 11:19:16.682727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
28145 11:19:16.715172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
28147 11:19:16.715734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
28148 11:19:16.747869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
28149 11:19:16.748332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
28151 11:19:16.781361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
28152 11:19:16.781801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
28154 11:19:16.814949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
28155 11:19:16.815372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
28157 11:19:16.847689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
28158 11:19:16.848099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
28160 11:19:16.879597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
28161 11:19:16.880004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
28163 11:19:16.913123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
28164 11:19:16.913500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
28166 11:19:16.945095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
28168 11:19:16.945543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
28169 11:19:16.979202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
28170 11:19:16.979619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
28172 11:19:17.011610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
28173 11:19:17.012033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
28175 11:19:17.045383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
28176 11:19:17.045818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
28178 11:19:17.076933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
28179 11:19:17.077386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
28181 11:19:17.109518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
28183 11:19:17.110091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
28184 11:19:17.140731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
28186 11:19:17.141185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
28187 11:19:17.171789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
28188 11:19:17.172214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
28190 11:19:17.207291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
28191 11:19:17.207773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
28193 11:19:17.240164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
28194 11:19:17.240605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
28196 11:19:17.273470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
28197 11:19:17.273922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
28199 11:19:17.307492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
28201 11:19:17.307924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
28202 11:19:17.339791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
28203 11:19:17.340245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
28205 11:19:17.372386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
28207 11:19:17.373019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
28208 11:19:17.404233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
28210 11:19:17.404840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
28211 11:19:17.435778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
28212 11:19:17.436169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
28214 11:19:17.467474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
28215 11:19:17.467861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
28217 11:19:17.500336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
28218 11:19:17.500726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
28220 11:19:17.532884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
28222 11:19:17.533329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
28223 11:19:17.566257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28224 11:19:17.566713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28226 11:19:17.598321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28228 11:19:17.598883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28229 11:19:17.631053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28230 11:19:17.631504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28232 11:19:17.662750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28233 11:19:17.663207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28235 11:19:17.695220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28236 11:19:17.695709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28238 11:19:17.729134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28239 11:19:17.729574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28241 11:19:17.762539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28242 11:19:17.762954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28244 11:19:17.794249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28246 11:19:17.794698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28247 11:19:17.826497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28249 11:19:17.826939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28250 11:19:17.858743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28251 11:19:17.859160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28253 11:19:17.891669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28254 11:19:17.892130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28256 11:19:17.931489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28257 11:19:17.931889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28259 11:19:17.962838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28260 11:19:17.963240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28262 11:19:17.993778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28263 11:19:17.994207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28265 11:19:18.026002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28267 11:19:18.026464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28268 11:19:18.056892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28270 11:19:18.057336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28271 11:19:18.088374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28272 11:19:18.088776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28274 11:19:18.120766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28275 11:19:18.121216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28277 11:19:18.152608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28278 11:19:18.152984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28280 11:19:18.183532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28282 11:19:18.183973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28283 11:19:18.214987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28285 11:19:18.215403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28286 11:19:18.246166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28288 11:19:18.246516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28289 11:19:18.277489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28290 11:19:18.277864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28292 11:19:18.309365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28293 11:19:18.309736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28295 11:19:18.341356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28296 11:19:18.341836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28298 11:19:18.372932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28299 11:19:18.373382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28301 11:19:18.405669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28302 11:19:18.406080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28304 11:19:18.437309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28305 11:19:18.437689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28307 11:19:18.470986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28308 11:19:18.471403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28310 11:19:18.503657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28311 11:19:18.504101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28313 11:19:18.537539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28315 11:19:18.538011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28316 11:19:18.575386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28317 11:19:18.575799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28319 11:19:18.607528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28320 11:19:18.608042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28322 11:19:18.639309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28324 11:19:18.639748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28325 11:19:18.672416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28326 11:19:18.672836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28328 11:19:18.704732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28330 11:19:18.705340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28331 11:19:18.736935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28332 11:19:18.737415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28334 11:19:18.768783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28335 11:19:18.769260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28337 11:19:18.799896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28338 11:19:18.800377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28340 11:19:18.831956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28341 11:19:18.832381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28343 11:19:18.865005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28344 11:19:18.865467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28346 11:19:18.898924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28347 11:19:18.899339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28349 11:19:18.931627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28350 11:19:18.932035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28352 11:19:18.964394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28353 11:19:18.964811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28355 11:19:18.999369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28356 11:19:18.999789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28358 11:19:19.032473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28359 11:19:19.032906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28361 11:19:19.068998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28362 11:19:19.069392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28364 11:19:19.107613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28365 11:19:19.108011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28367 11:19:19.143448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28369 11:19:19.143855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28370 11:19:19.179771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28371 11:19:19.180157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28373 11:19:19.212378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28374 11:19:19.212792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28376 11:19:19.245580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28377 11:19:19.245985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28379 11:19:19.279974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28381 11:19:19.280429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28382 11:19:19.315653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28383 11:19:19.316069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28385 11:19:19.348867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28387 11:19:19.349437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28388 11:19:19.380818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28389 11:19:19.381273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28391 11:19:19.415815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28392 11:19:19.416240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28394 11:19:19.450136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28396 11:19:19.450597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28397 11:19:19.483012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28398 11:19:19.483480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28400 11:19:19.515031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28401 11:19:19.515442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28403 11:19:19.547278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28405 11:19:19.547742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28406 11:19:19.581362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28407 11:19:19.581780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28409 11:19:19.614734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28410 11:19:19.615209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28412 11:19:19.646858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28413 11:19:19.647275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28415 11:19:19.679697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28416 11:19:19.680113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28418 11:19:19.712500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28420 11:19:19.713138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28421 11:19:19.744842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28423 11:19:19.745467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28424 11:19:19.776708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28426 11:19:19.777399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28427 11:19:19.809686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28429 11:19:19.810140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28430 11:19:19.841698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28431 11:19:19.842166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28433 11:19:19.873665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28434 11:19:19.874127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28436 11:19:19.947329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28438 11:19:19.947794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28439 11:19:19.979560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28441 11:19:19.980119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28442 11:19:20.012832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28443 11:19:20.013295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28445 11:19:20.045447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28446 11:19:20.045986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28448 11:19:20.079347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28449 11:19:20.079765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28451 11:19:20.112170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28453 11:19:20.112622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28454 11:19:20.144747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28455 11:19:20.145154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28457 11:19:20.177211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28459 11:19:20.177675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28460 11:19:20.209534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28461 11:19:20.209959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28463 11:19:20.241529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28464 11:19:20.241945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28466 11:19:20.273267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28467 11:19:20.273761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28469 11:19:20.305261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28470 11:19:20.305699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28472 11:19:20.337161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28473 11:19:20.337632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28475 11:19:20.369898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28477 11:19:20.370363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28478 11:19:20.403230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28480 11:19:20.403812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28481 11:19:20.436359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28482 11:19:20.436807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28484 11:19:20.469090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28485 11:19:20.469520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28487 11:19:20.503698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28489 11:19:20.504264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28490 11:19:20.536168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28492 11:19:20.536621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28493 11:19:20.569131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28494 11:19:20.569614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28496 11:19:20.603559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28497 11:19:20.603972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28499 11:19:20.639272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28500 11:19:20.639704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28502 11:19:20.673105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28504 11:19:20.673555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28505 11:19:20.709074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28506 11:19:20.709554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28508 11:19:20.744214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28509 11:19:20.744728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28511 11:19:20.777106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28512 11:19:20.777590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28514 11:19:20.809242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28515 11:19:20.809766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28517 11:19:20.843101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28518 11:19:20.843567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28520 11:19:20.875125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28521 11:19:20.875603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28523 11:19:20.909299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28524 11:19:20.909789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28526 11:19:20.945724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28528 11:19:20.946284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28529 11:19:20.988715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28530 11:19:20.989152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28532 11:19:21.022919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28533 11:19:21.023337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28535 11:19:21.056911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28536 11:19:21.057342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28538 11:19:21.089717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28539 11:19:21.090142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28541 11:19:21.121722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28542 11:19:21.122163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28544 11:19:21.153982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28546 11:19:21.154435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28547 11:19:21.186237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28548 11:19:21.186672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28550 11:19:21.218699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28552 11:19:21.219146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28553 11:19:21.250982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28554 11:19:21.251406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28556 11:19:21.283064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28557 11:19:21.283482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28559 11:19:21.315464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28560 11:19:21.315901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28562 11:19:21.347649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28563 11:19:21.348064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28565 11:19:21.379813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28566 11:19:21.380242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28568 11:19:21.411915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28569 11:19:21.412342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28571 11:19:21.444270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28572 11:19:21.444693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28574 11:19:21.476619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28575 11:19:21.477046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28577 11:19:21.510022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28579 11:19:21.510499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28580 11:19:21.542769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28582 11:19:21.543236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28583 11:19:21.574523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28584 11:19:21.574956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28586 11:19:21.605604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28587 11:19:21.606027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28589 11:19:21.636929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28590 11:19:21.637360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28592 11:19:21.668234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28593 11:19:21.668653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28595 11:19:21.699685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28596 11:19:21.700107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28598 11:19:21.731205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28599 11:19:21.731633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28601 11:19:21.763796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28602 11:19:21.764233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28604 11:19:21.795690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28605 11:19:21.796103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28607 11:19:21.827387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28608 11:19:21.827811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28610 11:19:21.859173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28612 11:19:21.859627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28613 11:19:21.893697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28615 11:19:21.894168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28616 11:19:21.927458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28618 11:19:21.927922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28619 11:19:21.960998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28620 11:19:21.961447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28622 11:19:21.994520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28623 11:19:21.994929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28625 11:19:22.026675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28626 11:19:22.027051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28628 11:19:22.058461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28630 11:19:22.058900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28631 11:19:22.089577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28632 11:19:22.089992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28634 11:19:22.129287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28635 11:19:22.129787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28637 11:19:22.179371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28638 11:19:22.179843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28640 11:19:22.211134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28642 11:19:22.211675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28643 11:19:22.242099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28645 11:19:22.242649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28646 11:19:22.276021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28647 11:19:22.276593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28649 11:19:22.309419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28650 11:19:22.309967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28652 11:19:22.342269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28653 11:19:22.342737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28655 11:19:22.374228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28657 11:19:22.374739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28658 11:19:22.406223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28660 11:19:22.406670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28661 11:19:22.438199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28663 11:19:22.438627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28664 11:19:22.469617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28665 11:19:22.470033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28667 11:19:22.501620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28668 11:19:22.502035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28670 11:19:22.533863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28672 11:19:22.534307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28673 11:19:22.566684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28674 11:19:22.567090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28676 11:19:22.598571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28677 11:19:22.598978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28679 11:19:22.630856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28680 11:19:22.631269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28682 11:19:22.663463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28684 11:19:22.663901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28685 11:19:22.696394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28687 11:19:22.696751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28688 11:19:22.728378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28689 11:19:22.728775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28691 11:19:22.760748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28692 11:19:22.761157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28694 11:19:22.792706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28695 11:19:22.793134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28697 11:19:22.825340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28699 11:19:22.825791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28700 11:19:22.857170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28702 11:19:22.857612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28703 11:19:22.888783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28705 11:19:22.889333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28706 11:19:22.919749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28707 11:19:22.920155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28709 11:19:22.950903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28710 11:19:22.951324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28712 11:19:22.982490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28714 11:19:22.982932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28715 11:19:23.013912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28716 11:19:23.014328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28718 11:19:23.045412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28720 11:19:23.045857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28721 11:19:23.077269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28722 11:19:23.077680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28724 11:19:23.108937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28725 11:19:23.109404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28727 11:19:23.140677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28729 11:19:23.141120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28730 11:19:23.172835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28732 11:19:23.173279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28733 11:19:23.204920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28735 11:19:23.205458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28736 11:19:23.236583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28737 11:19:23.237068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28739 11:19:23.269781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28740 11:19:23.270206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28742 11:19:23.301482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28744 11:19:23.301892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28745 11:19:23.332856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28746 11:19:23.333279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28748 11:19:23.364675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28749 11:19:23.365061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28751 11:19:23.395890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28752 11:19:23.396200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28754 11:19:23.426820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28755 11:19:23.427355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28757 11:19:23.457746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28759 11:19:23.458126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28760 11:19:23.489125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28761 11:19:23.489509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28763 11:19:23.520527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28764 11:19:23.520959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28766 11:19:23.551769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28767 11:19:23.552207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28769 11:19:23.583908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28770 11:19:23.584448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28772 11:19:23.617467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28773 11:19:23.617899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28775 11:19:23.650063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28777 11:19:23.650634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28778 11:19:23.683142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28780 11:19:23.683701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28781 11:19:23.716249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28782 11:19:23.716726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28784 11:19:23.748479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28785 11:19:23.748945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28787 11:19:23.781010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28788 11:19:23.781425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28790 11:19:23.813968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28791 11:19:23.814389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28793 11:19:23.847476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28795 11:19:23.848109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28796 11:19:23.879467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28798 11:19:23.879892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28799 11:19:23.911002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28800 11:19:23.911344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28802 11:19:23.943247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28803 11:19:23.943673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28805 11:19:23.975099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28807 11:19:23.975544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28808 11:19:24.007077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28809 11:19:24.007497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28811 11:19:24.039356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28813 11:19:24.039794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28814 11:19:24.070966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28816 11:19:24.071590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28817 11:19:24.102625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28818 11:19:24.103042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28820 11:19:24.134211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28822 11:19:24.134667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28823 11:19:24.165800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28824 11:19:24.166238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28826 11:19:24.197710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28828 11:19:24.198170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28829 11:19:24.228983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28831 11:19:24.229437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28832 11:19:24.260218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28834 11:19:24.260805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28835 11:19:24.291522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28836 11:19:24.292010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28838 11:19:24.323018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28839 11:19:24.323468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28841 11:19:24.354892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28843 11:19:24.355429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28844 11:19:24.385962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28845 11:19:24.386406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28847 11:19:24.417253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28848 11:19:24.417699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28850 11:19:24.449794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28851 11:19:24.450279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28853 11:19:24.481732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28854 11:19:24.482184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28856 11:19:24.513737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28858 11:19:24.514377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28859 11:19:24.551365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28861 11:19:24.551816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28862 11:19:24.583987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28864 11:19:24.584478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28865 11:19:24.616049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28867 11:19:24.616647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28868 11:19:24.647293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28869 11:19:24.647718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28871 11:19:24.679203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28873 11:19:24.679755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28874 11:19:24.710964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28875 11:19:24.711390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28877 11:19:24.743470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28878 11:19:24.743935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28880 11:19:24.775161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28881 11:19:24.775640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28883 11:19:24.814912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28884 11:19:24.815327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28886 11:19:24.847024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28888 11:19:24.847464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28889 11:19:24.879328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28891 11:19:24.879764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28892 11:19:24.911064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28894 11:19:24.911504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28895 11:19:24.941849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28897 11:19:24.942294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28898 11:19:24.972664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28899 11:19:24.973051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28901 11:19:25.024747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28902 11:19:25.025203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28904 11:19:25.074607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28905 11:19:25.075006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28907 11:19:25.111967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28908 11:19:25.112382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28910 11:19:25.147975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28912 11:19:25.148428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28913 11:19:25.183917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28914 11:19:25.184334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28916 11:19:25.219236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28918 11:19:25.219679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28919 11:19:25.256134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28920 11:19:25.256552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28922 11:19:25.295256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28923 11:19:25.295685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28925 11:19:25.330704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28926 11:19:25.331127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28928 11:19:25.365548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28929 11:19:25.365980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28931 11:19:25.401092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28932 11:19:25.401516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28934 11:19:25.436684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28935 11:19:25.437130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28937 11:19:25.473486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28939 11:19:25.473955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28940 11:19:25.507965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28942 11:19:25.508421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28943 11:19:25.542538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28944 11:19:25.542981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28946 11:19:25.576829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28948 11:19:25.577265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28949 11:19:25.612410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28950 11:19:25.612786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28952 11:19:25.646722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28954 11:19:25.647267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28955 11:19:25.683044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28956 11:19:25.683512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28958 11:19:25.725778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28959 11:19:25.726233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28961 11:19:25.764199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28962 11:19:25.764599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28964 11:19:25.798096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28966 11:19:25.798606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28967 11:19:25.832696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28969 11:19:25.833104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28970 11:19:25.867616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28972 11:19:25.868020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28973 11:19:25.906731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28975 11:19:25.907188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28976 11:19:25.941862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28977 11:19:25.942281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28979 11:19:25.978815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
28981 11:19:25.979266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
28982 11:19:26.015111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
28983 11:19:26.015473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
28985 11:19:26.051215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
28987 11:19:26.051674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
28988 11:19:26.086702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
28989 11:19:26.087113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
28991 11:19:26.120656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
28993 11:19:26.121203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
28994 11:19:26.155418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
28996 11:19:26.155838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
28997 11:19:26.189753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
28999 11:19:26.190400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
29000 11:19:26.225018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
29001 11:19:26.225476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
29003 11:19:26.260387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
29004 11:19:26.260868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
29006 11:19:26.295540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
29008 11:19:26.296161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
29009 11:19:26.331154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
29011 11:19:26.331612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
29012 11:19:26.366808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
29013 11:19:26.367228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
29015 11:19:26.402588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
29017 11:19:26.403042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
29018 11:19:26.438096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
29020 11:19:26.438556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
29021 11:19:26.473053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
29022 11:19:26.473468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
29024 11:19:26.507861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
29025 11:19:26.508295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
29027 11:19:26.543012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
29029 11:19:26.543309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
29030 11:19:26.578855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
29031 11:19:26.579252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
29033 11:19:26.614126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
29035 11:19:26.614712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
29036 11:19:26.648077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
29037 11:19:26.648418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
29039 11:19:26.684674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
29040 11:19:26.685067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
29042 11:19:26.720013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
29043 11:19:26.720387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
29045 11:19:26.755642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
29047 11:19:26.755975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
29048 11:19:26.791591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
29049 11:19:26.792022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
29051 11:19:26.826898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
29053 11:19:26.827407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
29054 11:19:26.861993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
29056 11:19:26.862513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
29057 11:19:26.898627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
29058 11:19:26.898999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
29060 11:19:26.933578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
29062 11:19:26.934134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
29063 11:19:26.968663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
29064 11:19:26.969085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
29066 11:19:27.003263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
29067 11:19:27.003552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
29069 11:19:27.038628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
29071 11:19:27.038929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
29072 11:19:27.072144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
29073 11:19:27.072500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
29075 11:19:27.105096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
29076 11:19:27.105486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
29078 11:19:27.137948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
29080 11:19:27.138455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
29081 11:19:27.171483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
29083 11:19:27.171987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
29084 11:19:27.203323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
29085 11:19:27.203758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
29087 11:19:27.236905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
29088 11:19:27.237321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
29090 11:19:27.270679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
29091 11:19:27.271132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
29093 11:19:27.303496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
29094 11:19:27.303985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
29096 11:19:27.337591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
29098 11:19:27.338201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
29099 11:19:27.371941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
29100 11:19:27.372376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
29102 11:19:27.407608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
29103 11:19:27.408017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
29105 11:19:27.441626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
29106 11:19:27.442140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
29108 11:19:27.475871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
29110 11:19:27.476423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
29111 11:19:27.508280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
29112 11:19:27.508695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
29114 11:19:27.540681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
29115 11:19:27.541117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
29117 11:19:27.572895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
29118 11:19:27.573389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
29120 11:19:27.614397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
29121 11:19:27.614868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
29123 11:19:27.646536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
29124 11:19:27.647036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
29126 11:19:27.678774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
29127 11:19:27.679250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
29129 11:19:27.711517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
29131 11:19:27.711976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
29132 11:19:27.743883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
29133 11:19:27.744295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
29135 11:19:27.776955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
29136 11:19:27.777436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
29138 11:19:27.809145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
29139 11:19:27.809538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
29141 11:19:27.841664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
29143 11:19:27.842252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
29144 11:19:27.873990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
29145 11:19:27.874390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
29147 11:19:27.906021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
29149 11:19:27.906564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
29150 11:19:27.939040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
29151 11:19:27.939398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
29153 11:19:27.971210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
29154 11:19:27.971604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
29156 11:19:28.003417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
29157 11:19:28.003847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
29159 11:19:28.035253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
29160 11:19:28.035690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
29162 11:19:28.067105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
29163 11:19:28.067523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
29165 11:19:28.098660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
29166 11:19:28.099102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
29168 11:19:28.129931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
29170 11:19:28.130399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
29171 11:19:28.162090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
29173 11:19:28.162564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
29174 11:19:28.195725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
29175 11:19:28.196137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
29177 11:19:28.228138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
29179 11:19:28.228602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
29180 11:19:28.259921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
29181 11:19:28.260358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
29183 11:19:28.292117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
29185 11:19:28.292572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
29186 11:19:28.324637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
29188 11:19:28.325093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
29189 11:19:28.356083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
29190 11:19:28.356512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
29192 11:19:28.387811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
29193 11:19:28.388248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
29195 11:19:28.420336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
29197 11:19:28.421005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
29198 11:19:28.452241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
29199 11:19:28.452728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
29201 11:19:28.484333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
29202 11:19:28.484801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
29204 11:19:28.517340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
29205 11:19:28.517683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
29207 11:19:28.550708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
29208 11:19:28.551196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
29210 11:19:28.584068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
29212 11:19:28.584621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
29213 11:19:28.615704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
29215 11:19:28.616153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
29216 11:19:28.648846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
29218 11:19:28.649308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
29219 11:19:28.684492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
29221 11:19:28.684944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
29222 11:19:28.716507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29224 11:19:28.716953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
29225 11:19:28.749338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29226 11:19:28.749752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29228 11:19:28.782551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29229 11:19:28.782985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29231 11:19:28.815189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29232 11:19:28.815614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29234 11:19:28.848573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29235 11:19:28.848988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29237 11:19:28.881474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29238 11:19:28.881908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29240 11:19:28.913830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29242 11:19:28.914288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29243 11:19:28.951305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29245 11:19:28.951760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29246 11:19:28.984363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29248 11:19:28.984814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29249 11:19:29.016597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29250 11:19:29.017088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29252 11:19:29.049264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29253 11:19:29.049712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29255 11:19:29.081724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29256 11:19:29.082146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29258 11:19:29.113907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29260 11:19:29.114476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29261 11:19:29.147009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29262 11:19:29.147500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29264 11:19:29.179271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29266 11:19:29.179891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29267 11:19:29.212503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29268 11:19:29.212981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29270 11:19:29.245231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29271 11:19:29.245699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29273 11:19:29.278730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29275 11:19:29.279190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29276 11:19:29.310722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29277 11:19:29.311160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29279 11:19:29.342947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29280 11:19:29.343363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29282 11:19:29.376008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29283 11:19:29.376445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29285 11:19:29.409096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29286 11:19:29.409532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29288 11:19:29.442633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29289 11:19:29.443034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29291 11:19:29.477149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29292 11:19:29.477626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29294 11:19:29.510633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29295 11:19:29.511084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29297 11:19:29.543986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29298 11:19:29.544492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29300 11:19:29.578783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29301 11:19:29.579266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29303 11:19:29.615091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29304 11:19:29.615548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29306 11:19:29.648621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29307 11:19:29.649205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29309 11:19:29.680844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29310 11:19:29.681310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29312 11:19:29.717406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29313 11:19:29.717908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29315 11:19:29.749769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29317 11:19:29.750241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29318 11:19:29.782408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29319 11:19:29.782821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29321 11:19:29.814721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29322 11:19:29.815160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29324 11:19:29.846810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29325 11:19:29.847246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29327 11:19:29.879019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29329 11:19:29.879482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29330 11:19:29.911199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29332 11:19:29.911769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29333 11:19:29.943123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29334 11:19:29.943590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29336 11:19:29.975209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29338 11:19:29.975759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29339 11:19:30.007265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29341 11:19:30.007822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29342 11:19:30.039689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29343 11:19:30.040153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29345 11:19:30.072448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29346 11:19:30.072918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29348 11:19:30.105163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29350 11:19:30.105727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29351 11:19:30.160109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29353 11:19:30.160566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29354 11:19:30.191583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29356 11:19:30.192160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29357 11:19:30.223291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29358 11:19:30.223766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29360 11:19:30.255658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29361 11:19:30.256214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29363 11:19:30.289373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29365 11:19:30.289976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29366 11:19:30.320962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29367 11:19:30.321441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29369 11:19:30.354545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29371 11:19:30.355097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29372 11:19:30.386863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29373 11:19:30.387303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29375 11:19:30.419188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29376 11:19:30.419661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29378 11:19:30.451657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29380 11:19:30.452245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29381 11:19:30.483896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29383 11:19:30.484484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29384 11:19:30.516304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29385 11:19:30.516719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29387 11:19:30.549633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29388 11:19:30.550138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29390 11:19:30.582317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29391 11:19:30.582756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29393 11:19:30.618735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29395 11:19:30.619140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29396 11:19:30.651037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29397 11:19:30.651364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29399 11:19:30.683078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29400 11:19:30.683432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29402 11:19:30.714762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29404 11:19:30.715209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29405 11:19:30.748297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29406 11:19:30.748694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29408 11:19:30.782828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29409 11:19:30.783205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29411 11:19:30.815010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29412 11:19:30.815493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29414 11:19:30.847967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29415 11:19:30.848440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29417 11:19:30.879350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29419 11:19:30.879912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29420 11:19:30.912792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29421 11:19:30.913161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29423 11:19:30.945140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29424 11:19:30.945539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29426 11:19:30.976675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29427 11:19:30.977029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29429 11:19:31.010187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29431 11:19:31.010749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29432 11:19:31.042955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29433 11:19:31.043266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29435 11:19:31.074536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29436 11:19:31.074823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29438 11:19:31.105332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29439 11:19:31.105678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29441 11:19:31.139197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29442 11:19:31.139548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29444 11:19:31.173309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29445 11:19:31.173615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29447 11:19:31.205448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29448 11:19:31.205846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29450 11:19:31.236950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29451 11:19:31.237238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29453 11:19:31.267696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29454 11:19:31.267983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29456 11:19:31.300229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29458 11:19:31.300786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29459 11:19:31.335417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29460 11:19:31.335818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29462 11:19:31.367936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29463 11:19:31.368257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29465 11:19:31.399699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29467 11:19:31.400149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29468 11:19:31.431345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29469 11:19:31.431726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29471 11:19:31.463448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29473 11:19:31.464093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29474 11:19:31.495188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29475 11:19:31.495593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29477 11:19:31.531948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29478 11:19:31.532332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29480 11:19:31.573079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29481 11:19:31.573481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29483 11:19:31.605793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29484 11:19:31.606261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29486 11:19:31.637726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29487 11:19:31.638168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29489 11:19:31.671137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29490 11:19:31.671485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29492 11:19:31.703472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29494 11:19:31.703943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29495 11:19:31.734856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29496 11:19:31.735212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29498 11:19:31.766943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29499 11:19:31.767234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29501 11:19:31.797695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29502 11:19:31.797982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29504 11:19:31.828831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29505 11:19:31.829118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29507 11:19:31.860415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29508 11:19:31.860767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29510 11:19:31.891713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29511 11:19:31.892070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29513 11:19:31.923538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29514 11:19:31.923891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29516 11:19:31.955191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29518 11:19:31.955642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29519 11:19:31.986739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29521 11:19:31.987205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29522 11:19:32.021321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29523 11:19:32.021774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29525 11:19:32.057466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29526 11:19:32.057803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29528 11:19:32.091373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29530 11:19:32.091677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29531 11:19:32.123315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29532 11:19:32.123684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29534 11:19:32.155023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29535 11:19:32.155378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29537 11:19:32.187106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29538 11:19:32.187465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29540 11:19:32.219050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29541 11:19:32.219404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29543 11:19:32.250545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29545 11:19:32.250981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29546 11:19:32.281675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29548 11:19:32.282104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29549 11:19:32.313129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29550 11:19:32.313416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29552 11:19:32.344815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29554 11:19:32.345041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29555 11:19:32.376151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29556 11:19:32.376428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29558 11:19:32.408132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29560 11:19:32.408577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29561 11:19:32.444125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29563 11:19:32.444574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29564 11:19:32.476226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29566 11:19:32.476795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29567 11:19:32.507360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29568 11:19:32.507708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29570 11:19:32.538888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29572 11:19:32.539323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29573 11:19:32.570149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29575 11:19:32.570579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29576 11:19:32.600804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29577 11:19:32.601151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29579 11:19:32.632387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29580 11:19:32.632680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29582 11:19:32.663447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29584 11:19:32.663742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29585 11:19:32.694074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29587 11:19:32.694525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29588 11:19:32.726182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29590 11:19:32.726639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29591 11:19:32.757641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29592 11:19:32.758067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29594 11:19:32.792607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29595 11:19:32.793075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29597 11:19:32.822758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29598 11:19:32.823230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29600 11:19:32.855050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29602 11:19:32.855632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29603 11:19:32.887644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29604 11:19:32.888052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29606 11:19:32.919165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29608 11:19:32.919747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29609 11:19:32.951053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29611 11:19:32.951658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29612 11:19:32.982804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29613 11:19:32.983217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29615 11:19:33.014659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29616 11:19:33.015066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29618 11:19:33.046508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29620 11:19:33.046951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29621 11:19:33.078123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29623 11:19:33.078560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29624 11:19:33.109409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29625 11:19:33.109810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29627 11:19:33.140942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29628 11:19:33.141306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29630 11:19:33.172001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29632 11:19:33.172301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29633 11:19:33.203620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29634 11:19:33.203897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29636 11:19:33.234996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29638 11:19:33.235425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29639 11:19:33.265864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29640 11:19:33.266211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29642 11:19:33.297290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29643 11:19:33.297637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29645 11:19:33.328649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29647 11:19:33.329071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29648 11:19:33.359869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29649 11:19:33.360217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29651 11:19:33.391183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29652 11:19:33.391540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29654 11:19:33.422109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29656 11:19:33.422533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29657 11:19:33.453527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29658 11:19:33.454033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29660 11:19:33.485281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29662 11:19:33.485902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29663 11:19:33.516241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29664 11:19:33.516622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29666 11:19:33.547203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29668 11:19:33.547656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29669 11:19:33.579184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29670 11:19:33.579590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29672 11:19:33.611088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29673 11:19:33.611496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29675 11:19:33.643165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29676 11:19:33.643575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29678 11:19:33.675066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29679 11:19:33.675470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29681 11:19:33.706160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29683 11:19:33.706599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29684 11:19:33.739840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29685 11:19:33.740229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29687 11:19:33.771573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29688 11:19:33.771939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29690 11:19:33.803646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29691 11:19:33.803928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29693 11:19:33.835370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29694 11:19:33.835647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29696 11:19:33.867722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29697 11:19:33.868115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29699 11:19:33.900032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29700 11:19:33.900510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29702 11:19:33.932130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29703 11:19:33.932592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29705 11:19:33.964445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29706 11:19:33.964884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29708 11:19:33.996758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29710 11:19:33.997203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29711 11:19:34.028547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29712 11:19:34.028971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29714 11:19:34.060992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29716 11:19:34.061448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29717 11:19:34.092238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29718 11:19:34.092650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29720 11:19:34.124242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29722 11:19:34.124683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29723 11:19:34.155969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29724 11:19:34.156392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29726 11:19:34.188308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29727 11:19:34.188709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29729 11:19:34.221013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29731 11:19:34.221527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29732 11:19:34.252486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29734 11:19:34.253107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29735 11:19:34.284480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29737 11:19:34.285103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29738 11:19:34.316321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29739 11:19:34.316790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29741 11:19:34.352020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29743 11:19:34.352584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29744 11:19:34.384165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29745 11:19:34.384599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29747 11:19:34.416404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29748 11:19:34.416834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29750 11:19:34.447601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29751 11:19:34.447957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29753 11:19:34.479727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29754 11:19:34.480208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29756 11:19:34.511389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29758 11:19:34.511845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29759 11:19:34.542906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29761 11:19:34.543450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29762 11:19:34.574749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29764 11:19:34.575272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29765 11:19:34.606284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29767 11:19:34.606741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29768 11:19:34.639398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29769 11:19:34.639769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29771 11:19:34.671701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29772 11:19:34.672030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29774 11:19:34.704334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29775 11:19:34.704686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29777 11:19:34.738332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29779 11:19:34.738773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29780 11:19:34.771031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29781 11:19:34.771439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29783 11:19:34.802973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29784 11:19:34.803378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29786 11:19:34.835778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29787 11:19:34.836152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29789 11:19:34.867198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29791 11:19:34.867699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29792 11:19:34.899251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29793 11:19:34.899597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29795 11:19:34.931367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29797 11:19:34.931906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29798 11:19:34.963334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29800 11:19:34.963918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29801 11:19:34.995073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29802 11:19:34.995552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29804 11:19:35.027663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29805 11:19:35.028115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29807 11:19:35.058770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29809 11:19:35.059199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29810 11:19:35.089954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29812 11:19:35.090428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29813 11:19:35.122851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29815 11:19:35.123415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29816 11:19:35.154929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29818 11:19:35.155561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29819 11:19:35.187029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29820 11:19:35.187437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29822 11:19:35.219099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29823 11:19:35.219457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29825 11:19:35.271918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29826 11:19:35.272263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29828 11:19:35.303848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29829 11:19:35.304195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29831 11:19:35.335456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29832 11:19:35.335867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29834 11:19:35.366974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29835 11:19:35.367378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29837 11:19:35.398663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29838 11:19:35.398995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29840 11:19:35.430716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29842 11:19:35.431013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29843 11:19:35.461859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29844 11:19:35.462205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29846 11:19:35.493177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29847 11:19:35.493524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29849 11:19:35.525172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29850 11:19:35.525521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29852 11:19:35.556739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29854 11:19:35.557248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29855 11:19:35.587797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29857 11:19:35.588283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29858 11:19:35.619609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29859 11:19:35.619973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29861 11:19:35.651152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29863 11:19:35.651451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29864 11:19:35.682840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29866 11:19:35.683427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29867 11:19:35.715537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29868 11:19:35.715992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29870 11:19:35.747176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29871 11:19:35.747612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29873 11:19:35.779643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29875 11:19:35.780198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29876 11:19:35.812249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29877 11:19:35.812634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29879 11:19:35.845204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29881 11:19:35.845739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29882 11:19:35.877897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29883 11:19:35.878279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29885 11:19:35.918589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29886 11:19:35.919006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29888 11:19:35.951396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29890 11:19:35.951911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29891 11:19:35.983287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29893 11:19:35.983725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29894 11:19:36.015164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29895 11:19:36.015519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29897 11:19:36.047069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29898 11:19:36.047626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29900 11:19:36.080152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29901 11:19:36.080616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29903 11:19:36.112794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29904 11:19:36.113227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29906 11:19:36.144856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29907 11:19:36.145200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29909 11:19:36.177036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29910 11:19:36.177383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29912 11:19:36.209598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29913 11:19:36.210032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29915 11:19:36.243762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29917 11:19:36.244219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29918 11:19:36.276316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29919 11:19:36.276801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29921 11:19:36.309439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29922 11:19:36.309911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29924 11:19:36.340840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29925 11:19:36.341204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29927 11:19:36.373034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29928 11:19:36.373396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29930 11:19:36.404837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29932 11:19:36.405275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29933 11:19:36.436833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29935 11:19:36.437353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29936 11:19:36.469370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29938 11:19:36.469998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29939 11:19:36.511645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29941 11:19:36.512283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29942 11:19:36.543576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29944 11:19:36.544024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29945 11:19:36.575930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29946 11:19:36.576358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29948 11:19:36.607634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29949 11:19:36.608039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29951 11:19:36.638843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29952 11:19:36.639197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29954 11:19:36.670703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29956 11:19:36.671169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29957 11:19:36.702014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29959 11:19:36.702591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29960 11:19:36.733108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29961 11:19:36.733536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29963 11:19:36.764835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29964 11:19:36.765282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29966 11:19:36.796121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29967 11:19:36.796561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29969 11:19:36.827746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29970 11:19:36.828194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29972 11:19:36.859030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29974 11:19:36.859538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29975 11:19:36.890771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29977 11:19:36.891305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29978 11:19:36.922608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29979 11:19:36.923045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
29981 11:19:36.954397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
29982 11:19:36.954824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
29984 11:19:36.986034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
29986 11:19:36.986581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
29987 11:19:37.017693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
29988 11:19:37.018132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
29990 11:19:37.048863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
29991 11:19:37.049305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
29993 11:19:37.080045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
29994 11:19:37.080474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
29996 11:19:37.112145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
29998 11:19:37.112594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
29999 11:19:37.143729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
30000 11:19:37.144138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
30002 11:19:37.175299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
30004 11:19:37.175925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
30005 11:19:37.207247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
30007 11:19:37.207868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
30008 11:19:37.238789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
30009 11:19:37.239222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
30011 11:19:37.271527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
30012 11:19:37.271940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
30014 11:19:37.303326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
30015 11:19:37.303755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
30017 11:19:37.336298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
30018 11:19:37.336728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
30020 11:19:37.368430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
30022 11:19:37.369007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
30023 11:19:37.399988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
30024 11:19:37.400351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
30026 11:19:37.431617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
30027 11:19:37.431962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
30029 11:19:37.463494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
30030 11:19:37.463849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
30032 11:19:37.495719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
30033 11:19:37.496104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
30035 11:19:37.527021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
30036 11:19:37.527418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
30038 11:19:37.559450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
30039 11:19:37.559862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
30041 11:19:37.591940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
30043 11:19:37.592532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
30044 11:19:37.623923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
30045 11:19:37.624386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
30047 11:19:37.655677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
30048 11:19:37.656026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
30050 11:19:37.686969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
30051 11:19:37.687255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
30053 11:19:37.720175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
30055 11:19:37.720655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
30056 11:19:37.754642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
30058 11:19:37.755101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
30059 11:19:37.787896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
30060 11:19:37.788365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
30062 11:19:37.821363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
30063 11:19:37.821764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
30065 11:19:37.856372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
30066 11:19:37.856795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
30068 11:19:37.891779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
30069 11:19:37.892133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
30071 11:19:37.925147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
30073 11:19:37.925599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
30074 11:19:37.958668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
30075 11:19:37.959127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
30077 11:19:37.990947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
30079 11:19:37.991354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
30080 11:19:38.023111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
30081 11:19:38.023465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
30083 11:19:38.055019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
30085 11:19:38.055322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
30086 11:19:38.086739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
30088 11:19:38.087194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
30089 11:19:38.118935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
30091 11:19:38.119303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
30092 11:19:38.150824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
30093 11:19:38.151234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
30095 11:19:38.181896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
30097 11:19:38.182256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
30098 11:19:38.213429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
30100 11:19:38.213822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
30101 11:19:38.244831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
30102 11:19:38.245277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
30104 11:19:38.276760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
30106 11:19:38.277373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
30107 11:19:38.308149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
30108 11:19:38.308626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
30110 11:19:38.344411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
30112 11:19:38.344968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
30113 11:19:38.376663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
30114 11:19:38.376960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
30116 11:19:38.407768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
30118 11:19:38.408230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
30119 11:19:38.439100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
30121 11:19:38.439564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
30122 11:19:38.470205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
30123 11:19:38.470635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
30125 11:19:38.501166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
30126 11:19:38.501610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
30128 11:19:38.532847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
30129 11:19:38.533328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
30131 11:19:38.564859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
30132 11:19:38.565334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
30134 11:19:38.597158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
30135 11:19:38.597566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
30137 11:19:38.630460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
30138 11:19:38.630878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
30140 11:19:38.661138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
30142 11:19:38.661604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
30143 11:19:38.691829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
30145 11:19:38.692262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
30146 11:19:38.722734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
30148 11:19:38.723044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
30149 11:19:38.753677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
30151 11:19:38.753971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
30152 11:19:38.785347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
30153 11:19:38.785626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
30155 11:19:38.818264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
30157 11:19:38.818910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
30158 11:19:38.851422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
30159 11:19:38.851784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
30161 11:19:38.883389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
30162 11:19:38.883707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
30164 11:19:38.915277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
30165 11:19:38.915635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
30167 11:19:38.947129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
30168 11:19:38.947452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
30170 11:19:38.979328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
30171 11:19:38.979627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
30173 11:19:39.013364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
30174 11:19:39.013686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
30176 11:19:39.046837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
30178 11:19:39.047286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
30179 11:19:39.079187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
30180 11:19:39.079546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
30182 11:19:39.112711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
30183 11:19:39.113131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
30185 11:19:39.147252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
30187 11:19:39.147698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
30188 11:19:39.181269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
30189 11:19:39.181633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
30191 11:19:39.215417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
30193 11:19:39.215892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
30194 11:19:39.248124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
30195 11:19:39.248523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
30197 11:19:39.281298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
30198 11:19:39.281679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
30200 11:19:39.313095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
30201 11:19:39.313502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
30203 11:19:39.344937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
30204 11:19:39.345339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
30206 11:19:39.376709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
30207 11:19:39.377119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
30209 11:19:39.409220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
30210 11:19:39.409629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
30212 11:19:39.440890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
30213 11:19:39.441293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
30215 11:19:39.472545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
30216 11:19:39.472822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
30218 11:19:39.506623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
30219 11:19:39.506966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
30221 11:19:39.539343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
30223 11:19:39.539893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
30224 11:19:39.572909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30225 11:19:39.573296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30227 11:19:39.606914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30229 11:19:39.607209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30230 11:19:39.640538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30232 11:19:39.641061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30233 11:19:39.674425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30234 11:19:39.674745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30236 11:19:39.706591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30237 11:19:39.706964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30239 11:19:39.738494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30240 11:19:39.738842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30242 11:19:39.769315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30243 11:19:39.769673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30245 11:19:39.800877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30247 11:19:39.801179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30248 11:19:39.831806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30249 11:19:39.832089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30251 11:19:39.863831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30252 11:19:39.864107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30254 11:19:39.895232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30255 11:19:39.895507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30257 11:19:39.926558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30258 11:19:39.926836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30260 11:19:39.957578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30261 11:19:39.957858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30263 11:19:39.988830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30264 11:19:39.989104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30266 11:19:40.020507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30267 11:19:40.020798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30269 11:19:40.052041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30271 11:19:40.052315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30272 11:19:40.086119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30274 11:19:40.086384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30275 11:19:40.117655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30276 11:19:40.117921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30278 11:19:40.149724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30279 11:19:40.150009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30281 11:19:40.182051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30283 11:19:40.182449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30284 11:19:40.213810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30286 11:19:40.214227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30287 11:19:40.246958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30288 11:19:40.247315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30290 11:19:40.279632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30291 11:19:40.279988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30293 11:19:40.312625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30295 11:19:40.313067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30296 11:19:40.344875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30297 11:19:40.345336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30299 11:19:40.398526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30300 11:19:40.398927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30302 11:19:40.429797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30303 11:19:40.430185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30305 11:19:40.462044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30307 11:19:40.462528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30308 11:19:40.493111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30309 11:19:40.493470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30311 11:19:40.524988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30312 11:19:40.525373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30314 11:19:40.557448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30316 11:19:40.557914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30317 11:19:40.589438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30318 11:19:40.589829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30320 11:19:40.623233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30322 11:19:40.623653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30323 11:19:40.658700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30324 11:19:40.659128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30326 11:19:40.691158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30327 11:19:40.691580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30329 11:19:40.724040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30330 11:19:40.724463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30332 11:19:40.755709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30334 11:19:40.756148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30335 11:19:40.787239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30336 11:19:40.787642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30338 11:19:40.819091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30340 11:19:40.819693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30341 11:19:40.851304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30342 11:19:40.851711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30344 11:19:40.883243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30346 11:19:40.883693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30347 11:19:40.917058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30348 11:19:40.917468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30350 11:19:40.948383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30352 11:19:40.948831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30353 11:19:40.982520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30354 11:19:40.982996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30356 11:19:41.015642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30358 11:19:41.016070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30359 11:19:41.049472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30361 11:19:41.049899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30362 11:19:41.084345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30363 11:19:41.084845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30365 11:19:41.117534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30366 11:19:41.118019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30368 11:19:41.149819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30370 11:19:41.150267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30371 11:19:41.182056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30373 11:19:41.182617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30374 11:19:41.214972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30376 11:19:41.215514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30377 11:19:41.247018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30378 11:19:41.247450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30380 11:19:41.279081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30381 11:19:41.279490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30383 11:19:41.314029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30384 11:19:41.314451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30386 11:19:41.346959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30387 11:19:41.347368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30389 11:19:41.379177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30391 11:19:41.379734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30392 11:19:41.411086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30394 11:19:41.411652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30395 11:19:41.443183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30396 11:19:41.443586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30398 11:19:41.475392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30399 11:19:41.475803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30401 11:19:41.508182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30403 11:19:41.508635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30404 11:19:41.540542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30405 11:19:41.540973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30407 11:19:41.573156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30408 11:19:41.573620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30410 11:19:41.604949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30411 11:19:41.605373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30413 11:19:41.636247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30415 11:19:41.636689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30416 11:19:41.667665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30417 11:19:41.668071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30419 11:19:41.699293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30421 11:19:41.699722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30422 11:19:41.731807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30424 11:19:41.732258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30425 11:19:41.765539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30427 11:19:41.766012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30428 11:19:41.801280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30430 11:19:41.801747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30431 11:19:41.834544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30433 11:19:41.834988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30434 11:19:41.865816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30435 11:19:41.866229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30437 11:19:41.897767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30438 11:19:41.898192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30440 11:19:41.929565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30441 11:19:41.930014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30443 11:19:41.961518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30445 11:19:41.961892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30446 11:19:41.993166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30448 11:19:41.993572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30449 11:19:42.024419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30450 11:19:42.024675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30452 11:19:42.055844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30453 11:19:42.056134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30455 11:19:42.087272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30457 11:19:42.087703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30458 11:19:42.122532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30459 11:19:42.122950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30461 11:19:42.154937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30462 11:19:42.155345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30464 11:19:42.187155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30465 11:19:42.187566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30467 11:19:42.219297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30468 11:19:42.219703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30470 11:19:42.251302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30471 11:19:42.251706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30473 11:19:42.283037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30474 11:19:42.283445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30476 11:19:42.319685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30477 11:19:42.320107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30479 11:19:42.353803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30480 11:19:42.354215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30482 11:19:42.386982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30484 11:19:42.387428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30485 11:19:42.418594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30486 11:19:42.418999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30488 11:19:42.449870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30489 11:19:42.450274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30491 11:19:42.480883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30492 11:19:42.481364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30494 11:19:42.512545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30495 11:19:42.513028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30497 11:19:42.544256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30499 11:19:42.544581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30500 11:19:42.575571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30501 11:19:42.575926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30503 11:19:42.607166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30504 11:19:42.607565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30506 11:19:42.639099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30508 11:19:42.639661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30509 11:19:42.670677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30510 11:19:42.671122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30512 11:19:42.701779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30514 11:19:42.702324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30515 11:19:42.733522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30516 11:19:42.733987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30518 11:19:42.764825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30519 11:19:42.765275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30521 11:19:42.796738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30522 11:19:42.797176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30524 11:19:42.829565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30525 11:19:42.830029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30527 11:19:42.860905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30528 11:19:42.861257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30530 11:19:42.891910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30531 11:19:42.892374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30533 11:19:42.923681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30535 11:19:42.924233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30536 11:19:42.955179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30537 11:19:42.955577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30539 11:19:42.987710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30541 11:19:42.988155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30542 11:19:43.019186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30544 11:19:43.019628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30545 11:19:43.050785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30546 11:19:43.051191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30548 11:19:43.082158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30550 11:19:43.082594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30551 11:19:43.114334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30552 11:19:43.114739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30554 11:19:43.146592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30556 11:19:43.147042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30557 11:19:43.177703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30558 11:19:43.178116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30560 11:19:43.208993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30562 11:19:43.209426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30563 11:19:43.240458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30564 11:19:43.240865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30566 11:19:43.272171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30568 11:19:43.272816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30569 11:19:43.303786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30571 11:19:43.304235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30572 11:19:43.335855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30573 11:19:43.336269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30575 11:19:43.367327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30576 11:19:43.367811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30578 11:19:43.398684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30580 11:19:43.399209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30581 11:19:43.429708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30583 11:19:43.430156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30584 11:19:43.465685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30586 11:19:43.466153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30587 11:19:43.498881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30588 11:19:43.499292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30590 11:19:43.532078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30591 11:19:43.532574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30593 11:19:43.571086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30594 11:19:43.571390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30596 11:19:43.608514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30598 11:19:43.609028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30599 11:19:43.643011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30601 11:19:43.643644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30602 11:19:43.676206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30603 11:19:43.676652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30605 11:19:43.710890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30607 11:19:43.711466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30608 11:19:43.744890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30609 11:19:43.745261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30611 11:19:43.779398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30612 11:19:43.779787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30614 11:19:43.814359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30615 11:19:43.814744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30617 11:19:43.848965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30619 11:19:43.849464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30620 11:19:43.880178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30621 11:19:43.880476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30623 11:19:43.911141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30625 11:19:43.911463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30626 11:19:43.942376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30628 11:19:43.942707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30629 11:19:43.972993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30630 11:19:43.973307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30632 11:19:44.003727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30633 11:19:44.004021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30635 11:19:44.035250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30636 11:19:44.035541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30638 11:19:44.067128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30639 11:19:44.067490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30641 11:19:44.098221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30643 11:19:44.098544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30644 11:19:44.129278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30645 11:19:44.129590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30647 11:19:44.160494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30648 11:19:44.160810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30650 11:19:44.192224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30651 11:19:44.192629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30653 11:19:44.223306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30654 11:19:44.223765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30656 11:19:44.254848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30658 11:19:44.255404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30659 11:19:44.286632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30660 11:19:44.287041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30662 11:19:44.317769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30663 11:19:44.318171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30665 11:19:44.349144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30666 11:19:44.349617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30668 11:19:44.380400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30669 11:19:44.380786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30671 11:19:44.411576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30672 11:19:44.412027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30674 11:19:44.443081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30676 11:19:44.443631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30677 11:19:44.474602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30678 11:19:44.475011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30680 11:19:44.509443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30681 11:19:44.509875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30683 11:19:44.540888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30684 11:19:44.541296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30686 11:19:44.572307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30687 11:19:44.572705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30689 11:19:44.605123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30690 11:19:44.605553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30692 11:19:44.640434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30693 11:19:44.640849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30695 11:19:44.675401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30696 11:19:44.675923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30698 11:19:44.708795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30699 11:19:44.709252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30701 11:19:44.744261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30703 11:19:44.744700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30704 11:19:44.775828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30705 11:19:44.776220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30707 11:19:44.807168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30709 11:19:44.807486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30710 11:19:44.839019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30711 11:19:44.839313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30713 11:19:44.871222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30715 11:19:44.871552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30716 11:19:44.901717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30717 11:19:44.902185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30719 11:19:44.936283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30721 11:19:44.936913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30722 11:19:44.967646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30723 11:19:44.968015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30725 11:19:44.999162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30726 11:19:44.999557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30728 11:19:45.030646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30730 11:19:45.031137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30731 11:19:45.062641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30732 11:19:45.062992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30734 11:19:45.093652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30735 11:19:45.094064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30737 11:19:45.125620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30738 11:19:45.126063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30740 11:19:45.157052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30741 11:19:45.157493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30743 11:19:45.188635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30745 11:19:45.189249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30746 11:19:45.220894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30747 11:19:45.221356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30749 11:19:45.252935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30751 11:19:45.253541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30752 11:19:45.284101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30753 11:19:45.284487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30755 11:19:45.315142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30756 11:19:45.315444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30758 11:19:45.346451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30759 11:19:45.346741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30761 11:19:45.377008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30763 11:19:45.377454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30764 11:19:45.408425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30766 11:19:45.408867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30767 11:19:45.440275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30768 11:19:45.440666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30770 11:19:45.471959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30772 11:19:45.472510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30773 11:19:45.524851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30774 11:19:45.525259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30776 11:19:45.556644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30778 11:19:45.557215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30779 11:19:45.588280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30781 11:19:45.588835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30782 11:19:45.619760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30783 11:19:45.620161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30785 11:19:45.652841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30786 11:19:45.653287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30788 11:19:45.685114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30790 11:19:45.685552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30791 11:19:45.717834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30792 11:19:45.718294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30794 11:19:45.750609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30795 11:19:45.751031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30797 11:19:45.789290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30799 11:19:45.789751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30800 11:19:45.821070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30801 11:19:45.821525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30803 11:19:45.852992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30804 11:19:45.853386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30806 11:19:45.884179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30808 11:19:45.884607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30809 11:19:45.916195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30810 11:19:45.916595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30812 11:19:45.947713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30813 11:19:45.948170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30815 11:19:45.978732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30816 11:19:45.979181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30818 11:19:46.010510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30820 11:19:46.011050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30821 11:19:46.041655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30822 11:19:46.042153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30824 11:19:46.076895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30826 11:19:46.077525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30827 11:19:46.109270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30829 11:19:46.109903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30830 11:19:46.140594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30832 11:19:46.141239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30833 11:19:46.171884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30834 11:19:46.172355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30836 11:19:46.203500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30837 11:19:46.203971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30839 11:19:46.235532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30840 11:19:46.235982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30842 11:19:46.268298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30843 11:19:46.268710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30845 11:19:46.300486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30847 11:19:46.300956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30848 11:19:46.332966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30849 11:19:46.333430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30851 11:19:46.365394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30852 11:19:46.365885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30854 11:19:46.397162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30855 11:19:46.397619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30857 11:19:46.429342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30858 11:19:46.429788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30860 11:19:46.461119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30861 11:19:46.461554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30863 11:19:46.493289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30864 11:19:46.493757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30866 11:19:46.525672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30868 11:19:46.526215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30869 11:19:46.557713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30870 11:19:46.558104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30872 11:19:46.590481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30873 11:19:46.590885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30875 11:19:46.622647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30877 11:19:46.623201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30878 11:19:46.653712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30879 11:19:46.654076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30881 11:19:46.686617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30882 11:19:46.686998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30884 11:19:46.718626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30885 11:19:46.719084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30887 11:19:46.750894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30889 11:19:46.751511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30890 11:19:46.783097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30892 11:19:46.783752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30893 11:19:46.815209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30894 11:19:46.815679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30896 11:19:46.848971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30897 11:19:46.849452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30899 11:19:46.881532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30901 11:19:46.882143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30902 11:19:46.913052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30903 11:19:46.913551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30905 11:19:46.944820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30906 11:19:46.945392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30908 11:19:46.980636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30910 11:19:46.981240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30911 11:19:47.012309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30913 11:19:47.012868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30914 11:19:47.044221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30916 11:19:47.044682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30917 11:19:47.075771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30919 11:19:47.076346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30920 11:19:47.107404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30921 11:19:47.107863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30923 11:19:47.139504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30924 11:19:47.139948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30926 11:19:47.171643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30927 11:19:47.172100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30929 11:19:47.203289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30930 11:19:47.203703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30932 11:19:47.235123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30933 11:19:47.235576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30935 11:19:47.266897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30936 11:19:47.267342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30938 11:19:47.299027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30939 11:19:47.299474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30941 11:19:47.330613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30942 11:19:47.331019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30944 11:19:47.361420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30946 11:19:47.361893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30947 11:19:47.392595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30948 11:19:47.392891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30950 11:19:47.423724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30952 11:19:47.424249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30953 11:19:47.454983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30954 11:19:47.455407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30956 11:19:47.486771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30957 11:19:47.487179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30959 11:19:47.518503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30960 11:19:47.518908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30962 11:19:47.549419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30963 11:19:47.549906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30965 11:19:47.581365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30966 11:19:47.581817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30968 11:19:47.614797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30970 11:19:47.615350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30971 11:19:47.647049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30973 11:19:47.647502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30974 11:19:47.678298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30976 11:19:47.678972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30977 11:19:47.709516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
30978 11:19:47.709908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30980 11:19:47.741133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
30981 11:19:47.741588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
30983 11:19:47.772481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
30984 11:19:47.772970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
30986 11:19:47.803929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
30988 11:19:47.804482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
30989 11:19:47.835467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
30990 11:19:47.835867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
30992 11:19:47.866524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
30993 11:19:47.866889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
30995 11:19:47.897367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
30996 11:19:47.897682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
30998 11:19:47.929019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
30999 11:19:47.929319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
31001 11:19:47.960753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
31002 11:19:47.961047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
31004 11:19:47.992054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
31006 11:19:47.992375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
31007 11:19:48.023430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
31008 11:19:48.023720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
31010 11:19:48.055104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
31011 11:19:48.055396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
31013 11:19:48.086768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
31015 11:19:48.087088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
31016 11:19:48.118528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
31017 11:19:48.118890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
31019 11:19:48.150897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
31020 11:19:48.151332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
31022 11:19:48.183264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
31023 11:19:48.183626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
31025 11:19:48.215025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
31027 11:19:48.215358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
31028 11:19:48.246771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
31030 11:19:48.247281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
31031 11:19:48.278338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
31032 11:19:48.278797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
31034 11:19:48.309917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
31036 11:19:48.310360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
31037 11:19:48.342159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
31039 11:19:48.342596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
31040 11:19:48.373636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
31042 11:19:48.374059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
31043 11:19:48.404944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
31044 11:19:48.405359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
31046 11:19:48.436919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
31048 11:19:48.437378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
31049 11:19:48.468951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
31051 11:19:48.469389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
31052 11:19:48.500909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
31053 11:19:48.501339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
31055 11:19:48.533820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
31056 11:19:48.534275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
31058 11:19:48.569245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
31060 11:19:48.569561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
31061 11:19:48.600764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
31062 11:19:48.601051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
31064 11:19:48.632168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
31065 11:19:48.632535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
31067 11:19:48.663944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
31068 11:19:48.664308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
31070 11:19:48.697371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
31071 11:19:48.697829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
31073 11:19:48.730519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
31074 11:19:48.730908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
31076 11:19:48.762505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
31077 11:19:48.762754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
31079 11:19:48.795526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
31080 11:19:48.795890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
31082 11:19:48.827769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
31084 11:19:48.828397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
31085 11:19:48.861669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
31086 11:19:48.861995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
31088 11:19:48.895099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
31089 11:19:48.895563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
31091 11:19:48.928828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
31093 11:19:48.929302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
31094 11:19:48.961941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
31096 11:19:48.962390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
31097 11:19:48.994447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
31099 11:19:48.994925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
31100 11:19:49.027628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
31101 11:19:49.028044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
31103 11:19:49.059703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
31105 11:19:49.060147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
31106 11:19:49.092197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
31108 11:19:49.092638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
31109 11:19:49.124169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
31110 11:19:49.124580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
31112 11:19:49.155853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
31114 11:19:49.156503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
31115 11:19:49.188628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
31116 11:19:49.189096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
31118 11:19:49.221176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
31119 11:19:49.221585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
31121 11:19:49.252979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
31123 11:19:49.253508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
31124 11:19:49.284701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
31125 11:19:49.285007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
31127 11:19:49.316212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
31128 11:19:49.316582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
31130 11:19:49.348689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
31131 11:19:49.349038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
31133 11:19:49.381010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
31134 11:19:49.381406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
31136 11:19:49.412807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
31137 11:19:49.413230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
31139 11:19:49.445394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
31141 11:19:49.445844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
31142 11:19:49.477219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
31143 11:19:49.477603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
31145 11:19:49.512341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
31146 11:19:49.512808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
31148 11:19:49.547670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
31150 11:19:49.548089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
31151 11:19:49.584750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
31152 11:19:49.585184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
31154 11:19:49.622935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
31155 11:19:49.623339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
31157 11:19:49.657076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
31158 11:19:49.657544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
31160 11:19:49.690796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
31161 11:19:49.691196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
31163 11:19:49.722611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
31164 11:19:49.723090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
31166 11:19:49.753642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
31167 11:19:49.754068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
31169 11:19:49.786227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
31171 11:19:49.786680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
31172 11:19:49.817555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
31173 11:19:49.817982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
31175 11:19:49.848886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
31176 11:19:49.849290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
31178 11:19:49.880275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
31179 11:19:49.880694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
31181 11:19:49.911872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
31182 11:19:49.912322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
31184 11:19:49.943218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
31185 11:19:49.943697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
31187 11:19:49.974419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
31188 11:19:49.974830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
31190 11:19:50.006650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
31191 11:19:50.007075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
31193 11:19:50.038882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
31195 11:19:50.039277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
31196 11:19:50.070970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
31197 11:19:50.071310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
31199 11:19:50.103244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
31201 11:19:50.103679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
31202 11:19:50.135100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
31204 11:19:50.135514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
31205 11:19:50.167704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
31206 11:19:50.168043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
31208 11:19:50.199809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
31209 11:19:50.200160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
31211 11:19:50.232322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
31212 11:19:50.232684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
31214 11:19:50.265394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
31215 11:19:50.265753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
31217 11:19:50.296888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
31218 11:19:50.297184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
31220 11:19:50.328411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
31222 11:19:50.328869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
31223 11:19:50.361298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31224 11:19:50.361770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31226 11:19:50.394005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31228 11:19:50.394449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31229 11:19:50.426089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31231 11:19:50.426547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31232 11:19:50.459161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31234 11:19:50.459788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31235 11:19:50.491908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31237 11:19:50.492558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31238 11:19:50.524332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31240 11:19:50.524830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31241 11:19:50.555525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31242 11:19:50.555849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31244 11:19:50.587561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31245 11:19:50.587956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31247 11:19:50.665836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31249 11:19:50.666407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31250 11:19:50.708650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31252 11:19:50.709110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31253 11:19:50.739843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31254 11:19:50.740248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31256 11:19:50.773777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31257 11:19:50.774322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31259 11:19:50.805282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31260 11:19:50.805686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31262 11:19:50.836912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31263 11:19:50.837298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31265 11:19:50.868575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31266 11:19:50.869063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31268 11:19:50.902164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31270 11:19:50.902592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31271 11:19:50.935378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31272 11:19:50.935762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31274 11:19:50.967257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31275 11:19:50.967652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31277 11:19:50.998794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31278 11:19:50.999186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31280 11:19:51.030993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31281 11:19:51.031414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31283 11:19:51.063762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31284 11:19:51.064252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31286 11:19:51.095650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31287 11:19:51.096099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31289 11:19:51.128517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31290 11:19:51.128929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31292 11:19:51.160664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31294 11:19:51.161121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31295 11:19:51.192622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31297 11:19:51.193070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31298 11:19:51.225248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31299 11:19:51.225628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31301 11:19:51.257562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31302 11:19:51.258009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31304 11:19:51.289248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31305 11:19:51.289716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31307 11:19:51.321029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31308 11:19:51.321310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31310 11:19:51.352582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31311 11:19:51.352933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31313 11:19:51.384089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31314 11:19:51.384460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31316 11:19:51.415661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31318 11:19:51.416148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31319 11:19:51.447283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31321 11:19:51.447770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31322 11:19:51.479523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31323 11:19:51.479880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31325 11:19:51.511420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31326 11:19:51.511788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31328 11:19:51.543131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31329 11:19:51.543494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31331 11:19:51.552999 <47>[ 302.757366] systemd-journald[109]: Sent WATCHDOG=1 notification.
31332 11:19:51.579838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31334 11:19:51.580270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31335 11:19:51.611545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31336 11:19:51.611940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31338 11:19:51.643814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31340 11:19:51.644379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31341 11:19:51.676134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31343 11:19:51.676681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31344 11:19:51.708188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31345 11:19:51.708633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31347 11:19:51.739917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31348 11:19:51.740378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31350 11:19:51.772147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31351 11:19:51.772591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31353 11:19:51.804143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31354 11:19:51.804603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31356 11:19:51.836274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31358 11:19:51.836848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31359 11:19:51.868442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31360 11:19:51.868902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31362 11:19:51.901384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31363 11:19:51.901851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31365 11:19:51.933358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31367 11:19:51.933919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31368 11:19:51.965744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31369 11:19:51.966232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31371 11:19:51.998979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31372 11:19:51.999415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31374 11:19:52.031291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31375 11:19:52.031677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31377 11:19:52.063658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31379 11:19:52.064094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31380 11:19:52.095404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31381 11:19:52.095690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31383 11:19:52.127060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31384 11:19:52.127343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31386 11:19:52.159975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31387 11:19:52.160324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31389 11:19:52.192073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31390 11:19:52.192436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31392 11:19:52.223882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31394 11:19:52.224313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31395 11:19:52.258198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31397 11:19:52.258667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31398 11:19:52.292445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31400 11:19:52.292891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31401 11:19:52.325199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31403 11:19:52.325658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31404 11:19:52.358858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31406 11:19:52.359490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31407 11:19:52.391199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31408 11:19:52.391574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31410 11:19:52.424506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31412 11:19:52.425084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31413 11:19:52.457050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31414 11:19:52.457507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31416 11:19:52.489402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31417 11:19:52.489830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31419 11:19:52.522806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31420 11:19:52.523222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31422 11:19:52.556742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31424 11:19:52.557111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31425 11:19:52.588744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31426 11:19:52.589243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31428 11:19:52.620290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31429 11:19:52.620608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31431 11:19:52.653781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31432 11:19:52.654107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31434 11:19:52.686039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31436 11:19:52.686381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31437 11:19:52.734815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31438 11:19:52.735103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31440 11:19:52.768344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31441 11:19:52.768869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31443 11:19:52.800934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31444 11:19:52.801323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31446 11:19:52.832979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31447 11:19:52.833329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31449 11:19:52.864567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31450 11:19:52.864911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31452 11:19:52.897113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31454 11:19:52.897588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31455 11:19:52.929131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31456 11:19:52.929558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31458 11:19:52.962605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31459 11:19:52.962934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31461 11:19:52.995478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31463 11:19:52.995784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31464 11:19:53.029585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31465 11:19:53.029875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31467 11:19:53.063824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31468 11:19:53.064106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31470 11:19:53.096581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31471 11:19:53.097052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31473 11:19:53.129006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31474 11:19:53.129358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31476 11:19:53.161249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31477 11:19:53.161594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31479 11:19:53.193594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31480 11:19:53.193885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31482 11:19:53.226425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31483 11:19:53.226818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31485 11:19:53.258579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31486 11:19:53.258855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31488 11:19:53.291893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31489 11:19:53.292236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31491 11:19:53.323682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31492 11:19:53.324079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31494 11:19:53.355707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31495 11:19:53.356112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31497 11:19:53.387086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31498 11:19:53.387483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31500 11:19:53.419403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31501 11:19:53.419825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31503 11:19:53.451226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31504 11:19:53.451636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31506 11:19:53.482777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31507 11:19:53.483174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31509 11:19:53.514702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31510 11:19:53.515134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31512 11:19:53.546039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31514 11:19:53.546536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31515 11:19:53.577745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31517 11:19:53.578051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31518 11:19:53.608812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31519 11:19:53.609096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31521 11:19:53.640680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31522 11:19:53.641070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31524 11:19:53.674234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31526 11:19:53.674883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31527 11:19:53.706111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31529 11:19:53.706556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31530 11:19:53.737710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31531 11:19:53.738171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31533 11:19:53.768932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31534 11:19:53.769277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31536 11:19:53.799826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31538 11:19:53.800245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31539 11:19:53.831134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31540 11:19:53.831503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31542 11:19:53.863067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31543 11:19:53.863414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31545 11:19:53.894034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31547 11:19:53.894467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31548 11:19:53.925373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31549 11:19:53.925683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31551 11:19:53.956923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31553 11:19:53.957349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31554 11:19:53.988398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31555 11:19:53.988750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31557 11:19:54.019609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31558 11:19:54.019960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31560 11:19:54.050880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31561 11:19:54.051221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31563 11:19:54.081510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31564 11:19:54.081945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31566 11:19:54.113164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31568 11:19:54.113625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31569 11:19:54.144591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31571 11:19:54.145236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31572 11:19:54.176210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31574 11:19:54.176653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31575 11:19:54.207931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31576 11:19:54.208337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31578 11:19:54.240214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31579 11:19:54.240639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31581 11:19:54.271966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31582 11:19:54.272375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31584 11:19:54.303991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31585 11:19:54.304460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31587 11:19:54.335661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31588 11:19:54.336127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31590 11:19:54.371135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31591 11:19:54.371519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31593 11:19:54.403115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31594 11:19:54.403461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31596 11:19:54.435413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31598 11:19:54.435868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31599 11:19:54.467369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31600 11:19:54.467811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31602 11:19:54.499170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31603 11:19:54.499516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31605 11:19:54.531183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31606 11:19:54.531647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31608 11:19:54.563007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31609 11:19:54.563482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31611 11:19:54.595260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31612 11:19:54.595665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31614 11:19:54.627890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31615 11:19:54.628284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31617 11:19:54.659373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31618 11:19:54.659764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31620 11:19:54.691300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31622 11:19:54.691790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31623 11:19:54.723098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31624 11:19:54.723467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31626 11:19:54.755194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31628 11:19:54.755597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31629 11:19:54.787306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31631 11:19:54.787702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31632 11:19:54.818978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31633 11:19:54.819252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31635 11:19:54.850910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31637 11:19:54.851345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31638 11:19:54.883298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31640 11:19:54.883931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31641 11:19:54.915154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31642 11:19:54.915559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31644 11:19:54.947408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31645 11:19:54.947890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31647 11:19:54.979651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31649 11:19:54.980238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31650 11:19:55.012648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31651 11:19:55.013144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31653 11:19:55.044583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31655 11:19:55.045079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31656 11:19:55.075583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31657 11:19:55.075932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31659 11:19:55.108345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31660 11:19:55.108848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31662 11:19:55.141025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31664 11:19:55.141423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31665 11:19:55.173620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31666 11:19:55.174067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31668 11:19:55.207472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31670 11:19:55.208041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31671 11:19:55.239253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31672 11:19:55.239740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31674 11:19:55.273237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31675 11:19:55.273769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31677 11:19:55.307960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31678 11:19:55.308535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31680 11:19:55.341167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31681 11:19:55.341597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31683 11:19:55.373659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31684 11:19:55.374078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31686 11:19:55.405490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31688 11:19:55.406164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31689 11:19:55.437867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31691 11:19:55.438326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31692 11:19:55.471093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31693 11:19:55.471571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31695 11:19:55.502994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31696 11:19:55.503464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31698 11:19:55.534523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31700 11:19:55.535135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31701 11:19:55.565552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31702 11:19:55.565964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31704 11:19:55.598208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31706 11:19:55.598651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31707 11:19:55.630498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31708 11:19:55.630905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31710 11:19:55.662922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31712 11:19:55.663361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31713 11:19:55.694387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31715 11:19:55.694953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31716 11:19:55.747537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31718 11:19:55.747966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31719 11:19:55.781018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31720 11:19:55.781381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31722 11:19:55.812897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31723 11:19:55.813257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31725 11:19:55.844765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31726 11:19:55.845055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31728 11:19:55.875780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31729 11:19:55.876068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31731 11:19:55.907507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31732 11:19:55.907790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31734 11:19:55.938992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31736 11:19:55.939509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31737 11:19:55.971601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31739 11:19:55.972057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31740 11:19:56.005399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31742 11:19:56.005774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31743 11:19:56.037061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31744 11:19:56.037349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31746 11:19:56.069138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31747 11:19:56.069534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31749 11:19:56.100917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31750 11:19:56.101324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31752 11:19:56.132976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31753 11:19:56.133416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31755 11:19:56.165043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31756 11:19:56.165453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31758 11:19:56.196777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31759 11:19:56.197235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31761 11:19:56.228292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31763 11:19:56.228847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31764 11:19:56.259715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31766 11:19:56.260160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31767 11:19:56.291404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31768 11:19:56.291849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31770 11:19:56.323892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31771 11:19:56.324277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31773 11:19:56.355741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31774 11:19:56.356090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31776 11:19:56.387607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31777 11:19:56.387956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31779 11:19:56.419487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31781 11:19:56.419790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31782 11:19:56.451061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31783 11:19:56.451415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31785 11:19:56.482749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31786 11:19:56.483109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31788 11:19:56.515138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31790 11:19:56.515575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31791 11:19:56.546991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31793 11:19:56.547457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31794 11:19:56.578936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31795 11:19:56.579338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31797 11:19:56.610504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31799 11:19:56.610942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31800 11:19:56.642556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31801 11:19:56.642966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31803 11:19:56.675726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31804 11:19:56.676134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31806 11:19:56.707340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31807 11:19:56.707764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31809 11:19:56.739157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31810 11:19:56.739583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31812 11:19:56.771184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31814 11:19:56.771715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31815 11:19:56.802337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31816 11:19:56.802681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31818 11:19:56.833439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31819 11:19:56.833789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31821 11:19:56.865061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31822 11:19:56.865349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31824 11:19:56.896700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31826 11:19:56.897127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31827 11:19:56.927992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31828 11:19:56.928278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31830 11:19:56.959853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31831 11:19:56.960222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31833 11:19:56.991152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31834 11:19:56.991435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31836 11:19:57.022768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31837 11:19:57.023052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31839 11:19:57.053793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31840 11:19:57.054075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31842 11:19:57.086574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31844 11:19:57.086866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31845 11:19:57.118653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31846 11:19:57.119058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31848 11:19:57.151883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31850 11:19:57.152390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31851 11:19:57.184593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31853 11:19:57.185053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31854 11:19:57.218915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31855 11:19:57.219266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31857 11:19:57.251011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31858 11:19:57.251366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31860 11:19:57.282846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31862 11:19:57.283269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31863 11:19:57.314815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31865 11:19:57.315381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31866 11:19:57.348210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31867 11:19:57.348608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31869 11:19:57.379921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31870 11:19:57.380194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31872 11:19:57.411442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31873 11:19:57.411840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31875 11:19:57.443233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31876 11:19:57.443614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31878 11:19:57.474971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31880 11:19:57.475339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31881 11:19:57.508473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31882 11:19:57.508835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31884 11:19:57.540759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31885 11:19:57.541037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31887 11:19:57.572794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31888 11:19:57.573083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31890 11:19:57.604134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31891 11:19:57.604503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31893 11:19:57.635593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31895 11:19:57.636024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31896 11:19:57.667267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31897 11:19:57.667615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31899 11:19:57.699951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31900 11:19:57.700299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31902 11:19:57.731789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31903 11:19:57.732155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31905 11:19:57.763164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31906 11:19:57.763515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31908 11:19:57.794839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31909 11:19:57.795237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31911 11:19:57.826644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31912 11:19:57.827023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31914 11:19:57.857441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31915 11:19:57.857879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31917 11:19:57.889615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31919 11:19:57.890094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31920 11:19:57.924055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31922 11:19:57.924596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31923 11:19:57.955989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31925 11:19:57.956438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31926 11:19:57.987950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31928 11:19:57.988403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31929 11:19:58.019678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31930 11:19:58.020056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31932 11:19:58.051223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31934 11:19:58.051667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31935 11:19:58.083722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31937 11:19:58.084367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31938 11:19:58.116646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31940 11:19:58.117186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31941 11:19:58.147721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31942 11:19:58.148142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31944 11:19:58.181246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31946 11:19:58.181719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31947 11:19:58.212902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31948 11:19:58.213263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31950 11:19:58.244679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31951 11:19:58.245029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31953 11:19:58.276390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31954 11:19:58.276736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31956 11:19:58.309191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31957 11:19:58.309608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31959 11:19:58.341621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31960 11:19:58.342053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31962 11:19:58.374625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31963 11:19:58.375039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31965 11:19:58.406608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31967 11:19:58.407174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31968 11:19:58.438192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31970 11:19:58.438792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31971 11:19:58.469271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31972 11:19:58.469636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31974 11:19:58.502871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31975 11:19:58.503331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31977 11:19:58.536567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31978 11:19:58.537041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31980 11:19:58.569324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
31982 11:19:58.569774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
31983 11:19:58.601846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
31984 11:19:58.602257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
31986 11:19:58.634042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
31988 11:19:58.634493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
31989 11:19:58.665710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
31991 11:19:58.666151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
31992 11:19:58.697394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
31994 11:19:58.697917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
31995 11:19:58.731181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
31997 11:19:58.731634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
31998 11:19:58.765435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
32000 11:19:58.765886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
32001 11:19:58.809189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
32002 11:19:58.809676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
32004 11:19:58.839389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
32006 11:19:58.839836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
32007 11:19:58.871694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
32008 11:19:58.872062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
32010 11:19:58.904053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
32011 11:19:58.904470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
32013 11:19:58.935513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
32014 11:19:58.935769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
32016 11:19:58.971583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
32017 11:19:58.971946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
32019 11:19:59.005242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
32020 11:19:59.005632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
32022 11:19:59.037110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
32024 11:19:59.037441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
32025 11:19:59.070999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
32026 11:19:59.071458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
32028 11:19:59.103094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
32029 11:19:59.103512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
32031 11:19:59.135026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
32032 11:19:59.135457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
32034 11:19:59.168340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
32035 11:19:59.168750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
32037 11:19:59.200661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
32038 11:19:59.201076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
32040 11:19:59.234522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
32042 11:19:59.234981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
32043 11:19:59.267343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
32044 11:19:59.267644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
32046 11:19:59.299297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
32047 11:19:59.299768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
32049 11:19:59.331340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
32051 11:19:59.331975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
32052 11:19:59.362932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
32053 11:19:59.363382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
32055 11:19:59.394503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
32056 11:19:59.394942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
32058 11:19:59.426630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
32059 11:19:59.427078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
32061 11:19:59.459277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
32062 11:19:59.459711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
32064 11:19:59.492272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
32065 11:19:59.492684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
32067 11:19:59.524709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
32068 11:19:59.525186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
32070 11:19:59.556517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
32071 11:19:59.556867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
32073 11:19:59.589768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
32074 11:19:59.590139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
32076 11:19:59.623213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
32077 11:19:59.623565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
32079 11:19:59.656768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
32080 11:19:59.657114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
32082 11:19:59.690485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
32083 11:19:59.690879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
32085 11:19:59.725319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
32087 11:19:59.725878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
32088 11:19:59.757250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
32090 11:19:59.757709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
32091 11:19:59.788814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
32092 11:19:59.789180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
32094 11:19:59.819527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
32095 11:19:59.819878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
32097 11:19:59.850699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
32098 11:19:59.851045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
32100 11:19:59.882788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
32101 11:19:59.883201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
32103 11:19:59.913488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
32104 11:19:59.913857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
32106 11:19:59.945148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
32108 11:19:59.945893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
32109 11:19:59.976836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
32110 11:19:59.977342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
32112 11:20:00.008993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
32113 11:20:00.009494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
32115 11:20:00.043209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
32116 11:20:00.043621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
32118 11:20:00.074943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
32119 11:20:00.075418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
32121 11:20:00.106270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
32123 11:20:00.106833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
32124 11:20:00.137409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
32125 11:20:00.137882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
32127 11:20:00.168984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
32128 11:20:00.169437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
32130 11:20:00.203106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
32131 11:20:00.203542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
32133 11:20:00.235454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
32134 11:20:00.235934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
32136 11:20:00.267683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
32138 11:20:00.268276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
32139 11:20:00.299769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
32141 11:20:00.300341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
32142 11:20:00.331366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
32143 11:20:00.331717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
32145 11:20:00.363220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
32146 11:20:00.363511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
32148 11:20:00.395193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
32149 11:20:00.395589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
32151 11:20:00.427669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
32152 11:20:00.428128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
32154 11:20:00.460316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
32156 11:20:00.460853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
32157 11:20:00.492888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
32158 11:20:00.493299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
32160 11:20:00.525714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
32161 11:20:00.526135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
32163 11:20:00.558256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
32165 11:20:00.558802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
32166 11:20:00.590932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
32167 11:20:00.591262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
32169 11:20:00.623453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
32171 11:20:00.623914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
32172 11:20:00.656458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
32174 11:20:00.657032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
32175 11:20:00.688346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
32177 11:20:00.688797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
32178 11:20:00.720415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
32179 11:20:00.720823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
32181 11:20:00.752284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
32183 11:20:00.752731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
32184 11:20:00.783950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
32185 11:20:00.784429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
32187 11:20:00.816256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
32188 11:20:00.816620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
32190 11:20:00.871515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
32192 11:20:00.871959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
32193 11:20:00.903887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
32194 11:20:00.904264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
32196 11:20:00.936024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
32197 11:20:00.936301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
32199 11:20:00.967239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
32200 11:20:00.967579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
32202 11:20:00.998872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
32204 11:20:00.999170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
32205 11:20:01.030265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
32206 11:20:01.030632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
32208 11:20:01.061515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
32209 11:20:01.061897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
32211 11:20:01.092355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
32213 11:20:01.092814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
32214 11:20:01.123646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
32216 11:20:01.124192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
32217 11:20:01.155062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
32218 11:20:01.155484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
32220 11:20:01.186649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
32221 11:20:01.187027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
32223 11:20:01.217788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32225 11:20:01.218245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
32226 11:20:01.250553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32227 11:20:01.250966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32229 11:20:01.281703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32230 11:20:01.282110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32232 11:20:01.313057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32233 11:20:01.313465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32235 11:20:01.344291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32236 11:20:01.344706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32238 11:20:01.375716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32240 11:20:01.376160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32241 11:20:01.407408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32243 11:20:01.407856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32244 11:20:01.439349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32245 11:20:01.439751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32247 11:20:01.471125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32249 11:20:01.471568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32250 11:20:01.503451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32251 11:20:01.503879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32253 11:20:01.535671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32255 11:20:01.536177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32256 11:20:01.566782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32257 11:20:01.567135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32259 11:20:01.597782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32260 11:20:01.598149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32262 11:20:01.629111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32263 11:20:01.629470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32265 11:20:01.660188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32266 11:20:01.660643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32268 11:20:01.692644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32269 11:20:01.693027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32271 11:20:01.724595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32272 11:20:01.724941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32274 11:20:01.755682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32275 11:20:01.756044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32277 11:20:01.787263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32278 11:20:01.787700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32280 11:20:01.818722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32281 11:20:01.819184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32283 11:20:01.850861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32285 11:20:01.851295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32286 11:20:01.883011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32288 11:20:01.883452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32289 11:20:01.915383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32291 11:20:01.915832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32292 11:20:01.947199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32294 11:20:01.947656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32295 11:20:01.978916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32296 11:20:01.979312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32298 11:20:02.010973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32300 11:20:02.011413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32301 11:20:02.042834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32303 11:20:02.043458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32304 11:20:02.075035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32306 11:20:02.075588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32307 11:20:02.106901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32309 11:20:02.107347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32310 11:20:02.138760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32311 11:20:02.139180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32313 11:20:02.171144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32315 11:20:02.171513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32316 11:20:02.202582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32317 11:20:02.202954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32319 11:20:02.233118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32320 11:20:02.233485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32322 11:20:02.265207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32323 11:20:02.265563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32325 11:20:02.296965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32326 11:20:02.297327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32328 11:20:02.331517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32330 11:20:02.332078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32331 11:20:02.364815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32333 11:20:02.365121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32334 11:20:02.396824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32335 11:20:02.397194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32337 11:20:02.432325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32339 11:20:02.432848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32340 11:20:02.464963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32341 11:20:02.465430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32343 11:20:02.498300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32345 11:20:02.498851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32346 11:20:02.530052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32348 11:20:02.530506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32349 11:20:02.580181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32351 11:20:02.580633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32352 11:20:02.615395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32354 11:20:02.615855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32355 11:20:02.648763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32356 11:20:02.649196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32358 11:20:02.682115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32360 11:20:02.682600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32361 11:20:02.715276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32362 11:20:02.715717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32364 11:20:02.748208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32365 11:20:02.748632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32367 11:20:02.780881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32368 11:20:02.781291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32370 11:20:02.813545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32371 11:20:02.813968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32373 11:20:02.846204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32375 11:20:02.846643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32376 11:20:02.884221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32377 11:20:02.884645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32379 11:20:02.920306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32380 11:20:02.920753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32382 11:20:02.956384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32384 11:20:02.956850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32385 11:20:03.001887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32386 11:20:03.002311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32388 11:20:03.034148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32390 11:20:03.034589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32391 11:20:03.065848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32392 11:20:03.066262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32394 11:20:03.100923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32395 11:20:03.101356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32397 11:20:03.132989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32399 11:20:03.133439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32400 11:20:03.164791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32401 11:20:03.165197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32403 11:20:03.196607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32405 11:20:03.197057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32406 11:20:03.228573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32407 11:20:03.228981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32409 11:20:03.259983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32410 11:20:03.260387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32412 11:20:03.292630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32413 11:20:03.293042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32415 11:20:03.324669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32416 11:20:03.325079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32418 11:20:03.356376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32419 11:20:03.356780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32421 11:20:03.388380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32422 11:20:03.388851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32424 11:20:03.420215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32425 11:20:03.420575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32427 11:20:03.452213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32429 11:20:03.452712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32430 11:20:03.486593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32431 11:20:03.486944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32433 11:20:03.523784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32434 11:20:03.524143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32436 11:20:03.558741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32437 11:20:03.559095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32439 11:20:03.599883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32440 11:20:03.600231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32442 11:20:03.635983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32443 11:20:03.636343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32445 11:20:03.672444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32446 11:20:03.672809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32448 11:20:03.708279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32449 11:20:03.708567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32451 11:20:03.743607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32452 11:20:03.743975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32454 11:20:03.781148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32456 11:20:03.781642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32457 11:20:03.812131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32458 11:20:03.812494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32460 11:20:03.843888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32461 11:20:03.844255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32463 11:20:03.875198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32464 11:20:03.875559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32466 11:20:03.907411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32467 11:20:03.907824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32469 11:20:03.940057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32471 11:20:03.940600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32472 11:20:03.972135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32473 11:20:03.972515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32475 11:20:04.004740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32476 11:20:04.005105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32478 11:20:04.037229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32480 11:20:04.037705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32481 11:20:04.069034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32483 11:20:04.069341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32484 11:20:04.101081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32485 11:20:04.101369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32487 11:20:04.132030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32488 11:20:04.132316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32490 11:20:04.163094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32491 11:20:04.163448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32493 11:20:04.194142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32495 11:20:04.194649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32496 11:20:04.226885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32497 11:20:04.227353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32499 11:20:04.260315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32500 11:20:04.260796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32502 11:20:04.292679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32503 11:20:04.293094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32505 11:20:04.325154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32506 11:20:04.325526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32508 11:20:04.357271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32509 11:20:04.357634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32511 11:20:04.388908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32512 11:20:04.389272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32514 11:20:04.421293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32515 11:20:04.421663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32517 11:20:04.455010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32518 11:20:04.455364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32520 11:20:04.487507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32521 11:20:04.487856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32523 11:20:04.520316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32524 11:20:04.520676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32526 11:20:04.552250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32527 11:20:04.552550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32529 11:20:04.587474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32530 11:20:04.587775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32532 11:20:04.622082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32534 11:20:04.622567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32535 11:20:04.659060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32536 11:20:04.659420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32538 11:20:04.696338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32539 11:20:04.696694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32541 11:20:04.731863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32543 11:20:04.732387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32544 11:20:04.764481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32545 11:20:04.764894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32547 11:20:04.796415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32548 11:20:04.796735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32550 11:20:04.827999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32551 11:20:04.828385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32553 11:20:04.861072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32554 11:20:04.861509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32556 11:20:04.893181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32557 11:20:04.893546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32559 11:20:04.925206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32560 11:20:04.925605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32562 11:20:04.956478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32563 11:20:04.956811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32565 11:20:04.988616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32566 11:20:04.989021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32568 11:20:05.019901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32569 11:20:05.020274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32571 11:20:05.050992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32573 11:20:05.051516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32574 11:20:05.083090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32575 11:20:05.083514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32577 11:20:05.115927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32578 11:20:05.116342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32580 11:20:05.149168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32581 11:20:05.149580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32583 11:20:05.187922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32584 11:20:05.188339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32586 11:20:05.223995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32587 11:20:05.224415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32589 11:20:05.258956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32590 11:20:05.259370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32592 11:20:05.291857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32593 11:20:05.292272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32595 11:20:05.324737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32596 11:20:05.325152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32598 11:20:05.356956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32599 11:20:05.357373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32601 11:20:05.389880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32602 11:20:05.390358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32604 11:20:05.422717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32605 11:20:05.423185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32607 11:20:05.457313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32608 11:20:05.457797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32610 11:20:05.494168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32612 11:20:05.494613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32613 11:20:05.528749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32614 11:20:05.529166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32616 11:20:05.564643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32617 11:20:05.565074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32619 11:20:05.598574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32620 11:20:05.599039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32622 11:20:05.631751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32623 11:20:05.632240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32625 11:20:05.665242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32626 11:20:05.665705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32628 11:20:05.698721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32629 11:20:05.699202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32631 11:20:05.732782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32632 11:20:05.733176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32634 11:20:05.767589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32635 11:20:05.768050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32637 11:20:05.802291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32639 11:20:05.802790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32640 11:20:05.836364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32641 11:20:05.836790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32643 11:20:05.869438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32645 11:20:05.869923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32646 11:20:05.902842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32647 11:20:05.903332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32649 11:20:05.934984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32650 11:20:05.935463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32652 11:20:05.992842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32654 11:20:05.993388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32655 11:20:06.028000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32657 11:20:06.028718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32658 11:20:06.060261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32659 11:20:06.060736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32661 11:20:06.093853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32662 11:20:06.094256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32664 11:20:06.131090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32666 11:20:06.131646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32667 11:20:06.162948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32668 11:20:06.163397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32670 11:20:06.195465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32671 11:20:06.195920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32673 11:20:06.228153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32674 11:20:06.228665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32676 11:20:06.261736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32677 11:20:06.262212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32679 11:20:06.294873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32680 11:20:06.295287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32682 11:20:06.327152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32683 11:20:06.327564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32685 11:20:06.359043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32686 11:20:06.359439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32688 11:20:06.391166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32689 11:20:06.391577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32691 11:20:06.423529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32692 11:20:06.423941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32694 11:20:06.456562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32695 11:20:06.457030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32697 11:20:06.490615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32698 11:20:06.491099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32700 11:20:06.522964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32701 11:20:06.523352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32703 11:20:06.554951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32704 11:20:06.555402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32706 11:20:06.595449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32707 11:20:06.595905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32709 11:20:06.637265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32710 11:20:06.637742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32712 11:20:06.671707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32713 11:20:06.672158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32715 11:20:06.704794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32717 11:20:06.705249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32718 11:20:06.738943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32719 11:20:06.739354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32721 11:20:06.773456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32722 11:20:06.773924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32724 11:20:06.806949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32725 11:20:06.807500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32727 11:20:06.840398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32728 11:20:06.840821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32730 11:20:06.884798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32731 11:20:06.885238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32733 11:20:06.919845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32734 11:20:06.920224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32736 11:20:06.953469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32737 11:20:06.953934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32739 11:20:06.987632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32740 11:20:06.988030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32742 11:20:07.021463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32743 11:20:07.021888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32745 11:20:07.055243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32746 11:20:07.055730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32748 11:20:07.089694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32749 11:20:07.090059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32751 11:20:07.124791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32752 11:20:07.125166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32754 11:20:07.157038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32755 11:20:07.157426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32757 11:20:07.189160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32758 11:20:07.189583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32760 11:20:07.221133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32761 11:20:07.221532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32763 11:20:07.253060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32764 11:20:07.253552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32766 11:20:07.285859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32767 11:20:07.286317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32769 11:20:07.319130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32770 11:20:07.319590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32772 11:20:07.352087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32773 11:20:07.352538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32775 11:20:07.385255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32776 11:20:07.385690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32778 11:20:07.417996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32779 11:20:07.418493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32781 11:20:07.450555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32782 11:20:07.450958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32784 11:20:07.483536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32785 11:20:07.483950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32787 11:20:07.517213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32788 11:20:07.517662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32790 11:20:07.549827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32791 11:20:07.550211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32793 11:20:07.583252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32794 11:20:07.583723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32796 11:20:07.615471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32797 11:20:07.615924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32799 11:20:07.647916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32800 11:20:07.648329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32802 11:20:07.680415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32803 11:20:07.680955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32805 11:20:07.714714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32806 11:20:07.715195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32808 11:20:07.753561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32809 11:20:07.753950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32811 11:20:07.794822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32812 11:20:07.795175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32814 11:20:07.828119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32815 11:20:07.828429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32817 11:20:07.862894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32818 11:20:07.863232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32820 11:20:07.905299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32821 11:20:07.905694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32823 11:20:07.938819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32824 11:20:07.939263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32826 11:20:07.972038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32828 11:20:07.972575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32829 11:20:08.007260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32830 11:20:08.007676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32832 11:20:08.041253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32834 11:20:08.041683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32835 11:20:08.074510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32836 11:20:08.074918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32838 11:20:08.107720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32839 11:20:08.108149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32841 11:20:08.139962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32842 11:20:08.140370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32844 11:20:08.172919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32845 11:20:08.173334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32847 11:20:08.207894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32849 11:20:08.208349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32850 11:20:08.241881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32851 11:20:08.242301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32853 11:20:08.275861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32854 11:20:08.276334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32856 11:20:08.308729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32857 11:20:08.309039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32859 11:20:08.342112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32861 11:20:08.342416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32862 11:20:08.375040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32863 11:20:08.375326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32865 11:20:08.407949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32866 11:20:08.408306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32868 11:20:08.440922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32869 11:20:08.441298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32871 11:20:08.473473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32873 11:20:08.473974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32874 11:20:08.506417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32875 11:20:08.506780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32877 11:20:08.539226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32879 11:20:08.539668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32880 11:20:08.571543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32882 11:20:08.571844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32883 11:20:08.604024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32884 11:20:08.604382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32886 11:20:08.636629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32887 11:20:08.636999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32889 11:20:08.669305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32891 11:20:08.669608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32892 11:20:08.703444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32893 11:20:08.703731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32895 11:20:08.736017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32896 11:20:08.736302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32898 11:20:08.768134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32900 11:20:08.768643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32901 11:20:08.801876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32902 11:20:08.802245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32904 11:20:08.835078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32905 11:20:08.835447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32907 11:20:08.868249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32908 11:20:08.868616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32910 11:20:08.900874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32912 11:20:08.901467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32913 11:20:08.932912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32915 11:20:08.933409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32916 11:20:08.965009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32918 11:20:08.965503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32919 11:20:08.997375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32920 11:20:08.997738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32922 11:20:09.030231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32924 11:20:09.030671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32925 11:20:09.061704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32927 11:20:09.062161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32928 11:20:09.094903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32929 11:20:09.095254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32931 11:20:09.127452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32932 11:20:09.127763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32934 11:20:09.159919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32935 11:20:09.160285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32937 11:20:09.192418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32938 11:20:09.192795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32940 11:20:09.225230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32941 11:20:09.225519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32943 11:20:09.257411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32945 11:20:09.257718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32946 11:20:09.290643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32947 11:20:09.291014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32949 11:20:09.323627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32950 11:20:09.324037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32952 11:20:09.355110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32953 11:20:09.355505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32955 11:20:09.387547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32957 11:20:09.387982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32958 11:20:09.420157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32960 11:20:09.420621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32961 11:20:09.451841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32963 11:20:09.452354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32964 11:20:09.483453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32966 11:20:09.483959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32967 11:20:09.514606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32968 11:20:09.514893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32970 11:20:09.545185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32971 11:20:09.545470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32973 11:20:09.575461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32974 11:20:09.575838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32976 11:20:09.607150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32977 11:20:09.607689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32979 11:20:09.638018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
32981 11:20:09.638379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
32982 11:20:09.668955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
32984 11:20:09.669323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
32985 11:20:09.701329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
32986 11:20:09.701595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
32988 11:20:09.735088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
32989 11:20:09.735377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
32991 11:20:09.771948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
32993 11:20:09.772386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
32994 11:20:09.807619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
32995 11:20:09.807968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
32997 11:20:09.839504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
32998 11:20:09.839849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
33000 11:20:09.871136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
33001 11:20:09.871485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
33003 11:20:09.901795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
33005 11:20:09.902228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
33006 11:20:09.932150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
33008 11:20:09.932601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
33009 11:20:09.962694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
33010 11:20:09.963042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
33012 11:20:09.992939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
33013 11:20:09.993294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
33015 11:20:10.023528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
33016 11:20:10.023811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
33018 11:20:10.053628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
33019 11:20:10.053917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
33021 11:20:10.084157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
33022 11:20:10.084510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
33024 11:20:10.115326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
33025 11:20:10.115678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
33027 11:20:10.146772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
33029 11:20:10.147204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
33030 11:20:10.176965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
33032 11:20:10.177412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
33033 11:20:10.207261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
33035 11:20:10.207687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
33036 11:20:10.238617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
33038 11:20:10.239046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
33039 11:20:10.269094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
33041 11:20:10.269531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
33042 11:20:10.299438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
33043 11:20:10.299731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
33045 11:20:10.330659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
33047 11:20:10.330959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
33048 11:20:10.361212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
33049 11:20:10.361496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
33051 11:20:10.391531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
33052 11:20:10.391885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
33054 11:20:10.421654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
33055 11:20:10.422014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
33057 11:20:10.452297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
33058 11:20:10.452647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
33060 11:20:10.483398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
33061 11:20:10.483682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
33063 11:20:10.514110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
33065 11:20:10.514546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
33066 11:20:10.544541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
33067 11:20:10.544908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
33069 11:20:10.575242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
33070 11:20:10.575592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
33072 11:20:10.605829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
33074 11:20:10.606291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
33075 11:20:10.636222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
33077 11:20:10.636650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
33078 11:20:10.666950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
33079 11:20:10.667301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
33081 11:20:10.697283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
33082 11:20:10.697631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
33084 11:20:10.727580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
33086 11:20:10.728015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
33087 11:20:10.758578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
33088 11:20:10.758924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
33090 11:20:10.790479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
33091 11:20:10.790828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
33093 11:20:10.822729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
33094 11:20:10.823102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
33096 11:20:10.853967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
33097 11:20:10.854319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
33099 11:20:10.884520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
33100 11:20:10.884871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
33102 11:20:10.916112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33103 11:20:10.916471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33105 11:20:10.947222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33106 11:20:10.947513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
33108 11:20:10.980395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33109 11:20:10.980682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33111 11:20:11.011510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33112 11:20:11.011863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33114 11:20:11.042308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33115 11:20:11.042660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
33117 11:20:11.073197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33118 11:20:11.073568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33120 11:20:11.125493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33121 11:20:11.125804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33123 11:20:11.156373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33124 11:20:11.156738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
33126 11:20:11.187119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33127 11:20:11.187407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33129 11:20:11.217760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33131 11:20:11.218199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33132 11:20:11.250784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
33134 11:20:11.251173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33135 11:20:11.283136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33136 11:20:11.283497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33138 11:20:11.313734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33139 11:20:11.314105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33141 11:20:11.344969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33142 11:20:11.345319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
33144 11:20:11.375876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33145 11:20:11.376224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33147 11:20:11.406732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
33149 11:20:11.407181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
33150 11:20:11.437118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33151 11:20:11.437405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33153 11:20:11.468849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33154 11:20:11.469293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
33156 11:20:11.500369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33158 11:20:11.500855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33159 11:20:11.531436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33161 11:20:11.531869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33162 11:20:11.566627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
33164 11:20:11.567056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33165 11:20:11.597434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33166 11:20:11.597802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33168 11:20:11.627929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33169 11:20:11.628343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33171 11:20:11.660004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33172 11:20:11.660386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
33174 11:20:11.690803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33175 11:20:11.691166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33177 11:20:11.721175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33178 11:20:11.721540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33180 11:20:11.751784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33181 11:20:11.752161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
33183 11:20:11.783104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33184 11:20:11.783391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33186 11:20:11.814371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33187 11:20:11.814731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33189 11:20:11.845370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33190 11:20:11.845693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
33192 11:20:11.875916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33194 11:20:11.876216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33195 11:20:11.906773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
33197 11:20:11.907212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
33198 11:20:11.937258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33199 11:20:11.937669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33201 11:20:11.967663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33202 11:20:11.968024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
33204 11:20:11.998497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33206 11:20:11.998953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33207 11:20:12.031027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33208 11:20:12.031462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33210 11:20:12.063221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
33212 11:20:12.063642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33213 11:20:12.093710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33214 11:20:12.094074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33216 11:20:12.125210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33217 11:20:12.125557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33219 11:20:12.155824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33220 11:20:12.156178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
33222 11:20:12.186848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33223 11:20:12.187194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33225 11:20:12.217349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33226 11:20:12.217689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33228 11:20:12.248076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33229 11:20:12.248427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33231 11:20:12.280474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33232 11:20:12.280916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33234 11:20:12.311344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33235 11:20:12.311629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33237 11:20:12.344166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33238 11:20:12.344537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33240 11:20:12.375498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33241 11:20:12.375853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33243 11:20:12.406694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33244 11:20:12.407061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33246 11:20:12.437608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33247 11:20:12.437899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33249 11:20:12.468159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33250 11:20:12.468442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33252 11:20:12.499557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33253 11:20:12.499910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33255 11:20:12.530811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33256 11:20:12.531163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33258 11:20:12.561305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33259 11:20:12.561677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33261 11:20:12.591628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33262 11:20:12.591973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33264 11:20:12.622665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33265 11:20:12.623030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33267 11:20:12.653422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33269 11:20:12.653931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33270 11:20:12.684557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33271 11:20:12.684924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33273 11:20:12.718226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33275 11:20:12.718689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33276 11:20:12.749418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33277 11:20:12.749828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33279 11:20:12.780282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33281 11:20:12.780830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33282 11:20:12.811176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33283 11:20:12.811463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33285 11:20:12.842792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33286 11:20:12.843086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33288 11:20:12.874919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33289 11:20:12.875340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33291 11:20:12.905039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33292 11:20:12.905326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33294 11:20:12.935838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33296 11:20:12.936316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33297 11:20:12.966691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33298 11:20:12.966976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33300 11:20:12.997421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33301 11:20:12.997794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33303 11:20:13.027980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33304 11:20:13.028329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33306 11:20:13.058376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33307 11:20:13.058742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33309 11:20:13.089094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33310 11:20:13.089469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33312 11:20:13.120175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33313 11:20:13.120550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33315 11:20:13.151022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33317 11:20:13.151461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33318 11:20:13.181716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33319 11:20:13.182094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33321 11:20:13.212117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33322 11:20:13.212464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33324 11:20:13.242817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33325 11:20:13.243174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33327 11:20:13.273564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33329 11:20:13.274002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33330 11:20:13.304637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33332 11:20:13.305117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33333 11:20:13.336341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33334 11:20:13.336679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33336 11:20:13.368496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33337 11:20:13.368860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33339 11:20:13.399753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33340 11:20:13.400048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33342 11:20:13.430689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33344 11:20:13.430990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33345 11:20:13.461429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33346 11:20:13.461798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33348 11:20:13.492710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33349 11:20:13.493074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33351 11:20:13.523512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33352 11:20:13.523878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33354 11:20:13.554699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33356 11:20:13.555252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33357 11:20:13.585897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33358 11:20:13.586355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33360 11:20:13.617070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33361 11:20:13.617529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33363 11:20:13.648691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33364 11:20:13.649071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33366 11:20:13.679509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33367 11:20:13.679884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33369 11:20:13.711863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33371 11:20:13.712415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33372 11:20:13.743141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33373 11:20:13.743602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33375 11:20:13.774505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33376 11:20:13.774963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33378 11:20:13.805485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33379 11:20:13.805952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33381 11:20:13.837269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33382 11:20:13.837673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33384 11:20:13.868669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33385 11:20:13.869127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33387 11:20:13.899601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33388 11:20:13.899999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33390 11:20:13.931108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33391 11:20:13.931500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33393 11:20:13.962676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33395 11:20:13.963221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33396 11:20:13.993522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33397 11:20:13.993971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33399 11:20:14.024963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33400 11:20:14.025399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33402 11:20:14.055791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33404 11:20:14.056324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33405 11:20:14.086955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33406 11:20:14.087393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33408 11:20:14.119173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33410 11:20:14.119781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33411 11:20:14.150933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33413 11:20:14.151461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33414 11:20:14.181721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33415 11:20:14.182157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33417 11:20:14.212825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33418 11:20:14.213254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33420 11:20:14.244009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33421 11:20:14.244442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33423 11:20:14.275259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33424 11:20:14.275699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33426 11:20:14.306532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33427 11:20:14.306960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33429 11:20:14.338268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33431 11:20:14.338803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33432 11:20:14.369409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33433 11:20:14.369850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33435 11:20:14.400272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33436 11:20:14.400680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33438 11:20:14.433289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33439 11:20:14.433681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33441 11:20:14.465715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33442 11:20:14.466159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33444 11:20:14.506033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33446 11:20:14.506612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33447 11:20:14.539946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33448 11:20:14.540407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33450 11:20:14.573474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33451 11:20:14.573991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33453 11:20:14.606302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33455 11:20:14.606994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33456 11:20:14.642642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33458 11:20:14.643096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33459 11:20:14.675880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33460 11:20:14.676347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33462 11:20:14.717703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33463 11:20:14.718157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33465 11:20:14.766099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33467 11:20:14.766418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33468 11:20:14.803330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33470 11:20:14.803886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33471 11:20:14.836212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33472 11:20:14.836618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33474 11:20:14.870996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33475 11:20:14.871479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33477 11:20:14.913439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33478 11:20:14.913927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33480 11:20:14.945426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33481 11:20:14.945671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33483 11:20:14.977678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33485 11:20:14.977996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33486 11:20:15.011455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33488 11:20:15.012013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33489 11:20:15.045399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33491 11:20:15.045981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33492 11:20:15.081054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33494 11:20:15.081837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33495 11:20:15.114108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33497 11:20:15.114733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33498 11:20:15.147111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33499 11:20:15.147466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33501 11:20:15.180638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33502 11:20:15.180989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33504 11:20:15.214965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33506 11:20:15.215417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33507 11:20:15.247884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33508 11:20:15.248248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33510 11:20:15.280449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33512 11:20:15.280884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33513 11:20:15.324219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33514 11:20:15.324616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33516 11:20:15.357086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33517 11:20:15.357466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33519 11:20:15.389280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33520 11:20:15.389805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33522 11:20:15.422173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33524 11:20:15.422662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33525 11:20:15.455367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33526 11:20:15.455734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33528 11:20:15.490005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33530 11:20:15.490471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33531 11:20:15.530732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33532 11:20:15.531097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33534 11:20:15.563971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33536 11:20:15.564639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33537 11:20:15.595424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33538 11:20:15.595868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33540 11:20:15.635961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33542 11:20:15.636472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33543 11:20:15.668490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33544 11:20:15.668959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33546 11:20:15.699825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33547 11:20:15.700194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33549 11:20:15.732313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33550 11:20:15.732682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33552 11:20:15.764979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33553 11:20:15.765332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33555 11:20:15.797457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33557 11:20:15.797917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33558 11:20:15.830160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33560 11:20:15.830755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33561 11:20:15.863152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33562 11:20:15.863528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33564 11:20:15.895788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33566 11:20:15.896490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33567 11:20:15.927190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33568 11:20:15.927630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33570 11:20:15.970313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33572 11:20:15.970755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33573 11:20:16.004155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33575 11:20:16.004606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33576 11:20:16.041136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33578 11:20:16.041570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33579 11:20:16.083944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33580 11:20:16.084354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33582 11:20:16.117730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33584 11:20:16.118455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33585 11:20:16.150820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33586 11:20:16.151297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33588 11:20:16.192181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33589 11:20:16.192642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33591 11:20:16.253540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33592 11:20:16.254022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33594 11:20:16.292749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33595 11:20:16.293232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33597 11:20:16.324778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33599 11:20:16.325356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33600 11:20:16.357360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33601 11:20:16.357819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33603 11:20:16.392189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33604 11:20:16.392605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33606 11:20:16.424879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33608 11:20:16.425324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33609 11:20:16.458323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33611 11:20:16.458768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33612 11:20:16.491359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33613 11:20:16.491782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33615 11:20:16.524847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33616 11:20:16.525320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33618 11:20:16.557739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33619 11:20:16.558270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33621 11:20:16.591787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33622 11:20:16.592238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33624 11:20:16.624518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33626 11:20:16.625050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33627 11:20:16.656827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33628 11:20:16.657286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33630 11:20:16.687979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33632 11:20:16.688565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33633 11:20:16.719269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33635 11:20:16.719576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33636 11:20:16.752734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33637 11:20:16.753124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33639 11:20:16.785628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33641 11:20:16.786205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33642 11:20:16.819456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33643 11:20:16.819812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33645 11:20:16.853298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33646 11:20:16.853672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33648 11:20:16.885062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33649 11:20:16.885418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33651 11:20:16.916048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33652 11:20:16.916491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33654 11:20:16.947191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33655 11:20:16.947587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33657 11:20:16.980051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33659 11:20:16.980610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33660 11:20:17.013639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33661 11:20:17.014012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33663 11:20:17.045203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33664 11:20:17.045489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33666 11:20:17.076473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33667 11:20:17.076759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33669 11:20:17.108154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33670 11:20:17.108434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33672 11:20:17.140678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33673 11:20:17.141026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33675 11:20:17.184845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33677 11:20:17.185143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33678 11:20:17.219401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33679 11:20:17.219816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33681 11:20:17.251794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33682 11:20:17.252268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33684 11:20:17.284767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33686 11:20:17.285332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33687 11:20:17.316179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33688 11:20:17.316614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33690 11:20:17.348105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33691 11:20:17.348557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33693 11:20:17.381269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33695 11:20:17.381999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33696 11:20:17.422769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33697 11:20:17.423230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33699 11:20:17.457443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33700 11:20:17.457865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33702 11:20:17.491690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33704 11:20:17.492327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33705 11:20:17.523359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33706 11:20:17.523763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33708 11:20:17.559131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33709 11:20:17.559544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33711 11:20:17.592046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33712 11:20:17.592480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33714 11:20:17.624136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33715 11:20:17.624537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33717 11:20:17.657092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33719 11:20:17.657554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33720 11:20:17.688148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33721 11:20:17.688532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33723 11:20:17.720041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33724 11:20:17.720474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33726 11:20:17.751329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33727 11:20:17.751704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33729 11:20:17.782951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33731 11:20:17.783570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33732 11:20:17.815135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33733 11:20:17.815545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33735 11:20:17.846859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33736 11:20:17.847266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33738 11:20:17.878382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33739 11:20:17.878775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33741 11:20:17.909822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33742 11:20:17.910182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33744 11:20:17.940823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33745 11:20:17.941297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33747 11:20:17.972084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33749 11:20:17.972618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33750 11:20:18.003271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33751 11:20:18.003672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33753 11:20:18.035169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33754 11:20:18.035642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33756 11:20:18.066755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33758 11:20:18.067386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33759 11:20:18.097717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33760 11:20:18.098156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33762 11:20:18.129718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33764 11:20:18.130259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33765 11:20:18.161953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33766 11:20:18.162387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33768 11:20:18.193361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33769 11:20:18.193788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33771 11:20:18.224378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33772 11:20:18.224858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33774 11:20:18.255511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33775 11:20:18.255889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33777 11:20:18.286582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33778 11:20:18.286943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33780 11:20:18.317665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33781 11:20:18.318086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33783 11:20:18.349143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33784 11:20:18.349547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33786 11:20:18.381207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33787 11:20:18.381677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33789 11:20:18.412403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33790 11:20:18.412844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33792 11:20:18.444388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33793 11:20:18.444832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33795 11:20:18.476354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33796 11:20:18.476797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33798 11:20:18.509126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33799 11:20:18.509615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33801 11:20:18.542791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33802 11:20:18.543276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33804 11:20:18.574069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33806 11:20:18.574706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33807 11:20:18.605216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33808 11:20:18.605688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33810 11:20:18.637085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33811 11:20:18.637552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33813 11:20:18.671892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33814 11:20:18.672302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33816 11:20:18.704116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33817 11:20:18.704596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33819 11:20:18.736105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33821 11:20:18.736560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33822 11:20:18.769261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33823 11:20:18.769682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33825 11:20:18.801193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33826 11:20:18.801628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33828 11:20:18.834764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33830 11:20:18.835332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33831 11:20:18.866610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33832 11:20:18.867098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33834 11:20:18.897830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33835 11:20:18.898283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33837 11:20:18.929274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33838 11:20:18.929743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33840 11:20:18.960440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33841 11:20:18.960845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33843 11:20:18.992064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33844 11:20:18.992524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33846 11:20:19.023356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33848 11:20:19.023884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33849 11:20:19.053894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33851 11:20:19.054413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33852 11:20:19.084741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33853 11:20:19.085202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33855 11:20:19.118860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33856 11:20:19.119354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33858 11:20:19.150732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33859 11:20:19.151197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33861 11:20:19.185235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33862 11:20:19.185725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33864 11:20:19.221462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33865 11:20:19.221855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33867 11:20:19.259067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33869 11:20:19.259464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33870 11:20:19.291072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33871 11:20:19.291442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33873 11:20:19.323033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33874 11:20:19.323403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33876 11:20:19.354266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33878 11:20:19.354705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33879 11:20:19.386098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33881 11:20:19.386469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33882 11:20:19.422701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33884 11:20:19.423194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33885 11:20:19.457252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33886 11:20:19.457724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33888 11:20:19.491351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33889 11:20:19.491763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33891 11:20:19.525955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33892 11:20:19.526426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33894 11:20:19.557087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33895 11:20:19.557469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33897 11:20:19.588237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33898 11:20:19.588682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33900 11:20:19.621937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33901 11:20:19.622437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33903 11:20:19.656303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33905 11:20:19.656908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33906 11:20:19.702196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33908 11:20:19.702799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33909 11:20:19.748254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33910 11:20:19.748762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33912 11:20:19.785181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33913 11:20:19.785678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33915 11:20:19.828536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33916 11:20:19.829023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33918 11:20:19.865099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33919 11:20:19.865541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33921 11:20:19.899385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33922 11:20:19.899806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33924 11:20:19.933209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33926 11:20:19.933584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33927 11:20:19.964011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33928 11:20:19.964453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33930 11:20:19.996474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33932 11:20:19.997129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33933 11:20:20.030407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33934 11:20:20.030876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33936 11:20:20.064083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33937 11:20:20.064549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33939 11:20:20.097581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33941 11:20:20.098161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33942 11:20:20.131413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33944 11:20:20.132164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33945 11:20:20.163811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33946 11:20:20.164296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33948 11:20:20.197137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33950 11:20:20.197885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33951 11:20:20.230175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33953 11:20:20.230838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33954 11:20:20.263144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33955 11:20:20.263582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33957 11:20:20.297729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33959 11:20:20.298387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33960 11:20:20.331163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33962 11:20:20.331540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33963 11:20:20.365185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33965 11:20:20.365807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33966 11:20:20.398306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33967 11:20:20.398689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33969 11:20:20.430142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33971 11:20:20.430872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33972 11:20:20.471547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33974 11:20:20.472238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33975 11:20:20.504007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33977 11:20:20.504697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33978 11:20:20.535963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33979 11:20:20.536425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33981 11:20:20.567822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33982 11:20:20.568465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
33984 11:20:20.600395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33985 11:20:20.600818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33987 11:20:20.636328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33989 11:20:20.636982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33990 11:20:20.672040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33991 11:20:20.672525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
33993 11:20:20.703737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33994 11:20:20.704193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33996 11:20:20.738270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33998 11:20:20.738713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33999 11:20:20.770898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
34000 11:20:20.771379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
34002 11:20:20.803260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
34003 11:20:20.803735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
34005 11:20:20.837418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
34006 11:20:20.837836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
34008 11:20:20.879412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
34010 11:20:20.879996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
34011 11:20:20.912246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
34012 11:20:20.912713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
34014 11:20:20.944573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
34016 11:20:20.945149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
34017 11:20:20.977392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
34019 11:20:20.977971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
34020 11:20:21.023207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
34022 11:20:21.023755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
34023 11:20:21.056342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
34025 11:20:21.056977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
34026 11:20:21.089558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
34028 11:20:21.090176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
34029 11:20:21.122809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
34030 11:20:21.123180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
34032 11:20:21.155550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
34033 11:20:21.155896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
34035 11:20:21.193029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
34036 11:20:21.193469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
34038 11:20:21.226223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
34040 11:20:21.226730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
34041 11:20:21.259704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
34042 11:20:21.260124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
34044 11:20:21.292463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
34045 11:20:21.292874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
34047 11:20:21.364761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
34048 11:20:21.365157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
34050 11:20:21.396815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
34051 11:20:21.397093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
34053 11:20:21.429932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
34055 11:20:21.430494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
34056 11:20:21.461680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
34057 11:20:21.462127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
34059 11:20:21.495341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
34060 11:20:21.495798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
34062 11:20:21.527623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
34063 11:20:21.528098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
34065 11:20:21.559748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
34066 11:20:21.560199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
34068 11:20:21.591943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
34069 11:20:21.592409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
34071 11:20:21.625096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
34072 11:20:21.625659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
34074 11:20:21.656503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
34076 11:20:21.657100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
34077 11:20:21.688485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
34078 11:20:21.688874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
34080 11:20:21.720777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
34082 11:20:21.721122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
34083 11:20:21.752220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
34084 11:20:21.752561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
34086 11:20:21.785718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
34088 11:20:21.786245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
34089 11:20:21.827761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
34091 11:20:21.828292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
34092 11:20:21.859326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
34094 11:20:21.859738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
34095 11:20:21.892059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
34096 11:20:21.892540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
34098 11:20:21.925137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
34099 11:20:21.925501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
34101 11:20:21.959199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
34102 11:20:21.959568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
34104 11:20:21.991855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
34106 11:20:21.992296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
34107 11:20:22.025526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
34109 11:20:22.025998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
34110 11:20:22.058946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
34111 11:20:22.059378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
34113 11:20:22.092312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
34114 11:20:22.092731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
34116 11:20:22.125133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
34117 11:20:22.125539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
34119 11:20:22.157102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
34120 11:20:22.157577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
34122 11:20:22.188825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
34124 11:20:22.189263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
34125 11:20:22.221354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
34126 11:20:22.221762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
34128 11:20:22.253204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
34130 11:20:22.253812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
34131 11:20:22.285361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
34132 11:20:22.285686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
34134 11:20:22.318328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
34136 11:20:22.318786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
34137 11:20:22.350412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
34138 11:20:22.350884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
34140 11:20:22.382616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
34141 11:20:22.383095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
34143 11:20:22.415899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
34144 11:20:22.416308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
34146 11:20:22.448495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
34148 11:20:22.448940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
34149 11:20:22.480867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
34150 11:20:22.481386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
34152 11:20:22.513903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
34154 11:20:22.514453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
34155 11:20:22.546840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
34156 11:20:22.547195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
34158 11:20:22.579167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
34159 11:20:22.579566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
34161 11:20:22.610662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
34162 11:20:22.611011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
34164 11:20:22.641885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
34166 11:20:22.642381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
34167 11:20:22.673851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
34168 11:20:22.674289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
34170 11:20:22.707237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
34172 11:20:22.707825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
34173 11:20:22.739339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
34174 11:20:22.739808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
34176 11:20:22.772622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
34178 11:20:22.773068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
34179 11:20:22.804690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
34180 11:20:22.805242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
34182 11:20:22.837569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
34183 11:20:22.838037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
34185 11:20:22.869327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
34187 11:20:22.869862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
34188 11:20:22.902179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
34190 11:20:22.902687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
34191 11:20:22.935268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
34193 11:20:22.935824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
34194 11:20:22.967734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
34195 11:20:22.968214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
34197 11:20:22.999904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
34198 11:20:23.000363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
34200 11:20:23.031800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
34202 11:20:23.032359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
34203 11:20:23.064187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
34205 11:20:23.064847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
34206 11:20:23.096073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
34207 11:20:23.096570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
34209 11:20:23.127608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
34210 11:20:23.128033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
34212 11:20:23.160341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
34214 11:20:23.160790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
34215 11:20:23.193034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
34216 11:20:23.193494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
34218 11:20:23.224045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
34219 11:20:23.224417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
34221 11:20:23.255284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
34222 11:20:23.255629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
34224 11:20:23.286780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34225 11:20:23.287126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34227 11:20:23.317357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34228 11:20:23.317686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34230 11:20:23.348279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34231 11:20:23.348628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34233 11:20:23.380093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34234 11:20:23.380438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34236 11:20:23.411209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34237 11:20:23.411552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34239 11:20:23.442686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34240 11:20:23.443028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34242 11:20:23.476418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34243 11:20:23.476830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34245 11:20:23.514250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34247 11:20:23.514827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34248 11:20:23.558941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34250 11:20:23.559371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34251 11:20:23.596363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34253 11:20:23.596777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34254 11:20:23.637969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34256 11:20:23.638443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34257 11:20:23.677432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34258 11:20:23.677784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34260 11:20:23.709037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34261 11:20:23.709384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34263 11:20:23.740879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34264 11:20:23.741223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34266 11:20:23.772292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34267 11:20:23.772640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34269 11:20:23.803586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34270 11:20:23.803937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34272 11:20:23.835547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34274 11:20:23.836043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34275 11:20:23.867213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34277 11:20:23.867734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34278 11:20:23.900559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34279 11:20:23.900899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34281 11:20:23.933692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34282 11:20:23.934037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34284 11:20:23.967491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34285 11:20:23.967831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34287 11:20:24.000999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34288 11:20:24.001342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34290 11:20:24.034556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34291 11:20:24.034952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34293 11:20:24.068072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34294 11:20:24.068763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34296 11:20:24.101586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34297 11:20:24.101955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34299 11:20:24.139378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34300 11:20:24.139664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34302 11:20:24.171517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34303 11:20:24.171801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34305 11:20:24.203309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34306 11:20:24.203670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34308 11:20:24.235956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34309 11:20:24.236314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34311 11:20:24.268926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34312 11:20:24.269369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34314 11:20:24.301726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34315 11:20:24.302104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34317 11:20:24.334907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34318 11:20:24.335393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34320 11:20:24.367793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34321 11:20:24.368275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34323 11:20:24.401240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34324 11:20:24.401611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34326 11:20:24.435299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34328 11:20:24.435757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34329 11:20:24.469070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34330 11:20:24.469547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34332 11:20:24.504551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34334 11:20:24.505211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34335 11:20:24.543920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34336 11:20:24.544322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34338 11:20:24.575957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34339 11:20:24.576369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34341 11:20:24.608778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34342 11:20:24.609168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34344 11:20:24.640221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34346 11:20:24.640822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34347 11:20:24.675733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34349 11:20:24.676298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34350 11:20:24.712250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34351 11:20:24.712699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34353 11:20:24.749384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34354 11:20:24.749798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34356 11:20:24.784855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34357 11:20:24.785381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34359 11:20:24.819409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34360 11:20:24.819807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34362 11:20:24.854652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34363 11:20:24.855031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34365 11:20:24.888479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34367 11:20:24.888909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34368 11:20:24.921314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34370 11:20:24.921755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34371 11:20:24.953361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34373 11:20:24.953748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34374 11:20:24.984781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34375 11:20:24.985087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34377 11:20:25.015780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34378 11:20:25.016256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34380 11:20:25.047610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34381 11:20:25.048065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34383 11:20:25.079611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34384 11:20:25.080074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34386 11:20:25.111944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34387 11:20:25.112359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34389 11:20:25.146314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34391 11:20:25.146954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34392 11:20:25.180199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34394 11:20:25.180963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34395 11:20:25.214878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34396 11:20:25.215291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34398 11:20:25.248975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34399 11:20:25.249439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34401 11:20:25.282425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34402 11:20:25.282779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34404 11:20:25.316129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34405 11:20:25.316519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34407 11:20:25.349302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34408 11:20:25.349762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34410 11:20:25.381489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34411 11:20:25.382038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34413 11:20:25.415173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34414 11:20:25.415715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34416 11:20:25.449473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34417 11:20:25.449947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34419 11:20:25.483023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34420 11:20:25.483483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34422 11:20:25.516136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34423 11:20:25.516490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34425 11:20:25.548720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34426 11:20:25.549098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34428 11:20:25.581036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34429 11:20:25.581457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34431 11:20:25.613386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34432 11:20:25.613858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34434 11:20:25.655143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34435 11:20:25.655606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34437 11:20:25.688603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34438 11:20:25.689145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34440 11:20:25.720890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34441 11:20:25.721313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34443 11:20:25.753955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34445 11:20:25.754422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34446 11:20:25.787443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34448 11:20:25.788083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34449 11:20:25.823334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34450 11:20:25.823852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34452 11:20:25.856932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34454 11:20:25.857489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34455 11:20:25.889786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34456 11:20:25.890250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34458 11:20:25.922883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34459 11:20:25.923286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34461 11:20:25.955160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34462 11:20:25.955453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34464 11:20:25.988704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34465 11:20:25.989119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34467 11:20:26.021364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34468 11:20:26.021804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34470 11:20:26.054927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34472 11:20:26.055384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34473 11:20:26.088440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34474 11:20:26.088860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34476 11:20:26.124089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34477 11:20:26.124505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34479 11:20:26.157476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34480 11:20:26.157915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34482 11:20:26.191943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34484 11:20:26.192393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34485 11:20:26.226959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34486 11:20:26.227395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34488 11:20:26.260500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34490 11:20:26.260964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34491 11:20:26.307359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34492 11:20:26.307814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34494 11:20:26.350111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34496 11:20:26.350378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34497 11:20:26.384545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34498 11:20:26.384842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34500 11:20:26.418507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34501 11:20:26.418961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34503 11:20:26.473418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34505 11:20:26.473977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34506 11:20:26.508601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34507 11:20:26.508983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34509 11:20:26.541989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34510 11:20:26.542365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34512 11:20:26.578803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34513 11:20:26.579163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34515 11:20:26.613605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34517 11:20:26.613910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34518 11:20:26.647523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34519 11:20:26.647810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34521 11:20:26.681975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34522 11:20:26.682421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34524 11:20:26.732126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34525 11:20:26.732526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34527 11:20:26.780598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34528 11:20:26.781041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34530 11:20:26.815298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34532 11:20:26.815749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34533 11:20:26.852351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34534 11:20:26.852812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34536 11:20:26.886841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34537 11:20:26.887191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34539 11:20:26.919721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34540 11:20:26.920110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34542 11:20:26.953006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34543 11:20:26.953429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34545 11:20:26.986754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34547 11:20:26.987219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34548 11:20:27.019926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34549 11:20:27.020369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34551 11:20:27.053266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34553 11:20:27.053851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34554 11:20:27.086553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34556 11:20:27.087117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34557 11:20:27.119560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34558 11:20:27.120030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34560 11:20:27.153956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34562 11:20:27.154598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34563 11:20:27.187170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34564 11:20:27.187574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34566 11:20:27.220996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34567 11:20:27.221354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34569 11:20:27.255084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34571 11:20:27.255534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34572 11:20:27.287826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34573 11:20:27.288325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34575 11:20:27.321683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34576 11:20:27.322171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34578 11:20:27.355589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34579 11:20:27.356074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34581 11:20:27.391741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34582 11:20:27.392211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34584 11:20:27.425366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34585 11:20:27.425804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34587 11:20:27.459399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34588 11:20:27.459831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34590 11:20:27.491568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34591 11:20:27.492005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34593 11:20:27.523673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34594 11:20:27.524080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34596 11:20:27.556302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34597 11:20:27.556729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34599 11:20:27.588259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34601 11:20:27.588856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34602 11:20:27.621299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34603 11:20:27.621762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34605 11:20:27.654824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34607 11:20:27.655388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34608 11:20:27.686956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34609 11:20:27.687429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34611 11:20:27.719147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34612 11:20:27.719617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34614 11:20:27.750948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34615 11:20:27.751464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34617 11:20:27.782895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34619 11:20:27.783547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34620 11:20:27.814944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34621 11:20:27.815392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34623 11:20:27.848506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34625 11:20:27.848961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34626 11:20:27.881597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34627 11:20:27.882075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34629 11:20:27.915103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34630 11:20:27.915600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34632 11:20:27.947191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34633 11:20:27.947690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34635 11:20:27.979134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34636 11:20:27.979619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34638 11:20:28.011079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34639 11:20:28.011507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34641 11:20:28.043430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34643 11:20:28.043879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34644 11:20:28.076293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34645 11:20:28.076780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34647 11:20:28.109137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34648 11:20:28.109615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34650 11:20:28.141975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34652 11:20:28.142630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34653 11:20:28.184100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34655 11:20:28.184664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34656 11:20:28.216772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34657 11:20:28.217171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34659 11:20:28.219832 + set +x
34660 11:20:28.220144 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 562648_1.1.3.5>
34661 11:20:28.220401 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 562648_1.1.3.5
34662 11:20:28.220479 Ending use of test pattern.
34663 11:20:28.220544 Ending test lava.1_kselftest-arm64_qemu (562648_1.1.3.5), duration 316.50
34665 11:20:28.223530 ok: lava_test_shell seems to have completed
34666 11:20:28.295763 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34667 11:20:28.304534 end: 3.1 lava-test-shell (duration 00:05:18) [common]
34668 11:20:28.304695 end: 3 lava-test-retry (duration 00:05:18) [common]
34669 11:20:28.304820 start: 4 finalize (timeout 00:03:33) [common]
34670 11:20:28.304943 start: 4.1 power-off (timeout 00:00:30) [common]
34671 11:20:28.305060 end: 4.1 power-off (duration 00:00:00) [common]
34672 11:20:28.305174 start: 4.2 read-feedback (timeout 00:03:33) [common]
34674 11:20:28.305676 Listened to connection for namespace 'common' for up to 1s
34675 11:20:29.309758 Finalising connection for namespace 'common'
34677 11:20:29.410732 / # poweroff
34678 11:20:29.411198 Already disconnected
34679 11:20:29.411380 poweroff
34680 11:20:29.813840 end: 4.2 read-feedback (duration 00:00:02) [common]
34681 11:20:29.814125 Already disconnected
34682 11:20:29.814285 end: 4 finalize (duration 00:00:02) [common]
34683 11:20:29.814451 Cleaning after the job
34684 11:20:29.814628 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/562648/deployimages-r_p1gz98/kernel
34685 11:20:29.823152 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/562648/deployimages-r_p1gz98/ramdisk
34686 11:20:29.839246 Stopping the qemu container lava-docker-qemu-562648-2.1.1-bznrx0998f
34687 11:20:31.128107 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/562648
34688 11:20:31.191295 Job finished correctly