Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 33
1 11:11:58.802701 lava-dispatcher, installed at version: 2023.05.1
2 11:11:58.802907 start: 0 validate
3 11:11:58.803032 Start time: 2023-06-05 11:11:58.803024+00:00 (UTC)
4 11:11:58.803154 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:11:58.803280 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 11:11:59.094278 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:11:59.095004 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:11:59.383391 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:11:59.383586 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:12:25.840938 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:12:25.841593 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:12:26.424899 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:12:26.425572 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:12:26.725952 validate duration: 27.92
16 11:12:26.727098 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:12:26.727620 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:12:26.728058 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:12:26.728628 Not decompressing ramdisk as can be used compressed.
20 11:12:26.729080 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/initrd.cpio.gz
21 11:12:26.729442 saving as /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/ramdisk/initrd.cpio.gz
22 11:12:26.729799 total size: 4665395 (4MB)
23 11:12:30.469900 progress 0% (0MB)
24 11:12:30.478626 progress 5% (0MB)
25 11:12:30.485455 progress 10% (0MB)
26 11:12:30.491820 progress 15% (0MB)
27 11:12:30.497362 progress 20% (0MB)
28 11:12:30.501398 progress 25% (1MB)
29 11:12:30.504674 progress 30% (1MB)
30 11:12:30.507485 progress 35% (1MB)
31 11:12:30.510221 progress 40% (1MB)
32 11:12:30.512846 progress 45% (2MB)
33 11:12:30.515085 progress 50% (2MB)
34 11:12:30.517090 progress 55% (2MB)
35 11:12:30.518992 progress 60% (2MB)
36 11:12:30.520862 progress 65% (2MB)
37 11:12:30.522506 progress 70% (3MB)
38 11:12:30.524147 progress 75% (3MB)
39 11:12:30.525806 progress 80% (3MB)
40 11:12:30.527506 progress 85% (3MB)
41 11:12:30.529069 progress 90% (4MB)
42 11:12:30.530651 progress 95% (4MB)
43 11:12:30.532066 progress 100% (4MB)
44 11:12:30.532237 4MB downloaded in 3.80s (1.17MB/s)
45 11:12:30.532396 end: 1.1.1 http-download (duration 00:00:04) [common]
47 11:12:30.532692 end: 1.1 download-retry (duration 00:00:04) [common]
48 11:12:30.532791 start: 1.2 download-retry (timeout 00:09:56) [common]
49 11:12:30.532893 start: 1.2.1 http-download (timeout 00:09:56) [common]
50 11:12:30.533053 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:12:30.533134 saving as /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/kernel/Image
52 11:12:30.533203 total size: 45746688 (43MB)
53 11:12:30.533271 No compression specified
54 11:12:30.825864 progress 0% (0MB)
55 11:12:30.870734 progress 5% (2MB)
56 11:12:30.888133 progress 10% (4MB)
57 11:12:30.900661 progress 15% (6MB)
58 11:12:30.912051 progress 20% (8MB)
59 11:12:30.923446 progress 25% (10MB)
60 11:12:30.934640 progress 30% (13MB)
61 11:12:30.946046 progress 35% (15MB)
62 11:12:30.957483 progress 40% (17MB)
63 11:12:30.968996 progress 45% (19MB)
64 11:12:30.980632 progress 50% (21MB)
65 11:12:30.991900 progress 55% (24MB)
66 11:12:31.003550 progress 60% (26MB)
67 11:12:31.015041 progress 65% (28MB)
68 11:12:31.026510 progress 70% (30MB)
69 11:12:31.038605 progress 75% (32MB)
70 11:12:31.049877 progress 80% (34MB)
71 11:12:31.061375 progress 85% (37MB)
72 11:12:31.072903 progress 90% (39MB)
73 11:12:31.084231 progress 95% (41MB)
74 11:12:31.095541 progress 100% (43MB)
75 11:12:31.095666 43MB downloaded in 0.56s (77.57MB/s)
76 11:12:31.095812 end: 1.2.1 http-download (duration 00:00:01) [common]
78 11:12:31.096052 end: 1.2 download-retry (duration 00:00:01) [common]
79 11:12:31.096141 start: 1.3 download-retry (timeout 00:09:56) [common]
80 11:12:31.096231 start: 1.3.1 http-download (timeout 00:09:56) [common]
81 11:12:31.096364 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:12:31.096432 saving as /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/dtb/mt8192-asurada-spherion-r0.dtb
83 11:12:31.096493 total size: 46924 (0MB)
84 11:12:31.096597 No compression specified
85 11:12:31.097694 progress 69% (0MB)
86 11:12:31.097967 progress 100% (0MB)
87 11:12:31.098119 0MB downloaded in 0.00s (27.57MB/s)
88 11:12:31.098237 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:12:31.098456 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:12:31.098541 start: 1.4 download-retry (timeout 00:09:56) [common]
92 11:12:31.098623 start: 1.4.1 http-download (timeout 00:09:56) [common]
93 11:12:31.098733 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/full.rootfs.tar.xz
94 11:12:31.098800 saving as /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/nfsrootfs/full.rootfs.tar
95 11:12:31.098861 total size: 125267308 (119MB)
96 11:12:31.098921 Using unxz to decompress xz
97 11:12:31.102431 progress 0% (0MB)
98 11:12:31.418996 progress 5% (6MB)
99 11:12:31.753691 progress 10% (11MB)
100 11:12:32.079449 progress 15% (17MB)
101 11:12:32.265516 progress 20% (23MB)
102 11:12:32.442852 progress 25% (29MB)
103 11:12:32.782311 progress 30% (35MB)
104 11:12:33.180890 progress 35% (41MB)
105 11:12:33.557271 progress 40% (47MB)
106 11:12:33.923089 progress 45% (53MB)
107 11:12:34.297160 progress 50% (59MB)
108 11:12:34.641803 progress 55% (65MB)
109 11:12:34.993362 progress 60% (71MB)
110 11:12:35.328538 progress 65% (77MB)
111 11:12:35.689883 progress 70% (83MB)
112 11:12:36.068122 progress 75% (89MB)
113 11:12:36.485954 progress 80% (95MB)
114 11:12:36.894091 progress 85% (101MB)
115 11:12:37.127842 progress 90% (107MB)
116 11:12:37.456701 progress 95% (113MB)
117 11:12:37.821007 progress 100% (119MB)
118 11:12:37.827053 119MB downloaded in 6.73s (17.76MB/s)
119 11:12:37.827351 end: 1.4.1 http-download (duration 00:00:07) [common]
121 11:12:37.827647 end: 1.4 download-retry (duration 00:00:07) [common]
122 11:12:37.827752 start: 1.5 download-retry (timeout 00:09:49) [common]
123 11:12:37.827859 start: 1.5.1 http-download (timeout 00:09:49) [common]
124 11:12:37.828023 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:12:37.828127 saving as /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/modules/modules.tar
126 11:12:37.828230 total size: 8547328 (8MB)
127 11:12:37.828343 Using unxz to decompress xz
128 11:12:38.128914 progress 0% (0MB)
129 11:12:38.187053 progress 5% (0MB)
130 11:12:38.213441 progress 10% (0MB)
131 11:12:38.238959 progress 15% (1MB)
132 11:12:38.262974 progress 20% (1MB)
133 11:12:38.288200 progress 25% (2MB)
134 11:12:38.312759 progress 30% (2MB)
135 11:12:38.337534 progress 35% (2MB)
136 11:12:38.361765 progress 40% (3MB)
137 11:12:38.386424 progress 45% (3MB)
138 11:12:38.409882 progress 50% (4MB)
139 11:12:38.432478 progress 55% (4MB)
140 11:12:38.456999 progress 60% (4MB)
141 11:12:38.481540 progress 65% (5MB)
142 11:12:38.506257 progress 70% (5MB)
143 11:12:38.532620 progress 75% (6MB)
144 11:12:38.561379 progress 80% (6MB)
145 11:12:38.583468 progress 85% (6MB)
146 11:12:38.607947 progress 90% (7MB)
147 11:12:38.630937 progress 95% (7MB)
148 11:12:38.654102 progress 100% (8MB)
149 11:12:38.659935 8MB downloaded in 0.83s (9.80MB/s)
150 11:12:38.660212 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:12:38.660556 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:12:38.660665 start: 1.6 prepare-tftp-overlay (timeout 00:09:48) [common]
154 11:12:38.660761 start: 1.6.1 extract-nfsrootfs (timeout 00:09:48) [common]
155 11:12:40.767827 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10591227/extract-nfsrootfs-_ng094gw
156 11:12:40.768028 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:12:40.768135 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 11:12:40.768296 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva
159 11:12:40.768423 makedir: /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin
160 11:12:40.768715 makedir: /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/tests
161 11:12:40.768818 makedir: /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/results
162 11:12:40.768921 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-add-keys
163 11:12:40.769059 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-add-sources
164 11:12:40.769186 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-background-process-start
165 11:12:40.769311 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-background-process-stop
166 11:12:40.769433 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-common-functions
167 11:12:40.769553 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-echo-ipv4
168 11:12:40.769675 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-install-packages
169 11:12:40.769795 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-installed-packages
170 11:12:40.769914 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-os-build
171 11:12:40.770035 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-probe-channel
172 11:12:40.770166 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-probe-ip
173 11:12:40.770286 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-target-ip
174 11:12:40.770404 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-target-mac
175 11:12:40.770522 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-target-storage
176 11:12:40.770644 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-test-case
177 11:12:40.770765 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-test-event
178 11:12:40.770891 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-test-feedback
179 11:12:40.771013 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-test-raise
180 11:12:40.771133 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-test-reference
181 11:12:40.771254 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-test-runner
182 11:12:40.771375 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-test-set
183 11:12:40.771496 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-test-shell
184 11:12:40.771619 Updating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-install-packages (oe)
185 11:12:40.771763 Updating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/bin/lava-installed-packages (oe)
186 11:12:40.771888 Creating /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/environment
187 11:12:40.771990 LAVA metadata
188 11:12:40.772063 - LAVA_JOB_ID=10591227
189 11:12:40.772127 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:12:40.772226 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
191 11:12:40.772293 skipped lava-vland-overlay
192 11:12:40.772367 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:12:40.772446 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
194 11:12:40.772508 skipped lava-multinode-overlay
195 11:12:40.772631 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:12:40.772711 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
197 11:12:40.772783 Loading test definitions
198 11:12:40.772875 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
199 11:12:40.772951 Using /lava-10591227 at stage 0
200 11:12:40.773251 uuid=10591227_1.6.2.3.1 testdef=None
201 11:12:40.773342 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:12:40.773430 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
203 11:12:40.773919 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:12:40.774148 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
206 11:12:40.774769 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:12:40.775004 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
209 11:12:40.775623 runner path: /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/0/tests/0_dmesg test_uuid 10591227_1.6.2.3.1
210 11:12:40.775777 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:12:40.776015 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:46) [common]
213 11:12:40.776093 Using /lava-10591227 at stage 1
214 11:12:40.776496 uuid=10591227_1.6.2.3.5 testdef=None
215 11:12:40.776654 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 11:12:40.776769 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
217 11:12:40.777301 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 11:12:40.777519 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
220 11:12:40.778147 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 11:12:40.778377 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
223 11:12:40.778984 runner path: /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/1/tests/1_bootrr test_uuid 10591227_1.6.2.3.5
224 11:12:40.779140 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 11:12:40.779345 Creating lava-test-runner.conf files
227 11:12:40.779410 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/0 for stage 0
228 11:12:40.779499 - 0_dmesg
229 11:12:40.779577 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591227/lava-overlay-3jluwvva/lava-10591227/1 for stage 1
230 11:12:40.779666 - 1_bootrr
231 11:12:40.779759 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 11:12:40.779843 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
233 11:12:40.788386 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 11:12:40.788632 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:46) [common]
235 11:12:40.788755 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 11:12:40.788845 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 11:12:40.788931 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:46) [common]
238 11:12:40.904287 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 11:12:40.904709 start: 1.6.4 extract-modules (timeout 00:09:46) [common]
240 11:12:40.904833 extracting modules file /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591227/extract-nfsrootfs-_ng094gw
241 11:12:41.109405 extracting modules file /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591227/extract-overlay-ramdisk-7w_uns96/ramdisk
242 11:12:41.320023 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 11:12:41.320189 start: 1.6.5 apply-overlay-tftp (timeout 00:09:45) [common]
244 11:12:41.320285 [common] Applying overlay to NFS
245 11:12:41.320358 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591227/compress-overlay-4ue331vy/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591227/extract-nfsrootfs-_ng094gw
246 11:12:41.328340 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 11:12:41.328455 start: 1.6.6 configure-preseed-file (timeout 00:09:45) [common]
248 11:12:41.328630 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 11:12:41.328725 start: 1.6.7 compress-ramdisk (timeout 00:09:45) [common]
250 11:12:41.328805 Building ramdisk /var/lib/lava/dispatcher/tmp/10591227/extract-overlay-ramdisk-7w_uns96/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591227/extract-overlay-ramdisk-7w_uns96/ramdisk
251 11:12:41.595753 >> 117801 blocks
252 11:12:43.549507 rename /var/lib/lava/dispatcher/tmp/10591227/extract-overlay-ramdisk-7w_uns96/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/ramdisk/ramdisk.cpio.gz
253 11:12:43.549963 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 11:12:43.550099 start: 1.6.8 prepare-kernel (timeout 00:09:43) [common]
255 11:12:43.550215 start: 1.6.8.1 prepare-fit (timeout 00:09:43) [common]
256 11:12:43.550323 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/kernel/Image'
257 11:12:55.033518 Returned 0 in 11 seconds
258 11:12:55.134402 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/kernel/image.itb
259 11:12:55.449793 output: FIT description: Kernel Image image with one or more FDT blobs
260 11:12:55.450168 output: Created: Mon Jun 5 12:12:55 2023
261 11:12:55.450251 output: Image 0 (kernel-1)
262 11:12:55.450320 output: Description:
263 11:12:55.450384 output: Created: Mon Jun 5 12:12:55 2023
264 11:12:55.450456 output: Type: Kernel Image
265 11:12:55.450518 output: Compression: lzma compressed
266 11:12:55.450587 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
267 11:12:55.450645 output: Architecture: AArch64
268 11:12:55.450706 output: OS: Linux
269 11:12:55.450763 output: Load Address: 0x00000000
270 11:12:55.450829 output: Entry Point: 0x00000000
271 11:12:55.450887 output: Hash algo: crc32
272 11:12:55.450950 output: Hash value: eb1cf9b8
273 11:12:55.451004 output: Image 1 (fdt-1)
274 11:12:55.451058 output: Description: mt8192-asurada-spherion-r0
275 11:12:55.451113 output: Created: Mon Jun 5 12:12:55 2023
276 11:12:55.451166 output: Type: Flat Device Tree
277 11:12:55.451220 output: Compression: uncompressed
278 11:12:55.451273 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
279 11:12:55.451327 output: Architecture: AArch64
280 11:12:55.451381 output: Hash algo: crc32
281 11:12:55.451435 output: Hash value: 1df858fa
282 11:12:55.451497 output: Image 2 (ramdisk-1)
283 11:12:55.451551 output: Description: unavailable
284 11:12:55.451604 output: Created: Mon Jun 5 12:12:55 2023
285 11:12:55.451658 output: Type: RAMDisk Image
286 11:12:55.451711 output: Compression: Unknown Compression
287 11:12:55.451765 output: Data Size: 17646437 Bytes = 17232.85 KiB = 16.83 MiB
288 11:12:55.451819 output: Architecture: AArch64
289 11:12:55.451872 output: OS: Linux
290 11:12:55.451926 output: Load Address: unavailable
291 11:12:55.451987 output: Entry Point: unavailable
292 11:12:55.452041 output: Hash algo: crc32
293 11:12:55.452102 output: Hash value: 56bd29da
294 11:12:55.452155 output: Default Configuration: 'conf-1'
295 11:12:55.452209 output: Configuration 0 (conf-1)
296 11:12:55.452261 output: Description: mt8192-asurada-spherion-r0
297 11:12:55.452314 output: Kernel: kernel-1
298 11:12:55.452374 output: Init Ramdisk: ramdisk-1
299 11:12:55.452429 output: FDT: fdt-1
300 11:12:55.452487 output: Loadables: kernel-1
301 11:12:55.452551 output:
302 11:12:55.452745 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
303 11:12:55.452855 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
304 11:12:55.452956 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
305 11:12:55.453056 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
306 11:12:55.453143 No LXC device requested
307 11:12:55.453224 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 11:12:55.453314 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
309 11:12:55.453391 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 11:12:55.453474 Checking files for TFTP limit of 4294967296 bytes.
311 11:12:55.453985 end: 1 tftp-deploy (duration 00:00:29) [common]
312 11:12:55.454102 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 11:12:55.454204 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 11:12:55.454348 substitutions:
315 11:12:55.454418 - {DTB}: 10591227/tftp-deploy-cv815yyk/dtb/mt8192-asurada-spherion-r0.dtb
316 11:12:55.454484 - {INITRD}: 10591227/tftp-deploy-cv815yyk/ramdisk/ramdisk.cpio.gz
317 11:12:55.454545 - {KERNEL}: 10591227/tftp-deploy-cv815yyk/kernel/Image
318 11:12:55.454605 - {LAVA_MAC}: None
319 11:12:55.454662 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10591227/extract-nfsrootfs-_ng094gw
320 11:12:55.454734 - {NFS_SERVER_IP}: 192.168.201.1
321 11:12:55.454793 - {PRESEED_CONFIG}: None
322 11:12:55.454850 - {PRESEED_LOCAL}: None
323 11:12:55.454906 - {RAMDISK}: 10591227/tftp-deploy-cv815yyk/ramdisk/ramdisk.cpio.gz
324 11:12:55.454962 - {ROOT_PART}: None
325 11:12:55.455025 - {ROOT}: None
326 11:12:55.455081 - {SERVER_IP}: 192.168.201.1
327 11:12:55.455136 - {TEE}: None
328 11:12:55.455198 Parsed boot commands:
329 11:12:55.455252 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 11:12:55.455447 Parsed boot commands: tftpboot 192.168.201.1 10591227/tftp-deploy-cv815yyk/kernel/image.itb 10591227/tftp-deploy-cv815yyk/kernel/cmdline
331 11:12:55.455539 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 11:12:55.455622 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 11:12:55.455724 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 11:12:55.455821 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 11:12:55.455902 Not connected, no need to disconnect.
336 11:12:55.455978 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 11:12:55.456070 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 11:12:55.456140 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
339 11:12:55.459556 Setting prompt string to ['lava-test: # ']
340 11:12:55.459904 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 11:12:55.460012 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 11:12:55.460114 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 11:12:55.460216 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 11:12:55.460407 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
345 11:13:00.602841 >> Command sent successfully.
346 11:13:00.613141 Returned 0 in 5 seconds
347 11:13:00.714253 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 11:13:00.714728 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 11:13:00.714865 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 11:13:00.714996 Setting prompt string to 'Starting depthcharge on Spherion...'
352 11:13:00.715098 Changing prompt to 'Starting depthcharge on Spherion...'
353 11:13:00.715204 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 11:13:00.715598 [Enter `^Ec?' for help]
355 11:13:00.877470
356 11:13:00.878028
357 11:13:00.878432 F0: 102B 0000
358 11:13:00.878813
359 11:13:00.879141 F3: 1001 0000 [0200]
360 11:13:00.879596
361 11:13:00.880840 F3: 1001 0000
362 11:13:00.881433
363 11:13:00.881942 F7: 102D 0000
364 11:13:00.882431
365 11:13:00.882975 F1: 0000 0000
366 11:13:00.883461
367 11:13:00.884270 V0: 0000 0000 [0001]
368 11:13:00.884789
369 11:13:00.885110 00: 0007 8000
370 11:13:00.885497
371 11:13:00.887902 01: 0000 0000
372 11:13:00.888431
373 11:13:00.888942 BP: 0C00 0209 [0000]
374 11:13:00.889413
375 11:13:00.891427 G0: 1182 0000
376 11:13:00.891948
377 11:13:00.892420 EC: 0000 0021 [4000]
378 11:13:00.892811
379 11:13:00.894942 S7: 0000 0000 [0000]
380 11:13:00.895528
381 11:13:00.896018 CC: 0000 0000 [0001]
382 11:13:00.896591
383 11:13:00.898699 T0: 0000 0040 [010F]
384 11:13:00.899208
385 11:13:00.899714 Jump to BL
386 11:13:00.900330
387 11:13:00.923632
388 11:13:00.924258
389 11:13:00.924834
390 11:13:00.930813 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 11:13:00.935038 ARM64: Exception handlers installed.
392 11:13:00.937914 ARM64: Testing exception
393 11:13:00.942087 ARM64: Done test exception
394 11:13:00.948906 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 11:13:00.959515 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 11:13:00.966931 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 11:13:00.974160 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 11:13:00.981102 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 11:13:00.991418 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 11:13:01.001259 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 11:13:01.008063 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 11:13:01.026642 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 11:13:01.029863 WDT: Last reset was cold boot
404 11:13:01.033503 SPI1(PAD0) initialized at 2873684 Hz
405 11:13:01.036631 SPI5(PAD0) initialized at 992727 Hz
406 11:13:01.039626 VBOOT: Loading verstage.
407 11:13:01.046630 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 11:13:01.049730 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 11:13:01.053374 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 11:13:01.056357 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 11:13:01.064128 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 11:13:01.070512 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 11:13:01.081606 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 11:13:01.082064
415 11:13:01.082575
416 11:13:01.091344 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 11:13:01.094706 ARM64: Exception handlers installed.
418 11:13:01.098009 ARM64: Testing exception
419 11:13:01.098638 ARM64: Done test exception
420 11:13:01.104411 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 11:13:01.108158 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:13:01.122200 Probing TPM: . done!
423 11:13:01.122697 TPM ready after 0 ms
424 11:13:01.129452 Connected to device vid:did:rid of 1ae0:0028:00
425 11:13:01.139669 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
426 11:13:01.178033 Initialized TPM device CR50 revision 0
427 11:13:01.189903 tlcl_send_startup: Startup return code is 0
428 11:13:01.190480 TPM: setup succeeded
429 11:13:01.201936 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 11:13:01.210319 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 11:13:01.221010 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 11:13:01.229366 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 11:13:01.233019 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 11:13:01.236040 in-header: 03 07 00 00 08 00 00 00
435 11:13:01.239220 in-data: aa e4 47 04 13 02 00 00
436 11:13:01.242902 Chrome EC: UHEPI supported
437 11:13:01.249563 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 11:13:01.252428 in-header: 03 ad 00 00 08 00 00 00
439 11:13:01.256079 in-data: 00 20 20 08 00 00 00 00
440 11:13:01.256542 Phase 1
441 11:13:01.259334 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 11:13:01.266162 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 11:13:01.272441 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 11:13:01.275704 Recovery requested (1009000e)
445 11:13:01.280282 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 11:13:01.288324 tlcl_extend: response is 0
447 11:13:01.296952 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 11:13:01.301881 tlcl_extend: response is 0
449 11:13:01.308502 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 11:13:01.328991 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 11:13:01.335576 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 11:13:01.336147
453 11:13:01.336669
454 11:13:01.346565 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 11:13:01.349753 ARM64: Exception handlers installed.
456 11:13:01.350347 ARM64: Testing exception
457 11:13:01.352626 ARM64: Done test exception
458 11:13:01.374908 pmic_efuse_setting: Set efuses in 11 msecs
459 11:13:01.378508 pmwrap_interface_init: Select PMIF_VLD_RDY
460 11:13:01.382673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 11:13:01.389089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 11:13:01.392368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 11:13:01.399061 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 11:13:01.402015 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 11:13:01.409071 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 11:13:01.412633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 11:13:01.415577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 11:13:01.422454 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 11:13:01.425484 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 11:13:01.432196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 11:13:01.435180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 11:13:01.438295 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 11:13:01.445540 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 11:13:01.452264 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 11:13:01.458871 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 11:13:01.461972 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 11:13:01.468535 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 11:13:01.475153 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 11:13:01.482058 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 11:13:01.485704 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 11:13:01.492876 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 11:13:01.495925 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 11:13:01.503527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 11:13:01.507154 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 11:13:01.513229 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 11:13:01.517501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 11:13:01.523870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 11:13:01.527574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 11:13:01.534126 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 11:13:01.537875 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 11:13:01.544396 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 11:13:01.548020 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 11:13:01.554931 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 11:13:01.557875 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 11:13:01.564308 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 11:13:01.567909 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 11:13:01.574541 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 11:13:01.578209 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 11:13:01.581663 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 11:13:01.585216 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 11:13:01.589426 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 11:13:01.596093 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 11:13:01.599473 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 11:13:01.602377 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 11:13:01.608947 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 11:13:01.612390 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 11:13:01.615953 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 11:13:01.622607 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 11:13:01.626057 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 11:13:01.628975 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 11:13:01.635649 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 11:13:01.646028 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 11:13:01.648941 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 11:13:01.659283 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 11:13:01.666000 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 11:13:01.672847 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 11:13:01.675919 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 11:13:01.679420 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 11:13:01.686714 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e
520 11:13:01.693624 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 11:13:01.696886 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
522 11:13:01.703349 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 11:13:01.711665 [RTC]rtc_get_frequency_meter,154: input=15, output=834
524 11:13:01.721168 [RTC]rtc_get_frequency_meter,154: input=7, output=709
525 11:13:01.730903 [RTC]rtc_get_frequency_meter,154: input=11, output=772
526 11:13:01.740258 [RTC]rtc_get_frequency_meter,154: input=13, output=804
527 11:13:01.749955 [RTC]rtc_get_frequency_meter,154: input=12, output=789
528 11:13:01.758984 [RTC]rtc_get_frequency_meter,154: input=12, output=788
529 11:13:01.768821 [RTC]rtc_get_frequency_meter,154: input=13, output=804
530 11:13:01.771762 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
531 11:13:01.778957 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
532 11:13:01.782481 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 11:13:01.785667 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 11:13:01.792131 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 11:13:01.795443 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 11:13:01.798980 ADC[4]: Raw value=904509 ID=7
537 11:13:01.799408 ADC[3]: Raw value=213282 ID=1
538 11:13:01.801993 RAM Code: 0x71
539 11:13:01.805747 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 11:13:01.812797 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 11:13:01.818675 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 11:13:01.825544 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 11:13:01.828689 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 11:13:01.832227 in-header: 03 07 00 00 08 00 00 00
545 11:13:01.835834 in-data: aa e4 47 04 13 02 00 00
546 11:13:01.838666 Chrome EC: UHEPI supported
547 11:13:01.845298 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 11:13:01.848816 in-header: 03 dd 00 00 08 00 00 00
549 11:13:01.851845 in-data: 90 20 60 08 00 00 00 00
550 11:13:01.855440 MRC: failed to locate region type 0.
551 11:13:01.862153 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 11:13:01.865266 DRAM-K: Running full calibration
553 11:13:01.871822 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 11:13:01.872261 header.status = 0x0
555 11:13:01.874976 header.version = 0x6 (expected: 0x6)
556 11:13:01.878404 header.size = 0xd00 (expected: 0xd00)
557 11:13:01.881931 header.flags = 0x0
558 11:13:01.888783 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 11:13:01.905466 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
560 11:13:01.912111 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 11:13:01.914924 dram_init: ddr_geometry: 2
562 11:13:01.918065 [EMI] MDL number = 2
563 11:13:01.918166 [EMI] Get MDL freq = 0
564 11:13:01.921589 dram_init: ddr_type: 0
565 11:13:01.921676 is_discrete_lpddr4: 1
566 11:13:01.924568 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 11:13:01.924668
568 11:13:01.928318
569 11:13:01.928431 [Bian_co] ETT version 0.0.0.1
570 11:13:01.934887 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 11:13:01.934977
572 11:13:01.937886 dramc_set_vcore_voltage set vcore to 650000
573 11:13:01.941755 Read voltage for 800, 4
574 11:13:01.941836 Vio18 = 0
575 11:13:01.941910 Vcore = 650000
576 11:13:01.944764 Vdram = 0
577 11:13:01.944843 Vddq = 0
578 11:13:01.944911 Vmddr = 0
579 11:13:01.947898 dram_init: config_dvfs: 1
580 11:13:01.951546 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 11:13:01.958170 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 11:13:01.961817 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
583 11:13:01.964894 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
584 11:13:01.968676 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
585 11:13:01.971525 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
586 11:13:01.974753 MEM_TYPE=3, freq_sel=18
587 11:13:01.978346 sv_algorithm_assistance_LP4_1600
588 11:13:01.981394 ============ PULL DRAM RESETB DOWN ============
589 11:13:01.988434 ========== PULL DRAM RESETB DOWN end =========
590 11:13:01.991491 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 11:13:01.994987 ===================================
592 11:13:01.997994 LPDDR4 DRAM CONFIGURATION
593 11:13:02.001618 ===================================
594 11:13:02.001846 EX_ROW_EN[0] = 0x0
595 11:13:02.004455 EX_ROW_EN[1] = 0x0
596 11:13:02.004686 LP4Y_EN = 0x0
597 11:13:02.007910 WORK_FSP = 0x0
598 11:13:02.008179 WL = 0x2
599 11:13:02.011128 RL = 0x2
600 11:13:02.011402 BL = 0x2
601 11:13:02.014681 RPST = 0x0
602 11:13:02.014931 RD_PRE = 0x0
603 11:13:02.018297 WR_PRE = 0x1
604 11:13:02.021278 WR_PST = 0x0
605 11:13:02.021626 DBI_WR = 0x0
606 11:13:02.024941 DBI_RD = 0x0
607 11:13:02.025329 OTF = 0x1
608 11:13:02.028225 ===================================
609 11:13:02.031362 ===================================
610 11:13:02.032102 ANA top config
611 11:13:02.034439 ===================================
612 11:13:02.037907 DLL_ASYNC_EN = 0
613 11:13:02.041562 ALL_SLAVE_EN = 1
614 11:13:02.044447 NEW_RANK_MODE = 1
615 11:13:02.047827 DLL_IDLE_MODE = 1
616 11:13:02.048413 LP45_APHY_COMB_EN = 1
617 11:13:02.050935 TX_ODT_DIS = 1
618 11:13:02.054410 NEW_8X_MODE = 1
619 11:13:02.058055 ===================================
620 11:13:02.061245 ===================================
621 11:13:02.064704 data_rate = 1600
622 11:13:02.067891 CKR = 1
623 11:13:02.068445 DQ_P2S_RATIO = 8
624 11:13:02.071507 ===================================
625 11:13:02.074662 CA_P2S_RATIO = 8
626 11:13:02.077739 DQ_CA_OPEN = 0
627 11:13:02.081451 DQ_SEMI_OPEN = 0
628 11:13:02.084379 CA_SEMI_OPEN = 0
629 11:13:02.087897 CA_FULL_RATE = 0
630 11:13:02.088469 DQ_CKDIV4_EN = 1
631 11:13:02.090957 CA_CKDIV4_EN = 1
632 11:13:02.094346 CA_PREDIV_EN = 0
633 11:13:02.098002 PH8_DLY = 0
634 11:13:02.101083 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 11:13:02.103956 DQ_AAMCK_DIV = 4
636 11:13:02.104672 CA_AAMCK_DIV = 4
637 11:13:02.107582 CA_ADMCK_DIV = 4
638 11:13:02.110889 DQ_TRACK_CA_EN = 0
639 11:13:02.114329 CA_PICK = 800
640 11:13:02.117794 CA_MCKIO = 800
641 11:13:02.120774 MCKIO_SEMI = 0
642 11:13:02.124328 PLL_FREQ = 3068
643 11:13:02.124844 DQ_UI_PI_RATIO = 32
644 11:13:02.127770 CA_UI_PI_RATIO = 0
645 11:13:02.130865 ===================================
646 11:13:02.134108 ===================================
647 11:13:02.137721 memory_type:LPDDR4
648 11:13:02.141416 GP_NUM : 10
649 11:13:02.141895 SRAM_EN : 1
650 11:13:02.143992 MD32_EN : 0
651 11:13:02.147741 ===================================
652 11:13:02.150648 [ANA_INIT] >>>>>>>>>>>>>>
653 11:13:02.151102 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 11:13:02.154021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 11:13:02.157474 ===================================
656 11:13:02.160590 data_rate = 1600,PCW = 0X7600
657 11:13:02.164168 ===================================
658 11:13:02.167713 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 11:13:02.174415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 11:13:02.181261 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 11:13:02.184071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 11:13:02.187810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 11:13:02.190915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 11:13:02.194412 [ANA_INIT] flow start
665 11:13:02.194874 [ANA_INIT] PLL >>>>>>>>
666 11:13:02.197336 [ANA_INIT] PLL <<<<<<<<
667 11:13:02.200709 [ANA_INIT] MIDPI >>>>>>>>
668 11:13:02.201136 [ANA_INIT] MIDPI <<<<<<<<
669 11:13:02.204377 [ANA_INIT] DLL >>>>>>>>
670 11:13:02.208023 [ANA_INIT] flow end
671 11:13:02.210897 ============ LP4 DIFF to SE enter ============
672 11:13:02.214256 ============ LP4 DIFF to SE exit ============
673 11:13:02.217257 [ANA_INIT] <<<<<<<<<<<<<
674 11:13:02.221000 [Flow] Enable top DCM control >>>>>
675 11:13:02.224400 [Flow] Enable top DCM control <<<<<
676 11:13:02.227272 Enable DLL master slave shuffle
677 11:13:02.230969 ==============================================================
678 11:13:02.234425 Gating Mode config
679 11:13:02.240962 ==============================================================
680 11:13:02.241410 Config description:
681 11:13:02.250850 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 11:13:02.257412 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 11:13:02.260886 SELPH_MODE 0: By rank 1: By Phase
684 11:13:02.267355 ==============================================================
685 11:13:02.271007 GAT_TRACK_EN = 1
686 11:13:02.274136 RX_GATING_MODE = 2
687 11:13:02.277183 RX_GATING_TRACK_MODE = 2
688 11:13:02.280823 SELPH_MODE = 1
689 11:13:02.283855 PICG_EARLY_EN = 1
690 11:13:02.287353 VALID_LAT_VALUE = 1
691 11:13:02.290436 ==============================================================
692 11:13:02.294344 Enter into Gating configuration >>>>
693 11:13:02.297304 Exit from Gating configuration <<<<
694 11:13:02.300809 Enter into DVFS_PRE_config >>>>>
695 11:13:02.313906 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 11:13:02.314386 Exit from DVFS_PRE_config <<<<<
697 11:13:02.316984 Enter into PICG configuration >>>>
698 11:13:02.320387 Exit from PICG configuration <<<<
699 11:13:02.323680 [RX_INPUT] configuration >>>>>
700 11:13:02.327313 [RX_INPUT] configuration <<<<<
701 11:13:02.333765 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 11:13:02.337136 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 11:13:02.344446 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 11:13:02.351516 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 11:13:02.354927 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 11:13:02.362329 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 11:13:02.365906 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 11:13:02.369644 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 11:13:02.373357 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 11:13:02.380119 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 11:13:02.383864 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 11:13:02.387401 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 11:13:02.391663 ===================================
714 11:13:02.394822 LPDDR4 DRAM CONFIGURATION
715 11:13:02.395458 ===================================
716 11:13:02.398278 EX_ROW_EN[0] = 0x0
717 11:13:02.402263 EX_ROW_EN[1] = 0x0
718 11:13:02.402764 LP4Y_EN = 0x0
719 11:13:02.405687 WORK_FSP = 0x0
720 11:13:02.406128 WL = 0x2
721 11:13:02.406566 RL = 0x2
722 11:13:02.409228 BL = 0x2
723 11:13:02.409830 RPST = 0x0
724 11:13:02.413047 RD_PRE = 0x0
725 11:13:02.413499 WR_PRE = 0x1
726 11:13:02.416574 WR_PST = 0x0
727 11:13:02.417223 DBI_WR = 0x0
728 11:13:02.420299 DBI_RD = 0x0
729 11:13:02.420844 OTF = 0x1
730 11:13:02.424024 ===================================
731 11:13:02.427965 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 11:13:02.431175 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 11:13:02.438776 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 11:13:02.439215 ===================================
735 11:13:02.442200 LPDDR4 DRAM CONFIGURATION
736 11:13:02.445808 ===================================
737 11:13:02.449999 EX_ROW_EN[0] = 0x10
738 11:13:02.450427 EX_ROW_EN[1] = 0x0
739 11:13:02.453383 LP4Y_EN = 0x0
740 11:13:02.453813 WORK_FSP = 0x0
741 11:13:02.454158 WL = 0x2
742 11:13:02.457515 RL = 0x2
743 11:13:02.457975 BL = 0x2
744 11:13:02.460863 RPST = 0x0
745 11:13:02.461312 RD_PRE = 0x0
746 11:13:02.464556 WR_PRE = 0x1
747 11:13:02.465003 WR_PST = 0x0
748 11:13:02.468338 DBI_WR = 0x0
749 11:13:02.468816 DBI_RD = 0x0
750 11:13:02.472279 OTF = 0x1
751 11:13:02.475254 ===================================
752 11:13:02.478781 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 11:13:02.484413 nWR fixed to 40
754 11:13:02.484886 [ModeRegInit_LP4] CH0 RK0
755 11:13:02.487228 [ModeRegInit_LP4] CH0 RK1
756 11:13:02.490901 [ModeRegInit_LP4] CH1 RK0
757 11:13:02.494616 [ModeRegInit_LP4] CH1 RK1
758 11:13:02.494701 match AC timing 13
759 11:13:02.498132 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 11:13:02.501064 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 11:13:02.508737 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 11:13:02.512068 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 11:13:02.515487 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 11:13:02.518482 [EMI DOE] emi_dcm 0
765 11:13:02.522070 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 11:13:02.522187 ==
767 11:13:02.525282 Dram Type= 6, Freq= 0, CH_0, rank 0
768 11:13:02.531785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 11:13:02.531918 ==
770 11:13:02.535457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 11:13:02.541846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 11:13:02.550812 [CA 0] Center 37 (6~68) winsize 63
773 11:13:02.554365 [CA 1] Center 37 (6~68) winsize 63
774 11:13:02.557780 [CA 2] Center 34 (4~65) winsize 62
775 11:13:02.561182 [CA 3] Center 34 (4~65) winsize 62
776 11:13:02.564802 [CA 4] Center 33 (3~64) winsize 62
777 11:13:02.568423 [CA 5] Center 33 (3~64) winsize 62
778 11:13:02.568904
779 11:13:02.572147 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 11:13:02.572561
781 11:13:02.575395 [CATrainingPosCal] consider 1 rank data
782 11:13:02.578771 u2DelayCellTimex100 = 270/100 ps
783 11:13:02.581888 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
784 11:13:02.585741 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
785 11:13:02.588644 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
786 11:13:02.592488 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
787 11:13:02.598952 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 11:13:02.601821 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 11:13:02.602255
790 11:13:02.604954 CA PerBit enable=1, Macro0, CA PI delay=33
791 11:13:02.605390
792 11:13:02.608398 [CBTSetCACLKResult] CA Dly = 33
793 11:13:02.608879 CS Dly: 6 (0~37)
794 11:13:02.609224 ==
795 11:13:02.611672 Dram Type= 6, Freq= 0, CH_0, rank 1
796 11:13:02.618576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 11:13:02.619013 ==
798 11:13:02.621944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 11:13:02.628026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 11:13:02.637236 [CA 0] Center 37 (6~68) winsize 63
801 11:13:02.640865 [CA 1] Center 37 (7~67) winsize 61
802 11:13:02.644329 [CA 2] Center 34 (4~65) winsize 62
803 11:13:02.647155 [CA 3] Center 34 (4~65) winsize 62
804 11:13:02.650822 [CA 4] Center 33 (3~64) winsize 62
805 11:13:02.654395 [CA 5] Center 33 (3~64) winsize 62
806 11:13:02.654828
807 11:13:02.657525 [CmdBusTrainingLP45] Vref(ca) range 1: 32
808 11:13:02.657957
809 11:13:02.660783 [CATrainingPosCal] consider 2 rank data
810 11:13:02.663892 u2DelayCellTimex100 = 270/100 ps
811 11:13:02.667691 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
812 11:13:02.670982 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
813 11:13:02.678151 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
814 11:13:02.681627 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 11:13:02.682060 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 11:13:02.685239 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 11:13:02.688730
818 11:13:02.692304 CA PerBit enable=1, Macro0, CA PI delay=33
819 11:13:02.692784
820 11:13:02.693132 [CBTSetCACLKResult] CA Dly = 33
821 11:13:02.696013 CS Dly: 6 (0~38)
822 11:13:02.696442
823 11:13:02.700366 ----->DramcWriteLeveling(PI) begin...
824 11:13:02.700833 ==
825 11:13:02.703576 Dram Type= 6, Freq= 0, CH_0, rank 0
826 11:13:02.707198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 11:13:02.707647 ==
828 11:13:02.710295 Write leveling (Byte 0): 30 => 30
829 11:13:02.713794 Write leveling (Byte 1): 30 => 30
830 11:13:02.717363 DramcWriteLeveling(PI) end<-----
831 11:13:02.717810
832 11:13:02.718182 ==
833 11:13:02.720318 Dram Type= 6, Freq= 0, CH_0, rank 0
834 11:13:02.723959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 11:13:02.724394 ==
836 11:13:02.727456 [Gating] SW mode calibration
837 11:13:02.734169 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 11:13:02.740626 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 11:13:02.743685 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 11:13:02.747256 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
841 11:13:02.750574 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 11:13:02.757089 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
843 11:13:02.760302 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:13:02.763668 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 11:13:02.770545 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 11:13:02.773537 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 11:13:02.776906 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 11:13:02.783616 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 11:13:02.787097 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 11:13:02.790362 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 11:13:02.796948 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 11:13:02.800007 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:13:02.803479 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:13:02.810127 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:13:02.813666 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:13:02.817214 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
857 11:13:02.823893 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
858 11:13:02.826803 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:13:02.830286 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:13:02.836914 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:13:02.840170 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:13:02.843942 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:13:02.849983 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:13:02.853523 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:13:02.856562 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
866 11:13:02.863448 0 9 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
867 11:13:02.866956 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 11:13:02.870276 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 11:13:02.876581 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 11:13:02.879852 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 11:13:02.883053 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 11:13:02.890057 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
873 11:13:02.893562 0 10 8 | B1->B0 | 3232 2a2a | 0 0 | (1 0) (1 1)
874 11:13:02.896545 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
875 11:13:02.900288 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:13:02.906299 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:13:02.909737 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:13:02.913456 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:13:02.919833 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 11:13:02.923132 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
881 11:13:02.926753 0 11 8 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
882 11:13:02.933494 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
883 11:13:02.936227 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 11:13:02.939190 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 11:13:02.946123 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 11:13:02.949652 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 11:13:02.952700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 11:13:02.959672 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 11:13:02.962745 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
890 11:13:02.966279 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
891 11:13:02.972957 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 11:13:02.975939 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 11:13:02.979281 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 11:13:02.986189 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 11:13:02.989200 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 11:13:02.992699 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 11:13:02.999285 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 11:13:03.002277 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 11:13:03.005781 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 11:13:03.012661 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 11:13:03.015540 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:13:03.019033 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:13:03.025750 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:13:03.029265 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
905 11:13:03.032435 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
906 11:13:03.039404 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
907 11:13:03.040032 Total UI for P1: 0, mck2ui 16
908 11:13:03.045567 best dqsien dly found for B0: ( 0, 14, 6)
909 11:13:03.049128 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
910 11:13:03.052274 Total UI for P1: 0, mck2ui 16
911 11:13:03.056172 best dqsien dly found for B1: ( 0, 14, 10)
912 11:13:03.058776 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
913 11:13:03.062437 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
914 11:13:03.062870
915 11:13:03.065594 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
916 11:13:03.070199 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
917 11:13:03.073264 [Gating] SW calibration Done
918 11:13:03.073708 ==
919 11:13:03.076592 Dram Type= 6, Freq= 0, CH_0, rank 0
920 11:13:03.079672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 11:13:03.080120 ==
922 11:13:03.083064 RX Vref Scan: 0
923 11:13:03.083505
924 11:13:03.083945 RX Vref 0 -> 0, step: 1
925 11:13:03.084360
926 11:13:03.086647 RX Delay -130 -> 252, step: 16
927 11:13:03.089526 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
928 11:13:03.096087 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
929 11:13:03.099715 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
930 11:13:03.103236 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
931 11:13:03.106212 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
932 11:13:03.109240 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
933 11:13:03.115929 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
934 11:13:03.119601 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
935 11:13:03.123047 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
936 11:13:03.125956 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
937 11:13:03.129636 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
938 11:13:03.136367 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
939 11:13:03.139442 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
940 11:13:03.142521 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
941 11:13:03.145973 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
942 11:13:03.152615 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
943 11:13:03.153062 ==
944 11:13:03.155806 Dram Type= 6, Freq= 0, CH_0, rank 0
945 11:13:03.159485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
946 11:13:03.159929 ==
947 11:13:03.160374 DQS Delay:
948 11:13:03.162968 DQS0 = 0, DQS1 = 0
949 11:13:03.163412 DQM Delay:
950 11:13:03.166008 DQM0 = 87, DQM1 = 78
951 11:13:03.166451 DQ Delay:
952 11:13:03.169837 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
953 11:13:03.173382 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
954 11:13:03.177176 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
955 11:13:03.180656 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
956 11:13:03.181102
957 11:13:03.181546
958 11:13:03.181964 ==
959 11:13:03.184918 Dram Type= 6, Freq= 0, CH_0, rank 0
960 11:13:03.188188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 11:13:03.188680 ==
962 11:13:03.189127
963 11:13:03.189543
964 11:13:03.189949 TX Vref Scan disable
965 11:13:03.191814 == TX Byte 0 ==
966 11:13:03.195309 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
967 11:13:03.198925 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
968 11:13:03.203275 == TX Byte 1 ==
969 11:13:03.206847 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
970 11:13:03.210396 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
971 11:13:03.210876 ==
972 11:13:03.214086 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:13:03.217711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:13:03.218157 ==
975 11:13:03.230355 TX Vref=22, minBit 4, minWin=27, winSum=442
976 11:13:03.233324 TX Vref=24, minBit 8, minWin=27, winSum=445
977 11:13:03.236995 TX Vref=26, minBit 1, minWin=28, winSum=449
978 11:13:03.240120 TX Vref=28, minBit 10, minWin=27, winSum=447
979 11:13:03.243818 TX Vref=30, minBit 10, minWin=27, winSum=448
980 11:13:03.250388 TX Vref=32, minBit 9, minWin=26, winSum=441
981 11:13:03.253422 [TxChooseVref] Worse bit 1, Min win 28, Win sum 449, Final Vref 26
982 11:13:03.253866
983 11:13:03.257010 Final TX Range 1 Vref 26
984 11:13:03.257472
985 11:13:03.257825 ==
986 11:13:03.259976 Dram Type= 6, Freq= 0, CH_0, rank 0
987 11:13:03.266781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 11:13:03.267323 ==
989 11:13:03.267669
990 11:13:03.267985
991 11:13:03.268290 TX Vref Scan disable
992 11:13:03.270973 == TX Byte 0 ==
993 11:13:03.274478 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
994 11:13:03.277847 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
995 11:13:03.281816 == TX Byte 1 ==
996 11:13:03.285165 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
997 11:13:03.288983 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
998 11:13:03.289412
999 11:13:03.289752 [DATLAT]
1000 11:13:03.292450 Freq=800, CH0 RK0
1001 11:13:03.292924
1002 11:13:03.293268 DATLAT Default: 0xa
1003 11:13:03.296696 0, 0xFFFF, sum = 0
1004 11:13:03.297132 1, 0xFFFF, sum = 0
1005 11:13:03.299767 2, 0xFFFF, sum = 0
1006 11:13:03.300203 3, 0xFFFF, sum = 0
1007 11:13:03.302813 4, 0xFFFF, sum = 0
1008 11:13:03.303249 5, 0xFFFF, sum = 0
1009 11:13:03.306564 6, 0xFFFF, sum = 0
1010 11:13:03.307015 7, 0xFFFF, sum = 0
1011 11:13:03.309268 8, 0xFFFF, sum = 0
1012 11:13:03.309705 9, 0x0, sum = 1
1013 11:13:03.313063 10, 0x0, sum = 2
1014 11:13:03.313500 11, 0x0, sum = 3
1015 11:13:03.316186 12, 0x0, sum = 4
1016 11:13:03.316654 best_step = 10
1017 11:13:03.316997
1018 11:13:03.317397 ==
1019 11:13:03.319157 Dram Type= 6, Freq= 0, CH_0, rank 0
1020 11:13:03.322839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1021 11:13:03.326067 ==
1022 11:13:03.326598 RX Vref Scan: 1
1023 11:13:03.326946
1024 11:13:03.329538 Set Vref Range= 32 -> 127
1025 11:13:03.329983
1026 11:13:03.332581 RX Vref 32 -> 127, step: 1
1027 11:13:03.333005
1028 11:13:03.333345 RX Delay -95 -> 252, step: 8
1029 11:13:03.333661
1030 11:13:03.335587 Set Vref, RX VrefLevel [Byte0]: 32
1031 11:13:03.339150 [Byte1]: 32
1032 11:13:03.343618
1033 11:13:03.344044 Set Vref, RX VrefLevel [Byte0]: 33
1034 11:13:03.346726 [Byte1]: 33
1035 11:13:03.350916
1036 11:13:03.351339 Set Vref, RX VrefLevel [Byte0]: 34
1037 11:13:03.354297 [Byte1]: 34
1038 11:13:03.358329
1039 11:13:03.358749 Set Vref, RX VrefLevel [Byte0]: 35
1040 11:13:03.361365 [Byte1]: 35
1041 11:13:03.365669
1042 11:13:03.369295 Set Vref, RX VrefLevel [Byte0]: 36
1043 11:13:03.369737 [Byte1]: 36
1044 11:13:03.373401
1045 11:13:03.373971 Set Vref, RX VrefLevel [Byte0]: 37
1046 11:13:03.376854 [Byte1]: 37
1047 11:13:03.380873
1048 11:13:03.381297 Set Vref, RX VrefLevel [Byte0]: 38
1049 11:13:03.384496 [Byte1]: 38
1050 11:13:03.388499
1051 11:13:03.388963 Set Vref, RX VrefLevel [Byte0]: 39
1052 11:13:03.391913 [Byte1]: 39
1053 11:13:03.396267
1054 11:13:03.396801 Set Vref, RX VrefLevel [Byte0]: 40
1055 11:13:03.399875 [Byte1]: 40
1056 11:13:03.404003
1057 11:13:03.404489 Set Vref, RX VrefLevel [Byte0]: 41
1058 11:13:03.407651 [Byte1]: 41
1059 11:13:03.411321
1060 11:13:03.411747 Set Vref, RX VrefLevel [Byte0]: 42
1061 11:13:03.414669 [Byte1]: 42
1062 11:13:03.419388
1063 11:13:03.419845 Set Vref, RX VrefLevel [Byte0]: 43
1064 11:13:03.422215 [Byte1]: 43
1065 11:13:03.426731
1066 11:13:03.427157 Set Vref, RX VrefLevel [Byte0]: 44
1067 11:13:03.430352 [Byte1]: 44
1068 11:13:03.434479
1069 11:13:03.434961 Set Vref, RX VrefLevel [Byte0]: 45
1070 11:13:03.437432 [Byte1]: 45
1071 11:13:03.442322
1072 11:13:03.442772 Set Vref, RX VrefLevel [Byte0]: 46
1073 11:13:03.445395 [Byte1]: 46
1074 11:13:03.449605
1075 11:13:03.450055 Set Vref, RX VrefLevel [Byte0]: 47
1076 11:13:03.452657 [Byte1]: 47
1077 11:13:03.457448
1078 11:13:03.457876 Set Vref, RX VrefLevel [Byte0]: 48
1079 11:13:03.460359 [Byte1]: 48
1080 11:13:03.464823
1081 11:13:03.467854 Set Vref, RX VrefLevel [Byte0]: 49
1082 11:13:03.471378 [Byte1]: 49
1083 11:13:03.471802
1084 11:13:03.474346 Set Vref, RX VrefLevel [Byte0]: 50
1085 11:13:03.477740 [Byte1]: 50
1086 11:13:03.478168
1087 11:13:03.481018 Set Vref, RX VrefLevel [Byte0]: 51
1088 11:13:03.484502 [Byte1]: 51
1089 11:13:03.484960
1090 11:13:03.487952 Set Vref, RX VrefLevel [Byte0]: 52
1091 11:13:03.490892 [Byte1]: 52
1092 11:13:03.494903
1093 11:13:03.495327 Set Vref, RX VrefLevel [Byte0]: 53
1094 11:13:03.498173 [Byte1]: 53
1095 11:13:03.502636
1096 11:13:03.503060 Set Vref, RX VrefLevel [Byte0]: 54
1097 11:13:03.506019 [Byte1]: 54
1098 11:13:03.510682
1099 11:13:03.511102 Set Vref, RX VrefLevel [Byte0]: 55
1100 11:13:03.513693 [Byte1]: 55
1101 11:13:03.518093
1102 11:13:03.518643 Set Vref, RX VrefLevel [Byte0]: 56
1103 11:13:03.521318 [Byte1]: 56
1104 11:13:03.525620
1105 11:13:03.526043 Set Vref, RX VrefLevel [Byte0]: 57
1106 11:13:03.529170 [Byte1]: 57
1107 11:13:03.533005
1108 11:13:03.533427 Set Vref, RX VrefLevel [Byte0]: 58
1109 11:13:03.536459 [Byte1]: 58
1110 11:13:03.540638
1111 11:13:03.541064 Set Vref, RX VrefLevel [Byte0]: 59
1112 11:13:03.544381 [Byte1]: 59
1113 11:13:03.548505
1114 11:13:03.548985 Set Vref, RX VrefLevel [Byte0]: 60
1115 11:13:03.551532 [Byte1]: 60
1116 11:13:03.555685
1117 11:13:03.556110 Set Vref, RX VrefLevel [Byte0]: 61
1118 11:13:03.558885 [Byte1]: 61
1119 11:13:03.563555
1120 11:13:03.566585 Set Vref, RX VrefLevel [Byte0]: 62
1121 11:13:03.570009 [Byte1]: 62
1122 11:13:03.570434
1123 11:13:03.573037 Set Vref, RX VrefLevel [Byte0]: 63
1124 11:13:03.576764 [Byte1]: 63
1125 11:13:03.577194
1126 11:13:03.579632 Set Vref, RX VrefLevel [Byte0]: 64
1127 11:13:03.583234 [Byte1]: 64
1128 11:13:03.583683
1129 11:13:03.586585 Set Vref, RX VrefLevel [Byte0]: 65
1130 11:13:03.589673 [Byte1]: 65
1131 11:13:03.593715
1132 11:13:03.594144 Set Vref, RX VrefLevel [Byte0]: 66
1133 11:13:03.600397 [Byte1]: 66
1134 11:13:03.600882
1135 11:13:03.603978 Set Vref, RX VrefLevel [Byte0]: 67
1136 11:13:03.607644 [Byte1]: 67
1137 11:13:03.608086
1138 11:13:03.611343 Set Vref, RX VrefLevel [Byte0]: 68
1139 11:13:03.614474 [Byte1]: 68
1140 11:13:03.614922
1141 11:13:03.618137 Set Vref, RX VrefLevel [Byte0]: 69
1142 11:13:03.621730 [Byte1]: 69
1143 11:13:03.622160
1144 11:13:03.625627 Set Vref, RX VrefLevel [Byte0]: 70
1145 11:13:03.629270 [Byte1]: 70
1146 11:13:03.629719
1147 11:13:03.633157 Set Vref, RX VrefLevel [Byte0]: 71
1148 11:13:03.636654 [Byte1]: 71
1149 11:13:03.637088
1150 11:13:03.640111 Set Vref, RX VrefLevel [Byte0]: 72
1151 11:13:03.644119 [Byte1]: 72
1152 11:13:03.647666
1153 11:13:03.648204 Set Vref, RX VrefLevel [Byte0]: 73
1154 11:13:03.650922 [Byte1]: 73
1155 11:13:03.654341
1156 11:13:03.658033 Set Vref, RX VrefLevel [Byte0]: 74
1157 11:13:03.658460 [Byte1]: 74
1158 11:13:03.662222
1159 11:13:03.662644 Set Vref, RX VrefLevel [Byte0]: 75
1160 11:13:03.665949 [Byte1]: 75
1161 11:13:03.669848
1162 11:13:03.670282 Set Vref, RX VrefLevel [Byte0]: 76
1163 11:13:03.672924 [Byte1]: 76
1164 11:13:03.677323
1165 11:13:03.681019 Set Vref, RX VrefLevel [Byte0]: 77
1166 11:13:03.681540 [Byte1]: 77
1167 11:13:03.685021
1168 11:13:03.685449 Set Vref, RX VrefLevel [Byte0]: 78
1169 11:13:03.688169 [Byte1]: 78
1170 11:13:03.692750
1171 11:13:03.693266 Set Vref, RX VrefLevel [Byte0]: 79
1172 11:13:03.696237 [Byte1]: 79
1173 11:13:03.700323
1174 11:13:03.700783 Set Vref, RX VrefLevel [Byte0]: 80
1175 11:13:03.704311 [Byte1]: 80
1176 11:13:03.708282
1177 11:13:03.708809 Set Vref, RX VrefLevel [Byte0]: 81
1178 11:13:03.711548 [Byte1]: 81
1179 11:13:03.715695
1180 11:13:03.716121 Final RX Vref Byte 0 = 66 to rank0
1181 11:13:03.719103 Final RX Vref Byte 1 = 58 to rank0
1182 11:13:03.722636 Final RX Vref Byte 0 = 66 to rank1
1183 11:13:03.726399 Final RX Vref Byte 1 = 58 to rank1==
1184 11:13:03.729911 Dram Type= 6, Freq= 0, CH_0, rank 0
1185 11:13:03.733797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1186 11:13:03.734290 ==
1187 11:13:03.734634 DQS Delay:
1188 11:13:03.737301 DQS0 = 0, DQS1 = 0
1189 11:13:03.737724 DQM Delay:
1190 11:13:03.740845 DQM0 = 86, DQM1 = 76
1191 11:13:03.741269 DQ Delay:
1192 11:13:03.745167 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1193 11:13:03.748924 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1194 11:13:03.749355 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =68
1195 11:13:03.752462 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1196 11:13:03.752922
1197 11:13:03.753254
1198 11:13:03.763378 [DQSOSCAuto] RK0, (LSB)MR18= 0x4527, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1199 11:13:03.763808 CH0 RK0: MR19=606, MR18=4527
1200 11:13:03.770434 CH0_RK0: MR19=0x606, MR18=0x4527, DQSOSC=392, MR23=63, INC=96, DEC=64
1201 11:13:03.771130
1202 11:13:03.773929 ----->DramcWriteLeveling(PI) begin...
1203 11:13:03.774364 ==
1204 11:13:03.777698 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 11:13:03.781396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 11:13:03.781985 ==
1207 11:13:03.785503 Write leveling (Byte 0): 32 => 32
1208 11:13:03.788725 Write leveling (Byte 1): 31 => 31
1209 11:13:03.792424 DramcWriteLeveling(PI) end<-----
1210 11:13:03.792775
1211 11:13:03.793017 ==
1212 11:13:03.796085 Dram Type= 6, Freq= 0, CH_0, rank 1
1213 11:13:03.799367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1214 11:13:03.799732 ==
1215 11:13:03.843984 [Gating] SW mode calibration
1216 11:13:03.845013 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1217 11:13:03.845552 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1218 11:13:03.846083 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1219 11:13:03.846605 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 11:13:03.847206 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1221 11:13:03.847755 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:13:03.848277 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:13:03.848828 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:13:03.849342 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:13:03.887986 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:13:03.888584 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:13:03.889120 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:13:03.889552 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:13:03.889956 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:13:03.890657 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:13:03.891019 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:13:03.891413 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:13:03.891801 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:13:03.892287 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:13:03.931998 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1236 11:13:03.932523 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1237 11:13:03.932831 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1238 11:13:03.932979 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:13:03.933081 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:13:03.933721 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:13:03.934009 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:13:03.934126 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:13:03.934249 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:13:03.934349 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (1 1) (1 1)
1245 11:13:03.946230 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1246 11:13:03.946327 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 11:13:03.949937 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:13:03.952932 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:13:03.956686 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 11:13:03.960254 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 11:13:03.964100 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1252 11:13:03.967737 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
1253 11:13:03.971362 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1254 11:13:03.975084 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:13:03.982687 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:13:03.986907 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:13:03.989895 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:13:03.994357 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:13:03.997823 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1260 11:13:04.005268 0 11 8 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (0 0)
1261 11:13:04.009007 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1262 11:13:04.012451 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:13:04.016417 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:13:04.019930 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:13:04.023617 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:13:04.031346 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:13:04.034791 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:13:04.038482 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1269 11:13:04.042214 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1270 11:13:04.045748 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:13:04.053180 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:13:04.056812 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:13:04.060509 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:13:04.064139 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:13:04.067724 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:13:04.075092 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:13:04.078780 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:13:04.082338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:13:04.085962 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:13:04.089977 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:13:04.096564 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:13:04.100021 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:13:04.103129 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1284 11:13:04.109850 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1285 11:13:04.113497 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 11:13:04.116347 Total UI for P1: 0, mck2ui 16
1287 11:13:04.119880 best dqsien dly found for B0: ( 0, 14, 6)
1288 11:13:04.122848 Total UI for P1: 0, mck2ui 16
1289 11:13:04.126414 best dqsien dly found for B1: ( 0, 14, 6)
1290 11:13:04.129414 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1291 11:13:04.132961 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1292 11:13:04.133442
1293 11:13:04.136425 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1294 11:13:04.139309 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1295 11:13:04.142905 [Gating] SW calibration Done
1296 11:13:04.143417 ==
1297 11:13:04.146387 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 11:13:04.149610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 11:13:04.153066 ==
1300 11:13:04.153508 RX Vref Scan: 0
1301 11:13:04.153847
1302 11:13:04.155965 RX Vref 0 -> 0, step: 1
1303 11:13:04.156391
1304 11:13:04.159734 RX Delay -130 -> 252, step: 16
1305 11:13:04.162634 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1306 11:13:04.166221 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1307 11:13:04.169316 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1308 11:13:04.173036 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1309 11:13:04.180138 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1310 11:13:04.182981 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1311 11:13:04.186436 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1312 11:13:04.189467 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1313 11:13:04.192629 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1314 11:13:04.199153 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1315 11:13:04.202709 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1316 11:13:04.205945 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1317 11:13:04.209552 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1318 11:13:04.212856 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1319 11:13:04.219253 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1320 11:13:04.222834 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1321 11:13:04.223433 ==
1322 11:13:04.225665 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 11:13:04.229356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 11:13:04.229917 ==
1325 11:13:04.232304 DQS Delay:
1326 11:13:04.232753 DQS0 = 0, DQS1 = 0
1327 11:13:04.233088 DQM Delay:
1328 11:13:04.236155 DQM0 = 86, DQM1 = 79
1329 11:13:04.236631 DQ Delay:
1330 11:13:04.239426 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1331 11:13:04.242468 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1332 11:13:04.245992 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1333 11:13:04.249019 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1334 11:13:04.249481
1335 11:13:04.249931
1336 11:13:04.250408 ==
1337 11:13:04.252560 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 11:13:04.256160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 11:13:04.258984 ==
1340 11:13:04.259435
1341 11:13:04.259975
1342 11:13:04.260503 TX Vref Scan disable
1343 11:13:04.262414 == TX Byte 0 ==
1344 11:13:04.266147 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1345 11:13:04.269092 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1346 11:13:04.272171 == TX Byte 1 ==
1347 11:13:04.275669 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1348 11:13:04.282540 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1349 11:13:04.282955 ==
1350 11:13:04.285922 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 11:13:04.289061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 11:13:04.289517 ==
1353 11:13:04.301509 TX Vref=22, minBit 8, minWin=27, winSum=443
1354 11:13:04.304751 TX Vref=24, minBit 11, minWin=27, winSum=448
1355 11:13:04.307854 TX Vref=26, minBit 9, minWin=27, winSum=446
1356 11:13:04.311510 TX Vref=28, minBit 9, minWin=27, winSum=446
1357 11:13:04.314610 TX Vref=30, minBit 8, minWin=27, winSum=448
1358 11:13:04.321327 TX Vref=32, minBit 8, minWin=27, winSum=442
1359 11:13:04.324062 [TxChooseVref] Worse bit 11, Min win 27, Win sum 448, Final Vref 24
1360 11:13:04.324143
1361 11:13:04.327520 Final TX Range 1 Vref 24
1362 11:13:04.327602
1363 11:13:04.327665 ==
1364 11:13:04.331198 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 11:13:04.334008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 11:13:04.337630 ==
1367 11:13:04.337710
1368 11:13:04.337773
1369 11:13:04.337832 TX Vref Scan disable
1370 11:13:04.341149 == TX Byte 0 ==
1371 11:13:04.344789 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1372 11:13:04.347637 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1373 11:13:04.351281 == TX Byte 1 ==
1374 11:13:04.354237 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1375 11:13:04.360856 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1376 11:13:04.360991
1377 11:13:04.361083 [DATLAT]
1378 11:13:04.361166 Freq=800, CH0 RK1
1379 11:13:04.361246
1380 11:13:04.364279 DATLAT Default: 0xa
1381 11:13:04.364392 0, 0xFFFF, sum = 0
1382 11:13:04.367881 1, 0xFFFF, sum = 0
1383 11:13:04.368005 2, 0xFFFF, sum = 0
1384 11:13:04.371129 3, 0xFFFF, sum = 0
1385 11:13:04.371274 4, 0xFFFF, sum = 0
1386 11:13:04.374600 5, 0xFFFF, sum = 0
1387 11:13:04.377787 6, 0xFFFF, sum = 0
1388 11:13:04.377939 7, 0xFFFF, sum = 0
1389 11:13:04.380900 8, 0xFFFF, sum = 0
1390 11:13:04.381072 9, 0x0, sum = 1
1391 11:13:04.381232 10, 0x0, sum = 2
1392 11:13:04.384409 11, 0x0, sum = 3
1393 11:13:04.384586 12, 0x0, sum = 4
1394 11:13:04.388337 best_step = 10
1395 11:13:04.388822
1396 11:13:04.389141 ==
1397 11:13:04.391377 Dram Type= 6, Freq= 0, CH_0, rank 1
1398 11:13:04.394434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 11:13:04.394827 ==
1400 11:13:04.398153 RX Vref Scan: 0
1401 11:13:04.398547
1402 11:13:04.399063 RX Vref 0 -> 0, step: 1
1403 11:13:04.399383
1404 11:13:04.401015 RX Delay -95 -> 252, step: 8
1405 11:13:04.407981 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1406 11:13:04.411352 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1407 11:13:04.414543 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1408 11:13:04.418086 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1409 11:13:04.421142 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1410 11:13:04.427890 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1411 11:13:04.431404 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1412 11:13:04.434518 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1413 11:13:04.437897 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1414 11:13:04.441511 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1415 11:13:04.448237 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1416 11:13:04.451279 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1417 11:13:04.454640 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1418 11:13:04.458144 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1419 11:13:04.464621 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1420 11:13:04.467806 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1421 11:13:04.468234 ==
1422 11:13:04.471197 Dram Type= 6, Freq= 0, CH_0, rank 1
1423 11:13:04.474759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 11:13:04.475187 ==
1425 11:13:04.475583 DQS Delay:
1426 11:13:04.477784 DQS0 = 0, DQS1 = 0
1427 11:13:04.478216 DQM Delay:
1428 11:13:04.481006 DQM0 = 86, DQM1 = 77
1429 11:13:04.481428 DQ Delay:
1430 11:13:04.484613 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1431 11:13:04.487833 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1432 11:13:04.490789 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1433 11:13:04.494211 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1434 11:13:04.494651
1435 11:13:04.494987
1436 11:13:04.504015 [DQSOSCAuto] RK1, (LSB)MR18= 0x4208, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1437 11:13:04.504588 CH0 RK1: MR19=606, MR18=4208
1438 11:13:04.510528 CH0_RK1: MR19=0x606, MR18=0x4208, DQSOSC=393, MR23=63, INC=95, DEC=63
1439 11:13:04.514369 [RxdqsGatingPostProcess] freq 800
1440 11:13:04.520433 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1441 11:13:04.524022 Pre-setting of DQS Precalculation
1442 11:13:04.527146 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1443 11:13:04.527572 ==
1444 11:13:04.530716 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 11:13:04.537321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 11:13:04.537841 ==
1447 11:13:04.540799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1448 11:13:04.547305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1449 11:13:04.556252 [CA 0] Center 36 (6~67) winsize 62
1450 11:13:04.559744 [CA 1] Center 36 (6~67) winsize 62
1451 11:13:04.562899 [CA 2] Center 34 (4~65) winsize 62
1452 11:13:04.566424 [CA 3] Center 34 (3~65) winsize 63
1453 11:13:04.569418 [CA 4] Center 34 (4~65) winsize 62
1454 11:13:04.572968 [CA 5] Center 34 (3~65) winsize 63
1455 11:13:04.573370
1456 11:13:04.576380 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1457 11:13:04.576898
1458 11:13:04.579897 [CATrainingPosCal] consider 1 rank data
1459 11:13:04.582924 u2DelayCellTimex100 = 270/100 ps
1460 11:13:04.585998 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1461 11:13:04.593201 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 11:13:04.596251 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 11:13:04.599302 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1464 11:13:04.602768 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 11:13:04.605992 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1466 11:13:04.606379
1467 11:13:04.609418 CA PerBit enable=1, Macro0, CA PI delay=34
1468 11:13:04.609799
1469 11:13:04.612929 [CBTSetCACLKResult] CA Dly = 34
1470 11:13:04.613398 CS Dly: 4 (0~35)
1471 11:13:04.615789 ==
1472 11:13:04.619358 Dram Type= 6, Freq= 0, CH_1, rank 1
1473 11:13:04.622797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 11:13:04.623417 ==
1475 11:13:04.625812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1476 11:13:04.632628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1477 11:13:04.642740 [CA 0] Center 36 (6~67) winsize 62
1478 11:13:04.646160 [CA 1] Center 37 (6~68) winsize 63
1479 11:13:04.648931 [CA 2] Center 34 (4~65) winsize 62
1480 11:13:04.652657 [CA 3] Center 34 (3~65) winsize 63
1481 11:13:04.656066 [CA 4] Center 34 (4~65) winsize 62
1482 11:13:04.658986 [CA 5] Center 34 (4~64) winsize 61
1483 11:13:04.659418
1484 11:13:04.662665 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1485 11:13:04.663098
1486 11:13:04.666163 [CATrainingPosCal] consider 2 rank data
1487 11:13:04.668838 u2DelayCellTimex100 = 270/100 ps
1488 11:13:04.672472 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1489 11:13:04.679108 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1490 11:13:04.682342 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1491 11:13:04.685933 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1492 11:13:04.689019 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1493 11:13:04.692144 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1494 11:13:04.692861
1495 11:13:04.695927 CA PerBit enable=1, Macro0, CA PI delay=34
1496 11:13:04.696358
1497 11:13:04.698724 [CBTSetCACLKResult] CA Dly = 34
1498 11:13:04.699168 CS Dly: 5 (0~37)
1499 11:13:04.702351
1500 11:13:04.705576 ----->DramcWriteLeveling(PI) begin...
1501 11:13:04.706014 ==
1502 11:13:04.709067 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 11:13:04.711970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 11:13:04.712429 ==
1505 11:13:04.715799 Write leveling (Byte 0): 26 => 26
1506 11:13:04.718645 Write leveling (Byte 1): 29 => 29
1507 11:13:04.722015 DramcWriteLeveling(PI) end<-----
1508 11:13:04.722441
1509 11:13:04.722775 ==
1510 11:13:04.725296 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 11:13:04.729015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1512 11:13:04.729443 ==
1513 11:13:04.732081 [Gating] SW mode calibration
1514 11:13:04.738645 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1515 11:13:04.745317 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1516 11:13:04.748868 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1517 11:13:04.752325 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1518 11:13:04.758319 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1519 11:13:04.761763 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:13:04.765359 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:13:04.772025 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:13:04.775405 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:13:04.778504 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:13:04.785264 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:13:04.788355 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:13:04.791270 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:13:04.798105 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:13:04.801786 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:13:04.804882 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:13:04.811469 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:13:04.814888 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:13:04.818223 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:13:04.824678 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1534 11:13:04.828017 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:13:04.831358 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:13:04.834899 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:13:04.841197 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:13:04.844855 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:13:04.847862 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:13:04.854622 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:13:04.857990 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:13:04.861607 0 9 8 | B1->B0 | 2d2d 3131 | 0 1 | (0 0) (0 0)
1543 11:13:04.868062 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 11:13:04.870871 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 11:13:04.874360 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:13:04.880880 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:13:04.884507 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 11:13:04.887402 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 11:13:04.894654 0 10 4 | B1->B0 | 3333 3232 | 0 0 | (0 1) (0 0)
1550 11:13:04.897579 0 10 8 | B1->B0 | 2a2a 2626 | 0 0 | (1 1) (1 1)
1551 11:13:04.900961 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:13:04.907792 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:13:04.911173 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:13:04.914181 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:13:04.920664 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:13:04.924296 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:13:04.927200 0 11 4 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
1558 11:13:04.933942 0 11 8 | B1->B0 | 3b3b 3d3d | 0 0 | (0 0) (0 0)
1559 11:13:04.936965 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:13:04.940790 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 11:13:04.947009 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:13:04.950647 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:13:04.953665 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:13:04.960663 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1565 11:13:04.963532 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1566 11:13:04.967206 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:13:04.973739 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:13:04.977276 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:13:04.980297 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:13:04.987104 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:13:04.990244 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:13:04.993640 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:13:05.000578 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:13:05.003156 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:13:05.006693 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:13:05.013451 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:13:05.016789 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:13:05.020246 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:13:05.026505 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:13:05.030170 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:13:05.033125 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:13:05.036488 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 11:13:05.039928 Total UI for P1: 0, mck2ui 16
1584 11:13:05.043051 best dqsien dly found for B0: ( 0, 14, 6)
1585 11:13:05.046853 Total UI for P1: 0, mck2ui 16
1586 11:13:05.050265 best dqsien dly found for B1: ( 0, 14, 6)
1587 11:13:05.053307 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1588 11:13:05.056853 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1589 11:13:05.060197
1590 11:13:05.063592 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1591 11:13:05.066603 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1592 11:13:05.069934 [Gating] SW calibration Done
1593 11:13:05.070359 ==
1594 11:13:05.073480 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 11:13:05.076553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 11:13:05.076984 ==
1597 11:13:05.077321 RX Vref Scan: 0
1598 11:13:05.077633
1599 11:13:05.079579 RX Vref 0 -> 0, step: 1
1600 11:13:05.080005
1601 11:13:05.082933 RX Delay -130 -> 252, step: 16
1602 11:13:05.086358 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1603 11:13:05.090110 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1604 11:13:05.096505 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1605 11:13:05.100212 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1606 11:13:05.102973 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1607 11:13:05.106167 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1608 11:13:05.109816 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1609 11:13:05.116421 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1610 11:13:05.119336 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1611 11:13:05.123044 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1612 11:13:05.126201 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1613 11:13:05.129764 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1614 11:13:05.136421 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1615 11:13:05.139327 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1616 11:13:05.143008 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1617 11:13:05.145972 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1618 11:13:05.149646 ==
1619 11:13:05.150142 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 11:13:05.156230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 11:13:05.156791 ==
1622 11:13:05.157184 DQS Delay:
1623 11:13:05.159295 DQS0 = 0, DQS1 = 0
1624 11:13:05.159766 DQM Delay:
1625 11:13:05.162808 DQM0 = 88, DQM1 = 78
1626 11:13:05.163455 DQ Delay:
1627 11:13:05.166423 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1628 11:13:05.169916 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1629 11:13:05.172637 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1630 11:13:05.175770 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1631 11:13:05.176204
1632 11:13:05.176589
1633 11:13:05.176919 ==
1634 11:13:05.179140 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 11:13:05.182806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 11:13:05.183332 ==
1637 11:13:05.183674
1638 11:13:05.184076
1639 11:13:05.186119 TX Vref Scan disable
1640 11:13:05.189513 == TX Byte 0 ==
1641 11:13:05.193224 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1642 11:13:05.196247 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1643 11:13:05.199156 == TX Byte 1 ==
1644 11:13:05.202631 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1645 11:13:05.205479 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1646 11:13:05.205952 ==
1647 11:13:05.209278 Dram Type= 6, Freq= 0, CH_1, rank 0
1648 11:13:05.212317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1649 11:13:05.216006 ==
1650 11:13:05.227424 TX Vref=22, minBit 15, minWin=26, winSum=440
1651 11:13:05.230860 TX Vref=24, minBit 9, minWin=27, winSum=447
1652 11:13:05.234128 TX Vref=26, minBit 9, minWin=27, winSum=448
1653 11:13:05.237148 TX Vref=28, minBit 9, minWin=27, winSum=446
1654 11:13:05.240708 TX Vref=30, minBit 10, minWin=27, winSum=448
1655 11:13:05.247145 TX Vref=32, minBit 8, minWin=27, winSum=445
1656 11:13:05.250787 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 26
1657 11:13:05.251217
1658 11:13:05.253995 Final TX Range 1 Vref 26
1659 11:13:05.254518
1660 11:13:05.254854 ==
1661 11:13:05.257321 Dram Type= 6, Freq= 0, CH_1, rank 0
1662 11:13:05.260591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1663 11:13:05.261022 ==
1664 11:13:05.264182
1665 11:13:05.264645
1666 11:13:05.264985 TX Vref Scan disable
1667 11:13:05.267274 == TX Byte 0 ==
1668 11:13:05.270842 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1669 11:13:05.273998 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1670 11:13:05.277133 == TX Byte 1 ==
1671 11:13:05.280750 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1672 11:13:05.287255 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1673 11:13:05.287742
1674 11:13:05.288081 [DATLAT]
1675 11:13:05.288397 Freq=800, CH1 RK0
1676 11:13:05.288757
1677 11:13:05.290287 DATLAT Default: 0xa
1678 11:13:05.290865 0, 0xFFFF, sum = 0
1679 11:13:05.293708 1, 0xFFFF, sum = 0
1680 11:13:05.296968 2, 0xFFFF, sum = 0
1681 11:13:05.297400 3, 0xFFFF, sum = 0
1682 11:13:05.300696 4, 0xFFFF, sum = 0
1683 11:13:05.301129 5, 0xFFFF, sum = 0
1684 11:13:05.303870 6, 0xFFFF, sum = 0
1685 11:13:05.304348 7, 0xFFFF, sum = 0
1686 11:13:05.306750 8, 0xFFFF, sum = 0
1687 11:13:05.307245 9, 0x0, sum = 1
1688 11:13:05.310151 10, 0x0, sum = 2
1689 11:13:05.310719 11, 0x0, sum = 3
1690 11:13:05.313399 12, 0x0, sum = 4
1691 11:13:05.313828 best_step = 10
1692 11:13:05.314212
1693 11:13:05.314532 ==
1694 11:13:05.316922 Dram Type= 6, Freq= 0, CH_1, rank 0
1695 11:13:05.319959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1696 11:13:05.320432 ==
1697 11:13:05.323502 RX Vref Scan: 1
1698 11:13:05.323919
1699 11:13:05.327116 Set Vref Range= 32 -> 127
1700 11:13:05.327560
1701 11:13:05.327891 RX Vref 32 -> 127, step: 1
1702 11:13:05.328199
1703 11:13:05.330294 RX Delay -95 -> 252, step: 8
1704 11:13:05.330725
1705 11:13:05.333349 Set Vref, RX VrefLevel [Byte0]: 32
1706 11:13:05.336963 [Byte1]: 32
1707 11:13:05.339944
1708 11:13:05.340437 Set Vref, RX VrefLevel [Byte0]: 33
1709 11:13:05.343528 [Byte1]: 33
1710 11:13:05.347648
1711 11:13:05.348137 Set Vref, RX VrefLevel [Byte0]: 34
1712 11:13:05.350804 [Byte1]: 34
1713 11:13:05.355471
1714 11:13:05.355956 Set Vref, RX VrefLevel [Byte0]: 35
1715 11:13:05.358475 [Byte1]: 35
1716 11:13:05.362813
1717 11:13:05.363290 Set Vref, RX VrefLevel [Byte0]: 36
1718 11:13:05.365811 [Byte1]: 36
1719 11:13:05.370865
1720 11:13:05.371345 Set Vref, RX VrefLevel [Byte0]: 37
1721 11:13:05.373723 [Byte1]: 37
1722 11:13:05.378325
1723 11:13:05.378756 Set Vref, RX VrefLevel [Byte0]: 38
1724 11:13:05.381284 [Byte1]: 38
1725 11:13:05.385667
1726 11:13:05.386088 Set Vref, RX VrefLevel [Byte0]: 39
1727 11:13:05.388957 [Byte1]: 39
1728 11:13:05.393105
1729 11:13:05.393525 Set Vref, RX VrefLevel [Byte0]: 40
1730 11:13:05.396243 [Byte1]: 40
1731 11:13:05.400622
1732 11:13:05.401042 Set Vref, RX VrefLevel [Byte0]: 41
1733 11:13:05.404248 [Byte1]: 41
1734 11:13:05.408488
1735 11:13:05.408950 Set Vref, RX VrefLevel [Byte0]: 42
1736 11:13:05.411443 [Byte1]: 42
1737 11:13:05.416207
1738 11:13:05.416660 Set Vref, RX VrefLevel [Byte0]: 43
1739 11:13:05.419247 [Byte1]: 43
1740 11:13:05.423432
1741 11:13:05.423847 Set Vref, RX VrefLevel [Byte0]: 44
1742 11:13:05.426677 [Byte1]: 44
1743 11:13:05.430837
1744 11:13:05.431253 Set Vref, RX VrefLevel [Byte0]: 45
1745 11:13:05.434453 [Byte1]: 45
1746 11:13:05.438730
1747 11:13:05.439181 Set Vref, RX VrefLevel [Byte0]: 46
1748 11:13:05.442204 [Byte1]: 46
1749 11:13:05.446397
1750 11:13:05.446823 Set Vref, RX VrefLevel [Byte0]: 47
1751 11:13:05.449447 [Byte1]: 47
1752 11:13:05.453954
1753 11:13:05.454378 Set Vref, RX VrefLevel [Byte0]: 48
1754 11:13:05.457361 [Byte1]: 48
1755 11:13:05.461486
1756 11:13:05.461906 Set Vref, RX VrefLevel [Byte0]: 49
1757 11:13:05.465044 [Byte1]: 49
1758 11:13:05.469327
1759 11:13:05.469749 Set Vref, RX VrefLevel [Byte0]: 50
1760 11:13:05.472426 [Byte1]: 50
1761 11:13:05.477064
1762 11:13:05.477488 Set Vref, RX VrefLevel [Byte0]: 51
1763 11:13:05.479825 [Byte1]: 51
1764 11:13:05.484621
1765 11:13:05.485052 Set Vref, RX VrefLevel [Byte0]: 52
1766 11:13:05.487549 [Byte1]: 52
1767 11:13:05.492160
1768 11:13:05.492729 Set Vref, RX VrefLevel [Byte0]: 53
1769 11:13:05.495026 [Byte1]: 53
1770 11:13:05.499811
1771 11:13:05.500241 Set Vref, RX VrefLevel [Byte0]: 54
1772 11:13:05.502703 [Byte1]: 54
1773 11:13:05.507619
1774 11:13:05.508200 Set Vref, RX VrefLevel [Byte0]: 55
1775 11:13:05.510354 [Byte1]: 55
1776 11:13:05.514562
1777 11:13:05.515008 Set Vref, RX VrefLevel [Byte0]: 56
1778 11:13:05.518326 [Byte1]: 56
1779 11:13:05.522559
1780 11:13:05.522985 Set Vref, RX VrefLevel [Byte0]: 57
1781 11:13:05.525741 [Byte1]: 57
1782 11:13:05.529877
1783 11:13:05.530307 Set Vref, RX VrefLevel [Byte0]: 58
1784 11:13:05.533589 [Byte1]: 58
1785 11:13:05.538068
1786 11:13:05.538607 Set Vref, RX VrefLevel [Byte0]: 59
1787 11:13:05.540625 [Byte1]: 59
1788 11:13:05.544949
1789 11:13:05.545398 Set Vref, RX VrefLevel [Byte0]: 60
1790 11:13:05.548642 [Byte1]: 60
1791 11:13:05.552918
1792 11:13:05.553460 Set Vref, RX VrefLevel [Byte0]: 61
1793 11:13:05.555939 [Byte1]: 61
1794 11:13:05.560265
1795 11:13:05.560770 Set Vref, RX VrefLevel [Byte0]: 62
1796 11:13:05.563671 [Byte1]: 62
1797 11:13:05.568063
1798 11:13:05.568686 Set Vref, RX VrefLevel [Byte0]: 63
1799 11:13:05.571146 [Byte1]: 63
1800 11:13:05.575420
1801 11:13:05.575905 Set Vref, RX VrefLevel [Byte0]: 64
1802 11:13:05.578852 [Byte1]: 64
1803 11:13:05.582999
1804 11:13:05.583559 Set Vref, RX VrefLevel [Byte0]: 65
1805 11:13:05.586620 [Byte1]: 65
1806 11:13:05.590502
1807 11:13:05.590928 Set Vref, RX VrefLevel [Byte0]: 66
1808 11:13:05.594116 [Byte1]: 66
1809 11:13:05.598379
1810 11:13:05.598836 Set Vref, RX VrefLevel [Byte0]: 67
1811 11:13:05.601713 [Byte1]: 67
1812 11:13:05.606046
1813 11:13:05.606473 Set Vref, RX VrefLevel [Byte0]: 68
1814 11:13:05.609632 [Byte1]: 68
1815 11:13:05.613701
1816 11:13:05.614222 Set Vref, RX VrefLevel [Byte0]: 69
1817 11:13:05.617294 [Byte1]: 69
1818 11:13:05.621275
1819 11:13:05.621705 Set Vref, RX VrefLevel [Byte0]: 70
1820 11:13:05.624273 [Byte1]: 70
1821 11:13:05.628666
1822 11:13:05.629190 Set Vref, RX VrefLevel [Byte0]: 71
1823 11:13:05.632288 [Byte1]: 71
1824 11:13:05.636508
1825 11:13:05.636986 Set Vref, RX VrefLevel [Byte0]: 72
1826 11:13:05.639540 [Byte1]: 72
1827 11:13:05.643627
1828 11:13:05.644204 Set Vref, RX VrefLevel [Byte0]: 73
1829 11:13:05.647296 [Byte1]: 73
1830 11:13:05.651312
1831 11:13:05.651883 Set Vref, RX VrefLevel [Byte0]: 74
1832 11:13:05.654643 [Byte1]: 74
1833 11:13:05.659721
1834 11:13:05.660242 Set Vref, RX VrefLevel [Byte0]: 75
1835 11:13:05.662732 [Byte1]: 75
1836 11:13:05.666665
1837 11:13:05.667095 Final RX Vref Byte 0 = 58 to rank0
1838 11:13:05.670760 Final RX Vref Byte 1 = 63 to rank0
1839 11:13:05.673738 Final RX Vref Byte 0 = 58 to rank1
1840 11:13:05.677414 Final RX Vref Byte 1 = 63 to rank1==
1841 11:13:05.680437 Dram Type= 6, Freq= 0, CH_1, rank 0
1842 11:13:05.683691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1843 11:13:05.686998 ==
1844 11:13:05.687517 DQS Delay:
1845 11:13:05.687859 DQS0 = 0, DQS1 = 0
1846 11:13:05.689904 DQM Delay:
1847 11:13:05.690364 DQM0 = 86, DQM1 = 79
1848 11:13:05.693426 DQ Delay:
1849 11:13:05.696746 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1850 11:13:05.700204 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1851 11:13:05.700767 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1852 11:13:05.707031 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1853 11:13:05.707464
1854 11:13:05.707800
1855 11:13:05.713422 [DQSOSCAuto] RK0, (LSB)MR18= 0x3420, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1856 11:13:05.716588 CH1 RK0: MR19=606, MR18=3420
1857 11:13:05.723088 CH1_RK0: MR19=0x606, MR18=0x3420, DQSOSC=396, MR23=63, INC=94, DEC=62
1858 11:13:05.723665
1859 11:13:05.726585 ----->DramcWriteLeveling(PI) begin...
1860 11:13:05.727076 ==
1861 11:13:05.729841 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 11:13:05.733157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 11:13:05.733613 ==
1864 11:13:05.736665 Write leveling (Byte 0): 26 => 26
1865 11:13:05.739879 Write leveling (Byte 1): 31 => 31
1866 11:13:05.743544 DramcWriteLeveling(PI) end<-----
1867 11:13:05.743975
1868 11:13:05.744310 ==
1869 11:13:05.746551 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 11:13:05.749889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1871 11:13:05.750514 ==
1872 11:13:05.752973 [Gating] SW mode calibration
1873 11:13:05.759612 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1874 11:13:05.766284 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1875 11:13:05.769923 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1876 11:13:05.772953 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1877 11:13:05.779771 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1878 11:13:05.783217 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:13:05.786129 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:13:05.792736 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:13:05.796149 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:13:05.799548 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:13:05.806511 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:13:05.809324 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:13:05.812740 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:13:05.819242 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:13:05.822665 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:13:05.826212 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:13:05.832761 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:13:05.836221 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:13:05.839457 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:13:05.846312 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1893 11:13:05.849729 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:13:05.852610 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:13:05.859412 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:13:05.862627 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:13:05.866237 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:13:05.872836 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:13:05.875883 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:13:05.879192 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:13:05.886257 0 9 8 | B1->B0 | 3131 2525 | 0 1 | (0 0) (1 1)
1902 11:13:05.889122 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 11:13:05.892936 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 11:13:05.895908 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 11:13:05.902728 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 11:13:05.905774 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 11:13:05.909100 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 11:13:05.916023 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 11:13:05.919085 0 10 8 | B1->B0 | 2525 2929 | 0 0 | (0 0) (0 0)
1910 11:13:05.922483 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:13:05.929594 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:13:05.932476 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 11:13:05.935517 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 11:13:05.942562 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 11:13:05.945477 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 11:13:05.949250 0 11 4 | B1->B0 | 2c2c 2626 | 0 1 | (0 0) (0 0)
1917 11:13:05.955242 0 11 8 | B1->B0 | 3c3c 3939 | 0 1 | (0 0) (0 0)
1918 11:13:05.959095 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 11:13:05.962312 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 11:13:05.969067 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 11:13:05.972314 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 11:13:05.975300 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 11:13:05.982467 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 11:13:05.985366 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1925 11:13:05.988925 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1926 11:13:05.995660 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:13:05.998855 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:13:06.001926 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:13:06.008909 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:13:06.012190 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:13:06.015601 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:13:06.022577 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:13:06.025537 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:13:06.029082 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:13:06.032348 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:13:06.039074 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:13:06.042364 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:13:06.045149 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:13:06.051898 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:13:06.055425 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:13:06.058632 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1942 11:13:06.065175 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 11:13:06.068120 Total UI for P1: 0, mck2ui 16
1944 11:13:06.072106 best dqsien dly found for B0: ( 0, 14, 8)
1945 11:13:06.075344 Total UI for P1: 0, mck2ui 16
1946 11:13:06.078683 best dqsien dly found for B1: ( 0, 14, 8)
1947 11:13:06.081787 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1948 11:13:06.085251 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1949 11:13:06.085737
1950 11:13:06.088220 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1951 11:13:06.091849 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1952 11:13:06.094761 [Gating] SW calibration Done
1953 11:13:06.095326 ==
1954 11:13:06.098589 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 11:13:06.101651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 11:13:06.102108 ==
1957 11:13:06.104651 RX Vref Scan: 0
1958 11:13:06.105156
1959 11:13:06.108198 RX Vref 0 -> 0, step: 1
1960 11:13:06.108775
1961 11:13:06.109115 RX Delay -130 -> 252, step: 16
1962 11:13:06.114627 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1963 11:13:06.118027 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1964 11:13:06.121594 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1965 11:13:06.124563 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1966 11:13:06.128342 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1967 11:13:06.134304 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1968 11:13:06.138013 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1969 11:13:06.140943 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1970 11:13:06.144492 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1971 11:13:06.151028 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1972 11:13:06.154642 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1973 11:13:06.157662 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1974 11:13:06.161295 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1975 11:13:06.164484 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1976 11:13:06.170942 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1977 11:13:06.174075 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1978 11:13:06.174503 ==
1979 11:13:06.177114 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 11:13:06.180660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 11:13:06.181090 ==
1982 11:13:06.184332 DQS Delay:
1983 11:13:06.184889 DQS0 = 0, DQS1 = 0
1984 11:13:06.185256 DQM Delay:
1985 11:13:06.187530 DQM0 = 88, DQM1 = 78
1986 11:13:06.188021 DQ Delay:
1987 11:13:06.190547 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1988 11:13:06.194153 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1989 11:13:06.197210 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =69
1990 11:13:06.200836 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1991 11:13:06.201415
1992 11:13:06.201866
1993 11:13:06.202200 ==
1994 11:13:06.203876 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 11:13:06.210479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 11:13:06.211042 ==
1997 11:13:06.211582
1998 11:13:06.212099
1999 11:13:06.213550 TX Vref Scan disable
2000 11:13:06.214130 == TX Byte 0 ==
2001 11:13:06.217021 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2002 11:13:06.223433 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2003 11:13:06.224030 == TX Byte 1 ==
2004 11:13:06.226999 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2005 11:13:06.233470 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2006 11:13:06.234058 ==
2007 11:13:06.236796 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 11:13:06.240373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 11:13:06.240814 ==
2010 11:13:06.253961 TX Vref=22, minBit 1, minWin=27, winSum=443
2011 11:13:06.257305 TX Vref=24, minBit 8, minWin=27, winSum=451
2012 11:13:06.260399 TX Vref=26, minBit 8, minWin=27, winSum=449
2013 11:13:06.263390 TX Vref=28, minBit 8, minWin=27, winSum=451
2014 11:13:06.266979 TX Vref=30, minBit 8, minWin=27, winSum=451
2015 11:13:06.273845 TX Vref=32, minBit 8, minWin=27, winSum=450
2016 11:13:06.277012 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 24
2017 11:13:06.277446
2018 11:13:06.280700 Final TX Range 1 Vref 24
2019 11:13:06.281133
2020 11:13:06.281517 ==
2021 11:13:06.283275 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 11:13:06.287085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 11:13:06.287169 ==
2024 11:13:06.290116
2025 11:13:06.290200
2026 11:13:06.290265 TX Vref Scan disable
2027 11:13:06.293553 == TX Byte 0 ==
2028 11:13:06.296480 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2029 11:13:06.303127 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2030 11:13:06.303210 == TX Byte 1 ==
2031 11:13:06.306809 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2032 11:13:06.313390 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2033 11:13:06.313499
2034 11:13:06.313593 [DATLAT]
2035 11:13:06.313683 Freq=800, CH1 RK1
2036 11:13:06.313768
2037 11:13:06.316465 DATLAT Default: 0xa
2038 11:13:06.316575 0, 0xFFFF, sum = 0
2039 11:13:06.320477 1, 0xFFFF, sum = 0
2040 11:13:06.323416 2, 0xFFFF, sum = 0
2041 11:13:06.323513 3, 0xFFFF, sum = 0
2042 11:13:06.326819 4, 0xFFFF, sum = 0
2043 11:13:06.326957 5, 0xFFFF, sum = 0
2044 11:13:06.329820 6, 0xFFFF, sum = 0
2045 11:13:06.329937 7, 0xFFFF, sum = 0
2046 11:13:06.333259 8, 0xFFFF, sum = 0
2047 11:13:06.333378 9, 0x0, sum = 1
2048 11:13:06.336141 10, 0x0, sum = 2
2049 11:13:06.336267 11, 0x0, sum = 3
2050 11:13:06.339685 12, 0x0, sum = 4
2051 11:13:06.339867 best_step = 10
2052 11:13:06.340027
2053 11:13:06.340174 ==
2054 11:13:06.342807 Dram Type= 6, Freq= 0, CH_1, rank 1
2055 11:13:06.346331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2056 11:13:06.346495 ==
2057 11:13:06.349642 RX Vref Scan: 0
2058 11:13:06.349818
2059 11:13:06.352757 RX Vref 0 -> 0, step: 1
2060 11:13:06.352931
2061 11:13:06.353068 RX Delay -111 -> 252, step: 8
2062 11:13:06.360347 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2063 11:13:06.363653 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2064 11:13:06.367257 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2065 11:13:06.371016 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
2066 11:13:06.374133 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2067 11:13:06.380816 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2068 11:13:06.383937 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2069 11:13:06.387460 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2070 11:13:06.390400 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2071 11:13:06.394061 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2072 11:13:06.400552 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2073 11:13:06.403938 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2074 11:13:06.407081 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2075 11:13:06.410225 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2076 11:13:06.417274 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2077 11:13:06.420411 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2078 11:13:06.420911 ==
2079 11:13:06.423432 Dram Type= 6, Freq= 0, CH_1, rank 1
2080 11:13:06.426871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2081 11:13:06.427452 ==
2082 11:13:06.429973 DQS Delay:
2083 11:13:06.430409 DQS0 = 0, DQS1 = 0
2084 11:13:06.430749 DQM Delay:
2085 11:13:06.433439 DQM0 = 87, DQM1 = 78
2086 11:13:06.433972 DQ Delay:
2087 11:13:06.436840 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2088 11:13:06.439848 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2089 11:13:06.443314 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
2090 11:13:06.446932 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2091 11:13:06.447516
2092 11:13:06.448011
2093 11:13:06.456829 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2094 11:13:06.457283 CH1 RK1: MR19=606, MR18=1A13
2095 11:13:06.463441 CH1_RK1: MR19=0x606, MR18=0x1A13, DQSOSC=403, MR23=63, INC=90, DEC=60
2096 11:13:06.466935 [RxdqsGatingPostProcess] freq 800
2097 11:13:06.473618 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2098 11:13:06.476458 Pre-setting of DQS Precalculation
2099 11:13:06.480197 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2100 11:13:06.486932 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2101 11:13:06.496598 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2102 11:13:06.497039
2103 11:13:06.497373
2104 11:13:06.499525 [Calibration Summary] 1600 Mbps
2105 11:13:06.499950 CH 0, Rank 0
2106 11:13:06.503089 SW Impedance : PASS
2107 11:13:06.503514 DUTY Scan : NO K
2108 11:13:06.506810 ZQ Calibration : PASS
2109 11:13:06.509700 Jitter Meter : NO K
2110 11:13:06.510126 CBT Training : PASS
2111 11:13:06.513362 Write leveling : PASS
2112 11:13:06.516397 RX DQS gating : PASS
2113 11:13:06.516858 RX DQ/DQS(RDDQC) : PASS
2114 11:13:06.519601 TX DQ/DQS : PASS
2115 11:13:06.520031 RX DATLAT : PASS
2116 11:13:06.523486 RX DQ/DQS(Engine): PASS
2117 11:13:06.526244 TX OE : NO K
2118 11:13:06.526678 All Pass.
2119 11:13:06.527012
2120 11:13:06.527324 CH 0, Rank 1
2121 11:13:06.529823 SW Impedance : PASS
2122 11:13:06.532922 DUTY Scan : NO K
2123 11:13:06.533365 ZQ Calibration : PASS
2124 11:13:06.536419 Jitter Meter : NO K
2125 11:13:06.539407 CBT Training : PASS
2126 11:13:06.539838 Write leveling : PASS
2127 11:13:06.542895 RX DQS gating : PASS
2128 11:13:06.546603 RX DQ/DQS(RDDQC) : PASS
2129 11:13:06.547033 TX DQ/DQS : PASS
2130 11:13:06.549291 RX DATLAT : PASS
2131 11:13:06.552829 RX DQ/DQS(Engine): PASS
2132 11:13:06.553300 TX OE : NO K
2133 11:13:06.556358 All Pass.
2134 11:13:06.556819
2135 11:13:06.557156 CH 1, Rank 0
2136 11:13:06.559659 SW Impedance : PASS
2137 11:13:06.560084 DUTY Scan : NO K
2138 11:13:06.562877 ZQ Calibration : PASS
2139 11:13:06.566415 Jitter Meter : NO K
2140 11:13:06.566842 CBT Training : PASS
2141 11:13:06.569327 Write leveling : PASS
2142 11:13:06.572666 RX DQS gating : PASS
2143 11:13:06.573159 RX DQ/DQS(RDDQC) : PASS
2144 11:13:06.575765 TX DQ/DQS : PASS
2145 11:13:06.576241 RX DATLAT : PASS
2146 11:13:06.579623 RX DQ/DQS(Engine): PASS
2147 11:13:06.582289 TX OE : NO K
2148 11:13:06.582375 All Pass.
2149 11:13:06.582458
2150 11:13:06.582536 CH 1, Rank 1
2151 11:13:06.585619 SW Impedance : PASS
2152 11:13:06.589125 DUTY Scan : NO K
2153 11:13:06.589208 ZQ Calibration : PASS
2154 11:13:06.592061 Jitter Meter : NO K
2155 11:13:06.595177 CBT Training : PASS
2156 11:13:06.595260 Write leveling : PASS
2157 11:13:06.598933 RX DQS gating : PASS
2158 11:13:06.602206 RX DQ/DQS(RDDQC) : PASS
2159 11:13:06.602639 TX DQ/DQS : PASS
2160 11:13:06.606016 RX DATLAT : PASS
2161 11:13:06.608897 RX DQ/DQS(Engine): PASS
2162 11:13:06.609366 TX OE : NO K
2163 11:13:06.612320 All Pass.
2164 11:13:06.612861
2165 11:13:06.613339 DramC Write-DBI off
2166 11:13:06.616066 PER_BANK_REFRESH: Hybrid Mode
2167 11:13:06.616734 TX_TRACKING: ON
2168 11:13:06.618960 [GetDramInforAfterCalByMRR] Vendor 6.
2169 11:13:06.625346 [GetDramInforAfterCalByMRR] Revision 606.
2170 11:13:06.629195 [GetDramInforAfterCalByMRR] Revision 2 0.
2171 11:13:06.629620 MR0 0x3b3b
2172 11:13:06.629952 MR8 0x5151
2173 11:13:06.632291 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 11:13:06.632743
2175 11:13:06.635784 MR0 0x3b3b
2176 11:13:06.636220 MR8 0x5151
2177 11:13:06.638797 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 11:13:06.639241
2179 11:13:06.648798 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2180 11:13:06.652565 [FAST_K] Save calibration result to emmc
2181 11:13:06.655985 [FAST_K] Save calibration result to emmc
2182 11:13:06.658895 dram_init: config_dvfs: 1
2183 11:13:06.662290 dramc_set_vcore_voltage set vcore to 662500
2184 11:13:06.665816 Read voltage for 1200, 2
2185 11:13:06.666251 Vio18 = 0
2186 11:13:06.666643 Vcore = 662500
2187 11:13:06.668831 Vdram = 0
2188 11:13:06.669272 Vddq = 0
2189 11:13:06.669608 Vmddr = 0
2190 11:13:06.675883 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2191 11:13:06.678786 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2192 11:13:06.682315 MEM_TYPE=3, freq_sel=15
2193 11:13:06.685403 sv_algorithm_assistance_LP4_1600
2194 11:13:06.688571 ============ PULL DRAM RESETB DOWN ============
2195 11:13:06.692033 ========== PULL DRAM RESETB DOWN end =========
2196 11:13:06.698856 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2197 11:13:06.701830 ===================================
2198 11:13:06.702259 LPDDR4 DRAM CONFIGURATION
2199 11:13:06.705414 ===================================
2200 11:13:06.709002 EX_ROW_EN[0] = 0x0
2201 11:13:06.711952 EX_ROW_EN[1] = 0x0
2202 11:13:06.712413 LP4Y_EN = 0x0
2203 11:13:06.715397 WORK_FSP = 0x0
2204 11:13:06.715828 WL = 0x4
2205 11:13:06.718432 RL = 0x4
2206 11:13:06.718864 BL = 0x2
2207 11:13:06.722070 RPST = 0x0
2208 11:13:06.722555 RD_PRE = 0x0
2209 11:13:06.725121 WR_PRE = 0x1
2210 11:13:06.725549 WR_PST = 0x0
2211 11:13:06.728888 DBI_WR = 0x0
2212 11:13:06.729476 DBI_RD = 0x0
2213 11:13:06.731958 OTF = 0x1
2214 11:13:06.734966 ===================================
2215 11:13:06.738950 ===================================
2216 11:13:06.739480 ANA top config
2217 11:13:06.741959 ===================================
2218 11:13:06.745262 DLL_ASYNC_EN = 0
2219 11:13:06.748147 ALL_SLAVE_EN = 0
2220 11:13:06.751542 NEW_RANK_MODE = 1
2221 11:13:06.751975 DLL_IDLE_MODE = 1
2222 11:13:06.754945 LP45_APHY_COMB_EN = 1
2223 11:13:06.758530 TX_ODT_DIS = 1
2224 11:13:06.761398 NEW_8X_MODE = 1
2225 11:13:06.764735 ===================================
2226 11:13:06.768199 ===================================
2227 11:13:06.771686 data_rate = 2400
2228 11:13:06.772112 CKR = 1
2229 11:13:06.774629 DQ_P2S_RATIO = 8
2230 11:13:06.778167 ===================================
2231 11:13:06.781816 CA_P2S_RATIO = 8
2232 11:13:06.784728 DQ_CA_OPEN = 0
2233 11:13:06.788166 DQ_SEMI_OPEN = 0
2234 11:13:06.791808 CA_SEMI_OPEN = 0
2235 11:13:06.792234 CA_FULL_RATE = 0
2236 11:13:06.794812 DQ_CKDIV4_EN = 0
2237 11:13:06.797774 CA_CKDIV4_EN = 0
2238 11:13:06.801631 CA_PREDIV_EN = 0
2239 11:13:06.804642 PH8_DLY = 17
2240 11:13:06.808294 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2241 11:13:06.808756 DQ_AAMCK_DIV = 4
2242 11:13:06.811316 CA_AAMCK_DIV = 4
2243 11:13:06.815070 CA_ADMCK_DIV = 4
2244 11:13:06.818426 DQ_TRACK_CA_EN = 0
2245 11:13:06.821250 CA_PICK = 1200
2246 11:13:06.824634 CA_MCKIO = 1200
2247 11:13:06.827657 MCKIO_SEMI = 0
2248 11:13:06.831343 PLL_FREQ = 2366
2249 11:13:06.831811 DQ_UI_PI_RATIO = 32
2250 11:13:06.834313 CA_UI_PI_RATIO = 0
2251 11:13:06.838091 ===================================
2252 11:13:06.840983 ===================================
2253 11:13:06.844179 memory_type:LPDDR4
2254 11:13:06.848042 GP_NUM : 10
2255 11:13:06.848621 SRAM_EN : 1
2256 11:13:06.851225 MD32_EN : 0
2257 11:13:06.854578 ===================================
2258 11:13:06.855183 [ANA_INIT] >>>>>>>>>>>>>>
2259 11:13:06.858071 <<<<<< [CONFIGURE PHASE]: ANA_TX
2260 11:13:06.861144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2261 11:13:06.864612 ===================================
2262 11:13:06.867705 data_rate = 2400,PCW = 0X5b00
2263 11:13:06.870964 ===================================
2264 11:13:06.874371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2265 11:13:06.881022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2266 11:13:06.887466 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2267 11:13:06.891238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2268 11:13:06.894594 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2269 11:13:06.897665 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2270 11:13:06.901210 [ANA_INIT] flow start
2271 11:13:06.901630 [ANA_INIT] PLL >>>>>>>>
2272 11:13:06.904185 [ANA_INIT] PLL <<<<<<<<
2273 11:13:06.907948 [ANA_INIT] MIDPI >>>>>>>>
2274 11:13:06.908367 [ANA_INIT] MIDPI <<<<<<<<
2275 11:13:06.910765 [ANA_INIT] DLL >>>>>>>>
2276 11:13:06.914639 [ANA_INIT] DLL <<<<<<<<
2277 11:13:06.915170 [ANA_INIT] flow end
2278 11:13:06.920952 ============ LP4 DIFF to SE enter ============
2279 11:13:06.924124 ============ LP4 DIFF to SE exit ============
2280 11:13:06.924602 [ANA_INIT] <<<<<<<<<<<<<
2281 11:13:06.927405 [Flow] Enable top DCM control >>>>>
2282 11:13:06.930991 [Flow] Enable top DCM control <<<<<
2283 11:13:06.934592 Enable DLL master slave shuffle
2284 11:13:06.941088 ==============================================================
2285 11:13:06.944270 Gating Mode config
2286 11:13:06.947957 ==============================================================
2287 11:13:06.951077 Config description:
2288 11:13:06.961105 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2289 11:13:06.967688 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2290 11:13:06.970958 SELPH_MODE 0: By rank 1: By Phase
2291 11:13:06.977669 ==============================================================
2292 11:13:06.981009 GAT_TRACK_EN = 1
2293 11:13:06.984609 RX_GATING_MODE = 2
2294 11:13:06.987516 RX_GATING_TRACK_MODE = 2
2295 11:13:06.987952 SELPH_MODE = 1
2296 11:13:06.990508 PICG_EARLY_EN = 1
2297 11:13:06.994277 VALID_LAT_VALUE = 1
2298 11:13:07.000979 ==============================================================
2299 11:13:07.003815 Enter into Gating configuration >>>>
2300 11:13:07.007469 Exit from Gating configuration <<<<
2301 11:13:07.010621 Enter into DVFS_PRE_config >>>>>
2302 11:13:07.020374 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2303 11:13:07.023292 Exit from DVFS_PRE_config <<<<<
2304 11:13:07.027200 Enter into PICG configuration >>>>
2305 11:13:07.030228 Exit from PICG configuration <<<<
2306 11:13:07.033697 [RX_INPUT] configuration >>>>>
2307 11:13:07.037020 [RX_INPUT] configuration <<<<<
2308 11:13:07.040742 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2309 11:13:07.047327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2310 11:13:07.053258 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2311 11:13:07.060493 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2312 11:13:07.066951 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2313 11:13:07.069883 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2314 11:13:07.076867 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2315 11:13:07.080148 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2316 11:13:07.083248 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2317 11:13:07.086552 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2318 11:13:07.093679 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2319 11:13:07.096639 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2320 11:13:07.100231 ===================================
2321 11:13:07.103292 LPDDR4 DRAM CONFIGURATION
2322 11:13:07.106905 ===================================
2323 11:13:07.107331 EX_ROW_EN[0] = 0x0
2324 11:13:07.109935 EX_ROW_EN[1] = 0x0
2325 11:13:07.110360 LP4Y_EN = 0x0
2326 11:13:07.113646 WORK_FSP = 0x0
2327 11:13:07.114070 WL = 0x4
2328 11:13:07.116644 RL = 0x4
2329 11:13:07.117068 BL = 0x2
2330 11:13:07.120288 RPST = 0x0
2331 11:13:07.120780 RD_PRE = 0x0
2332 11:13:07.123237 WR_PRE = 0x1
2333 11:13:07.123660 WR_PST = 0x0
2334 11:13:07.126183 DBI_WR = 0x0
2335 11:13:07.130044 DBI_RD = 0x0
2336 11:13:07.130468 OTF = 0x1
2337 11:13:07.133114 ===================================
2338 11:13:07.136494 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2339 11:13:07.139486 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2340 11:13:07.146021 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2341 11:13:07.149626 ===================================
2342 11:13:07.152923 LPDDR4 DRAM CONFIGURATION
2343 11:13:07.156413 ===================================
2344 11:13:07.156891 EX_ROW_EN[0] = 0x10
2345 11:13:07.159385 EX_ROW_EN[1] = 0x0
2346 11:13:07.159957 LP4Y_EN = 0x0
2347 11:13:07.162438 WORK_FSP = 0x0
2348 11:13:07.162885 WL = 0x4
2349 11:13:07.165777 RL = 0x4
2350 11:13:07.166210 BL = 0x2
2351 11:13:07.169230 RPST = 0x0
2352 11:13:07.169643 RD_PRE = 0x0
2353 11:13:07.172693 WR_PRE = 0x1
2354 11:13:07.173111 WR_PST = 0x0
2355 11:13:07.176087 DBI_WR = 0x0
2356 11:13:07.176506 DBI_RD = 0x0
2357 11:13:07.179492 OTF = 0x1
2358 11:13:07.182705 ===================================
2359 11:13:07.189047 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2360 11:13:07.189349 ==
2361 11:13:07.192429 Dram Type= 6, Freq= 0, CH_0, rank 0
2362 11:13:07.196128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 11:13:07.196430 ==
2364 11:13:07.199353 [Duty_Offset_Calibration]
2365 11:13:07.199651 B0:1 B1:-1 CA:0
2366 11:13:07.202267
2367 11:13:07.205615 [DutyScan_Calibration_Flow] k_type=0
2368 11:13:07.213364
2369 11:13:07.213662 ==CLK 0==
2370 11:13:07.216465 Final CLK duty delay cell = 0
2371 11:13:07.220357 [0] MAX Duty = 5125%(X100), DQS PI = 24
2372 11:13:07.223174 [0] MIN Duty = 4875%(X100), DQS PI = 8
2373 11:13:07.223472 [0] AVG Duty = 5000%(X100)
2374 11:13:07.226755
2375 11:13:07.230033 CH0 CLK Duty spec in!! Max-Min= 250%
2376 11:13:07.233621 [DutyScan_Calibration_Flow] ====Done====
2377 11:13:07.234240
2378 11:13:07.236684 [DutyScan_Calibration_Flow] k_type=1
2379 11:13:07.251188
2380 11:13:07.251620 ==DQS 0 ==
2381 11:13:07.254294 Final DQS duty delay cell = -4
2382 11:13:07.258052 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2383 11:13:07.260989 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2384 11:13:07.264667 [-4] AVG Duty = 4968%(X100)
2385 11:13:07.265082
2386 11:13:07.265422 ==DQS 1 ==
2387 11:13:07.268374 Final DQS duty delay cell = -4
2388 11:13:07.271190 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2389 11:13:07.274714 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2390 11:13:07.277654 [-4] AVG Duty = 4938%(X100)
2391 11:13:07.278075
2392 11:13:07.281089 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2393 11:13:07.281509
2394 11:13:07.284641 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2395 11:13:07.287765 [DutyScan_Calibration_Flow] ====Done====
2396 11:13:07.288207
2397 11:13:07.291294 [DutyScan_Calibration_Flow] k_type=3
2398 11:13:07.309474
2399 11:13:07.309887 ==DQM 0 ==
2400 11:13:07.312968 Final DQM duty delay cell = 0
2401 11:13:07.316088 [0] MAX Duty = 5062%(X100), DQS PI = 38
2402 11:13:07.319038 [0] MIN Duty = 4875%(X100), DQS PI = 8
2403 11:13:07.319453 [0] AVG Duty = 4968%(X100)
2404 11:13:07.322652
2405 11:13:07.323076 ==DQM 1 ==
2406 11:13:07.325688 Final DQM duty delay cell = 4
2407 11:13:07.329111 [4] MAX Duty = 5187%(X100), DQS PI = 14
2408 11:13:07.332162 [4] MIN Duty = 5000%(X100), DQS PI = 22
2409 11:13:07.335756 [4] AVG Duty = 5093%(X100)
2410 11:13:07.336195
2411 11:13:07.338915 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2412 11:13:07.339340
2413 11:13:07.342912 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2414 11:13:07.345572 [DutyScan_Calibration_Flow] ====Done====
2415 11:13:07.346006
2416 11:13:07.349077 [DutyScan_Calibration_Flow] k_type=2
2417 11:13:07.364250
2418 11:13:07.364718 ==DQ 0 ==
2419 11:13:07.367482 Final DQ duty delay cell = -4
2420 11:13:07.370534 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2421 11:13:07.374195 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2422 11:13:07.377154 [-4] AVG Duty = 4969%(X100)
2423 11:13:07.377582
2424 11:13:07.377913 ==DQ 1 ==
2425 11:13:07.380463 Final DQ duty delay cell = -4
2426 11:13:07.384267 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2427 11:13:07.387165 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2428 11:13:07.390420 [-4] AVG Duty = 4922%(X100)
2429 11:13:07.390879
2430 11:13:07.393784 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2431 11:13:07.394210
2432 11:13:07.397841 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2433 11:13:07.400668 [DutyScan_Calibration_Flow] ====Done====
2434 11:13:07.401094 ==
2435 11:13:07.404012 Dram Type= 6, Freq= 0, CH_1, rank 0
2436 11:13:07.407655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2437 11:13:07.408085 ==
2438 11:13:07.410442 [Duty_Offset_Calibration]
2439 11:13:07.410804 B0:-1 B1:1 CA:2
2440 11:13:07.411122
2441 11:13:07.414058 [DutyScan_Calibration_Flow] k_type=0
2442 11:13:07.424853
2443 11:13:07.425278 ==CLK 0==
2444 11:13:07.427953 Final CLK duty delay cell = 0
2445 11:13:07.430969 [0] MAX Duty = 5156%(X100), DQS PI = 4
2446 11:13:07.434478 [0] MIN Duty = 5000%(X100), DQS PI = 28
2447 11:13:07.434906 [0] AVG Duty = 5078%(X100)
2448 11:13:07.437699
2449 11:13:07.441332 CH1 CLK Duty spec in!! Max-Min= 156%
2450 11:13:07.444388 [DutyScan_Calibration_Flow] ====Done====
2451 11:13:07.444852
2452 11:13:07.447998 [DutyScan_Calibration_Flow] k_type=1
2453 11:13:07.463697
2454 11:13:07.464127 ==DQS 0 ==
2455 11:13:07.466723 Final DQS duty delay cell = 0
2456 11:13:07.470514 [0] MAX Duty = 5156%(X100), DQS PI = 16
2457 11:13:07.473560 [0] MIN Duty = 4907%(X100), DQS PI = 38
2458 11:13:07.477002 [0] AVG Duty = 5031%(X100)
2459 11:13:07.477462
2460 11:13:07.477821 ==DQS 1 ==
2461 11:13:07.480120 Final DQS duty delay cell = 0
2462 11:13:07.483749 [0] MAX Duty = 5062%(X100), DQS PI = 0
2463 11:13:07.486723 [0] MIN Duty = 4969%(X100), DQS PI = 26
2464 11:13:07.490017 [0] AVG Duty = 5015%(X100)
2465 11:13:07.490445
2466 11:13:07.493348 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2467 11:13:07.493804
2468 11:13:07.496568 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2469 11:13:07.499956 [DutyScan_Calibration_Flow] ====Done====
2470 11:13:07.500379
2471 11:13:07.503300 [DutyScan_Calibration_Flow] k_type=3
2472 11:13:07.519474
2473 11:13:07.519895 ==DQM 0 ==
2474 11:13:07.522910 Final DQM duty delay cell = -4
2475 11:13:07.526049 [-4] MAX Duty = 5062%(X100), DQS PI = 2
2476 11:13:07.529640 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2477 11:13:07.532825 [-4] AVG Duty = 4969%(X100)
2478 11:13:07.533244
2479 11:13:07.533623 ==DQM 1 ==
2480 11:13:07.535823 Final DQM duty delay cell = 0
2481 11:13:07.539340 [0] MAX Duty = 5187%(X100), DQS PI = 36
2482 11:13:07.542953 [0] MIN Duty = 4969%(X100), DQS PI = 4
2483 11:13:07.546074 [0] AVG Duty = 5078%(X100)
2484 11:13:07.546490
2485 11:13:07.549659 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2486 11:13:07.550113
2487 11:13:07.552542 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2488 11:13:07.556227 [DutyScan_Calibration_Flow] ====Done====
2489 11:13:07.556680
2490 11:13:07.559294 [DutyScan_Calibration_Flow] k_type=2
2491 11:13:07.576082
2492 11:13:07.576502 ==DQ 0 ==
2493 11:13:07.579512 Final DQ duty delay cell = 0
2494 11:13:07.582805 [0] MAX Duty = 5187%(X100), DQS PI = 62
2495 11:13:07.586529 [0] MIN Duty = 4907%(X100), DQS PI = 38
2496 11:13:07.586971 [0] AVG Duty = 5047%(X100)
2497 11:13:07.589603
2498 11:13:07.590026 ==DQ 1 ==
2499 11:13:07.592338 Final DQ duty delay cell = 0
2500 11:13:07.595808 [0] MAX Duty = 5124%(X100), DQS PI = 42
2501 11:13:07.599127 [0] MIN Duty = 4969%(X100), DQS PI = 2
2502 11:13:07.599553 [0] AVG Duty = 5046%(X100)
2503 11:13:07.599891
2504 11:13:07.602511 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2505 11:13:07.605814
2506 11:13:07.609177 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2507 11:13:07.612578 [DutyScan_Calibration_Flow] ====Done====
2508 11:13:07.616132 nWR fixed to 30
2509 11:13:07.616584 [ModeRegInit_LP4] CH0 RK0
2510 11:13:07.619078 [ModeRegInit_LP4] CH0 RK1
2511 11:13:07.622351 [ModeRegInit_LP4] CH1 RK0
2512 11:13:07.626002 [ModeRegInit_LP4] CH1 RK1
2513 11:13:07.626470 match AC timing 7
2514 11:13:07.629499 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2515 11:13:07.635601 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2516 11:13:07.639159 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2517 11:13:07.645656 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2518 11:13:07.649396 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2519 11:13:07.649870 ==
2520 11:13:07.652191 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 11:13:07.655319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 11:13:07.655862 ==
2523 11:13:07.662049 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2524 11:13:07.669065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2525 11:13:07.676430 [CA 0] Center 39 (9~70) winsize 62
2526 11:13:07.679344 [CA 1] Center 39 (9~70) winsize 62
2527 11:13:07.682480 [CA 2] Center 35 (5~66) winsize 62
2528 11:13:07.686050 [CA 3] Center 35 (5~65) winsize 61
2529 11:13:07.689757 [CA 4] Center 33 (3~64) winsize 62
2530 11:13:07.692653 [CA 5] Center 33 (4~63) winsize 60
2531 11:13:07.693201
2532 11:13:07.695821 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2533 11:13:07.696368
2534 11:13:07.699539 [CATrainingPosCal] consider 1 rank data
2535 11:13:07.702408 u2DelayCellTimex100 = 270/100 ps
2536 11:13:07.706297 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2537 11:13:07.712373 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2538 11:13:07.715662 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2539 11:13:07.719257 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2540 11:13:07.722667 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2541 11:13:07.726030 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2542 11:13:07.726492
2543 11:13:07.729258 CA PerBit enable=1, Macro0, CA PI delay=33
2544 11:13:07.729703
2545 11:13:07.732661 [CBTSetCACLKResult] CA Dly = 33
2546 11:13:07.733088 CS Dly: 8 (0~39)
2547 11:13:07.735725 ==
2548 11:13:07.739317 Dram Type= 6, Freq= 0, CH_0, rank 1
2549 11:13:07.742541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 11:13:07.743081 ==
2551 11:13:07.746091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2552 11:13:07.752088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2553 11:13:07.761750 [CA 0] Center 39 (9~70) winsize 62
2554 11:13:07.764820 [CA 1] Center 39 (9~70) winsize 62
2555 11:13:07.768417 [CA 2] Center 35 (5~66) winsize 62
2556 11:13:07.772189 [CA 3] Center 34 (4~65) winsize 62
2557 11:13:07.775193 [CA 4] Center 33 (3~64) winsize 62
2558 11:13:07.778918 [CA 5] Center 33 (3~63) winsize 61
2559 11:13:07.779458
2560 11:13:07.781790 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2561 11:13:07.782221
2562 11:13:07.785261 [CATrainingPosCal] consider 2 rank data
2563 11:13:07.788480 u2DelayCellTimex100 = 270/100 ps
2564 11:13:07.791296 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2565 11:13:07.798613 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2566 11:13:07.801647 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2567 11:13:07.804826 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2568 11:13:07.807852 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2569 11:13:07.811429 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2570 11:13:07.812051
2571 11:13:07.814618 CA PerBit enable=1, Macro0, CA PI delay=33
2572 11:13:07.815163
2573 11:13:07.817906 [CBTSetCACLKResult] CA Dly = 33
2574 11:13:07.821134 CS Dly: 8 (0~40)
2575 11:13:07.821614
2576 11:13:07.824630 ----->DramcWriteLeveling(PI) begin...
2577 11:13:07.825112 ==
2578 11:13:07.828039 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 11:13:07.831462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 11:13:07.832112 ==
2581 11:13:07.834385 Write leveling (Byte 0): 32 => 32
2582 11:13:07.837576 Write leveling (Byte 1): 30 => 30
2583 11:13:07.840924 DramcWriteLeveling(PI) end<-----
2584 11:13:07.841383
2585 11:13:07.841716 ==
2586 11:13:07.844237 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 11:13:07.847897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 11:13:07.848565 ==
2589 11:13:07.850923 [Gating] SW mode calibration
2590 11:13:07.857837 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2591 11:13:07.864352 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2592 11:13:07.867400 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2593 11:13:07.871233 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
2594 11:13:07.877787 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 11:13:07.880747 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 11:13:07.883708 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 11:13:07.890367 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 11:13:07.894092 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 11:13:07.897283 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
2600 11:13:07.904047 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
2601 11:13:07.907648 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 11:13:07.910535 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 11:13:07.917029 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 11:13:07.920386 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 11:13:07.923986 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 11:13:07.930999 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 11:13:07.933969 1 0 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
2608 11:13:07.937012 1 1 0 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
2609 11:13:07.943768 1 1 4 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
2610 11:13:07.947058 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 11:13:07.950167 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 11:13:07.956719 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 11:13:07.959976 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 11:13:07.963552 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2615 11:13:07.970353 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2616 11:13:07.973365 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2617 11:13:07.976431 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2618 11:13:07.982967 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:13:07.986600 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:13:07.989502 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:13:07.996720 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:13:07.999643 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:13:08.002807 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 11:13:08.009534 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:13:08.013406 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:13:08.016286 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 11:13:08.023149 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:13:08.026372 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:13:08.029862 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:13:08.032901 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:13:08.039582 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2632 11:13:08.042945 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2633 11:13:08.046004 Total UI for P1: 0, mck2ui 16
2634 11:13:08.049732 best dqsien dly found for B0: ( 1, 3, 28)
2635 11:13:08.052663 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2636 11:13:08.059441 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2637 11:13:08.062649 Total UI for P1: 0, mck2ui 16
2638 11:13:08.066145 best dqsien dly found for B1: ( 1, 4, 2)
2639 11:13:08.069886 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2640 11:13:08.072723 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2641 11:13:08.073158
2642 11:13:08.075877 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2643 11:13:08.079635 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2644 11:13:08.082701 [Gating] SW calibration Done
2645 11:13:08.083133 ==
2646 11:13:08.086350 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 11:13:08.089237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 11:13:08.089667 ==
2649 11:13:08.092452 RX Vref Scan: 0
2650 11:13:08.092907
2651 11:13:08.093245 RX Vref 0 -> 0, step: 1
2652 11:13:08.096008
2653 11:13:08.096436 RX Delay -40 -> 252, step: 8
2654 11:13:08.102574 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2655 11:13:08.105580 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2656 11:13:08.109226 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2657 11:13:08.112336 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2658 11:13:08.115982 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2659 11:13:08.122879 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2660 11:13:08.125691 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2661 11:13:08.129280 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2662 11:13:08.132755 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2663 11:13:08.135601 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2664 11:13:08.138978 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2665 11:13:08.145874 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2666 11:13:08.149182 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2667 11:13:08.152369 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2668 11:13:08.155512 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2669 11:13:08.162478 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2670 11:13:08.162913 ==
2671 11:13:08.165771 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 11:13:08.169059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 11:13:08.169492 ==
2674 11:13:08.169834 DQS Delay:
2675 11:13:08.171993 DQS0 = 0, DQS1 = 0
2676 11:13:08.172418 DQM Delay:
2677 11:13:08.175602 DQM0 = 119, DQM1 = 106
2678 11:13:08.176029 DQ Delay:
2679 11:13:08.178662 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2680 11:13:08.182338 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2681 11:13:08.185518 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2682 11:13:08.189000 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2683 11:13:08.189508
2684 11:13:08.189851
2685 11:13:08.191937 ==
2686 11:13:08.192597 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 11:13:08.198713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 11:13:08.199147 ==
2689 11:13:08.199483
2690 11:13:08.199794
2691 11:13:08.202362 TX Vref Scan disable
2692 11:13:08.202788 == TX Byte 0 ==
2693 11:13:08.205381 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2694 11:13:08.212056 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2695 11:13:08.212662 == TX Byte 1 ==
2696 11:13:08.215160 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2697 11:13:08.222126 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2698 11:13:08.222668 ==
2699 11:13:08.225071 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 11:13:08.228309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 11:13:08.228959 ==
2702 11:13:08.240170 TX Vref=22, minBit 1, minWin=25, winSum=416
2703 11:13:08.244142 TX Vref=24, minBit 0, minWin=26, winSum=421
2704 11:13:08.247178 TX Vref=26, minBit 1, minWin=25, winSum=431
2705 11:13:08.250093 TX Vref=28, minBit 4, minWin=26, winSum=431
2706 11:13:08.253724 TX Vref=30, minBit 5, minWin=26, winSum=431
2707 11:13:08.260140 TX Vref=32, minBit 4, minWin=26, winSum=429
2708 11:13:08.263639 [TxChooseVref] Worse bit 4, Min win 26, Win sum 431, Final Vref 28
2709 11:13:08.264087
2710 11:13:08.267067 Final TX Range 1 Vref 28
2711 11:13:08.267493
2712 11:13:08.267991 ==
2713 11:13:08.270374 Dram Type= 6, Freq= 0, CH_0, rank 0
2714 11:13:08.274076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2715 11:13:08.276873 ==
2716 11:13:08.277300
2717 11:13:08.277629
2718 11:13:08.277938 TX Vref Scan disable
2719 11:13:08.279902 == TX Byte 0 ==
2720 11:13:08.283672 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2721 11:13:08.290259 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2722 11:13:08.290689 == TX Byte 1 ==
2723 11:13:08.293260 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2724 11:13:08.300038 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2725 11:13:08.300469
2726 11:13:08.300834 [DATLAT]
2727 11:13:08.301149 Freq=1200, CH0 RK0
2728 11:13:08.301451
2729 11:13:08.303031 DATLAT Default: 0xd
2730 11:13:08.306796 0, 0xFFFF, sum = 0
2731 11:13:08.307230 1, 0xFFFF, sum = 0
2732 11:13:08.309788 2, 0xFFFF, sum = 0
2733 11:13:08.310232 3, 0xFFFF, sum = 0
2734 11:13:08.313265 4, 0xFFFF, sum = 0
2735 11:13:08.313792 5, 0xFFFF, sum = 0
2736 11:13:08.316810 6, 0xFFFF, sum = 0
2737 11:13:08.317239 7, 0xFFFF, sum = 0
2738 11:13:08.319943 8, 0xFFFF, sum = 0
2739 11:13:08.320372 9, 0xFFFF, sum = 0
2740 11:13:08.323293 10, 0xFFFF, sum = 0
2741 11:13:08.323822 11, 0xFFFF, sum = 0
2742 11:13:08.326453 12, 0x0, sum = 1
2743 11:13:08.326883 13, 0x0, sum = 2
2744 11:13:08.329592 14, 0x0, sum = 3
2745 11:13:08.330025 15, 0x0, sum = 4
2746 11:13:08.333159 best_step = 13
2747 11:13:08.333582
2748 11:13:08.333913 ==
2749 11:13:08.336243 Dram Type= 6, Freq= 0, CH_0, rank 0
2750 11:13:08.340178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2751 11:13:08.340644 ==
2752 11:13:08.341007 RX Vref Scan: 1
2753 11:13:08.342948
2754 11:13:08.343463 Set Vref Range= 32 -> 127
2755 11:13:08.343806
2756 11:13:08.346376 RX Vref 32 -> 127, step: 1
2757 11:13:08.346799
2758 11:13:08.349929 RX Delay -21 -> 252, step: 4
2759 11:13:08.350351
2760 11:13:08.352918 Set Vref, RX VrefLevel [Byte0]: 32
2761 11:13:08.356379 [Byte1]: 32
2762 11:13:08.356831
2763 11:13:08.359800 Set Vref, RX VrefLevel [Byte0]: 33
2764 11:13:08.362970 [Byte1]: 33
2765 11:13:08.366516
2766 11:13:08.366934 Set Vref, RX VrefLevel [Byte0]: 34
2767 11:13:08.369972 [Byte1]: 34
2768 11:13:08.374903
2769 11:13:08.375441 Set Vref, RX VrefLevel [Byte0]: 35
2770 11:13:08.377914 [Byte1]: 35
2771 11:13:08.382780
2772 11:13:08.383205 Set Vref, RX VrefLevel [Byte0]: 36
2773 11:13:08.385757 [Byte1]: 36
2774 11:13:08.390743
2775 11:13:08.391168 Set Vref, RX VrefLevel [Byte0]: 37
2776 11:13:08.393954 [Byte1]: 37
2777 11:13:08.398888
2778 11:13:08.399408 Set Vref, RX VrefLevel [Byte0]: 38
2779 11:13:08.401514 [Byte1]: 38
2780 11:13:08.406417
2781 11:13:08.406842 Set Vref, RX VrefLevel [Byte0]: 39
2782 11:13:08.409632 [Byte1]: 39
2783 11:13:08.414328
2784 11:13:08.414885 Set Vref, RX VrefLevel [Byte0]: 40
2785 11:13:08.417589 [Byte1]: 40
2786 11:13:08.422437
2787 11:13:08.422964 Set Vref, RX VrefLevel [Byte0]: 41
2788 11:13:08.425826 [Byte1]: 41
2789 11:13:08.430101
2790 11:13:08.430622 Set Vref, RX VrefLevel [Byte0]: 42
2791 11:13:08.433833 [Byte1]: 42
2792 11:13:08.438505
2793 11:13:08.439117 Set Vref, RX VrefLevel [Byte0]: 43
2794 11:13:08.441407 [Byte1]: 43
2795 11:13:08.446459
2796 11:13:08.449212 Set Vref, RX VrefLevel [Byte0]: 44
2797 11:13:08.449691 [Byte1]: 44
2798 11:13:08.453855
2799 11:13:08.454276 Set Vref, RX VrefLevel [Byte0]: 45
2800 11:13:08.457403 [Byte1]: 45
2801 11:13:08.461953
2802 11:13:08.462395 Set Vref, RX VrefLevel [Byte0]: 46
2803 11:13:08.465478 [Byte1]: 46
2804 11:13:08.470145
2805 11:13:08.470588 Set Vref, RX VrefLevel [Byte0]: 47
2806 11:13:08.473097 [Byte1]: 47
2807 11:13:08.477765
2808 11:13:08.478204 Set Vref, RX VrefLevel [Byte0]: 48
2809 11:13:08.481334 [Byte1]: 48
2810 11:13:08.485742
2811 11:13:08.486225 Set Vref, RX VrefLevel [Byte0]: 49
2812 11:13:08.489209 [Byte1]: 49
2813 11:13:08.493369
2814 11:13:08.493859 Set Vref, RX VrefLevel [Byte0]: 50
2815 11:13:08.496892 [Byte1]: 50
2816 11:13:08.501842
2817 11:13:08.502285 Set Vref, RX VrefLevel [Byte0]: 51
2818 11:13:08.504627 [Byte1]: 51
2819 11:13:08.509559
2820 11:13:08.510000 Set Vref, RX VrefLevel [Byte0]: 52
2821 11:13:08.512983 [Byte1]: 52
2822 11:13:08.517136
2823 11:13:08.517557 Set Vref, RX VrefLevel [Byte0]: 53
2824 11:13:08.520819 [Byte1]: 53
2825 11:13:08.524993
2826 11:13:08.525418 Set Vref, RX VrefLevel [Byte0]: 54
2827 11:13:08.528822 [Byte1]: 54
2828 11:13:08.533275
2829 11:13:08.533797 Set Vref, RX VrefLevel [Byte0]: 55
2830 11:13:08.536631 [Byte1]: 55
2831 11:13:08.541158
2832 11:13:08.541583 Set Vref, RX VrefLevel [Byte0]: 56
2833 11:13:08.544048 [Byte1]: 56
2834 11:13:08.548964
2835 11:13:08.549391 Set Vref, RX VrefLevel [Byte0]: 57
2836 11:13:08.552561 [Byte1]: 57
2837 11:13:08.556679
2838 11:13:08.557101 Set Vref, RX VrefLevel [Byte0]: 58
2839 11:13:08.559870 [Byte1]: 58
2840 11:13:08.564393
2841 11:13:08.564522 Set Vref, RX VrefLevel [Byte0]: 59
2842 11:13:08.567821 [Byte1]: 59
2843 11:13:08.572364
2844 11:13:08.572446 Set Vref, RX VrefLevel [Byte0]: 60
2845 11:13:08.576113 [Byte1]: 60
2846 11:13:08.580637
2847 11:13:08.580718 Set Vref, RX VrefLevel [Byte0]: 61
2848 11:13:08.583417 [Byte1]: 61
2849 11:13:08.588024
2850 11:13:08.588106 Set Vref, RX VrefLevel [Byte0]: 62
2851 11:13:08.591924 [Byte1]: 62
2852 11:13:08.596123
2853 11:13:08.596206 Set Vref, RX VrefLevel [Byte0]: 63
2854 11:13:08.599888 [Byte1]: 63
2855 11:13:08.603996
2856 11:13:08.604078 Set Vref, RX VrefLevel [Byte0]: 64
2857 11:13:08.607583 [Byte1]: 64
2858 11:13:08.612114
2859 11:13:08.612229 Set Vref, RX VrefLevel [Byte0]: 65
2860 11:13:08.615684 [Byte1]: 65
2861 11:13:08.619911
2862 11:13:08.620005 Set Vref, RX VrefLevel [Byte0]: 66
2863 11:13:08.623473 [Byte1]: 66
2864 11:13:08.627747
2865 11:13:08.627844 Set Vref, RX VrefLevel [Byte0]: 67
2866 11:13:08.631333 [Byte1]: 67
2867 11:13:08.635771
2868 11:13:08.635845 Set Vref, RX VrefLevel [Byte0]: 68
2869 11:13:08.639272 [Byte1]: 68
2870 11:13:08.643509
2871 11:13:08.643597 Set Vref, RX VrefLevel [Byte0]: 69
2872 11:13:08.647267 [Byte1]: 69
2873 11:13:08.652186
2874 11:13:08.652295 Set Vref, RX VrefLevel [Byte0]: 70
2875 11:13:08.655246 [Byte1]: 70
2876 11:13:08.659565
2877 11:13:08.659647 Set Vref, RX VrefLevel [Byte0]: 71
2878 11:13:08.662964 [Byte1]: 71
2879 11:13:08.667540
2880 11:13:08.667647 Set Vref, RX VrefLevel [Byte0]: 72
2881 11:13:08.671073 [Byte1]: 72
2882 11:13:08.675517
2883 11:13:08.675617 Set Vref, RX VrefLevel [Byte0]: 73
2884 11:13:08.678721 [Byte1]: 73
2885 11:13:08.683427
2886 11:13:08.683534 Set Vref, RX VrefLevel [Byte0]: 74
2887 11:13:08.686775 [Byte1]: 74
2888 11:13:08.691523
2889 11:13:08.691597 Set Vref, RX VrefLevel [Byte0]: 75
2890 11:13:08.694529 [Byte1]: 75
2891 11:13:08.699468
2892 11:13:08.699550 Set Vref, RX VrefLevel [Byte0]: 76
2893 11:13:08.702609 [Byte1]: 76
2894 11:13:08.706952
2895 11:13:08.707035 Set Vref, RX VrefLevel [Byte0]: 77
2896 11:13:08.710607 [Byte1]: 77
2897 11:13:08.715110
2898 11:13:08.715192 Final RX Vref Byte 0 = 59 to rank0
2899 11:13:08.718165 Final RX Vref Byte 1 = 47 to rank0
2900 11:13:08.721878 Final RX Vref Byte 0 = 59 to rank1
2901 11:13:08.724754 Final RX Vref Byte 1 = 47 to rank1==
2902 11:13:08.728409 Dram Type= 6, Freq= 0, CH_0, rank 0
2903 11:13:08.734964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 11:13:08.735048 ==
2905 11:13:08.735114 DQS Delay:
2906 11:13:08.735174 DQS0 = 0, DQS1 = 0
2907 11:13:08.738069 DQM Delay:
2908 11:13:08.738151 DQM0 = 119, DQM1 = 105
2909 11:13:08.741656 DQ Delay:
2910 11:13:08.744811 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2911 11:13:08.747817 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =128
2912 11:13:08.751300 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =100
2913 11:13:08.755261 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =116
2914 11:13:08.755344
2915 11:13:08.755410
2916 11:13:08.761879 [DQSOSCAuto] RK0, (LSB)MR18= 0xffb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2917 11:13:08.764834 CH0 RK0: MR19=403, MR18=FFB
2918 11:13:08.771156 CH0_RK0: MR19=0x403, MR18=0xFFB, DQSOSC=404, MR23=63, INC=40, DEC=26
2919 11:13:08.771239
2920 11:13:08.774869 ----->DramcWriteLeveling(PI) begin...
2921 11:13:08.774953 ==
2922 11:13:08.777679 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 11:13:08.781364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 11:13:08.784804 ==
2925 11:13:08.784900 Write leveling (Byte 0): 33 => 33
2926 11:13:08.787930 Write leveling (Byte 1): 30 => 30
2927 11:13:08.791362 DramcWriteLeveling(PI) end<-----
2928 11:13:08.791465
2929 11:13:08.791546 ==
2930 11:13:08.794906 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 11:13:08.802043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 11:13:08.802470 ==
2933 11:13:08.805029 [Gating] SW mode calibration
2934 11:13:08.811794 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2935 11:13:08.814800 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2936 11:13:08.821567 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2937 11:13:08.824630 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2938 11:13:08.828094 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2939 11:13:08.834775 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2940 11:13:08.837685 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2941 11:13:08.841240 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2942 11:13:08.847805 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2943 11:13:08.851043 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2944 11:13:08.854651 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2945 11:13:08.860711 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2946 11:13:08.864204 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2947 11:13:08.867816 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2948 11:13:08.874119 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2949 11:13:08.877745 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2950 11:13:08.881108 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2951 11:13:08.887627 1 0 28 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
2952 11:13:08.890980 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2953 11:13:08.894198 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 11:13:08.900394 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2955 11:13:08.904024 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2956 11:13:08.907136 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 11:13:08.910929 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2958 11:13:08.917473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2959 11:13:08.920536 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2960 11:13:08.924212 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2961 11:13:08.930779 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:13:08.934100 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 11:13:08.937484 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 11:13:08.944333 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 11:13:08.947335 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 11:13:08.950358 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 11:13:08.957215 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 11:13:08.960841 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 11:13:08.963891 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 11:13:08.970370 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 11:13:08.974013 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 11:13:08.977459 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 11:13:08.983813 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 11:13:08.987309 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2975 11:13:08.990178 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2976 11:13:08.996931 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2977 11:13:08.997365 Total UI for P1: 0, mck2ui 16
2978 11:13:09.003548 best dqsien dly found for B0: ( 1, 3, 26)
2979 11:13:09.006820 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 11:13:09.010491 Total UI for P1: 0, mck2ui 16
2981 11:13:09.013496 best dqsien dly found for B1: ( 1, 4, 0)
2982 11:13:09.017032 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2983 11:13:09.020106 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2984 11:13:09.020623
2985 11:13:09.023686 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2986 11:13:09.026699 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2987 11:13:09.030230 [Gating] SW calibration Done
2988 11:13:09.030657 ==
2989 11:13:09.033788 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 11:13:09.036566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 11:13:09.036999 ==
2992 11:13:09.039981 RX Vref Scan: 0
2993 11:13:09.040064
2994 11:13:09.042949 RX Vref 0 -> 0, step: 1
2995 11:13:09.043033
2996 11:13:09.043107 RX Delay -40 -> 252, step: 8
2997 11:13:09.049948 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2998 11:13:09.053401 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2999 11:13:09.056479 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3000 11:13:09.059459 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3001 11:13:09.063516 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3002 11:13:09.069689 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3003 11:13:09.073231 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3004 11:13:09.076639 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3005 11:13:09.079625 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3006 11:13:09.082962 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3007 11:13:09.089547 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3008 11:13:09.093083 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3009 11:13:09.096210 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3010 11:13:09.099845 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3011 11:13:09.106446 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3012 11:13:09.110041 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3013 11:13:09.110484 ==
3014 11:13:09.112979 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 11:13:09.115970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 11:13:09.116402 ==
3017 11:13:09.116793 DQS Delay:
3018 11:13:09.119781 DQS0 = 0, DQS1 = 0
3019 11:13:09.120210 DQM Delay:
3020 11:13:09.123268 DQM0 = 117, DQM1 = 108
3021 11:13:09.123697 DQ Delay:
3022 11:13:09.126095 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3023 11:13:09.129662 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3024 11:13:09.132670 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3025 11:13:09.136155 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =111
3026 11:13:09.139380
3027 11:13:09.139817
3028 11:13:09.140212 ==
3029 11:13:09.142926 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 11:13:09.146061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 11:13:09.146686 ==
3032 11:13:09.147043
3033 11:13:09.147364
3034 11:13:09.149665 TX Vref Scan disable
3035 11:13:09.150245 == TX Byte 0 ==
3036 11:13:09.156404 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3037 11:13:09.159639 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3038 11:13:09.160074 == TX Byte 1 ==
3039 11:13:09.165896 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3040 11:13:09.169063 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3041 11:13:09.169496 ==
3042 11:13:09.172710 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 11:13:09.175799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 11:13:09.176168 ==
3045 11:13:09.189005 TX Vref=22, minBit 1, minWin=26, winSum=421
3046 11:13:09.192456 TX Vref=24, minBit 0, minWin=26, winSum=428
3047 11:13:09.195080 TX Vref=26, minBit 8, minWin=26, winSum=432
3048 11:13:09.198667 TX Vref=28, minBit 13, minWin=25, winSum=436
3049 11:13:09.202353 TX Vref=30, minBit 10, minWin=26, winSum=437
3050 11:13:09.208582 TX Vref=32, minBit 2, minWin=26, winSum=429
3051 11:13:09.212057 [TxChooseVref] Worse bit 10, Min win 26, Win sum 437, Final Vref 30
3052 11:13:09.212642
3053 11:13:09.215452 Final TX Range 1 Vref 30
3054 11:13:09.215989
3055 11:13:09.216327 ==
3056 11:13:09.218371 Dram Type= 6, Freq= 0, CH_0, rank 1
3057 11:13:09.221754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 11:13:09.225048 ==
3059 11:13:09.225474
3060 11:13:09.225807
3061 11:13:09.226115 TX Vref Scan disable
3062 11:13:09.228603 == TX Byte 0 ==
3063 11:13:09.232169 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3064 11:13:09.238905 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3065 11:13:09.239335 == TX Byte 1 ==
3066 11:13:09.242328 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3067 11:13:09.248322 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3068 11:13:09.248779
3069 11:13:09.249117 [DATLAT]
3070 11:13:09.249428 Freq=1200, CH0 RK1
3071 11:13:09.249732
3072 11:13:09.252032 DATLAT Default: 0xd
3073 11:13:09.252464 0, 0xFFFF, sum = 0
3074 11:13:09.255094 1, 0xFFFF, sum = 0
3075 11:13:09.258567 2, 0xFFFF, sum = 0
3076 11:13:09.259005 3, 0xFFFF, sum = 0
3077 11:13:09.261337 4, 0xFFFF, sum = 0
3078 11:13:09.261775 5, 0xFFFF, sum = 0
3079 11:13:09.265040 6, 0xFFFF, sum = 0
3080 11:13:09.265481 7, 0xFFFF, sum = 0
3081 11:13:09.268568 8, 0xFFFF, sum = 0
3082 11:13:09.269019 9, 0xFFFF, sum = 0
3083 11:13:09.271669 10, 0xFFFF, sum = 0
3084 11:13:09.272109 11, 0xFFFF, sum = 0
3085 11:13:09.274774 12, 0x0, sum = 1
3086 11:13:09.275210 13, 0x0, sum = 2
3087 11:13:09.278412 14, 0x0, sum = 3
3088 11:13:09.278846 15, 0x0, sum = 4
3089 11:13:09.281073 best_step = 13
3090 11:13:09.281156
3091 11:13:09.281222 ==
3092 11:13:09.284877 Dram Type= 6, Freq= 0, CH_0, rank 1
3093 11:13:09.287690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 11:13:09.287774 ==
3095 11:13:09.287839 RX Vref Scan: 0
3096 11:13:09.287899
3097 11:13:09.291130 RX Vref 0 -> 0, step: 1
3098 11:13:09.291213
3099 11:13:09.294477 RX Delay -21 -> 252, step: 4
3100 11:13:09.298063 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3101 11:13:09.304422 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3102 11:13:09.307527 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3103 11:13:09.311059 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3104 11:13:09.314613 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3105 11:13:09.317551 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3106 11:13:09.324626 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3107 11:13:09.327788 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3108 11:13:09.330736 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3109 11:13:09.334274 iDelay=199, Bit 9, Center 92 (23 ~ 162) 140
3110 11:13:09.337327 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3111 11:13:09.344049 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3112 11:13:09.347324 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3113 11:13:09.350947 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3114 11:13:09.354018 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3115 11:13:09.360789 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3116 11:13:09.360905 ==
3117 11:13:09.364483 Dram Type= 6, Freq= 0, CH_0, rank 1
3118 11:13:09.367568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 11:13:09.367682 ==
3120 11:13:09.367776 DQS Delay:
3121 11:13:09.370620 DQS0 = 0, DQS1 = 0
3122 11:13:09.370702 DQM Delay:
3123 11:13:09.373838 DQM0 = 116, DQM1 = 107
3124 11:13:09.373920 DQ Delay:
3125 11:13:09.377422 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3126 11:13:09.380426 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3127 11:13:09.384088 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3128 11:13:09.387077 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3129 11:13:09.387160
3130 11:13:09.387224
3131 11:13:09.397007 [DQSOSCAuto] RK1, (LSB)MR18= 0x11eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3132 11:13:09.400619 CH0 RK1: MR19=403, MR18=11EB
3133 11:13:09.403539 CH0_RK1: MR19=0x403, MR18=0x11EB, DQSOSC=403, MR23=63, INC=40, DEC=26
3134 11:13:09.406969 [RxdqsGatingPostProcess] freq 1200
3135 11:13:09.413962 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3136 11:13:09.417154 best DQS0 dly(2T, 0.5T) = (0, 11)
3137 11:13:09.420502 best DQS1 dly(2T, 0.5T) = (0, 12)
3138 11:13:09.424175 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3139 11:13:09.427075 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3140 11:13:09.430653 best DQS0 dly(2T, 0.5T) = (0, 11)
3141 11:13:09.433658 best DQS1 dly(2T, 0.5T) = (0, 12)
3142 11:13:09.436716 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3143 11:13:09.440225 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3144 11:13:09.444015 Pre-setting of DQS Precalculation
3145 11:13:09.446797 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3146 11:13:09.446903 ==
3147 11:13:09.449852 Dram Type= 6, Freq= 0, CH_1, rank 0
3148 11:13:09.453163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3149 11:13:09.453266 ==
3150 11:13:09.459857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3151 11:13:09.466687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3152 11:13:09.474582 [CA 0] Center 37 (7~67) winsize 61
3153 11:13:09.477745 [CA 1] Center 37 (7~68) winsize 62
3154 11:13:09.481396 [CA 2] Center 34 (5~64) winsize 60
3155 11:13:09.484470 [CA 3] Center 33 (3~64) winsize 62
3156 11:13:09.488094 [CA 4] Center 34 (4~64) winsize 61
3157 11:13:09.491907 [CA 5] Center 33 (3~64) winsize 62
3158 11:13:09.492014
3159 11:13:09.494684 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3160 11:13:09.494767
3161 11:13:09.498310 [CATrainingPosCal] consider 1 rank data
3162 11:13:09.501957 u2DelayCellTimex100 = 270/100 ps
3163 11:13:09.504612 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3164 11:13:09.508112 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3165 11:13:09.514591 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3166 11:13:09.518137 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3167 11:13:09.521701 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3168 11:13:09.524705 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3169 11:13:09.524852
3170 11:13:09.528186 CA PerBit enable=1, Macro0, CA PI delay=33
3171 11:13:09.528349
3172 11:13:09.531452 [CBTSetCACLKResult] CA Dly = 33
3173 11:13:09.532005 CS Dly: 5 (0~36)
3174 11:13:09.532371 ==
3175 11:13:09.534580 Dram Type= 6, Freq= 0, CH_1, rank 1
3176 11:13:09.541439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 11:13:09.541897 ==
3178 11:13:09.544885 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3179 11:13:09.551742 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3180 11:13:09.560712 [CA 0] Center 37 (7~67) winsize 61
3181 11:13:09.564132 [CA 1] Center 37 (7~68) winsize 62
3182 11:13:09.567252 [CA 2] Center 34 (4~65) winsize 62
3183 11:13:09.570605 [CA 3] Center 33 (3~64) winsize 62
3184 11:13:09.573957 [CA 4] Center 34 (3~65) winsize 63
3185 11:13:09.577017 [CA 5] Center 33 (3~64) winsize 62
3186 11:13:09.577440
3187 11:13:09.581110 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3188 11:13:09.581626
3189 11:13:09.583889 [CATrainingPosCal] consider 2 rank data
3190 11:13:09.587048 u2DelayCellTimex100 = 270/100 ps
3191 11:13:09.590487 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3192 11:13:09.596869 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3193 11:13:09.600120 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3194 11:13:09.603532 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3195 11:13:09.607034 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3196 11:13:09.609985 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3197 11:13:09.610467
3198 11:13:09.613475 CA PerBit enable=1, Macro0, CA PI delay=33
3199 11:13:09.613901
3200 11:13:09.616858 [CBTSetCACLKResult] CA Dly = 33
3201 11:13:09.620430 CS Dly: 7 (0~40)
3202 11:13:09.620901
3203 11:13:09.623457 ----->DramcWriteLeveling(PI) begin...
3204 11:13:09.624013 ==
3205 11:13:09.626966 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 11:13:09.629897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 11:13:09.630365 ==
3208 11:13:09.633727 Write leveling (Byte 0): 24 => 24
3209 11:13:09.636728 Write leveling (Byte 1): 28 => 28
3210 11:13:09.640267 DramcWriteLeveling(PI) end<-----
3211 11:13:09.640801
3212 11:13:09.641160 ==
3213 11:13:09.643393 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 11:13:09.646483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 11:13:09.646944 ==
3216 11:13:09.649887 [Gating] SW mode calibration
3217 11:13:09.656680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3218 11:13:09.663165 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3219 11:13:09.666447 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3220 11:13:09.669722 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3221 11:13:09.676414 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3222 11:13:09.679985 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3223 11:13:09.683141 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3224 11:13:09.689584 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3225 11:13:09.693374 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
3226 11:13:09.696393 0 15 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
3227 11:13:09.702992 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3228 11:13:09.706173 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3229 11:13:09.709521 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3230 11:13:09.716199 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3231 11:13:09.719140 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3232 11:13:09.722589 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3233 11:13:09.729303 1 0 24 | B1->B0 | 2626 3e3e | 0 0 | (0 0) (1 1)
3234 11:13:09.732890 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3235 11:13:09.736195 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3236 11:13:09.742337 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 11:13:09.745439 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 11:13:09.748986 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 11:13:09.752040 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3240 11:13:09.758933 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 11:13:09.762422 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3242 11:13:09.765287 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3243 11:13:09.771966 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 11:13:09.775543 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 11:13:09.779240 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 11:13:09.785850 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 11:13:09.789053 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 11:13:09.792108 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 11:13:09.798738 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 11:13:09.802397 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 11:13:09.805412 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 11:13:09.811960 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 11:13:09.815394 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 11:13:09.818839 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 11:13:09.825244 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 11:13:09.828774 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 11:13:09.832667 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3258 11:13:09.838455 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3259 11:13:09.841904 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3260 11:13:09.845437 Total UI for P1: 0, mck2ui 16
3261 11:13:09.848429 best dqsien dly found for B0: ( 1, 3, 26)
3262 11:13:09.852005 Total UI for P1: 0, mck2ui 16
3263 11:13:09.855125 best dqsien dly found for B1: ( 1, 3, 28)
3264 11:13:09.858248 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3265 11:13:09.861918 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3266 11:13:09.862016
3267 11:13:09.864887 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3268 11:13:09.868457 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3269 11:13:09.872042 [Gating] SW calibration Done
3270 11:13:09.872125 ==
3271 11:13:09.875153 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 11:13:09.878765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 11:13:09.878848 ==
3274 11:13:09.881652 RX Vref Scan: 0
3275 11:13:09.881765
3276 11:13:09.885321 RX Vref 0 -> 0, step: 1
3277 11:13:09.885404
3278 11:13:09.885487 RX Delay -40 -> 252, step: 8
3279 11:13:09.892165 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3280 11:13:09.895164 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3281 11:13:09.898547 iDelay=208, Bit 2, Center 115 (48 ~ 183) 136
3282 11:13:09.902249 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3283 11:13:09.905145 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3284 11:13:09.911892 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3285 11:13:09.915726 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3286 11:13:09.919095 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3287 11:13:09.922005 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3288 11:13:09.924943 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3289 11:13:09.931856 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3290 11:13:09.935661 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3291 11:13:09.938571 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3292 11:13:09.941484 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3293 11:13:09.945003 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3294 11:13:09.951446 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3295 11:13:09.951583 ==
3296 11:13:09.955042 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 11:13:09.958574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 11:13:09.958697 ==
3299 11:13:09.958812 DQS Delay:
3300 11:13:09.961676 DQS0 = 0, DQS1 = 0
3301 11:13:09.961803 DQM Delay:
3302 11:13:09.965016 DQM0 = 120, DQM1 = 110
3303 11:13:09.965144 DQ Delay:
3304 11:13:09.968262 DQ0 =123, DQ1 =115, DQ2 =115, DQ3 =119
3305 11:13:09.972092 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3306 11:13:09.975722 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3307 11:13:09.978543 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3308 11:13:09.978985
3309 11:13:09.979448
3310 11:13:09.982117 ==
3311 11:13:09.985268 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 11:13:09.988975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 11:13:09.989418 ==
3314 11:13:09.989856
3315 11:13:09.990272
3316 11:13:09.992015 TX Vref Scan disable
3317 11:13:09.992645 == TX Byte 0 ==
3318 11:13:09.995409 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3319 11:13:10.002171 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3320 11:13:10.002623 == TX Byte 1 ==
3321 11:13:10.004962 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3322 11:13:10.011805 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3323 11:13:10.012294 ==
3324 11:13:10.015283 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 11:13:10.018498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 11:13:10.019023 ==
3327 11:13:10.030565 TX Vref=22, minBit 13, minWin=25, winSum=418
3328 11:13:10.033661 TX Vref=24, minBit 10, minWin=25, winSum=420
3329 11:13:10.037042 TX Vref=26, minBit 0, minWin=26, winSum=426
3330 11:13:10.040829 TX Vref=28, minBit 1, minWin=26, winSum=428
3331 11:13:10.043574 TX Vref=30, minBit 9, minWin=25, winSum=426
3332 11:13:10.050819 TX Vref=32, minBit 7, minWin=25, winSum=419
3333 11:13:10.053601 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3334 11:13:10.054032
3335 11:13:10.056964 Final TX Range 1 Vref 28
3336 11:13:10.057394
3337 11:13:10.057728 ==
3338 11:13:10.060608 Dram Type= 6, Freq= 0, CH_1, rank 0
3339 11:13:10.063618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3340 11:13:10.067128 ==
3341 11:13:10.067559
3342 11:13:10.067894
3343 11:13:10.068208 TX Vref Scan disable
3344 11:13:10.070364 == TX Byte 0 ==
3345 11:13:10.073950 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3346 11:13:10.080611 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3347 11:13:10.081032 == TX Byte 1 ==
3348 11:13:10.083902 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3349 11:13:10.087048 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3350 11:13:10.090552
3351 11:13:10.090964 [DATLAT]
3352 11:13:10.091285 Freq=1200, CH1 RK0
3353 11:13:10.091586
3354 11:13:10.093765 DATLAT Default: 0xd
3355 11:13:10.094179 0, 0xFFFF, sum = 0
3356 11:13:10.097275 1, 0xFFFF, sum = 0
3357 11:13:10.097576 2, 0xFFFF, sum = 0
3358 11:13:10.100297 3, 0xFFFF, sum = 0
3359 11:13:10.100618 4, 0xFFFF, sum = 0
3360 11:13:10.104322 5, 0xFFFF, sum = 0
3361 11:13:10.107334 6, 0xFFFF, sum = 0
3362 11:13:10.107652 7, 0xFFFF, sum = 0
3363 11:13:10.110077 8, 0xFFFF, sum = 0
3364 11:13:10.110305 9, 0xFFFF, sum = 0
3365 11:13:10.113689 10, 0xFFFF, sum = 0
3366 11:13:10.114000 11, 0xFFFF, sum = 0
3367 11:13:10.116886 12, 0x0, sum = 1
3368 11:13:10.117198 13, 0x0, sum = 2
3369 11:13:10.120305 14, 0x0, sum = 3
3370 11:13:10.120548 15, 0x0, sum = 4
3371 11:13:10.120728 best_step = 13
3372 11:13:10.123415
3373 11:13:10.123637 ==
3374 11:13:10.127019 Dram Type= 6, Freq= 0, CH_1, rank 0
3375 11:13:10.129894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3376 11:13:10.130140 ==
3377 11:13:10.130318 RX Vref Scan: 1
3378 11:13:10.130481
3379 11:13:10.133412 Set Vref Range= 32 -> 127
3380 11:13:10.133634
3381 11:13:10.136876 RX Vref 32 -> 127, step: 1
3382 11:13:10.137099
3383 11:13:10.140377 RX Delay -21 -> 252, step: 4
3384 11:13:10.140681
3385 11:13:10.143504 Set Vref, RX VrefLevel [Byte0]: 32
3386 11:13:10.146773 [Byte1]: 32
3387 11:13:10.147126
3388 11:13:10.150289 Set Vref, RX VrefLevel [Byte0]: 33
3389 11:13:10.153725 [Byte1]: 33
3390 11:13:10.156796
3391 11:13:10.157275 Set Vref, RX VrefLevel [Byte0]: 34
3392 11:13:10.160287 [Byte1]: 34
3393 11:13:10.165033
3394 11:13:10.168119 Set Vref, RX VrefLevel [Byte0]: 35
3395 11:13:10.168581 [Byte1]: 35
3396 11:13:10.172978
3397 11:13:10.173401 Set Vref, RX VrefLevel [Byte0]: 36
3398 11:13:10.175921 [Byte1]: 36
3399 11:13:10.180605
3400 11:13:10.181018 Set Vref, RX VrefLevel [Byte0]: 37
3401 11:13:10.183717 [Byte1]: 37
3402 11:13:10.188212
3403 11:13:10.188807 Set Vref, RX VrefLevel [Byte0]: 38
3404 11:13:10.191908 [Byte1]: 38
3405 11:13:10.196318
3406 11:13:10.196891 Set Vref, RX VrefLevel [Byte0]: 39
3407 11:13:10.199904 [Byte1]: 39
3408 11:13:10.204229
3409 11:13:10.204855 Set Vref, RX VrefLevel [Byte0]: 40
3410 11:13:10.207750 [Byte1]: 40
3411 11:13:10.212554
3412 11:13:10.213044 Set Vref, RX VrefLevel [Byte0]: 41
3413 11:13:10.215842 [Byte1]: 41
3414 11:13:10.220247
3415 11:13:10.220703 Set Vref, RX VrefLevel [Byte0]: 42
3416 11:13:10.223886 [Byte1]: 42
3417 11:13:10.228082
3418 11:13:10.228492 Set Vref, RX VrefLevel [Byte0]: 43
3419 11:13:10.231687 [Byte1]: 43
3420 11:13:10.236302
3421 11:13:10.236823 Set Vref, RX VrefLevel [Byte0]: 44
3422 11:13:10.239841 [Byte1]: 44
3423 11:13:10.244463
3424 11:13:10.244923 Set Vref, RX VrefLevel [Byte0]: 45
3425 11:13:10.247265 [Byte1]: 45
3426 11:13:10.251924
3427 11:13:10.252403 Set Vref, RX VrefLevel [Byte0]: 46
3428 11:13:10.255393 [Byte1]: 46
3429 11:13:10.259702
3430 11:13:10.260124 Set Vref, RX VrefLevel [Byte0]: 47
3431 11:13:10.263270 [Byte1]: 47
3432 11:13:10.267615
3433 11:13:10.268191 Set Vref, RX VrefLevel [Byte0]: 48
3434 11:13:10.271220 [Byte1]: 48
3435 11:13:10.275464
3436 11:13:10.275878 Set Vref, RX VrefLevel [Byte0]: 49
3437 11:13:10.279286 [Byte1]: 49
3438 11:13:10.284106
3439 11:13:10.284541 Set Vref, RX VrefLevel [Byte0]: 50
3440 11:13:10.286998 [Byte1]: 50
3441 11:13:10.291660
3442 11:13:10.292070 Set Vref, RX VrefLevel [Byte0]: 51
3443 11:13:10.294672 [Byte1]: 51
3444 11:13:10.299598
3445 11:13:10.300011 Set Vref, RX VrefLevel [Byte0]: 52
3446 11:13:10.302607 [Byte1]: 52
3447 11:13:10.307307
3448 11:13:10.307730 Set Vref, RX VrefLevel [Byte0]: 53
3449 11:13:10.310989 [Byte1]: 53
3450 11:13:10.315307
3451 11:13:10.315720 Set Vref, RX VrefLevel [Byte0]: 54
3452 11:13:10.318383 [Byte1]: 54
3453 11:13:10.323302
3454 11:13:10.323713 Set Vref, RX VrefLevel [Byte0]: 55
3455 11:13:10.326317 [Byte1]: 55
3456 11:13:10.330925
3457 11:13:10.331336 Set Vref, RX VrefLevel [Byte0]: 56
3458 11:13:10.334099 [Byte1]: 56
3459 11:13:10.338889
3460 11:13:10.339303 Set Vref, RX VrefLevel [Byte0]: 57
3461 11:13:10.342208 [Byte1]: 57
3462 11:13:10.346999
3463 11:13:10.347414 Set Vref, RX VrefLevel [Byte0]: 58
3464 11:13:10.350475 [Byte1]: 58
3465 11:13:10.355143
3466 11:13:10.355556 Set Vref, RX VrefLevel [Byte0]: 59
3467 11:13:10.358212 [Byte1]: 59
3468 11:13:10.362882
3469 11:13:10.366198 Set Vref, RX VrefLevel [Byte0]: 60
3470 11:13:10.369005 [Byte1]: 60
3471 11:13:10.369422
3472 11:13:10.372644 Set Vref, RX VrefLevel [Byte0]: 61
3473 11:13:10.376279 [Byte1]: 61
3474 11:13:10.376735
3475 11:13:10.378947 Set Vref, RX VrefLevel [Byte0]: 62
3476 11:13:10.382004 [Byte1]: 62
3477 11:13:10.386422
3478 11:13:10.386502 Set Vref, RX VrefLevel [Byte0]: 63
3479 11:13:10.389865 [Byte1]: 63
3480 11:13:10.394051
3481 11:13:10.394137 Set Vref, RX VrefLevel [Byte0]: 64
3482 11:13:10.397513 [Byte1]: 64
3483 11:13:10.401820
3484 11:13:10.401906 Set Vref, RX VrefLevel [Byte0]: 65
3485 11:13:10.405315 [Byte1]: 65
3486 11:13:10.410422
3487 11:13:10.410524 Set Vref, RX VrefLevel [Byte0]: 66
3488 11:13:10.413411 [Byte1]: 66
3489 11:13:10.417856
3490 11:13:10.418045 Set Vref, RX VrefLevel [Byte0]: 67
3491 11:13:10.421456 [Byte1]: 67
3492 11:13:10.425885
3493 11:13:10.426102 Set Vref, RX VrefLevel [Byte0]: 68
3494 11:13:10.429589 [Byte1]: 68
3495 11:13:10.433831
3496 11:13:10.434065 Set Vref, RX VrefLevel [Byte0]: 69
3497 11:13:10.437537 [Byte1]: 69
3498 11:13:10.441524
3499 11:13:10.441848 Final RX Vref Byte 0 = 48 to rank0
3500 11:13:10.445160 Final RX Vref Byte 1 = 50 to rank0
3501 11:13:10.448549 Final RX Vref Byte 0 = 48 to rank1
3502 11:13:10.451913 Final RX Vref Byte 1 = 50 to rank1==
3503 11:13:10.454774 Dram Type= 6, Freq= 0, CH_1, rank 0
3504 11:13:10.461213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 11:13:10.461297 ==
3506 11:13:10.461363 DQS Delay:
3507 11:13:10.461423 DQS0 = 0, DQS1 = 0
3508 11:13:10.464643 DQM Delay:
3509 11:13:10.464726 DQM0 = 117, DQM1 = 110
3510 11:13:10.468424 DQ Delay:
3511 11:13:10.471280 DQ0 =122, DQ1 =112, DQ2 =108, DQ3 =112
3512 11:13:10.474776 DQ4 =116, DQ5 =128, DQ6 =126, DQ7 =114
3513 11:13:10.478453 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =98
3514 11:13:10.481531 DQ12 =118, DQ13 =116, DQ14 =120, DQ15 =120
3515 11:13:10.481627
3516 11:13:10.481701
3517 11:13:10.488174 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3518 11:13:10.491746 CH1 RK0: MR19=403, MR18=2F5
3519 11:13:10.497962 CH1_RK0: MR19=0x403, MR18=0x2F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3520 11:13:10.498085
3521 11:13:10.501514 ----->DramcWriteLeveling(PI) begin...
3522 11:13:10.501641 ==
3523 11:13:10.504475 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 11:13:10.508229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 11:13:10.511673 ==
3526 11:13:10.511898 Write leveling (Byte 0): 23 => 23
3527 11:13:10.514794 Write leveling (Byte 1): 28 => 28
3528 11:13:10.517696 DramcWriteLeveling(PI) end<-----
3529 11:13:10.517900
3530 11:13:10.518057 ==
3531 11:13:10.521404 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 11:13:10.528113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 11:13:10.528419 ==
3534 11:13:10.531170 [Gating] SW mode calibration
3535 11:13:10.537925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3536 11:13:10.540828 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3537 11:13:10.547455 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3538 11:13:10.550870 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3539 11:13:10.553996 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3540 11:13:10.560511 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 11:13:10.563866 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 11:13:10.567472 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 11:13:10.573826 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3544 11:13:10.577461 0 15 28 | B1->B0 | 2424 2b2b | 0 0 | (1 1) (0 1)
3545 11:13:10.580755 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3546 11:13:10.587465 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3547 11:13:10.590447 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 11:13:10.593462 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 11:13:10.600334 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 11:13:10.603987 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 11:13:10.606850 1 0 24 | B1->B0 | 2a2a 2424 | 1 0 | (0 0) (0 0)
3552 11:13:10.613526 1 0 28 | B1->B0 | 4444 3d3d | 0 0 | (0 0) (1 1)
3553 11:13:10.617159 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 11:13:10.620039 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 11:13:10.626781 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 11:13:10.629804 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 11:13:10.633573 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 11:13:10.639969 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 11:13:10.643660 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3560 11:13:10.646614 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3561 11:13:10.653012 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 11:13:10.656258 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 11:13:10.659422 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 11:13:10.666234 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 11:13:10.669893 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 11:13:10.672831 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 11:13:10.680104 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 11:13:10.682973 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 11:13:10.686503 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 11:13:10.693082 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 11:13:10.696025 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 11:13:10.699734 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 11:13:10.706137 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 11:13:10.709649 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 11:13:10.712611 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3576 11:13:10.719246 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3577 11:13:10.722741 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3578 11:13:10.725913 Total UI for P1: 0, mck2ui 16
3579 11:13:10.729527 best dqsien dly found for B0: ( 1, 3, 26)
3580 11:13:10.732677 Total UI for P1: 0, mck2ui 16
3581 11:13:10.736061 best dqsien dly found for B1: ( 1, 3, 26)
3582 11:13:10.739101 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3583 11:13:10.742724 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3584 11:13:10.743278
3585 11:13:10.745598 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3586 11:13:10.749130 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3587 11:13:10.752319 [Gating] SW calibration Done
3588 11:13:10.752812 ==
3589 11:13:10.755746 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 11:13:10.758855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 11:13:10.762162 ==
3592 11:13:10.762733 RX Vref Scan: 0
3593 11:13:10.763257
3594 11:13:10.765754 RX Vref 0 -> 0, step: 1
3595 11:13:10.766302
3596 11:13:10.768475 RX Delay -40 -> 252, step: 8
3597 11:13:10.771973 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3598 11:13:10.775504 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3599 11:13:10.778773 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3600 11:13:10.781873 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3601 11:13:10.788297 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3602 11:13:10.791566 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3603 11:13:10.794897 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3604 11:13:10.798635 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3605 11:13:10.801669 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3606 11:13:10.808403 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3607 11:13:10.811544 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3608 11:13:10.815235 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3609 11:13:10.818053 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3610 11:13:10.821454 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3611 11:13:10.828197 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3612 11:13:10.831144 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3613 11:13:10.831745 ==
3614 11:13:10.834903 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 11:13:10.837693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 11:13:10.838121 ==
3617 11:13:10.841360 DQS Delay:
3618 11:13:10.841782 DQS0 = 0, DQS1 = 0
3619 11:13:10.842118 DQM Delay:
3620 11:13:10.844424 DQM0 = 118, DQM1 = 109
3621 11:13:10.844894 DQ Delay:
3622 11:13:10.847980 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3623 11:13:10.854077 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3624 11:13:10.857851 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3625 11:13:10.860622 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3626 11:13:10.861047
3627 11:13:10.861381
3628 11:13:10.861693 ==
3629 11:13:10.864217 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 11:13:10.867870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 11:13:10.868301 ==
3632 11:13:10.868681
3633 11:13:10.869003
3634 11:13:10.870698 TX Vref Scan disable
3635 11:13:10.874276 == TX Byte 0 ==
3636 11:13:10.877652 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3637 11:13:10.880771 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3638 11:13:10.884285 == TX Byte 1 ==
3639 11:13:10.887815 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3640 11:13:10.890685 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3641 11:13:10.891110 ==
3642 11:13:10.894168 Dram Type= 6, Freq= 0, CH_1, rank 1
3643 11:13:10.897530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3644 11:13:10.897980 ==
3645 11:13:10.910911 TX Vref=22, minBit 8, minWin=25, winSum=425
3646 11:13:10.914377 TX Vref=24, minBit 1, minWin=26, winSum=428
3647 11:13:10.917272 TX Vref=26, minBit 13, minWin=26, winSum=431
3648 11:13:10.920302 TX Vref=28, minBit 0, minWin=27, winSum=434
3649 11:13:10.923642 TX Vref=30, minBit 5, minWin=26, winSum=431
3650 11:13:10.930306 TX Vref=32, minBit 0, minWin=26, winSum=430
3651 11:13:10.933992 [TxChooseVref] Worse bit 0, Min win 27, Win sum 434, Final Vref 28
3652 11:13:10.934419
3653 11:13:10.936972 Final TX Range 1 Vref 28
3654 11:13:10.937397
3655 11:13:10.937734 ==
3656 11:13:10.940493 Dram Type= 6, Freq= 0, CH_1, rank 1
3657 11:13:10.943715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3658 11:13:10.946790 ==
3659 11:13:10.947212
3660 11:13:10.947546
3661 11:13:10.947857 TX Vref Scan disable
3662 11:13:10.950642 == TX Byte 0 ==
3663 11:13:10.954299 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3664 11:13:10.960354 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3665 11:13:10.961014 == TX Byte 1 ==
3666 11:13:10.963787 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3667 11:13:10.970085 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3668 11:13:10.970523
3669 11:13:10.970919 [DATLAT]
3670 11:13:10.971451 Freq=1200, CH1 RK1
3671 11:13:10.971914
3672 11:13:10.973494 DATLAT Default: 0xd
3673 11:13:10.976609 0, 0xFFFF, sum = 0
3674 11:13:10.977193 1, 0xFFFF, sum = 0
3675 11:13:10.980117 2, 0xFFFF, sum = 0
3676 11:13:10.980700 3, 0xFFFF, sum = 0
3677 11:13:10.983426 4, 0xFFFF, sum = 0
3678 11:13:10.984022 5, 0xFFFF, sum = 0
3679 11:13:10.987021 6, 0xFFFF, sum = 0
3680 11:13:10.987594 7, 0xFFFF, sum = 0
3681 11:13:10.989937 8, 0xFFFF, sum = 0
3682 11:13:10.990372 9, 0xFFFF, sum = 0
3683 11:13:10.993550 10, 0xFFFF, sum = 0
3684 11:13:10.993982 11, 0xFFFF, sum = 0
3685 11:13:10.997043 12, 0x0, sum = 1
3686 11:13:10.997516 13, 0x0, sum = 2
3687 11:13:11.000034 14, 0x0, sum = 3
3688 11:13:11.000506 15, 0x0, sum = 4
3689 11:13:11.003587 best_step = 13
3690 11:13:11.004074
3691 11:13:11.004414 ==
3692 11:13:11.006991 Dram Type= 6, Freq= 0, CH_1, rank 1
3693 11:13:11.010072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3694 11:13:11.010547 ==
3695 11:13:11.013079 RX Vref Scan: 0
3696 11:13:11.013498
3697 11:13:11.013825 RX Vref 0 -> 0, step: 1
3698 11:13:11.014132
3699 11:13:11.016730 RX Delay -21 -> 252, step: 4
3700 11:13:11.023378 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3701 11:13:11.026430 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3702 11:13:11.029850 iDelay=199, Bit 2, Center 108 (47 ~ 170) 124
3703 11:13:11.033389 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3704 11:13:11.036442 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3705 11:13:11.042823 iDelay=199, Bit 5, Center 130 (67 ~ 194) 128
3706 11:13:11.046404 iDelay=199, Bit 6, Center 132 (67 ~ 198) 132
3707 11:13:11.049556 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3708 11:13:11.052631 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3709 11:13:11.056319 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3710 11:13:11.063018 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3711 11:13:11.066103 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3712 11:13:11.069204 iDelay=199, Bit 12, Center 120 (51 ~ 190) 140
3713 11:13:11.072671 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3714 11:13:11.079151 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3715 11:13:11.082716 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3716 11:13:11.083156 ==
3717 11:13:11.085586 Dram Type= 6, Freq= 0, CH_1, rank 1
3718 11:13:11.088911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3719 11:13:11.089339 ==
3720 11:13:11.089673 DQS Delay:
3721 11:13:11.092333 DQS0 = 0, DQS1 = 0
3722 11:13:11.092807 DQM Delay:
3723 11:13:11.095352 DQM0 = 118, DQM1 = 110
3724 11:13:11.095777 DQ Delay:
3725 11:13:11.098998 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =114
3726 11:13:11.102213 DQ4 =116, DQ5 =130, DQ6 =132, DQ7 =116
3727 11:13:11.105985 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100
3728 11:13:11.112301 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =118
3729 11:13:11.112754
3730 11:13:11.113089
3731 11:13:11.119061 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8f3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
3732 11:13:11.122129 CH1 RK1: MR19=303, MR18=F8F3
3733 11:13:11.128685 CH1_RK1: MR19=0x303, MR18=0xF8F3, DQSOSC=413, MR23=63, INC=38, DEC=25
3734 11:13:11.132359 [RxdqsGatingPostProcess] freq 1200
3735 11:13:11.135403 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3736 11:13:11.138552 best DQS0 dly(2T, 0.5T) = (0, 11)
3737 11:13:11.141563 best DQS1 dly(2T, 0.5T) = (0, 11)
3738 11:13:11.145057 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3739 11:13:11.148203 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3740 11:13:11.151801 best DQS0 dly(2T, 0.5T) = (0, 11)
3741 11:13:11.154910 best DQS1 dly(2T, 0.5T) = (0, 11)
3742 11:13:11.158548 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3743 11:13:11.161535 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3744 11:13:11.165130 Pre-setting of DQS Precalculation
3745 11:13:11.168383 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3746 11:13:11.178309 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3747 11:13:11.184507 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3748 11:13:11.184969
3749 11:13:11.185304
3750 11:13:11.187938 [Calibration Summary] 2400 Mbps
3751 11:13:11.188362 CH 0, Rank 0
3752 11:13:11.191318 SW Impedance : PASS
3753 11:13:11.195006 DUTY Scan : NO K
3754 11:13:11.195432 ZQ Calibration : PASS
3755 11:13:11.197815 Jitter Meter : NO K
3756 11:13:11.198243 CBT Training : PASS
3757 11:13:11.201304 Write leveling : PASS
3758 11:13:11.204888 RX DQS gating : PASS
3759 11:13:11.205313 RX DQ/DQS(RDDQC) : PASS
3760 11:13:11.207825 TX DQ/DQS : PASS
3761 11:13:11.211209 RX DATLAT : PASS
3762 11:13:11.211638 RX DQ/DQS(Engine): PASS
3763 11:13:11.214684 TX OE : NO K
3764 11:13:11.215109 All Pass.
3765 11:13:11.215446
3766 11:13:11.217669 CH 0, Rank 1
3767 11:13:11.218094 SW Impedance : PASS
3768 11:13:11.221475 DUTY Scan : NO K
3769 11:13:11.224492 ZQ Calibration : PASS
3770 11:13:11.224942 Jitter Meter : NO K
3771 11:13:11.227572 CBT Training : PASS
3772 11:13:11.231224 Write leveling : PASS
3773 11:13:11.231647 RX DQS gating : PASS
3774 11:13:11.234330 RX DQ/DQS(RDDQC) : PASS
3775 11:13:11.237627 TX DQ/DQS : PASS
3776 11:13:11.238051 RX DATLAT : PASS
3777 11:13:11.240570 RX DQ/DQS(Engine): PASS
3778 11:13:11.244297 TX OE : NO K
3779 11:13:11.244754 All Pass.
3780 11:13:11.245088
3781 11:13:11.245399 CH 1, Rank 0
3782 11:13:11.247266 SW Impedance : PASS
3783 11:13:11.250868 DUTY Scan : NO K
3784 11:13:11.251292 ZQ Calibration : PASS
3785 11:13:11.254078 Jitter Meter : NO K
3786 11:13:11.257077 CBT Training : PASS
3787 11:13:11.257503 Write leveling : PASS
3788 11:13:11.260711 RX DQS gating : PASS
3789 11:13:11.261139 RX DQ/DQS(RDDQC) : PASS
3790 11:13:11.263806 TX DQ/DQS : PASS
3791 11:13:11.267282 RX DATLAT : PASS
3792 11:13:11.267706 RX DQ/DQS(Engine): PASS
3793 11:13:11.270993 TX OE : NO K
3794 11:13:11.271422 All Pass.
3795 11:13:11.271757
3796 11:13:11.273909 CH 1, Rank 1
3797 11:13:11.274376 SW Impedance : PASS
3798 11:13:11.277036 DUTY Scan : NO K
3799 11:13:11.280445 ZQ Calibration : PASS
3800 11:13:11.280924 Jitter Meter : NO K
3801 11:13:11.283755 CBT Training : PASS
3802 11:13:11.287335 Write leveling : PASS
3803 11:13:11.287758 RX DQS gating : PASS
3804 11:13:11.290728 RX DQ/DQS(RDDQC) : PASS
3805 11:13:11.293637 TX DQ/DQS : PASS
3806 11:13:11.294085 RX DATLAT : PASS
3807 11:13:11.297123 RX DQ/DQS(Engine): PASS
3808 11:13:11.300040 TX OE : NO K
3809 11:13:11.300466 All Pass.
3810 11:13:11.300856
3811 11:13:11.301172 DramC Write-DBI off
3812 11:13:11.303630 PER_BANK_REFRESH: Hybrid Mode
3813 11:13:11.307277 TX_TRACKING: ON
3814 11:13:11.313664 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3815 11:13:11.320042 [FAST_K] Save calibration result to emmc
3816 11:13:11.323949 dramc_set_vcore_voltage set vcore to 650000
3817 11:13:11.324478 Read voltage for 600, 5
3818 11:13:11.326936 Vio18 = 0
3819 11:13:11.327361 Vcore = 650000
3820 11:13:11.327694 Vdram = 0
3821 11:13:11.330470 Vddq = 0
3822 11:13:11.330894 Vmddr = 0
3823 11:13:11.333371 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3824 11:13:11.340234 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3825 11:13:11.343506 MEM_TYPE=3, freq_sel=19
3826 11:13:11.346579 sv_algorithm_assistance_LP4_1600
3827 11:13:11.350186 ============ PULL DRAM RESETB DOWN ============
3828 11:13:11.353075 ========== PULL DRAM RESETB DOWN end =========
3829 11:13:11.360296 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3830 11:13:11.363449 ===================================
3831 11:13:11.363886 LPDDR4 DRAM CONFIGURATION
3832 11:13:11.366630 ===================================
3833 11:13:11.369620 EX_ROW_EN[0] = 0x0
3834 11:13:11.370047 EX_ROW_EN[1] = 0x0
3835 11:13:11.373397 LP4Y_EN = 0x0
3836 11:13:11.373822 WORK_FSP = 0x0
3837 11:13:11.376399 WL = 0x2
3838 11:13:11.376869 RL = 0x2
3839 11:13:11.379627 BL = 0x2
3840 11:13:11.383316 RPST = 0x0
3841 11:13:11.383845 RD_PRE = 0x0
3842 11:13:11.386693 WR_PRE = 0x1
3843 11:13:11.387119 WR_PST = 0x0
3844 11:13:11.389856 DBI_WR = 0x0
3845 11:13:11.390297 DBI_RD = 0x0
3846 11:13:11.393170 OTF = 0x1
3847 11:13:11.396161 ===================================
3848 11:13:11.399716 ===================================
3849 11:13:11.400143 ANA top config
3850 11:13:11.402943 ===================================
3851 11:13:11.406059 DLL_ASYNC_EN = 0
3852 11:13:11.409444 ALL_SLAVE_EN = 1
3853 11:13:11.409869 NEW_RANK_MODE = 1
3854 11:13:11.412957 DLL_IDLE_MODE = 1
3855 11:13:11.416135 LP45_APHY_COMB_EN = 1
3856 11:13:11.419339 TX_ODT_DIS = 1
3857 11:13:11.422979 NEW_8X_MODE = 1
3858 11:13:11.425780 ===================================
3859 11:13:11.426212 ===================================
3860 11:13:11.429527 data_rate = 1200
3861 11:13:11.432459 CKR = 1
3862 11:13:11.436132 DQ_P2S_RATIO = 8
3863 11:13:11.439063 ===================================
3864 11:13:11.442493 CA_P2S_RATIO = 8
3865 11:13:11.445573 DQ_CA_OPEN = 0
3866 11:13:11.449118 DQ_SEMI_OPEN = 0
3867 11:13:11.449545 CA_SEMI_OPEN = 0
3868 11:13:11.452657 CA_FULL_RATE = 0
3869 11:13:11.455597 DQ_CKDIV4_EN = 1
3870 11:13:11.459421 CA_CKDIV4_EN = 1
3871 11:13:11.462523 CA_PREDIV_EN = 0
3872 11:13:11.465681 PH8_DLY = 0
3873 11:13:11.466106 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3874 11:13:11.469227 DQ_AAMCK_DIV = 4
3875 11:13:11.472353 CA_AAMCK_DIV = 4
3876 11:13:11.475426 CA_ADMCK_DIV = 4
3877 11:13:11.479219 DQ_TRACK_CA_EN = 0
3878 11:13:11.482140 CA_PICK = 600
3879 11:13:11.485873 CA_MCKIO = 600
3880 11:13:11.486299 MCKIO_SEMI = 0
3881 11:13:11.488691 PLL_FREQ = 2288
3882 11:13:11.492340 DQ_UI_PI_RATIO = 32
3883 11:13:11.495649 CA_UI_PI_RATIO = 0
3884 11:13:11.498589 ===================================
3885 11:13:11.501863 ===================================
3886 11:13:11.505180 memory_type:LPDDR4
3887 11:13:11.505604 GP_NUM : 10
3888 11:13:11.508497 SRAM_EN : 1
3889 11:13:11.512039 MD32_EN : 0
3890 11:13:11.514923 ===================================
3891 11:13:11.515353 [ANA_INIT] >>>>>>>>>>>>>>
3892 11:13:11.518797 <<<<<< [CONFIGURE PHASE]: ANA_TX
3893 11:13:11.521870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3894 11:13:11.525392 ===================================
3895 11:13:11.528179 data_rate = 1200,PCW = 0X5800
3896 11:13:11.531738 ===================================
3897 11:13:11.534690 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3898 11:13:11.541366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3899 11:13:11.545148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3900 11:13:11.551373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3901 11:13:11.554659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3902 11:13:11.558151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3903 11:13:11.561187 [ANA_INIT] flow start
3904 11:13:11.561609 [ANA_INIT] PLL >>>>>>>>
3905 11:13:11.564690 [ANA_INIT] PLL <<<<<<<<
3906 11:13:11.567696 [ANA_INIT] MIDPI >>>>>>>>
3907 11:13:11.568121 [ANA_INIT] MIDPI <<<<<<<<
3908 11:13:11.571307 [ANA_INIT] DLL >>>>>>>>
3909 11:13:11.574393 [ANA_INIT] flow end
3910 11:13:11.577519 ============ LP4 DIFF to SE enter ============
3911 11:13:11.581290 ============ LP4 DIFF to SE exit ============
3912 11:13:11.584101 [ANA_INIT] <<<<<<<<<<<<<
3913 11:13:11.587941 [Flow] Enable top DCM control >>>>>
3914 11:13:11.591045 [Flow] Enable top DCM control <<<<<
3915 11:13:11.594066 Enable DLL master slave shuffle
3916 11:13:11.597521 ==============================================================
3917 11:13:11.601117 Gating Mode config
3918 11:13:11.607635 ==============================================================
3919 11:13:11.608063 Config description:
3920 11:13:11.617412 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3921 11:13:11.624237 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3922 11:13:11.627351 SELPH_MODE 0: By rank 1: By Phase
3923 11:13:11.634377 ==============================================================
3924 11:13:11.637308 GAT_TRACK_EN = 1
3925 11:13:11.640750 RX_GATING_MODE = 2
3926 11:13:11.643927 RX_GATING_TRACK_MODE = 2
3927 11:13:11.646865 SELPH_MODE = 1
3928 11:13:11.650522 PICG_EARLY_EN = 1
3929 11:13:11.653582 VALID_LAT_VALUE = 1
3930 11:13:11.656660 ==============================================================
3931 11:13:11.660336 Enter into Gating configuration >>>>
3932 11:13:11.663664 Exit from Gating configuration <<<<
3933 11:13:11.666797 Enter into DVFS_PRE_config >>>>>
3934 11:13:11.679584 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3935 11:13:11.683230 Exit from DVFS_PRE_config <<<<<
3936 11:13:11.686279 Enter into PICG configuration >>>>
3937 11:13:11.689845 Exit from PICG configuration <<<<
3938 11:13:11.690523 [RX_INPUT] configuration >>>>>
3939 11:13:11.693248 [RX_INPUT] configuration <<<<<
3940 11:13:11.700036 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3941 11:13:11.703173 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3942 11:13:11.709932 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3943 11:13:11.716338 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3944 11:13:11.722860 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3945 11:13:11.729771 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3946 11:13:11.732618 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3947 11:13:11.736111 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3948 11:13:11.742547 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3949 11:13:11.746139 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3950 11:13:11.749336 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3951 11:13:11.756075 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3952 11:13:11.759059 ===================================
3953 11:13:11.759627 LPDDR4 DRAM CONFIGURATION
3954 11:13:11.762164 ===================================
3955 11:13:11.765660 EX_ROW_EN[0] = 0x0
3956 11:13:11.766084 EX_ROW_EN[1] = 0x0
3957 11:13:11.769112 LP4Y_EN = 0x0
3958 11:13:11.769539 WORK_FSP = 0x0
3959 11:13:11.772116 WL = 0x2
3960 11:13:11.772573 RL = 0x2
3961 11:13:11.775780 BL = 0x2
3962 11:13:11.778781 RPST = 0x0
3963 11:13:11.779201 RD_PRE = 0x0
3964 11:13:11.782524 WR_PRE = 0x1
3965 11:13:11.782986 WR_PST = 0x0
3966 11:13:11.785503 DBI_WR = 0x0
3967 11:13:11.785941 DBI_RD = 0x0
3968 11:13:11.788630 OTF = 0x1
3969 11:13:11.792244 ===================================
3970 11:13:11.795409 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3971 11:13:11.799012 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3972 11:13:11.805643 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3973 11:13:11.808405 ===================================
3974 11:13:11.809006 LPDDR4 DRAM CONFIGURATION
3975 11:13:11.812032 ===================================
3976 11:13:11.815366 EX_ROW_EN[0] = 0x10
3977 11:13:11.815842 EX_ROW_EN[1] = 0x0
3978 11:13:11.818414 LP4Y_EN = 0x0
3979 11:13:11.818986 WORK_FSP = 0x0
3980 11:13:11.821910 WL = 0x2
3981 11:13:11.825296 RL = 0x2
3982 11:13:11.825777 BL = 0x2
3983 11:13:11.828244 RPST = 0x0
3984 11:13:11.828708 RD_PRE = 0x0
3985 11:13:11.831755 WR_PRE = 0x1
3986 11:13:11.832172 WR_PST = 0x0
3987 11:13:11.834842 DBI_WR = 0x0
3988 11:13:11.835264 DBI_RD = 0x0
3989 11:13:11.838139 OTF = 0x1
3990 11:13:11.841252 ===================================
3991 11:13:11.848182 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3992 11:13:11.851619 nWR fixed to 30
3993 11:13:11.852040 [ModeRegInit_LP4] CH0 RK0
3994 11:13:11.854683 [ModeRegInit_LP4] CH0 RK1
3995 11:13:11.857889 [ModeRegInit_LP4] CH1 RK0
3996 11:13:11.858309 [ModeRegInit_LP4] CH1 RK1
3997 11:13:11.861220 match AC timing 17
3998 11:13:11.864463 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3999 11:13:11.870849 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4000 11:13:11.874434 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4001 11:13:11.878295 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4002 11:13:11.884450 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4003 11:13:11.884899 ==
4004 11:13:11.888169 Dram Type= 6, Freq= 0, CH_0, rank 0
4005 11:13:11.891133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 11:13:11.891558 ==
4007 11:13:11.897997 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4008 11:13:11.904629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4009 11:13:11.907856 [CA 0] Center 36 (6~66) winsize 61
4010 11:13:11.910747 [CA 1] Center 36 (6~66) winsize 61
4011 11:13:11.914097 [CA 2] Center 34 (3~65) winsize 63
4012 11:13:11.917162 [CA 3] Center 34 (3~65) winsize 63
4013 11:13:11.920642 [CA 4] Center 33 (3~64) winsize 62
4014 11:13:11.924124 [CA 5] Center 33 (3~64) winsize 62
4015 11:13:11.924585
4016 11:13:11.927703 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4017 11:13:11.928127
4018 11:13:11.930438 [CATrainingPosCal] consider 1 rank data
4019 11:13:11.934065 u2DelayCellTimex100 = 270/100 ps
4020 11:13:11.937002 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4021 11:13:11.940683 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4022 11:13:11.944086 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4023 11:13:11.947014 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4024 11:13:11.950249 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4025 11:13:11.954121 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 11:13:11.954645
4027 11:13:11.960602 CA PerBit enable=1, Macro0, CA PI delay=33
4028 11:13:11.961118
4029 11:13:11.963578 [CBTSetCACLKResult] CA Dly = 33
4030 11:13:11.964001 CS Dly: 5 (0~36)
4031 11:13:11.964334 ==
4032 11:13:11.966705 Dram Type= 6, Freq= 0, CH_0, rank 1
4033 11:13:11.970277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 11:13:11.970703 ==
4035 11:13:11.976753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4036 11:13:11.983760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4037 11:13:11.987202 [CA 0] Center 35 (5~66) winsize 62
4038 11:13:11.990012 [CA 1] Center 36 (6~66) winsize 61
4039 11:13:11.993163 [CA 2] Center 33 (3~64) winsize 62
4040 11:13:11.997036 [CA 3] Center 33 (3~64) winsize 62
4041 11:13:11.999988 [CA 4] Center 33 (2~64) winsize 63
4042 11:13:12.003400 [CA 5] Center 33 (3~64) winsize 62
4043 11:13:12.003822
4044 11:13:12.006501 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4045 11:13:12.007023
4046 11:13:12.010196 [CATrainingPosCal] consider 2 rank data
4047 11:13:12.013277 u2DelayCellTimex100 = 270/100 ps
4048 11:13:12.016329 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4049 11:13:12.019747 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4050 11:13:12.022803 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4051 11:13:12.026597 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4052 11:13:12.033118 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4053 11:13:12.036424 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4054 11:13:12.036907
4055 11:13:12.039382 CA PerBit enable=1, Macro0, CA PI delay=33
4056 11:13:12.039840
4057 11:13:12.042951 [CBTSetCACLKResult] CA Dly = 33
4058 11:13:12.043382 CS Dly: 5 (0~37)
4059 11:13:12.043720
4060 11:13:12.046114 ----->DramcWriteLeveling(PI) begin...
4061 11:13:12.046552 ==
4062 11:13:12.049189 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 11:13:12.056059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 11:13:12.056779 ==
4065 11:13:12.059150 Write leveling (Byte 0): 32 => 32
4066 11:13:12.062997 Write leveling (Byte 1): 29 => 29
4067 11:13:12.063616 DramcWriteLeveling(PI) end<-----
4068 11:13:12.065831
4069 11:13:12.066359 ==
4070 11:13:12.069170 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 11:13:12.072942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 11:13:12.073552 ==
4073 11:13:12.075612 [Gating] SW mode calibration
4074 11:13:12.082225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4075 11:13:12.085378 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4076 11:13:12.092199 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4077 11:13:12.095592 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4078 11:13:12.098648 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4079 11:13:12.105353 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4080 11:13:12.108957 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4081 11:13:12.112016 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4082 11:13:12.118806 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4083 11:13:12.122029 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 11:13:12.125395 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 11:13:12.132228 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 11:13:12.135275 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 11:13:12.138760 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4088 11:13:12.145159 0 10 16 | B1->B0 | 3535 4040 | 1 0 | (1 1) (0 0)
4089 11:13:12.148562 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 11:13:12.152175 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 11:13:12.158561 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 11:13:12.162037 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 11:13:12.165050 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 11:13:12.171508 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 11:13:12.175177 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 11:13:12.178257 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 11:13:12.184968 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 11:13:12.188456 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 11:13:12.191286 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 11:13:12.198021 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 11:13:12.201163 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 11:13:12.204595 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 11:13:12.211442 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 11:13:12.214601 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 11:13:12.218026 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 11:13:12.224184 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 11:13:12.227690 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 11:13:12.231285 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 11:13:12.237689 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 11:13:12.241396 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 11:13:12.244144 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4112 11:13:12.251161 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4113 11:13:12.251588 Total UI for P1: 0, mck2ui 16
4114 11:13:12.257556 best dqsien dly found for B0: ( 0, 13, 12)
4115 11:13:12.257985 Total UI for P1: 0, mck2ui 16
4116 11:13:12.263894 best dqsien dly found for B1: ( 0, 13, 14)
4117 11:13:12.267664 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4118 11:13:12.270511 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4119 11:13:12.270936
4120 11:13:12.273638 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4121 11:13:12.277383 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4122 11:13:12.280475 [Gating] SW calibration Done
4123 11:13:12.280940 ==
4124 11:13:12.284225 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 11:13:12.287084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 11:13:12.287513 ==
4127 11:13:12.290431 RX Vref Scan: 0
4128 11:13:12.290854
4129 11:13:12.293941 RX Vref 0 -> 0, step: 1
4130 11:13:12.294363
4131 11:13:12.294693 RX Delay -230 -> 252, step: 16
4132 11:13:12.300022 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4133 11:13:12.303607 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4134 11:13:12.307112 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4135 11:13:12.310127 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4136 11:13:12.316980 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4137 11:13:12.319894 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4138 11:13:12.323507 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4139 11:13:12.326532 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4140 11:13:12.333150 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4141 11:13:12.336844 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4142 11:13:12.340195 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4143 11:13:12.343120 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4144 11:13:12.349723 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4145 11:13:12.353218 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4146 11:13:12.356614 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4147 11:13:12.359530 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4148 11:13:12.360059 ==
4149 11:13:12.363250 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 11:13:12.369483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 11:13:12.369913 ==
4152 11:13:12.370247 DQS Delay:
4153 11:13:12.372911 DQS0 = 0, DQS1 = 0
4154 11:13:12.373360 DQM Delay:
4155 11:13:12.373895 DQM0 = 43, DQM1 = 32
4156 11:13:12.376030 DQ Delay:
4157 11:13:12.379854 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4158 11:13:12.382977 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4159 11:13:12.386569 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4160 11:13:12.389506 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4161 11:13:12.389931
4162 11:13:12.390259
4163 11:13:12.390566 ==
4164 11:13:12.392617 Dram Type= 6, Freq= 0, CH_0, rank 0
4165 11:13:12.396557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 11:13:12.397101 ==
4167 11:13:12.397445
4168 11:13:12.397755
4169 11:13:12.399184 TX Vref Scan disable
4170 11:13:12.402804 == TX Byte 0 ==
4171 11:13:12.405683 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4172 11:13:12.409200 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4173 11:13:12.412726 == TX Byte 1 ==
4174 11:13:12.416098 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4175 11:13:12.419102 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4176 11:13:12.419528 ==
4177 11:13:12.422363 Dram Type= 6, Freq= 0, CH_0, rank 0
4178 11:13:12.426029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 11:13:12.428950 ==
4180 11:13:12.429375
4181 11:13:12.429707
4182 11:13:12.430016 TX Vref Scan disable
4183 11:13:12.432615 == TX Byte 0 ==
4184 11:13:12.435688 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4185 11:13:12.442641 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4186 11:13:12.442758 == TX Byte 1 ==
4187 11:13:12.445560 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4188 11:13:12.451962 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4189 11:13:12.452067
4190 11:13:12.452173 [DATLAT]
4191 11:13:12.452272 Freq=600, CH0 RK0
4192 11:13:12.452376
4193 11:13:12.455509 DATLAT Default: 0x9
4194 11:13:12.458503 0, 0xFFFF, sum = 0
4195 11:13:12.458617 1, 0xFFFF, sum = 0
4196 11:13:12.461914 2, 0xFFFF, sum = 0
4197 11:13:12.462018 3, 0xFFFF, sum = 0
4198 11:13:12.465413 4, 0xFFFF, sum = 0
4199 11:13:12.465517 5, 0xFFFF, sum = 0
4200 11:13:12.468497 6, 0xFFFF, sum = 0
4201 11:13:12.468635 7, 0xFFFF, sum = 0
4202 11:13:12.472049 8, 0x0, sum = 1
4203 11:13:12.472155 9, 0x0, sum = 2
4204 11:13:12.474801 10, 0x0, sum = 3
4205 11:13:12.474907 11, 0x0, sum = 4
4206 11:13:12.475009 best_step = 9
4207 11:13:12.475103
4208 11:13:12.478467 ==
4209 11:13:12.481474 Dram Type= 6, Freq= 0, CH_0, rank 0
4210 11:13:12.485185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 11:13:12.485286 ==
4212 11:13:12.485381 RX Vref Scan: 1
4213 11:13:12.485474
4214 11:13:12.488078 RX Vref 0 -> 0, step: 1
4215 11:13:12.488173
4216 11:13:12.491303 RX Delay -179 -> 252, step: 8
4217 11:13:12.491396
4218 11:13:12.494974 Set Vref, RX VrefLevel [Byte0]: 59
4219 11:13:12.497910 [Byte1]: 47
4220 11:13:12.498006
4221 11:13:12.501383 Final RX Vref Byte 0 = 59 to rank0
4222 11:13:12.505178 Final RX Vref Byte 1 = 47 to rank0
4223 11:13:12.508087 Final RX Vref Byte 0 = 59 to rank1
4224 11:13:12.511116 Final RX Vref Byte 1 = 47 to rank1==
4225 11:13:12.514753 Dram Type= 6, Freq= 0, CH_0, rank 0
4226 11:13:12.518468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 11:13:12.521515 ==
4228 11:13:12.521611 DQS Delay:
4229 11:13:12.521701 DQS0 = 0, DQS1 = 0
4230 11:13:12.524512 DQM Delay:
4231 11:13:12.524635 DQM0 = 44, DQM1 = 32
4232 11:13:12.528366 DQ Delay:
4233 11:13:12.528484 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4234 11:13:12.531260 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4235 11:13:12.534338 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4236 11:13:12.537803 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4237 11:13:12.541450
4238 11:13:12.541551
4239 11:13:12.547646 [DQSOSCAuto] RK0, (LSB)MR18= 0x673f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4240 11:13:12.550969 CH0 RK0: MR19=808, MR18=673F
4241 11:13:12.557605 CH0_RK0: MR19=0x808, MR18=0x673F, DQSOSC=390, MR23=63, INC=172, DEC=114
4242 11:13:12.557710
4243 11:13:12.561028 ----->DramcWriteLeveling(PI) begin...
4244 11:13:12.561133 ==
4245 11:13:12.564046 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 11:13:12.567524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 11:13:12.567633 ==
4248 11:13:12.570906 Write leveling (Byte 0): 34 => 34
4249 11:13:12.574258 Write leveling (Byte 1): 31 => 31
4250 11:13:12.577364 DramcWriteLeveling(PI) end<-----
4251 11:13:12.577473
4252 11:13:12.577566 ==
4253 11:13:12.580779 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 11:13:12.584439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 11:13:12.584585 ==
4256 11:13:12.587448 [Gating] SW mode calibration
4257 11:13:12.594194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4258 11:13:12.600944 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4259 11:13:12.603862 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4260 11:13:12.610549 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4261 11:13:12.614170 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4262 11:13:12.617063 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4263 11:13:12.623773 0 9 16 | B1->B0 | 2c2c 2727 | 1 0 | (1 0) (0 0)
4264 11:13:12.626928 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 11:13:12.630538 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 11:13:12.637160 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 11:13:12.640716 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 11:13:12.643797 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 11:13:12.650575 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 11:13:12.653608 0 10 12 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 0)
4271 11:13:12.656932 0 10 16 | B1->B0 | 4141 3f3f | 1 0 | (0 0) (0 0)
4272 11:13:12.660241 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 11:13:12.666842 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 11:13:12.670434 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 11:13:12.673333 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 11:13:12.679759 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 11:13:12.683195 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 11:13:12.686904 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4279 11:13:12.693582 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4280 11:13:12.696503 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 11:13:12.703101 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 11:13:12.706714 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 11:13:12.709940 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 11:13:12.716397 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 11:13:12.719506 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 11:13:12.723210 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 11:13:12.729315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 11:13:12.733054 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 11:13:12.736093 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 11:13:12.742828 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 11:13:12.745988 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 11:13:12.749447 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 11:13:12.756228 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 11:13:12.759238 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4295 11:13:12.762716 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4296 11:13:12.766151 Total UI for P1: 0, mck2ui 16
4297 11:13:12.769324 best dqsien dly found for B0: ( 0, 13, 12)
4298 11:13:12.772564 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 11:13:12.775995 Total UI for P1: 0, mck2ui 16
4300 11:13:12.779312 best dqsien dly found for B1: ( 0, 13, 14)
4301 11:13:12.785915 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4302 11:13:12.789692 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4303 11:13:12.790123
4304 11:13:12.792251 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4305 11:13:12.795647 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4306 11:13:12.798689 [Gating] SW calibration Done
4307 11:13:12.799099 ==
4308 11:13:12.802081 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 11:13:12.805456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 11:13:12.805727 ==
4311 11:13:12.808570 RX Vref Scan: 0
4312 11:13:12.808879
4313 11:13:12.809106 RX Vref 0 -> 0, step: 1
4314 11:13:12.809320
4315 11:13:12.812115 RX Delay -230 -> 252, step: 16
4316 11:13:12.815597 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4317 11:13:12.822052 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4318 11:13:12.825310 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4319 11:13:12.828385 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4320 11:13:12.832136 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4321 11:13:12.838222 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4322 11:13:12.841718 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4323 11:13:12.844690 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4324 11:13:12.848428 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4325 11:13:12.855021 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4326 11:13:12.858010 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4327 11:13:12.861591 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4328 11:13:12.864914 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4329 11:13:12.871363 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4330 11:13:12.874703 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4331 11:13:12.878186 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4332 11:13:12.878770 ==
4333 11:13:12.881417 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 11:13:12.884808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 11:13:12.887556 ==
4336 11:13:12.888129 DQS Delay:
4337 11:13:12.888708 DQS0 = 0, DQS1 = 0
4338 11:13:12.890850 DQM Delay:
4339 11:13:12.891374 DQM0 = 41, DQM1 = 36
4340 11:13:12.894641 DQ Delay:
4341 11:13:12.895159 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4342 11:13:12.897765 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4343 11:13:12.900976 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4344 11:13:12.904551 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4345 11:13:12.907689
4346 11:13:12.908184
4347 11:13:12.908710 ==
4348 11:13:12.910884 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 11:13:12.914334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 11:13:12.914940 ==
4351 11:13:12.915436
4352 11:13:12.915830
4353 11:13:12.917885 TX Vref Scan disable
4354 11:13:12.918494 == TX Byte 0 ==
4355 11:13:12.923994 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4356 11:13:12.927615 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4357 11:13:12.928108 == TX Byte 1 ==
4358 11:13:12.933623 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4359 11:13:12.937330 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4360 11:13:12.937671 ==
4361 11:13:12.940942 Dram Type= 6, Freq= 0, CH_0, rank 1
4362 11:13:12.944022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 11:13:12.944658 ==
4364 11:13:12.945010
4365 11:13:12.947094
4366 11:13:12.947650 TX Vref Scan disable
4367 11:13:12.950653 == TX Byte 0 ==
4368 11:13:12.954277 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4369 11:13:12.957147 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4370 11:13:12.960963 == TX Byte 1 ==
4371 11:13:12.963880 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4372 11:13:12.970702 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4373 11:13:12.971116
4374 11:13:12.971441 [DATLAT]
4375 11:13:12.971767 Freq=600, CH0 RK1
4376 11:13:12.972084
4377 11:13:12.974234 DATLAT Default: 0x9
4378 11:13:12.974712 0, 0xFFFF, sum = 0
4379 11:13:12.977034 1, 0xFFFF, sum = 0
4380 11:13:12.980501 2, 0xFFFF, sum = 0
4381 11:13:12.980989 3, 0xFFFF, sum = 0
4382 11:13:12.983798 4, 0xFFFF, sum = 0
4383 11:13:12.984217 5, 0xFFFF, sum = 0
4384 11:13:12.987025 6, 0xFFFF, sum = 0
4385 11:13:12.987477 7, 0xFFFF, sum = 0
4386 11:13:12.990401 8, 0x0, sum = 1
4387 11:13:12.990824 9, 0x0, sum = 2
4388 11:13:12.993498 10, 0x0, sum = 3
4389 11:13:12.993973 11, 0x0, sum = 4
4390 11:13:12.994333 best_step = 9
4391 11:13:12.994671
4392 11:13:12.996852 ==
4393 11:13:13.000128 Dram Type= 6, Freq= 0, CH_0, rank 1
4394 11:13:13.003621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 11:13:13.004064 ==
4396 11:13:13.004550 RX Vref Scan: 0
4397 11:13:13.005092
4398 11:13:13.006583 RX Vref 0 -> 0, step: 1
4399 11:13:13.006992
4400 11:13:13.010281 RX Delay -179 -> 252, step: 8
4401 11:13:13.016333 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4402 11:13:13.020165 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4403 11:13:13.023738 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4404 11:13:13.026485 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4405 11:13:13.030067 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4406 11:13:13.036638 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4407 11:13:13.040063 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4408 11:13:13.043388 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4409 11:13:13.046446 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4410 11:13:13.053026 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4411 11:13:13.056180 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4412 11:13:13.059817 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4413 11:13:13.062788 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4414 11:13:13.069495 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4415 11:13:13.073169 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4416 11:13:13.076211 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4417 11:13:13.076663 ==
4418 11:13:13.079212 Dram Type= 6, Freq= 0, CH_0, rank 1
4419 11:13:13.082717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 11:13:13.086226 ==
4421 11:13:13.086644 DQS Delay:
4422 11:13:13.086970 DQS0 = 0, DQS1 = 0
4423 11:13:13.089690 DQM Delay:
4424 11:13:13.090102 DQM0 = 41, DQM1 = 36
4425 11:13:13.092583 DQ Delay:
4426 11:13:13.092997 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4427 11:13:13.096161 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4428 11:13:13.099472 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4429 11:13:13.102392 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4430 11:13:13.102817
4431 11:13:13.105839
4432 11:13:13.112708 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e11, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4433 11:13:13.115904 CH0 RK1: MR19=808, MR18=5E11
4434 11:13:13.122510 CH0_RK1: MR19=0x808, MR18=0x5E11, DQSOSC=392, MR23=63, INC=170, DEC=113
4435 11:13:13.125514 [RxdqsGatingPostProcess] freq 600
4436 11:13:13.129091 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4437 11:13:13.131990 Pre-setting of DQS Precalculation
4438 11:13:13.138702 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4439 11:13:13.139126 ==
4440 11:13:13.142289 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 11:13:13.145173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 11:13:13.145600 ==
4443 11:13:13.151913 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4444 11:13:13.154938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4445 11:13:13.159806 [CA 0] Center 35 (5~66) winsize 62
4446 11:13:13.162791 [CA 1] Center 35 (5~66) winsize 62
4447 11:13:13.165983 [CA 2] Center 33 (3~64) winsize 62
4448 11:13:13.169473 [CA 3] Center 33 (3~64) winsize 62
4449 11:13:13.172570 [CA 4] Center 34 (3~65) winsize 63
4450 11:13:13.176208 [CA 5] Center 33 (3~64) winsize 62
4451 11:13:13.176672
4452 11:13:13.179182 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4453 11:13:13.179612
4454 11:13:13.182767 [CATrainingPosCal] consider 1 rank data
4455 11:13:13.185794 u2DelayCellTimex100 = 270/100 ps
4456 11:13:13.189246 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4457 11:13:13.195872 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4458 11:13:13.199063 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4459 11:13:13.202852 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4460 11:13:13.205557 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4461 11:13:13.209005 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4462 11:13:13.209474
4463 11:13:13.212503 CA PerBit enable=1, Macro0, CA PI delay=33
4464 11:13:13.212970
4465 11:13:13.215681 [CBTSetCACLKResult] CA Dly = 33
4466 11:13:13.219042 CS Dly: 4 (0~35)
4467 11:13:13.219465 ==
4468 11:13:13.222620 Dram Type= 6, Freq= 0, CH_1, rank 1
4469 11:13:13.225814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 11:13:13.226243 ==
4471 11:13:13.232263 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4472 11:13:13.235235 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4473 11:13:13.240009 [CA 0] Center 35 (5~66) winsize 62
4474 11:13:13.242797 [CA 1] Center 36 (6~66) winsize 61
4475 11:13:13.246426 [CA 2] Center 34 (3~65) winsize 63
4476 11:13:13.249446 [CA 3] Center 33 (3~64) winsize 62
4477 11:13:13.253177 [CA 4] Center 34 (4~65) winsize 62
4478 11:13:13.256146 [CA 5] Center 34 (3~65) winsize 63
4479 11:13:13.256628
4480 11:13:13.259765 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4481 11:13:13.260204
4482 11:13:13.262977 [CATrainingPosCal] consider 2 rank data
4483 11:13:13.266688 u2DelayCellTimex100 = 270/100 ps
4484 11:13:13.269551 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4485 11:13:13.273165 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4486 11:13:13.278965 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4487 11:13:13.282846 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4488 11:13:13.286306 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4489 11:13:13.288951 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4490 11:13:13.289096
4491 11:13:13.292607 CA PerBit enable=1, Macro0, CA PI delay=33
4492 11:13:13.293075
4493 11:13:13.296015 [CBTSetCACLKResult] CA Dly = 33
4494 11:13:13.296446 CS Dly: 4 (0~36)
4495 11:13:13.299552
4496 11:13:13.302400 ----->DramcWriteLeveling(PI) begin...
4497 11:13:13.302839 ==
4498 11:13:13.305958 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 11:13:13.309396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 11:13:13.309850 ==
4501 11:13:13.312249 Write leveling (Byte 0): 29 => 29
4502 11:13:13.315800 Write leveling (Byte 1): 31 => 31
4503 11:13:13.319538 DramcWriteLeveling(PI) end<-----
4504 11:13:13.319967
4505 11:13:13.320307 ==
4506 11:13:13.322508 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 11:13:13.325575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 11:13:13.326008 ==
4509 11:13:13.329351 [Gating] SW mode calibration
4510 11:13:13.335960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4511 11:13:13.341827 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4512 11:13:13.345605 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4513 11:13:13.348800 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4514 11:13:13.355680 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4515 11:13:13.358564 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4516 11:13:13.362211 0 9 16 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
4517 11:13:13.368826 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4518 11:13:13.371806 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 11:13:13.375507 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 11:13:13.382110 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 11:13:13.385291 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 11:13:13.388203 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 11:13:13.394943 0 10 12 | B1->B0 | 2d2d 3939 | 0 0 | (0 0) (0 0)
4524 11:13:13.398288 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 11:13:13.401817 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 11:13:13.408364 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 11:13:13.411909 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 11:13:13.414962 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 11:13:13.421826 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 11:13:13.424920 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 11:13:13.428286 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4532 11:13:13.435032 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 11:13:13.437879 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 11:13:13.441696 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 11:13:13.448568 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 11:13:13.451346 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 11:13:13.455104 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 11:13:13.461552 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 11:13:13.464430 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 11:13:13.468167 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 11:13:13.474737 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 11:13:13.477820 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 11:13:13.481267 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 11:13:13.487304 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 11:13:13.491073 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 11:13:13.494186 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 11:13:13.500864 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4548 11:13:13.504437 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4549 11:13:13.507678 Total UI for P1: 0, mck2ui 16
4550 11:13:13.510759 best dqsien dly found for B0: ( 0, 13, 12)
4551 11:13:13.514328 Total UI for P1: 0, mck2ui 16
4552 11:13:13.517709 best dqsien dly found for B1: ( 0, 13, 14)
4553 11:13:13.521192 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4554 11:13:13.524088 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4555 11:13:13.524513
4556 11:13:13.527440 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4557 11:13:13.530816 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4558 11:13:13.533927 [Gating] SW calibration Done
4559 11:13:13.534718 ==
4560 11:13:13.537345 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 11:13:13.540394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 11:13:13.544089 ==
4563 11:13:13.544659 RX Vref Scan: 0
4564 11:13:13.545004
4565 11:13:13.547053 RX Vref 0 -> 0, step: 1
4566 11:13:13.547476
4567 11:13:13.550136 RX Delay -230 -> 252, step: 16
4568 11:13:13.553741 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4569 11:13:13.556910 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4570 11:13:13.560494 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4571 11:13:13.566603 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4572 11:13:13.570091 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4573 11:13:13.573637 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4574 11:13:13.576655 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4575 11:13:13.579821 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4576 11:13:13.586537 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4577 11:13:13.590286 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4578 11:13:13.592956 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4579 11:13:13.596512 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4580 11:13:13.602707 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4581 11:13:13.606456 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4582 11:13:13.609698 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4583 11:13:13.612506 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4584 11:13:13.612612 ==
4585 11:13:13.616115 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 11:13:13.622487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 11:13:13.622571 ==
4588 11:13:13.622637 DQS Delay:
4589 11:13:13.626068 DQS0 = 0, DQS1 = 0
4590 11:13:13.626151 DQM Delay:
4591 11:13:13.629336 DQM0 = 46, DQM1 = 33
4592 11:13:13.629419 DQ Delay:
4593 11:13:13.632403 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4594 11:13:13.635861 DQ4 =33, DQ5 =65, DQ6 =65, DQ7 =41
4595 11:13:13.639320 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4596 11:13:13.642547 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =49
4597 11:13:13.642630
4598 11:13:13.642694
4599 11:13:13.642753 ==
4600 11:13:13.645580 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 11:13:13.649066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 11:13:13.649150 ==
4603 11:13:13.649215
4604 11:13:13.649275
4605 11:13:13.652141 TX Vref Scan disable
4606 11:13:13.655846 == TX Byte 0 ==
4607 11:13:13.658812 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4608 11:13:13.662455 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4609 11:13:13.665499 == TX Byte 1 ==
4610 11:13:13.668981 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4611 11:13:13.672056 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4612 11:13:13.672161 ==
4613 11:13:13.675757 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 11:13:13.682249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 11:13:13.682390 ==
4616 11:13:13.682499
4617 11:13:13.682591
4618 11:13:13.682686 TX Vref Scan disable
4619 11:13:13.685869 == TX Byte 0 ==
4620 11:13:13.689487 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4621 11:13:13.696335 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4622 11:13:13.696537 == TX Byte 1 ==
4623 11:13:13.699028 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4624 11:13:13.705699 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4625 11:13:13.705792
4626 11:13:13.705858 [DATLAT]
4627 11:13:13.705918 Freq=600, CH1 RK0
4628 11:13:13.705995
4629 11:13:13.708800 DATLAT Default: 0x9
4630 11:13:13.712309 0, 0xFFFF, sum = 0
4631 11:13:13.712390 1, 0xFFFF, sum = 0
4632 11:13:13.715720 2, 0xFFFF, sum = 0
4633 11:13:13.715795 3, 0xFFFF, sum = 0
4634 11:13:13.718505 4, 0xFFFF, sum = 0
4635 11:13:13.718578 5, 0xFFFF, sum = 0
4636 11:13:13.722146 6, 0xFFFF, sum = 0
4637 11:13:13.722219 7, 0xFFFF, sum = 0
4638 11:13:13.725133 8, 0x0, sum = 1
4639 11:13:13.725213 9, 0x0, sum = 2
4640 11:13:13.728738 10, 0x0, sum = 3
4641 11:13:13.728811 11, 0x0, sum = 4
4642 11:13:13.728880 best_step = 9
4643 11:13:13.731751
4644 11:13:13.731831 ==
4645 11:13:13.735107 Dram Type= 6, Freq= 0, CH_1, rank 0
4646 11:13:13.738773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 11:13:13.738851 ==
4648 11:13:13.738913 RX Vref Scan: 1
4649 11:13:13.738972
4650 11:13:13.742316 RX Vref 0 -> 0, step: 1
4651 11:13:13.742479
4652 11:13:13.745261 RX Delay -195 -> 252, step: 8
4653 11:13:13.745411
4654 11:13:13.748404 Set Vref, RX VrefLevel [Byte0]: 48
4655 11:13:13.751982 [Byte1]: 50
4656 11:13:13.755218
4657 11:13:13.755408 Final RX Vref Byte 0 = 48 to rank0
4658 11:13:13.758656 Final RX Vref Byte 1 = 50 to rank0
4659 11:13:13.761587 Final RX Vref Byte 0 = 48 to rank1
4660 11:13:13.765559 Final RX Vref Byte 1 = 50 to rank1==
4661 11:13:13.768836 Dram Type= 6, Freq= 0, CH_1, rank 0
4662 11:13:13.775475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 11:13:13.775926 ==
4664 11:13:13.776303 DQS Delay:
4665 11:13:13.776884 DQS0 = 0, DQS1 = 0
4666 11:13:13.778449 DQM Delay:
4667 11:13:13.778971 DQM0 = 45, DQM1 = 34
4668 11:13:13.781590 DQ Delay:
4669 11:13:13.785300 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4670 11:13:13.788289 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =44
4671 11:13:13.791979 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4672 11:13:13.794887 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4673 11:13:13.795442
4674 11:13:13.795951
4675 11:13:13.801632 [DQSOSCAuto] RK0, (LSB)MR18= 0x5338, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4676 11:13:13.804797 CH1 RK0: MR19=808, MR18=5338
4677 11:13:13.811500 CH1_RK0: MR19=0x808, MR18=0x5338, DQSOSC=394, MR23=63, INC=168, DEC=112
4678 11:13:13.811931
4679 11:13:13.814838 ----->DramcWriteLeveling(PI) begin...
4680 11:13:13.815279 ==
4681 11:13:13.817952 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 11:13:13.821808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 11:13:13.822240 ==
4684 11:13:13.824840 Write leveling (Byte 0): 28 => 28
4685 11:13:13.828358 Write leveling (Byte 1): 31 => 31
4686 11:13:13.831717 DramcWriteLeveling(PI) end<-----
4687 11:13:13.832140
4688 11:13:13.832470 ==
4689 11:13:13.834607 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 11:13:13.838186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 11:13:13.838615 ==
4692 11:13:13.841443 [Gating] SW mode calibration
4693 11:13:13.847984 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4694 11:13:13.854714 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4695 11:13:13.857834 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4696 11:13:13.864509 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4697 11:13:13.868107 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4698 11:13:13.871732 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (1 0) (1 0)
4699 11:13:13.878100 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4700 11:13:13.881062 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4701 11:13:13.884649 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4702 11:13:13.891019 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 11:13:13.894527 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 11:13:13.897528 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 11:13:13.904197 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 11:13:13.907793 0 10 12 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (0 0)
4707 11:13:13.910954 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4708 11:13:13.917347 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 11:13:13.920397 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 11:13:13.923985 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 11:13:13.930457 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 11:13:13.934018 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 11:13:13.936978 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 11:13:13.943860 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 11:13:13.946815 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 11:13:13.950152 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 11:13:13.956461 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 11:13:13.959649 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 11:13:13.963448 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 11:13:13.969577 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 11:13:13.973192 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 11:13:13.976779 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 11:13:13.983353 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 11:13:13.986596 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 11:13:13.989554 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 11:13:13.996279 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 11:13:13.999489 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 11:13:14.003488 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 11:13:14.009273 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 11:13:14.012955 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4731 11:13:14.016122 Total UI for P1: 0, mck2ui 16
4732 11:13:14.019107 best dqsien dly found for B1: ( 0, 13, 10)
4733 11:13:14.023079 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4734 11:13:14.025875 Total UI for P1: 0, mck2ui 16
4735 11:13:14.029492 best dqsien dly found for B0: ( 0, 13, 12)
4736 11:13:14.032599 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4737 11:13:14.036141 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4738 11:13:14.036614
4739 11:13:14.042906 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4740 11:13:14.045805 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4741 11:13:14.046268 [Gating] SW calibration Done
4742 11:13:14.049225 ==
4743 11:13:14.052500 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 11:13:14.055896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 11:13:14.056336 ==
4746 11:13:14.056823 RX Vref Scan: 0
4747 11:13:14.057237
4748 11:13:14.058842 RX Vref 0 -> 0, step: 1
4749 11:13:14.059292
4750 11:13:14.062252 RX Delay -230 -> 252, step: 16
4751 11:13:14.065950 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4752 11:13:14.068946 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4753 11:13:14.075653 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4754 11:13:14.078688 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4755 11:13:14.082429 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4756 11:13:14.085363 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4757 11:13:14.092419 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4758 11:13:14.095375 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4759 11:13:14.098554 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4760 11:13:14.102081 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4761 11:13:14.108811 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4762 11:13:14.111636 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4763 11:13:14.115353 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4764 11:13:14.118184 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4765 11:13:14.125384 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4766 11:13:14.128104 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4767 11:13:14.128799 ==
4768 11:13:14.131598 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 11:13:14.134863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 11:13:14.135321 ==
4771 11:13:14.138242 DQS Delay:
4772 11:13:14.138668 DQS0 = 0, DQS1 = 0
4773 11:13:14.139006 DQM Delay:
4774 11:13:14.141748 DQM0 = 41, DQM1 = 35
4775 11:13:14.142177 DQ Delay:
4776 11:13:14.145077 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4777 11:13:14.147852 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4778 11:13:14.151521 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4779 11:13:14.154787 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4780 11:13:14.155250
4781 11:13:14.155825
4782 11:13:14.156219 ==
4783 11:13:14.157869 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 11:13:14.164302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 11:13:14.164778 ==
4786 11:13:14.165141
4787 11:13:14.165522
4788 11:13:14.165910 TX Vref Scan disable
4789 11:13:14.168082 == TX Byte 0 ==
4790 11:13:14.171304 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4791 11:13:14.178074 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4792 11:13:14.178640 == TX Byte 1 ==
4793 11:13:14.181526 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4794 11:13:14.188285 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4795 11:13:14.188918 ==
4796 11:13:14.191669 Dram Type= 6, Freq= 0, CH_1, rank 1
4797 11:13:14.194820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4798 11:13:14.195250 ==
4799 11:13:14.195584
4800 11:13:14.195922
4801 11:13:14.197903 TX Vref Scan disable
4802 11:13:14.201540 == TX Byte 0 ==
4803 11:13:14.204389 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4804 11:13:14.208201 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4805 11:13:14.211156 == TX Byte 1 ==
4806 11:13:14.214992 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4807 11:13:14.218307 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4808 11:13:14.218869
4809 11:13:14.219332 [DATLAT]
4810 11:13:14.221469 Freq=600, CH1 RK1
4811 11:13:14.221918
4812 11:13:14.222258 DATLAT Default: 0x9
4813 11:13:14.224441 0, 0xFFFF, sum = 0
4814 11:13:14.228248 1, 0xFFFF, sum = 0
4815 11:13:14.228721 2, 0xFFFF, sum = 0
4816 11:13:14.231237 3, 0xFFFF, sum = 0
4817 11:13:14.231689 4, 0xFFFF, sum = 0
4818 11:13:14.234974 5, 0xFFFF, sum = 0
4819 11:13:14.235738 6, 0xFFFF, sum = 0
4820 11:13:14.237853 7, 0xFFFF, sum = 0
4821 11:13:14.238495 8, 0x0, sum = 1
4822 11:13:14.241525 9, 0x0, sum = 2
4823 11:13:14.242099 10, 0x0, sum = 3
4824 11:13:14.244182 11, 0x0, sum = 4
4825 11:13:14.244677 best_step = 9
4826 11:13:14.245021
4827 11:13:14.245401 ==
4828 11:13:14.247654 Dram Type= 6, Freq= 0, CH_1, rank 1
4829 11:13:14.250976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4830 11:13:14.251431 ==
4831 11:13:14.254364 RX Vref Scan: 0
4832 11:13:14.254977
4833 11:13:14.257503 RX Vref 0 -> 0, step: 1
4834 11:13:14.257941
4835 11:13:14.258512 RX Delay -195 -> 252, step: 8
4836 11:13:14.265359 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4837 11:13:14.268852 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4838 11:13:14.271768 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4839 11:13:14.275283 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4840 11:13:14.281668 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4841 11:13:14.285286 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4842 11:13:14.288373 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4843 11:13:14.291791 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4844 11:13:14.294803 iDelay=213, Bit 8, Center 20 (-139 ~ 180) 320
4845 11:13:14.301315 iDelay=213, Bit 9, Center 20 (-139 ~ 180) 320
4846 11:13:14.305045 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4847 11:13:14.308008 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4848 11:13:14.311513 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4849 11:13:14.318202 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4850 11:13:14.321218 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4851 11:13:14.324762 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4852 11:13:14.324868 ==
4853 11:13:14.327877 Dram Type= 6, Freq= 0, CH_1, rank 1
4854 11:13:14.331567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4855 11:13:14.334435 ==
4856 11:13:14.334557 DQS Delay:
4857 11:13:14.334623 DQS0 = 0, DQS1 = 0
4858 11:13:14.338156 DQM Delay:
4859 11:13:14.338299 DQM0 = 42, DQM1 = 34
4860 11:13:14.341238 DQ Delay:
4861 11:13:14.344281 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4862 11:13:14.344414 DQ4 =40, DQ5 =56, DQ6 =56, DQ7 =40
4863 11:13:14.348041 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4864 11:13:14.351486 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =48
4865 11:13:14.354332
4866 11:13:14.354422
4867 11:13:14.361120 [DQSOSCAuto] RK1, (LSB)MR18= 0x3328, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4868 11:13:14.364129 CH1 RK1: MR19=808, MR18=3328
4869 11:13:14.370507 CH1_RK1: MR19=0x808, MR18=0x3328, DQSOSC=400, MR23=63, INC=163, DEC=109
4870 11:13:14.373929 [RxdqsGatingPostProcess] freq 600
4871 11:13:14.377396 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4872 11:13:14.380361 Pre-setting of DQS Precalculation
4873 11:13:14.387322 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4874 11:13:14.393877 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4875 11:13:14.400440 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4876 11:13:14.400558
4877 11:13:14.400644
4878 11:13:14.403981 [Calibration Summary] 1200 Mbps
4879 11:13:14.404097 CH 0, Rank 0
4880 11:13:14.406850 SW Impedance : PASS
4881 11:13:14.410462 DUTY Scan : NO K
4882 11:13:14.410561 ZQ Calibration : PASS
4883 11:13:14.413673 Jitter Meter : NO K
4884 11:13:14.416643 CBT Training : PASS
4885 11:13:14.416735 Write leveling : PASS
4886 11:13:14.420227 RX DQS gating : PASS
4887 11:13:14.423369 RX DQ/DQS(RDDQC) : PASS
4888 11:13:14.423463 TX DQ/DQS : PASS
4889 11:13:14.426790 RX DATLAT : PASS
4890 11:13:14.429841 RX DQ/DQS(Engine): PASS
4891 11:13:14.429936 TX OE : NO K
4892 11:13:14.433396 All Pass.
4893 11:13:14.433488
4894 11:13:14.433559 CH 0, Rank 1
4895 11:13:14.436311 SW Impedance : PASS
4896 11:13:14.436401 DUTY Scan : NO K
4897 11:13:14.439550 ZQ Calibration : PASS
4898 11:13:14.443117 Jitter Meter : NO K
4899 11:13:14.443207 CBT Training : PASS
4900 11:13:14.446803 Write leveling : PASS
4901 11:13:14.449527 RX DQS gating : PASS
4902 11:13:14.449619 RX DQ/DQS(RDDQC) : PASS
4903 11:13:14.453242 TX DQ/DQS : PASS
4904 11:13:14.456001 RX DATLAT : PASS
4905 11:13:14.456084 RX DQ/DQS(Engine): PASS
4906 11:13:14.459566 TX OE : NO K
4907 11:13:14.459650 All Pass.
4908 11:13:14.459716
4909 11:13:14.462582 CH 1, Rank 0
4910 11:13:14.462664 SW Impedance : PASS
4911 11:13:14.466144 DUTY Scan : NO K
4912 11:13:14.469173 ZQ Calibration : PASS
4913 11:13:14.469256 Jitter Meter : NO K
4914 11:13:14.472744 CBT Training : PASS
4915 11:13:14.476389 Write leveling : PASS
4916 11:13:14.476861 RX DQS gating : PASS
4917 11:13:14.479280 RX DQ/DQS(RDDQC) : PASS
4918 11:13:14.479702 TX DQ/DQS : PASS
4919 11:13:14.482544 RX DATLAT : PASS
4920 11:13:14.486165 RX DQ/DQS(Engine): PASS
4921 11:13:14.486598 TX OE : NO K
4922 11:13:14.489945 All Pass.
4923 11:13:14.490367
4924 11:13:14.490700 CH 1, Rank 1
4925 11:13:14.492928 SW Impedance : PASS
4926 11:13:14.493351 DUTY Scan : NO K
4927 11:13:14.495817 ZQ Calibration : PASS
4928 11:13:14.499585 Jitter Meter : NO K
4929 11:13:14.500009 CBT Training : PASS
4930 11:13:14.503112 Write leveling : PASS
4931 11:13:14.506039 RX DQS gating : PASS
4932 11:13:14.506462 RX DQ/DQS(RDDQC) : PASS
4933 11:13:14.509668 TX DQ/DQS : PASS
4934 11:13:14.512659 RX DATLAT : PASS
4935 11:13:14.513088 RX DQ/DQS(Engine): PASS
4936 11:13:14.515932 TX OE : NO K
4937 11:13:14.516361 All Pass.
4938 11:13:14.516725
4939 11:13:14.519319 DramC Write-DBI off
4940 11:13:14.522418 PER_BANK_REFRESH: Hybrid Mode
4941 11:13:14.522845 TX_TRACKING: ON
4942 11:13:14.532755 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4943 11:13:14.535814 [FAST_K] Save calibration result to emmc
4944 11:13:14.539140 dramc_set_vcore_voltage set vcore to 662500
4945 11:13:14.542349 Read voltage for 933, 3
4946 11:13:14.542778 Vio18 = 0
4947 11:13:14.543144 Vcore = 662500
4948 11:13:14.545948 Vdram = 0
4949 11:13:14.546455 Vddq = 0
4950 11:13:14.546895 Vmddr = 0
4951 11:13:14.551898 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4952 11:13:14.555282 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4953 11:13:14.558286 MEM_TYPE=3, freq_sel=17
4954 11:13:14.561761 sv_algorithm_assistance_LP4_1600
4955 11:13:14.565122 ============ PULL DRAM RESETB DOWN ============
4956 11:13:14.572070 ========== PULL DRAM RESETB DOWN end =========
4957 11:13:14.574967 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4958 11:13:14.578407 ===================================
4959 11:13:14.581852 LPDDR4 DRAM CONFIGURATION
4960 11:13:14.584671 ===================================
4961 11:13:14.584786 EX_ROW_EN[0] = 0x0
4962 11:13:14.588102 EX_ROW_EN[1] = 0x0
4963 11:13:14.588205 LP4Y_EN = 0x0
4964 11:13:14.591766 WORK_FSP = 0x0
4965 11:13:14.591854 WL = 0x3
4966 11:13:14.594696 RL = 0x3
4967 11:13:14.594809 BL = 0x2
4968 11:13:14.598454 RPST = 0x0
4969 11:13:14.598540 RD_PRE = 0x0
4970 11:13:14.601533 WR_PRE = 0x1
4971 11:13:14.601616 WR_PST = 0x0
4972 11:13:14.604513 DBI_WR = 0x0
4973 11:13:14.608027 DBI_RD = 0x0
4974 11:13:14.608110 OTF = 0x1
4975 11:13:14.611782 ===================================
4976 11:13:14.614877 ===================================
4977 11:13:14.614960 ANA top config
4978 11:13:14.617821 ===================================
4979 11:13:14.621699 DLL_ASYNC_EN = 0
4980 11:13:14.624503 ALL_SLAVE_EN = 1
4981 11:13:14.628073 NEW_RANK_MODE = 1
4982 11:13:14.631130 DLL_IDLE_MODE = 1
4983 11:13:14.631219 LP45_APHY_COMB_EN = 1
4984 11:13:14.634782 TX_ODT_DIS = 1
4985 11:13:14.637892 NEW_8X_MODE = 1
4986 11:13:14.640830 ===================================
4987 11:13:14.644453 ===================================
4988 11:13:14.647537 data_rate = 1866
4989 11:13:14.651119 CKR = 1
4990 11:13:14.651243 DQ_P2S_RATIO = 8
4991 11:13:14.654148 ===================================
4992 11:13:14.657884 CA_P2S_RATIO = 8
4993 11:13:14.661286 DQ_CA_OPEN = 0
4994 11:13:14.664117 DQ_SEMI_OPEN = 0
4995 11:13:14.667754 CA_SEMI_OPEN = 0
4996 11:13:14.670619 CA_FULL_RATE = 0
4997 11:13:14.670846 DQ_CKDIV4_EN = 1
4998 11:13:14.674175 CA_CKDIV4_EN = 1
4999 11:13:14.677661 CA_PREDIV_EN = 0
5000 11:13:14.681000 PH8_DLY = 0
5001 11:13:14.684560 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5002 11:13:14.687178 DQ_AAMCK_DIV = 4
5003 11:13:14.687507 CA_AAMCK_DIV = 4
5004 11:13:14.690722 CA_ADMCK_DIV = 4
5005 11:13:14.694366 DQ_TRACK_CA_EN = 0
5006 11:13:14.697183 CA_PICK = 933
5007 11:13:14.700819 CA_MCKIO = 933
5008 11:13:14.703898 MCKIO_SEMI = 0
5009 11:13:14.706922 PLL_FREQ = 3732
5010 11:13:14.710460 DQ_UI_PI_RATIO = 32
5011 11:13:14.710642 CA_UI_PI_RATIO = 0
5012 11:13:14.713766 ===================================
5013 11:13:14.716828 ===================================
5014 11:13:14.720354 memory_type:LPDDR4
5015 11:13:14.723524 GP_NUM : 10
5016 11:13:14.723701 SRAM_EN : 1
5017 11:13:14.727106 MD32_EN : 0
5018 11:13:14.729931 ===================================
5019 11:13:14.733631 [ANA_INIT] >>>>>>>>>>>>>>
5020 11:13:14.736519 <<<<<< [CONFIGURE PHASE]: ANA_TX
5021 11:13:14.740010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5022 11:13:14.743218 ===================================
5023 11:13:14.743327 data_rate = 1866,PCW = 0X8f00
5024 11:13:14.746810 ===================================
5025 11:13:14.750104 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5026 11:13:14.756712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5027 11:13:14.763320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5028 11:13:14.766814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5029 11:13:14.769732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5030 11:13:14.773256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5031 11:13:14.776705 [ANA_INIT] flow start
5032 11:13:14.779618 [ANA_INIT] PLL >>>>>>>>
5033 11:13:14.779734 [ANA_INIT] PLL <<<<<<<<
5034 11:13:14.783304 [ANA_INIT] MIDPI >>>>>>>>
5035 11:13:14.786687 [ANA_INIT] MIDPI <<<<<<<<
5036 11:13:14.786843 [ANA_INIT] DLL >>>>>>>>
5037 11:13:14.789754 [ANA_INIT] flow end
5038 11:13:14.793180 ============ LP4 DIFF to SE enter ============
5039 11:13:14.796593 ============ LP4 DIFF to SE exit ============
5040 11:13:14.799405 [ANA_INIT] <<<<<<<<<<<<<
5041 11:13:14.803177 [Flow] Enable top DCM control >>>>>
5042 11:13:14.806444 [Flow] Enable top DCM control <<<<<
5043 11:13:14.809820 Enable DLL master slave shuffle
5044 11:13:14.816479 ==============================================================
5045 11:13:14.816944 Gating Mode config
5046 11:13:14.822896 ==============================================================
5047 11:13:14.826653 Config description:
5048 11:13:14.833432 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5049 11:13:14.839294 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5050 11:13:14.846704 SELPH_MODE 0: By rank 1: By Phase
5051 11:13:14.852734 ==============================================================
5052 11:13:14.853252 GAT_TRACK_EN = 1
5053 11:13:14.856400 RX_GATING_MODE = 2
5054 11:13:14.859549 RX_GATING_TRACK_MODE = 2
5055 11:13:14.863064 SELPH_MODE = 1
5056 11:13:14.866120 PICG_EARLY_EN = 1
5057 11:13:14.869552 VALID_LAT_VALUE = 1
5058 11:13:14.876041 ==============================================================
5059 11:13:14.879577 Enter into Gating configuration >>>>
5060 11:13:14.882388 Exit from Gating configuration <<<<
5061 11:13:14.885845 Enter into DVFS_PRE_config >>>>>
5062 11:13:14.895564 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5063 11:13:14.899271 Exit from DVFS_PRE_config <<<<<
5064 11:13:14.902209 Enter into PICG configuration >>>>
5065 11:13:14.905626 Exit from PICG configuration <<<<
5066 11:13:14.909193 [RX_INPUT] configuration >>>>>
5067 11:13:14.912352 [RX_INPUT] configuration <<<<<
5068 11:13:14.915400 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5069 11:13:14.922048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5070 11:13:14.929051 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5071 11:13:14.931871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5072 11:13:14.938520 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5073 11:13:14.945292 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5074 11:13:14.948908 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5075 11:13:14.955149 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5076 11:13:14.958271 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5077 11:13:14.961850 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5078 11:13:14.965026 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5079 11:13:14.971595 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5080 11:13:14.975108 ===================================
5081 11:13:14.975588 LPDDR4 DRAM CONFIGURATION
5082 11:13:14.978327 ===================================
5083 11:13:14.981517 EX_ROW_EN[0] = 0x0
5084 11:13:14.984989 EX_ROW_EN[1] = 0x0
5085 11:13:14.985458 LP4Y_EN = 0x0
5086 11:13:14.988358 WORK_FSP = 0x0
5087 11:13:14.988869 WL = 0x3
5088 11:13:14.991117 RL = 0x3
5089 11:13:14.991637 BL = 0x2
5090 11:13:14.994542 RPST = 0x0
5091 11:13:14.995112 RD_PRE = 0x0
5092 11:13:14.998152 WR_PRE = 0x1
5093 11:13:14.998584 WR_PST = 0x0
5094 11:13:15.001368 DBI_WR = 0x0
5095 11:13:15.001799 DBI_RD = 0x0
5096 11:13:15.004464 OTF = 0x1
5097 11:13:15.007914 ===================================
5098 11:13:15.011503 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5099 11:13:15.014727 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5100 11:13:15.021345 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5101 11:13:15.024384 ===================================
5102 11:13:15.024882 LPDDR4 DRAM CONFIGURATION
5103 11:13:15.027728 ===================================
5104 11:13:15.030806 EX_ROW_EN[0] = 0x10
5105 11:13:15.034455 EX_ROW_EN[1] = 0x0
5106 11:13:15.034903 LP4Y_EN = 0x0
5107 11:13:15.038257 WORK_FSP = 0x0
5108 11:13:15.038687 WL = 0x3
5109 11:13:15.041068 RL = 0x3
5110 11:13:15.041537 BL = 0x2
5111 11:13:15.044272 RPST = 0x0
5112 11:13:15.044755 RD_PRE = 0x0
5113 11:13:15.047699 WR_PRE = 0x1
5114 11:13:15.048124 WR_PST = 0x0
5115 11:13:15.050772 DBI_WR = 0x0
5116 11:13:15.051227 DBI_RD = 0x0
5117 11:13:15.054390 OTF = 0x1
5118 11:13:15.057462 ===================================
5119 11:13:15.064139 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5120 11:13:15.068054 nWR fixed to 30
5121 11:13:15.070647 [ModeRegInit_LP4] CH0 RK0
5122 11:13:15.071080 [ModeRegInit_LP4] CH0 RK1
5123 11:13:15.073990 [ModeRegInit_LP4] CH1 RK0
5124 11:13:15.077411 [ModeRegInit_LP4] CH1 RK1
5125 11:13:15.077859 match AC timing 9
5126 11:13:15.083853 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5127 11:13:15.087255 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5128 11:13:15.090306 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5129 11:13:15.097095 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5130 11:13:15.100428 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5131 11:13:15.100923 ==
5132 11:13:15.103307 Dram Type= 6, Freq= 0, CH_0, rank 0
5133 11:13:15.106959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5134 11:13:15.107391 ==
5135 11:13:15.113380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5136 11:13:15.120305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5137 11:13:15.123568 [CA 0] Center 37 (7~68) winsize 62
5138 11:13:15.126630 [CA 1] Center 37 (7~68) winsize 62
5139 11:13:15.130224 [CA 2] Center 34 (4~65) winsize 62
5140 11:13:15.133735 [CA 3] Center 34 (4~65) winsize 62
5141 11:13:15.136588 [CA 4] Center 33 (3~64) winsize 62
5142 11:13:15.139709 [CA 5] Center 33 (3~63) winsize 61
5143 11:13:15.140216
5144 11:13:15.143306 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5145 11:13:15.143735
5146 11:13:15.146311 [CATrainingPosCal] consider 1 rank data
5147 11:13:15.149902 u2DelayCellTimex100 = 270/100 ps
5148 11:13:15.153124 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5149 11:13:15.156777 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5150 11:13:15.159722 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5151 11:13:15.163394 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5152 11:13:15.166902 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5153 11:13:15.173409 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5154 11:13:15.173945
5155 11:13:15.176342 CA PerBit enable=1, Macro0, CA PI delay=33
5156 11:13:15.176959
5157 11:13:15.179762 [CBTSetCACLKResult] CA Dly = 33
5158 11:13:15.180184 CS Dly: 7 (0~38)
5159 11:13:15.180552 ==
5160 11:13:15.182771 Dram Type= 6, Freq= 0, CH_0, rank 1
5161 11:13:15.186399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 11:13:15.189806 ==
5163 11:13:15.192832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5164 11:13:15.199611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5165 11:13:15.202689 [CA 0] Center 37 (7~68) winsize 62
5166 11:13:15.206224 [CA 1] Center 37 (7~68) winsize 62
5167 11:13:15.209747 [CA 2] Center 34 (4~65) winsize 62
5168 11:13:15.212424 [CA 3] Center 34 (4~65) winsize 62
5169 11:13:15.216106 [CA 4] Center 33 (3~64) winsize 62
5170 11:13:15.219566 [CA 5] Center 33 (3~63) winsize 61
5171 11:13:15.220002
5172 11:13:15.222667 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5173 11:13:15.223103
5174 11:13:15.225661 [CATrainingPosCal] consider 2 rank data
5175 11:13:15.229280 u2DelayCellTimex100 = 270/100 ps
5176 11:13:15.232031 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5177 11:13:15.235588 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5178 11:13:15.238572 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5179 11:13:15.245904 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5180 11:13:15.248858 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5181 11:13:15.252150 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5182 11:13:15.252622
5183 11:13:15.255815 CA PerBit enable=1, Macro0, CA PI delay=33
5184 11:13:15.256253
5185 11:13:15.258785 [CBTSetCACLKResult] CA Dly = 33
5186 11:13:15.259222 CS Dly: 7 (0~39)
5187 11:13:15.259654
5188 11:13:15.262517 ----->DramcWriteLeveling(PI) begin...
5189 11:13:15.265732 ==
5190 11:13:15.268596 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 11:13:15.272289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 11:13:15.272818 ==
5193 11:13:15.275156 Write leveling (Byte 0): 34 => 34
5194 11:13:15.278757 Write leveling (Byte 1): 29 => 29
5195 11:13:15.281960 DramcWriteLeveling(PI) end<-----
5196 11:13:15.282395
5197 11:13:15.282828 ==
5198 11:13:15.285502 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 11:13:15.288357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 11:13:15.288851 ==
5201 11:13:15.291792 [Gating] SW mode calibration
5202 11:13:15.298457 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5203 11:13:15.305277 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5204 11:13:15.307974 0 14 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
5205 11:13:15.311367 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5206 11:13:15.318287 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5207 11:13:15.321739 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 11:13:15.324827 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 11:13:15.331484 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 11:13:15.334551 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 11:13:15.338166 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5212 11:13:15.344710 0 15 0 | B1->B0 | 3232 2828 | 1 0 | (1 0) (1 0)
5213 11:13:15.348177 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5214 11:13:15.351056 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 11:13:15.358205 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 11:13:15.361395 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 11:13:15.364470 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 11:13:15.371167 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 11:13:15.374330 0 15 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5220 11:13:15.377855 1 0 0 | B1->B0 | 3030 4343 | 0 0 | (1 1) (0 0)
5221 11:13:15.384675 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 11:13:15.387712 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 11:13:15.390812 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 11:13:15.397930 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 11:13:15.401449 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 11:13:15.403870 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 11:13:15.410759 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5228 11:13:15.414550 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5229 11:13:15.417522 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5230 11:13:15.423922 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 11:13:15.427330 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 11:13:15.430401 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 11:13:15.437265 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 11:13:15.440330 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 11:13:15.443251 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 11:13:15.450061 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 11:13:15.453887 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 11:13:15.456799 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 11:13:15.463331 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 11:13:15.466562 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 11:13:15.470366 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 11:13:15.476354 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5243 11:13:15.479732 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5244 11:13:15.482885 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5245 11:13:15.486443 Total UI for P1: 0, mck2ui 16
5246 11:13:15.489377 best dqsien dly found for B0: ( 1, 2, 26)
5247 11:13:15.496071 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5248 11:13:15.496503 Total UI for P1: 0, mck2ui 16
5249 11:13:15.502623 best dqsien dly found for B1: ( 1, 3, 0)
5250 11:13:15.506024 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5251 11:13:15.509121 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5252 11:13:15.509699
5253 11:13:15.512952 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5254 11:13:15.515793 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5255 11:13:15.519010 [Gating] SW calibration Done
5256 11:13:15.519567 ==
5257 11:13:15.522575 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 11:13:15.526156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 11:13:15.526734 ==
5260 11:13:15.528900 RX Vref Scan: 0
5261 11:13:15.529350
5262 11:13:15.529689 RX Vref 0 -> 0, step: 1
5263 11:13:15.530039
5264 11:13:15.532554 RX Delay -80 -> 252, step: 8
5265 11:13:15.535972 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5266 11:13:15.542214 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5267 11:13:15.545706 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5268 11:13:15.548731 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5269 11:13:15.552501 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5270 11:13:15.555560 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5271 11:13:15.559034 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5272 11:13:15.565682 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5273 11:13:15.569219 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5274 11:13:15.572418 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5275 11:13:15.575434 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5276 11:13:15.579149 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5277 11:13:15.585243 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5278 11:13:15.588971 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5279 11:13:15.592037 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5280 11:13:15.595532 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5281 11:13:15.595979 ==
5282 11:13:15.598594 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 11:13:15.601564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 11:13:15.605027 ==
5285 11:13:15.605581 DQS Delay:
5286 11:13:15.606108 DQS0 = 0, DQS1 = 0
5287 11:13:15.608626 DQM Delay:
5288 11:13:15.609056 DQM0 = 97, DQM1 = 87
5289 11:13:15.612085 DQ Delay:
5290 11:13:15.615047 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5291 11:13:15.618459 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5292 11:13:15.621454 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5293 11:13:15.624823 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5294 11:13:15.625262
5295 11:13:15.625615
5296 11:13:15.625929 ==
5297 11:13:15.628216 Dram Type= 6, Freq= 0, CH_0, rank 0
5298 11:13:15.631603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 11:13:15.632036 ==
5300 11:13:15.632400
5301 11:13:15.632766
5302 11:13:15.634836 TX Vref Scan disable
5303 11:13:15.635408 == TX Byte 0 ==
5304 11:13:15.641349 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5305 11:13:15.644348 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5306 11:13:15.644934 == TX Byte 1 ==
5307 11:13:15.651477 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5308 11:13:15.654489 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5309 11:13:15.654953 ==
5310 11:13:15.657541 Dram Type= 6, Freq= 0, CH_0, rank 0
5311 11:13:15.661054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 11:13:15.664568 ==
5313 11:13:15.664998
5314 11:13:15.665331
5315 11:13:15.665676 TX Vref Scan disable
5316 11:13:15.667608 == TX Byte 0 ==
5317 11:13:15.671158 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5318 11:13:15.677360 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5319 11:13:15.677908 == TX Byte 1 ==
5320 11:13:15.680754 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5321 11:13:15.687436 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5322 11:13:15.688025
5323 11:13:15.688551 [DATLAT]
5324 11:13:15.688928 Freq=933, CH0 RK0
5325 11:13:15.689331
5326 11:13:15.690527 DATLAT Default: 0xd
5327 11:13:15.694229 0, 0xFFFF, sum = 0
5328 11:13:15.694823 1, 0xFFFF, sum = 0
5329 11:13:15.697441 2, 0xFFFF, sum = 0
5330 11:13:15.697946 3, 0xFFFF, sum = 0
5331 11:13:15.700327 4, 0xFFFF, sum = 0
5332 11:13:15.700832 5, 0xFFFF, sum = 0
5333 11:13:15.704051 6, 0xFFFF, sum = 0
5334 11:13:15.704488 7, 0xFFFF, sum = 0
5335 11:13:15.707181 8, 0xFFFF, sum = 0
5336 11:13:15.707648 9, 0xFFFF, sum = 0
5337 11:13:15.710221 10, 0x0, sum = 1
5338 11:13:15.710670 11, 0x0, sum = 2
5339 11:13:15.713509 12, 0x0, sum = 3
5340 11:13:15.714078 13, 0x0, sum = 4
5341 11:13:15.717009 best_step = 11
5342 11:13:15.717642
5343 11:13:15.718206 ==
5344 11:13:15.720085 Dram Type= 6, Freq= 0, CH_0, rank 0
5345 11:13:15.723509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 11:13:15.724084 ==
5347 11:13:15.724621 RX Vref Scan: 1
5348 11:13:15.726978
5349 11:13:15.727538 RX Vref 0 -> 0, step: 1
5350 11:13:15.728027
5351 11:13:15.729929 RX Delay -61 -> 252, step: 4
5352 11:13:15.730457
5353 11:13:15.733414 Set Vref, RX VrefLevel [Byte0]: 59
5354 11:13:15.736948 [Byte1]: 47
5355 11:13:15.740347
5356 11:13:15.740861 Final RX Vref Byte 0 = 59 to rank0
5357 11:13:15.743322 Final RX Vref Byte 1 = 47 to rank0
5358 11:13:15.746666 Final RX Vref Byte 0 = 59 to rank1
5359 11:13:15.750247 Final RX Vref Byte 1 = 47 to rank1==
5360 11:13:15.753540 Dram Type= 6, Freq= 0, CH_0, rank 0
5361 11:13:15.759866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 11:13:15.760317 ==
5363 11:13:15.760801 DQS Delay:
5364 11:13:15.763478 DQS0 = 0, DQS1 = 0
5365 11:13:15.763889 DQM Delay:
5366 11:13:15.764311 DQM0 = 97, DQM1 = 84
5367 11:13:15.766426 DQ Delay:
5368 11:13:15.770225 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5369 11:13:15.773063 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5370 11:13:15.776693 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =80
5371 11:13:15.779768 DQ12 =90, DQ13 =88, DQ14 =94, DQ15 =92
5372 11:13:15.780232
5373 11:13:15.780792
5374 11:13:15.786965 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5375 11:13:15.790176 CH0 RK0: MR19=505, MR18=2A11
5376 11:13:15.796903 CH0_RK0: MR19=0x505, MR18=0x2A11, DQSOSC=408, MR23=63, INC=65, DEC=43
5377 11:13:15.797393
5378 11:13:15.799912 ----->DramcWriteLeveling(PI) begin...
5379 11:13:15.800411 ==
5380 11:13:15.803515 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 11:13:15.806590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 11:13:15.807246 ==
5383 11:13:15.809511 Write leveling (Byte 0): 33 => 33
5384 11:13:15.813188 Write leveling (Byte 1): 33 => 33
5385 11:13:15.816448 DramcWriteLeveling(PI) end<-----
5386 11:13:15.817056
5387 11:13:15.817452 ==
5388 11:13:15.820095 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 11:13:15.822925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 11:13:15.823489 ==
5391 11:13:15.826562 [Gating] SW mode calibration
5392 11:13:15.833057 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5393 11:13:15.839356 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5394 11:13:15.842829 0 14 0 | B1->B0 | 2b2b 3131 | 1 1 | (1 1) (1 1)
5395 11:13:15.849682 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5396 11:13:15.852654 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5397 11:13:15.856200 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 11:13:15.862329 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 11:13:15.865864 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 11:13:15.868841 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 11:13:15.875596 0 14 28 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 0)
5402 11:13:15.879126 0 15 0 | B1->B0 | 3030 2b2b | 1 1 | (1 1) (0 0)
5403 11:13:15.882085 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 11:13:15.888620 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5405 11:13:15.891780 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 11:13:15.895511 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 11:13:15.902111 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 11:13:15.905253 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 11:13:15.908743 0 15 28 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
5410 11:13:15.915357 1 0 0 | B1->B0 | 4141 4343 | 0 0 | (0 0) (0 0)
5411 11:13:15.918264 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 11:13:15.921530 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 11:13:15.928008 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 11:13:15.931600 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 11:13:15.935083 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 11:13:15.941488 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 11:13:15.944849 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5418 11:13:15.948512 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5419 11:13:15.954619 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5420 11:13:15.958084 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 11:13:15.961022 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 11:13:15.967791 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 11:13:15.971251 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 11:13:15.974670 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 11:13:15.981320 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 11:13:15.984460 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 11:13:15.987499 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 11:13:15.994042 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 11:13:15.997752 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 11:13:16.000965 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 11:13:16.007532 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 11:13:16.011249 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 11:13:16.014187 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5434 11:13:16.020857 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5435 11:13:16.021290 Total UI for P1: 0, mck2ui 16
5436 11:13:16.027494 best dqsien dly found for B0: ( 1, 2, 28)
5437 11:13:16.030891 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 11:13:16.033809 Total UI for P1: 0, mck2ui 16
5439 11:13:16.037318 best dqsien dly found for B1: ( 1, 2, 30)
5440 11:13:16.040690 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5441 11:13:16.043721 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5442 11:13:16.044150
5443 11:13:16.047056 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5444 11:13:16.050118 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5445 11:13:16.053595 [Gating] SW calibration Done
5446 11:13:16.054021 ==
5447 11:13:16.057126 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 11:13:16.063358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 11:13:16.063786 ==
5450 11:13:16.064120 RX Vref Scan: 0
5451 11:13:16.064575
5452 11:13:16.066815 RX Vref 0 -> 0, step: 1
5453 11:13:16.067257
5454 11:13:16.069925 RX Delay -80 -> 252, step: 8
5455 11:13:16.073444 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5456 11:13:16.076545 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5457 11:13:16.080216 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5458 11:13:16.083419 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5459 11:13:16.086498 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5460 11:13:16.093347 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5461 11:13:16.096972 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5462 11:13:16.099817 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5463 11:13:16.103478 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5464 11:13:16.106577 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5465 11:13:16.113297 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5466 11:13:16.116882 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5467 11:13:16.119563 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5468 11:13:16.123273 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5469 11:13:16.126240 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5470 11:13:16.129811 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5471 11:13:16.133196 ==
5472 11:13:16.136817 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 11:13:16.139727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 11:13:16.140198 ==
5475 11:13:16.140575 DQS Delay:
5476 11:13:16.143375 DQS0 = 0, DQS1 = 0
5477 11:13:16.143800 DQM Delay:
5478 11:13:16.146521 DQM0 = 96, DQM1 = 87
5479 11:13:16.147123 DQ Delay:
5480 11:13:16.149622 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5481 11:13:16.153079 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5482 11:13:16.156599 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =79
5483 11:13:16.159650 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5484 11:13:16.160097
5485 11:13:16.160434
5486 11:13:16.160805 ==
5487 11:13:16.163164 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 11:13:16.166624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 11:13:16.167227 ==
5490 11:13:16.167746
5491 11:13:16.168243
5492 11:13:16.169405 TX Vref Scan disable
5493 11:13:16.172926 == TX Byte 0 ==
5494 11:13:16.176385 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5495 11:13:16.179467 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5496 11:13:16.183219 == TX Byte 1 ==
5497 11:13:16.186165 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5498 11:13:16.189895 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5499 11:13:16.190322 ==
5500 11:13:16.192933 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 11:13:16.198964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 11:13:16.199484 ==
5503 11:13:16.199825
5504 11:13:16.200137
5505 11:13:16.200439 TX Vref Scan disable
5506 11:13:16.203470 == TX Byte 0 ==
5507 11:13:16.206847 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5508 11:13:16.213373 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5509 11:13:16.213908 == TX Byte 1 ==
5510 11:13:16.217077 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5511 11:13:16.223561 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5512 11:13:16.223990
5513 11:13:16.224327 [DATLAT]
5514 11:13:16.224709 Freq=933, CH0 RK1
5515 11:13:16.225031
5516 11:13:16.226733 DATLAT Default: 0xb
5517 11:13:16.227277 0, 0xFFFF, sum = 0
5518 11:13:16.230278 1, 0xFFFF, sum = 0
5519 11:13:16.230715 2, 0xFFFF, sum = 0
5520 11:13:16.233225 3, 0xFFFF, sum = 0
5521 11:13:16.236892 4, 0xFFFF, sum = 0
5522 11:13:16.237329 5, 0xFFFF, sum = 0
5523 11:13:16.239686 6, 0xFFFF, sum = 0
5524 11:13:16.240125 7, 0xFFFF, sum = 0
5525 11:13:16.243172 8, 0xFFFF, sum = 0
5526 11:13:16.243607 9, 0xFFFF, sum = 0
5527 11:13:16.246604 10, 0x0, sum = 1
5528 11:13:16.247042 11, 0x0, sum = 2
5529 11:13:16.249568 12, 0x0, sum = 3
5530 11:13:16.250029 13, 0x0, sum = 4
5531 11:13:16.250371 best_step = 11
5532 11:13:16.250680
5533 11:13:16.253078 ==
5534 11:13:16.256616 Dram Type= 6, Freq= 0, CH_0, rank 1
5535 11:13:16.259978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 11:13:16.260405 ==
5537 11:13:16.260794 RX Vref Scan: 0
5538 11:13:16.261112
5539 11:13:16.262834 RX Vref 0 -> 0, step: 1
5540 11:13:16.263255
5541 11:13:16.265976 RX Delay -69 -> 252, step: 4
5542 11:13:16.272934 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5543 11:13:16.275891 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5544 11:13:16.279335 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5545 11:13:16.282554 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5546 11:13:16.286146 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5547 11:13:16.289034 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5548 11:13:16.295525 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5549 11:13:16.298540 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5550 11:13:16.302441 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5551 11:13:16.305514 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5552 11:13:16.308408 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5553 11:13:16.315153 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5554 11:13:16.318711 iDelay=203, Bit 12, Center 94 (3 ~ 186) 184
5555 11:13:16.321702 iDelay=203, Bit 13, Center 94 (3 ~ 186) 184
5556 11:13:16.324676 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5557 11:13:16.328276 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5558 11:13:16.328400 ==
5559 11:13:16.332063 Dram Type= 6, Freq= 0, CH_0, rank 1
5560 11:13:16.338087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 11:13:16.338171 ==
5562 11:13:16.338239 DQS Delay:
5563 11:13:16.341670 DQS0 = 0, DQS1 = 0
5564 11:13:16.341753 DQM Delay:
5565 11:13:16.344479 DQM0 = 95, DQM1 = 86
5566 11:13:16.344596 DQ Delay:
5567 11:13:16.348033 DQ0 =94, DQ1 =98, DQ2 =90, DQ3 =92
5568 11:13:16.351696 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5569 11:13:16.354694 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =78
5570 11:13:16.358111 DQ12 =94, DQ13 =94, DQ14 =94, DQ15 =94
5571 11:13:16.358194
5572 11:13:16.358258
5573 11:13:16.364625 [DQSOSCAuto] RK1, (LSB)MR18= 0x24f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5574 11:13:16.368385 CH0 RK1: MR19=504, MR18=24F5
5575 11:13:16.374665 CH0_RK1: MR19=0x504, MR18=0x24F5, DQSOSC=410, MR23=63, INC=64, DEC=42
5576 11:13:16.377413 [RxdqsGatingPostProcess] freq 933
5577 11:13:16.384210 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5578 11:13:16.388144 best DQS0 dly(2T, 0.5T) = (0, 10)
5579 11:13:16.388616 best DQS1 dly(2T, 0.5T) = (0, 11)
5580 11:13:16.391189 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5581 11:13:16.394178 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5582 11:13:16.397600 best DQS0 dly(2T, 0.5T) = (0, 10)
5583 11:13:16.401190 best DQS1 dly(2T, 0.5T) = (0, 10)
5584 11:13:16.404228 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5585 11:13:16.407065 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5586 11:13:16.410718 Pre-setting of DQS Precalculation
5587 11:13:16.416982 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5588 11:13:16.417089 ==
5589 11:13:16.420529 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 11:13:16.423572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 11:13:16.423669 ==
5592 11:13:16.430214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5593 11:13:16.437697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5594 11:13:16.440568 [CA 0] Center 36 (6~67) winsize 62
5595 11:13:16.443812 [CA 1] Center 36 (6~67) winsize 62
5596 11:13:16.447079 [CA 2] Center 34 (4~65) winsize 62
5597 11:13:16.450509 [CA 3] Center 33 (3~64) winsize 62
5598 11:13:16.454304 [CA 4] Center 34 (4~65) winsize 62
5599 11:13:16.456996 [CA 5] Center 33 (3~64) winsize 62
5600 11:13:16.457441
5601 11:13:16.460469 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5602 11:13:16.460982
5603 11:13:16.463461 [CATrainingPosCal] consider 1 rank data
5604 11:13:16.466800 u2DelayCellTimex100 = 270/100 ps
5605 11:13:16.470404 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5606 11:13:16.473671 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5607 11:13:16.476588 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5608 11:13:16.479841 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5609 11:13:16.483269 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5610 11:13:16.486796 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5611 11:13:16.487221
5612 11:13:16.489883 CA PerBit enable=1, Macro0, CA PI delay=33
5613 11:13:16.493435
5614 11:13:16.493859 [CBTSetCACLKResult] CA Dly = 33
5615 11:13:16.496512 CS Dly: 6 (0~37)
5616 11:13:16.496958 ==
5617 11:13:16.499982 Dram Type= 6, Freq= 0, CH_1, rank 1
5618 11:13:16.503444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 11:13:16.503873 ==
5620 11:13:16.510015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5621 11:13:16.516801 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5622 11:13:16.519767 [CA 0] Center 36 (6~67) winsize 62
5623 11:13:16.523417 [CA 1] Center 37 (7~67) winsize 61
5624 11:13:16.526295 [CA 2] Center 34 (4~65) winsize 62
5625 11:13:16.529888 [CA 3] Center 33 (3~64) winsize 62
5626 11:13:16.533512 [CA 4] Center 34 (3~65) winsize 63
5627 11:13:16.536222 [CA 5] Center 33 (3~64) winsize 62
5628 11:13:16.536689
5629 11:13:16.539922 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5630 11:13:16.540353
5631 11:13:16.543090 [CATrainingPosCal] consider 2 rank data
5632 11:13:16.546434 u2DelayCellTimex100 = 270/100 ps
5633 11:13:16.550259 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5634 11:13:16.553139 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5635 11:13:16.556461 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5636 11:13:16.559625 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5637 11:13:16.562943 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5638 11:13:16.566499 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5639 11:13:16.566931
5640 11:13:16.573344 CA PerBit enable=1, Macro0, CA PI delay=33
5641 11:13:16.573861
5642 11:13:16.574204 [CBTSetCACLKResult] CA Dly = 33
5643 11:13:16.576156 CS Dly: 7 (0~39)
5644 11:13:16.576673
5645 11:13:16.579677 ----->DramcWriteLeveling(PI) begin...
5646 11:13:16.580190 ==
5647 11:13:16.583111 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 11:13:16.586305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 11:13:16.586843 ==
5650 11:13:16.589424 Write leveling (Byte 0): 27 => 27
5651 11:13:16.593048 Write leveling (Byte 1): 27 => 27
5652 11:13:16.596112 DramcWriteLeveling(PI) end<-----
5653 11:13:16.596569
5654 11:13:16.596925 ==
5655 11:13:16.599835 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 11:13:16.606198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 11:13:16.606746 ==
5658 11:13:16.607095 [Gating] SW mode calibration
5659 11:13:16.615711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5660 11:13:16.619403 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5661 11:13:16.622087 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5662 11:13:16.628906 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5663 11:13:16.631932 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 11:13:16.635521 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 11:13:16.642119 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 11:13:16.645233 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5667 11:13:16.648904 0 14 24 | B1->B0 | 3434 3131 | 0 1 | (0 1) (1 0)
5668 11:13:16.655017 0 14 28 | B1->B0 | 2e2e 2a2a | 0 1 | (0 1) (1 0)
5669 11:13:16.658433 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5670 11:13:16.661822 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5671 11:13:16.668532 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 11:13:16.671465 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 11:13:16.675073 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 11:13:16.681425 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 11:13:16.684975 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5676 11:13:16.687981 0 15 28 | B1->B0 | 2e2e 3939 | 1 0 | (0 0) (1 1)
5677 11:13:16.694621 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5678 11:13:16.698252 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 11:13:16.701279 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 11:13:16.707863 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 11:13:16.711093 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 11:13:16.714994 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 11:13:16.721030 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5684 11:13:16.724711 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5685 11:13:16.727694 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5686 11:13:16.734689 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 11:13:16.737691 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 11:13:16.741251 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 11:13:16.747949 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 11:13:16.751062 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 11:13:16.754773 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 11:13:16.760970 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 11:13:16.764398 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 11:13:16.767418 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 11:13:16.773762 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 11:13:16.777184 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 11:13:16.780548 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 11:13:16.787456 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 11:13:16.790633 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5700 11:13:16.794142 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5701 11:13:16.796976 Total UI for P1: 0, mck2ui 16
5702 11:13:16.800465 best dqsien dly found for B0: ( 1, 2, 24)
5703 11:13:16.806666 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5704 11:13:16.806805 Total UI for P1: 0, mck2ui 16
5705 11:13:16.813929 best dqsien dly found for B1: ( 1, 2, 26)
5706 11:13:16.816750 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5707 11:13:16.820505 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5708 11:13:16.820624
5709 11:13:16.823641 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5710 11:13:16.826696 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5711 11:13:16.830284 [Gating] SW calibration Done
5712 11:13:16.830373 ==
5713 11:13:16.834030 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 11:13:16.836880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 11:13:16.836976 ==
5716 11:13:16.840509 RX Vref Scan: 0
5717 11:13:16.840614
5718 11:13:16.840689 RX Vref 0 -> 0, step: 1
5719 11:13:16.843599
5720 11:13:16.843700 RX Delay -80 -> 252, step: 8
5721 11:13:16.850130 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5722 11:13:16.853162 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5723 11:13:16.856893 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5724 11:13:16.859927 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5725 11:13:16.862965 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5726 11:13:16.866591 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5727 11:13:16.873390 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5728 11:13:16.876365 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5729 11:13:16.879755 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5730 11:13:16.883240 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5731 11:13:16.886833 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5732 11:13:16.893320 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5733 11:13:16.896167 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5734 11:13:16.899721 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5735 11:13:16.903263 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5736 11:13:16.906307 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5737 11:13:16.906920 ==
5738 11:13:16.909443 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 11:13:16.916032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 11:13:16.916564 ==
5741 11:13:16.916924 DQS Delay:
5742 11:13:16.919545 DQS0 = 0, DQS1 = 0
5743 11:13:16.920013 DQM Delay:
5744 11:13:16.920483 DQM0 = 101, DQM1 = 91
5745 11:13:16.923160 DQ Delay:
5746 11:13:16.926139 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =103
5747 11:13:16.929750 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =99
5748 11:13:16.932731 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5749 11:13:16.936582 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5750 11:13:16.937118
5751 11:13:16.937456
5752 11:13:16.937763 ==
5753 11:13:16.939433 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 11:13:16.942474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 11:13:16.942927 ==
5756 11:13:16.943321
5757 11:13:16.943655
5758 11:13:16.946120 TX Vref Scan disable
5759 11:13:16.948932 == TX Byte 0 ==
5760 11:13:16.952849 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5761 11:13:16.955627 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5762 11:13:16.958804 == TX Byte 1 ==
5763 11:13:16.962738 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5764 11:13:16.965604 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5765 11:13:16.966051 ==
5766 11:13:16.969197 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 11:13:16.975498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 11:13:16.976000 ==
5769 11:13:16.976336
5770 11:13:16.976722
5771 11:13:16.977036 TX Vref Scan disable
5772 11:13:16.979598 == TX Byte 0 ==
5773 11:13:16.982636 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5774 11:13:16.989477 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5775 11:13:16.989974 == TX Byte 1 ==
5776 11:13:16.992502 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5777 11:13:16.999108 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5778 11:13:16.999566
5779 11:13:16.999926 [DATLAT]
5780 11:13:17.000414 Freq=933, CH1 RK0
5781 11:13:17.000902
5782 11:13:17.002513 DATLAT Default: 0xd
5783 11:13:17.002942 0, 0xFFFF, sum = 0
5784 11:13:17.005954 1, 0xFFFF, sum = 0
5785 11:13:17.009148 2, 0xFFFF, sum = 0
5786 11:13:17.009611 3, 0xFFFF, sum = 0
5787 11:13:17.012292 4, 0xFFFF, sum = 0
5788 11:13:17.012784 5, 0xFFFF, sum = 0
5789 11:13:17.015678 6, 0xFFFF, sum = 0
5790 11:13:17.016122 7, 0xFFFF, sum = 0
5791 11:13:17.018887 8, 0xFFFF, sum = 0
5792 11:13:17.019316 9, 0xFFFF, sum = 0
5793 11:13:17.022678 10, 0x0, sum = 1
5794 11:13:17.023133 11, 0x0, sum = 2
5795 11:13:17.025547 12, 0x0, sum = 3
5796 11:13:17.025980 13, 0x0, sum = 4
5797 11:13:17.029058 best_step = 11
5798 11:13:17.029482
5799 11:13:17.029816 ==
5800 11:13:17.031924 Dram Type= 6, Freq= 0, CH_1, rank 0
5801 11:13:17.035548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 11:13:17.035977 ==
5803 11:13:17.036311 RX Vref Scan: 1
5804 11:13:17.036664
5805 11:13:17.038690 RX Vref 0 -> 0, step: 1
5806 11:13:17.039113
5807 11:13:17.042262 RX Delay -69 -> 252, step: 4
5808 11:13:17.042687
5809 11:13:17.045302 Set Vref, RX VrefLevel [Byte0]: 48
5810 11:13:17.048219 [Byte1]: 50
5811 11:13:17.051791
5812 11:13:17.052214 Final RX Vref Byte 0 = 48 to rank0
5813 11:13:17.055343 Final RX Vref Byte 1 = 50 to rank0
5814 11:13:17.058513 Final RX Vref Byte 0 = 48 to rank1
5815 11:13:17.062075 Final RX Vref Byte 1 = 50 to rank1==
5816 11:13:17.065114 Dram Type= 6, Freq= 0, CH_1, rank 0
5817 11:13:17.072034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 11:13:17.072474 ==
5819 11:13:17.072875 DQS Delay:
5820 11:13:17.075048 DQS0 = 0, DQS1 = 0
5821 11:13:17.075542 DQM Delay:
5822 11:13:17.075980 DQM0 = 101, DQM1 = 94
5823 11:13:17.078651 DQ Delay:
5824 11:13:17.081578 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5825 11:13:17.085132 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5826 11:13:17.088125 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =84
5827 11:13:17.091896 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =106
5828 11:13:17.092335
5829 11:13:17.092843
5830 11:13:17.098442 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5831 11:13:17.101776 CH1 RK0: MR19=505, MR18=1B0A
5832 11:13:17.108226 CH1_RK0: MR19=0x505, MR18=0x1B0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5833 11:13:17.108802
5834 11:13:17.111531 ----->DramcWriteLeveling(PI) begin...
5835 11:13:17.112106 ==
5836 11:13:17.115102 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 11:13:17.118098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 11:13:17.118605 ==
5839 11:13:17.121851 Write leveling (Byte 0): 24 => 24
5840 11:13:17.125018 Write leveling (Byte 1): 31 => 31
5841 11:13:17.128382 DramcWriteLeveling(PI) end<-----
5842 11:13:17.129008
5843 11:13:17.129455 ==
5844 11:13:17.131453 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 11:13:17.138292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 11:13:17.138738 ==
5847 11:13:17.139178 [Gating] SW mode calibration
5848 11:13:17.147956 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5849 11:13:17.151534 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5850 11:13:17.154630 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5851 11:13:17.161252 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5852 11:13:17.164365 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5853 11:13:17.168060 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 11:13:17.174087 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 11:13:17.177812 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 11:13:17.180767 0 14 24 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
5857 11:13:17.187960 0 14 28 | B1->B0 | 2f2f 3030 | 0 0 | (1 1) (0 1)
5858 11:13:17.191007 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5859 11:13:17.194046 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5860 11:13:17.200667 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5861 11:13:17.203980 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 11:13:17.207497 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 11:13:17.214063 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 11:13:17.217486 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5865 11:13:17.220400 0 15 28 | B1->B0 | 3b3b 3636 | 0 0 | (0 0) (0 0)
5866 11:13:17.226967 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5867 11:13:17.230668 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 11:13:17.233647 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 11:13:17.240217 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 11:13:17.243329 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 11:13:17.247189 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5872 11:13:17.253930 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5873 11:13:17.256851 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5874 11:13:17.259922 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 11:13:17.267115 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 11:13:17.270174 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 11:13:17.273614 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 11:13:17.279819 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 11:13:17.283389 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 11:13:17.287021 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 11:13:17.293033 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 11:13:17.296325 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 11:13:17.299988 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 11:13:17.306307 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 11:13:17.309933 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 11:13:17.312893 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 11:13:17.319392 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 11:13:17.322633 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5889 11:13:17.326323 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5890 11:13:17.329431 Total UI for P1: 0, mck2ui 16
5891 11:13:17.333016 best dqsien dly found for B1: ( 1, 2, 24)
5892 11:13:17.339571 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5893 11:13:17.340129 Total UI for P1: 0, mck2ui 16
5894 11:13:17.346068 best dqsien dly found for B0: ( 1, 2, 28)
5895 11:13:17.349245 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5896 11:13:17.352710 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5897 11:13:17.353134
5898 11:13:17.356300 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5899 11:13:17.359437 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5900 11:13:17.362490 [Gating] SW calibration Done
5901 11:13:17.362932 ==
5902 11:13:17.366244 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 11:13:17.369209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 11:13:17.369643 ==
5905 11:13:17.372691 RX Vref Scan: 0
5906 11:13:17.373168
5907 11:13:17.373510 RX Vref 0 -> 0, step: 1
5908 11:13:17.373830
5909 11:13:17.375782 RX Delay -80 -> 252, step: 8
5910 11:13:17.382529 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5911 11:13:17.385570 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5912 11:13:17.389241 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5913 11:13:17.392132 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5914 11:13:17.395535 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5915 11:13:17.398874 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5916 11:13:17.405798 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5917 11:13:17.408657 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5918 11:13:17.412176 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5919 11:13:17.415594 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5920 11:13:17.419351 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5921 11:13:17.425132 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5922 11:13:17.428992 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5923 11:13:17.432205 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5924 11:13:17.435056 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5925 11:13:17.438333 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5926 11:13:17.438887 ==
5927 11:13:17.441709 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 11:13:17.448211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 11:13:17.448672 ==
5930 11:13:17.449048 DQS Delay:
5931 11:13:17.451351 DQS0 = 0, DQS1 = 0
5932 11:13:17.451792 DQM Delay:
5933 11:13:17.452157 DQM0 = 99, DQM1 = 90
5934 11:13:17.455086 DQ Delay:
5935 11:13:17.458049 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5936 11:13:17.461596 DQ4 =95, DQ5 =115, DQ6 =107, DQ7 =95
5937 11:13:17.464707 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5938 11:13:17.468326 DQ12 =103, DQ13 =99, DQ14 =95, DQ15 =99
5939 11:13:17.468825
5940 11:13:17.469210
5941 11:13:17.469531 ==
5942 11:13:17.471273 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 11:13:17.475118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 11:13:17.475556 ==
5945 11:13:17.475929
5946 11:13:17.476274
5947 11:13:17.478158 TX Vref Scan disable
5948 11:13:17.481923 == TX Byte 0 ==
5949 11:13:17.485080 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5950 11:13:17.488147 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5951 11:13:17.491516 == TX Byte 1 ==
5952 11:13:17.494673 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5953 11:13:17.498058 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5954 11:13:17.498493 ==
5955 11:13:17.501067 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 11:13:17.504375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 11:13:17.507987 ==
5958 11:13:17.508631
5959 11:13:17.509053
5960 11:13:17.509393 TX Vref Scan disable
5961 11:13:17.511391 == TX Byte 0 ==
5962 11:13:17.514916 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5963 11:13:17.521459 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5964 11:13:17.521889 == TX Byte 1 ==
5965 11:13:17.524962 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5966 11:13:17.531555 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5967 11:13:17.532029
5968 11:13:17.532489 [DATLAT]
5969 11:13:17.532961 Freq=933, CH1 RK1
5970 11:13:17.533410
5971 11:13:17.534380 DATLAT Default: 0xb
5972 11:13:17.537825 0, 0xFFFF, sum = 0
5973 11:13:17.537911 1, 0xFFFF, sum = 0
5974 11:13:17.540825 2, 0xFFFF, sum = 0
5975 11:13:17.540910 3, 0xFFFF, sum = 0
5976 11:13:17.543898 4, 0xFFFF, sum = 0
5977 11:13:17.544012 5, 0xFFFF, sum = 0
5978 11:13:17.547576 6, 0xFFFF, sum = 0
5979 11:13:17.547660 7, 0xFFFF, sum = 0
5980 11:13:17.550573 8, 0xFFFF, sum = 0
5981 11:13:17.550658 9, 0xFFFF, sum = 0
5982 11:13:17.553955 10, 0x0, sum = 1
5983 11:13:17.554031 11, 0x0, sum = 2
5984 11:13:17.557113 12, 0x0, sum = 3
5985 11:13:17.557188 13, 0x0, sum = 4
5986 11:13:17.560738 best_step = 11
5987 11:13:17.560834
5988 11:13:17.560911 ==
5989 11:13:17.563603 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 11:13:17.567304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 11:13:17.567383 ==
5992 11:13:17.567467 RX Vref Scan: 0
5993 11:13:17.570399
5994 11:13:17.570482 RX Vref 0 -> 0, step: 1
5995 11:13:17.570565
5996 11:13:17.573411 RX Delay -61 -> 252, step: 4
5997 11:13:17.580012 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5998 11:13:17.583718 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
5999 11:13:17.586764 iDelay=207, Bit 2, Center 92 (7 ~ 178) 172
6000 11:13:17.590403 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6001 11:13:17.593551 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6002 11:13:17.600267 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6003 11:13:17.603640 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6004 11:13:17.606717 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6005 11:13:17.610179 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
6006 11:13:17.613608 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6007 11:13:17.616774 iDelay=207, Bit 10, Center 94 (7 ~ 182) 176
6008 11:13:17.623582 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6009 11:13:17.626390 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6010 11:13:17.629820 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
6011 11:13:17.632930 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6012 11:13:17.636783 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6013 11:13:17.639636 ==
6014 11:13:17.643138 Dram Type= 6, Freq= 0, CH_1, rank 1
6015 11:13:17.646536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6016 11:13:17.646720 ==
6017 11:13:17.646848 DQS Delay:
6018 11:13:17.649644 DQS0 = 0, DQS1 = 0
6019 11:13:17.649789 DQM Delay:
6020 11:13:17.653154 DQM0 = 102, DQM1 = 92
6021 11:13:17.653371 DQ Delay:
6022 11:13:17.656330 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
6023 11:13:17.659409 DQ4 =100, DQ5 =110, DQ6 =116, DQ7 =98
6024 11:13:17.662530 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =84
6025 11:13:17.666103 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =102
6026 11:13:17.666181
6027 11:13:17.666262
6028 11:13:17.675742 [DQSOSCAuto] RK1, (LSB)MR18= 0x600, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
6029 11:13:17.675826 CH1 RK1: MR19=505, MR18=600
6030 11:13:17.682321 CH1_RK1: MR19=0x505, MR18=0x600, DQSOSC=420, MR23=63, INC=61, DEC=40
6031 11:13:17.686269 [RxdqsGatingPostProcess] freq 933
6032 11:13:17.692314 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6033 11:13:17.695917 best DQS0 dly(2T, 0.5T) = (0, 10)
6034 11:13:17.698991 best DQS1 dly(2T, 0.5T) = (0, 10)
6035 11:13:17.702233 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6036 11:13:17.705588 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6037 11:13:17.708965 best DQS0 dly(2T, 0.5T) = (0, 10)
6038 11:13:17.709104 best DQS1 dly(2T, 0.5T) = (0, 10)
6039 11:13:17.712614 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6040 11:13:17.715548 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6041 11:13:17.718925 Pre-setting of DQS Precalculation
6042 11:13:17.725367 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6043 11:13:17.731907 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6044 11:13:17.738494 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6045 11:13:17.738580
6046 11:13:17.738665
6047 11:13:17.741919 [Calibration Summary] 1866 Mbps
6048 11:13:17.745082 CH 0, Rank 0
6049 11:13:17.745166 SW Impedance : PASS
6050 11:13:17.748664 DUTY Scan : NO K
6051 11:13:17.748749 ZQ Calibration : PASS
6052 11:13:17.751762 Jitter Meter : NO K
6053 11:13:17.755440 CBT Training : PASS
6054 11:13:17.755524 Write leveling : PASS
6055 11:13:17.758848 RX DQS gating : PASS
6056 11:13:17.761599 RX DQ/DQS(RDDQC) : PASS
6057 11:13:17.761683 TX DQ/DQS : PASS
6058 11:13:17.765128 RX DATLAT : PASS
6059 11:13:17.768261 RX DQ/DQS(Engine): PASS
6060 11:13:17.768357 TX OE : NO K
6061 11:13:17.771956 All Pass.
6062 11:13:17.772063
6063 11:13:17.772167 CH 0, Rank 1
6064 11:13:17.775043 SW Impedance : PASS
6065 11:13:17.775147 DUTY Scan : NO K
6066 11:13:17.778688 ZQ Calibration : PASS
6067 11:13:17.781705 Jitter Meter : NO K
6068 11:13:17.781819 CBT Training : PASS
6069 11:13:17.785459 Write leveling : PASS
6070 11:13:17.788426 RX DQS gating : PASS
6071 11:13:17.788602 RX DQ/DQS(RDDQC) : PASS
6072 11:13:17.791753 TX DQ/DQS : PASS
6073 11:13:17.795253 RX DATLAT : PASS
6074 11:13:17.795446 RX DQ/DQS(Engine): PASS
6075 11:13:17.798267 TX OE : NO K
6076 11:13:17.798459 All Pass.
6077 11:13:17.798597
6078 11:13:17.801361 CH 1, Rank 0
6079 11:13:17.801568 SW Impedance : PASS
6080 11:13:17.804506 DUTY Scan : NO K
6081 11:13:17.808165 ZQ Calibration : PASS
6082 11:13:17.808411 Jitter Meter : NO K
6083 11:13:17.811462 CBT Training : PASS
6084 11:13:17.814670 Write leveling : PASS
6085 11:13:17.814978 RX DQS gating : PASS
6086 11:13:17.818086 RX DQ/DQS(RDDQC) : PASS
6087 11:13:17.821224 TX DQ/DQS : PASS
6088 11:13:17.821615 RX DATLAT : PASS
6089 11:13:17.824893 RX DQ/DQS(Engine): PASS
6090 11:13:17.825312 TX OE : NO K
6091 11:13:17.827791 All Pass.
6092 11:13:17.828208
6093 11:13:17.828669 CH 1, Rank 1
6094 11:13:17.831299 SW Impedance : PASS
6095 11:13:17.834683 DUTY Scan : NO K
6096 11:13:17.835104 ZQ Calibration : PASS
6097 11:13:17.838449 Jitter Meter : NO K
6098 11:13:17.838870 CBT Training : PASS
6099 11:13:17.841297 Write leveling : PASS
6100 11:13:17.844023 RX DQS gating : PASS
6101 11:13:17.844444 RX DQ/DQS(RDDQC) : PASS
6102 11:13:17.847642 TX DQ/DQS : PASS
6103 11:13:17.850810 RX DATLAT : PASS
6104 11:13:17.851230 RX DQ/DQS(Engine): PASS
6105 11:13:17.854440 TX OE : NO K
6106 11:13:17.854858 All Pass.
6107 11:13:17.855187
6108 11:13:17.857305 DramC Write-DBI off
6109 11:13:17.860931 PER_BANK_REFRESH: Hybrid Mode
6110 11:13:17.861377 TX_TRACKING: ON
6111 11:13:17.870839 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6112 11:13:17.873847 [FAST_K] Save calibration result to emmc
6113 11:13:17.877381 dramc_set_vcore_voltage set vcore to 650000
6114 11:13:17.880554 Read voltage for 400, 6
6115 11:13:17.881029 Vio18 = 0
6116 11:13:17.883592 Vcore = 650000
6117 11:13:17.884019 Vdram = 0
6118 11:13:17.884354 Vddq = 0
6119 11:13:17.884718 Vmddr = 0
6120 11:13:17.890244 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6121 11:13:17.897119 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6122 11:13:17.897643 MEM_TYPE=3, freq_sel=20
6123 11:13:17.900576 sv_algorithm_assistance_LP4_800
6124 11:13:17.903587 ============ PULL DRAM RESETB DOWN ============
6125 11:13:17.910206 ========== PULL DRAM RESETB DOWN end =========
6126 11:13:17.913849 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6127 11:13:17.916863 ===================================
6128 11:13:17.920007 LPDDR4 DRAM CONFIGURATION
6129 11:13:17.923738 ===================================
6130 11:13:17.924311 EX_ROW_EN[0] = 0x0
6131 11:13:17.926604 EX_ROW_EN[1] = 0x0
6132 11:13:17.927028 LP4Y_EN = 0x0
6133 11:13:17.930140 WORK_FSP = 0x0
6134 11:13:17.930563 WL = 0x2
6135 11:13:17.934004 RL = 0x2
6136 11:13:17.936667 BL = 0x2
6137 11:13:17.937104 RPST = 0x0
6138 11:13:17.940267 RD_PRE = 0x0
6139 11:13:17.940925 WR_PRE = 0x1
6140 11:13:17.942902 WR_PST = 0x0
6141 11:13:17.943458 DBI_WR = 0x0
6142 11:13:17.946488 DBI_RD = 0x0
6143 11:13:17.946925 OTF = 0x1
6144 11:13:17.949876 ===================================
6145 11:13:17.953353 ===================================
6146 11:13:17.956382 ANA top config
6147 11:13:17.959485 ===================================
6148 11:13:17.959912 DLL_ASYNC_EN = 0
6149 11:13:17.963061 ALL_SLAVE_EN = 1
6150 11:13:17.966492 NEW_RANK_MODE = 1
6151 11:13:17.969417 DLL_IDLE_MODE = 1
6152 11:13:17.969842 LP45_APHY_COMB_EN = 1
6153 11:13:17.972909 TX_ODT_DIS = 1
6154 11:13:17.976056 NEW_8X_MODE = 1
6155 11:13:17.979862 ===================================
6156 11:13:17.982879 ===================================
6157 11:13:17.986438 data_rate = 800
6158 11:13:17.989602 CKR = 1
6159 11:13:17.992436 DQ_P2S_RATIO = 4
6160 11:13:17.996209 ===================================
6161 11:13:17.999328 CA_P2S_RATIO = 4
6162 11:13:17.999903 DQ_CA_OPEN = 0
6163 11:13:18.002385 DQ_SEMI_OPEN = 1
6164 11:13:18.005838 CA_SEMI_OPEN = 1
6165 11:13:18.008920 CA_FULL_RATE = 0
6166 11:13:18.012606 DQ_CKDIV4_EN = 0
6167 11:13:18.015712 CA_CKDIV4_EN = 1
6168 11:13:18.016139 CA_PREDIV_EN = 0
6169 11:13:18.019223 PH8_DLY = 0
6170 11:13:18.022438 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6171 11:13:18.025895 DQ_AAMCK_DIV = 0
6172 11:13:18.028999 CA_AAMCK_DIV = 0
6173 11:13:18.032193 CA_ADMCK_DIV = 4
6174 11:13:18.032682 DQ_TRACK_CA_EN = 0
6175 11:13:18.035764 CA_PICK = 800
6176 11:13:18.038590 CA_MCKIO = 400
6177 11:13:18.042087 MCKIO_SEMI = 400
6178 11:13:18.045177 PLL_FREQ = 3016
6179 11:13:18.049032 DQ_UI_PI_RATIO = 32
6180 11:13:18.051837 CA_UI_PI_RATIO = 32
6181 11:13:18.055286 ===================================
6182 11:13:18.058728 ===================================
6183 11:13:18.059552 memory_type:LPDDR4
6184 11:13:18.061741 GP_NUM : 10
6185 11:13:18.065515 SRAM_EN : 1
6186 11:13:18.065945 MD32_EN : 0
6187 11:13:18.068563 ===================================
6188 11:13:18.071585 [ANA_INIT] >>>>>>>>>>>>>>
6189 11:13:18.075148 <<<<<< [CONFIGURE PHASE]: ANA_TX
6190 11:13:18.078342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6191 11:13:18.081455 ===================================
6192 11:13:18.085143 data_rate = 800,PCW = 0X7400
6193 11:13:18.088116 ===================================
6194 11:13:18.091643 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6195 11:13:18.094837 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6196 11:13:18.108082 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6197 11:13:18.111655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6198 11:13:18.114680 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6199 11:13:18.118424 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6200 11:13:18.121260 [ANA_INIT] flow start
6201 11:13:18.124794 [ANA_INIT] PLL >>>>>>>>
6202 11:13:18.125332 [ANA_INIT] PLL <<<<<<<<
6203 11:13:18.128240 [ANA_INIT] MIDPI >>>>>>>>
6204 11:13:18.131666 [ANA_INIT] MIDPI <<<<<<<<
6205 11:13:18.132147 [ANA_INIT] DLL >>>>>>>>
6206 11:13:18.134618 [ANA_INIT] flow end
6207 11:13:18.138153 ============ LP4 DIFF to SE enter ============
6208 11:13:18.141581 ============ LP4 DIFF to SE exit ============
6209 11:13:18.144582 [ANA_INIT] <<<<<<<<<<<<<
6210 11:13:18.147838 [Flow] Enable top DCM control >>>>>
6211 11:13:18.151610 [Flow] Enable top DCM control <<<<<
6212 11:13:18.154431 Enable DLL master slave shuffle
6213 11:13:18.160950 ==============================================================
6214 11:13:18.161425 Gating Mode config
6215 11:13:18.168220 ==============================================================
6216 11:13:18.168711 Config description:
6217 11:13:18.177978 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6218 11:13:18.184296 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6219 11:13:18.190790 SELPH_MODE 0: By rank 1: By Phase
6220 11:13:18.197485 ==============================================================
6221 11:13:18.197920 GAT_TRACK_EN = 0
6222 11:13:18.201263 RX_GATING_MODE = 2
6223 11:13:18.204266 RX_GATING_TRACK_MODE = 2
6224 11:13:18.207366 SELPH_MODE = 1
6225 11:13:18.211095 PICG_EARLY_EN = 1
6226 11:13:18.214105 VALID_LAT_VALUE = 1
6227 11:13:18.220733 ==============================================================
6228 11:13:18.223967 Enter into Gating configuration >>>>
6229 11:13:18.227350 Exit from Gating configuration <<<<
6230 11:13:18.230495 Enter into DVFS_PRE_config >>>>>
6231 11:13:18.240665 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6232 11:13:18.243685 Exit from DVFS_PRE_config <<<<<
6233 11:13:18.247075 Enter into PICG configuration >>>>
6234 11:13:18.250202 Exit from PICG configuration <<<<
6235 11:13:18.253787 [RX_INPUT] configuration >>>>>
6236 11:13:18.254259 [RX_INPUT] configuration <<<<<
6237 11:13:18.260286 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6238 11:13:18.267202 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6239 11:13:18.273799 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6240 11:13:18.276984 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6241 11:13:18.283614 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6242 11:13:18.290302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6243 11:13:18.293291 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6244 11:13:18.299988 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6245 11:13:18.303664 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6246 11:13:18.306826 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6247 11:13:18.310358 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6248 11:13:18.316917 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6249 11:13:18.320066 ===================================
6250 11:13:18.320487 LPDDR4 DRAM CONFIGURATION
6251 11:13:18.323047 ===================================
6252 11:13:18.326699 EX_ROW_EN[0] = 0x0
6253 11:13:18.329689 EX_ROW_EN[1] = 0x0
6254 11:13:18.330111 LP4Y_EN = 0x0
6255 11:13:18.333198 WORK_FSP = 0x0
6256 11:13:18.333622 WL = 0x2
6257 11:13:18.336140 RL = 0x2
6258 11:13:18.336583 BL = 0x2
6259 11:13:18.339729 RPST = 0x0
6260 11:13:18.340171 RD_PRE = 0x0
6261 11:13:18.343301 WR_PRE = 0x1
6262 11:13:18.343816 WR_PST = 0x0
6263 11:13:18.346223 DBI_WR = 0x0
6264 11:13:18.346641 DBI_RD = 0x0
6265 11:13:18.349901 OTF = 0x1
6266 11:13:18.352747 ===================================
6267 11:13:18.356396 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6268 11:13:18.359896 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6269 11:13:18.366077 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6270 11:13:18.369189 ===================================
6271 11:13:18.369277 LPDDR4 DRAM CONFIGURATION
6272 11:13:18.372392 ===================================
6273 11:13:18.376032 EX_ROW_EN[0] = 0x10
6274 11:13:18.379117 EX_ROW_EN[1] = 0x0
6275 11:13:18.379200 LP4Y_EN = 0x0
6276 11:13:18.382128 WORK_FSP = 0x0
6277 11:13:18.382209 WL = 0x2
6278 11:13:18.385462 RL = 0x2
6279 11:13:18.385551 BL = 0x2
6280 11:13:18.389135 RPST = 0x0
6281 11:13:18.389217 RD_PRE = 0x0
6282 11:13:18.392202 WR_PRE = 0x1
6283 11:13:18.392283 WR_PST = 0x0
6284 11:13:18.395426 DBI_WR = 0x0
6285 11:13:18.395508 DBI_RD = 0x0
6286 11:13:18.399060 OTF = 0x1
6287 11:13:18.402102 ===================================
6288 11:13:18.409137 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6289 11:13:18.412244 nWR fixed to 30
6290 11:13:18.415654 [ModeRegInit_LP4] CH0 RK0
6291 11:13:18.415806 [ModeRegInit_LP4] CH0 RK1
6292 11:13:18.418840 [ModeRegInit_LP4] CH1 RK0
6293 11:13:18.422569 [ModeRegInit_LP4] CH1 RK1
6294 11:13:18.422671 match AC timing 19
6295 11:13:18.428485 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6296 11:13:18.432040 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6297 11:13:18.435279 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6298 11:13:18.441857 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6299 11:13:18.445416 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6300 11:13:18.445595 ==
6301 11:13:18.448417 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 11:13:18.452358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 11:13:18.452712 ==
6304 11:13:18.458583 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6305 11:13:18.465057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6306 11:13:18.468827 [CA 0] Center 36 (8~64) winsize 57
6307 11:13:18.472081 [CA 1] Center 36 (8~64) winsize 57
6308 11:13:18.475629 [CA 2] Center 36 (8~64) winsize 57
6309 11:13:18.476116 [CA 3] Center 36 (8~64) winsize 57
6310 11:13:18.478451 [CA 4] Center 36 (8~64) winsize 57
6311 11:13:18.481835 [CA 5] Center 36 (8~64) winsize 57
6312 11:13:18.482319
6313 11:13:18.488600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6314 11:13:18.489171
6315 11:13:18.491730 [CATrainingPosCal] consider 1 rank data
6316 11:13:18.495435 u2DelayCellTimex100 = 270/100 ps
6317 11:13:18.498252 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 11:13:18.501327 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 11:13:18.504836 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 11:13:18.508618 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 11:13:18.511578 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 11:13:18.515316 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 11:13:18.515843
6324 11:13:18.518251 CA PerBit enable=1, Macro0, CA PI delay=36
6325 11:13:18.518674
6326 11:13:18.521314 [CBTSetCACLKResult] CA Dly = 36
6327 11:13:18.524835 CS Dly: 1 (0~32)
6328 11:13:18.525271 ==
6329 11:13:18.528206 Dram Type= 6, Freq= 0, CH_0, rank 1
6330 11:13:18.530954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 11:13:18.531036 ==
6332 11:13:18.537477 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6333 11:13:18.544173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6334 11:13:18.547081 [CA 0] Center 36 (8~64) winsize 57
6335 11:13:18.547160 [CA 1] Center 36 (8~64) winsize 57
6336 11:13:18.550590 [CA 2] Center 36 (8~64) winsize 57
6337 11:13:18.554357 [CA 3] Center 36 (8~64) winsize 57
6338 11:13:18.557054 [CA 4] Center 36 (8~64) winsize 57
6339 11:13:18.560358 [CA 5] Center 36 (8~64) winsize 57
6340 11:13:18.560439
6341 11:13:18.564069 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6342 11:13:18.564140
6343 11:13:18.570346 [CATrainingPosCal] consider 2 rank data
6344 11:13:18.570425 u2DelayCellTimex100 = 270/100 ps
6345 11:13:18.576905 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 11:13:18.579990 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 11:13:18.583379 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 11:13:18.586824 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 11:13:18.590078 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 11:13:18.593455 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 11:13:18.593536
6352 11:13:18.596479 CA PerBit enable=1, Macro0, CA PI delay=36
6353 11:13:18.596600
6354 11:13:18.600215 [CBTSetCACLKResult] CA Dly = 36
6355 11:13:18.603154 CS Dly: 1 (0~32)
6356 11:13:18.603231
6357 11:13:18.606799 ----->DramcWriteLeveling(PI) begin...
6358 11:13:18.606874 ==
6359 11:13:18.609896 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 11:13:18.613015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 11:13:18.613102 ==
6362 11:13:18.616674 Write leveling (Byte 0): 40 => 8
6363 11:13:18.619704 Write leveling (Byte 1): 32 => 0
6364 11:13:18.622771 DramcWriteLeveling(PI) end<-----
6365 11:13:18.622851
6366 11:13:18.622913 ==
6367 11:13:18.626519 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 11:13:18.629518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 11:13:18.629604 ==
6370 11:13:18.633450 [Gating] SW mode calibration
6371 11:13:18.639965 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6372 11:13:18.646629 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6373 11:13:18.649609 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6374 11:13:18.656362 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6375 11:13:18.659793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6376 11:13:18.662848 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6377 11:13:18.666164 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6378 11:13:18.672707 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6379 11:13:18.676335 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 11:13:18.679385 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 11:13:18.685780 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6382 11:13:18.689230 Total UI for P1: 0, mck2ui 16
6383 11:13:18.692611 best dqsien dly found for B0: ( 0, 14, 24)
6384 11:13:18.696261 Total UI for P1: 0, mck2ui 16
6385 11:13:18.699427 best dqsien dly found for B1: ( 0, 14, 24)
6386 11:13:18.702351 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6387 11:13:18.705991 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6388 11:13:18.706425
6389 11:13:18.708934 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6390 11:13:18.712552 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6391 11:13:18.716425 [Gating] SW calibration Done
6392 11:13:18.716930 ==
6393 11:13:18.719588 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 11:13:18.722275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 11:13:18.722691 ==
6396 11:13:18.726143 RX Vref Scan: 0
6397 11:13:18.726555
6398 11:13:18.729241 RX Vref 0 -> 0, step: 1
6399 11:13:18.729703
6400 11:13:18.730039 RX Delay -410 -> 252, step: 16
6401 11:13:18.736030 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6402 11:13:18.738947 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6403 11:13:18.742547 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6404 11:13:18.748999 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6405 11:13:18.752610 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6406 11:13:18.755671 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6407 11:13:18.759162 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6408 11:13:18.765741 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6409 11:13:18.768715 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6410 11:13:18.772325 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6411 11:13:18.775370 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6412 11:13:18.782384 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6413 11:13:18.785238 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6414 11:13:18.788820 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6415 11:13:18.791762 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6416 11:13:18.798835 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6417 11:13:18.799250 ==
6418 11:13:18.801753 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 11:13:18.805440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 11:13:18.805853 ==
6421 11:13:18.806177 DQS Delay:
6422 11:13:18.808421 DQS0 = 43, DQS1 = 59
6423 11:13:18.808886 DQM Delay:
6424 11:13:18.812033 DQM0 = 9, DQM1 = 11
6425 11:13:18.812492 DQ Delay:
6426 11:13:18.814938 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6427 11:13:18.818645 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6428 11:13:18.821885 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6429 11:13:18.824896 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6430 11:13:18.825342
6431 11:13:18.825672
6432 11:13:18.825998 ==
6433 11:13:18.828359 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 11:13:18.831325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 11:13:18.831751 ==
6436 11:13:18.832082
6437 11:13:18.835052
6438 11:13:18.835469 TX Vref Scan disable
6439 11:13:18.838480 == TX Byte 0 ==
6440 11:13:18.841094 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6441 11:13:18.844852 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6442 11:13:18.848223 == TX Byte 1 ==
6443 11:13:18.851364 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6444 11:13:18.854707 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6445 11:13:18.855292 ==
6446 11:13:18.858135 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 11:13:18.864651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 11:13:18.865179 ==
6449 11:13:18.865516
6450 11:13:18.865874
6451 11:13:18.866171 TX Vref Scan disable
6452 11:13:18.867974 == TX Byte 0 ==
6453 11:13:18.870932 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6454 11:13:18.874494 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6455 11:13:18.877358 == TX Byte 1 ==
6456 11:13:18.880987 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6457 11:13:18.884353 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6458 11:13:18.884888
6459 11:13:18.887387 [DATLAT]
6460 11:13:18.887816 Freq=400, CH0 RK0
6461 11:13:18.888150
6462 11:13:18.890978 DATLAT Default: 0xf
6463 11:13:18.891452 0, 0xFFFF, sum = 0
6464 11:13:18.893959 1, 0xFFFF, sum = 0
6465 11:13:18.894455 2, 0xFFFF, sum = 0
6466 11:13:18.897520 3, 0xFFFF, sum = 0
6467 11:13:18.898025 4, 0xFFFF, sum = 0
6468 11:13:18.900903 5, 0xFFFF, sum = 0
6469 11:13:18.901420 6, 0xFFFF, sum = 0
6470 11:13:18.904179 7, 0xFFFF, sum = 0
6471 11:13:18.904715 8, 0xFFFF, sum = 0
6472 11:13:18.907481 9, 0xFFFF, sum = 0
6473 11:13:18.910460 10, 0xFFFF, sum = 0
6474 11:13:18.910967 11, 0xFFFF, sum = 0
6475 11:13:18.914098 12, 0xFFFF, sum = 0
6476 11:13:18.914602 13, 0x0, sum = 1
6477 11:13:18.917199 14, 0x0, sum = 2
6478 11:13:18.917645 15, 0x0, sum = 3
6479 11:13:18.920512 16, 0x0, sum = 4
6480 11:13:18.921192 best_step = 14
6481 11:13:18.921608
6482 11:13:18.922020 ==
6483 11:13:18.923682 Dram Type= 6, Freq= 0, CH_0, rank 0
6484 11:13:18.927472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 11:13:18.927915 ==
6486 11:13:18.930713 RX Vref Scan: 1
6487 11:13:18.931262
6488 11:13:18.933602 RX Vref 0 -> 0, step: 1
6489 11:13:18.934044
6490 11:13:18.934486 RX Delay -359 -> 252, step: 8
6491 11:13:18.937276
6492 11:13:18.937718 Set Vref, RX VrefLevel [Byte0]: 59
6493 11:13:18.940127 [Byte1]: 47
6494 11:13:18.946079
6495 11:13:18.946522 Final RX Vref Byte 0 = 59 to rank0
6496 11:13:18.949098 Final RX Vref Byte 1 = 47 to rank0
6497 11:13:18.952898 Final RX Vref Byte 0 = 59 to rank1
6498 11:13:18.955789 Final RX Vref Byte 1 = 47 to rank1==
6499 11:13:18.958838 Dram Type= 6, Freq= 0, CH_0, rank 0
6500 11:13:18.965549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 11:13:18.965984 ==
6502 11:13:18.966367 DQS Delay:
6503 11:13:18.969113 DQS0 = 44, DQS1 = 60
6504 11:13:18.969596 DQM Delay:
6505 11:13:18.969936 DQM0 = 8, DQM1 = 12
6506 11:13:18.972644 DQ Delay:
6507 11:13:18.975573 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6508 11:13:18.976003 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6509 11:13:18.979009 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6510 11:13:18.981973 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6511 11:13:18.982397
6512 11:13:18.982728
6513 11:13:18.992212 [DQSOSCAuto] RK0, (LSB)MR18= 0xbf83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6514 11:13:18.995288 CH0 RK0: MR19=C0C, MR18=BF83
6515 11:13:19.002195 CH0_RK0: MR19=0xC0C, MR18=0xBF83, DQSOSC=386, MR23=63, INC=396, DEC=264
6516 11:13:19.002626 ==
6517 11:13:19.005740 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 11:13:19.008632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 11:13:19.009125 ==
6520 11:13:19.012080 [Gating] SW mode calibration
6521 11:13:19.018789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6522 11:13:19.025195 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6523 11:13:19.028911 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6524 11:13:19.031814 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6525 11:13:19.038546 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6526 11:13:19.041519 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6527 11:13:19.045337 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6528 11:13:19.051971 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6529 11:13:19.055291 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 11:13:19.059003 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 11:13:19.064873 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6532 11:13:19.065367 Total UI for P1: 0, mck2ui 16
6533 11:13:19.068553 best dqsien dly found for B0: ( 0, 14, 24)
6534 11:13:19.071417 Total UI for P1: 0, mck2ui 16
6535 11:13:19.074716 best dqsien dly found for B1: ( 0, 14, 24)
6536 11:13:19.081479 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6537 11:13:19.085183 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6538 11:13:19.085687
6539 11:13:19.088096 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6540 11:13:19.091511 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6541 11:13:19.094744 [Gating] SW calibration Done
6542 11:13:19.095169 ==
6543 11:13:19.097996 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 11:13:19.101278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 11:13:19.101708 ==
6546 11:13:19.104154 RX Vref Scan: 0
6547 11:13:19.104745
6548 11:13:19.105095 RX Vref 0 -> 0, step: 1
6549 11:13:19.105412
6550 11:13:19.107828 RX Delay -410 -> 252, step: 16
6551 11:13:19.114162 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6552 11:13:19.117701 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6553 11:13:19.120693 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6554 11:13:19.124208 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6555 11:13:19.130804 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6556 11:13:19.133825 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6557 11:13:19.137400 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6558 11:13:19.140416 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6559 11:13:19.147676 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6560 11:13:19.150848 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6561 11:13:19.153791 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6562 11:13:19.157359 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6563 11:13:19.164030 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6564 11:13:19.166935 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6565 11:13:19.170625 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6566 11:13:19.173781 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6567 11:13:19.177200 ==
6568 11:13:19.180566 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 11:13:19.183691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 11:13:19.184275 ==
6571 11:13:19.184670 DQS Delay:
6572 11:13:19.187321 DQS0 = 43, DQS1 = 59
6573 11:13:19.187781 DQM Delay:
6574 11:13:19.190147 DQM0 = 11, DQM1 = 16
6575 11:13:19.190609 DQ Delay:
6576 11:13:19.193467 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6577 11:13:19.197156 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6578 11:13:19.200041 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6579 11:13:19.203600 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6580 11:13:19.204190
6581 11:13:19.204746
6582 11:13:19.205228 ==
6583 11:13:19.207048 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 11:13:19.210238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 11:13:19.210833 ==
6586 11:13:19.211360
6587 11:13:19.211810
6588 11:13:19.213007 TX Vref Scan disable
6589 11:13:19.213659 == TX Byte 0 ==
6590 11:13:19.220071 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6591 11:13:19.222984 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6592 11:13:19.223558 == TX Byte 1 ==
6593 11:13:19.229708 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6594 11:13:19.233064 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6595 11:13:19.233173 ==
6596 11:13:19.235932 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 11:13:19.239586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 11:13:19.239695 ==
6599 11:13:19.239764
6600 11:13:19.239825
6601 11:13:19.242760 TX Vref Scan disable
6602 11:13:19.242867 == TX Byte 0 ==
6603 11:13:19.249335 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6604 11:13:19.252381 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6605 11:13:19.252498 == TX Byte 1 ==
6606 11:13:19.259687 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6607 11:13:19.262736 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6608 11:13:19.262867
6609 11:13:19.262975 [DATLAT]
6610 11:13:19.265755 Freq=400, CH0 RK1
6611 11:13:19.265886
6612 11:13:19.265999 DATLAT Default: 0xe
6613 11:13:19.269334 0, 0xFFFF, sum = 0
6614 11:13:19.269469 1, 0xFFFF, sum = 0
6615 11:13:19.272492 2, 0xFFFF, sum = 0
6616 11:13:19.272655 3, 0xFFFF, sum = 0
6617 11:13:19.275555 4, 0xFFFF, sum = 0
6618 11:13:19.278935 5, 0xFFFF, sum = 0
6619 11:13:19.279050 6, 0xFFFF, sum = 0
6620 11:13:19.282480 7, 0xFFFF, sum = 0
6621 11:13:19.282601 8, 0xFFFF, sum = 0
6622 11:13:19.285496 9, 0xFFFF, sum = 0
6623 11:13:19.285606 10, 0xFFFF, sum = 0
6624 11:13:19.288957 11, 0xFFFF, sum = 0
6625 11:13:19.289069 12, 0xFFFF, sum = 0
6626 11:13:19.292282 13, 0x0, sum = 1
6627 11:13:19.292395 14, 0x0, sum = 2
6628 11:13:19.295772 15, 0x0, sum = 3
6629 11:13:19.295883 16, 0x0, sum = 4
6630 11:13:19.298937 best_step = 14
6631 11:13:19.299055
6632 11:13:19.299155 ==
6633 11:13:19.302281 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 11:13:19.305367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 11:13:19.305482 ==
6636 11:13:19.305579 RX Vref Scan: 0
6637 11:13:19.305670
6638 11:13:19.308841 RX Vref 0 -> 0, step: 1
6639 11:13:19.308925
6640 11:13:19.311884 RX Delay -359 -> 252, step: 8
6641 11:13:19.319408 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6642 11:13:19.322939 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6643 11:13:19.325957 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6644 11:13:19.332766 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6645 11:13:19.335965 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6646 11:13:19.339549 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6647 11:13:19.342586 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6648 11:13:19.349111 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6649 11:13:19.352253 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6650 11:13:19.355736 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6651 11:13:19.358824 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6652 11:13:19.365426 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6653 11:13:19.369073 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6654 11:13:19.372115 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6655 11:13:19.375339 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6656 11:13:19.381787 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6657 11:13:19.381866 ==
6658 11:13:19.385493 Dram Type= 6, Freq= 0, CH_0, rank 1
6659 11:13:19.389105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 11:13:19.389178 ==
6661 11:13:19.389239 DQS Delay:
6662 11:13:19.392036 DQS0 = 44, DQS1 = 60
6663 11:13:19.392109 DQM Delay:
6664 11:13:19.395696 DQM0 = 8, DQM1 = 16
6665 11:13:19.395771 DQ Delay:
6666 11:13:19.398617 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6667 11:13:19.402032 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6668 11:13:19.405600 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6669 11:13:19.408534 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6670 11:13:19.408613
6671 11:13:19.408680
6672 11:13:19.415241 [DQSOSCAuto] RK1, (LSB)MR18= 0xb33e, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 387 ps
6673 11:13:19.418907 CH0 RK1: MR19=C0C, MR18=B33E
6674 11:13:19.425195 CH0_RK1: MR19=0xC0C, MR18=0xB33E, DQSOSC=387, MR23=63, INC=394, DEC=262
6675 11:13:19.428247 [RxdqsGatingPostProcess] freq 400
6676 11:13:19.434801 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6677 11:13:19.438553 best DQS0 dly(2T, 0.5T) = (0, 10)
6678 11:13:19.441382 best DQS1 dly(2T, 0.5T) = (0, 10)
6679 11:13:19.445131 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6680 11:13:19.448024 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6681 11:13:19.448128 best DQS0 dly(2T, 0.5T) = (0, 10)
6682 11:13:19.451707 best DQS1 dly(2T, 0.5T) = (0, 10)
6683 11:13:19.454822 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6684 11:13:19.457995 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6685 11:13:19.461616 Pre-setting of DQS Precalculation
6686 11:13:19.467826 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6687 11:13:19.468067 ==
6688 11:13:19.471610 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 11:13:19.474570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 11:13:19.474748 ==
6691 11:13:19.481195 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6692 11:13:19.487714 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6693 11:13:19.490661 [CA 0] Center 36 (8~64) winsize 57
6694 11:13:19.494162 [CA 1] Center 36 (8~64) winsize 57
6695 11:13:19.497367 [CA 2] Center 36 (8~64) winsize 57
6696 11:13:19.497450 [CA 3] Center 36 (8~64) winsize 57
6697 11:13:19.500975 [CA 4] Center 36 (8~64) winsize 57
6698 11:13:19.504366 [CA 5] Center 36 (8~64) winsize 57
6699 11:13:19.504491
6700 11:13:19.510905 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6701 11:13:19.511010
6702 11:13:19.514865 [CATrainingPosCal] consider 1 rank data
6703 11:13:19.518229 u2DelayCellTimex100 = 270/100 ps
6704 11:13:19.520918 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 11:13:19.523865 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 11:13:19.527364 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 11:13:19.530765 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 11:13:19.534406 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 11:13:19.537441 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 11:13:19.537648
6711 11:13:19.540558 CA PerBit enable=1, Macro0, CA PI delay=36
6712 11:13:19.540764
6713 11:13:19.544214 [CBTSetCACLKResult] CA Dly = 36
6714 11:13:19.547710 CS Dly: 1 (0~32)
6715 11:13:19.548018 ==
6716 11:13:19.550500 Dram Type= 6, Freq= 0, CH_1, rank 1
6717 11:13:19.554126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 11:13:19.554210 ==
6719 11:13:19.560146 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6720 11:13:19.563762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6721 11:13:19.566791 [CA 0] Center 36 (8~64) winsize 57
6722 11:13:19.570620 [CA 1] Center 36 (8~64) winsize 57
6723 11:13:19.573707 [CA 2] Center 36 (8~64) winsize 57
6724 11:13:19.577382 [CA 3] Center 36 (8~64) winsize 57
6725 11:13:19.580116 [CA 4] Center 36 (8~64) winsize 57
6726 11:13:19.583364 [CA 5] Center 36 (8~64) winsize 57
6727 11:13:19.583459
6728 11:13:19.587194 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6729 11:13:19.587298
6730 11:13:19.590095 [CATrainingPosCal] consider 2 rank data
6731 11:13:19.593632 u2DelayCellTimex100 = 270/100 ps
6732 11:13:19.596524 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 11:13:19.603098 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 11:13:19.606570 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 11:13:19.610290 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 11:13:19.613441 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 11:13:19.616680 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 11:13:19.616795
6739 11:13:19.619957 CA PerBit enable=1, Macro0, CA PI delay=36
6740 11:13:19.620152
6741 11:13:19.623577 [CBTSetCACLKResult] CA Dly = 36
6742 11:13:19.623783 CS Dly: 1 (0~32)
6743 11:13:19.626926
6744 11:13:19.630197 ----->DramcWriteLeveling(PI) begin...
6745 11:13:19.630468 ==
6746 11:13:19.633037 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 11:13:19.636760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 11:13:19.636938 ==
6749 11:13:19.639709 Write leveling (Byte 0): 40 => 8
6750 11:13:19.643349 Write leveling (Byte 1): 32 => 0
6751 11:13:19.646469 DramcWriteLeveling(PI) end<-----
6752 11:13:19.646716
6753 11:13:19.646911 ==
6754 11:13:19.649501 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 11:13:19.653199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 11:13:19.653550 ==
6757 11:13:19.656790 [Gating] SW mode calibration
6758 11:13:19.662896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6759 11:13:19.670031 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6760 11:13:19.672961 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6761 11:13:19.676142 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6762 11:13:19.682647 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6763 11:13:19.685747 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6764 11:13:19.689508 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6765 11:13:19.696162 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6766 11:13:19.699154 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 11:13:19.702451 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 11:13:19.709115 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6769 11:13:19.712404 Total UI for P1: 0, mck2ui 16
6770 11:13:19.716041 best dqsien dly found for B0: ( 0, 14, 24)
6771 11:13:19.716469 Total UI for P1: 0, mck2ui 16
6772 11:13:19.722279 best dqsien dly found for B1: ( 0, 14, 24)
6773 11:13:19.725822 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6774 11:13:19.728561 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6775 11:13:19.729015
6776 11:13:19.732172 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6777 11:13:19.735518 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6778 11:13:19.738921 [Gating] SW calibration Done
6779 11:13:19.739447 ==
6780 11:13:19.741914 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 11:13:19.745491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 11:13:19.746153 ==
6783 11:13:19.748551 RX Vref Scan: 0
6784 11:13:19.748987
6785 11:13:19.751645 RX Vref 0 -> 0, step: 1
6786 11:13:19.752154
6787 11:13:19.752579 RX Delay -410 -> 252, step: 16
6788 11:13:19.758446 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6789 11:13:19.762139 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6790 11:13:19.765085 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6791 11:13:19.771887 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6792 11:13:19.774954 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6793 11:13:19.778583 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6794 11:13:19.781674 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6795 11:13:19.788343 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6796 11:13:19.791202 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6797 11:13:19.794382 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6798 11:13:19.798216 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6799 11:13:19.804887 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6800 11:13:19.808205 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6801 11:13:19.811205 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6802 11:13:19.814326 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6803 11:13:19.821268 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6804 11:13:19.821695 ==
6805 11:13:19.824621 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 11:13:19.827519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 11:13:19.827945 ==
6808 11:13:19.828290 DQS Delay:
6809 11:13:19.830969 DQS0 = 43, DQS1 = 51
6810 11:13:19.831390 DQM Delay:
6811 11:13:19.834495 DQM0 = 12, DQM1 = 14
6812 11:13:19.834922 DQ Delay:
6813 11:13:19.837468 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6814 11:13:19.840986 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6815 11:13:19.844340 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6816 11:13:19.847878 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6817 11:13:19.848302
6818 11:13:19.848672
6819 11:13:19.848990 ==
6820 11:13:19.850961 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 11:13:19.854468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 11:13:19.854896 ==
6823 11:13:19.855232
6824 11:13:19.857538
6825 11:13:19.857958 TX Vref Scan disable
6826 11:13:19.861064 == TX Byte 0 ==
6827 11:13:19.864007 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6828 11:13:19.867662 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6829 11:13:19.870672 == TX Byte 1 ==
6830 11:13:19.874507 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6831 11:13:19.877177 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6832 11:13:19.877634 ==
6833 11:13:19.880822 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 11:13:19.883797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 11:13:19.886997 ==
6836 11:13:19.887415
6837 11:13:19.887784
6838 11:13:19.888094 TX Vref Scan disable
6839 11:13:19.890596 == TX Byte 0 ==
6840 11:13:19.894036 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6841 11:13:19.897105 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6842 11:13:19.900158 == TX Byte 1 ==
6843 11:13:19.903697 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6844 11:13:19.906890 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6845 11:13:19.907316
6846 11:13:19.910504 [DATLAT]
6847 11:13:19.910940 Freq=400, CH1 RK0
6848 11:13:19.911301
6849 11:13:19.913425 DATLAT Default: 0xf
6850 11:13:19.913862 0, 0xFFFF, sum = 0
6851 11:13:19.916964 1, 0xFFFF, sum = 0
6852 11:13:19.917408 2, 0xFFFF, sum = 0
6853 11:13:19.920322 3, 0xFFFF, sum = 0
6854 11:13:19.920846 4, 0xFFFF, sum = 0
6855 11:13:19.923379 5, 0xFFFF, sum = 0
6856 11:13:19.923809 6, 0xFFFF, sum = 0
6857 11:13:19.926844 7, 0xFFFF, sum = 0
6858 11:13:19.927336 8, 0xFFFF, sum = 0
6859 11:13:19.929874 9, 0xFFFF, sum = 0
6860 11:13:19.933274 10, 0xFFFF, sum = 0
6861 11:13:19.933710 11, 0xFFFF, sum = 0
6862 11:13:19.936936 12, 0xFFFF, sum = 0
6863 11:13:19.937370 13, 0x0, sum = 1
6864 11:13:19.939865 14, 0x0, sum = 2
6865 11:13:19.940300 15, 0x0, sum = 3
6866 11:13:19.943463 16, 0x0, sum = 4
6867 11:13:19.943948 best_step = 14
6868 11:13:19.944285
6869 11:13:19.944663 ==
6870 11:13:19.946372 Dram Type= 6, Freq= 0, CH_1, rank 0
6871 11:13:19.949776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 11:13:19.950351 ==
6873 11:13:19.953262 RX Vref Scan: 1
6874 11:13:19.953679
6875 11:13:19.956317 RX Vref 0 -> 0, step: 1
6876 11:13:19.956781
6877 11:13:19.957114 RX Delay -343 -> 252, step: 8
6878 11:13:19.957422
6879 11:13:19.959460 Set Vref, RX VrefLevel [Byte0]: 48
6880 11:13:19.962983 [Byte1]: 50
6881 11:13:19.968278
6882 11:13:19.968735 Final RX Vref Byte 0 = 48 to rank0
6883 11:13:19.971829 Final RX Vref Byte 1 = 50 to rank0
6884 11:13:19.975220 Final RX Vref Byte 0 = 48 to rank1
6885 11:13:19.978442 Final RX Vref Byte 1 = 50 to rank1==
6886 11:13:19.981430 Dram Type= 6, Freq= 0, CH_1, rank 0
6887 11:13:19.988234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 11:13:19.988817 ==
6889 11:13:19.989167 DQS Delay:
6890 11:13:19.991427 DQS0 = 44, DQS1 = 52
6891 11:13:19.991845 DQM Delay:
6892 11:13:19.992176 DQM0 = 8, DQM1 = 10
6893 11:13:19.994874 DQ Delay:
6894 11:13:19.998467 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6895 11:13:19.998887 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6896 11:13:20.001508 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6897 11:13:20.004471 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6898 11:13:20.004946
6899 11:13:20.008224
6900 11:13:20.014720 [DQSOSCAuto] RK0, (LSB)MR18= 0x956b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6901 11:13:20.018155 CH1 RK0: MR19=C0C, MR18=956B
6902 11:13:20.024768 CH1_RK0: MR19=0xC0C, MR18=0x956B, DQSOSC=391, MR23=63, INC=386, DEC=257
6903 11:13:20.025190 ==
6904 11:13:20.028417 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 11:13:20.031347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 11:13:20.031771 ==
6907 11:13:20.034395 [Gating] SW mode calibration
6908 11:13:20.041326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6909 11:13:20.047942 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6910 11:13:20.051460 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6911 11:13:20.054471 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6912 11:13:20.061050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6913 11:13:20.064479 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6914 11:13:20.067494 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6915 11:13:20.073802 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6916 11:13:20.077453 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 11:13:20.080645 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 11:13:20.087246 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6919 11:13:20.087669 Total UI for P1: 0, mck2ui 16
6920 11:13:20.094205 best dqsien dly found for B0: ( 0, 14, 24)
6921 11:13:20.094628 Total UI for P1: 0, mck2ui 16
6922 11:13:20.097104 best dqsien dly found for B1: ( 0, 14, 24)
6923 11:13:20.103855 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6924 11:13:20.106843 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6925 11:13:20.107494
6926 11:13:20.110501 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6927 11:13:20.113739 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6928 11:13:20.116740 [Gating] SW calibration Done
6929 11:13:20.117161 ==
6930 11:13:20.120152 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 11:13:20.123506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 11:13:20.123929 ==
6933 11:13:20.126878 RX Vref Scan: 0
6934 11:13:20.127295
6935 11:13:20.127628 RX Vref 0 -> 0, step: 1
6936 11:13:20.127958
6937 11:13:20.129984 RX Delay -410 -> 252, step: 16
6938 11:13:20.136483 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6939 11:13:20.139977 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6940 11:13:20.143540 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6941 11:13:20.146362 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6942 11:13:20.153105 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6943 11:13:20.156476 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6944 11:13:20.159972 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6945 11:13:20.163018 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6946 11:13:20.169763 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6947 11:13:20.172683 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6948 11:13:20.176281 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6949 11:13:20.179231 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6950 11:13:20.185867 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6951 11:13:20.189553 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6952 11:13:20.192480 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6953 11:13:20.199341 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6954 11:13:20.199423 ==
6955 11:13:20.202863 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 11:13:20.205874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 11:13:20.205956 ==
6958 11:13:20.206021 DQS Delay:
6959 11:13:20.208959 DQS0 = 51, DQS1 = 51
6960 11:13:20.209040 DQM Delay:
6961 11:13:20.212665 DQM0 = 19, DQM1 = 13
6962 11:13:20.212746 DQ Delay:
6963 11:13:20.215586 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6964 11:13:20.218664 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6965 11:13:20.222390 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6966 11:13:20.225276 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6967 11:13:20.225358
6968 11:13:20.225420
6969 11:13:20.225478 ==
6970 11:13:20.228830 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 11:13:20.232298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 11:13:20.232380 ==
6973 11:13:20.232445
6974 11:13:20.235214
6975 11:13:20.235295 TX Vref Scan disable
6976 11:13:20.238673 == TX Byte 0 ==
6977 11:13:20.242214 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6978 11:13:20.245384 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6979 11:13:20.248751 == TX Byte 1 ==
6980 11:13:20.252308 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6981 11:13:20.255466 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6982 11:13:20.255645 ==
6983 11:13:20.259359 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 11:13:20.261897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 11:13:20.265058 ==
6986 11:13:20.265257
6987 11:13:20.265363
6988 11:13:20.265461 TX Vref Scan disable
6989 11:13:20.268753 == TX Byte 0 ==
6990 11:13:20.271839 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6991 11:13:20.275430 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6992 11:13:20.278371 == TX Byte 1 ==
6993 11:13:20.281957 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6994 11:13:20.284820 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6995 11:13:20.285051
6996 11:13:20.288489 [DATLAT]
6997 11:13:20.288701 Freq=400, CH1 RK1
6998 11:13:20.288892
6999 11:13:20.291699 DATLAT Default: 0xe
7000 11:13:20.291938 0, 0xFFFF, sum = 0
7001 11:13:20.294780 1, 0xFFFF, sum = 0
7002 11:13:20.295082 2, 0xFFFF, sum = 0
7003 11:13:20.298695 3, 0xFFFF, sum = 0
7004 11:13:20.299188 4, 0xFFFF, sum = 0
7005 11:13:20.301580 5, 0xFFFF, sum = 0
7006 11:13:20.301972 6, 0xFFFF, sum = 0
7007 11:13:20.305353 7, 0xFFFF, sum = 0
7008 11:13:20.305778 8, 0xFFFF, sum = 0
7009 11:13:20.308353 9, 0xFFFF, sum = 0
7010 11:13:20.308824 10, 0xFFFF, sum = 0
7011 11:13:20.311458 11, 0xFFFF, sum = 0
7012 11:13:20.311884 12, 0xFFFF, sum = 0
7013 11:13:20.315416 13, 0x0, sum = 1
7014 11:13:20.316065 14, 0x0, sum = 2
7015 11:13:20.318037 15, 0x0, sum = 3
7016 11:13:20.318510 16, 0x0, sum = 4
7017 11:13:20.321095 best_step = 14
7018 11:13:20.321581
7019 11:13:20.321977 ==
7020 11:13:20.324614 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 11:13:20.327749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 11:13:20.328176 ==
7023 11:13:20.331287 RX Vref Scan: 0
7024 11:13:20.331856
7025 11:13:20.332256 RX Vref 0 -> 0, step: 1
7026 11:13:20.332736
7027 11:13:20.334242 RX Delay -343 -> 252, step: 8
7028 11:13:20.342676 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7029 11:13:20.346152 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7030 11:13:20.349445 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7031 11:13:20.355716 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7032 11:13:20.359398 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7033 11:13:20.363055 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7034 11:13:20.365858 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
7035 11:13:20.372549 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7036 11:13:20.375608 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7037 11:13:20.379032 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7038 11:13:20.382125 iDelay=225, Bit 10, Center -44 (-287 ~ 200) 488
7039 11:13:20.389272 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7040 11:13:20.392220 iDelay=225, Bit 12, Center -32 (-279 ~ 216) 496
7041 11:13:20.395999 iDelay=225, Bit 13, Center -36 (-279 ~ 208) 488
7042 11:13:20.398915 iDelay=225, Bit 14, Center -36 (-279 ~ 208) 488
7043 11:13:20.406048 iDelay=225, Bit 15, Center -36 (-279 ~ 208) 488
7044 11:13:20.406473 ==
7045 11:13:20.409136 Dram Type= 6, Freq= 0, CH_1, rank 1
7046 11:13:20.412268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7047 11:13:20.412724 ==
7048 11:13:20.413060 DQS Delay:
7049 11:13:20.415962 DQS0 = 48, DQS1 = 56
7050 11:13:20.416381 DQM Delay:
7051 11:13:20.418875 DQM0 = 14, DQM1 = 12
7052 11:13:20.419293 DQ Delay:
7053 11:13:20.422892 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
7054 11:13:20.425472 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =12
7055 11:13:20.429187 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7056 11:13:20.432162 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
7057 11:13:20.432634
7058 11:13:20.432973
7059 11:13:20.438707 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7060 11:13:20.442120 CH1 RK1: MR19=C0C, MR18=6B59
7061 11:13:20.448561 CH1_RK1: MR19=0xC0C, MR18=0x6B59, DQSOSC=396, MR23=63, INC=376, DEC=251
7062 11:13:20.452134 [RxdqsGatingPostProcess] freq 400
7063 11:13:20.458745 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7064 11:13:20.462220 best DQS0 dly(2T, 0.5T) = (0, 10)
7065 11:13:20.465066 best DQS1 dly(2T, 0.5T) = (0, 10)
7066 11:13:20.468545 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7067 11:13:20.471908 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7068 11:13:20.472329 best DQS0 dly(2T, 0.5T) = (0, 10)
7069 11:13:20.475075 best DQS1 dly(2T, 0.5T) = (0, 10)
7070 11:13:20.478904 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7071 11:13:20.481723 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7072 11:13:20.485265 Pre-setting of DQS Precalculation
7073 11:13:20.492100 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7074 11:13:20.498533 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7075 11:13:20.505175 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7076 11:13:20.505600
7077 11:13:20.505928
7078 11:13:20.508119 [Calibration Summary] 800 Mbps
7079 11:13:20.508620 CH 0, Rank 0
7080 11:13:20.511880 SW Impedance : PASS
7081 11:13:20.515058 DUTY Scan : NO K
7082 11:13:20.515488 ZQ Calibration : PASS
7083 11:13:20.517948 Jitter Meter : NO K
7084 11:13:20.521475 CBT Training : PASS
7085 11:13:20.521903 Write leveling : PASS
7086 11:13:20.525051 RX DQS gating : PASS
7087 11:13:20.528206 RX DQ/DQS(RDDQC) : PASS
7088 11:13:20.528671 TX DQ/DQS : PASS
7089 11:13:20.531133 RX DATLAT : PASS
7090 11:13:20.534614 RX DQ/DQS(Engine): PASS
7091 11:13:20.535042 TX OE : NO K
7092 11:13:20.537758 All Pass.
7093 11:13:20.538186
7094 11:13:20.538521 CH 0, Rank 1
7095 11:13:20.541343 SW Impedance : PASS
7096 11:13:20.541772 DUTY Scan : NO K
7097 11:13:20.544759 ZQ Calibration : PASS
7098 11:13:20.547717 Jitter Meter : NO K
7099 11:13:20.548147 CBT Training : PASS
7100 11:13:20.551289 Write leveling : NO K
7101 11:13:20.551732 RX DQS gating : PASS
7102 11:13:20.554318 RX DQ/DQS(RDDQC) : PASS
7103 11:13:20.557816 TX DQ/DQS : PASS
7104 11:13:20.558267 RX DATLAT : PASS
7105 11:13:20.561162 RX DQ/DQS(Engine): PASS
7106 11:13:20.564189 TX OE : NO K
7107 11:13:20.564655 All Pass.
7108 11:13:20.565012
7109 11:13:20.565321 CH 1, Rank 0
7110 11:13:20.567583 SW Impedance : PASS
7111 11:13:20.571180 DUTY Scan : NO K
7112 11:13:20.571601 ZQ Calibration : PASS
7113 11:13:20.574223 Jitter Meter : NO K
7114 11:13:20.577694 CBT Training : PASS
7115 11:13:20.578116 Write leveling : PASS
7116 11:13:20.580705 RX DQS gating : PASS
7117 11:13:20.584079 RX DQ/DQS(RDDQC) : PASS
7118 11:13:20.584496 TX DQ/DQS : PASS
7119 11:13:20.587710 RX DATLAT : PASS
7120 11:13:20.590566 RX DQ/DQS(Engine): PASS
7121 11:13:20.590991 TX OE : NO K
7122 11:13:20.594201 All Pass.
7123 11:13:20.594624
7124 11:13:20.594977 CH 1, Rank 1
7125 11:13:20.597292 SW Impedance : PASS
7126 11:13:20.597712 DUTY Scan : NO K
7127 11:13:20.600894 ZQ Calibration : PASS
7128 11:13:20.603743 Jitter Meter : NO K
7129 11:13:20.604165 CBT Training : PASS
7130 11:13:20.607445 Write leveling : NO K
7131 11:13:20.610522 RX DQS gating : PASS
7132 11:13:20.610945 RX DQ/DQS(RDDQC) : PASS
7133 11:13:20.614084 TX DQ/DQS : PASS
7134 11:13:20.616875 RX DATLAT : PASS
7135 11:13:20.617319 RX DQ/DQS(Engine): PASS
7136 11:13:20.620464 TX OE : NO K
7137 11:13:20.620935 All Pass.
7138 11:13:20.621264
7139 11:13:20.623696 DramC Write-DBI off
7140 11:13:20.627198 PER_BANK_REFRESH: Hybrid Mode
7141 11:13:20.627631 TX_TRACKING: ON
7142 11:13:20.637048 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7143 11:13:20.640683 [FAST_K] Save calibration result to emmc
7144 11:13:20.643906 dramc_set_vcore_voltage set vcore to 725000
7145 11:13:20.647497 Read voltage for 1600, 0
7146 11:13:20.648018 Vio18 = 0
7147 11:13:20.648350 Vcore = 725000
7148 11:13:20.650126 Vdram = 0
7149 11:13:20.650558 Vddq = 0
7150 11:13:20.650888 Vmddr = 0
7151 11:13:20.657024 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7152 11:13:20.660118 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7153 11:13:20.663603 MEM_TYPE=3, freq_sel=13
7154 11:13:20.666992 sv_algorithm_assistance_LP4_3733
7155 11:13:20.670341 ============ PULL DRAM RESETB DOWN ============
7156 11:13:20.673583 ========== PULL DRAM RESETB DOWN end =========
7157 11:13:20.680067 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7158 11:13:20.683716 ===================================
7159 11:13:20.684142 LPDDR4 DRAM CONFIGURATION
7160 11:13:20.686574 ===================================
7161 11:13:20.690111 EX_ROW_EN[0] = 0x0
7162 11:13:20.693881 EX_ROW_EN[1] = 0x0
7163 11:13:20.694411 LP4Y_EN = 0x0
7164 11:13:20.696505 WORK_FSP = 0x1
7165 11:13:20.696975 WL = 0x5
7166 11:13:20.699621 RL = 0x5
7167 11:13:20.700056 BL = 0x2
7168 11:13:20.703278 RPST = 0x0
7169 11:13:20.703876 RD_PRE = 0x0
7170 11:13:20.706248 WR_PRE = 0x1
7171 11:13:20.706671 WR_PST = 0x1
7172 11:13:20.709813 DBI_WR = 0x0
7173 11:13:20.710266 DBI_RD = 0x0
7174 11:13:20.712833 OTF = 0x1
7175 11:13:20.716421 ===================================
7176 11:13:20.719451 ===================================
7177 11:13:20.719875 ANA top config
7178 11:13:20.723081 ===================================
7179 11:13:20.726128 DLL_ASYNC_EN = 0
7180 11:13:20.729766 ALL_SLAVE_EN = 0
7181 11:13:20.732643 NEW_RANK_MODE = 1
7182 11:13:20.733094 DLL_IDLE_MODE = 1
7183 11:13:20.736559 LP45_APHY_COMB_EN = 1
7184 11:13:20.739411 TX_ODT_DIS = 0
7185 11:13:20.742999 NEW_8X_MODE = 1
7186 11:13:20.745926 ===================================
7187 11:13:20.749739 ===================================
7188 11:13:20.752627 data_rate = 3200
7189 11:13:20.756287 CKR = 1
7190 11:13:20.756896 DQ_P2S_RATIO = 8
7191 11:13:20.759244 ===================================
7192 11:13:20.762791 CA_P2S_RATIO = 8
7193 11:13:20.765636 DQ_CA_OPEN = 0
7194 11:13:20.769211 DQ_SEMI_OPEN = 0
7195 11:13:20.772334 CA_SEMI_OPEN = 0
7196 11:13:20.775792 CA_FULL_RATE = 0
7197 11:13:20.776238 DQ_CKDIV4_EN = 0
7198 11:13:20.779257 CA_CKDIV4_EN = 0
7199 11:13:20.782350 CA_PREDIV_EN = 0
7200 11:13:20.785794 PH8_DLY = 12
7201 11:13:20.789398 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7202 11:13:20.792304 DQ_AAMCK_DIV = 4
7203 11:13:20.792771 CA_AAMCK_DIV = 4
7204 11:13:20.795749 CA_ADMCK_DIV = 4
7205 11:13:20.798750 DQ_TRACK_CA_EN = 0
7206 11:13:20.801890 CA_PICK = 1600
7207 11:13:20.805778 CA_MCKIO = 1600
7208 11:13:20.808574 MCKIO_SEMI = 0
7209 11:13:20.812203 PLL_FREQ = 3068
7210 11:13:20.815217 DQ_UI_PI_RATIO = 32
7211 11:13:20.815640 CA_UI_PI_RATIO = 0
7212 11:13:20.819321 ===================================
7213 11:13:20.822390 ===================================
7214 11:13:20.825071 memory_type:LPDDR4
7215 11:13:20.828948 GP_NUM : 10
7216 11:13:20.829489 SRAM_EN : 1
7217 11:13:20.831646 MD32_EN : 0
7218 11:13:20.835462 ===================================
7219 11:13:20.838301 [ANA_INIT] >>>>>>>>>>>>>>
7220 11:13:20.841654 <<<<<< [CONFIGURE PHASE]: ANA_TX
7221 11:13:20.845296 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7222 11:13:20.848344 ===================================
7223 11:13:20.848830 data_rate = 3200,PCW = 0X7600
7224 11:13:20.851389 ===================================
7225 11:13:20.855056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7226 11:13:20.861415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7227 11:13:20.867846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7228 11:13:20.871577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7229 11:13:20.874204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7230 11:13:20.877938 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7231 11:13:20.880812 [ANA_INIT] flow start
7232 11:13:20.884426 [ANA_INIT] PLL >>>>>>>>
7233 11:13:20.884909 [ANA_INIT] PLL <<<<<<<<
7234 11:13:20.887392 [ANA_INIT] MIDPI >>>>>>>>
7235 11:13:20.891246 [ANA_INIT] MIDPI <<<<<<<<
7236 11:13:20.891674 [ANA_INIT] DLL >>>>>>>>
7237 11:13:20.894552 [ANA_INIT] DLL <<<<<<<<
7238 11:13:20.897237 [ANA_INIT] flow end
7239 11:13:20.900771 ============ LP4 DIFF to SE enter ============
7240 11:13:20.903808 ============ LP4 DIFF to SE exit ============
7241 11:13:20.907410 [ANA_INIT] <<<<<<<<<<<<<
7242 11:13:20.910807 [Flow] Enable top DCM control >>>>>
7243 11:13:20.914008 [Flow] Enable top DCM control <<<<<
7244 11:13:20.917410 Enable DLL master slave shuffle
7245 11:13:20.920437 ==============================================================
7246 11:13:20.924068 Gating Mode config
7247 11:13:20.930871 ==============================================================
7248 11:13:20.931406 Config description:
7249 11:13:20.940215 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7250 11:13:20.946731 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7251 11:13:20.953568 SELPH_MODE 0: By rank 1: By Phase
7252 11:13:20.956826 ==============================================================
7253 11:13:20.960118 GAT_TRACK_EN = 1
7254 11:13:20.963568 RX_GATING_MODE = 2
7255 11:13:20.966543 RX_GATING_TRACK_MODE = 2
7256 11:13:20.969955 SELPH_MODE = 1
7257 11:13:20.973282 PICG_EARLY_EN = 1
7258 11:13:20.976287 VALID_LAT_VALUE = 1
7259 11:13:20.983141 ==============================================================
7260 11:13:20.986675 Enter into Gating configuration >>>>
7261 11:13:20.989660 Exit from Gating configuration <<<<
7262 11:13:20.990090 Enter into DVFS_PRE_config >>>>>
7263 11:13:21.003221 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7264 11:13:21.006150 Exit from DVFS_PRE_config <<<<<
7265 11:13:21.009523 Enter into PICG configuration >>>>
7266 11:13:21.012878 Exit from PICG configuration <<<<
7267 11:13:21.016458 [RX_INPUT] configuration >>>>>
7268 11:13:21.017017 [RX_INPUT] configuration <<<<<
7269 11:13:21.022901 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7270 11:13:21.029392 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7271 11:13:21.032552 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7272 11:13:21.039255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7273 11:13:21.045964 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7274 11:13:21.052652 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7275 11:13:21.056780 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7276 11:13:21.059742 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7277 11:13:21.066234 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7278 11:13:21.069197 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7279 11:13:21.072678 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7280 11:13:21.079000 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7281 11:13:21.082534 ===================================
7282 11:13:21.082973 LPDDR4 DRAM CONFIGURATION
7283 11:13:21.086001 ===================================
7284 11:13:21.089024 EX_ROW_EN[0] = 0x0
7285 11:13:21.089454 EX_ROW_EN[1] = 0x0
7286 11:13:21.092623 LP4Y_EN = 0x0
7287 11:13:21.095438 WORK_FSP = 0x1
7288 11:13:21.095865 WL = 0x5
7289 11:13:21.099025 RL = 0x5
7290 11:13:21.099454 BL = 0x2
7291 11:13:21.102601 RPST = 0x0
7292 11:13:21.103028 RD_PRE = 0x0
7293 11:13:21.105529 WR_PRE = 0x1
7294 11:13:21.105969 WR_PST = 0x1
7295 11:13:21.108920 DBI_WR = 0x0
7296 11:13:21.109363 DBI_RD = 0x0
7297 11:13:21.112308 OTF = 0x1
7298 11:13:21.115572 ===================================
7299 11:13:21.118713 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7300 11:13:21.122274 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7301 11:13:21.128391 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7302 11:13:21.131997 ===================================
7303 11:13:21.132431 LPDDR4 DRAM CONFIGURATION
7304 11:13:21.135006 ===================================
7305 11:13:21.138953 EX_ROW_EN[0] = 0x10
7306 11:13:21.141979 EX_ROW_EN[1] = 0x0
7307 11:13:21.142555 LP4Y_EN = 0x0
7308 11:13:21.144787 WORK_FSP = 0x1
7309 11:13:21.145216 WL = 0x5
7310 11:13:21.148437 RL = 0x5
7311 11:13:21.148950 BL = 0x2
7312 11:13:21.151919 RPST = 0x0
7313 11:13:21.152351 RD_PRE = 0x0
7314 11:13:21.155010 WR_PRE = 0x1
7315 11:13:21.155565 WR_PST = 0x1
7316 11:13:21.157969 DBI_WR = 0x0
7317 11:13:21.158393 DBI_RD = 0x0
7318 11:13:21.161271 OTF = 0x1
7319 11:13:21.164203 ===================================
7320 11:13:21.170989 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7321 11:13:21.171072 ==
7322 11:13:21.174549 Dram Type= 6, Freq= 0, CH_0, rank 0
7323 11:13:21.177575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7324 11:13:21.177687 ==
7325 11:13:21.181384 [Duty_Offset_Calibration]
7326 11:13:21.181472 B0:1 B1:-1 CA:0
7327 11:13:21.181541
7328 11:13:21.184305 [DutyScan_Calibration_Flow] k_type=0
7329 11:13:21.195333
7330 11:13:21.195516 ==CLK 0==
7331 11:13:21.198181 Final CLK duty delay cell = 0
7332 11:13:21.201590 [0] MAX Duty = 5125%(X100), DQS PI = 24
7333 11:13:21.205347 [0] MIN Duty = 4907%(X100), DQS PI = 4
7334 11:13:21.205470 [0] AVG Duty = 5016%(X100)
7335 11:13:21.208214
7336 11:13:21.211662 CH0 CLK Duty spec in!! Max-Min= 218%
7337 11:13:21.214607 [DutyScan_Calibration_Flow] ====Done====
7338 11:13:21.214690
7339 11:13:21.218116 [DutyScan_Calibration_Flow] k_type=1
7340 11:13:21.233911
7341 11:13:21.234013 ==DQS 0 ==
7342 11:13:21.237569 Final DQS duty delay cell = -4
7343 11:13:21.240709 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7344 11:13:21.244405 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7345 11:13:21.247147 [-4] AVG Duty = 4922%(X100)
7346 11:13:21.247266
7347 11:13:21.247359 ==DQS 1 ==
7348 11:13:21.250725 Final DQS duty delay cell = 0
7349 11:13:21.254058 [0] MAX Duty = 5156%(X100), DQS PI = 0
7350 11:13:21.256999 [0] MIN Duty = 5031%(X100), DQS PI = 22
7351 11:13:21.260214 [0] AVG Duty = 5093%(X100)
7352 11:13:21.260362
7353 11:13:21.263790 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7354 11:13:21.263958
7355 11:13:21.266886 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7356 11:13:21.270593 [DutyScan_Calibration_Flow] ====Done====
7357 11:13:21.270818
7358 11:13:21.273697 [DutyScan_Calibration_Flow] k_type=3
7359 11:13:21.291848
7360 11:13:21.292399 ==DQM 0 ==
7361 11:13:21.295395 Final DQM duty delay cell = 0
7362 11:13:21.298551 [0] MAX Duty = 5124%(X100), DQS PI = 20
7363 11:13:21.301813 [0] MIN Duty = 4907%(X100), DQS PI = 8
7364 11:13:21.304778 [0] AVG Duty = 5015%(X100)
7365 11:13:21.305190
7366 11:13:21.305506 ==DQM 1 ==
7367 11:13:21.308190 Final DQM duty delay cell = 0
7368 11:13:21.311651 [0] MAX Duty = 5000%(X100), DQS PI = 4
7369 11:13:21.315128 [0] MIN Duty = 4813%(X100), DQS PI = 20
7370 11:13:21.318155 [0] AVG Duty = 4906%(X100)
7371 11:13:21.318573
7372 11:13:21.321964 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7373 11:13:21.322383
7374 11:13:21.324929 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7375 11:13:21.327995 [DutyScan_Calibration_Flow] ====Done====
7376 11:13:21.328411
7377 11:13:21.331275 [DutyScan_Calibration_Flow] k_type=2
7378 11:13:21.348155
7379 11:13:21.348573 ==DQ 0 ==
7380 11:13:21.351417 Final DQ duty delay cell = -4
7381 11:13:21.354986 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7382 11:13:21.357876 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7383 11:13:21.360889 [-4] AVG Duty = 4953%(X100)
7384 11:13:21.361303
7385 11:13:21.361626 ==DQ 1 ==
7386 11:13:21.364433 Final DQ duty delay cell = 0
7387 11:13:21.367683 [0] MAX Duty = 5125%(X100), DQS PI = 2
7388 11:13:21.371131 [0] MIN Duty = 5000%(X100), DQS PI = 34
7389 11:13:21.374152 [0] AVG Duty = 5062%(X100)
7390 11:13:21.374584
7391 11:13:21.377271 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7392 11:13:21.377715
7393 11:13:21.380956 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7394 11:13:21.383806 [DutyScan_Calibration_Flow] ====Done====
7395 11:13:21.384211 ==
7396 11:13:21.387267 Dram Type= 6, Freq= 0, CH_1, rank 0
7397 11:13:21.390910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7398 11:13:21.391466 ==
7399 11:13:21.393992 [Duty_Offset_Calibration]
7400 11:13:21.394501 B0:-1 B1:1 CA:2
7401 11:13:21.397411
7402 11:13:21.399977 [DutyScan_Calibration_Flow] k_type=0
7403 11:13:21.408196
7404 11:13:21.408339 ==CLK 0==
7405 11:13:21.411704 Final CLK duty delay cell = 0
7406 11:13:21.415037 [0] MAX Duty = 5187%(X100), DQS PI = 24
7407 11:13:21.417834 [0] MIN Duty = 4969%(X100), DQS PI = 0
7408 11:13:21.421372 [0] AVG Duty = 5078%(X100)
7409 11:13:21.421453
7410 11:13:21.424907 CH1 CLK Duty spec in!! Max-Min= 218%
7411 11:13:21.428226 [DutyScan_Calibration_Flow] ====Done====
7412 11:13:21.428692
7413 11:13:21.431482 [DutyScan_Calibration_Flow] k_type=1
7414 11:13:21.448232
7415 11:13:21.448708 ==DQS 0 ==
7416 11:13:21.451912 Final DQS duty delay cell = 0
7417 11:13:21.454938 [0] MAX Duty = 5156%(X100), DQS PI = 20
7418 11:13:21.458465 [0] MIN Duty = 4907%(X100), DQS PI = 10
7419 11:13:21.461513 [0] AVG Duty = 5031%(X100)
7420 11:13:21.461980
7421 11:13:21.462386 ==DQS 1 ==
7422 11:13:21.464740 Final DQS duty delay cell = 0
7423 11:13:21.468295 [0] MAX Duty = 5093%(X100), DQS PI = 22
7424 11:13:21.471274 [0] MIN Duty = 4969%(X100), DQS PI = 54
7425 11:13:21.474829 [0] AVG Duty = 5031%(X100)
7426 11:13:21.475283
7427 11:13:21.477971 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7428 11:13:21.478473
7429 11:13:21.481661 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7430 11:13:21.484794 [DutyScan_Calibration_Flow] ====Done====
7431 11:13:21.485211
7432 11:13:21.487862 [DutyScan_Calibration_Flow] k_type=3
7433 11:13:21.504380
7434 11:13:21.504876 ==DQM 0 ==
7435 11:13:21.507897 Final DQM duty delay cell = -4
7436 11:13:21.510876 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7437 11:13:21.514381 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7438 11:13:21.517937 [-4] AVG Duty = 4922%(X100)
7439 11:13:21.518426
7440 11:13:21.518844 ==DQM 1 ==
7441 11:13:21.520785 Final DQM duty delay cell = 0
7442 11:13:21.524196 [0] MAX Duty = 5125%(X100), DQS PI = 0
7443 11:13:21.527526 [0] MIN Duty = 4969%(X100), DQS PI = 34
7444 11:13:21.530651 [0] AVG Duty = 5047%(X100)
7445 11:13:21.531073
7446 11:13:21.534170 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7447 11:13:21.534593
7448 11:13:21.537107 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7449 11:13:21.540787 [DutyScan_Calibration_Flow] ====Done====
7450 11:13:21.541334
7451 11:13:21.543655 [DutyScan_Calibration_Flow] k_type=2
7452 11:13:21.561675
7453 11:13:21.562247 ==DQ 0 ==
7454 11:13:21.564667 Final DQ duty delay cell = 0
7455 11:13:21.568335 [0] MAX Duty = 5187%(X100), DQS PI = 32
7456 11:13:21.571404 [0] MIN Duty = 4906%(X100), DQS PI = 8
7457 11:13:21.571844 [0] AVG Duty = 5046%(X100)
7458 11:13:21.574537
7459 11:13:21.574973 ==DQ 1 ==
7460 11:13:21.578192 Final DQ duty delay cell = 0
7461 11:13:21.581116 [0] MAX Duty = 5156%(X100), DQS PI = 8
7462 11:13:21.585211 [0] MIN Duty = 4969%(X100), DQS PI = 56
7463 11:13:21.585786 [0] AVG Duty = 5062%(X100)
7464 11:13:21.586265
7465 11:13:21.590871 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7466 11:13:21.591381
7467 11:13:21.594331 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7468 11:13:21.597745 [DutyScan_Calibration_Flow] ====Done====
7469 11:13:21.600556 nWR fixed to 30
7470 11:13:21.603959 [ModeRegInit_LP4] CH0 RK0
7471 11:13:21.604212 [ModeRegInit_LP4] CH0 RK1
7472 11:13:21.607452 [ModeRegInit_LP4] CH1 RK0
7473 11:13:21.610979 [ModeRegInit_LP4] CH1 RK1
7474 11:13:21.611163 match AC timing 5
7475 11:13:21.617424 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7476 11:13:21.620354 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7477 11:13:21.623609 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7478 11:13:21.630112 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7479 11:13:21.633748 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7480 11:13:21.634090 [MiockJmeterHQA]
7481 11:13:21.636495
7482 11:13:21.636682 [DramcMiockJmeter] u1RxGatingPI = 0
7483 11:13:21.640445 0 : 4252, 4027
7484 11:13:21.640671 4 : 4257, 4029
7485 11:13:21.643414 8 : 4252, 4027
7486 11:13:21.643601 12 : 4366, 4140
7487 11:13:21.647057 16 : 4363, 4137
7488 11:13:21.647243 20 : 4252, 4027
7489 11:13:21.647400 24 : 4252, 4027
7490 11:13:21.649816 28 : 4253, 4027
7491 11:13:21.650003 32 : 4363, 4138
7492 11:13:21.653555 36 : 4252, 4027
7493 11:13:21.653748 40 : 4363, 4137
7494 11:13:21.656546 44 : 4250, 4027
7495 11:13:21.656755 48 : 4252, 4027
7496 11:13:21.660195 52 : 4250, 4027
7497 11:13:21.660380 56 : 4252, 4029
7498 11:13:21.660556 60 : 4361, 4138
7499 11:13:21.663043 64 : 4250, 4027
7500 11:13:21.663255 68 : 4361, 4137
7501 11:13:21.666846 72 : 4250, 4027
7502 11:13:21.667048 76 : 4250, 4027
7503 11:13:21.669892 80 : 4250, 4027
7504 11:13:21.670099 84 : 4361, 4138
7505 11:13:21.673035 88 : 4250, 4026
7506 11:13:21.673231 92 : 4360, 517
7507 11:13:21.673378 96 : 4253, 0
7508 11:13:21.676650 100 : 4252, 0
7509 11:13:21.676846 104 : 4250, 0
7510 11:13:21.679553 108 : 4250, 0
7511 11:13:21.679740 112 : 4252, 0
7512 11:13:21.679888 116 : 4250, 0
7513 11:13:21.683235 120 : 4250, 0
7514 11:13:21.683477 124 : 4252, 0
7515 11:13:21.686189 128 : 4250, 0
7516 11:13:21.686436 132 : 4250, 0
7517 11:13:21.686651 136 : 4252, 0
7518 11:13:21.689746 140 : 4250, 0
7519 11:13:21.690006 144 : 4361, 0
7520 11:13:21.690259 148 : 4360, 0
7521 11:13:21.692864 152 : 4250, 0
7522 11:13:21.693075 156 : 4250, 0
7523 11:13:21.695888 160 : 4250, 0
7524 11:13:21.696090 164 : 4250, 0
7525 11:13:21.696311 168 : 4250, 0
7526 11:13:21.699475 172 : 4250, 0
7527 11:13:21.699718 176 : 4252, 0
7528 11:13:21.703101 180 : 4361, 0
7529 11:13:21.703285 184 : 4250, 0
7530 11:13:21.703439 188 : 4250, 0
7531 11:13:21.705947 192 : 4250, 0
7532 11:13:21.706032 196 : 4361, 0
7533 11:13:21.709461 200 : 4360, 0
7534 11:13:21.709546 204 : 4250, 0
7535 11:13:21.709614 208 : 4361, 0
7536 11:13:21.712455 212 : 4250, 0
7537 11:13:21.712564 216 : 4250, 0
7538 11:13:21.715689 220 : 4251, 0
7539 11:13:21.715773 224 : 4250, 604
7540 11:13:21.715840 228 : 4361, 3641
7541 11:13:21.719098 232 : 4250, 4027
7542 11:13:21.719183 236 : 4360, 4137
7543 11:13:21.722130 240 : 4250, 4026
7544 11:13:21.722214 244 : 4250, 4027
7545 11:13:21.725655 248 : 4250, 4027
7546 11:13:21.725739 252 : 4252, 4029
7547 11:13:21.729404 256 : 4250, 4026
7548 11:13:21.729494 260 : 4250, 4027
7549 11:13:21.732454 264 : 4250, 4027
7550 11:13:21.732584 268 : 4252, 4029
7551 11:13:21.735902 272 : 4250, 4027
7552 11:13:21.736000 276 : 4361, 4137
7553 11:13:21.738677 280 : 4361, 4138
7554 11:13:21.738783 284 : 4250, 4027
7555 11:13:21.742258 288 : 4363, 4140
7556 11:13:21.742364 292 : 4250, 4027
7557 11:13:21.742447 296 : 4250, 4027
7558 11:13:21.745283 300 : 4252, 4027
7559 11:13:21.745366 304 : 4252, 4029
7560 11:13:21.748967 308 : 4250, 4027
7561 11:13:21.749050 312 : 4250, 4027
7562 11:13:21.751905 316 : 4250, 4027
7563 11:13:21.752014 320 : 4252, 4029
7564 11:13:21.755477 324 : 4250, 4026
7565 11:13:21.755561 328 : 4361, 4137
7566 11:13:21.758452 332 : 4360, 4138
7567 11:13:21.758535 336 : 4250, 3702
7568 11:13:21.762119 340 : 4363, 1701
7569 11:13:21.762202
7570 11:13:21.762267 MIOCK jitter meter ch=0
7571 11:13:21.762325
7572 11:13:21.765164 1T = (340-92) = 248 dly cells
7573 11:13:21.771855 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7574 11:13:21.771962 ==
7575 11:13:21.774898 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 11:13:21.778558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 11:13:21.778670 ==
7578 11:13:21.784773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7579 11:13:21.788291 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7580 11:13:21.794564 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7581 11:13:21.798217 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7582 11:13:21.808349 [CA 0] Center 43 (12~74) winsize 63
7583 11:13:21.811457 [CA 1] Center 42 (12~73) winsize 62
7584 11:13:21.814423 [CA 2] Center 38 (9~68) winsize 60
7585 11:13:21.817887 [CA 3] Center 38 (8~68) winsize 61
7586 11:13:21.821373 [CA 4] Center 36 (7~66) winsize 60
7587 11:13:21.824455 [CA 5] Center 35 (6~65) winsize 60
7588 11:13:21.824579
7589 11:13:21.827997 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7590 11:13:21.828085
7591 11:13:21.831629 [CATrainingPosCal] consider 1 rank data
7592 11:13:21.834511 u2DelayCellTimex100 = 262/100 ps
7593 11:13:21.841105 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7594 11:13:21.844563 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7595 11:13:21.847744 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7596 11:13:21.850788 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7597 11:13:21.854381 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7598 11:13:21.857265 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7599 11:13:21.857347
7600 11:13:21.860871 CA PerBit enable=1, Macro0, CA PI delay=35
7601 11:13:21.860962
7602 11:13:21.864317 [CBTSetCACLKResult] CA Dly = 35
7603 11:13:21.867388 CS Dly: 11 (0~42)
7604 11:13:21.870494 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7605 11:13:21.874159 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7606 11:13:21.874261 ==
7607 11:13:21.877160 Dram Type= 6, Freq= 0, CH_0, rank 1
7608 11:13:21.883700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 11:13:21.883818 ==
7610 11:13:21.886994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7611 11:13:21.893479 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7612 11:13:21.897080 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7613 11:13:21.903798 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7614 11:13:21.911638 [CA 0] Center 43 (13~74) winsize 62
7615 11:13:21.915106 [CA 1] Center 44 (14~74) winsize 61
7616 11:13:21.918133 [CA 2] Center 38 (9~68) winsize 60
7617 11:13:21.921689 [CA 3] Center 38 (9~68) winsize 60
7618 11:13:21.924721 [CA 4] Center 36 (7~66) winsize 60
7619 11:13:21.928196 [CA 5] Center 36 (6~66) winsize 61
7620 11:13:21.928300
7621 11:13:21.931134 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7622 11:13:21.931244
7623 11:13:21.934675 [CATrainingPosCal] consider 2 rank data
7624 11:13:21.937800 u2DelayCellTimex100 = 262/100 ps
7625 11:13:21.944501 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7626 11:13:21.948099 CA1 delay=43 (14~73),Diff = 8 PI (29 cell)
7627 11:13:21.951718 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7628 11:13:21.954690 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7629 11:13:21.957767 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7630 11:13:21.961340 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7631 11:13:21.961468
7632 11:13:21.964388 CA PerBit enable=1, Macro0, CA PI delay=35
7633 11:13:21.964537
7634 11:13:21.967999 [CBTSetCACLKResult] CA Dly = 35
7635 11:13:21.970872 CS Dly: 11 (0~43)
7636 11:13:21.974557 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7637 11:13:21.977523 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7638 11:13:21.977677
7639 11:13:21.981329 ----->DramcWriteLeveling(PI) begin...
7640 11:13:21.981521 ==
7641 11:13:21.987323 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 11:13:21.990297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 11:13:21.990553 ==
7644 11:13:21.993804 Write leveling (Byte 0): 37 => 37
7645 11:13:21.996979 Write leveling (Byte 1): 28 => 28
7646 11:13:22.000575 DramcWriteLeveling(PI) end<-----
7647 11:13:22.000887
7648 11:13:22.001148 ==
7649 11:13:22.003704 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 11:13:22.007423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 11:13:22.007868 ==
7652 11:13:22.010289 [Gating] SW mode calibration
7653 11:13:22.017260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7654 11:13:22.023555 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7655 11:13:22.026650 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 11:13:22.030081 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 11:13:22.036911 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 11:13:22.040012 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7659 11:13:22.043395 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7660 11:13:22.049944 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (1 1) (1 1)
7661 11:13:22.053381 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7662 11:13:22.057206 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 11:13:22.063322 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7664 11:13:22.066444 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7665 11:13:22.069762 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7666 11:13:22.076600 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
7667 11:13:22.079671 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7668 11:13:22.082765 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7669 11:13:22.089427 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7670 11:13:22.092863 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 11:13:22.095907 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 11:13:22.102558 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 11:13:22.106428 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 11:13:22.109409 1 6 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7675 11:13:22.115973 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7676 11:13:22.119029 1 6 20 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
7677 11:13:22.122478 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7678 11:13:22.128913 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 11:13:22.132617 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 11:13:22.135633 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 11:13:22.142442 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7682 11:13:22.145900 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7683 11:13:22.148840 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7684 11:13:22.156007 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7685 11:13:22.158847 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7686 11:13:22.161936 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 11:13:22.168724 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 11:13:22.172094 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 11:13:22.175242 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 11:13:22.182237 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 11:13:22.185085 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 11:13:22.188795 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 11:13:22.195154 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 11:13:22.198040 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 11:13:22.201774 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 11:13:22.208304 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 11:13:22.211272 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7698 11:13:22.214908 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7699 11:13:22.221710 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7700 11:13:22.222189 Total UI for P1: 0, mck2ui 16
7701 11:13:22.228062 best dqsien dly found for B0: ( 1, 9, 10)
7702 11:13:22.231377 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7703 11:13:22.234443 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7704 11:13:22.241177 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7705 11:13:22.241602 Total UI for P1: 0, mck2ui 16
7706 11:13:22.247656 best dqsien dly found for B1: ( 1, 9, 22)
7707 11:13:22.251010 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7708 11:13:22.254344 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7709 11:13:22.254426
7710 11:13:22.257309 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7711 11:13:22.260749 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7712 11:13:22.264048 [Gating] SW calibration Done
7713 11:13:22.264167 ==
7714 11:13:22.267014 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 11:13:22.270988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 11:13:22.271071 ==
7717 11:13:22.273849 RX Vref Scan: 0
7718 11:13:22.273930
7719 11:13:22.273994 RX Vref 0 -> 0, step: 1
7720 11:13:22.277204
7721 11:13:22.277285 RX Delay 0 -> 252, step: 8
7722 11:13:22.280630 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7723 11:13:22.287432 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7724 11:13:22.290263 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7725 11:13:22.293714 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7726 11:13:22.297070 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7727 11:13:22.300194 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7728 11:13:22.306939 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7729 11:13:22.310427 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7730 11:13:22.313532 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7731 11:13:22.316489 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7732 11:13:22.323520 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7733 11:13:22.326966 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7734 11:13:22.329846 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7735 11:13:22.333574 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7736 11:13:22.336474 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7737 11:13:22.343484 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7738 11:13:22.343914 ==
7739 11:13:22.347034 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 11:13:22.350616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 11:13:22.351095 ==
7742 11:13:22.351453 DQS Delay:
7743 11:13:22.353400 DQS0 = 0, DQS1 = 0
7744 11:13:22.353917 DQM Delay:
7745 11:13:22.356903 DQM0 = 136, DQM1 = 126
7746 11:13:22.357379 DQ Delay:
7747 11:13:22.360315 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7748 11:13:22.363285 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =147
7749 11:13:22.366603 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7750 11:13:22.369688 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7751 11:13:22.373342
7752 11:13:22.373913
7753 11:13:22.374478 ==
7754 11:13:22.376440 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 11:13:22.379976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 11:13:22.380545 ==
7757 11:13:22.380995
7758 11:13:22.381482
7759 11:13:22.382975 TX Vref Scan disable
7760 11:13:22.383507 == TX Byte 0 ==
7761 11:13:22.389656 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7762 11:13:22.393090 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7763 11:13:22.393656 == TX Byte 1 ==
7764 11:13:22.399115 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7765 11:13:22.402579 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7766 11:13:22.403165 ==
7767 11:13:22.406362 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 11:13:22.409378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 11:13:22.409941 ==
7770 11:13:22.422750
7771 11:13:22.426289 TX Vref early break, caculate TX vref
7772 11:13:22.429329 TX Vref=16, minBit 4, minWin=22, winSum=373
7773 11:13:22.432859 TX Vref=18, minBit 1, minWin=23, winSum=382
7774 11:13:22.436184 TX Vref=20, minBit 3, minWin=23, winSum=392
7775 11:13:22.439688 TX Vref=22, minBit 1, minWin=24, winSum=402
7776 11:13:22.442686 TX Vref=24, minBit 0, minWin=25, winSum=411
7777 11:13:22.449114 TX Vref=26, minBit 0, minWin=24, winSum=418
7778 11:13:22.452562 TX Vref=28, minBit 0, minWin=25, winSum=422
7779 11:13:22.455735 TX Vref=30, minBit 0, minWin=24, winSum=408
7780 11:13:22.459204 TX Vref=32, minBit 5, minWin=23, winSum=397
7781 11:13:22.466020 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
7782 11:13:22.466514
7783 11:13:22.469249 Final TX Range 0 Vref 28
7784 11:13:22.469669
7785 11:13:22.469999 ==
7786 11:13:22.472202 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 11:13:22.475873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 11:13:22.476330 ==
7789 11:13:22.476784
7790 11:13:22.477105
7791 11:13:22.478805 TX Vref Scan disable
7792 11:13:22.485407 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7793 11:13:22.485843 == TX Byte 0 ==
7794 11:13:22.488982 u2DelayCellOfst[0]=11 cells (3 PI)
7795 11:13:22.491938 u2DelayCellOfst[1]=14 cells (4 PI)
7796 11:13:22.495748 u2DelayCellOfst[2]=11 cells (3 PI)
7797 11:13:22.498734 u2DelayCellOfst[3]=11 cells (3 PI)
7798 11:13:22.502185 u2DelayCellOfst[4]=11 cells (3 PI)
7799 11:13:22.505122 u2DelayCellOfst[5]=0 cells (0 PI)
7800 11:13:22.508824 u2DelayCellOfst[6]=14 cells (4 PI)
7801 11:13:22.511820 u2DelayCellOfst[7]=18 cells (5 PI)
7802 11:13:22.514854 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7803 11:13:22.518589 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7804 11:13:22.521530 == TX Byte 1 ==
7805 11:13:22.525376 u2DelayCellOfst[8]=0 cells (0 PI)
7806 11:13:22.525899 u2DelayCellOfst[9]=3 cells (1 PI)
7807 11:13:22.528251 u2DelayCellOfst[10]=3 cells (1 PI)
7808 11:13:22.531812 u2DelayCellOfst[11]=3 cells (1 PI)
7809 11:13:22.534800 u2DelayCellOfst[12]=11 cells (3 PI)
7810 11:13:22.538407 u2DelayCellOfst[13]=11 cells (3 PI)
7811 11:13:22.541778 u2DelayCellOfst[14]=14 cells (4 PI)
7812 11:13:22.544687 u2DelayCellOfst[15]=11 cells (3 PI)
7813 11:13:22.548194 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7814 11:13:22.555310 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7815 11:13:22.555856 DramC Write-DBI on
7816 11:13:22.556287 ==
7817 11:13:22.557733 Dram Type= 6, Freq= 0, CH_0, rank 0
7818 11:13:22.564881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7819 11:13:22.565338 ==
7820 11:13:22.565673
7821 11:13:22.565983
7822 11:13:22.566284 TX Vref Scan disable
7823 11:13:22.569065 == TX Byte 0 ==
7824 11:13:22.571801 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7825 11:13:22.575301 == TX Byte 1 ==
7826 11:13:22.578217 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7827 11:13:22.581735 DramC Write-DBI off
7828 11:13:22.582159
7829 11:13:22.582492 [DATLAT]
7830 11:13:22.582804 Freq=1600, CH0 RK0
7831 11:13:22.583103
7832 11:13:22.585297 DATLAT Default: 0xf
7833 11:13:22.588286 0, 0xFFFF, sum = 0
7834 11:13:22.588743 1, 0xFFFF, sum = 0
7835 11:13:22.591614 2, 0xFFFF, sum = 0
7836 11:13:22.592067 3, 0xFFFF, sum = 0
7837 11:13:22.594995 4, 0xFFFF, sum = 0
7838 11:13:22.595437 5, 0xFFFF, sum = 0
7839 11:13:22.598025 6, 0xFFFF, sum = 0
7840 11:13:22.598467 7, 0xFFFF, sum = 0
7841 11:13:22.601463 8, 0xFFFF, sum = 0
7842 11:13:22.601906 9, 0xFFFF, sum = 0
7843 11:13:22.604473 10, 0xFFFF, sum = 0
7844 11:13:22.604951 11, 0xFFFF, sum = 0
7845 11:13:22.608363 12, 0xFFFF, sum = 0
7846 11:13:22.608857 13, 0xFFFF, sum = 0
7847 11:13:22.611281 14, 0x0, sum = 1
7848 11:13:22.611723 15, 0x0, sum = 2
7849 11:13:22.614836 16, 0x0, sum = 3
7850 11:13:22.615276 17, 0x0, sum = 4
7851 11:13:22.617915 best_step = 15
7852 11:13:22.618401
7853 11:13:22.618738 ==
7854 11:13:22.621625 Dram Type= 6, Freq= 0, CH_0, rank 0
7855 11:13:22.624697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7856 11:13:22.625120 ==
7857 11:13:22.627903 RX Vref Scan: 1
7858 11:13:22.628321
7859 11:13:22.628701 Set Vref Range= 24 -> 127
7860 11:13:22.629014
7861 11:13:22.631557 RX Vref 24 -> 127, step: 1
7862 11:13:22.631975
7863 11:13:22.634394 RX Delay 19 -> 252, step: 4
7864 11:13:22.634890
7865 11:13:22.637639 Set Vref, RX VrefLevel [Byte0]: 24
7866 11:13:22.641170 [Byte1]: 24
7867 11:13:22.641589
7868 11:13:22.644407 Set Vref, RX VrefLevel [Byte0]: 25
7869 11:13:22.647875 [Byte1]: 25
7870 11:13:22.651383
7871 11:13:22.651828 Set Vref, RX VrefLevel [Byte0]: 26
7872 11:13:22.654400 [Byte1]: 26
7873 11:13:22.658707
7874 11:13:22.659126 Set Vref, RX VrefLevel [Byte0]: 27
7875 11:13:22.661931 [Byte1]: 27
7876 11:13:22.666289
7877 11:13:22.666765 Set Vref, RX VrefLevel [Byte0]: 28
7878 11:13:22.669794 [Byte1]: 28
7879 11:13:22.673967
7880 11:13:22.674386 Set Vref, RX VrefLevel [Byte0]: 29
7881 11:13:22.677300 [Byte1]: 29
7882 11:13:22.681446
7883 11:13:22.681921 Set Vref, RX VrefLevel [Byte0]: 30
7884 11:13:22.684810 [Byte1]: 30
7885 11:13:22.688739
7886 11:13:22.689158 Set Vref, RX VrefLevel [Byte0]: 31
7887 11:13:22.692298 [Byte1]: 31
7888 11:13:22.696631
7889 11:13:22.697048 Set Vref, RX VrefLevel [Byte0]: 32
7890 11:13:22.700232 [Byte1]: 32
7891 11:13:22.704421
7892 11:13:22.704988 Set Vref, RX VrefLevel [Byte0]: 33
7893 11:13:22.707458 [Byte1]: 33
7894 11:13:22.711690
7895 11:13:22.712222 Set Vref, RX VrefLevel [Byte0]: 34
7896 11:13:22.715161 [Byte1]: 34
7897 11:13:22.719290
7898 11:13:22.719789 Set Vref, RX VrefLevel [Byte0]: 35
7899 11:13:22.722336 [Byte1]: 35
7900 11:13:22.726627
7901 11:13:22.727045 Set Vref, RX VrefLevel [Byte0]: 36
7902 11:13:22.730423 [Byte1]: 36
7903 11:13:22.734457
7904 11:13:22.734938 Set Vref, RX VrefLevel [Byte0]: 37
7905 11:13:22.737823 [Byte1]: 37
7906 11:13:22.741859
7907 11:13:22.742470 Set Vref, RX VrefLevel [Byte0]: 38
7908 11:13:22.745656 [Byte1]: 38
7909 11:13:22.749604
7910 11:13:22.750193 Set Vref, RX VrefLevel [Byte0]: 39
7911 11:13:22.753088 [Byte1]: 39
7912 11:13:22.757429
7913 11:13:22.757846 Set Vref, RX VrefLevel [Byte0]: 40
7914 11:13:22.760297 [Byte1]: 40
7915 11:13:22.764597
7916 11:13:22.765013 Set Vref, RX VrefLevel [Byte0]: 41
7917 11:13:22.767839 [Byte1]: 41
7918 11:13:22.772009
7919 11:13:22.772431 Set Vref, RX VrefLevel [Byte0]: 42
7920 11:13:22.775516 [Byte1]: 42
7921 11:13:22.779744
7922 11:13:22.780163 Set Vref, RX VrefLevel [Byte0]: 43
7923 11:13:22.783092 [Byte1]: 43
7924 11:13:22.787655
7925 11:13:22.788073 Set Vref, RX VrefLevel [Byte0]: 44
7926 11:13:22.790606 [Byte1]: 44
7927 11:13:22.795484
7928 11:13:22.795902 Set Vref, RX VrefLevel [Byte0]: 45
7929 11:13:22.798554 [Byte1]: 45
7930 11:13:22.802710
7931 11:13:22.803134 Set Vref, RX VrefLevel [Byte0]: 46
7932 11:13:22.806032 [Byte1]: 46
7933 11:13:22.810497
7934 11:13:22.810915 Set Vref, RX VrefLevel [Byte0]: 47
7935 11:13:22.813466 [Byte1]: 47
7936 11:13:22.817623
7937 11:13:22.818076 Set Vref, RX VrefLevel [Byte0]: 48
7938 11:13:22.821312 [Byte1]: 48
7939 11:13:22.825651
7940 11:13:22.826219 Set Vref, RX VrefLevel [Byte0]: 49
7941 11:13:22.828552 [Byte1]: 49
7942 11:13:22.832815
7943 11:13:22.833243 Set Vref, RX VrefLevel [Byte0]: 50
7944 11:13:22.836609 [Byte1]: 50
7945 11:13:22.840470
7946 11:13:22.841032 Set Vref, RX VrefLevel [Byte0]: 51
7947 11:13:22.843847 [Byte1]: 51
7948 11:13:22.848143
7949 11:13:22.848624 Set Vref, RX VrefLevel [Byte0]: 52
7950 11:13:22.851218 [Byte1]: 52
7951 11:13:22.855746
7952 11:13:22.856175 Set Vref, RX VrefLevel [Byte0]: 53
7953 11:13:22.859132 [Byte1]: 53
7954 11:13:22.863254
7955 11:13:22.863832 Set Vref, RX VrefLevel [Byte0]: 54
7956 11:13:22.866951 [Byte1]: 54
7957 11:13:22.871058
7958 11:13:22.871552 Set Vref, RX VrefLevel [Byte0]: 55
7959 11:13:22.873993 [Byte1]: 55
7960 11:13:22.878712
7961 11:13:22.879154 Set Vref, RX VrefLevel [Byte0]: 56
7962 11:13:22.881593 [Byte1]: 56
7963 11:13:22.886215
7964 11:13:22.886700 Set Vref, RX VrefLevel [Byte0]: 57
7965 11:13:22.888953 [Byte1]: 57
7966 11:13:22.893935
7967 11:13:22.894359 Set Vref, RX VrefLevel [Byte0]: 58
7968 11:13:22.897232 [Byte1]: 58
7969 11:13:22.901413
7970 11:13:22.901866 Set Vref, RX VrefLevel [Byte0]: 59
7971 11:13:22.904684 [Byte1]: 59
7972 11:13:22.908654
7973 11:13:22.909165 Set Vref, RX VrefLevel [Byte0]: 60
7974 11:13:22.912232 [Byte1]: 60
7975 11:13:22.916189
7976 11:13:22.916697 Set Vref, RX VrefLevel [Byte0]: 61
7977 11:13:22.919266 [Byte1]: 61
7978 11:13:22.923791
7979 11:13:22.924387 Set Vref, RX VrefLevel [Byte0]: 62
7980 11:13:22.927558 [Byte1]: 62
7981 11:13:22.931788
7982 11:13:22.932208 Set Vref, RX VrefLevel [Byte0]: 63
7983 11:13:22.935127 [Byte1]: 63
7984 11:13:22.939599
7985 11:13:22.940122 Set Vref, RX VrefLevel [Byte0]: 64
7986 11:13:22.942305 [Byte1]: 64
7987 11:13:22.946227
7988 11:13:22.946661 Set Vref, RX VrefLevel [Byte0]: 65
7989 11:13:22.949813 [Byte1]: 65
7990 11:13:22.953982
7991 11:13:22.954401 Set Vref, RX VrefLevel [Byte0]: 66
7992 11:13:22.957172 [Byte1]: 66
7993 11:13:22.961347
7994 11:13:22.961767 Set Vref, RX VrefLevel [Byte0]: 67
7995 11:13:22.964772 [Byte1]: 67
7996 11:13:22.969491
7997 11:13:22.969924 Set Vref, RX VrefLevel [Byte0]: 68
7998 11:13:22.972419 [Byte1]: 68
7999 11:13:22.976820
8000 11:13:22.977238 Set Vref, RX VrefLevel [Byte0]: 69
8001 11:13:22.980216 [Byte1]: 69
8002 11:13:22.984393
8003 11:13:22.984874 Set Vref, RX VrefLevel [Byte0]: 70
8004 11:13:22.987342 [Byte1]: 70
8005 11:13:22.991994
8006 11:13:22.992412 Set Vref, RX VrefLevel [Byte0]: 71
8007 11:13:22.995427 [Byte1]: 71
8008 11:13:22.999524
8009 11:13:22.999943 Set Vref, RX VrefLevel [Byte0]: 72
8010 11:13:23.002946 [Byte1]: 72
8011 11:13:23.007182
8012 11:13:23.010268 Set Vref, RX VrefLevel [Byte0]: 73
8013 11:13:23.013527 [Byte1]: 73
8014 11:13:23.014120
8015 11:13:23.016978 Set Vref, RX VrefLevel [Byte0]: 74
8016 11:13:23.019984 [Byte1]: 74
8017 11:13:23.020414
8018 11:13:23.023756 Set Vref, RX VrefLevel [Byte0]: 75
8019 11:13:23.026926 [Byte1]: 75
8020 11:13:23.027345
8021 11:13:23.030024 Set Vref, RX VrefLevel [Byte0]: 76
8022 11:13:23.032965 [Byte1]: 76
8023 11:13:23.037103
8024 11:13:23.037521 Set Vref, RX VrefLevel [Byte0]: 77
8025 11:13:23.041001 [Byte1]: 77
8026 11:13:23.044857
8027 11:13:23.045387 Set Vref, RX VrefLevel [Byte0]: 78
8028 11:13:23.048356 [Byte1]: 78
8029 11:13:23.052692
8030 11:13:23.053113 Final RX Vref Byte 0 = 66 to rank0
8031 11:13:23.055692 Final RX Vref Byte 1 = 58 to rank0
8032 11:13:23.059527 Final RX Vref Byte 0 = 66 to rank1
8033 11:13:23.062700 Final RX Vref Byte 1 = 58 to rank1==
8034 11:13:23.066247 Dram Type= 6, Freq= 0, CH_0, rank 0
8035 11:13:23.072270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 11:13:23.072759 ==
8037 11:13:23.073109 DQS Delay:
8038 11:13:23.075596 DQS0 = 0, DQS1 = 0
8039 11:13:23.076146 DQM Delay:
8040 11:13:23.076491 DQM0 = 133, DQM1 = 123
8041 11:13:23.078779 DQ Delay:
8042 11:13:23.082074 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =132
8043 11:13:23.085325 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8044 11:13:23.089023 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =118
8045 11:13:23.092464 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
8046 11:13:23.092984
8047 11:13:23.093338
8048 11:13:23.093660
8049 11:13:23.095241 [DramC_TX_OE_Calibration] TA2
8050 11:13:23.098821 Original DQ_B0 (3 6) =30, OEN = 27
8051 11:13:23.101829 Original DQ_B1 (3 6) =30, OEN = 27
8052 11:13:23.105418 24, 0x0, End_B0=24 End_B1=24
8053 11:13:23.105868 25, 0x0, End_B0=25 End_B1=25
8054 11:13:23.108986 26, 0x0, End_B0=26 End_B1=26
8055 11:13:23.111885 27, 0x0, End_B0=27 End_B1=27
8056 11:13:23.115074 28, 0x0, End_B0=28 End_B1=28
8057 11:13:23.118381 29, 0x0, End_B0=29 End_B1=29
8058 11:13:23.118846 30, 0x0, End_B0=30 End_B1=30
8059 11:13:23.121909 31, 0x5151, End_B0=30 End_B1=30
8060 11:13:23.125289 Byte0 end_step=30 best_step=27
8061 11:13:23.128432 Byte1 end_step=30 best_step=27
8062 11:13:23.131842 Byte0 TX OE(2T, 0.5T) = (3, 3)
8063 11:13:23.134959 Byte1 TX OE(2T, 0.5T) = (3, 3)
8064 11:13:23.135385
8065 11:13:23.135781
8066 11:13:23.141780 [DQSOSCAuto] RK0, (LSB)MR18= 0x2214, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8067 11:13:23.144729 CH0 RK0: MR19=303, MR18=2214
8068 11:13:23.151498 CH0_RK0: MR19=0x303, MR18=0x2214, DQSOSC=392, MR23=63, INC=24, DEC=16
8069 11:13:23.151926
8070 11:13:23.154283 ----->DramcWriteLeveling(PI) begin...
8071 11:13:23.154862 ==
8072 11:13:23.157584 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 11:13:23.161019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 11:13:23.161450 ==
8075 11:13:23.164638 Write leveling (Byte 0): 35 => 35
8076 11:13:23.167536 Write leveling (Byte 1): 29 => 29
8077 11:13:23.171119 DramcWriteLeveling(PI) end<-----
8078 11:13:23.171547
8079 11:13:23.171879 ==
8080 11:13:23.174202 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 11:13:23.181053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 11:13:23.181553 ==
8083 11:13:23.181907 [Gating] SW mode calibration
8084 11:13:23.190976 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8085 11:13:23.194041 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8086 11:13:23.197648 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 11:13:23.204038 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 11:13:23.207633 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 11:13:23.210385 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8090 11:13:23.216969 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8091 11:13:23.220490 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
8092 11:13:23.223739 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8093 11:13:23.230881 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8094 11:13:23.233859 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8095 11:13:23.236928 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8096 11:13:23.243807 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8097 11:13:23.247487 1 5 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
8098 11:13:23.250518 1 5 16 | B1->B0 | 3434 2626 | 0 0 | (0 1) (0 0)
8099 11:13:23.257180 1 5 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
8100 11:13:23.260168 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8101 11:13:23.263953 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 11:13:23.270633 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8103 11:13:23.273425 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8104 11:13:23.277128 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8105 11:13:23.283702 1 6 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
8106 11:13:23.286720 1 6 16 | B1->B0 | 2c2c 4444 | 0 0 | (0 0) (0 0)
8107 11:13:23.290518 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8108 11:13:23.296946 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 11:13:23.299866 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 11:13:23.303195 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 11:13:23.309628 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8112 11:13:23.313228 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8113 11:13:23.316680 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8114 11:13:23.323342 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8115 11:13:23.326740 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 11:13:23.329792 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8117 11:13:23.336179 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 11:13:23.340020 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 11:13:23.342964 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 11:13:23.349381 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 11:13:23.352600 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 11:13:23.355799 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 11:13:23.362421 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 11:13:23.365991 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 11:13:23.369044 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 11:13:23.376111 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 11:13:23.378943 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 11:13:23.382433 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8129 11:13:23.388899 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8130 11:13:23.392349 Total UI for P1: 0, mck2ui 16
8131 11:13:23.395503 best dqsien dly found for B0: ( 1, 9, 8)
8132 11:13:23.399006 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8133 11:13:23.402363 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8134 11:13:23.408775 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8135 11:13:23.411757 Total UI for P1: 0, mck2ui 16
8136 11:13:23.415300 best dqsien dly found for B1: ( 1, 9, 16)
8137 11:13:23.418761 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8138 11:13:23.421541 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8139 11:13:23.421974
8140 11:13:23.425308 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8141 11:13:23.428272 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8142 11:13:23.431896 [Gating] SW calibration Done
8143 11:13:23.432325 ==
8144 11:13:23.434857 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 11:13:23.438546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 11:13:23.438980 ==
8147 11:13:23.441436 RX Vref Scan: 0
8148 11:13:23.441864
8149 11:13:23.445168 RX Vref 0 -> 0, step: 1
8150 11:13:23.445598
8151 11:13:23.445935 RX Delay 0 -> 252, step: 8
8152 11:13:23.451696 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8153 11:13:23.454842 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8154 11:13:23.458153 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8155 11:13:23.461272 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8156 11:13:23.465004 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8157 11:13:23.470795 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8158 11:13:23.474442 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8159 11:13:23.477553 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8160 11:13:23.481075 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8161 11:13:23.484365 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8162 11:13:23.491378 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8163 11:13:23.494248 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8164 11:13:23.497627 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8165 11:13:23.500645 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8166 11:13:23.507596 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8167 11:13:23.510560 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8168 11:13:23.510994 ==
8169 11:13:23.514005 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 11:13:23.517448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 11:13:23.517993 ==
8172 11:13:23.520393 DQS Delay:
8173 11:13:23.520894 DQS0 = 0, DQS1 = 0
8174 11:13:23.521241 DQM Delay:
8175 11:13:23.523800 DQM0 = 133, DQM1 = 129
8176 11:13:23.524228 DQ Delay:
8177 11:13:23.527264 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8178 11:13:23.530348 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8179 11:13:23.534033 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8180 11:13:23.540628 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8181 11:13:23.541295
8182 11:13:23.541654
8183 11:13:23.541977 ==
8184 11:13:23.543503 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 11:13:23.547188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 11:13:23.547622 ==
8187 11:13:23.547961
8188 11:13:23.548276
8189 11:13:23.550169 TX Vref Scan disable
8190 11:13:23.550612 == TX Byte 0 ==
8191 11:13:23.556924 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8192 11:13:23.559995 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8193 11:13:23.560425 == TX Byte 1 ==
8194 11:13:23.566814 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8195 11:13:23.569655 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8196 11:13:23.570091 ==
8197 11:13:23.573452 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 11:13:23.576454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 11:13:23.576905 ==
8200 11:13:23.591631
8201 11:13:23.594425 TX Vref early break, caculate TX vref
8202 11:13:23.598135 TX Vref=16, minBit 2, minWin=22, winSum=379
8203 11:13:23.601260 TX Vref=18, minBit 1, minWin=22, winSum=389
8204 11:13:23.604490 TX Vref=20, minBit 1, minWin=23, winSum=397
8205 11:13:23.607417 TX Vref=22, minBit 1, minWin=24, winSum=406
8206 11:13:23.610719 TX Vref=24, minBit 1, minWin=24, winSum=411
8207 11:13:23.617907 TX Vref=26, minBit 0, minWin=25, winSum=418
8208 11:13:23.620654 TX Vref=28, minBit 0, minWin=24, winSum=415
8209 11:13:23.624166 TX Vref=30, minBit 1, minWin=23, winSum=405
8210 11:13:23.627265 TX Vref=32, minBit 1, minWin=23, winSum=397
8211 11:13:23.630688 TX Vref=34, minBit 1, minWin=22, winSum=390
8212 11:13:23.637262 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8213 11:13:23.637733
8214 11:13:23.640986 Final TX Range 0 Vref 26
8215 11:13:23.641420
8216 11:13:23.641798 ==
8217 11:13:23.644095 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 11:13:23.647096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 11:13:23.647656 ==
8220 11:13:23.648044
8221 11:13:23.648362
8222 11:13:23.650715 TX Vref Scan disable
8223 11:13:23.657433 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8224 11:13:23.657861 == TX Byte 0 ==
8225 11:13:23.660429 u2DelayCellOfst[0]=14 cells (4 PI)
8226 11:13:23.663698 u2DelayCellOfst[1]=18 cells (5 PI)
8227 11:13:23.667252 u2DelayCellOfst[2]=14 cells (4 PI)
8228 11:13:23.670718 u2DelayCellOfst[3]=14 cells (4 PI)
8229 11:13:23.673799 u2DelayCellOfst[4]=11 cells (3 PI)
8230 11:13:23.677153 u2DelayCellOfst[5]=0 cells (0 PI)
8231 11:13:23.680349 u2DelayCellOfst[6]=18 cells (5 PI)
8232 11:13:23.683969 u2DelayCellOfst[7]=22 cells (6 PI)
8233 11:13:23.687029 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8234 11:13:23.690237 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8235 11:13:23.694178 == TX Byte 1 ==
8236 11:13:23.696938 u2DelayCellOfst[8]=0 cells (0 PI)
8237 11:13:23.700295 u2DelayCellOfst[9]=3 cells (1 PI)
8238 11:13:23.703219 u2DelayCellOfst[10]=7 cells (2 PI)
8239 11:13:23.703646 u2DelayCellOfst[11]=3 cells (1 PI)
8240 11:13:23.707124 u2DelayCellOfst[12]=14 cells (4 PI)
8241 11:13:23.709775 u2DelayCellOfst[13]=14 cells (4 PI)
8242 11:13:23.713518 u2DelayCellOfst[14]=18 cells (5 PI)
8243 11:13:23.716664 u2DelayCellOfst[15]=11 cells (3 PI)
8244 11:13:23.723431 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8245 11:13:23.726360 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8246 11:13:23.726854 DramC Write-DBI on
8247 11:13:23.729811 ==
8248 11:13:23.730239 Dram Type= 6, Freq= 0, CH_0, rank 1
8249 11:13:23.736334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8250 11:13:23.736872 ==
8251 11:13:23.737222
8252 11:13:23.737538
8253 11:13:23.739677 TX Vref Scan disable
8254 11:13:23.740104 == TX Byte 0 ==
8255 11:13:23.746492 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8256 11:13:23.747124 == TX Byte 1 ==
8257 11:13:23.749742 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8258 11:13:23.752588 DramC Write-DBI off
8259 11:13:23.753015
8260 11:13:23.753354 [DATLAT]
8261 11:13:23.756172 Freq=1600, CH0 RK1
8262 11:13:23.756655
8263 11:13:23.757107 DATLAT Default: 0xf
8264 11:13:23.759337 0, 0xFFFF, sum = 0
8265 11:13:23.759777 1, 0xFFFF, sum = 0
8266 11:13:23.762858 2, 0xFFFF, sum = 0
8267 11:13:23.763331 3, 0xFFFF, sum = 0
8268 11:13:23.765940 4, 0xFFFF, sum = 0
8269 11:13:23.766443 5, 0xFFFF, sum = 0
8270 11:13:23.769323 6, 0xFFFF, sum = 0
8271 11:13:23.772381 7, 0xFFFF, sum = 0
8272 11:13:23.772873 8, 0xFFFF, sum = 0
8273 11:13:23.776102 9, 0xFFFF, sum = 0
8274 11:13:23.776574 10, 0xFFFF, sum = 0
8275 11:13:23.779084 11, 0xFFFF, sum = 0
8276 11:13:23.779541 12, 0xFFFF, sum = 0
8277 11:13:23.782857 13, 0xFFFF, sum = 0
8278 11:13:23.783293 14, 0x0, sum = 1
8279 11:13:23.785898 15, 0x0, sum = 2
8280 11:13:23.786352 16, 0x0, sum = 3
8281 11:13:23.788887 17, 0x0, sum = 4
8282 11:13:23.789330 best_step = 15
8283 11:13:23.789696
8284 11:13:23.790022 ==
8285 11:13:23.792575 Dram Type= 6, Freq= 0, CH_0, rank 1
8286 11:13:23.795488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 11:13:23.798677 ==
8288 11:13:23.799156 RX Vref Scan: 0
8289 11:13:23.799579
8290 11:13:23.802073 RX Vref 0 -> 0, step: 1
8291 11:13:23.802504
8292 11:13:23.805582 RX Delay 11 -> 252, step: 4
8293 11:13:23.808384 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8294 11:13:23.811940 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8295 11:13:23.814937 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8296 11:13:23.821356 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8297 11:13:23.824829 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8298 11:13:23.828215 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8299 11:13:23.831052 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8300 11:13:23.834660 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8301 11:13:23.841139 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8302 11:13:23.844670 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8303 11:13:23.847765 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8304 11:13:23.851262 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8305 11:13:23.854381 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8306 11:13:23.861012 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8307 11:13:23.864828 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8308 11:13:23.867848 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8309 11:13:23.867942 ==
8310 11:13:23.870912 Dram Type= 6, Freq= 0, CH_0, rank 1
8311 11:13:23.877372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 11:13:23.877456 ==
8313 11:13:23.877522 DQS Delay:
8314 11:13:23.877584 DQS0 = 0, DQS1 = 0
8315 11:13:23.880983 DQM Delay:
8316 11:13:23.881067 DQM0 = 130, DQM1 = 125
8317 11:13:23.884172 DQ Delay:
8318 11:13:23.887692 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8319 11:13:23.890732 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8320 11:13:23.894491 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8321 11:13:23.897357 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8322 11:13:23.897441
8323 11:13:23.897515
8324 11:13:23.897576
8325 11:13:23.900365 [DramC_TX_OE_Calibration] TA2
8326 11:13:23.903464 Original DQ_B0 (3 6) =30, OEN = 27
8327 11:13:23.907027 Original DQ_B1 (3 6) =30, OEN = 27
8328 11:13:23.910440 24, 0x0, End_B0=24 End_B1=24
8329 11:13:23.910543 25, 0x0, End_B0=25 End_B1=25
8330 11:13:23.913519 26, 0x0, End_B0=26 End_B1=26
8331 11:13:23.917096 27, 0x0, End_B0=27 End_B1=27
8332 11:13:23.920050 28, 0x0, End_B0=28 End_B1=28
8333 11:13:23.923765 29, 0x0, End_B0=29 End_B1=29
8334 11:13:23.923843 30, 0x0, End_B0=30 End_B1=30
8335 11:13:23.926948 31, 0x4141, End_B0=30 End_B1=30
8336 11:13:23.930500 Byte0 end_step=30 best_step=27
8337 11:13:23.933772 Byte1 end_step=30 best_step=27
8338 11:13:23.936792 Byte0 TX OE(2T, 0.5T) = (3, 3)
8339 11:13:23.940425 Byte1 TX OE(2T, 0.5T) = (3, 3)
8340 11:13:23.940553
8341 11:13:23.940631
8342 11:13:23.946891 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8343 11:13:23.950250 CH0 RK1: MR19=303, MR18=1E01
8344 11:13:23.957008 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8345 11:13:23.960038 [RxdqsGatingPostProcess] freq 1600
8346 11:13:23.963508 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8347 11:13:23.966539 best DQS0 dly(2T, 0.5T) = (1, 1)
8348 11:13:23.970218 best DQS1 dly(2T, 0.5T) = (1, 1)
8349 11:13:23.973225 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8350 11:13:23.976340 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8351 11:13:23.980154 best DQS0 dly(2T, 0.5T) = (1, 1)
8352 11:13:23.983126 best DQS1 dly(2T, 0.5T) = (1, 1)
8353 11:13:23.986668 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8354 11:13:23.989868 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8355 11:13:23.993373 Pre-setting of DQS Precalculation
8356 11:13:23.996489 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8357 11:13:23.996677 ==
8358 11:13:24.000020 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 11:13:24.006215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 11:13:24.006509 ==
8361 11:13:24.009987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8362 11:13:24.016491 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8363 11:13:24.020124 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8364 11:13:24.027467 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8365 11:13:24.034047 [CA 0] Center 41 (12~71) winsize 60
8366 11:13:24.037429 [CA 1] Center 42 (13~71) winsize 59
8367 11:13:24.040894 [CA 2] Center 37 (8~66) winsize 59
8368 11:13:24.043895 [CA 3] Center 36 (7~65) winsize 59
8369 11:13:24.047197 [CA 4] Center 37 (7~67) winsize 61
8370 11:13:24.050918 [CA 5] Center 36 (7~66) winsize 60
8371 11:13:24.051337
8372 11:13:24.053829 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8373 11:13:24.054251
8374 11:13:24.057355 [CATrainingPosCal] consider 1 rank data
8375 11:13:24.060653 u2DelayCellTimex100 = 262/100 ps
8376 11:13:24.066866 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8377 11:13:24.070453 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8378 11:13:24.073630 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8379 11:13:24.077270 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8380 11:13:24.080235 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8381 11:13:24.083773 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8382 11:13:24.084272
8383 11:13:24.086845 CA PerBit enable=1, Macro0, CA PI delay=36
8384 11:13:24.087272
8385 11:13:24.089949 [CBTSetCACLKResult] CA Dly = 36
8386 11:13:24.093110 CS Dly: 9 (0~40)
8387 11:13:24.096584 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8388 11:13:24.099748 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8389 11:13:24.100190 ==
8390 11:13:24.102840 Dram Type= 6, Freq= 0, CH_1, rank 1
8391 11:13:24.110032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 11:13:24.110453 ==
8393 11:13:24.113040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8394 11:13:24.119243 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8395 11:13:24.122758 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8396 11:13:24.129582 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8397 11:13:24.137225 [CA 0] Center 43 (14~72) winsize 59
8398 11:13:24.140579 [CA 1] Center 42 (13~72) winsize 60
8399 11:13:24.143586 [CA 2] Center 37 (8~67) winsize 60
8400 11:13:24.146950 [CA 3] Center 37 (8~67) winsize 60
8401 11:13:24.150639 [CA 4] Center 37 (8~67) winsize 60
8402 11:13:24.154008 [CA 5] Center 37 (8~67) winsize 60
8403 11:13:24.154452
8404 11:13:24.157001 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8405 11:13:24.157426
8406 11:13:24.160369 [CATrainingPosCal] consider 2 rank data
8407 11:13:24.164140 u2DelayCellTimex100 = 262/100 ps
8408 11:13:24.169954 CA0 delay=42 (14~71),Diff = 6 PI (22 cell)
8409 11:13:24.173425 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8410 11:13:24.176598 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8411 11:13:24.180236 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8412 11:13:24.183230 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8413 11:13:24.186748 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8414 11:13:24.187176
8415 11:13:24.189780 CA PerBit enable=1, Macro0, CA PI delay=36
8416 11:13:24.190218
8417 11:13:24.193585 [CBTSetCACLKResult] CA Dly = 36
8418 11:13:24.196666 CS Dly: 11 (0~44)
8419 11:13:24.200204 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8420 11:13:24.203347 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8421 11:13:24.203894
8422 11:13:24.206380 ----->DramcWriteLeveling(PI) begin...
8423 11:13:24.206813 ==
8424 11:13:24.210302 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 11:13:24.216566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 11:13:24.217018 ==
8427 11:13:24.219506 Write leveling (Byte 0): 23 => 23
8428 11:13:24.222935 Write leveling (Byte 1): 26 => 26
8429 11:13:24.223510 DramcWriteLeveling(PI) end<-----
8430 11:13:24.224029
8431 11:13:24.226559 ==
8432 11:13:24.229978 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 11:13:24.232998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 11:13:24.233590 ==
8435 11:13:24.236067 [Gating] SW mode calibration
8436 11:13:24.242530 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8437 11:13:24.245983 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8438 11:13:24.252349 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 11:13:24.256258 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 11:13:24.259342 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 11:13:24.266298 1 4 12 | B1->B0 | 2f2f 3434 | 1 0 | (0 0) (0 0)
8442 11:13:24.269148 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 11:13:24.272350 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 11:13:24.279156 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 11:13:24.282339 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8446 11:13:24.285951 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8447 11:13:24.292306 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8448 11:13:24.295500 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8449 11:13:24.298760 1 5 12 | B1->B0 | 3131 2727 | 0 0 | (0 1) (1 0)
8450 11:13:24.305671 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8451 11:13:24.308632 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 11:13:24.311736 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 11:13:24.318797 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8454 11:13:24.321722 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8455 11:13:24.325367 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8456 11:13:24.332119 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8457 11:13:24.335201 1 6 12 | B1->B0 | 3232 4040 | 1 0 | (0 0) (0 0)
8458 11:13:24.338171 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 11:13:24.344902 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 11:13:24.348335 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 11:13:24.351692 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 11:13:24.358071 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 11:13:24.361642 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 11:13:24.365064 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8465 11:13:24.371664 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8466 11:13:24.374646 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8467 11:13:24.377759 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 11:13:24.384778 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 11:13:24.387663 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 11:13:24.390761 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 11:13:24.397363 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 11:13:24.401053 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 11:13:24.404115 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 11:13:24.410967 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 11:13:24.414464 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 11:13:24.417356 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 11:13:24.423958 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 11:13:24.427739 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 11:13:24.430611 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 11:13:24.437548 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8481 11:13:24.440812 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8482 11:13:24.443821 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 11:13:24.447565 Total UI for P1: 0, mck2ui 16
8484 11:13:24.450226 best dqsien dly found for B0: ( 1, 9, 10)
8485 11:13:24.453734 Total UI for P1: 0, mck2ui 16
8486 11:13:24.457355 best dqsien dly found for B1: ( 1, 9, 10)
8487 11:13:24.460845 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8488 11:13:24.463706 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8489 11:13:24.464129
8490 11:13:24.469984 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8491 11:13:24.473591 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8492 11:13:24.477303 [Gating] SW calibration Done
8493 11:13:24.477727 ==
8494 11:13:24.480257 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 11:13:24.483508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 11:13:24.483937 ==
8497 11:13:24.484270 RX Vref Scan: 0
8498 11:13:24.486904
8499 11:13:24.487328 RX Vref 0 -> 0, step: 1
8500 11:13:24.487666
8501 11:13:24.489741 RX Delay 0 -> 252, step: 8
8502 11:13:24.493412 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8503 11:13:24.496447 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8504 11:13:24.503297 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8505 11:13:24.506890 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8506 11:13:24.510164 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8507 11:13:24.512849 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8508 11:13:24.516687 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8509 11:13:24.523245 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8510 11:13:24.526284 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8511 11:13:24.529322 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8512 11:13:24.532828 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8513 11:13:24.539319 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8514 11:13:24.542850 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8515 11:13:24.545933 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8516 11:13:24.549549 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8517 11:13:24.552381 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8518 11:13:24.556049 ==
8519 11:13:24.559306 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 11:13:24.562991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 11:13:24.563551 ==
8522 11:13:24.563987 DQS Delay:
8523 11:13:24.565806 DQS0 = 0, DQS1 = 0
8524 11:13:24.566270 DQM Delay:
8525 11:13:24.569025 DQM0 = 137, DQM1 = 129
8526 11:13:24.569449 DQ Delay:
8527 11:13:24.572834 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8528 11:13:24.575862 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8529 11:13:24.579523 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8530 11:13:24.582383 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8531 11:13:24.582809
8532 11:13:24.583144
8533 11:13:24.583456 ==
8534 11:13:24.585518 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 11:13:24.592329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 11:13:24.592798 ==
8537 11:13:24.593193
8538 11:13:24.593522
8539 11:13:24.595482 TX Vref Scan disable
8540 11:13:24.595904 == TX Byte 0 ==
8541 11:13:24.599028 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8542 11:13:24.605131 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8543 11:13:24.605683 == TX Byte 1 ==
8544 11:13:24.608965 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8545 11:13:24.615502 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8546 11:13:24.616018 ==
8547 11:13:24.618578 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 11:13:24.621522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 11:13:24.621954 ==
8550 11:13:24.635024
8551 11:13:24.637846 TX Vref early break, caculate TX vref
8552 11:13:24.641562 TX Vref=16, minBit 5, minWin=21, winSum=372
8553 11:13:24.644440 TX Vref=18, minBit 0, minWin=22, winSum=385
8554 11:13:24.648116 TX Vref=20, minBit 0, minWin=22, winSum=391
8555 11:13:24.651233 TX Vref=22, minBit 5, minWin=23, winSum=400
8556 11:13:24.654838 TX Vref=24, minBit 0, minWin=24, winSum=409
8557 11:13:24.661052 TX Vref=26, minBit 0, minWin=24, winSum=418
8558 11:13:24.664442 TX Vref=28, minBit 5, minWin=24, winSum=420
8559 11:13:24.667856 TX Vref=30, minBit 0, minWin=23, winSum=410
8560 11:13:24.670762 TX Vref=32, minBit 0, minWin=24, winSum=403
8561 11:13:24.674195 TX Vref=34, minBit 5, minWin=22, winSum=391
8562 11:13:24.680787 [TxChooseVref] Worse bit 5, Min win 24, Win sum 420, Final Vref 28
8563 11:13:24.681254
8564 11:13:24.684142 Final TX Range 0 Vref 28
8565 11:13:24.684802
8566 11:13:24.685161 ==
8567 11:13:24.687233 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 11:13:24.690884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 11:13:24.691469 ==
8570 11:13:24.691946
8571 11:13:24.692441
8572 11:13:24.693807 TX Vref Scan disable
8573 11:13:24.700282 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8574 11:13:24.700864 == TX Byte 0 ==
8575 11:13:24.703804 u2DelayCellOfst[0]=14 cells (4 PI)
8576 11:13:24.707343 u2DelayCellOfst[1]=11 cells (3 PI)
8577 11:13:24.710374 u2DelayCellOfst[2]=0 cells (0 PI)
8578 11:13:24.713499 u2DelayCellOfst[3]=3 cells (1 PI)
8579 11:13:24.717140 u2DelayCellOfst[4]=7 cells (2 PI)
8580 11:13:24.720215 u2DelayCellOfst[5]=18 cells (5 PI)
8581 11:13:24.723235 u2DelayCellOfst[6]=18 cells (5 PI)
8582 11:13:24.726805 u2DelayCellOfst[7]=3 cells (1 PI)
8583 11:13:24.729870 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8584 11:13:24.733466 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8585 11:13:24.736739 == TX Byte 1 ==
8586 11:13:24.740180 u2DelayCellOfst[8]=0 cells (0 PI)
8587 11:13:24.743783 u2DelayCellOfst[9]=3 cells (1 PI)
8588 11:13:24.746753 u2DelayCellOfst[10]=11 cells (3 PI)
8589 11:13:24.747198 u2DelayCellOfst[11]=3 cells (1 PI)
8590 11:13:24.749752 u2DelayCellOfst[12]=14 cells (4 PI)
8591 11:13:24.753382 u2DelayCellOfst[13]=18 cells (5 PI)
8592 11:13:24.756466 u2DelayCellOfst[14]=18 cells (5 PI)
8593 11:13:24.760230 u2DelayCellOfst[15]=18 cells (5 PI)
8594 11:13:24.766112 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8595 11:13:24.769469 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8596 11:13:24.769948 DramC Write-DBI on
8597 11:13:24.772958 ==
8598 11:13:24.776442 Dram Type= 6, Freq= 0, CH_1, rank 0
8599 11:13:24.779931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8600 11:13:24.780357 ==
8601 11:13:24.780736
8602 11:13:24.781051
8603 11:13:24.782744 TX Vref Scan disable
8604 11:13:24.783164 == TX Byte 0 ==
8605 11:13:24.789261 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8606 11:13:24.789686 == TX Byte 1 ==
8607 11:13:24.792389 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8608 11:13:24.795771 DramC Write-DBI off
8609 11:13:24.796195
8610 11:13:24.796561 [DATLAT]
8611 11:13:24.799025 Freq=1600, CH1 RK0
8612 11:13:24.799446
8613 11:13:24.799777 DATLAT Default: 0xf
8614 11:13:24.802616 0, 0xFFFF, sum = 0
8615 11:13:24.803047 1, 0xFFFF, sum = 0
8616 11:13:24.806148 2, 0xFFFF, sum = 0
8617 11:13:24.806580 3, 0xFFFF, sum = 0
8618 11:13:24.809879 4, 0xFFFF, sum = 0
8619 11:13:24.812740 5, 0xFFFF, sum = 0
8620 11:13:24.813178 6, 0xFFFF, sum = 0
8621 11:13:24.815805 7, 0xFFFF, sum = 0
8622 11:13:24.816236 8, 0xFFFF, sum = 0
8623 11:13:24.819532 9, 0xFFFF, sum = 0
8624 11:13:24.819961 10, 0xFFFF, sum = 0
8625 11:13:24.822600 11, 0xFFFF, sum = 0
8626 11:13:24.823033 12, 0xFFFF, sum = 0
8627 11:13:24.825676 13, 0xFFFF, sum = 0
8628 11:13:24.826126 14, 0x0, sum = 1
8629 11:13:24.828736 15, 0x0, sum = 2
8630 11:13:24.829166 16, 0x0, sum = 3
8631 11:13:24.832335 17, 0x0, sum = 4
8632 11:13:24.832797 best_step = 15
8633 11:13:24.833133
8634 11:13:24.833442 ==
8635 11:13:24.835481 Dram Type= 6, Freq= 0, CH_1, rank 0
8636 11:13:24.841962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8637 11:13:24.842393 ==
8638 11:13:24.842731 RX Vref Scan: 1
8639 11:13:24.843043
8640 11:13:24.845669 Set Vref Range= 24 -> 127
8641 11:13:24.846094
8642 11:13:24.848790 RX Vref 24 -> 127, step: 1
8643 11:13:24.849216
8644 11:13:24.849549 RX Delay 11 -> 252, step: 4
8645 11:13:24.849865
8646 11:13:24.851602 Set Vref, RX VrefLevel [Byte0]: 24
8647 11:13:24.855088 [Byte1]: 24
8648 11:13:24.859291
8649 11:13:24.859715 Set Vref, RX VrefLevel [Byte0]: 25
8650 11:13:24.862335 [Byte1]: 25
8651 11:13:24.866848
8652 11:13:24.867269 Set Vref, RX VrefLevel [Byte0]: 26
8653 11:13:24.870408 [Byte1]: 26
8654 11:13:24.874302
8655 11:13:24.874728 Set Vref, RX VrefLevel [Byte0]: 27
8656 11:13:24.877769 [Byte1]: 27
8657 11:13:24.882521
8658 11:13:24.882944 Set Vref, RX VrefLevel [Byte0]: 28
8659 11:13:24.884989 [Byte1]: 28
8660 11:13:24.889907
8661 11:13:24.890329 Set Vref, RX VrefLevel [Byte0]: 29
8662 11:13:24.892840 [Byte1]: 29
8663 11:13:24.897201
8664 11:13:24.897667 Set Vref, RX VrefLevel [Byte0]: 30
8665 11:13:24.900233 [Byte1]: 30
8666 11:13:24.905238
8667 11:13:24.905659 Set Vref, RX VrefLevel [Byte0]: 31
8668 11:13:24.908105 [Byte1]: 31
8669 11:13:24.912858
8670 11:13:24.913330 Set Vref, RX VrefLevel [Byte0]: 32
8671 11:13:24.915926 [Byte1]: 32
8672 11:13:24.919962
8673 11:13:24.920382 Set Vref, RX VrefLevel [Byte0]: 33
8674 11:13:24.923686 [Byte1]: 33
8675 11:13:24.928036
8676 11:13:24.928460 Set Vref, RX VrefLevel [Byte0]: 34
8677 11:13:24.931375 [Byte1]: 34
8678 11:13:24.935400
8679 11:13:24.935912 Set Vref, RX VrefLevel [Byte0]: 35
8680 11:13:24.938976 [Byte1]: 35
8681 11:13:24.943388
8682 11:13:24.943902 Set Vref, RX VrefLevel [Byte0]: 36
8683 11:13:24.946417 [Byte1]: 36
8684 11:13:24.950814
8685 11:13:24.951381 Set Vref, RX VrefLevel [Byte0]: 37
8686 11:13:24.953735 [Byte1]: 37
8687 11:13:24.957731
8688 11:13:24.957813 Set Vref, RX VrefLevel [Byte0]: 38
8689 11:13:24.960984 [Byte1]: 38
8690 11:13:24.966144
8691 11:13:24.966232 Set Vref, RX VrefLevel [Byte0]: 39
8692 11:13:24.969043 [Byte1]: 39
8693 11:13:24.973281
8694 11:13:24.973376 Set Vref, RX VrefLevel [Byte0]: 40
8695 11:13:24.976207 [Byte1]: 40
8696 11:13:24.981102
8697 11:13:24.981215 Set Vref, RX VrefLevel [Byte0]: 41
8698 11:13:24.983771 [Byte1]: 41
8699 11:13:24.988643
8700 11:13:24.988724 Set Vref, RX VrefLevel [Byte0]: 42
8701 11:13:24.991965 [Byte1]: 42
8702 11:13:24.995904
8703 11:13:24.995975 Set Vref, RX VrefLevel [Byte0]: 43
8704 11:13:24.999348 [Byte1]: 43
8705 11:13:25.003956
8706 11:13:25.004037 Set Vref, RX VrefLevel [Byte0]: 44
8707 11:13:25.006880 [Byte1]: 44
8708 11:13:25.011151
8709 11:13:25.011237 Set Vref, RX VrefLevel [Byte0]: 45
8710 11:13:25.014854 [Byte1]: 45
8711 11:13:25.019081
8712 11:13:25.019163 Set Vref, RX VrefLevel [Byte0]: 46
8713 11:13:25.022006 [Byte1]: 46
8714 11:13:25.026253
8715 11:13:25.026348 Set Vref, RX VrefLevel [Byte0]: 47
8716 11:13:25.029502 [Byte1]: 47
8717 11:13:25.034282
8718 11:13:25.034440 Set Vref, RX VrefLevel [Byte0]: 48
8719 11:13:25.037266 [Byte1]: 48
8720 11:13:25.041457
8721 11:13:25.041579 Set Vref, RX VrefLevel [Byte0]: 49
8722 11:13:25.045108 [Byte1]: 49
8723 11:13:25.049416
8724 11:13:25.049553 Set Vref, RX VrefLevel [Byte0]: 50
8725 11:13:25.052481 [Byte1]: 50
8726 11:13:25.056819
8727 11:13:25.057005 Set Vref, RX VrefLevel [Byte0]: 51
8728 11:13:25.060025 [Byte1]: 51
8729 11:13:25.064511
8730 11:13:25.064735 Set Vref, RX VrefLevel [Byte0]: 52
8731 11:13:25.067386 [Byte1]: 52
8732 11:13:25.071831
8733 11:13:25.071913 Set Vref, RX VrefLevel [Byte0]: 53
8734 11:13:25.075456 [Byte1]: 53
8735 11:13:25.079572
8736 11:13:25.079654 Set Vref, RX VrefLevel [Byte0]: 54
8737 11:13:25.083143 [Byte1]: 54
8738 11:13:25.087474
8739 11:13:25.087556 Set Vref, RX VrefLevel [Byte0]: 55
8740 11:13:25.090453 [Byte1]: 55
8741 11:13:25.095230
8742 11:13:25.095650 Set Vref, RX VrefLevel [Byte0]: 56
8743 11:13:25.098706 [Byte1]: 56
8744 11:13:25.103090
8745 11:13:25.103513 Set Vref, RX VrefLevel [Byte0]: 57
8746 11:13:25.105906 [Byte1]: 57
8747 11:13:25.110446
8748 11:13:25.110870 Set Vref, RX VrefLevel [Byte0]: 58
8749 11:13:25.113444 [Byte1]: 58
8750 11:13:25.117728
8751 11:13:25.118151 Set Vref, RX VrefLevel [Byte0]: 59
8752 11:13:25.121156 [Byte1]: 59
8753 11:13:25.125333
8754 11:13:25.125415 Set Vref, RX VrefLevel [Byte0]: 60
8755 11:13:25.128851 [Byte1]: 60
8756 11:13:25.133177
8757 11:13:25.133272 Set Vref, RX VrefLevel [Byte0]: 61
8758 11:13:25.136260 [Byte1]: 61
8759 11:13:25.140449
8760 11:13:25.140643 Set Vref, RX VrefLevel [Byte0]: 62
8761 11:13:25.144333 [Byte1]: 62
8762 11:13:25.148558
8763 11:13:25.148982 Set Vref, RX VrefLevel [Byte0]: 63
8764 11:13:25.151810 [Byte1]: 63
8765 11:13:25.156129
8766 11:13:25.156573 Set Vref, RX VrefLevel [Byte0]: 64
8767 11:13:25.159176 [Byte1]: 64
8768 11:13:25.163543
8769 11:13:25.163964 Set Vref, RX VrefLevel [Byte0]: 65
8770 11:13:25.167067 [Byte1]: 65
8771 11:13:25.171376
8772 11:13:25.171462 Set Vref, RX VrefLevel [Byte0]: 66
8773 11:13:25.174007 [Byte1]: 66
8774 11:13:25.178855
8775 11:13:25.178937 Set Vref, RX VrefLevel [Byte0]: 67
8776 11:13:25.181868 [Byte1]: 67
8777 11:13:25.186197
8778 11:13:25.186279 Set Vref, RX VrefLevel [Byte0]: 68
8779 11:13:25.189227 [Byte1]: 68
8780 11:13:25.194024
8781 11:13:25.194106 Set Vref, RX VrefLevel [Byte0]: 69
8782 11:13:25.196815 [Byte1]: 69
8783 11:13:25.201471
8784 11:13:25.201553 Set Vref, RX VrefLevel [Byte0]: 70
8785 11:13:25.204850 [Byte1]: 70
8786 11:13:25.208826
8787 11:13:25.208908 Set Vref, RX VrefLevel [Byte0]: 71
8788 11:13:25.212169 [Byte1]: 71
8789 11:13:25.216964
8790 11:13:25.217046 Set Vref, RX VrefLevel [Byte0]: 72
8791 11:13:25.219751 [Byte1]: 72
8792 11:13:25.224413
8793 11:13:25.224501 Set Vref, RX VrefLevel [Byte0]: 73
8794 11:13:25.227405 [Byte1]: 73
8795 11:13:25.231714
8796 11:13:25.231808 Final RX Vref Byte 0 = 52 to rank0
8797 11:13:25.235671 Final RX Vref Byte 1 = 58 to rank0
8798 11:13:25.238768 Final RX Vref Byte 0 = 52 to rank1
8799 11:13:25.242613 Final RX Vref Byte 1 = 58 to rank1==
8800 11:13:25.245518 Dram Type= 6, Freq= 0, CH_1, rank 0
8801 11:13:25.252357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8802 11:13:25.252826 ==
8803 11:13:25.253162 DQS Delay:
8804 11:13:25.255245 DQS0 = 0, DQS1 = 0
8805 11:13:25.255674 DQM Delay:
8806 11:13:25.256028 DQM0 = 133, DQM1 = 127
8807 11:13:25.259058 DQ Delay:
8808 11:13:25.261900 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8809 11:13:25.265513 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8810 11:13:25.268496 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8811 11:13:25.271962 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8812 11:13:25.272385
8813 11:13:25.272769
8814 11:13:25.273083
8815 11:13:25.275230 [DramC_TX_OE_Calibration] TA2
8816 11:13:25.279016 Original DQ_B0 (3 6) =30, OEN = 27
8817 11:13:25.281899 Original DQ_B1 (3 6) =30, OEN = 27
8818 11:13:25.285606 24, 0x0, End_B0=24 End_B1=24
8819 11:13:25.286040 25, 0x0, End_B0=25 End_B1=25
8820 11:13:25.288915 26, 0x0, End_B0=26 End_B1=26
8821 11:13:25.291697 27, 0x0, End_B0=27 End_B1=27
8822 11:13:25.295399 28, 0x0, End_B0=28 End_B1=28
8823 11:13:25.298501 29, 0x0, End_B0=29 End_B1=29
8824 11:13:25.298933 30, 0x0, End_B0=30 End_B1=30
8825 11:13:25.301828 31, 0x4141, End_B0=30 End_B1=30
8826 11:13:25.305207 Byte0 end_step=30 best_step=27
8827 11:13:25.308141 Byte1 end_step=30 best_step=27
8828 11:13:25.311492 Byte0 TX OE(2T, 0.5T) = (3, 3)
8829 11:13:25.314890 Byte1 TX OE(2T, 0.5T) = (3, 3)
8830 11:13:25.315339
8831 11:13:25.315743
8832 11:13:25.321426 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8833 11:13:25.325008 CH1 RK0: MR19=303, MR18=1A0F
8834 11:13:25.331204 CH1_RK0: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8835 11:13:25.331694
8836 11:13:25.334767 ----->DramcWriteLeveling(PI) begin...
8837 11:13:25.335214 ==
8838 11:13:25.338259 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 11:13:25.341170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 11:13:25.341742 ==
8841 11:13:25.345009 Write leveling (Byte 0): 23 => 23
8842 11:13:25.347892 Write leveling (Byte 1): 27 => 27
8843 11:13:25.350975 DramcWriteLeveling(PI) end<-----
8844 11:13:25.351397
8845 11:13:25.351729 ==
8846 11:13:25.354733 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 11:13:25.357772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 11:13:25.360693 ==
8849 11:13:25.361218 [Gating] SW mode calibration
8850 11:13:25.370904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8851 11:13:25.374230 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8852 11:13:25.377590 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 11:13:25.383791 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8854 11:13:25.386993 1 4 8 | B1->B0 | 2524 2323 | 1 0 | (0 0) (0 0)
8855 11:13:25.390820 1 4 12 | B1->B0 | 3433 2424 | 1 0 | (0 0) (0 0)
8856 11:13:25.397013 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8857 11:13:25.400620 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8858 11:13:25.403813 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8859 11:13:25.410316 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8860 11:13:25.413512 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8861 11:13:25.416815 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8862 11:13:25.423730 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8863 11:13:25.426988 1 5 12 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)
8864 11:13:25.430113 1 5 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8865 11:13:25.436744 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 11:13:25.440302 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 11:13:25.443316 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8868 11:13:25.450369 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8869 11:13:25.453802 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8870 11:13:25.457175 1 6 8 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (0 0)
8871 11:13:25.463855 1 6 12 | B1->B0 | 4646 2b2a | 0 1 | (0 0) (0 0)
8872 11:13:25.466972 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 11:13:25.470286 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 11:13:25.476586 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 11:13:25.479580 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 11:13:25.483188 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8877 11:13:25.489708 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 11:13:25.492916 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8879 11:13:25.496664 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8880 11:13:25.502791 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8881 11:13:25.506650 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 11:13:25.509289 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 11:13:25.515842 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 11:13:25.519309 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 11:13:25.522617 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 11:13:25.529383 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 11:13:25.532251 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 11:13:25.536136 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 11:13:25.542312 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 11:13:25.545711 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 11:13:25.548609 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 11:13:25.555709 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 11:13:25.558917 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8894 11:13:25.562393 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8895 11:13:25.568362 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8896 11:13:25.571978 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 11:13:25.574961 Total UI for P1: 0, mck2ui 16
8898 11:13:25.578083 best dqsien dly found for B0: ( 1, 9, 12)
8899 11:13:25.581707 Total UI for P1: 0, mck2ui 16
8900 11:13:25.584869 best dqsien dly found for B1: ( 1, 9, 8)
8901 11:13:25.587927 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8902 11:13:25.591411 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8903 11:13:25.591853
8904 11:13:25.594415 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8905 11:13:25.601292 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8906 11:13:25.601912 [Gating] SW calibration Done
8907 11:13:25.602418 ==
8908 11:13:25.604338 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 11:13:25.611070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 11:13:25.611527 ==
8911 11:13:25.611970 RX Vref Scan: 0
8912 11:13:25.612326
8913 11:13:25.614088 RX Vref 0 -> 0, step: 1
8914 11:13:25.614514
8915 11:13:25.617577 RX Delay 0 -> 252, step: 8
8916 11:13:25.620630 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8917 11:13:25.624193 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8918 11:13:25.627772 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8919 11:13:25.634241 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8920 11:13:25.637599 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8921 11:13:25.640986 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8922 11:13:25.643948 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8923 11:13:25.647351 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8924 11:13:25.653791 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8925 11:13:25.657328 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8926 11:13:25.660429 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8927 11:13:25.664046 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8928 11:13:25.666982 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8929 11:13:25.673791 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8930 11:13:25.676881 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8931 11:13:25.679896 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8932 11:13:25.680618 ==
8933 11:13:25.683465 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 11:13:25.690209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 11:13:25.690644 ==
8936 11:13:25.690983 DQS Delay:
8937 11:13:25.691295 DQS0 = 0, DQS1 = 0
8938 11:13:25.693194 DQM Delay:
8939 11:13:25.693621 DQM0 = 137, DQM1 = 129
8940 11:13:25.696708 DQ Delay:
8941 11:13:25.699743 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8942 11:13:25.703536 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8943 11:13:25.706535 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8944 11:13:25.709628 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8945 11:13:25.710074
8946 11:13:25.710415
8947 11:13:25.710726 ==
8948 11:13:25.713142 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 11:13:25.716206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 11:13:25.719824 ==
8951 11:13:25.720252
8952 11:13:25.720621
8953 11:13:25.720943 TX Vref Scan disable
8954 11:13:25.723336 == TX Byte 0 ==
8955 11:13:25.726421 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8956 11:13:25.729303 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8957 11:13:25.732622 == TX Byte 1 ==
8958 11:13:25.736155 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8959 11:13:25.739485 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8960 11:13:25.742689 ==
8961 11:13:25.746549 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 11:13:25.749576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 11:13:25.749665 ==
8964 11:13:25.762644
8965 11:13:25.766302 TX Vref early break, caculate TX vref
8966 11:13:25.769181 TX Vref=16, minBit 1, minWin=22, winSum=376
8967 11:13:25.772395 TX Vref=18, minBit 0, minWin=23, winSum=395
8968 11:13:25.775963 TX Vref=20, minBit 1, minWin=23, winSum=399
8969 11:13:25.779146 TX Vref=22, minBit 5, minWin=23, winSum=403
8970 11:13:25.782528 TX Vref=24, minBit 1, minWin=24, winSum=412
8971 11:13:25.789373 TX Vref=26, minBit 0, minWin=25, winSum=418
8972 11:13:25.792419 TX Vref=28, minBit 0, minWin=24, winSum=418
8973 11:13:25.796097 TX Vref=30, minBit 0, minWin=24, winSum=410
8974 11:13:25.798900 TX Vref=32, minBit 0, minWin=23, winSum=404
8975 11:13:25.802434 TX Vref=34, minBit 0, minWin=23, winSum=398
8976 11:13:25.809203 TX Vref=36, minBit 0, minWin=21, winSum=384
8977 11:13:25.812156 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8978 11:13:25.812721
8979 11:13:25.815426 Final TX Range 0 Vref 26
8980 11:13:25.815853
8981 11:13:25.816190 ==
8982 11:13:25.818817 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 11:13:25.822005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 11:13:25.822435 ==
8985 11:13:25.825540
8986 11:13:25.825964
8987 11:13:25.826299 TX Vref Scan disable
8988 11:13:25.832360 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8989 11:13:25.832863 == TX Byte 0 ==
8990 11:13:25.835260 u2DelayCellOfst[0]=18 cells (5 PI)
8991 11:13:25.838811 u2DelayCellOfst[1]=11 cells (3 PI)
8992 11:13:25.842104 u2DelayCellOfst[2]=0 cells (0 PI)
8993 11:13:25.845109 u2DelayCellOfst[3]=3 cells (1 PI)
8994 11:13:25.848610 u2DelayCellOfst[4]=7 cells (2 PI)
8995 11:13:25.852145 u2DelayCellOfst[5]=18 cells (5 PI)
8996 11:13:25.855666 u2DelayCellOfst[6]=18 cells (5 PI)
8997 11:13:25.858358 u2DelayCellOfst[7]=3 cells (1 PI)
8998 11:13:25.861694 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8999 11:13:25.865072 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9000 11:13:25.868410 == TX Byte 1 ==
9001 11:13:25.871644 u2DelayCellOfst[8]=0 cells (0 PI)
9002 11:13:25.874980 u2DelayCellOfst[9]=3 cells (1 PI)
9003 11:13:25.878702 u2DelayCellOfst[10]=14 cells (4 PI)
9004 11:13:25.881949 u2DelayCellOfst[11]=3 cells (1 PI)
9005 11:13:25.884930 u2DelayCellOfst[12]=14 cells (4 PI)
9006 11:13:25.885362 u2DelayCellOfst[13]=18 cells (5 PI)
9007 11:13:25.888377 u2DelayCellOfst[14]=18 cells (5 PI)
9008 11:13:25.891490 u2DelayCellOfst[15]=18 cells (5 PI)
9009 11:13:25.898378 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9010 11:13:25.901321 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9011 11:13:25.904877 DramC Write-DBI on
9012 11:13:25.905307 ==
9013 11:13:25.907720 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 11:13:25.911423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 11:13:25.911855 ==
9016 11:13:25.912191
9017 11:13:25.912504
9018 11:13:25.914479 TX Vref Scan disable
9019 11:13:25.914920 == TX Byte 0 ==
9020 11:13:25.921002 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9021 11:13:25.921432 == TX Byte 1 ==
9022 11:13:25.924602 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9023 11:13:25.927691 DramC Write-DBI off
9024 11:13:25.928142
9025 11:13:25.928487 [DATLAT]
9026 11:13:25.931354 Freq=1600, CH1 RK1
9027 11:13:25.931780
9028 11:13:25.932118 DATLAT Default: 0xf
9029 11:13:25.934228 0, 0xFFFF, sum = 0
9030 11:13:25.934595 1, 0xFFFF, sum = 0
9031 11:13:25.937875 2, 0xFFFF, sum = 0
9032 11:13:25.938338 3, 0xFFFF, sum = 0
9033 11:13:25.940919 4, 0xFFFF, sum = 0
9034 11:13:25.944449 5, 0xFFFF, sum = 0
9035 11:13:25.944916 6, 0xFFFF, sum = 0
9036 11:13:25.947734 7, 0xFFFF, sum = 0
9037 11:13:25.948165 8, 0xFFFF, sum = 0
9038 11:13:25.951011 9, 0xFFFF, sum = 0
9039 11:13:25.951685 10, 0xFFFF, sum = 0
9040 11:13:25.954469 11, 0xFFFF, sum = 0
9041 11:13:25.955058 12, 0xFFFF, sum = 0
9042 11:13:25.957341 13, 0xFFFF, sum = 0
9043 11:13:25.957778 14, 0x0, sum = 1
9044 11:13:25.960945 15, 0x0, sum = 2
9045 11:13:25.961599 16, 0x0, sum = 3
9046 11:13:25.964351 17, 0x0, sum = 4
9047 11:13:25.964848 best_step = 15
9048 11:13:25.965187
9049 11:13:25.965623 ==
9050 11:13:25.967858 Dram Type= 6, Freq= 0, CH_1, rank 1
9051 11:13:25.970767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9052 11:13:25.973819 ==
9053 11:13:25.974262 RX Vref Scan: 0
9054 11:13:25.974650
9055 11:13:25.977271 RX Vref 0 -> 0, step: 1
9056 11:13:25.977698
9057 11:13:25.980653 RX Delay 11 -> 252, step: 4
9058 11:13:25.984172 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9059 11:13:25.987165 iDelay=203, Bit 1, Center 126 (75 ~ 178) 104
9060 11:13:25.990666 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9061 11:13:25.997307 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9062 11:13:26.000382 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9063 11:13:26.003732 iDelay=203, Bit 5, Center 142 (91 ~ 194) 104
9064 11:13:26.006655 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9065 11:13:26.010378 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9066 11:13:26.016445 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9067 11:13:26.020074 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9068 11:13:26.023185 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9069 11:13:26.026278 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9070 11:13:26.029918 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9071 11:13:26.036574 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9072 11:13:26.039582 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9073 11:13:26.043095 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9074 11:13:26.043198 ==
9075 11:13:26.046160 Dram Type= 6, Freq= 0, CH_1, rank 1
9076 11:13:26.052684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9077 11:13:26.052766 ==
9078 11:13:26.052880 DQS Delay:
9079 11:13:26.052942 DQS0 = 0, DQS1 = 0
9080 11:13:26.056227 DQM Delay:
9081 11:13:26.056345 DQM0 = 133, DQM1 = 126
9082 11:13:26.059319 DQ Delay:
9083 11:13:26.062855 DQ0 =138, DQ1 =126, DQ2 =122, DQ3 =130
9084 11:13:26.065777 DQ4 =132, DQ5 =142, DQ6 =146, DQ7 =130
9085 11:13:26.069322 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9086 11:13:26.072145 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9087 11:13:26.072246
9088 11:13:26.072340
9089 11:13:26.072432
9090 11:13:26.075872 [DramC_TX_OE_Calibration] TA2
9091 11:13:26.079442 Original DQ_B0 (3 6) =30, OEN = 27
9092 11:13:26.082630 Original DQ_B1 (3 6) =30, OEN = 27
9093 11:13:26.085660 24, 0x0, End_B0=24 End_B1=24
9094 11:13:26.085743 25, 0x0, End_B0=25 End_B1=25
9095 11:13:26.089218 26, 0x0, End_B0=26 End_B1=26
9096 11:13:26.092489 27, 0x0, End_B0=27 End_B1=27
9097 11:13:26.095980 28, 0x0, End_B0=28 End_B1=28
9098 11:13:26.099138 29, 0x0, End_B0=29 End_B1=29
9099 11:13:26.099219 30, 0x0, End_B0=30 End_B1=30
9100 11:13:26.102141 31, 0x4545, End_B0=30 End_B1=30
9101 11:13:26.105771 Byte0 end_step=30 best_step=27
9102 11:13:26.108774 Byte1 end_step=30 best_step=27
9103 11:13:26.111905 Byte0 TX OE(2T, 0.5T) = (3, 3)
9104 11:13:26.115505 Byte1 TX OE(2T, 0.5T) = (3, 3)
9105 11:13:26.115605
9106 11:13:26.115699
9107 11:13:26.122185 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9108 11:13:26.125218 CH1 RK1: MR19=303, MR18=F0B
9109 11:13:26.131699 CH1_RK1: MR19=0x303, MR18=0xF0B, DQSOSC=402, MR23=63, INC=22, DEC=15
9110 11:13:26.135369 [RxdqsGatingPostProcess] freq 1600
9111 11:13:26.138437 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9112 11:13:26.142071 best DQS0 dly(2T, 0.5T) = (1, 1)
9113 11:13:26.144965 best DQS1 dly(2T, 0.5T) = (1, 1)
9114 11:13:26.148566 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9115 11:13:26.151755 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9116 11:13:26.155413 best DQS0 dly(2T, 0.5T) = (1, 1)
9117 11:13:26.158370 best DQS1 dly(2T, 0.5T) = (1, 1)
9118 11:13:26.161913 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9119 11:13:26.164885 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9120 11:13:26.168426 Pre-setting of DQS Precalculation
9121 11:13:26.171487 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9122 11:13:26.178354 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9123 11:13:26.188031 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9124 11:13:26.188141
9125 11:13:26.188236
9126 11:13:26.191575 [Calibration Summary] 3200 Mbps
9127 11:13:26.191659 CH 0, Rank 0
9128 11:13:26.195100 SW Impedance : PASS
9129 11:13:26.195199 DUTY Scan : NO K
9130 11:13:26.198162 ZQ Calibration : PASS
9131 11:13:26.198259 Jitter Meter : NO K
9132 11:13:26.201269 CBT Training : PASS
9133 11:13:26.204493 Write leveling : PASS
9134 11:13:26.204616 RX DQS gating : PASS
9135 11:13:26.207936 RX DQ/DQS(RDDQC) : PASS
9136 11:13:26.211606 TX DQ/DQS : PASS
9137 11:13:26.211680 RX DATLAT : PASS
9138 11:13:26.214642 RX DQ/DQS(Engine): PASS
9139 11:13:26.217709 TX OE : PASS
9140 11:13:26.217791 All Pass.
9141 11:13:26.217853
9142 11:13:26.217912 CH 0, Rank 1
9143 11:13:26.221108 SW Impedance : PASS
9144 11:13:26.224312 DUTY Scan : NO K
9145 11:13:26.224423 ZQ Calibration : PASS
9146 11:13:26.227981 Jitter Meter : NO K
9147 11:13:26.231007 CBT Training : PASS
9148 11:13:26.231111 Write leveling : PASS
9149 11:13:26.234605 RX DQS gating : PASS
9150 11:13:26.237735 RX DQ/DQS(RDDQC) : PASS
9151 11:13:26.237819 TX DQ/DQS : PASS
9152 11:13:26.241280 RX DATLAT : PASS
9153 11:13:26.244889 RX DQ/DQS(Engine): PASS
9154 11:13:26.244972 TX OE : PASS
9155 11:13:26.245038 All Pass.
9156 11:13:26.247908
9157 11:13:26.247990 CH 1, Rank 0
9158 11:13:26.251656 SW Impedance : PASS
9159 11:13:26.251739 DUTY Scan : NO K
9160 11:13:26.254686 ZQ Calibration : PASS
9161 11:13:26.258764 Jitter Meter : NO K
9162 11:13:26.258930 CBT Training : PASS
9163 11:13:26.261032 Write leveling : PASS
9164 11:13:26.261172 RX DQS gating : PASS
9165 11:13:26.264483 RX DQ/DQS(RDDQC) : PASS
9166 11:13:26.267483 TX DQ/DQS : PASS
9167 11:13:26.267585 RX DATLAT : PASS
9168 11:13:26.271331 RX DQ/DQS(Engine): PASS
9169 11:13:26.274315 TX OE : PASS
9170 11:13:26.274425 All Pass.
9171 11:13:26.274525
9172 11:13:26.274621 CH 1, Rank 1
9173 11:13:26.277892 SW Impedance : PASS
9174 11:13:26.281349 DUTY Scan : NO K
9175 11:13:26.281446 ZQ Calibration : PASS
9176 11:13:26.284195 Jitter Meter : NO K
9177 11:13:26.287680 CBT Training : PASS
9178 11:13:26.287793 Write leveling : PASS
9179 11:13:26.290631 RX DQS gating : PASS
9180 11:13:26.293937 RX DQ/DQS(RDDQC) : PASS
9181 11:13:26.294061 TX DQ/DQS : PASS
9182 11:13:26.297390 RX DATLAT : PASS
9183 11:13:26.300754 RX DQ/DQS(Engine): PASS
9184 11:13:26.300893 TX OE : PASS
9185 11:13:26.303834 All Pass.
9186 11:13:26.303988
9187 11:13:26.304110 DramC Write-DBI on
9188 11:13:26.307426 PER_BANK_REFRESH: Hybrid Mode
9189 11:13:26.307624 TX_TRACKING: ON
9190 11:13:26.317134 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9191 11:13:26.326926 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9192 11:13:26.333626 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9193 11:13:26.337444 [FAST_K] Save calibration result to emmc
9194 11:13:26.340246 sync common calibartion params.
9195 11:13:26.340739 sync cbt_mode0:1, 1:1
9196 11:13:26.343919 dram_init: ddr_geometry: 2
9197 11:13:26.346930 dram_init: ddr_geometry: 2
9198 11:13:26.350657 dram_init: ddr_geometry: 2
9199 11:13:26.351313 0:dram_rank_size:100000000
9200 11:13:26.353657 1:dram_rank_size:100000000
9201 11:13:26.360199 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9202 11:13:26.360856 DFS_SHUFFLE_HW_MODE: ON
9203 11:13:26.363816 dramc_set_vcore_voltage set vcore to 725000
9204 11:13:26.366767 Read voltage for 1600, 0
9205 11:13:26.367351 Vio18 = 0
9206 11:13:26.370269 Vcore = 725000
9207 11:13:26.370699 Vdram = 0
9208 11:13:26.371201 Vddq = 0
9209 11:13:26.373672 Vmddr = 0
9210 11:13:26.374241 switch to 3200 Mbps bootup
9211 11:13:26.376765 [DramcRunTimeConfig]
9212 11:13:26.377236 PHYPLL
9213 11:13:26.380092 DPM_CONTROL_AFTERK: ON
9214 11:13:26.380724 PER_BANK_REFRESH: ON
9215 11:13:26.383372 REFRESH_OVERHEAD_REDUCTION: ON
9216 11:13:26.386924 CMD_PICG_NEW_MODE: OFF
9217 11:13:26.387482 XRTWTW_NEW_MODE: ON
9218 11:13:26.389907 XRTRTR_NEW_MODE: ON
9219 11:13:26.390335 TX_TRACKING: ON
9220 11:13:26.393405 RDSEL_TRACKING: OFF
9221 11:13:26.396300 DQS Precalculation for DVFS: ON
9222 11:13:26.396828 RX_TRACKING: OFF
9223 11:13:26.399857 HW_GATING DBG: ON
9224 11:13:26.400283 ZQCS_ENABLE_LP4: ON
9225 11:13:26.403256 RX_PICG_NEW_MODE: ON
9226 11:13:26.403682 TX_PICG_NEW_MODE: ON
9227 11:13:26.406295 ENABLE_RX_DCM_DPHY: ON
9228 11:13:26.410003 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9229 11:13:26.412950 DUMMY_READ_FOR_TRACKING: OFF
9230 11:13:26.416736 !!! SPM_CONTROL_AFTERK: OFF
9231 11:13:26.417200 !!! SPM could not control APHY
9232 11:13:26.419780 IMPEDANCE_TRACKING: ON
9233 11:13:26.420285 TEMP_SENSOR: ON
9234 11:13:26.422873 HW_SAVE_FOR_SR: OFF
9235 11:13:26.426600 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9236 11:13:26.429904 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9237 11:13:26.433059 Read ODT Tracking: ON
9238 11:13:26.433507 Refresh Rate DeBounce: ON
9239 11:13:26.436021 DFS_NO_QUEUE_FLUSH: ON
9240 11:13:26.439705 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9241 11:13:26.443236 ENABLE_DFS_RUNTIME_MRW: OFF
9242 11:13:26.443687 DDR_RESERVE_NEW_MODE: ON
9243 11:13:26.446430 MR_CBT_SWITCH_FREQ: ON
9244 11:13:26.449380 =========================
9245 11:13:26.467605 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9246 11:13:26.470310 dram_init: ddr_geometry: 2
9247 11:13:26.489349 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9248 11:13:26.492193 dram_init: dram init end (result: 0)
9249 11:13:26.498983 DRAM-K: Full calibration passed in 24621 msecs
9250 11:13:26.501840 MRC: failed to locate region type 0.
9251 11:13:26.502265 DRAM rank0 size:0x100000000,
9252 11:13:26.505388 DRAM rank1 size=0x100000000
9253 11:13:26.515502 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9254 11:13:26.522177 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9255 11:13:26.529049 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9256 11:13:26.535551 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9257 11:13:26.538938 DRAM rank0 size:0x100000000,
9258 11:13:26.541939 DRAM rank1 size=0x100000000
9259 11:13:26.542425 CBMEM:
9260 11:13:26.544853 IMD: root @ 0xfffff000 254 entries.
9261 11:13:26.548382 IMD: root @ 0xffffec00 62 entries.
9262 11:13:26.552046 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9263 11:13:26.558635 WARNING: RO_VPD is uninitialized or empty.
9264 11:13:26.561764 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9265 11:13:26.568975 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9266 11:13:26.581899 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9267 11:13:26.592958 BS: romstage times (exec / console): total (unknown) / 24119 ms
9268 11:13:26.593390
9269 11:13:26.593743
9270 11:13:26.602922 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9271 11:13:26.606150 ARM64: Exception handlers installed.
9272 11:13:26.609543 ARM64: Testing exception
9273 11:13:26.613037 ARM64: Done test exception
9274 11:13:26.613716 Enumerating buses...
9275 11:13:26.616258 Show all devs... Before device enumeration.
9276 11:13:26.619473 Root Device: enabled 1
9277 11:13:26.623182 CPU_CLUSTER: 0: enabled 1
9278 11:13:26.623603 CPU: 00: enabled 1
9279 11:13:26.626560 Compare with tree...
9280 11:13:26.626977 Root Device: enabled 1
9281 11:13:26.629167 CPU_CLUSTER: 0: enabled 1
9282 11:13:26.632858 CPU: 00: enabled 1
9283 11:13:26.633285 Root Device scanning...
9284 11:13:26.635970 scan_static_bus for Root Device
9285 11:13:26.639285 CPU_CLUSTER: 0 enabled
9286 11:13:26.642755 scan_static_bus for Root Device done
9287 11:13:26.646322 scan_bus: bus Root Device finished in 8 msecs
9288 11:13:26.646765 done
9289 11:13:26.652874 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9290 11:13:26.655946 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9291 11:13:26.662504 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9292 11:13:26.665634 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9293 11:13:26.669134 Allocating resources...
9294 11:13:26.672170 Reading resources...
9295 11:13:26.676026 Root Device read_resources bus 0 link: 0
9296 11:13:26.678869 DRAM rank0 size:0x100000000,
9297 11:13:26.679305 DRAM rank1 size=0x100000000
9298 11:13:26.682140 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9299 11:13:26.685804 CPU: 00 missing read_resources
9300 11:13:26.692416 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9301 11:13:26.695351 Root Device read_resources bus 0 link: 0 done
9302 11:13:26.695783 Done reading resources.
9303 11:13:26.702089 Show resources in subtree (Root Device)...After reading.
9304 11:13:26.705780 Root Device child on link 0 CPU_CLUSTER: 0
9305 11:13:26.708962 CPU_CLUSTER: 0 child on link 0 CPU: 00
9306 11:13:26.718385 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9307 11:13:26.718820 CPU: 00
9308 11:13:26.721797 Root Device assign_resources, bus 0 link: 0
9309 11:13:26.725424 CPU_CLUSTER: 0 missing set_resources
9310 11:13:26.732061 Root Device assign_resources, bus 0 link: 0 done
9311 11:13:26.732590 Done setting resources.
9312 11:13:26.738258 Show resources in subtree (Root Device)...After assigning values.
9313 11:13:26.741722 Root Device child on link 0 CPU_CLUSTER: 0
9314 11:13:26.744786 CPU_CLUSTER: 0 child on link 0 CPU: 00
9315 11:13:26.754903 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9316 11:13:26.755338 CPU: 00
9317 11:13:26.758538 Done allocating resources.
9318 11:13:26.765284 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9319 11:13:26.765721 Enabling resources...
9320 11:13:26.766063 done.
9321 11:13:26.771461 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9322 11:13:26.774384 Initializing devices...
9323 11:13:26.774813 Root Device init
9324 11:13:26.778190 init hardware done!
9325 11:13:26.778620 0x00000018: ctrlr->caps
9326 11:13:26.781243 52.000 MHz: ctrlr->f_max
9327 11:13:26.785056 0.400 MHz: ctrlr->f_min
9328 11:13:26.785627 0x40ff8080: ctrlr->voltages
9329 11:13:26.787801 sclk: 390625
9330 11:13:26.788229 Bus Width = 1
9331 11:13:26.788609 sclk: 390625
9332 11:13:26.791345 Bus Width = 1
9333 11:13:26.794780 Early init status = 3
9334 11:13:26.797690 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9335 11:13:26.801341 in-header: 03 fc 00 00 01 00 00 00
9336 11:13:26.804623 in-data: 00
9337 11:13:26.807702 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9338 11:13:26.813386 in-header: 03 fd 00 00 00 00 00 00
9339 11:13:26.816283 in-data:
9340 11:13:26.819783 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9341 11:13:26.823812 in-header: 03 fc 00 00 01 00 00 00
9342 11:13:26.826967 in-data: 00
9343 11:13:26.830026 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9344 11:13:26.835106 in-header: 03 fd 00 00 00 00 00 00
9345 11:13:26.838123 in-data:
9346 11:13:26.841747 [SSUSB] Setting up USB HOST controller...
9347 11:13:26.844861 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9348 11:13:26.848634 [SSUSB] phy power-on done.
9349 11:13:26.851402 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9350 11:13:26.858005 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9351 11:13:26.861722 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9352 11:13:26.868320 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9353 11:13:26.874564 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9354 11:13:26.881361 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9355 11:13:26.888151 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9356 11:13:26.894970 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9357 11:13:26.897678 SPM: binary array size = 0x9dc
9358 11:13:26.901473 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9359 11:13:26.907681 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9360 11:13:26.914344 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9361 11:13:26.921265 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9362 11:13:26.924062 configure_display: Starting display init
9363 11:13:26.958611 anx7625_power_on_init: Init interface.
9364 11:13:26.962256 anx7625_disable_pd_protocol: Disabled PD feature.
9365 11:13:26.965360 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9366 11:13:26.992862 anx7625_start_dp_work: Secure OCM version=00
9367 11:13:26.996233 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9368 11:13:27.011562 sp_tx_get_edid_block: EDID Block = 1
9369 11:13:27.113853 Extracted contents:
9370 11:13:27.117217 header: 00 ff ff ff ff ff ff 00
9371 11:13:27.120462 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9372 11:13:27.123465 version: 01 04
9373 11:13:27.126706 basic params: 95 1f 11 78 0a
9374 11:13:27.130266 chroma info: 76 90 94 55 54 90 27 21 50 54
9375 11:13:27.133688 established: 00 00 00
9376 11:13:27.139967 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9377 11:13:27.143010 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9378 11:13:27.149717 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9379 11:13:27.156585 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9380 11:13:27.163207 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9381 11:13:27.166634 extensions: 00
9382 11:13:27.167056 checksum: fb
9383 11:13:27.167390
9384 11:13:27.170207 Manufacturer: IVO Model 57d Serial Number 0
9385 11:13:27.172989 Made week 0 of 2020
9386 11:13:27.176165 EDID version: 1.4
9387 11:13:27.176615 Digital display
9388 11:13:27.179699 6 bits per primary color channel
9389 11:13:27.180132 DisplayPort interface
9390 11:13:27.182873 Maximum image size: 31 cm x 17 cm
9391 11:13:27.186452 Gamma: 220%
9392 11:13:27.186878 Check DPMS levels
9393 11:13:27.190220 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9394 11:13:27.196087 First detailed timing is preferred timing
9395 11:13:27.196545 Established timings supported:
9396 11:13:27.199835 Standard timings supported:
9397 11:13:27.202900 Detailed timings
9398 11:13:27.206083 Hex of detail: 383680a07038204018303c0035ae10000019
9399 11:13:27.212689 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9400 11:13:27.216087 0780 0798 07c8 0820 hborder 0
9401 11:13:27.219040 0438 043b 0447 0458 vborder 0
9402 11:13:27.222621 -hsync -vsync
9403 11:13:27.223093 Did detailed timing
9404 11:13:27.229206 Hex of detail: 000000000000000000000000000000000000
9405 11:13:27.232568 Manufacturer-specified data, tag 0
9406 11:13:27.235931 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9407 11:13:27.239388 ASCII string: InfoVision
9408 11:13:27.242486 Hex of detail: 000000fe00523134304e574635205248200a
9409 11:13:27.245945 ASCII string: R140NWF5 RH
9410 11:13:27.246369 Checksum
9411 11:13:27.249185 Checksum: 0xfb (valid)
9412 11:13:27.252696 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9413 11:13:27.255897 DSI data_rate: 832800000 bps
9414 11:13:27.262068 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9415 11:13:27.265394 anx7625_parse_edid: pixelclock(138800).
9416 11:13:27.268691 hactive(1920), hsync(48), hfp(24), hbp(88)
9417 11:13:27.272085 vactive(1080), vsync(12), vfp(3), vbp(17)
9418 11:13:27.275375 anx7625_dsi_config: config dsi.
9419 11:13:27.282008 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9420 11:13:27.294981 anx7625_dsi_config: success to config DSI
9421 11:13:27.298617 anx7625_dp_start: MIPI phy setup OK.
9422 11:13:27.302355 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9423 11:13:27.305289 mtk_ddp_mode_set invalid vrefresh 60
9424 11:13:27.308964 main_disp_path_setup
9425 11:13:27.309047 ovl_layer_smi_id_en
9426 11:13:27.311803 ovl_layer_smi_id_en
9427 11:13:27.311886 ccorr_config
9428 11:13:27.311950 aal_config
9429 11:13:27.315475 gamma_config
9430 11:13:27.315557 postmask_config
9431 11:13:27.318024 dither_config
9432 11:13:27.321597 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9433 11:13:27.328184 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9434 11:13:27.331674 Root Device init finished in 553 msecs
9435 11:13:27.335084 CPU_CLUSTER: 0 init
9436 11:13:27.341677 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9437 11:13:27.348089 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9438 11:13:27.348187 APU_MBOX 0x190000b0 = 0x10001
9439 11:13:27.351244 APU_MBOX 0x190001b0 = 0x10001
9440 11:13:27.354917 APU_MBOX 0x190005b0 = 0x10001
9441 11:13:27.357928 APU_MBOX 0x190006b0 = 0x10001
9442 11:13:27.364419 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9443 11:13:27.374235 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9444 11:13:27.386685 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9445 11:13:27.393311 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9446 11:13:27.404921 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9447 11:13:27.414016 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9448 11:13:27.417353 CPU_CLUSTER: 0 init finished in 81 msecs
9449 11:13:27.421024 Devices initialized
9450 11:13:27.423855 Show all devs... After init.
9451 11:13:27.423958 Root Device: enabled 1
9452 11:13:27.427512 CPU_CLUSTER: 0: enabled 1
9453 11:13:27.430634 CPU: 00: enabled 1
9454 11:13:27.433668 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9455 11:13:27.437172 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9456 11:13:27.440621 ELOG: NV offset 0x57f000 size 0x1000
9457 11:13:27.447042 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9458 11:13:27.453551 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9459 11:13:27.457178 ELOG: Event(17) added with size 13 at 2023-06-05 11:13:27 UTC
9460 11:13:27.463786 out: cmd=0x121: 03 db 21 01 00 00 00 00
9461 11:13:27.466895 in-header: 03 c4 00 00 2c 00 00 00
9462 11:13:27.477015 in-data: 9b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9463 11:13:27.483405 ELOG: Event(A1) added with size 10 at 2023-06-05 11:13:27 UTC
9464 11:13:27.489931 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9465 11:13:27.496531 ELOG: Event(A0) added with size 9 at 2023-06-05 11:13:27 UTC
9466 11:13:27.500364 elog_add_boot_reason: Logged dev mode boot
9467 11:13:27.506447 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9468 11:13:27.506531 Finalize devices...
9469 11:13:27.510136 Devices finalized
9470 11:13:27.513306 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9471 11:13:27.516219 Writing coreboot table at 0xffe64000
9472 11:13:27.519910 0. 000000000010a000-0000000000113fff: RAMSTAGE
9473 11:13:27.526909 1. 0000000040000000-00000000400fffff: RAM
9474 11:13:27.529687 2. 0000000040100000-000000004032afff: RAMSTAGE
9475 11:13:27.533379 3. 000000004032b000-00000000545fffff: RAM
9476 11:13:27.536360 4. 0000000054600000-000000005465ffff: BL31
9477 11:13:27.539902 5. 0000000054660000-00000000ffe63fff: RAM
9478 11:13:27.545855 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9479 11:13:27.549414 7. 0000000100000000-000000023fffffff: RAM
9480 11:13:27.552896 Passing 5 GPIOs to payload:
9481 11:13:27.555887 NAME | PORT | POLARITY | VALUE
9482 11:13:27.562567 EC in RW | 0x000000aa | low | undefined
9483 11:13:27.566251 EC interrupt | 0x00000005 | low | undefined
9484 11:13:27.569325 TPM interrupt | 0x000000ab | high | undefined
9485 11:13:27.576164 SD card detect | 0x00000011 | high | undefined
9486 11:13:27.579068 speaker enable | 0x00000093 | high | undefined
9487 11:13:27.582859 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9488 11:13:27.585915 in-header: 03 f9 00 00 02 00 00 00
9489 11:13:27.588901 in-data: 02 00
9490 11:13:27.592539 ADC[4]: Raw value=903400 ID=7
9491 11:13:27.592695 ADC[3]: Raw value=213652 ID=1
9492 11:13:27.595486 RAM Code: 0x71
9493 11:13:27.599344 ADC[6]: Raw value=75406 ID=0
9494 11:13:27.602478 ADC[5]: Raw value=213652 ID=1
9495 11:13:27.602772 SKU Code: 0x1
9496 11:13:27.609040 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9497 11:13:27.609399 coreboot table: 964 bytes.
9498 11:13:27.612323 IMD ROOT 0. 0xfffff000 0x00001000
9499 11:13:27.615281 IMD SMALL 1. 0xffffe000 0x00001000
9500 11:13:27.619115 RO MCACHE 2. 0xffffc000 0x00001104
9501 11:13:27.622132 CONSOLE 3. 0xfff7c000 0x00080000
9502 11:13:27.625464 FMAP 4. 0xfff7b000 0x00000452
9503 11:13:27.629164 TIME STAMP 5. 0xfff7a000 0x00000910
9504 11:13:27.632246 VBOOT WORK 6. 0xfff66000 0x00014000
9505 11:13:27.635454 RAMOOPS 7. 0xffe66000 0x00100000
9506 11:13:27.639180 COREBOOT 8. 0xffe64000 0x00002000
9507 11:13:27.642327 IMD small region:
9508 11:13:27.645192 IMD ROOT 0. 0xffffec00 0x00000400
9509 11:13:27.648684 VPD 1. 0xffffeba0 0x0000004c
9510 11:13:27.652242 MMC STATUS 2. 0xffffeb80 0x00000004
9511 11:13:27.658636 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9512 11:13:27.659063 Probing TPM: done!
9513 11:13:27.662088 Connected to device vid:did:rid of 1ae0:0028:00
9514 11:13:27.673398 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9515 11:13:27.676590 Initialized TPM device CR50 revision 0
9516 11:13:27.680426 Checking cr50 for pending updates
9517 11:13:27.684030 Reading cr50 TPM mode
9518 11:13:27.693100 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9519 11:13:27.699212 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9520 11:13:27.739394 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9521 11:13:27.742692 Checking segment from ROM address 0x40100000
9522 11:13:27.749272 Checking segment from ROM address 0x4010001c
9523 11:13:27.752623 Loading segment from ROM address 0x40100000
9524 11:13:27.753048 code (compression=0)
9525 11:13:27.762508 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9526 11:13:27.768967 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9527 11:13:27.769451 it's not compressed!
9528 11:13:27.776067 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9529 11:13:27.782147 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9530 11:13:27.799597 Loading segment from ROM address 0x4010001c
9531 11:13:27.800030 Entry Point 0x80000000
9532 11:13:27.803401 Loaded segments
9533 11:13:27.806598 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9534 11:13:27.813199 Jumping to boot code at 0x80000000(0xffe64000)
9535 11:13:27.820098 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9536 11:13:27.826353 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9537 11:13:27.834476 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9538 11:13:27.838065 Checking segment from ROM address 0x40100000
9539 11:13:27.841156 Checking segment from ROM address 0x4010001c
9540 11:13:27.847292 Loading segment from ROM address 0x40100000
9541 11:13:27.847769 code (compression=1)
9542 11:13:27.854445 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9543 11:13:27.863884 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9544 11:13:27.864318 using LZMA
9545 11:13:27.872781 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9546 11:13:27.878825 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9547 11:13:27.882439 Loading segment from ROM address 0x4010001c
9548 11:13:27.883035 Entry Point 0x54601000
9549 11:13:27.886119 Loaded segments
9550 11:13:27.889085 NOTICE: MT8192 bl31_setup
9551 11:13:27.896421 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9552 11:13:27.899785 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9553 11:13:27.902906 WARNING: region 0:
9554 11:13:27.906395 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9555 11:13:27.906827 WARNING: region 1:
9556 11:13:27.912477 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9557 11:13:27.916322 WARNING: region 2:
9558 11:13:27.919293 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9559 11:13:27.922799 WARNING: region 3:
9560 11:13:27.926422 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9561 11:13:27.929421 WARNING: region 4:
9562 11:13:27.935952 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9563 11:13:27.936386 WARNING: region 5:
9564 11:13:27.939076 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9565 11:13:27.942451 WARNING: region 6:
9566 11:13:27.945877 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9567 11:13:27.949294 WARNING: region 7:
9568 11:13:27.952846 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9569 11:13:27.959180 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9570 11:13:27.962764 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9571 11:13:27.965817 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9572 11:13:27.972586 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9573 11:13:27.975364 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9574 11:13:27.982206 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9575 11:13:27.986044 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9576 11:13:27.989082 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9577 11:13:27.995645 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9578 11:13:27.999378 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9579 11:13:28.002234 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9580 11:13:28.008777 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9581 11:13:28.012304 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9582 11:13:28.016080 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9583 11:13:28.022620 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9584 11:13:28.025546 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9585 11:13:28.032209 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9586 11:13:28.035723 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9587 11:13:28.038776 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9588 11:13:28.045346 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9589 11:13:28.048864 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9590 11:13:28.055326 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9591 11:13:28.058901 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9592 11:13:28.062288 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9593 11:13:28.069098 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9594 11:13:28.071974 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9595 11:13:28.078794 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9596 11:13:28.081934 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9597 11:13:28.085331 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9598 11:13:28.091966 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9599 11:13:28.095660 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9600 11:13:28.101650 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9601 11:13:28.105198 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9602 11:13:28.108321 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9603 11:13:28.111863 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9604 11:13:28.118501 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9605 11:13:28.121558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9606 11:13:28.125227 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9607 11:13:28.128783 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9608 11:13:28.134853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9609 11:13:28.138394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9610 11:13:28.141682 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9611 11:13:28.144800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9612 11:13:28.152001 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9613 11:13:28.154744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9614 11:13:28.158623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9615 11:13:28.161849 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9616 11:13:28.168492 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9617 11:13:28.171227 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9618 11:13:28.177748 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9619 11:13:28.181331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9620 11:13:28.184436 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9621 11:13:28.191344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9622 11:13:28.194492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9623 11:13:28.201149 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9624 11:13:28.204139 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9625 11:13:28.210816 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9626 11:13:28.214289 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9627 11:13:28.220808 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9628 11:13:28.224630 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9629 11:13:28.227592 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9630 11:13:28.234229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9631 11:13:28.237776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9632 11:13:28.244469 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9633 11:13:28.247439 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9634 11:13:28.254019 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9635 11:13:28.257750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9636 11:13:28.260804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9637 11:13:28.267871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9638 11:13:28.270624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9639 11:13:28.277637 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9640 11:13:28.281155 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9641 11:13:28.287641 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9642 11:13:28.291171 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9643 11:13:28.294001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9644 11:13:28.300652 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9645 11:13:28.304176 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9646 11:13:28.310786 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9647 11:13:28.314073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9648 11:13:28.320644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9649 11:13:28.324181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9650 11:13:28.330795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9651 11:13:28.333842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9652 11:13:28.340480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9653 11:13:28.343625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9654 11:13:28.347281 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9655 11:13:28.353991 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9656 11:13:28.357016 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9657 11:13:28.363704 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9658 11:13:28.367137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9659 11:13:28.373618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9660 11:13:28.376930 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9661 11:13:28.380368 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9662 11:13:28.386701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9663 11:13:28.390187 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9664 11:13:28.397137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9665 11:13:28.400055 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9666 11:13:28.403579 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9667 11:13:28.410470 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9668 11:13:28.413486 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9669 11:13:28.417059 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9670 11:13:28.420259 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9671 11:13:28.426848 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9672 11:13:28.429871 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9673 11:13:28.436595 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9674 11:13:28.439960 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9675 11:13:28.443720 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9676 11:13:28.449922 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9677 11:13:28.453558 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9678 11:13:28.460141 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9679 11:13:28.463172 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9680 11:13:28.466761 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9681 11:13:28.473587 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9682 11:13:28.476497 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9683 11:13:28.483141 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9684 11:13:28.486389 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9685 11:13:28.490132 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9686 11:13:28.496370 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9687 11:13:28.499985 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9688 11:13:28.502837 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9689 11:13:28.506661 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9690 11:13:28.513063 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9691 11:13:28.516673 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9692 11:13:28.519580 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9693 11:13:28.526186 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9694 11:13:28.529827 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9695 11:13:28.532801 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9696 11:13:28.539392 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9697 11:13:28.543047 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9698 11:13:28.549682 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9699 11:13:28.552838 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9700 11:13:28.556409 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9701 11:13:28.563210 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9702 11:13:28.566320 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9703 11:13:28.572969 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9704 11:13:28.576661 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9705 11:13:28.579626 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9706 11:13:28.586183 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9707 11:13:28.589570 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9708 11:13:28.592414 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9709 11:13:28.599481 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9710 11:13:28.602639 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9711 11:13:28.609542 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9712 11:13:28.612304 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9713 11:13:28.616223 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9714 11:13:28.622272 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9715 11:13:28.625925 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9716 11:13:28.632193 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9717 11:13:28.635536 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9718 11:13:28.638972 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9719 11:13:28.645960 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9720 11:13:28.648870 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9721 11:13:28.655714 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9722 11:13:28.659267 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9723 11:13:28.662199 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9724 11:13:28.668614 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9725 11:13:28.672108 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9726 11:13:28.679042 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9727 11:13:28.682130 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9728 11:13:28.685065 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9729 11:13:28.691941 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9730 11:13:28.694866 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9731 11:13:28.701616 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9732 11:13:28.704888 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9733 11:13:28.708304 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9734 11:13:28.714940 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9735 11:13:28.717690 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9736 11:13:28.724705 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9737 11:13:28.727737 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9738 11:13:28.730911 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9739 11:13:28.737516 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9740 11:13:28.740414 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9741 11:13:28.747198 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9742 11:13:28.750823 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9743 11:13:28.753809 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9744 11:13:28.760434 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9745 11:13:28.764031 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9746 11:13:28.770591 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9747 11:13:28.774020 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9748 11:13:28.777042 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9749 11:13:28.783768 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9750 11:13:28.786790 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9751 11:13:28.793428 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9752 11:13:28.796458 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9753 11:13:28.803022 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9754 11:13:28.806611 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9755 11:13:28.809553 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9756 11:13:28.816379 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9757 11:13:28.820094 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9758 11:13:28.826487 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9759 11:13:28.829354 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9760 11:13:28.835879 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9761 11:13:28.839571 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9762 11:13:28.842420 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9763 11:13:28.849342 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9764 11:13:28.852683 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9765 11:13:28.859635 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9766 11:13:28.862636 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9767 11:13:28.865708 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9768 11:13:28.872343 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9769 11:13:28.875421 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9770 11:13:28.882134 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9771 11:13:28.885224 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9772 11:13:28.892186 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9773 11:13:28.895229 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9774 11:13:28.898754 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9775 11:13:28.905248 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9776 11:13:28.908805 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9777 11:13:28.915334 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9778 11:13:28.918919 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9779 11:13:28.925317 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9780 11:13:28.928216 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9781 11:13:28.931572 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9782 11:13:28.938384 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9783 11:13:28.941405 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9784 11:13:28.947917 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9785 11:13:28.951496 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9786 11:13:28.957900 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9787 11:13:28.961780 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9788 11:13:28.964959 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9789 11:13:28.971557 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9790 11:13:28.975074 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9791 11:13:28.981086 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9792 11:13:28.984825 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9793 11:13:28.991273 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9794 11:13:28.995055 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9795 11:13:28.997928 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9796 11:13:29.004456 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9797 11:13:29.008220 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9798 11:13:29.014283 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9799 11:13:29.017554 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9800 11:13:29.021102 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9801 11:13:29.024036 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9802 11:13:29.027385 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9803 11:13:29.034151 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9804 11:13:29.037592 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9805 11:13:29.043733 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9806 11:13:29.047172 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9807 11:13:29.050473 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9808 11:13:29.056942 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9809 11:13:29.060471 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9810 11:13:29.067134 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9811 11:13:29.070059 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9812 11:13:29.073995 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9813 11:13:29.080010 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9814 11:13:29.083741 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9815 11:13:29.086734 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9816 11:13:29.093454 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9817 11:13:29.096378 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9818 11:13:29.099997 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9819 11:13:29.106759 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9820 11:13:29.109741 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9821 11:13:29.116116 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9822 11:13:29.119613 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9823 11:13:29.123165 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9824 11:13:29.129597 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9825 11:13:29.133274 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9826 11:13:29.139729 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9827 11:13:29.142700 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9828 11:13:29.146032 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9829 11:13:29.152421 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9830 11:13:29.156088 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9831 11:13:29.159035 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9832 11:13:29.165783 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9833 11:13:29.168910 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9834 11:13:29.175585 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9835 11:13:29.179437 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9836 11:13:29.182541 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9837 11:13:29.189332 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9838 11:13:29.192313 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9839 11:13:29.195879 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9840 11:13:29.199026 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9841 11:13:29.202190 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9842 11:13:29.208742 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9843 11:13:29.212402 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9844 11:13:29.215458 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9845 11:13:29.218974 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9846 11:13:29.225478 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9847 11:13:29.228893 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9848 11:13:29.231782 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9849 11:13:29.238966 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9850 11:13:29.241925 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9851 11:13:29.245494 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9852 11:13:29.251833 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9853 11:13:29.255433 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9854 11:13:29.261859 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9855 11:13:29.264655 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9856 11:13:29.268149 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9857 11:13:29.275209 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9858 11:13:29.278242 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9859 11:13:29.285131 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9860 11:13:29.287964 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9861 11:13:29.291233 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9862 11:13:29.297954 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9863 11:13:29.301626 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9864 11:13:29.308270 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9865 11:13:29.311504 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9866 11:13:29.314672 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9867 11:13:29.321085 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9868 11:13:29.324331 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9869 11:13:29.330993 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9870 11:13:29.334068 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9871 11:13:29.340919 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9872 11:13:29.343965 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9873 11:13:29.351021 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9874 11:13:29.353793 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9875 11:13:29.357314 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9876 11:13:29.363811 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9877 11:13:29.367225 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9878 11:13:29.373929 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9879 11:13:29.377194 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9880 11:13:29.380831 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9881 11:13:29.387576 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9882 11:13:29.390349 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9883 11:13:29.397351 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9884 11:13:29.400302 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9885 11:13:29.403843 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9886 11:13:29.410089 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9887 11:13:29.413699 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9888 11:13:29.420306 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9889 11:13:29.423512 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9890 11:13:29.426957 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9891 11:13:29.433531 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9892 11:13:29.436497 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9893 11:13:29.443370 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9894 11:13:29.446373 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9895 11:13:29.453518 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9896 11:13:29.456996 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9897 11:13:29.460056 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9898 11:13:29.466456 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9899 11:13:29.469944 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9900 11:13:29.476392 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9901 11:13:29.479915 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9902 11:13:29.482869 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9903 11:13:29.489954 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9904 11:13:29.492997 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9905 11:13:29.499701 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9906 11:13:29.502724 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9907 11:13:29.506401 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9908 11:13:29.513014 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9909 11:13:29.516041 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9910 11:13:29.523033 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9911 11:13:29.525880 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9912 11:13:29.532350 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9913 11:13:29.535828 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9914 11:13:29.539238 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9915 11:13:29.545864 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9916 11:13:29.548794 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9917 11:13:29.555813 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9918 11:13:29.558976 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9919 11:13:29.565189 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9920 11:13:29.568578 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9921 11:13:29.572084 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9922 11:13:29.579002 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9923 11:13:29.581959 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9924 11:13:29.588418 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9925 11:13:29.591944 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9926 11:13:29.598616 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9927 11:13:29.601671 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9928 11:13:29.608487 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9929 11:13:29.611517 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9930 11:13:29.615052 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9931 11:13:29.622014 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9932 11:13:29.625091 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9933 11:13:29.631873 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9934 11:13:29.634835 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9935 11:13:29.641084 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9936 11:13:29.644800 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9937 11:13:29.651607 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9938 11:13:29.654551 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9939 11:13:29.657911 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9940 11:13:29.664444 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9941 11:13:29.667927 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9942 11:13:29.674376 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9943 11:13:29.677436 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9944 11:13:29.684383 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9945 11:13:29.687316 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9946 11:13:29.690953 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9947 11:13:29.697643 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9948 11:13:29.700876 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9949 11:13:29.706945 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9950 11:13:29.710675 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9951 11:13:29.717353 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9952 11:13:29.720178 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9953 11:13:29.726956 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9954 11:13:29.730556 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9955 11:13:29.733257 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9956 11:13:29.740143 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9957 11:13:29.743016 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9958 11:13:29.749437 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9959 11:13:29.753001 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9960 11:13:29.759618 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9961 11:13:29.762996 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9962 11:13:29.769515 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9963 11:13:29.773387 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9964 11:13:29.776239 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9965 11:13:29.783362 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9966 11:13:29.786240 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9967 11:13:29.793484 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9968 11:13:29.796332 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9969 11:13:29.802847 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9970 11:13:29.806450 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9971 11:13:29.809398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9972 11:13:29.816266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9973 11:13:29.819842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9974 11:13:29.826031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9975 11:13:29.829544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9976 11:13:29.836268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9977 11:13:29.839053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9978 11:13:29.845790 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9979 11:13:29.849493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9980 11:13:29.855994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9981 11:13:29.859850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9982 11:13:29.865916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9983 11:13:29.869080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9984 11:13:29.875917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9985 11:13:29.878986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9986 11:13:29.886005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9987 11:13:29.888878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9988 11:13:29.895656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9989 11:13:29.898703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9990 11:13:29.905216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9991 11:13:29.908833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9992 11:13:29.915212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9993 11:13:29.918695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9994 11:13:29.925534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9995 11:13:29.928619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9996 11:13:29.935308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9997 11:13:29.938662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9998 11:13:29.945470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9999 11:13:29.948282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10000 11:13:29.954788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10001 11:13:29.958446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10002 11:13:29.964934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10003 11:13:29.968199 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10004 11:13:29.971168 INFO: [APUAPC] vio 0
10005 11:13:29.974794 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10006 11:13:29.981161 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10007 11:13:29.984027 INFO: [APUAPC] D0_APC_0: 0x400510
10008 11:13:29.984470 INFO: [APUAPC] D0_APC_1: 0x0
10009 11:13:29.988070 INFO: [APUAPC] D0_APC_2: 0x1540
10010 11:13:29.990856 INFO: [APUAPC] D0_APC_3: 0x0
10011 11:13:29.994322 INFO: [APUAPC] D1_APC_0: 0xffffffff
10012 11:13:29.997738 INFO: [APUAPC] D1_APC_1: 0xffffffff
10013 11:13:30.001156 INFO: [APUAPC] D1_APC_2: 0x3fffff
10014 11:13:30.004087 INFO: [APUAPC] D1_APC_3: 0x0
10015 11:13:30.007594 INFO: [APUAPC] D2_APC_0: 0xffffffff
10016 11:13:30.011058 INFO: [APUAPC] D2_APC_1: 0xffffffff
10017 11:13:30.014161 INFO: [APUAPC] D2_APC_2: 0x3fffff
10018 11:13:30.017224 INFO: [APUAPC] D2_APC_3: 0x0
10019 11:13:30.020352 INFO: [APUAPC] D3_APC_0: 0xffffffff
10020 11:13:30.023920 INFO: [APUAPC] D3_APC_1: 0xffffffff
10021 11:13:30.027017 INFO: [APUAPC] D3_APC_2: 0x3fffff
10022 11:13:30.030502 INFO: [APUAPC] D3_APC_3: 0x0
10023 11:13:30.033786 INFO: [APUAPC] D4_APC_0: 0xffffffff
10024 11:13:30.037456 INFO: [APUAPC] D4_APC_1: 0xffffffff
10025 11:13:30.040320 INFO: [APUAPC] D4_APC_2: 0x3fffff
10026 11:13:30.044183 INFO: [APUAPC] D4_APC_3: 0x0
10027 11:13:30.047219 INFO: [APUAPC] D5_APC_0: 0xffffffff
10028 11:13:30.050699 INFO: [APUAPC] D5_APC_1: 0xffffffff
10029 11:13:30.054257 INFO: [APUAPC] D5_APC_2: 0x3fffff
10030 11:13:30.056987 INFO: [APUAPC] D5_APC_3: 0x0
10031 11:13:30.060411 INFO: [APUAPC] D6_APC_0: 0xffffffff
10032 11:13:30.064074 INFO: [APUAPC] D6_APC_1: 0xffffffff
10033 11:13:30.067245 INFO: [APUAPC] D6_APC_2: 0x3fffff
10034 11:13:30.070000 INFO: [APUAPC] D6_APC_3: 0x0
10035 11:13:30.073509 INFO: [APUAPC] D7_APC_0: 0xffffffff
10036 11:13:30.077032 INFO: [APUAPC] D7_APC_1: 0xffffffff
10037 11:13:30.079960 INFO: [APUAPC] D7_APC_2: 0x3fffff
10038 11:13:30.083587 INFO: [APUAPC] D7_APC_3: 0x0
10039 11:13:30.086467 INFO: [APUAPC] D8_APC_0: 0xffffffff
10040 11:13:30.089935 INFO: [APUAPC] D8_APC_1: 0xffffffff
10041 11:13:30.093086 INFO: [APUAPC] D8_APC_2: 0x3fffff
10042 11:13:30.096645 INFO: [APUAPC] D8_APC_3: 0x0
10043 11:13:30.099657 INFO: [APUAPC] D9_APC_0: 0xffffffff
10044 11:13:30.103070 INFO: [APUAPC] D9_APC_1: 0xffffffff
10045 11:13:30.106467 INFO: [APUAPC] D9_APC_2: 0x3fffff
10046 11:13:30.109648 INFO: [APUAPC] D9_APC_3: 0x0
10047 11:13:30.113106 INFO: [APUAPC] D10_APC_0: 0xffffffff
10048 11:13:30.116724 INFO: [APUAPC] D10_APC_1: 0xffffffff
10049 11:13:30.119652 INFO: [APUAPC] D10_APC_2: 0x3fffff
10050 11:13:30.123181 INFO: [APUAPC] D10_APC_3: 0x0
10051 11:13:30.126086 INFO: [APUAPC] D11_APC_0: 0xffffffff
10052 11:13:30.129747 INFO: [APUAPC] D11_APC_1: 0xffffffff
10053 11:13:30.132611 INFO: [APUAPC] D11_APC_2: 0x3fffff
10054 11:13:30.136383 INFO: [APUAPC] D11_APC_3: 0x0
10055 11:13:30.139410 INFO: [APUAPC] D12_APC_0: 0xffffffff
10056 11:13:30.142912 INFO: [APUAPC] D12_APC_1: 0xffffffff
10057 11:13:30.145959 INFO: [APUAPC] D12_APC_2: 0x3fffff
10058 11:13:30.149658 INFO: [APUAPC] D12_APC_3: 0x0
10059 11:13:30.152483 INFO: [APUAPC] D13_APC_0: 0xffffffff
10060 11:13:30.156138 INFO: [APUAPC] D13_APC_1: 0xffffffff
10061 11:13:30.159139 INFO: [APUAPC] D13_APC_2: 0x3fffff
10062 11:13:30.162249 INFO: [APUAPC] D13_APC_3: 0x0
10063 11:13:30.165606 INFO: [APUAPC] D14_APC_0: 0xffffffff
10064 11:13:30.169363 INFO: [APUAPC] D14_APC_1: 0xffffffff
10065 11:13:30.172344 INFO: [APUAPC] D14_APC_2: 0x3fffff
10066 11:13:30.176063 INFO: [APUAPC] D14_APC_3: 0x0
10067 11:13:30.179051 INFO: [APUAPC] D15_APC_0: 0xffffffff
10068 11:13:30.182563 INFO: [APUAPC] D15_APC_1: 0xffffffff
10069 11:13:30.185667 INFO: [APUAPC] D15_APC_2: 0x3fffff
10070 11:13:30.189090 INFO: [APUAPC] D15_APC_3: 0x0
10071 11:13:30.191950 INFO: [APUAPC] APC_CON: 0x4
10072 11:13:30.195388 INFO: [NOCDAPC] D0_APC_0: 0x0
10073 11:13:30.198882 INFO: [NOCDAPC] D0_APC_1: 0x0
10074 11:13:30.202226 INFO: [NOCDAPC] D1_APC_0: 0x0
10075 11:13:30.202871 INFO: [NOCDAPC] D1_APC_1: 0xfff
10076 11:13:30.205272 INFO: [NOCDAPC] D2_APC_0: 0x0
10077 11:13:30.208641 INFO: [NOCDAPC] D2_APC_1: 0xfff
10078 11:13:30.212100 INFO: [NOCDAPC] D3_APC_0: 0x0
10079 11:13:30.215697 INFO: [NOCDAPC] D3_APC_1: 0xfff
10080 11:13:30.218535 INFO: [NOCDAPC] D4_APC_0: 0x0
10081 11:13:30.221615 INFO: [NOCDAPC] D4_APC_1: 0xfff
10082 11:13:30.224853 INFO: [NOCDAPC] D5_APC_0: 0x0
10083 11:13:30.228053 INFO: [NOCDAPC] D5_APC_1: 0xfff
10084 11:13:30.231739 INFO: [NOCDAPC] D6_APC_0: 0x0
10085 11:13:30.234866 INFO: [NOCDAPC] D6_APC_1: 0xfff
10086 11:13:30.234981 INFO: [NOCDAPC] D7_APC_0: 0x0
10087 11:13:30.238065 INFO: [NOCDAPC] D7_APC_1: 0xfff
10088 11:13:30.241069 INFO: [NOCDAPC] D8_APC_0: 0x0
10089 11:13:30.244623 INFO: [NOCDAPC] D8_APC_1: 0xfff
10090 11:13:30.247770 INFO: [NOCDAPC] D9_APC_0: 0x0
10091 11:13:30.251308 INFO: [NOCDAPC] D9_APC_1: 0xfff
10092 11:13:30.254366 INFO: [NOCDAPC] D10_APC_0: 0x0
10093 11:13:30.257995 INFO: [NOCDAPC] D10_APC_1: 0xfff
10094 11:13:30.261017 INFO: [NOCDAPC] D11_APC_0: 0x0
10095 11:13:30.264645 INFO: [NOCDAPC] D11_APC_1: 0xfff
10096 11:13:30.267591 INFO: [NOCDAPC] D12_APC_0: 0x0
10097 11:13:30.270905 INFO: [NOCDAPC] D12_APC_1: 0xfff
10098 11:13:30.274690 INFO: [NOCDAPC] D13_APC_0: 0x0
10099 11:13:30.277662 INFO: [NOCDAPC] D13_APC_1: 0xfff
10100 11:13:30.281179 INFO: [NOCDAPC] D14_APC_0: 0x0
10101 11:13:30.281255 INFO: [NOCDAPC] D14_APC_1: 0xfff
10102 11:13:30.284859 INFO: [NOCDAPC] D15_APC_0: 0x0
10103 11:13:30.287584 INFO: [NOCDAPC] D15_APC_1: 0xfff
10104 11:13:30.290786 INFO: [NOCDAPC] APC_CON: 0x4
10105 11:13:30.294259 INFO: [APUAPC] set_apusys_apc done
10106 11:13:30.297732 INFO: [DEVAPC] devapc_init done
10107 11:13:30.300908 INFO: GICv3 without legacy support detected.
10108 11:13:30.307801 INFO: ARM GICv3 driver initialized in EL3
10109 11:13:30.310869 INFO: Maximum SPI INTID supported: 639
10110 11:13:30.314372 INFO: BL31: Initializing runtime services
10111 11:13:30.321002 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10112 11:13:30.321087 INFO: SPM: enable CPC mode
10113 11:13:30.327549 INFO: mcdi ready for mcusys-off-idle and system suspend
10114 11:13:30.330482 INFO: BL31: Preparing for EL3 exit to normal world
10115 11:13:30.337390 INFO: Entry point address = 0x80000000
10116 11:13:30.337480 INFO: SPSR = 0x8
10117 11:13:30.343486
10118 11:13:30.343573
10119 11:13:30.343639
10120 11:13:30.347031 Starting depthcharge on Spherion...
10121 11:13:30.347116
10122 11:13:30.347182 Wipe memory regions:
10123 11:13:30.347242
10124 11:13:30.347885 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10125 11:13:30.347987 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10126 11:13:30.348075 Setting prompt string to ['asurada:']
10127 11:13:30.348369 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10128 11:13:30.350023 [0x00000040000000, 0x00000054600000)
10129 11:13:30.472867
10130 11:13:30.473021 [0x00000054660000, 0x00000080000000)
10131 11:13:30.733858
10132 11:13:30.734391 [0x000000821a7280, 0x000000ffe64000)
10133 11:13:31.478568
10134 11:13:31.478720 [0x00000100000000, 0x00000240000000)
10135 11:13:33.369283
10136 11:13:33.372214 Initializing XHCI USB controller at 0x11200000.
10137 11:13:34.353801
10138 11:13:34.354327 R8152: Initializing
10139 11:13:34.354668
10140 11:13:34.357302 Version 9 (ocp_data = 6010)
10141 11:13:34.357733
10142 11:13:34.360287 R8152: Done initializing
10143 11:13:34.360744
10144 11:13:34.361151 Adding net device
10145 11:13:34.882743
10146 11:13:34.885437 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10147 11:13:34.885957
10148 11:13:34.886306
10149 11:13:34.886708
10150 11:13:34.887493 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10152 11:13:34.988760 asurada: tftpboot 192.168.201.1 10591227/tftp-deploy-cv815yyk/kernel/image.itb 10591227/tftp-deploy-cv815yyk/kernel/cmdline
10153 11:13:34.988936 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10154 11:13:34.989018 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10155 11:13:34.993011 tftpboot 192.168.201.1 10591227/tftp-deploy-cv815yyk/kernel/image.ittp-deploy-cv815yyk/kernel/cmdline
10156 11:13:34.993097
10157 11:13:34.993164 Waiting for link
10158 11:13:35.195391
10159 11:13:35.195549 done.
10160 11:13:35.195622
10161 11:13:35.195684 MAC: f4:f5:e8:50:de:0a
10162 11:13:35.195743
10163 11:13:35.198966 Sending DHCP discover... done.
10164 11:13:35.199052
10165 11:13:35.202004 Waiting for reply... done.
10166 11:13:35.202088
10167 11:13:35.205507 Sending DHCP request... done.
10168 11:13:35.205592
10169 11:13:35.205658 Waiting for reply... done.
10170 11:13:35.205720
10171 11:13:35.208506 My ip is 192.168.201.14
10172 11:13:35.208634
10173 11:13:35.212258 The DHCP server ip is 192.168.201.1
10174 11:13:35.212343
10175 11:13:35.215114 TFTP server IP predefined by user: 192.168.201.1
10176 11:13:35.215216
10177 11:13:35.222182 Bootfile predefined by user: 10591227/tftp-deploy-cv815yyk/kernel/image.itb
10178 11:13:35.222267
10179 11:13:35.225201 Sending tftp read request... done.
10180 11:13:35.225285
10181 11:13:35.228169 Waiting for the transfer...
10182 11:13:35.228254
10183 11:13:35.449780 00000000 ################################################################
10184 11:13:35.449959
10185 11:13:35.673738 00080000 ################################################################
10186 11:13:35.673914
10187 11:13:35.900845 00100000 ################################################################
10188 11:13:35.901021
10189 11:13:36.130032 00180000 ################################################################
10190 11:13:36.130205
10191 11:13:36.354076 00200000 ################################################################
10192 11:13:36.354219
10193 11:13:36.582892 00280000 ################################################################
10194 11:13:36.583066
10195 11:13:36.805146 00300000 ################################################################
10196 11:13:36.805320
10197 11:13:37.030641 00380000 ################################################################
10198 11:13:37.030780
10199 11:13:37.255947 00400000 ################################################################
10200 11:13:37.256124
10201 11:13:37.482756 00480000 ################################################################
10202 11:13:37.482911
10203 11:13:37.710475 00500000 ################################################################
10204 11:13:37.710642
10205 11:13:37.933370 00580000 ################################################################
10206 11:13:37.933521
10207 11:13:38.169670 00600000 ################################################################
10208 11:13:38.169815
10209 11:13:38.393986 00680000 ################################################################
10210 11:13:38.394129
10211 11:13:38.620061 00700000 ################################################################
10212 11:13:38.620207
10213 11:13:38.843341 00780000 ################################################################
10214 11:13:38.843485
10215 11:13:39.070149 00800000 ################################################################
10216 11:13:39.070295
10217 11:13:39.291807 00880000 ################################################################
10218 11:13:39.291957
10219 11:13:39.519151 00900000 ################################################################
10220 11:13:39.519295
10221 11:13:39.743068 00980000 ################################################################
10222 11:13:39.743234
10223 11:13:39.966341 00a00000 ################################################################
10224 11:13:39.966512
10225 11:13:40.199093 00a80000 ################################################################
10226 11:13:40.199262
10227 11:13:40.425707 00b00000 ################################################################
10228 11:13:40.425876
10229 11:13:40.649742 00b80000 ################################################################
10230 11:13:40.649887
10231 11:13:40.880311 00c00000 ################################################################
10232 11:13:40.880486
10233 11:13:41.104064 00c80000 ################################################################
10234 11:13:41.104210
10235 11:13:41.327494 00d00000 ################################################################
10236 11:13:41.327644
10237 11:13:41.553964 00d80000 ################################################################
10238 11:13:41.554170
10239 11:13:41.773950 00e00000 ################################################################
10240 11:13:41.774114
10241 11:13:41.998992 00e80000 ################################################################
10242 11:13:41.999139
10243 11:13:42.243376 00f00000 ################################################################
10244 11:13:42.243555
10245 11:13:42.473992 00f80000 ################################################################
10246 11:13:42.474158
10247 11:13:42.707200 01000000 ################################################################
10248 11:13:42.707380
10249 11:13:42.936612 01080000 ################################################################
10250 11:13:42.936786
10251 11:13:43.161023 01100000 ################################################################
10252 11:13:43.161170
10253 11:13:43.412432 01180000 ################################################################
10254 11:13:43.412601
10255 11:13:43.639884 01200000 ################################################################
10256 11:13:43.640035
10257 11:13:43.874067 01280000 ################################################################
10258 11:13:43.874213
10259 11:13:44.101567 01300000 ################################################################
10260 11:13:44.101702
10261 11:13:44.326489 01380000 ################################################################
10262 11:13:44.326639
10263 11:13:44.548905 01400000 ################################################################
10264 11:13:44.549094
10265 11:13:44.784440 01480000 ################################################################
10266 11:13:44.784622
10267 11:13:45.034112 01500000 ################################################################
10268 11:13:45.034264
10269 11:13:45.251727 01580000 ################################################################
10270 11:13:45.251908
10271 11:13:45.471812 01600000 ################################################################
10272 11:13:45.471959
10273 11:13:45.688808 01680000 ################################################################
10274 11:13:45.688985
10275 11:13:45.910705 01700000 ################################################################
10276 11:13:45.910855
10277 11:13:46.138207 01780000 ################################################################
10278 11:13:46.138347
10279 11:13:46.365163 01800000 ################################################################
10280 11:13:46.365314
10281 11:13:46.591233 01880000 ################################################################
10282 11:13:46.591383
10283 11:13:46.820740 01900000 ################################################################
10284 11:13:46.820891
10285 11:13:47.070924 01980000 ################################################################
10286 11:13:47.071094
10287 11:13:47.284197 01a00000 ################################################################ done.
10288 11:13:47.284379
10289 11:13:47.287830 The bootfile was 27781418 bytes long.
10290 11:13:47.287941
10291 11:13:47.291146 Sending tftp read request... done.
10292 11:13:47.291259
10293 11:13:47.294836 Waiting for the transfer...
10294 11:13:47.294952
10295 11:13:47.295056 00000000 # done.
10296 11:13:47.295165
10297 11:13:47.304277 Command line loaded dynamically from TFTP file: 10591227/tftp-deploy-cv815yyk/kernel/cmdline
10298 11:13:47.304389
10299 11:13:47.324318 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591227/extract-nfsrootfs-_ng094gw,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10300 11:13:47.324436
10301 11:13:47.324542 Loading FIT.
10302 11:13:47.324611
10303 11:13:47.327289 Image ramdisk-1 has 17646437 bytes.
10304 11:13:47.327406
10305 11:13:47.330439 Image fdt-1 has 46924 bytes.
10306 11:13:47.330559
10307 11:13:47.334060 Image kernel-1 has 10086024 bytes.
10308 11:13:47.334163
10309 11:13:47.340711 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10310 11:13:47.340815
10311 11:13:47.360681 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10312 11:13:47.360812
10313 11:13:47.363695 Choosing best match conf-1 for compat google,spherion-rev2.
10314 11:13:47.368464
10315 11:13:47.372764 Connected to device vid:did:rid of 1ae0:0028:00
10316 11:13:47.379975
10317 11:13:47.383560 tpm_get_response: command 0x17b, return code 0x0
10318 11:13:47.383652
10319 11:13:47.387141 ec_init: CrosEC protocol v3 supported (256, 248)
10320 11:13:47.391122
10321 11:13:47.394437 tpm_cleanup: add release locality here.
10322 11:13:47.394542
10323 11:13:47.394689 Shutting down all USB controllers.
10324 11:13:47.397325
10325 11:13:47.397440 Removing current net device
10326 11:13:47.397535
10327 11:13:47.403894 Exiting depthcharge with code 4 at timestamp: 46477163
10328 11:13:47.404002
10329 11:13:47.407476 LZMA decompressing kernel-1 to 0x821a6718
10330 11:13:47.407581
10331 11:13:47.410252 LZMA decompressing kernel-1 to 0x40000000
10332 11:13:48.677273
10333 11:13:48.677458 jumping to kernel
10334 11:13:48.677893 end: 2.2.4 bootloader-commands (duration 00:00:18) [common]
10335 11:13:48.678025 start: 2.2.5 auto-login-action (timeout 00:04:07) [common]
10336 11:13:48.678122 Setting prompt string to ['Linux version [0-9]']
10337 11:13:48.678262 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10338 11:13:48.678344 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10339 11:13:48.759152
10340 11:13:48.762383 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10341 11:13:48.766118 start: 2.2.5.1 login-action (timeout 00:04:07) [common]
10342 11:13:48.766238 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10343 11:13:48.766353 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10344 11:13:48.766461 Using line separator: #'\n'#
10345 11:13:48.766536 No login prompt set.
10346 11:13:48.766615 Parsing kernel messages
10347 11:13:48.766702 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10348 11:13:48.766835 [login-action] Waiting for messages, (timeout 00:04:07)
10349 11:13:48.785834 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10350 11:13:48.788882 [ 0.000000] random: crng init done
10351 11:13:48.795077 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10352 11:13:48.798795 [ 0.000000] efi: UEFI not found.
10353 11:13:48.805451 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10354 11:13:48.811554 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10355 11:13:48.821717 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10356 11:13:48.831373 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10357 11:13:48.837920 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10358 11:13:48.844890 [ 0.000000] printk: bootconsole [mtk8250] enabled
10359 11:13:48.851283 [ 0.000000] NUMA: No NUMA configuration found
10360 11:13:48.857518 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10361 11:13:48.864346 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10362 11:13:48.864430 [ 0.000000] Zone ranges:
10363 11:13:48.870540 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10364 11:13:48.874039 [ 0.000000] DMA32 empty
10365 11:13:48.880276 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10366 11:13:48.883768 [ 0.000000] Movable zone start for each node
10367 11:13:48.887296 [ 0.000000] Early memory node ranges
10368 11:13:48.893842 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10369 11:13:48.899953 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10370 11:13:48.906741 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10371 11:13:48.913309 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10372 11:13:48.919988 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10373 11:13:48.926605 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10374 11:13:48.983412 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10375 11:13:48.989674 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10376 11:13:48.996260 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10377 11:13:48.999896 [ 0.000000] psci: probing for conduit method from DT.
10378 11:13:49.006545 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10379 11:13:49.009439 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10380 11:13:49.016113 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10381 11:13:49.019701 [ 0.000000] psci: SMC Calling Convention v1.2
10382 11:13:49.025885 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10383 11:13:49.029412 [ 0.000000] Detected VIPT I-cache on CPU0
10384 11:13:49.036119 [ 0.000000] CPU features: detected: GIC system register CPU interface
10385 11:13:49.042156 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10386 11:13:49.048801 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10387 11:13:49.055422 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10388 11:13:49.065470 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10389 11:13:49.071913 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10390 11:13:49.075441 [ 0.000000] alternatives: applying boot alternatives
10391 11:13:49.082466 [ 0.000000] Fallback order for Node 0: 0
10392 11:13:49.088674 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10393 11:13:49.092065 [ 0.000000] Policy zone: Normal
10394 11:13:49.111886 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591227/extract-nfsrootfs-_ng094gw,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10395 11:13:49.121669 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10396 11:13:49.132766 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10397 11:13:49.142528 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10398 11:13:49.149167 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10399 11:13:49.152176 <6>[ 0.000000] software IO TLB: area num 8.
10400 11:13:49.209137 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10401 11:13:49.359240 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10402 11:13:49.365287 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10403 11:13:49.371839 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10404 11:13:49.375471 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10405 11:13:49.381704 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10406 11:13:49.388706 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10407 11:13:49.391917 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10408 11:13:49.401446 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10409 11:13:49.408425 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10410 11:13:49.414642 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10411 11:13:49.421456 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10412 11:13:49.424742 <6>[ 0.000000] GICv3: 608 SPIs implemented
10413 11:13:49.428248 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10414 11:13:49.435007 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10415 11:13:49.438033 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10416 11:13:49.444824 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10417 11:13:49.457471 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10418 11:13:49.470858 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10419 11:13:49.477242 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10420 11:13:49.485359 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10421 11:13:49.498543 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10422 11:13:49.505498 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10423 11:13:49.511885 <6>[ 0.009228] Console: colour dummy device 80x25
10424 11:13:49.522178 <6>[ 0.013958] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10425 11:13:49.528319 <6>[ 0.024400] pid_max: default: 32768 minimum: 301
10426 11:13:49.531830 <6>[ 0.029274] LSM: Security Framework initializing
10427 11:13:49.538465 <6>[ 0.034214] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10428 11:13:49.548178 <6>[ 0.042027] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10429 11:13:49.558177 <6>[ 0.051457] cblist_init_generic: Setting adjustable number of callback queues.
10430 11:13:49.561757 <6>[ 0.058955] cblist_init_generic: Setting shift to 3 and lim to 1.
10431 11:13:49.567887 <6>[ 0.065331] cblist_init_generic: Setting shift to 3 and lim to 1.
10432 11:13:49.575093 <6>[ 0.071736] rcu: Hierarchical SRCU implementation.
10433 11:13:49.580969 <6>[ 0.076750] rcu: Max phase no-delay instances is 1000.
10434 11:13:49.587661 <6>[ 0.083800] EFI services will not be available.
10435 11:13:49.591074 <6>[ 0.088802] smp: Bringing up secondary CPUs ...
10436 11:13:49.598772 <6>[ 0.093855] Detected VIPT I-cache on CPU1
10437 11:13:49.605322 <6>[ 0.093930] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10438 11:13:49.612102 <6>[ 0.093962] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10439 11:13:49.615519 <6>[ 0.094298] Detected VIPT I-cache on CPU2
10440 11:13:49.624970 <6>[ 0.094353] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10441 11:13:49.631810 <6>[ 0.094370] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10442 11:13:49.634914 <6>[ 0.094637] Detected VIPT I-cache on CPU3
10443 11:13:49.641712 <6>[ 0.094685] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10444 11:13:49.648221 <6>[ 0.094700] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10445 11:13:49.651834 <6>[ 0.095007] CPU features: detected: Spectre-v4
10446 11:13:49.658431 <6>[ 0.095013] CPU features: detected: Spectre-BHB
10447 11:13:49.661751 <6>[ 0.095019] Detected PIPT I-cache on CPU4
10448 11:13:49.668082 <6>[ 0.095077] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10449 11:13:49.674889 <6>[ 0.095094] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10450 11:13:49.681147 <6>[ 0.095386] Detected PIPT I-cache on CPU5
10451 11:13:49.687904 <6>[ 0.095441] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10452 11:13:49.694934 <6>[ 0.095457] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10453 11:13:49.697775 <6>[ 0.095728] Detected PIPT I-cache on CPU6
10454 11:13:49.704774 <6>[ 0.095792] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10455 11:13:49.711099 <6>[ 0.095809] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10456 11:13:49.718165 <6>[ 0.096108] Detected PIPT I-cache on CPU7
10457 11:13:49.724640 <6>[ 0.096173] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10458 11:13:49.731198 <6>[ 0.096189] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10459 11:13:49.734203 <6>[ 0.096235] smp: Brought up 1 node, 8 CPUs
10460 11:13:49.740587 <6>[ 0.237522] SMP: Total of 8 processors activated.
10461 11:13:49.744250 <6>[ 0.242443] CPU features: detected: 32-bit EL0 Support
10462 11:13:49.754039 <6>[ 0.247805] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10463 11:13:49.760845 <6>[ 0.256606] CPU features: detected: Common not Private translations
10464 11:13:49.767520 <6>[ 0.263081] CPU features: detected: CRC32 instructions
10465 11:13:49.774099 <6>[ 0.268465] CPU features: detected: RCpc load-acquire (LDAPR)
10466 11:13:49.776950 <6>[ 0.274425] CPU features: detected: LSE atomic instructions
10467 11:13:49.783513 <6>[ 0.280242] CPU features: detected: Privileged Access Never
10468 11:13:49.790087 <6>[ 0.286021] CPU features: detected: RAS Extension Support
10469 11:13:49.796637 <6>[ 0.291630] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10470 11:13:49.800289 <6>[ 0.298850] CPU: All CPU(s) started at EL2
10471 11:13:49.806350 <6>[ 0.303193] alternatives: applying system-wide alternatives
10472 11:13:49.816427 <6>[ 0.313881] devtmpfs: initialized
10473 11:13:49.832595 <6>[ 0.323020] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10474 11:13:49.839273 <6>[ 0.332979] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10475 11:13:49.845545 <6>[ 0.341197] pinctrl core: initialized pinctrl subsystem
10476 11:13:49.848961 <6>[ 0.347853] DMI not present or invalid.
10477 11:13:49.855679 <6>[ 0.352260] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10478 11:13:49.865304 <6>[ 0.359147] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10479 11:13:49.871970 <6>[ 0.366727] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10480 11:13:49.881582 <6>[ 0.374957] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10481 11:13:49.885218 <6>[ 0.383196] audit: initializing netlink subsys (disabled)
10482 11:13:49.894972 <5>[ 0.388888] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10483 11:13:49.901460 <6>[ 0.389605] thermal_sys: Registered thermal governor 'step_wise'
10484 11:13:49.908628 <6>[ 0.396853] thermal_sys: Registered thermal governor 'power_allocator'
10485 11:13:49.911381 <6>[ 0.403107] cpuidle: using governor menu
10486 11:13:49.918252 <6>[ 0.414060] NET: Registered PF_QIPCRTR protocol family
10487 11:13:49.924585 <6>[ 0.419549] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10488 11:13:49.930870 <6>[ 0.426648] ASID allocator initialised with 32768 entries
10489 11:13:49.934312 <6>[ 0.433234] Serial: AMBA PL011 UART driver
10490 11:13:49.944108 <4>[ 0.441961] Trying to register duplicate clock ID: 134
10491 11:13:49.999062 <6>[ 0.499395] KASLR enabled
10492 11:13:50.013057 <6>[ 0.507175] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10493 11:13:50.020184 <6>[ 0.514186] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10494 11:13:50.026629 <6>[ 0.520675] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10495 11:13:50.033035 <6>[ 0.527684] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10496 11:13:50.039340 <6>[ 0.534170] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10497 11:13:50.046532 <6>[ 0.541176] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10498 11:13:50.053111 <6>[ 0.547660] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10499 11:13:50.059419 <6>[ 0.554664] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10500 11:13:50.063037 <6>[ 0.562188] ACPI: Interpreter disabled.
10501 11:13:50.071468 <6>[ 0.568598] iommu: Default domain type: Translated
10502 11:13:50.078016 <6>[ 0.573711] iommu: DMA domain TLB invalidation policy: strict mode
10503 11:13:50.081106 <5>[ 0.580366] SCSI subsystem initialized
10504 11:13:50.087731 <6>[ 0.584530] usbcore: registered new interface driver usbfs
10505 11:13:50.094317 <6>[ 0.590264] usbcore: registered new interface driver hub
10506 11:13:50.097828 <6>[ 0.595817] usbcore: registered new device driver usb
10507 11:13:50.104239 <6>[ 0.601904] pps_core: LinuxPPS API ver. 1 registered
10508 11:13:50.114606 <6>[ 0.607100] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10509 11:13:50.117545 <6>[ 0.616446] PTP clock support registered
10510 11:13:50.121018 <6>[ 0.620685] EDAC MC: Ver: 3.0.0
10511 11:13:50.128394 <6>[ 0.625839] FPGA manager framework
10512 11:13:50.134822 <6>[ 0.629522] Advanced Linux Sound Architecture Driver Initialized.
10513 11:13:50.138205 <6>[ 0.636293] vgaarb: loaded
10514 11:13:50.144848 <6>[ 0.639457] clocksource: Switched to clocksource arch_sys_counter
10515 11:13:50.148245 <5>[ 0.645891] VFS: Disk quotas dquot_6.6.0
10516 11:13:50.154611 <6>[ 0.650075] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10517 11:13:50.157844 <6>[ 0.657265] pnp: PnP ACPI: disabled
10518 11:13:50.167018 <6>[ 0.663978] NET: Registered PF_INET protocol family
10519 11:13:50.176638 <6>[ 0.669564] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10520 11:13:50.187910 <6>[ 0.681844] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10521 11:13:50.197530 <6>[ 0.690661] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10522 11:13:50.204331 <6>[ 0.698628] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10523 11:13:50.214094 <6>[ 0.707326] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10524 11:13:50.221230 <6>[ 0.717041] TCP: Hash tables configured (established 65536 bind 65536)
10525 11:13:50.227477 <6>[ 0.723900] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10526 11:13:50.237500 <6>[ 0.731099] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10527 11:13:50.244268 <6>[ 0.738802] NET: Registered PF_UNIX/PF_LOCAL protocol family
10528 11:13:50.247056 <6>[ 0.744972] RPC: Registered named UNIX socket transport module.
10529 11:13:50.254219 <6>[ 0.751123] RPC: Registered udp transport module.
10530 11:13:50.257321 <6>[ 0.756056] RPC: Registered tcp transport module.
10531 11:13:50.263876 <6>[ 0.760987] RPC: Registered tcp NFSv4.1 backchannel transport module.
10532 11:13:50.270772 <6>[ 0.767658] PCI: CLS 0 bytes, default 64
10533 11:13:50.273671 <6>[ 0.772015] Unpacking initramfs...
10534 11:13:50.289936 <6>[ 0.784100] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10535 11:13:50.299709 <6>[ 0.792739] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10536 11:13:50.303436 <6>[ 0.801573] kvm [1]: IPA Size Limit: 40 bits
10537 11:13:50.309914 <6>[ 0.806097] kvm [1]: GICv3: no GICV resource entry
10538 11:13:50.312892 <6>[ 0.811118] kvm [1]: disabling GICv2 emulation
10539 11:13:50.319589 <6>[ 0.815802] kvm [1]: GIC system register CPU interface enabled
10540 11:13:50.323216 <6>[ 0.821957] kvm [1]: vgic interrupt IRQ18
10541 11:13:50.329533 <6>[ 0.826324] kvm [1]: VHE mode initialized successfully
10542 11:13:50.336599 <5>[ 0.832819] Initialise system trusted keyrings
10543 11:13:50.343044 <6>[ 0.837668] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10544 11:13:50.350379 <6>[ 0.847744] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10545 11:13:50.356965 <5>[ 0.854152] NFS: Registering the id_resolver key type
10546 11:13:50.360311 <5>[ 0.859460] Key type id_resolver registered
10547 11:13:50.367069 <5>[ 0.863872] Key type id_legacy registered
10548 11:13:50.373745 <6>[ 0.868151] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10549 11:13:50.380113 <6>[ 0.875071] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10550 11:13:50.386903 <6>[ 0.882791] 9p: Installing v9fs 9p2000 file system support
10551 11:13:50.423386 <5>[ 0.920765] Key type asymmetric registered
10552 11:13:50.426863 <5>[ 0.925098] Asymmetric key parser 'x509' registered
10553 11:13:50.436501 <6>[ 0.930241] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10554 11:13:50.440056 <6>[ 0.937857] io scheduler mq-deadline registered
10555 11:13:50.443367 <6>[ 0.942619] io scheduler kyber registered
10556 11:13:50.462489 <6>[ 0.959759] EINJ: ACPI disabled.
10557 11:13:50.494245 <4>[ 0.984708] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10558 11:13:50.503622 <4>[ 0.995343] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10559 11:13:50.518651 <6>[ 1.016245] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10560 11:13:50.526767 <6>[ 1.024251] printk: console [ttyS0] disabled
10561 11:13:50.554820 <6>[ 1.048907] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10562 11:13:50.561792 <6>[ 1.058387] printk: console [ttyS0] enabled
10563 11:13:50.564682 <6>[ 1.058387] printk: console [ttyS0] enabled
10564 11:13:50.571238 <6>[ 1.067282] printk: bootconsole [mtk8250] disabled
10565 11:13:50.575061 <6>[ 1.067282] printk: bootconsole [mtk8250] disabled
10566 11:13:50.581706 <6>[ 1.078466] SuperH (H)SCI(F) driver initialized
10567 11:13:50.584567 <6>[ 1.083746] msm_serial: driver initialized
10568 11:13:50.598764 <6>[ 1.092673] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10569 11:13:50.608762 <6>[ 1.101219] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10570 11:13:50.615174 <6>[ 1.109760] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10571 11:13:50.624918 <6>[ 1.118391] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10572 11:13:50.635318 <6>[ 1.127097] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10573 11:13:50.641802 <6>[ 1.135810] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10574 11:13:50.651565 <6>[ 1.144351] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10575 11:13:50.658175 <6>[ 1.153170] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10576 11:13:50.667971 <6>[ 1.161718] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10577 11:13:50.680005 <6>[ 1.177373] loop: module loaded
10578 11:13:50.686581 <6>[ 1.183455] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10579 11:13:50.709448 <4>[ 1.206845] mtk-pmic-keys: Failed to locate of_node [id: -1]
10580 11:13:50.715840 <6>[ 1.213641] megasas: 07.719.03.00-rc1
10581 11:13:50.725370 <6>[ 1.223143] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10582 11:13:50.737030 <6>[ 1.234851] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10583 11:13:50.754182 <6>[ 1.251642] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10584 11:13:50.814705 <6>[ 1.305884] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10585 11:13:51.002679 <6>[ 1.500264] Freeing initrd memory: 17228K
10586 11:13:51.013125 <6>[ 1.510496] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10587 11:13:51.023704 <6>[ 1.521189] tun: Universal TUN/TAP device driver, 1.6
10588 11:13:51.027102 <6>[ 1.527232] thunder_xcv, ver 1.0
10589 11:13:51.030697 <6>[ 1.530735] thunder_bgx, ver 1.0
10590 11:13:51.033642 <6>[ 1.534231] nicpf, ver 1.0
10591 11:13:51.044185 <6>[ 1.538227] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10592 11:13:51.047763 <6>[ 1.545702] hns3: Copyright (c) 2017 Huawei Corporation.
10593 11:13:51.054325 <6>[ 1.551288] hclge is initializing
10594 11:13:51.057256 <6>[ 1.554867] e1000: Intel(R) PRO/1000 Network Driver
10595 11:13:51.064002 <6>[ 1.559995] e1000: Copyright (c) 1999-2006 Intel Corporation.
10596 11:13:51.067372 <6>[ 1.566011] e1000e: Intel(R) PRO/1000 Network Driver
10597 11:13:51.073907 <6>[ 1.571226] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10598 11:13:51.080776 <6>[ 1.577412] igb: Intel(R) Gigabit Ethernet Network Driver
10599 11:13:51.087353 <6>[ 1.583062] igb: Copyright (c) 2007-2014 Intel Corporation.
10600 11:13:51.093600 <6>[ 1.588899] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10601 11:13:51.100322 <6>[ 1.595417] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10602 11:13:51.103538 <6>[ 1.601877] sky2: driver version 1.30
10603 11:13:51.110173 <6>[ 1.606849] VFIO - User Level meta-driver version: 0.3
10604 11:13:51.118014 <6>[ 1.614959] usbcore: registered new interface driver usb-storage
10605 11:13:51.124026 <6>[ 1.621409] usbcore: registered new device driver onboard-usb-hub
10606 11:13:51.133336 <6>[ 1.630443] mt6397-rtc mt6359-rtc: registered as rtc0
10607 11:13:51.143290 <6>[ 1.635911] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:13:51 UTC (1685963631)
10608 11:13:51.146322 <6>[ 1.645488] i2c_dev: i2c /dev entries driver
10609 11:13:51.163248 <6>[ 1.657092] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10610 11:13:51.169630 <6>[ 1.667296] sdhci: Secure Digital Host Controller Interface driver
10611 11:13:51.176228 <6>[ 1.673732] sdhci: Copyright(c) Pierre Ossman
10612 11:13:51.182918 <6>[ 1.679130] Synopsys Designware Multimedia Card Interface Driver
10613 11:13:51.186893 <6>[ 1.685744] mmc0: CQHCI version 5.10
10614 11:13:51.193200 <6>[ 1.686280] sdhci-pltfm: SDHCI platform and OF driver helper
10615 11:13:51.200266 <6>[ 1.697790] ledtrig-cpu: registered to indicate activity on CPUs
10616 11:13:51.210638 <6>[ 1.705022] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10617 11:13:51.214467 <6>[ 1.712430] usbcore: registered new interface driver usbhid
10618 11:13:51.220635 <6>[ 1.718258] usbhid: USB HID core driver
10619 11:13:51.227730 <6>[ 1.722510] spi_master spi0: will run message pump with realtime priority
10620 11:13:51.276349 <6>[ 1.766708] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10621 11:13:51.296149 <6>[ 1.782808] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10622 11:13:51.298941 <6>[ 1.796370] mmc0: Command Queue Engine enabled
10623 11:13:51.305923 <6>[ 1.798143] cros-ec-spi spi0.0: Chrome EC device registered
10624 11:13:51.312490 <6>[ 1.801100] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10625 11:13:51.316202 <6>[ 1.814446] mmcblk0: mmc0:0001 DA4128 116 GiB
10626 11:13:51.328337 <6>[ 1.825809] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10627 11:13:51.338538 <6>[ 1.826966] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10628 11:13:51.345016 <6>[ 1.833194] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10629 11:13:51.348692 <6>[ 1.843196] NET: Registered PF_PACKET protocol family
10630 11:13:51.354993 <6>[ 1.846933] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10631 11:13:51.357998 <6>[ 1.851723] 9pnet: Installing 9P2000 support
10632 11:13:51.364669 <6>[ 1.857436] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10633 11:13:51.371253 <5>[ 1.861381] Key type dns_resolver registered
10634 11:13:51.374357 <6>[ 1.873048] registered taskstats version 1
10635 11:13:51.381477 <5>[ 1.877493] Loading compiled-in X.509 certificates
10636 11:13:51.413255 <4>[ 1.904195] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10637 11:13:51.423671 <4>[ 1.914882] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10638 11:13:51.433840 <3>[ 1.927783] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10639 11:13:51.445888 <6>[ 1.943141] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10640 11:13:51.452667 <6>[ 1.950024] xhci-mtk 11200000.usb: xHCI Host Controller
10641 11:13:51.459617 <6>[ 1.955522] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10642 11:13:51.469518 <6>[ 1.963374] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10643 11:13:51.476242 <6>[ 1.972815] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10644 11:13:51.482479 <6>[ 1.978924] xhci-mtk 11200000.usb: xHCI Host Controller
10645 11:13:51.489033 <6>[ 1.984407] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10646 11:13:51.495630 <6>[ 1.992064] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10647 11:13:51.501780 <6>[ 1.999774] hub 1-0:1.0: USB hub found
10648 11:13:51.505475 <6>[ 2.003796] hub 1-0:1.0: 1 port detected
10649 11:13:51.516116 <6>[ 2.008127] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10650 11:13:51.519300 <6>[ 2.016853] hub 2-0:1.0: USB hub found
10651 11:13:51.522268 <6>[ 2.020886] hub 2-0:1.0: 1 port detected
10652 11:13:51.530580 <6>[ 2.028140] mtk-msdc 11f70000.mmc: Got CD GPIO
10653 11:13:51.548157 <6>[ 2.042083] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10654 11:13:51.554611 <6>[ 2.050121] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10655 11:13:51.564291 <4>[ 2.058100] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10656 11:13:51.574150 <6>[ 2.067759] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10657 11:13:51.580827 <6>[ 2.075841] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10658 11:13:51.587585 <6>[ 2.083872] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10659 11:13:51.597582 <6>[ 2.091788] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10660 11:13:51.603992 <6>[ 2.099609] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10661 11:13:51.613978 <6>[ 2.107432] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10662 11:13:51.623876 <6>[ 2.118258] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10663 11:13:51.634356 <6>[ 2.126628] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10664 11:13:51.641132 <6>[ 2.134989] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10665 11:13:51.650994 <6>[ 2.143333] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10666 11:13:51.657453 <6>[ 2.151677] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10667 11:13:51.667539 <6>[ 2.160019] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10668 11:13:51.674142 <6>[ 2.168361] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10669 11:13:51.683693 <6>[ 2.176704] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10670 11:13:51.690631 <6>[ 2.185046] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10671 11:13:51.700542 <6>[ 2.193388] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10672 11:13:51.707035 <6>[ 2.201731] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10673 11:13:51.716880 <6>[ 2.210074] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10674 11:13:51.723563 <6>[ 2.218417] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10675 11:13:51.733764 <6>[ 2.226765] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10676 11:13:51.740194 <6>[ 2.235110] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10677 11:13:51.746885 <6>[ 2.244065] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10678 11:13:51.754093 <6>[ 2.251570] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10679 11:13:51.761158 <6>[ 2.258587] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10680 11:13:51.771577 <6>[ 2.265710] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10681 11:13:51.778148 <6>[ 2.272982] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10682 11:13:51.787981 <6>[ 2.279888] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10683 11:13:51.794547 <6>[ 2.289029] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10684 11:13:51.805191 <6>[ 2.298156] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10685 11:13:51.814445 <6>[ 2.307459] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10686 11:13:51.824759 <6>[ 2.316934] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10687 11:13:51.834434 <6>[ 2.326407] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10688 11:13:51.840943 <6>[ 2.335534] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10689 11:13:51.850746 <6>[ 2.345008] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10690 11:13:51.861118 <6>[ 2.354135] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10691 11:13:51.870815 <6>[ 2.363436] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10692 11:13:51.880854 <6>[ 2.373601] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10693 11:13:51.890987 <6>[ 2.385095] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10694 11:13:51.897570 <6>[ 2.395046] Trying to probe devices needed for running init ...
10695 11:13:51.933261 <6>[ 2.427702] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10696 11:13:52.086615 <6>[ 2.583730] hub 1-1:1.0: USB hub found
10697 11:13:52.089726 <6>[ 2.588090] hub 1-1:1.0: 4 ports detected
10698 11:13:52.213574 <6>[ 2.707789] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10699 11:13:52.240826 <6>[ 2.738086] hub 2-1:1.0: USB hub found
10700 11:13:52.243608 <6>[ 2.742559] hub 2-1:1.0: 3 ports detected
10701 11:13:52.409652 <6>[ 2.903762] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10702 11:13:52.540181 <6>[ 3.037615] hub 1-1.1:1.0: USB hub found
10703 11:13:52.543529 <6>[ 3.041897] hub 1-1.1:1.0: 4 ports detected
10704 11:13:52.657155 <6>[ 3.151588] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10705 11:13:52.790185 <6>[ 3.287756] hub 1-1.4:1.0: USB hub found
10706 11:13:52.793424 <6>[ 3.292429] hub 1-1.4:1.0: 2 ports detected
10707 11:13:52.873165 <6>[ 3.367734] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10708 11:13:53.061794 <6>[ 3.555731] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10709 11:13:53.146225 <3>[ 3.643819] usb 1-1.1.4: device descriptor read/64, error -32
10710 11:13:53.338047 <3>[ 3.835939] usb 1-1.1.4: device descriptor read/64, error -32
10711 11:13:53.533240 <6>[ 4.027735] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10712 11:13:53.721480 <6>[ 4.215753] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10713 11:13:53.805942 <3>[ 4.303936] usb 1-1.1.4: device descriptor read/64, error -32
10714 11:13:53.998236 <3>[ 4.495938] usb 1-1.1.4: device descriptor read/64, error -32
10715 11:13:54.110378 <6>[ 4.608298] usb 1-1.1-port4: attempt power cycle
10716 11:13:54.197195 <6>[ 4.691731] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10717 11:13:54.721332 <6>[ 5.215729] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10718 11:13:54.727913 <4>[ 5.223182] usb 1-1.1.4: Device not responding to setup address.
10719 11:13:54.938118 <4>[ 5.436036] usb 1-1.1.4: Device not responding to setup address.
10720 11:13:55.149558 <3>[ 5.647583] usb 1-1.1.4: device not accepting address 10, error -71
10721 11:13:55.237523 <6>[ 5.731689] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10722 11:13:55.243543 <4>[ 5.739206] usb 1-1.1.4: Device not responding to setup address.
10723 11:13:55.454196 <4>[ 5.952091] usb 1-1.1.4: Device not responding to setup address.
10724 11:13:55.666207 <3>[ 6.163584] usb 1-1.1.4: device not accepting address 11, error -71
10725 11:13:55.672597 <3>[ 6.170530] usb 1-1.1-port4: unable to enumerate USB device
10726 11:14:04.198202 <6>[ 14.700283] ALSA device list:
10727 11:14:04.204573 <6>[ 14.703540] No soundcards found.
10728 11:14:04.216916 <6>[ 14.715966] Freeing unused kernel memory: 8384K
10729 11:14:04.219839 <6>[ 14.720899] Run /init as init process
10730 11:14:04.230248 Loading, please wait...
10731 11:14:04.249440 Starting version 247.3-7+deb11u2
10732 11:14:04.566115 <6>[ 15.061822] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10733 11:14:04.580203 <6>[ 15.079138] remoteproc remoteproc0: scp is available
10734 11:14:04.590337 <4>[ 15.084562] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10735 11:14:04.596981 <6>[ 15.094410] remoteproc remoteproc0: powering up scp
10736 11:14:04.606360 <4>[ 15.099587] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10737 11:14:04.613313 <3>[ 15.101085] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 11:14:04.620035 <3>[ 15.112667] remoteproc remoteproc0: request_firmware failed: -2
10739 11:14:04.626148 <3>[ 15.117849] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 11:14:04.636547 <3>[ 15.131832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 11:14:04.653765 <3>[ 15.149405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 11:14:04.660606 <4>[ 15.156391] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10743 11:14:04.670273 <3>[ 15.157545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 11:14:04.676810 <4>[ 15.164996] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10745 11:14:04.683603 <3>[ 15.172911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 11:14:04.693327 <6>[ 15.177277] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10747 11:14:04.699852 <6>[ 15.177323] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10748 11:14:04.709990 <6>[ 15.177336] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10749 11:14:04.713506 <6>[ 15.196442] mc: Linux media interface: v0.10
10750 11:14:04.723074 <3>[ 15.204566] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 11:14:04.729682 <3>[ 15.204576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 11:14:04.740111 <3>[ 15.204655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 11:14:04.746334 <3>[ 15.204716] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 11:14:04.752941 <3>[ 15.204725] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 11:14:04.763818 <6>[ 15.214039] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10756 11:14:04.766952 <6>[ 15.214147] usbcore: registered new interface driver r8152
10757 11:14:04.776914 <3>[ 15.217935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 11:14:04.783828 <3>[ 15.218024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 11:14:04.793882 <4>[ 15.237045] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10760 11:14:04.797638 <4>[ 15.237045] Fallback method does not support PEC.
10761 11:14:04.804260 <3>[ 15.242236] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 11:14:04.814731 <3>[ 15.242249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 11:14:04.821060 <3>[ 15.242274] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 11:14:04.831060 <3>[ 15.242283] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 11:14:04.837164 <3>[ 15.266853] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10766 11:14:04.847503 <3>[ 15.271858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 11:14:04.857215 <6>[ 15.290718] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10768 11:14:04.864081 <6>[ 15.296831] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10769 11:14:04.870291 <6>[ 15.296838] pci_bus 0000:00: root bus resource [bus 00-ff]
10770 11:14:04.876919 <6>[ 15.296847] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10771 11:14:04.887151 <6>[ 15.296852] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10772 11:14:04.893118 <6>[ 15.296890] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10773 11:14:04.899816 <6>[ 15.296911] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10774 11:14:04.903590 <6>[ 15.296999] pci 0000:00:00.0: supports D1 D2
10775 11:14:04.910120 <6>[ 15.297003] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10776 11:14:04.919441 <6>[ 15.298654] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10777 11:14:04.926415 <6>[ 15.298756] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10778 11:14:04.933031 <6>[ 15.298787] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10779 11:14:04.939520 <6>[ 15.298806] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10780 11:14:04.948951 <6>[ 15.298825] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10781 11:14:04.952607 <6>[ 15.298947] pci 0000:01:00.0: supports D1 D2
10782 11:14:04.959152 <6>[ 15.298950] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10783 11:14:04.968678 <3>[ 15.301616] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10784 11:14:04.975418 <6>[ 15.311964] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10785 11:14:04.982493 <6>[ 15.318090] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10786 11:14:04.991773 <6>[ 15.325945] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10787 11:14:05.002246 <6>[ 15.336296] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10788 11:14:05.008860 <6>[ 15.342796] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10789 11:14:05.018719 <6>[ 15.351282] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10790 11:14:05.025183 <6>[ 15.360178] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10791 11:14:05.031840 <6>[ 15.380795] videodev: Linux video capture interface: v2.00
10792 11:14:05.038043 <6>[ 15.390013] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10793 11:14:05.045149 <6>[ 15.397604] usbcore: registered new interface driver cdc_ether
10794 11:14:05.055034 <6>[ 15.404180] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10795 11:14:05.057927 <6>[ 15.409829] Bluetooth: Core ver 2.22
10796 11:14:05.065028 <6>[ 15.415387] pci 0000:00:00.0: PCI bridge to [bus 01]
10797 11:14:05.067854 <6>[ 15.415596] usbcore: registered new interface driver r8153_ecm
10798 11:14:05.074810 <6>[ 15.423640] NET: Registered PF_BLUETOOTH protocol family
10799 11:14:05.084413 <6>[ 15.429857] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10800 11:14:05.090935 <6>[ 15.437336] Bluetooth: HCI device and connection manager initialized
10801 11:14:05.097758 <6>[ 15.438578] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10802 11:14:05.107595 <6>[ 15.440066] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10803 11:14:05.114023 <6>[ 15.440344] usbcore: registered new interface driver uvcvideo
10804 11:14:05.123995 <4>[ 15.443097] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10805 11:14:05.133527 <4>[ 15.443106] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10806 11:14:05.136939 <6>[ 15.445010] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10807 11:14:05.143761 <6>[ 15.452308] Bluetooth: HCI socket layer initialized
10808 11:14:05.150280 <6>[ 15.453034] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10809 11:14:05.157005 <6>[ 15.457697] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10810 11:14:05.160242 <6>[ 15.463688] Bluetooth: L2CAP socket layer initialized
10811 11:14:05.166591 <6>[ 15.463697] Bluetooth: SCO socket layer initialized
10812 11:14:05.173379 <6>[ 15.472870] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10813 11:14:05.176906 <6>[ 15.495565] r8152 1-1.1.1:1.0 eth0: v1.12.13
10814 11:14:05.186037 <5>[ 15.524415] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10815 11:14:05.189559 <6>[ 15.536609] usbcore: registered new interface driver btusb
10816 11:14:05.199625 <4>[ 15.537579] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10817 11:14:05.206348 <3>[ 15.537593] Bluetooth: hci0: Failed to load firmware file (-2)
10818 11:14:05.212893 <3>[ 15.537599] Bluetooth: hci0: Failed to set up firmware (-2)
10819 11:14:05.223000 <4>[ 15.537604] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10820 11:14:05.228926 <6>[ 15.540050] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10821 11:14:05.235543 <5>[ 15.554940] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10822 11:14:05.247962 <4>[ 15.743975] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10823 11:14:05.254786 <6>[ 15.752874] cfg80211: failed to load regulatory.db
10824 11:14:05.297355 <6>[ 15.793096] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10825 11:14:05.304140 <6>[ 15.800609] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10826 11:14:05.328502 <6>[ 15.827304] mt7921e 0000:01:00.0: ASIC revision: 79610010
10827 11:14:05.434255 <4>[ 15.927049] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10828 11:14:05.438042 Begin: Loading essential drivers ... done.
10829 11:14:05.440960 Begin: Running /scripts/init-premount ... done.
10830 11:14:05.451361 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10831 11:14:05.457904 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10832 11:14:05.461345 Device /sys/class/net/enxf4f5e850de0a found
10833 11:14:05.464416 done.
10834 11:14:05.520257 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10835 11:14:05.553795 <4>[ 16.045792] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10836 11:14:05.672878 <4>[ 16.165283] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10837 11:14:05.789146 <4>[ 16.281263] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10838 11:14:05.904630 <4>[ 16.397138] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10839 11:14:06.020435 <4>[ 16.513093] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10840 11:14:06.136703 <4>[ 16.629193] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10841 11:14:06.252494 <4>[ 16.745017] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10842 11:14:06.368306 <4>[ 16.861027] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10843 11:14:06.484178 <4>[ 16.976905] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10844 11:14:06.591377 <3>[ 17.090886] mt7921e 0000:01:00.0: hardware init failed
10845 11:14:06.636628 IP-Config: no response after 2 secs - giving up
10846 11:14:06.640192 <6>[ 17.140121] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10847 11:14:06.687116 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10848 11:14:07.790658 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10849 11:14:07.797315 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10850 11:14:07.804110 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10851 11:14:07.810271 host : mt8192-asurada-spherion-r0-cbg-9
10852 11:14:07.817644 domain : lava-rack
10853 11:14:07.823821 rootserver: 192.168.201.1 rootpath:
10854 11:14:07.824413 filename :
10855 11:14:07.886900 done.
10856 11:14:07.894422 Begin: Running /scripts/nfs-bottom ... done.
10857 11:14:07.911799 Begin: Running /scripts/init-bottom ... done.
10858 11:14:08.998674 <6>[ 19.498471] NET: Registered PF_INET6 protocol family
10859 11:14:09.005532 <6>[ 19.505179] Segment Routing with IPv6
10860 11:14:09.008475 <6>[ 19.509140] In-situ OAM (IOAM) with IPv6
10861 11:14:09.118685 <30>[ 19.598435] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10862 11:14:09.122219 <30>[ 19.622216] systemd[1]: Detected architecture arm64.
10863 11:14:09.142445
10864 11:14:09.145846 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10865 11:14:09.146280
10866 11:14:09.166230 <30>[ 19.666042] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10867 11:14:09.668302 <30>[ 20.164793] systemd[1]: Queued start job for default target Graphical Interface.
10868 11:14:09.688671 <30>[ 20.188722] systemd[1]: Created slice system-getty.slice.
10869 11:14:09.695782 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10870 11:14:09.712646 <30>[ 20.212327] systemd[1]: Created slice system-modprobe.slice.
10871 11:14:09.719731 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10872 11:14:09.737312 <30>[ 20.237072] systemd[1]: Created slice system-serial\x2dgetty.slice.
10873 11:14:09.747468 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10874 11:14:09.764273 <30>[ 20.264288] systemd[1]: Created slice User and Session Slice.
10875 11:14:09.770698 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10876 11:14:09.791595 <30>[ 20.288293] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10877 11:14:09.801458 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10878 11:14:09.819437 <30>[ 20.316021] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10879 11:14:09.826113 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10880 11:14:09.847160 <30>[ 20.339819] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10881 11:14:09.853682 <30>[ 20.351872] systemd[1]: Reached target Local Encrypted Volumes.
10882 11:14:09.860131 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10883 11:14:09.876439 <30>[ 20.375861] systemd[1]: Reached target Paths.
10884 11:14:09.879380 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10885 11:14:09.896394 <30>[ 20.395792] systemd[1]: Reached target Remote File Systems.
10886 11:14:09.903012 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10887 11:14:09.920104 <30>[ 20.420008] systemd[1]: Reached target Slices.
10888 11:14:09.926925 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10889 11:14:09.940501 <30>[ 20.439806] systemd[1]: Reached target Swap.
10890 11:14:09.943341 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10891 11:14:09.963468 <30>[ 20.460111] systemd[1]: Listening on initctl Compatibility Named Pipe.
10892 11:14:09.970210 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10893 11:14:09.976481 <30>[ 20.475334] systemd[1]: Listening on Journal Audit Socket.
10894 11:14:09.983370 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10895 11:14:09.996884 <30>[ 20.496567] systemd[1]: Listening on Journal Socket (/dev/log).
10896 11:14:10.003129 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10897 11:14:10.020717 <30>[ 20.520559] systemd[1]: Listening on Journal Socket.
10898 11:14:10.027178 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10899 11:14:10.044672 <30>[ 20.540909] systemd[1]: Listening on Network Service Netlink Socket.
10900 11:14:10.050978 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10901 11:14:10.066089 <30>[ 20.565703] systemd[1]: Listening on udev Control Socket.
10902 11:14:10.072070 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10903 11:14:10.088349 <30>[ 20.588032] systemd[1]: Listening on udev Kernel Socket.
10904 11:14:10.094885 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10905 11:14:10.144227 <30>[ 20.644135] systemd[1]: Mounting Huge Pages File System...
10906 11:14:10.150675 Mounting [0;1;39mHuge Pages File System[0m...
10907 11:14:10.166325 <30>[ 20.666404] systemd[1]: Mounting POSIX Message Queue File System...
10908 11:14:10.173304 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10909 11:14:10.190266 <30>[ 20.690251] systemd[1]: Mounting Kernel Debug File System...
10910 11:14:10.196810 Mounting [0;1;39mKernel Debug File System[0m...
10911 11:14:10.215223 <30>[ 20.712005] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10912 11:14:10.238063 <30>[ 20.734984] systemd[1]: Starting Create list of static device nodes for the current kernel...
10913 11:14:10.244929 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10914 11:14:10.262403 <30>[ 20.762417] systemd[1]: Starting Load Kernel Module configfs...
10915 11:14:10.269054 Starting [0;1;39mLoad Kernel Module configfs[0m...
10916 11:14:10.286153 <30>[ 20.786048] systemd[1]: Starting Load Kernel Module drm...
10917 11:14:10.292865 Starting [0;1;39mLoad Kernel Module drm[0m...
10918 11:14:10.310211 <30>[ 20.810163] systemd[1]: Starting Load Kernel Module fuse...
10919 11:14:10.316576 Starting [0;1;39mLoad Kernel Module fuse[0m...
10920 11:14:10.342436 <6>[ 20.842145] fuse: init (API version 7.37)
10921 11:14:10.352183 <30>[ 20.842379] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10922 11:14:10.392448 <30>[ 20.892273] systemd[1]: Starting Journal Service...
10923 11:14:10.395558 Starting [0;1;39mJournal Service[0m...
10924 11:14:10.419012 <30>[ 20.918502] systemd[1]: Starting Load Kernel Modules...
10925 11:14:10.425306 Starting [0;1;39mLoad Kernel Modules[0m...
10926 11:14:10.446035 <30>[ 20.942687] systemd[1]: Starting Remount Root and Kernel File Systems...
10927 11:14:10.452239 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10928 11:14:10.471214 <30>[ 20.970970] systemd[1]: Starting Coldplug All udev Devices...
10929 11:14:10.477367 Starting [0;1;39mColdplug All udev Devices[0m...
10930 11:14:10.495018 <30>[ 20.995307] systemd[1]: Mounted Huge Pages File System.
10931 11:14:10.502084 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10932 11:14:10.516125 <30>[ 21.016225] systemd[1]: Mounted POSIX Message Queue File System.
10933 11:14:10.522574 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10934 11:14:10.540799 <30>[ 21.040277] systemd[1]: Mounted Kernel Debug File System.
10935 11:14:10.554297 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0<3>[ 21.051139] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 11:14:10.557216 m.
10937 11:14:10.576056 <30>[ 21.072631] systemd[1]: Finished Create list of static device nodes for the current kernel.
10938 11:14:10.589955 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes<3>[ 21.086311] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 11:14:10.593391 for the current kernel[0m.
10940 11:14:10.608768 <30>[ 21.108809] systemd[1]: modprobe@configfs.service: Succeeded.
10941 11:14:10.615355 <30>[ 21.115535] systemd[1]: Finished Load Kernel Module configfs.
10942 11:14:10.622469 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10943 11:14:10.640111 <3>[ 21.136477] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 11:14:10.646584 <30>[ 21.136935] systemd[1]: modprobe@drm.service: Succeeded.
10945 11:14:10.653036 <30>[ 21.151749] systemd[1]: Finished Load Kernel Module drm.
10946 11:14:10.659674 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10947 11:14:10.673892 <3>[ 21.170839] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 11:14:10.681302 <30>[ 21.180902] systemd[1]: modprobe@fuse.service: Succeeded.
10949 11:14:10.687357 <30>[ 21.187343] systemd[1]: Finished Load Kernel Module fuse.
10950 11:14:10.694640 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10951 11:14:10.704871 <3>[ 21.201366] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 11:14:10.711626 <30>[ 21.211836] systemd[1]: Finished Load Kernel Modules.
10953 11:14:10.718562 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10954 11:14:10.740439 <3>[ 21.236779] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 11:14:10.747125 <30>[ 21.237084] systemd[1]: Finished Remount Root and Kernel File Systems.
10956 11:14:10.753578 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10957 11:14:10.776092 <3>[ 21.272061] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 11:14:10.804119 <30>[ 21.303338] systemd[1]: Mounting FUSE Control File System...
10959 11:14:10.813829 <3>[ 21.305112] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 11:14:10.820193 Mounting [0;1;39mFUSE Control File System[0m...
10961 11:14:10.834558 <30>[ 21.334280] systemd[1]: Mounting Kernel Configuration File System...
10962 11:14:10.848138 Mountin<3>[ 21.342387] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 11:14:10.851825 g [0;1;39mKernel Configuration File System[0m...
10964 11:14:10.877268 <30>[ 21.373752] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10965 11:14:10.887535 <3>[ 21.375213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 11:14:10.897317 <30>[ 21.382805] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10967 11:14:10.932818 <30>[ 21.432570] systemd[1]: Starting Load/Save Random Seed...
10968 11:14:10.939759 Starting [0;1;39mLoad/Save Random Seed[0m...
10969 11:14:10.959671 <30>[ 21.458867] systemd[1]: Starting Apply Kernel Variables...
10970 11:14:10.966675 Starting [0;1;39mApply Kernel Variables[0m...
10971 11:14:10.983964 <30>[ 21.483535] systemd[1]: Starting Create System Users...
10972 11:14:10.990588 Starting [0;1;39mCreate System Users[0m...
10973 11:14:11.006250 <30>[ 21.505236] systemd[1]: Started Journal Service.
10974 11:14:11.022740 [[0;32m OK [0m] Started [0;<4>[ 21.512151] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10975 11:14:11.032417 1;39mJournal Ser<3>[ 21.528855] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10976 11:14:11.035352 vice[0m.
10977 11:14:11.050390 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10978 11:14:11.069001 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10979 11:14:11.080612 See 'systemctl status systemd-udev-trigger.service' for details.
10980 11:14:11.096924 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10981 11:14:11.113523 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10982 11:14:11.128880 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10983 11:14:11.145114 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10984 11:14:11.184991 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10985 11:14:11.202655 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10986 11:14:11.238295 <46>[ 21.734635] systemd-journald[296]: Received client request to flush runtime journal.
10987 11:14:11.275670 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10988 11:14:11.288978 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10989 11:14:11.304253 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10990 11:14:11.360005 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10991 11:14:12.627453 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10992 11:14:12.672700 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10993 11:14:12.694024 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10994 11:14:12.715138 Starting [0;1;39mNetwork Service[0m...
10995 11:14:13.022086 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10996 11:14:13.060096 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10997 11:14:13.081618 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10998 11:14:13.277208 <6>[ 23.777756] remoteproc remoteproc0: powering up scp
10999 11:14:13.290274 <4>[ 23.787127] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11000 11:14:13.297047 <3>[ 23.797009] remoteproc remoteproc0: request_firmware failed: -2
11001 11:14:13.306377 <3>[ 23.803189] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11002 11:14:13.391154 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11003 11:14:13.411380 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11004 11:14:13.428955 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11005 11:14:13.448626 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11006 11:14:13.463689 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11007 11:14:13.528279 Starting [0;1;39mNetwork Name Resolution[0m...
11008 11:14:13.546670 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11009 11:14:13.576334 Starting [0;1;39mNetwork Time Synchronization[0m...
11010 11:14:13.594222 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11011 11:14:13.616552 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11012 11:14:13.646981 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11013 11:14:14.005161 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11014 11:14:14.020032 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11015 11:14:14.038948 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11016 11:14:14.055329 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11017 11:14:14.071382 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11018 11:14:14.095256 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11019 11:14:14.120828 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11020 11:14:14.144619 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11021 11:14:14.164338 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11022 11:14:14.175434 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11023 11:14:14.196209 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11024 11:14:14.206975 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11025 11:14:14.223451 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11026 11:14:14.275689 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11027 11:14:14.375333 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11028 11:14:14.411479 Starting [0;1;39mUser Login Management[0m...
11029 11:14:14.433215 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11030 11:14:14.452580 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11031 11:14:14.474681 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11032 11:14:14.519757 Starting [0;1;39mPermit User Sessions[0m...
11033 11:14:14.609213 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11034 11:14:14.661816 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11035 11:14:14.703078 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11036 11:14:14.709948 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11037 11:14:14.732798 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11038 11:14:14.755040 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11039 11:14:14.779016 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11040 11:14:14.799240 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11041 11:14:14.845153 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11042 11:14:14.876133 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11043 11:14:14.970363
11044 11:14:14.970514
11045 11:14:14.973247 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11046 11:14:14.973344
11047 11:14:14.976910 debian-bullseye-arm64 login: root (automatic login)
11048 11:14:14.976996
11049 11:14:14.977062
11050 11:14:15.210773 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023 aarch64
11051 11:14:15.210926
11052 11:14:15.217777 The programs included with the Debian GNU/Linux system are free software;
11053 11:14:15.224333 the exact distribution terms for each program are described in the
11054 11:14:15.227220 individual files in /usr/share/doc/*/copyright.
11055 11:14:15.227305
11056 11:14:15.233933 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11057 11:14:15.237112 permitted by applicable law.
11058 11:14:15.268104 Matched prompt #10: / #
11060 11:14:15.268383 Setting prompt string to ['/ #']
11061 11:14:15.268479 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11063 11:14:15.268714 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11064 11:14:15.268802 start: 2.2.6 expect-shell-connection (timeout 00:03:40) [common]
11065 11:14:15.268873 Setting prompt string to ['/ #']
11066 11:14:15.268933 Forcing a shell prompt, looking for ['/ #']
11068 11:14:15.319163 / #
11069 11:14:15.319337 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11070 11:14:15.319460 Waiting using forced prompt support (timeout 00:02:30)
11071 11:14:15.324042
11072 11:14:15.324326 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11073 11:14:15.324421 start: 2.2.7 export-device-env (timeout 00:03:40) [common]
11075 11:14:15.424850 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591227/extract-nfsrootfs-_ng094gw'
11076 11:14:15.429857 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591227/extract-nfsrootfs-_ng094gw'
11078 11:14:15.530388 / # export NFS_SERVER_IP='192.168.201.1'
11079 11:14:15.535165 export NFS_SERVER_IP='192.168.201.1'
11080 11:14:15.535467 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11081 11:14:15.535562 end: 2.2 depthcharge-retry (duration 00:01:20) [common]
11082 11:14:15.535648 end: 2 depthcharge-action (duration 00:01:20) [common]
11083 11:14:15.535739 start: 3 lava-test-retry (timeout 00:01:00) [common]
11084 11:14:15.535826 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11085 11:14:15.535900 Using namespace: common
11087 11:14:15.636230 / # #
11088 11:14:15.636409 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11089 11:14:15.642045 #
11090 11:14:15.642305 Using /lava-10591227
11092 11:14:15.742753 / # export SHELL=/bin/sh
11093 11:14:15.747799 export SHELL=/bin/sh
11095 11:14:15.848333 / # . /lava-10591227/environment
11096 11:14:15.853526 . /lava-10591227/environment
11098 11:14:15.958736 / # /lava-10591227/bin/lava-test-runner /lava-10591227/0
11099 11:14:15.958896 Test shell timeout: 10s (minimum of the action and connection timeout)
11100 11:14:15.963494 /lava-10591227/bin/lava-test-runner /lava-10591227/0
11101 11:14:16.141999 + export TESTRUN_ID=0_dmesg
11102 11:14:16.145924 + cd /lava-10591227/0/tests/0_dmesg
11103 11:14:16.148728 + cat uuid
11104 11:14:16.155402 + UUID=10591227_<8>[ 26.654291] <LAVA_SIGNAL_STARTRUN 0_dmesg 10591227_1.6.2.3.1>
11105 11:14:16.155659 Received signal: <STARTRUN> 0_dmesg 10591227_1.6.2.3.1
11106 11:14:16.155752 Starting test lava.0_dmesg (10591227_1.6.2.3.1)
11107 11:14:16.155843 Skipping test definition patterns.
11108 11:14:16.158421 1.6.2.3.1
11109 11:14:16.158510 + set +x
11110 11:14:16.161992 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11111 11:14:16.233769 <8>[ 26.730952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11112 11:14:16.234092 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11114 11:14:16.286109 <8>[ 26.783264] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11115 11:14:16.286399 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11117 11:14:16.347946 <8>[ 26.844884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11118 11:14:16.348623 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11120 11:14:16.351379 + set +x
11121 11:14:16.354836 <8>[ 26.854302] <LAVA_SIGNAL_ENDRUN 0_dmesg 10591227_1.6.2.3.1>
11122 11:14:16.355507 Received signal: <ENDRUN> 0_dmesg 10591227_1.6.2.3.1
11123 11:14:16.355917 Ending use of test pattern.
11124 11:14:16.356237 Ending test lava.0_dmesg (10591227_1.6.2.3.1), duration 0.20
11126 11:14:16.359780 <LAVA_TEST_RUNNER EXIT>
11127 11:14:16.360443 ok: lava_test_shell seems to have completed
11128 11:14:16.360999 alert: pass
crit: pass
emerg: pass
11129 11:14:16.361409 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11130 11:14:16.361823 end: 3 lava-test-retry (duration 00:00:01) [common]
11131 11:14:16.362235 start: 4 lava-test-retry (timeout 00:01:00) [common]
11132 11:14:16.362642 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11133 11:14:16.362968 Using namespace: common
11135 11:14:16.463946 / # #
11136 11:14:16.464472 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11137 11:14:16.465059 Using /lava-10591227
11139 11:14:16.566057 export SHELL=/bin/sh
11140 11:14:16.566717 #
11142 11:14:16.667976 / # export SHELL=/bin/sh. /lava-10591227/environment
11143 11:14:16.668690
11145 11:14:16.770115 / # . /lava-10591227/environment/lava-10591227/bin/lava-test-runner /lava-10591227/1
11146 11:14:16.770638 Test shell timeout: 10s (minimum of the action and connection timeout)
11147 11:14:16.771158
11148 11:14:16.776803 / # /lava-10591227/bin/lava-test-runner /lava-10591227/1
11149 11:14:16.874959 + export TESTRUN_ID=1_bootrr
11150 11:14:16.878359 + cd /lava-10591227/1/tests/1_bootrr
11151 11:14:16.881716 + cat uuid
11152 11:14:16.893263 + UUID=10591227_1.<8>[ 27.390206] <LAVA_SIGNAL_STARTRUN 1_bootrr 10591227_1.6.2.3.5>
11153 11:14:16.893956 6.2.3.5
11154 11:14:16.894532 + set +x
11155 11:14:16.895330 Received signal: <STARTRUN> 1_bootrr 10591227_1.6.2.3.5
11156 11:14:16.895850 Starting test lava.1_bootrr (10591227_1.6.2.3.5)
11157 11:14:16.896355 Skipping test definition patterns.
11158 11:14:16.906000 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10591227/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11159 11:14:16.909684 + cd /opt/bootrr/libexec/bootrr
11160 11:14:16.910112 + sh helpers/bootrr-auto
11161 11:14:16.950573 /lava-10591227/1/../bin/lava-test-case
11162 11:14:16.970951 <8>[ 27.468336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11163 11:14:16.971210 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11165 11:14:17.004697 /lava-10591227/1/../bin/lava-test-case
11166 11:14:17.025307 <8>[ 27.522737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11167 11:14:17.025569 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11169 11:14:17.044195 /lava-10591227/1/../bin/lava-test-case
11170 11:14:17.063788 <8>[ 27.561377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11171 11:14:17.064067 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11173 11:14:17.106328 /lava-10591227/1/../bin/lava-test-case
11174 11:14:17.125368 <8>[ 27.622962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11175 11:14:17.125635 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11177 11:14:17.157732 /lava-10591227/1/../bin/lava-test-case
11178 11:14:17.175320 <8>[ 27.672738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11179 11:14:17.175593 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11181 11:14:17.205603 /lava-10591227/1/../bin/lava-test-case
11182 11:14:17.228029 <8>[ 27.724768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11183 11:14:17.228676 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11185 11:14:17.263323 /lava-10591227/1/../bin/lava-test-case
11186 11:14:17.290059 <8>[ 27.786989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11187 11:14:17.290753 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11189 11:14:17.316660 /lava-10591227/1/../bin/lava-test-case
11190 11:14:17.337134 <8>[ 27.834651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11191 11:14:17.337390 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11193 11:14:17.356940 /lava-10591227/1/../bin/lava-test-case
11194 11:14:17.379076 <8>[ 27.876723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11195 11:14:17.379378 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11197 11:14:17.405194 /lava-10591227/1/../bin/lava-test-case
11198 11:14:17.423669 <8>[ 27.921079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11199 11:14:17.423950 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11201 11:14:17.441691 /lava-10591227/1/../bin/lava-test-case
11202 11:14:17.461359 <8>[ 27.958783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11203 11:14:17.461622 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11205 11:14:17.490966 /lava-10591227/1/../bin/lava-test-case
11206 11:14:17.514805 <8>[ 28.012180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11207 11:14:17.515080 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11209 11:14:17.551086 /lava-10591227/1/../bin/lava-test-case
11210 11:14:17.572996 <8>[ 28.070503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11211 11:14:17.573262 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11213 11:14:17.602542 /lava-10591227/1/../bin/lava-test-case
11214 11:14:17.621707 <8>[ 28.119450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11215 11:14:17.621981 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11217 11:14:17.647313 /lava-10591227/1/../bin/lava-test-case
11218 11:14:17.669207 <8>[ 28.166761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11219 11:14:17.669479 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11221 11:14:17.690921 /lava-10591227/1/../bin/lava-test-case
11222 11:14:17.712837 <8>[ 28.209654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11223 11:14:17.713291 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11225 11:14:17.744811 /lava-10591227/1/../bin/lava-test-case
11226 11:14:17.772280 <8>[ 28.269542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11227 11:14:17.773097 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11229 11:14:17.793684 /lava-10591227/1/../bin/lava-test-case
11230 11:14:17.819487 <8>[ 28.316654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11231 11:14:17.820240 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11233 11:14:17.854892 /lava-10591227/1/../bin/lava-test-case
11234 11:14:17.879730 <8>[ 28.377086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11235 11:14:17.880503 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11237 11:14:17.907464 /lava-10591227/1/../bin/lava-test-case
11238 11:14:17.926404 <8>[ 28.424232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11239 11:14:17.926669 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11241 11:14:17.951384 /lava-10591227/1/../bin/lava-test-case
11242 11:14:17.967498 <8>[ 28.464623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11243 11:14:17.967758 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11245 11:14:17.982579 /lava-10591227/1/../bin/lava-test-case
11246 11:14:18.002109 <8>[ 28.499922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11247 11:14:18.002367 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11249 11:14:18.029925 /lava-10591227/1/../bin/lava-test-case
11250 11:14:18.049789 <8>[ 28.547364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11251 11:14:18.050047 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11253 11:14:18.066184 /lava-10591227/1/../bin/lava-test-case
11254 11:14:18.082161 <8>[ 28.579967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11255 11:14:18.082420 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11257 11:14:18.110548 /lava-10591227/1/../bin/lava-test-case
11258 11:14:18.130633 <8>[ 28.628007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11259 11:14:18.130888 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11261 11:14:18.157494 /lava-10591227/1/../bin/lava-test-case
11262 11:14:18.177502 <8>[ 28.675348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11263 11:14:18.177776 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11265 11:14:18.195542 /lava-10591227/1/../bin/lava-test-case
11266 11:14:18.219667 <8>[ 28.717399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11267 11:14:18.219926 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11269 11:14:18.252025 /lava-10591227/1/../bin/lava-test-case
11270 11:14:18.271191 <8>[ 28.769061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11271 11:14:18.271452 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11273 11:14:18.287009 /lava-10591227/1/../bin/lava-test-case
11274 11:14:18.304338 <8>[ 28.801598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11275 11:14:18.304629 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11277 11:14:18.328395 /lava-10591227/1/../bin/lava-test-case
11278 11:14:18.347235 <8>[ 28.844731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11279 11:14:18.347519 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11281 11:14:18.370076 /lava-10591227/1/../bin/lava-test-case
11282 11:14:18.387457 <8>[ 28.885200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11283 11:14:18.387743 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11285 11:14:18.410682 /lava-10591227/1/../bin/lava-test-case
11286 11:14:18.433532 <8>[ 28.931219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11287 11:14:18.433790 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11289 11:14:18.456611 /lava-10591227/1/../bin/lava-test-case
11290 11:14:18.474290 <8>[ 28.971758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11291 11:14:18.474544 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11293 11:14:18.493222 /lava-10591227/1/../bin/lava-test-case
11294 11:14:18.513295 <8>[ 29.010940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11295 11:14:18.513557 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11297 11:14:18.537691 /lava-10591227/1/../bin/lava-test-case
11298 11:14:18.556276 <8>[ 29.054013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11299 11:14:18.556573 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11301 11:14:18.592507 /lava-10591227/1/../bin/lava-test-case
11302 11:14:18.615380 <8>[ 29.113212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11303 11:14:18.615647 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11305 11:14:18.634270 /lava-10591227/1/../bin/lava-test-case
11306 11:14:18.657562 <8>[ 29.155304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11307 11:14:18.657815 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11309 11:14:18.687337 /lava-10591227/1/../bin/lava-test-case
11310 11:14:18.709345 <8>[ 29.207260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11311 11:14:18.709600 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11313 11:14:18.728035 /lava-10591227/1/../bin/lava-test-case
11314 11:14:18.750766 <8>[ 29.248681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11315 11:14:18.751059 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11317 11:14:18.774562 /lava-10591227/1/../bin/lava-test-case
11318 11:14:18.791161 <8>[ 29.289134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11319 11:14:18.791420 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11321 11:14:18.806172 /lava-10591227/1/../bin/lava-test-case
11322 11:14:18.825454 <8>[ 29.323270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11323 11:14:18.825710 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11325 11:14:18.851562 /lava-10591227/1/../bin/lava-test-case
11326 11:14:18.871433 <8>[ 29.369007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11327 11:14:18.871711 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11329 11:14:18.889137 /lava-10591227/1/../bin/lava-test-case
11330 11:14:18.912211 <8>[ 29.410014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11331 11:14:18.912490 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11333 11:14:18.956226 /lava-10591227/1/../bin/lava-test-case
11334 11:14:18.973099 <8>[ 29.470912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11335 11:14:18.973354 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11337 11:14:18.990730 /lava-10591227/1/../bin/lava-test-case
11338 11:14:19.009814 <8>[ 29.507531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11339 11:14:19.010065 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11341 11:14:19.035113 /lava-10591227/1/../bin/lava-test-case
11342 11:14:19.057113 <8>[ 29.554655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11343 11:14:19.057370 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11345 11:14:19.072647 /lava-10591227/1/../bin/lava-test-case
11346 11:14:19.092013 <8>[ 29.590102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11347 11:14:19.092317 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11349 11:14:19.116817 /lava-10591227/1/../bin/lava-test-case
11350 11:14:19.138347 <8>[ 29.635840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11351 11:14:19.138602 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11353 11:14:19.154399 /lava-10591227/1/../bin/lava-test-case
11354 11:14:19.172837 <8>[ 29.670634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11355 11:14:19.173097 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11357 11:14:19.200615 /lava-10591227/1/../bin/lava-test-case
11358 11:14:19.219744 <8>[ 29.717055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11359 11:14:19.220002 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11361 11:14:19.244458 /lava-10591227/1/../bin/lava-test-case
11362 11:14:19.263938 <8>[ 29.761671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11363 11:14:19.264193 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11365 11:14:20.328486 /lava-10591227/1/../bin/lava-test-case
11366 11:14:20.357825 <8>[ 30.855330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11367 11:14:20.358158 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11369 11:14:21.411983 /lava-10591227/1/../bin/lava-test-case
11370 11:14:21.433891 <8>[ 31.931652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11371 11:14:21.434230 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11372 11:14:21.434327 Bad test result: blocked
11373 11:14:21.452989 /lava-10591227/1/../bin/lava-test-case
11374 11:14:21.478162 <8>[ 31.976125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11375 11:14:21.478456 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11377 11:14:21.502206 /lava-10591227/1/../bin/lava-test-case
11378 11:14:21.522454 <8>[ 32.019947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11379 11:14:21.522708 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11381 11:14:21.553150 /lava-10591227/1/../bin/lava-test-case
11382 11:14:21.581290 <8>[ 32.078871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11383 11:14:21.581945 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11385 11:14:21.618563 /lava-10591227/1/../bin/lava-test-case
11386 11:14:21.639971 <8>[ 32.137859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11387 11:14:21.640230 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11389 11:14:21.667227 /lava-10591227/1/../bin/lava-test-case
11390 11:14:21.688965 <8>[ 32.187122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11391 11:14:21.689223 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11393 11:14:21.719974 /lava-10591227/1/../bin/lava-test-case
11394 11:14:21.745303 <8>[ 32.242985] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11395 11:14:21.745802 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11397 11:14:21.779566 /lava-10591227/1/../bin/lava-test-case
11398 11:14:21.802051 <8>[ 32.299534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11399 11:14:21.802737 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11401 11:14:21.833530 /lava-10591227/1/../bin/lava-test-case
11402 11:14:21.856048 <8>[ 32.353741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11403 11:14:21.856725 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11405 11:14:21.885227 /lava-10591227/1/../bin/lava-test-case
11406 11:14:21.906997 <8>[ 32.405053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11407 11:14:21.907267 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11409 11:14:21.923093 /lava-10591227/1/../bin/lava-test-case
11410 11:14:21.941137 <8>[ 32.438855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11411 11:14:21.941397 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11413 11:14:21.964817 /lava-10591227/1/../bin/lava-test-case
11414 11:14:21.984767 <8>[ 32.482316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11415 11:14:21.985041 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11417 11:14:22.000496 /lava-10591227/1/../bin/lava-test-case
11418 11:14:22.020179 <8>[ 32.517838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11419 11:14:22.020454 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11421 11:14:22.047548 /lava-10591227/1/../bin/lava-test-case
11422 11:14:22.074585 <8>[ 32.572346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11423 11:14:22.075361 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11425 11:14:22.104141 /lava-10591227/1/../bin/lava-test-case
11426 11:14:22.129970 <8>[ 32.627736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11427 11:14:22.130816 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11429 11:14:22.170991 /lava-10591227/1/../bin/lava-test-case
11430 11:14:22.201621 <8>[ 32.699438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11431 11:14:22.202518 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11433 11:14:22.235336 /lava-10591227/1/../bin/lava-test-case
11434 11:14:22.260596 <8>[ 32.758623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11435 11:14:22.261311 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11437 11:14:22.289124 /lava-10591227/1/../bin/lava-test-case
11438 11:14:22.313780 <8>[ 32.812043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11439 11:14:22.314088 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11441 11:14:22.344646 /lava-10591227/1/../bin/lava-test-case
11442 11:14:22.363369 <8>[ 32.861053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11443 11:14:22.364200 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11445 11:14:22.391545 /lava-10591227/1/../bin/lava-test-case
11446 11:14:22.416058 <8>[ 32.913826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11447 11:14:22.416945 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11449 11:14:22.457511 /lava-10591227/1/../bin/lava-test-case
11450 11:14:22.489968 <8>[ 32.987967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11451 11:14:22.490351 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11453 11:14:22.520676 /lava-10591227/1/../bin/lava-test-case
11454 11:14:22.548560 <8>[ 33.045984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11455 11:14:22.549235 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11457 11:14:22.584009 /lava-10591227/1/../bin/lava-test-case
11458 11:14:22.614819 <8>[ 33.112352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11459 11:14:22.615608 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11461 11:14:22.646701 /lava-10591227/1/../bin/lava-test-case
11462 11:14:22.670217 <8>[ 33.168142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11463 11:14:22.670900 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11465 11:14:22.701225 /lava-10591227/1/../bin/lava-test-case
11466 11:14:22.730044 <8>[ 33.227513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11467 11:14:22.730744 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11469 11:14:22.760761 /lava-10591227/1/../bin/lava-test-case
11470 11:14:22.792379 <8>[ 33.290322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11471 11:14:22.793116 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11473 11:14:22.824278 /lava-10591227/1/../bin/lava-test-case
11474 11:14:22.852367 <8>[ 33.350203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11475 11:14:22.853091 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11477 11:14:22.878274 /lava-10591227/1/../bin/lava-test-case
11478 11:14:22.899584 <8>[ 33.397287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11479 11:14:22.900284 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11481 11:14:22.930714 /lava-10591227/1/../bin/lava-test-case
11482 11:14:22.961696 <8>[ 33.459186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11483 11:14:22.962466 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11485 11:14:22.990741 /lava-10591227/1/../bin/lava-test-case
11486 11:14:23.010242 <8>[ 33.508617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11487 11:14:23.010505 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11489 11:14:23.027782 /lava-10591227/1/../bin/lava-test-case
11490 11:14:23.051292 <8>[ 33.549367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11491 11:14:23.051571 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11493 11:14:23.082890 /lava-10591227/1/../bin/lava-test-case
11494 11:14:23.102084 <8>[ 33.600313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11495 11:14:23.102391 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11497 11:14:23.117482 /lava-10591227/1/../bin/lava-test-case
11498 11:14:23.134463 <8>[ 33.632567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11499 11:14:23.134770 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11501 11:14:23.164791 /lava-10591227/1/../bin/lava-test-case
11502 11:14:23.188533 <8>[ 33.686476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11503 11:14:23.188807 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11505 11:14:23.206545 /lava-10591227/1/../bin/lava-test-case
11506 11:14:23.232970 <8>[ 33.730917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11507 11:14:23.233509 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11509 11:14:23.266334 /lava-10591227/1/../bin/lava-test-case
11510 11:14:23.294874 <8>[ 33.792832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11511 11:14:23.295631 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11513 11:14:23.316394 /lava-10591227/1/../bin/lava-test-case
11514 11:14:23.344784 <8>[ 33.842536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11515 11:14:23.345592 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11517 11:14:23.377307 /lava-10591227/1/../bin/lava-test-case
11518 11:14:23.398970 <8>[ 33.897168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11519 11:14:23.399243 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11521 11:14:23.426109 /lava-10591227/1/../bin/lava-test-case
11522 11:14:23.443112 <8>[ 33.941571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11523 11:14:23.443378 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11525 11:14:23.467593 /lava-10591227/1/../bin/lava-test-case
11526 11:14:23.485368 <8>[ 33.983491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11527 11:14:23.485641 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11529 11:14:23.499905 /lava-10591227/1/../bin/lava-test-case
11530 11:14:23.519636 <8>[ 34.017798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11531 11:14:23.519904 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11533 11:14:23.546094 /lava-10591227/1/../bin/lava-test-case
11534 11:14:23.564785 <8>[ 34.062726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11535 11:14:23.565066 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11537 11:14:23.592164 /lava-10591227/1/../bin/lava-test-case
11538 11:14:23.612889 <8>[ 34.111511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11539 11:14:23.613184 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11541 11:14:23.631836 /lava-10591227/1/../bin/lava-test-case
11542 11:14:23.653661 <8>[ 34.151734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11543 11:14:23.653939 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11545 11:14:23.683051 /lava-10591227/1/../bin/lava-test-case
11546 11:14:23.704757 <8>[ 34.203347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11547 11:14:23.705052 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11549 11:14:23.732735 /lava-10591227/1/../bin/lava-test-case
11550 11:14:23.752078 <8>[ 34.249856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11551 11:14:23.752360 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11553 11:14:23.775454 /lava-10591227/1/../bin/lava-test-case
11554 11:14:23.795723 <8>[ 34.293642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11555 11:14:23.796007 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11557 11:14:23.813596 /lava-10591227/1/../bin/lava-test-case
11558 11:14:23.835305 <8>[ 34.333038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11559 11:14:23.835586 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11561 11:14:24.882425 /lava-10591227/1/../bin/lava-test-case
11562 11:14:24.909955 <8>[ 35.408090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11563 11:14:24.910279 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11565 11:14:24.927942 /lava-10591227/1/../bin/lava-test-case
11566 11:14:24.947188 <8>[ 35.445535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11567 11:14:24.947483 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11569 11:14:25.992719 /lava-10591227/1/../bin/lava-test-case
11570 11:14:26.023682 <8>[ 36.521794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11571 11:14:26.024391 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11573 11:14:26.043117 /lava-10591227/1/../bin/lava-test-case
11574 11:14:26.067218 <8>[ 36.565173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11575 11:14:26.067983 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11577 11:14:27.119359 /lava-10591227/1/../bin/lava-test-case
11578 11:14:27.144984 <8>[ 37.643206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11579 11:14:27.145684 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11581 11:14:27.166176 /lava-10591227/1/../bin/lava-test-case
11582 11:14:27.190011 <8>[ 37.688423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11583 11:14:27.190756 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11585 11:14:28.242655 /lava-10591227/1/../bin/lava-test-case
11586 11:14:28.264525 <8>[ 38.763643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11587 11:14:28.264816 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11589 11:14:28.283296 /lava-10591227/1/../bin/lava-test-case
11590 11:14:28.301589 <8>[ 38.799989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11591 11:14:28.301850 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11593 11:14:29.341045 /lava-10591227/1/../bin/lava-test-case
11594 11:14:29.362553 <8>[ 39.861173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11595 11:14:29.363242 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11597 11:14:29.381551 /lava-10591227/1/../bin/lava-test-case
11598 11:14:29.406137 <8>[ 39.904603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11599 11:14:29.406847 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11601 11:14:30.455593 /lava-10591227/1/../bin/lava-test-case
11602 11:14:30.477579 <8>[ 40.976307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11603 11:14:30.477851 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11605 11:14:30.498681 /lava-10591227/1/../bin/lava-test-case
11606 11:14:30.524471 <8>[ 41.022979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11607 11:14:30.525200 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11609 11:14:31.569314 /lava-10591227/1/../bin/lava-test-case
11610 11:14:31.600589 <8>[ 42.099051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11611 11:14:31.601295 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11613 11:14:31.619573 /lava-10591227/1/../bin/lava-test-case
11614 11:14:31.647411 <8>[ 42.146432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11615 11:14:31.648118 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11617 11:14:31.665549 /lava-10591227/1/../bin/lava-test-case
11618 11:14:31.685927 <8>[ 42.184365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11619 11:14:31.686612 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11621 11:14:32.741529 /lava-10591227/1/../bin/lava-test-case
11622 11:14:32.772663 <8>[ 43.271037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11623 11:14:32.773379 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11625 11:14:32.793518 /lava-10591227/1/../bin/lava-test-case
11626 11:14:32.817732 <8>[ 43.316832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11627 11:14:32.818426 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11629 11:14:32.847643 /lava-10591227/1/../bin/lava-test-case
11630 11:14:32.875709 <8>[ 43.374747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11631 11:14:32.876445 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11633 11:14:32.894691 /lava-10591227/1/../bin/lava-test-case
11634 11:14:32.912398 <8>[ 43.411359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11635 11:14:32.912705 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11637 11:14:32.939772 /lava-10591227/1/../bin/lava-test-case
11638 11:14:32.959135 <8>[ 43.458038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11639 11:14:32.959403 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11641 11:14:32.982579 /lava-10591227/1/../bin/lava-test-case
11642 11:14:33.004164 <8>[ 43.503356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11643 11:14:33.004419 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11645 11:14:33.030884 /lava-10591227/1/../bin/lava-test-case
11646 11:14:33.051083 <8>[ 43.550349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11647 11:14:33.051352 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11649 11:14:33.076279 /lava-10591227/1/../bin/lava-test-case
11650 11:14:33.099137 <8>[ 43.598034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11651 11:14:33.099819 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11653 11:14:33.129993 /lava-10591227/1/../bin/lava-test-case
11654 11:14:33.150898 <8>[ 43.649892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11655 11:14:33.151657 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11657 11:14:33.182364 /lava-10591227/1/../bin/lava-test-case
11658 11:14:33.206045 <8>[ 43.704790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11659 11:14:33.206914 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11661 11:14:33.225161 /lava-10591227/1/../bin/lava-test-case
11662 11:14:33.245138 <8>[ 43.744086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11663 11:14:33.245433 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11665 11:14:33.269778 /lava-10591227/1/../bin/lava-test-case
11666 11:14:33.290833 <8>[ 43.789912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11667 11:14:33.291105 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11669 11:14:33.306440 /lava-10591227/1/../bin/lava-test-case
11670 11:14:33.323906 <8>[ 43.823228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11671 11:14:33.324160 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11673 11:14:33.353905 /lava-10591227/1/../bin/lava-test-case
11674 11:14:33.371311 <8>[ 43.870465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11675 11:14:33.371601 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11677 11:14:33.387793 /lava-10591227/1/../bin/lava-test-case
11678 11:14:33.404127 <8>[ 43.903443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11679 11:14:33.404383 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11681 11:14:33.428664 /lava-10591227/1/../bin/lava-test-case
11682 11:14:33.448464 <8>[ 43.947874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11683 11:14:33.448759 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11685 11:14:33.464366 /lava-10591227/1/../bin/lava-test-case
11686 11:14:33.481404 <8>[ 43.980638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11687 11:14:33.481670 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11689 11:14:33.509494 /lava-10591227/1/../bin/lava-test-case
11690 11:14:33.528690 <8>[ 44.028013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11691 11:14:33.528949 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11693 11:14:33.546464 /lava-10591227/1/../bin/lava-test-case
11694 11:14:33.564391 <8>[ 44.063477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11695 11:14:33.564679 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11697 11:14:33.586242 /lava-10591227/1/../bin/lava-test-case
11698 11:14:33.603011 <8>[ 44.102701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11699 11:14:33.603273 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11701 11:14:33.620658 /lava-10591227/1/../bin/lava-test-case
11702 11:14:33.639905 <8>[ 44.138967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11703 11:14:33.640181 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11705 11:14:34.684022 /lava-10591227/1/../bin/lava-test-case
11706 11:14:34.711757 <8>[ 45.210628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11707 11:14:34.712645 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11709 11:14:35.760261 /lava-10591227/1/../bin/lava-test-case
11710 11:14:35.792081 <8>[ 46.291301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11711 11:14:35.792981 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11713 11:14:35.813950 /lava-10591227/1/../bin/lava-test-case
11714 11:14:35.844628 <8>[ 46.343828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11715 11:14:35.845330 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11717 11:14:35.872702 /lava-10591227/1/../bin/lava-test-case
11718 11:14:35.891775 <8>[ 46.391144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11719 11:14:35.892044 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11721 11:14:35.912457 /lava-10591227/1/../bin/lava-test-case
11722 11:14:35.933546 <8>[ 46.432627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11723 11:14:35.933819 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11725 11:14:35.966696 /lava-10591227/1/../bin/lava-test-case
11726 11:14:35.992475 <8>[ 46.491578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11727 11:14:35.992771 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11729 11:14:36.010257 /lava-10591227/1/../bin/lava-test-case
11730 11:14:36.013469 <6>[ 46.517238] vpu: disabling
11731 11:14:36.017197 <6>[ 46.520294] vproc2: disabling
11732 11:14:36.020185 <6>[ 46.523564] vproc1: disabling
11733 11:14:36.023696 <6>[ 46.526824] vaud18: disabling
11734 11:14:36.029960 <8>[ 46.528332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11735 11:14:36.030234 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11737 11:14:36.033419 <6>[ 46.530259] vsram_others: disabling
11738 11:14:36.036848 <6>[ 46.541868] va09: disabling
11739 11:14:36.040019 <6>[ 46.544967] vsram_md: disabling
11740 11:14:36.043132 <6>[ 46.548470] Vgpu: disabling
11741 11:14:36.057517 /lava-10591227/1/../bin/lava-test-case
11742 11:14:36.074925 <8>[ 46.574395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11743 11:14:36.075200 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11745 11:14:36.107237 /lava-10591227/1/../bin/lava-test-case
11746 11:14:36.126000 <8>[ 46.625669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11747 11:14:36.126279 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11749 11:14:36.161879 /lava-10591227/1/../bin/lava-test-case
11750 11:14:36.189701 <8>[ 46.689482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11751 11:14:36.190064 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11753 11:14:36.207423 /lava-10591227/1/../bin/lava-test-case
11754 11:14:36.226436 <8>[ 46.725466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11755 11:14:36.227119 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11757 11:14:36.262729 /lava-10591227/1/../bin/lava-test-case
11758 11:14:36.289888 <8>[ 46.789582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11759 11:14:36.290170 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11761 11:14:36.308212 /lava-10591227/1/../bin/lava-test-case
11762 11:14:36.325859 <8>[ 46.825640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11763 11:14:36.326118 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11765 11:14:36.357670 /lava-10591227/1/../bin/lava-test-case
11766 11:14:36.378656 <8>[ 46.877968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11767 11:14:36.378926 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11769 11:14:36.396294 /lava-10591227/1/../bin/lava-test-case
11770 11:14:36.415611 <8>[ 46.915402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11771 11:14:36.415876 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11773 11:14:36.451253 /lava-10591227/1/../bin/lava-test-case
11774 11:14:36.469128 <8>[ 46.968816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11775 11:14:36.469421 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11777 11:14:36.488767 /lava-10591227/1/../bin/lava-test-case
11778 11:14:36.508982 <8>[ 47.008391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11779 11:14:36.509347 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11781 11:14:36.538968 /lava-10591227/1/../bin/lava-test-case
11782 11:14:36.561571 <8>[ 47.060893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11783 11:14:36.562353 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11785 11:14:36.583503 /lava-10591227/1/../bin/lava-test-case
11786 11:14:36.609126 <8>[ 47.108415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11787 11:14:36.610030 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11789 11:14:36.640808 /lava-10591227/1/../bin/lava-test-case
11790 11:14:36.666799 <8>[ 47.166309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11791 11:14:36.667489 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11793 11:14:36.687416 /lava-10591227/1/../bin/lava-test-case
11794 11:14:36.709498 <8>[ 47.209320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11795 11:14:36.709778 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11797 11:14:36.738608 /lava-10591227/1/../bin/lava-test-case
11798 11:14:36.759007 <8>[ 47.258480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11799 11:14:36.759283 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11801 11:14:37.798093 /lava-10591227/1/../bin/lava-test-case
11802 11:14:37.823881 <8>[ 48.323242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11803 11:14:37.824702 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11805 11:14:38.859785 /lava-10591227/1/../bin/lava-test-case
11806 11:14:38.890066 <8>[ 49.389558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11807 11:14:38.890912 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11808 11:14:38.891339 Bad test result: blocked
11809 11:14:38.909111 /lava-10591227/1/../bin/lava-test-case
11810 11:14:38.934499 <8>[ 49.433895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11811 11:14:38.935392 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11813 11:14:39.982088 /lava-10591227/1/../bin/lava-test-case
11814 11:14:40.007539 <8>[ 50.507514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11815 11:14:40.008282 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11817 11:14:40.030334 /lava-10591227/1/../bin/lava-test-case
11818 11:14:40.060703 <8>[ 50.560392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11819 11:14:40.061392 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11821 11:14:40.090296 /lava-10591227/1/../bin/lava-test-case
11822 11:14:40.117968 <8>[ 50.617454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11823 11:14:40.118776 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11825 11:14:40.150454 /lava-10591227/1/../bin/lava-test-case
11826 11:14:40.179428 <8>[ 50.679221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11827 11:14:40.180266 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11829 11:14:40.199065 /lava-10591227/1/../bin/lava-test-case
11830 11:14:40.226733 <8>[ 50.726596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11831 11:14:40.227416 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11833 11:14:40.260951 /lava-10591227/1/../bin/lava-test-case
11834 11:14:40.288544 <8>[ 50.788682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11835 11:14:40.288808 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11837 11:14:40.313417 /lava-10591227/1/../bin/lava-test-case
11838 11:14:40.329570 <8>[ 50.829772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11839 11:14:40.329841 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11841 11:14:41.368638 /lava-10591227/1/../bin/lava-test-case
11842 11:14:41.399418 <8>[ 51.899271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11843 11:14:41.400206 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11845 11:14:41.417637 /lava-10591227/1/../bin/lava-test-case
11846 11:14:41.439071 <8>[ 51.938821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11847 11:14:41.439887 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11849 11:14:42.479659 /lava-10591227/1/../bin/lava-test-case
11850 11:14:42.512892 <8>[ 53.013178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11851 11:14:42.513606 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11853 11:14:42.531820 /lava-10591227/1/../bin/lava-test-case
11854 11:14:42.559648 <8>[ 53.059374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11855 11:14:42.560336 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11857 11:14:43.596793 /lava-10591227/1/../bin/lava-test-case
11858 11:14:43.629970 <8>[ 54.129866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11859 11:14:43.630774 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11861 11:14:43.650953 /lava-10591227/1/../bin/lava-test-case
11862 11:14:43.678382 <8>[ 54.178708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11863 11:14:43.679095 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11865 11:14:44.724802 /lava-10591227/1/../bin/lava-test-case
11866 11:14:44.762025 <8>[ 55.262099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11867 11:14:44.762858 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11869 11:14:44.781342 /lava-10591227/1/../bin/lava-test-case
11870 11:14:44.804535 <8>[ 55.304887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11871 11:14:44.804790 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11873 11:14:44.830518 /lava-10591227/1/../bin/lava-test-case
11874 11:14:44.854658 <8>[ 55.355112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11875 11:14:44.855035 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11877 11:14:44.883967 /lava-10591227/1/../bin/lava-test-case
11878 11:14:44.918721 <8>[ 55.418597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11879 11:14:44.919476 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11881 11:14:44.943881 /lava-10591227/1/../bin/lava-test-case
11882 11:14:44.973525 <8>[ 55.473809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11883 11:14:44.974227 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11885 11:14:45.007065 /lava-10591227/1/../bin/lava-test-case
11886 11:14:45.033142 <8>[ 55.533529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11887 11:14:45.033904 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11889 11:14:45.058332 /lava-10591227/1/../bin/lava-test-case
11890 11:14:45.076004 <8>[ 55.576256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11891 11:14:45.076275 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11893 11:14:45.102991 /lava-10591227/1/../bin/lava-test-case
11894 11:14:45.123061 <8>[ 55.623038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11895 11:14:45.123589 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11897 11:14:45.144309 /lava-10591227/1/../bin/lava-test-case
11898 11:14:45.169839 <8>[ 55.670085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11899 11:14:45.170527 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11901 11:14:46.216671 /lava-10591227/1/../bin/lava-test-case
11902 11:14:46.246737 <8>[ 56.747334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11903 11:14:46.247435 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11905 11:14:46.254846 + <8>[ 56.758733] <LAVA_SIGNAL_ENDRUN 1_bootrr 10591227_1.6.2.3.5>
11906 11:14:46.255528 Received signal: <ENDRUN> 1_bootrr 10591227_1.6.2.3.5
11907 11:14:46.255915 Ending use of test pattern.
11908 11:14:46.256235 Ending test lava.1_bootrr (10591227_1.6.2.3.5), duration 29.36
11910 11:14:46.258463 set +x
11911 11:14:46.261429 <LAVA_TEST_RUNNER EXIT>
11912 11:14:46.262097 ok: lava_test_shell seems to have completed
11913 11:14:46.267272 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11914 11:14:46.267999 end: 4.1 lava-test-shell (duration 00:00:30) [common]
11915 11:14:46.268445 end: 4 lava-test-retry (duration 00:00:30) [common]
11916 11:14:46.268917 start: 5 finalize (timeout 00:07:40) [common]
11917 11:14:46.269365 start: 5.1 power-off (timeout 00:00:30) [common]
11918 11:14:46.270114 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11919 11:14:46.384049 >> Command sent successfully.
11920 11:14:46.386785 Returned 0 in 0 seconds
11921 11:14:46.487521 end: 5.1 power-off (duration 00:00:00) [common]
11923 11:14:46.489139 start: 5.2 read-feedback (timeout 00:07:40) [common]
11924 11:14:46.490618 Listened to connection for namespace 'common' for up to 1s
11925 11:14:47.491014 Finalising connection for namespace 'common'
11926 11:14:47.491276 Disconnecting from shell: Finalise
11927 11:14:47.491420 / #
11928 11:14:47.592188 end: 5.2 read-feedback (duration 00:00:01) [common]
11929 11:14:47.592941 end: 5 finalize (duration 00:00:01) [common]
11930 11:14:47.593527 Cleaning after the job
11931 11:14:47.594027 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/ramdisk
11932 11:14:47.603574 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/kernel
11933 11:14:47.632984 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/dtb
11934 11:14:47.633398 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/nfsrootfs
11935 11:14:47.694643 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591227/tftp-deploy-cv815yyk/modules
11936 11:14:47.700079 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591227
11937 11:14:48.007899 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591227
11938 11:14:48.008084 Job finished correctly