Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 0
1 11:12:01.997428 lava-dispatcher, installed at version: 2023.05.1
2 11:12:01.997646 start: 0 validate
3 11:12:01.997789 Start time: 2023-06-05 11:12:01.997782+00:00 (UTC)
4 11:12:01.997918 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:12:01.998054 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 11:12:02.289761 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:12:02.290079 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:12:02.572064 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:12:02.572272 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:12:22.562789 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:12:22.563017 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:12:23.151958 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:12:23.152185 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:12:23.439979 validate duration: 21.44
16 11:12:23.440364 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:12:23.440510 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:12:23.440642 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:12:23.440813 Not decompressing ramdisk as can be used compressed.
20 11:12:23.440942 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 11:12:23.441051 saving as /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/ramdisk/initrd.cpio.gz
22 11:12:23.441149 total size: 4665601 (4MB)
23 11:12:26.428336 progress 0% (0MB)
24 11:12:26.430104 progress 5% (0MB)
25 11:12:26.431642 progress 10% (0MB)
26 11:12:26.433101 progress 15% (0MB)
27 11:12:26.434409 progress 20% (0MB)
28 11:12:26.435735 progress 25% (1MB)
29 11:12:26.437005 progress 30% (1MB)
30 11:12:26.438299 progress 35% (1MB)
31 11:12:26.439641 progress 40% (1MB)
32 11:12:26.441088 progress 45% (2MB)
33 11:12:26.442427 progress 50% (2MB)
34 11:12:26.443882 progress 55% (2MB)
35 11:12:26.445257 progress 60% (2MB)
36 11:12:26.446788 progress 65% (2MB)
37 11:12:26.448315 progress 70% (3MB)
38 11:12:26.449816 progress 75% (3MB)
39 11:12:26.451518 progress 80% (3MB)
40 11:12:26.453056 progress 85% (3MB)
41 11:12:26.454469 progress 90% (4MB)
42 11:12:26.455789 progress 95% (4MB)
43 11:12:26.457153 progress 100% (4MB)
44 11:12:26.457370 4MB downloaded in 3.02s (1.48MB/s)
45 11:12:26.457610 end: 1.1.1 http-download (duration 00:00:03) [common]
47 11:12:26.458022 end: 1.1 download-retry (duration 00:00:03) [common]
48 11:12:26.458220 start: 1.2 download-retry (timeout 00:09:57) [common]
49 11:12:26.458340 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 11:12:26.458493 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:12:26.458567 saving as /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/kernel/Image
52 11:12:26.458648 total size: 45746688 (43MB)
53 11:12:26.458711 No compression specified
54 11:12:26.460497 progress 0% (0MB)
55 11:12:26.473953 progress 5% (2MB)
56 11:12:26.487124 progress 10% (4MB)
57 11:12:26.500994 progress 15% (6MB)
58 11:12:26.514595 progress 20% (8MB)
59 11:12:26.528360 progress 25% (10MB)
60 11:12:26.542014 progress 30% (13MB)
61 11:12:26.554946 progress 35% (15MB)
62 11:12:26.567748 progress 40% (17MB)
63 11:12:26.580561 progress 45% (19MB)
64 11:12:26.592653 progress 50% (21MB)
65 11:12:26.604773 progress 55% (24MB)
66 11:12:26.616667 progress 60% (26MB)
67 11:12:26.628797 progress 65% (28MB)
68 11:12:26.640807 progress 70% (30MB)
69 11:12:26.653333 progress 75% (32MB)
70 11:12:26.665587 progress 80% (34MB)
71 11:12:26.677645 progress 85% (37MB)
72 11:12:26.689606 progress 90% (39MB)
73 11:12:26.701863 progress 95% (41MB)
74 11:12:26.713818 progress 100% (43MB)
75 11:12:26.714007 43MB downloaded in 0.26s (170.85MB/s)
76 11:12:26.714169 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:12:26.714413 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:12:26.714506 start: 1.3 download-retry (timeout 00:09:57) [common]
80 11:12:26.714596 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 11:12:26.714730 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:12:26.714802 saving as /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/dtb/mt8192-asurada-spherion-r0.dtb
83 11:12:26.714865 total size: 46924 (0MB)
84 11:12:26.714926 No compression specified
85 11:12:26.716031 progress 69% (0MB)
86 11:12:26.716308 progress 100% (0MB)
87 11:12:26.716463 0MB downloaded in 0.00s (28.05MB/s)
88 11:12:26.716585 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:12:26.716817 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:12:26.716906 start: 1.4 download-retry (timeout 00:09:57) [common]
92 11:12:26.716990 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 11:12:26.717100 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 11:12:26.717170 saving as /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/nfsrootfs/full.rootfs.tar
95 11:12:26.717233 total size: 200770336 (191MB)
96 11:12:26.717295 Using unxz to decompress xz
97 11:12:26.721294 progress 0% (0MB)
98 11:12:27.288862 progress 5% (9MB)
99 11:12:27.828312 progress 10% (19MB)
100 11:12:28.452940 progress 15% (28MB)
101 11:12:28.842443 progress 20% (38MB)
102 11:12:29.176601 progress 25% (47MB)
103 11:12:29.800563 progress 30% (57MB)
104 11:12:30.372589 progress 35% (67MB)
105 11:12:30.987051 progress 40% (76MB)
106 11:12:31.576532 progress 45% (86MB)
107 11:12:32.181082 progress 50% (95MB)
108 11:12:32.842169 progress 55% (105MB)
109 11:12:33.529801 progress 60% (114MB)
110 11:12:33.653220 progress 65% (124MB)
111 11:12:33.801171 progress 70% (134MB)
112 11:12:33.899996 progress 75% (143MB)
113 11:12:33.974597 progress 80% (153MB)
114 11:12:34.043019 progress 85% (162MB)
115 11:12:34.149528 progress 90% (172MB)
116 11:12:34.438914 progress 95% (181MB)
117 11:12:35.032679 progress 100% (191MB)
118 11:12:35.037755 191MB downloaded in 8.32s (23.01MB/s)
119 11:12:35.038100 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:12:35.038407 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:12:35.038498 start: 1.5 download-retry (timeout 00:09:48) [common]
123 11:12:35.038613 start: 1.5.1 http-download (timeout 00:09:48) [common]
124 11:12:35.038765 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:12:35.038849 saving as /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/modules/modules.tar
126 11:12:35.038911 total size: 8547328 (8MB)
127 11:12:35.039000 Using unxz to decompress xz
128 11:12:35.334712 progress 0% (0MB)
129 11:12:35.357871 progress 5% (0MB)
130 11:12:35.384446 progress 10% (0MB)
131 11:12:35.412076 progress 15% (1MB)
132 11:12:35.438234 progress 20% (1MB)
133 11:12:35.465501 progress 25% (2MB)
134 11:12:35.491864 progress 30% (2MB)
135 11:12:35.518539 progress 35% (2MB)
136 11:12:35.544831 progress 40% (3MB)
137 11:12:35.571707 progress 45% (3MB)
138 11:12:35.597216 progress 50% (4MB)
139 11:12:35.620694 progress 55% (4MB)
140 11:12:35.646869 progress 60% (4MB)
141 11:12:35.672739 progress 65% (5MB)
142 11:12:35.698845 progress 70% (5MB)
143 11:12:35.726299 progress 75% (6MB)
144 11:12:35.756228 progress 80% (6MB)
145 11:12:35.779218 progress 85% (6MB)
146 11:12:35.804666 progress 90% (7MB)
147 11:12:35.828622 progress 95% (7MB)
148 11:12:35.852992 progress 100% (8MB)
149 11:12:35.859103 8MB downloaded in 0.82s (9.94MB/s)
150 11:12:35.859469 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:12:35.859761 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:12:35.859867 start: 1.6 prepare-tftp-overlay (timeout 00:09:48) [common]
154 11:12:35.859971 start: 1.6.1 extract-nfsrootfs (timeout 00:09:48) [common]
155 11:12:39.563113 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10591219/extract-nfsrootfs-1v2va2w7
156 11:12:39.563300 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:12:39.563568 start: 1.6.2 lava-overlay (timeout 00:09:44) [common]
158 11:12:39.563768 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu
159 11:12:39.563901 makedir: /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin
160 11:12:39.564001 makedir: /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/tests
161 11:12:39.564097 makedir: /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/results
162 11:12:39.564200 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-add-keys
163 11:12:39.564341 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-add-sources
164 11:12:39.564465 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-background-process-start
165 11:12:39.564586 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-background-process-stop
166 11:12:39.564705 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-common-functions
167 11:12:39.564824 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-echo-ipv4
168 11:12:39.564941 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-install-packages
169 11:12:39.565057 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-installed-packages
170 11:12:39.565177 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-os-build
171 11:12:39.565293 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-probe-channel
172 11:12:39.565409 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-probe-ip
173 11:12:39.565529 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-target-ip
174 11:12:39.565645 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-target-mac
175 11:12:39.565761 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-target-storage
176 11:12:39.565879 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-test-case
177 11:12:39.565998 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-test-event
178 11:12:39.566114 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-test-feedback
179 11:12:39.566230 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-test-raise
180 11:12:39.566347 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-test-reference
181 11:12:39.566464 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-test-runner
182 11:12:39.566582 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-test-set
183 11:12:39.566697 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-test-shell
184 11:12:39.566817 Updating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-add-keys (debian)
185 11:12:39.566956 Updating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-add-sources (debian)
186 11:12:39.567092 Updating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-install-packages (debian)
187 11:12:39.567227 Updating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-installed-packages (debian)
188 11:12:39.567404 Updating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/bin/lava-os-build (debian)
189 11:12:39.567523 Creating /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/environment
190 11:12:39.567619 LAVA metadata
191 11:12:39.567686 - LAVA_JOB_ID=10591219
192 11:12:39.567748 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:12:39.567845 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:44) [common]
194 11:12:39.567912 skipped lava-vland-overlay
195 11:12:39.567985 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:12:39.568068 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:44) [common]
197 11:12:39.568128 skipped lava-multinode-overlay
198 11:12:39.568200 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:12:39.568277 start: 1.6.2.3 test-definition (timeout 00:09:44) [common]
200 11:12:39.568350 Loading test definitions
201 11:12:39.568440 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:44) [common]
202 11:12:39.568510 Using /lava-10591219 at stage 0
203 11:12:39.568793 uuid=10591219_1.6.2.3.1 testdef=None
204 11:12:39.568879 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:12:39.568962 start: 1.6.2.3.2 test-overlay (timeout 00:09:44) [common]
206 11:12:39.569418 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:12:39.569638 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:44) [common]
209 11:12:39.570167 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:12:39.570398 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:44) [common]
212 11:12:39.570926 runner path: /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/0/tests/0_timesync-off test_uuid 10591219_1.6.2.3.1
213 11:12:39.571082 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:12:39.571302 start: 1.6.2.3.5 git-repo-action (timeout 00:09:44) [common]
216 11:12:39.571600 Using /lava-10591219 at stage 0
217 11:12:39.571711 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:12:39.571790 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/0/tests/1_kselftest-rtc'
219 11:12:42.791811 Running '/usr/bin/git checkout kernelci.org
220 11:12:42.947360 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 11:12:42.948089 uuid=10591219_1.6.2.3.5 testdef=None
222 11:12:42.948263 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 11:12:42.948523 start: 1.6.2.3.6 test-overlay (timeout 00:09:40) [common]
225 11:12:42.949301 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:12:42.949543 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:40) [common]
228 11:12:42.950507 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:12:42.950750 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:40) [common]
231 11:12:42.951691 runner path: /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/0/tests/1_kselftest-rtc test_uuid 10591219_1.6.2.3.5
232 11:12:42.951787 BOARD='mt8192-asurada-spherion-r0'
233 11:12:42.951854 BRANCH='cip'
234 11:12:42.951916 SKIPFILE='/dev/null'
235 11:12:42.951976 SKIP_INSTALL='True'
236 11:12:42.952035 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:12:42.952094 TST_CASENAME=''
238 11:12:42.952151 TST_CMDFILES='rtc'
239 11:12:42.952293 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:12:42.952526 Creating lava-test-runner.conf files
242 11:12:42.952592 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591219/lava-overlay-_id783wu/lava-10591219/0 for stage 0
243 11:12:42.952685 - 0_timesync-off
244 11:12:42.952758 - 1_kselftest-rtc
245 11:12:42.952861 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 11:12:42.952955 start: 1.6.2.4 compress-overlay (timeout 00:09:40) [common]
247 11:12:50.692152 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:12:50.692332 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 11:12:50.692471 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:12:50.692607 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 11:12:50.692734 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 11:12:50.811106 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:12:50.811583 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
254 11:12:50.811758 extracting modules file /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591219/extract-nfsrootfs-1v2va2w7
255 11:12:51.033958 extracting modules file /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591219/extract-overlay-ramdisk-yoeq9f01/ramdisk
256 11:12:51.253250 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:12:51.253430 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 11:12:51.253524 [common] Applying overlay to NFS
259 11:12:51.253595 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591219/compress-overlay-b36u4hyx/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591219/extract-nfsrootfs-1v2va2w7
260 11:12:52.292093 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:12:52.292303 start: 1.6.6 configure-preseed-file (timeout 00:09:31) [common]
262 11:12:52.292410 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:12:52.292507 start: 1.6.7 compress-ramdisk (timeout 00:09:31) [common]
264 11:12:52.292605 Building ramdisk /var/lib/lava/dispatcher/tmp/10591219/extract-overlay-ramdisk-yoeq9f01/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591219/extract-overlay-ramdisk-yoeq9f01/ramdisk
265 11:12:52.568769 >> 117801 blocks
266 11:12:54.601655 rename /var/lib/lava/dispatcher/tmp/10591219/extract-overlay-ramdisk-yoeq9f01/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/ramdisk/ramdisk.cpio.gz
267 11:12:54.602206 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:12:54.602392 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 11:12:54.602541 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 11:12:54.602697 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/kernel/Image'
271 11:13:07.211729 Returned 0 in 12 seconds
272 11:13:07.312332 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/kernel/image.itb
273 11:13:07.636068 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:13:07.636431 output: Created: Mon Jun 5 12:13:07 2023
275 11:13:07.636503 output: Image 0 (kernel-1)
276 11:13:07.636571 output: Description:
277 11:13:07.636636 output: Created: Mon Jun 5 12:13:07 2023
278 11:13:07.636701 output: Type: Kernel Image
279 11:13:07.636763 output: Compression: lzma compressed
280 11:13:07.636822 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
281 11:13:07.636881 output: Architecture: AArch64
282 11:13:07.636939 output: OS: Linux
283 11:13:07.636998 output: Load Address: 0x00000000
284 11:13:07.637057 output: Entry Point: 0x00000000
285 11:13:07.637114 output: Hash algo: crc32
286 11:13:07.637170 output: Hash value: eb1cf9b8
287 11:13:07.637224 output: Image 1 (fdt-1)
288 11:13:07.637278 output: Description: mt8192-asurada-spherion-r0
289 11:13:07.637332 output: Created: Mon Jun 5 12:13:07 2023
290 11:13:07.637386 output: Type: Flat Device Tree
291 11:13:07.637440 output: Compression: uncompressed
292 11:13:07.637494 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 11:13:07.637548 output: Architecture: AArch64
294 11:13:07.637602 output: Hash algo: crc32
295 11:13:07.637656 output: Hash value: 1df858fa
296 11:13:07.637710 output: Image 2 (ramdisk-1)
297 11:13:07.637763 output: Description: unavailable
298 11:13:07.637816 output: Created: Mon Jun 5 12:13:07 2023
299 11:13:07.637870 output: Type: RAMDisk Image
300 11:13:07.637923 output: Compression: Unknown Compression
301 11:13:07.637977 output: Data Size: 17639676 Bytes = 17226.25 KiB = 16.82 MiB
302 11:13:07.638031 output: Architecture: AArch64
303 11:13:07.638085 output: OS: Linux
304 11:13:07.638139 output: Load Address: unavailable
305 11:13:07.638193 output: Entry Point: unavailable
306 11:13:07.638246 output: Hash algo: crc32
307 11:13:07.638299 output: Hash value: 70ca9047
308 11:13:07.638353 output: Default Configuration: 'conf-1'
309 11:13:07.638406 output: Configuration 0 (conf-1)
310 11:13:07.638460 output: Description: mt8192-asurada-spherion-r0
311 11:13:07.638514 output: Kernel: kernel-1
312 11:13:07.638567 output: Init Ramdisk: ramdisk-1
313 11:13:07.638621 output: FDT: fdt-1
314 11:13:07.638674 output: Loadables: kernel-1
315 11:13:07.638728 output:
316 11:13:07.638931 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 11:13:07.639034 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 11:13:07.639137 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 11:13:07.639235 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 11:13:07.639320 No LXC device requested
321 11:13:07.639409 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:13:07.639502 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 11:13:07.639581 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:13:07.639651 Checking files for TFTP limit of 4294967296 bytes.
325 11:13:07.640149 end: 1 tftp-deploy (duration 00:00:44) [common]
326 11:13:07.640258 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:13:07.640351 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:13:07.640482 substitutions:
329 11:13:07.640552 - {DTB}: 10591219/tftp-deploy-nqwh2nxw/dtb/mt8192-asurada-spherion-r0.dtb
330 11:13:07.640621 - {INITRD}: 10591219/tftp-deploy-nqwh2nxw/ramdisk/ramdisk.cpio.gz
331 11:13:07.640682 - {KERNEL}: 10591219/tftp-deploy-nqwh2nxw/kernel/Image
332 11:13:07.640741 - {LAVA_MAC}: None
333 11:13:07.640798 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10591219/extract-nfsrootfs-1v2va2w7
334 11:13:07.640855 - {NFS_SERVER_IP}: 192.168.201.1
335 11:13:07.640911 - {PRESEED_CONFIG}: None
336 11:13:07.640967 - {PRESEED_LOCAL}: None
337 11:13:07.641022 - {RAMDISK}: 10591219/tftp-deploy-nqwh2nxw/ramdisk/ramdisk.cpio.gz
338 11:13:07.641081 - {ROOT_PART}: None
339 11:13:07.641138 - {ROOT}: None
340 11:13:07.641194 - {SERVER_IP}: 192.168.201.1
341 11:13:07.641249 - {TEE}: None
342 11:13:07.641305 Parsed boot commands:
343 11:13:07.641361 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:13:07.641536 Parsed boot commands: tftpboot 192.168.201.1 10591219/tftp-deploy-nqwh2nxw/kernel/image.itb 10591219/tftp-deploy-nqwh2nxw/kernel/cmdline
345 11:13:07.641629 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:13:07.641716 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:13:07.641805 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:13:07.641894 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:13:07.641965 Not connected, no need to disconnect.
350 11:13:07.642063 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:13:07.642150 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:13:07.642219 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
353 11:13:07.645703 Setting prompt string to ['lava-test: # ']
354 11:13:07.646065 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:13:07.646179 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:13:07.646280 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:13:07.646378 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:13:07.646581 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 11:13:12.781955 >> Command sent successfully.
360 11:13:12.784549 Returned 0 in 5 seconds
361 11:13:12.884907 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:13:12.885252 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:13:12.885360 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:13:12.885459 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:13:12.885537 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:13:12.885610 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:13:12.885882 [Enter `^Ec?' for help]
369 11:13:13.057669
370 11:13:13.057817
371 11:13:13.057890 F0: 102B 0000
372 11:13:13.057955
373 11:13:13.058017 F3: 1001 0000 [0200]
374 11:13:13.058077
375 11:13:13.061946 F3: 1001 0000
376 11:13:13.062033
377 11:13:13.062101 F7: 102D 0000
378 11:13:13.062163
379 11:13:13.062224 F1: 0000 0000
380 11:13:13.062288
381 11:13:13.065227 V0: 0000 0000 [0001]
382 11:13:13.065312
383 11:13:13.065380 00: 0007 8000
384 11:13:13.065447
385 11:13:13.069538 01: 0000 0000
386 11:13:13.069625
387 11:13:13.069693 BP: 0C00 0209 [0000]
388 11:13:13.069757
389 11:13:13.072497 G0: 1182 0000
390 11:13:13.072584
391 11:13:13.072654 EC: 0000 0021 [4000]
392 11:13:13.072725
393 11:13:13.076180 S7: 0000 0000 [0000]
394 11:13:13.076262
395 11:13:13.076329 CC: 0000 0000 [0001]
396 11:13:13.076399
397 11:13:13.079769 T0: 0000 0040 [010F]
398 11:13:13.079850
399 11:13:13.079916 Jump to BL
400 11:13:13.079979
401 11:13:13.105024
402 11:13:13.105148
403 11:13:13.105247
404 11:13:13.112312 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:13:13.116321 ARM64: Exception handlers installed.
406 11:13:13.120317 ARM64: Testing exception
407 11:13:13.120428 ARM64: Done test exception
408 11:13:13.127710 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:13:13.139170 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:13:13.145932 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:13:13.155827 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:13:13.162886 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:13:13.169773 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:13:13.181284 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:13:13.188413 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:13:13.208259 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:13:13.211553 WDT: Last reset was cold boot
418 11:13:13.214761 SPI1(PAD0) initialized at 2873684 Hz
419 11:13:13.218074 SPI5(PAD0) initialized at 992727 Hz
420 11:13:13.221504 VBOOT: Loading verstage.
421 11:13:13.228199 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:13:13.231590 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:13:13.234846 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:13:13.237532 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:13:13.245121 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:13:13.251673 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:13:13.262817 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 11:13:13.263372
429 11:13:13.263736
430 11:13:13.273807 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:13:13.276961 ARM64: Exception handlers installed.
432 11:13:13.277401 ARM64: Testing exception
433 11:13:13.280900 ARM64: Done test exception
434 11:13:13.284001 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:13:13.290845 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:13:13.304143 Probing TPM: . done!
437 11:13:13.304587 TPM ready after 0 ms
438 11:13:13.311422 Connected to device vid:did:rid of 1ae0:0028:00
439 11:13:13.317807 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 11:13:13.378281 Initialized TPM device CR50 revision 0
441 11:13:13.389730 tlcl_send_startup: Startup return code is 0
442 11:13:13.390196 TPM: setup succeeded
443 11:13:13.401307 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:13:13.410433 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:13:13.424452 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:13:13.431669 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:13:13.435171 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:13:13.438956 in-header: 03 07 00 00 08 00 00 00
449 11:13:13.442411 in-data: aa e4 47 04 13 02 00 00
450 11:13:13.446607 Chrome EC: UHEPI supported
451 11:13:13.449876 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:13:13.454170 in-header: 03 95 00 00 08 00 00 00
453 11:13:13.458009 in-data: 18 20 20 08 00 00 00 00
454 11:13:13.458510 Phase 1
455 11:13:13.461544 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:13:13.469140 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:13:13.476451 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:13:13.476940 Recovery requested (1009000e)
459 11:13:13.487512 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:13:13.492196 tlcl_extend: response is 0
461 11:13:13.503026 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:13:13.507086 tlcl_extend: response is 0
463 11:13:13.514481 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:13:13.533914 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:13:13.540696 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:13:13.541148
467 11:13:13.541600
468 11:13:13.550669 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:13:13.554172 ARM64: Exception handlers installed.
470 11:13:13.557569 ARM64: Testing exception
471 11:13:13.558091 ARM64: Done test exception
472 11:13:13.579074 pmic_efuse_setting: Set efuses in 11 msecs
473 11:13:13.582569 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:13:13.589224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:13:13.592566 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:13:13.599847 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:13:13.603654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:13:13.607517 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:13:13.614347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:13:13.618638 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:13:13.622310 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:13:13.626329 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:13:13.633929 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:13:13.637167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:13:13.641951 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:13:13.645161 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:13:13.653369 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:13:13.656691 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:13:13.664028 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:13:13.668003 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:13:13.675601 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:13:13.679608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:13:13.686973 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:13:13.690601 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:13:13.697803 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:13:13.701701 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:13:13.709359 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:13:13.712848 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:13:13.720509 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:13:13.723598 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:13:13.727616 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:13:13.734571 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:13:13.738393 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:13:13.742112 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:13:13.749548 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:13:13.752748 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:13:13.760091 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:13:13.764172 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:13:13.767494 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:13:13.775692 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:13:13.778896 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:13:13.782801 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:13:13.786172 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:13:13.790015 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:13:13.797177 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:13:13.801086 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:13:13.805217 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:13:13.808628 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:13:13.811888 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:13:13.816279 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:13:13.823455 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:13:13.826960 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:13:13.830650 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:13:13.835098 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:13:13.842518 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:13:13.849898 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:13:13.853700 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:13:13.864518 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:13:13.872227 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:13:13.875417 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:13:13.882866 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:13:13.886545 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:13:13.894440 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 11:13:13.898316 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:13:13.901903 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:13:13.905238 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:13:13.917092 [RTC]rtc_get_frequency_meter,154: input=15, output=760
538 11:13:13.926132 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 11:13:13.936486 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 11:13:13.946068 [RTC]rtc_get_frequency_meter,154: input=17, output=803
541 11:13:13.954797 [RTC]rtc_get_frequency_meter,154: input=16, output=783
542 11:13:13.964674 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 11:13:13.974881 [RTC]rtc_get_frequency_meter,154: input=17, output=804
544 11:13:13.978501 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 11:13:13.982538 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 11:13:13.985712 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:13:13.993464 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:13:13.997436 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:13:14.001278 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:13:14.001804 ADC[4]: Raw value=906203 ID=7
551 11:13:14.004652 ADC[3]: Raw value=213441 ID=1
552 11:13:14.008598 RAM Code: 0x71
553 11:13:14.012570 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:13:14.015891 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:13:14.023949 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:13:14.031074 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:13:14.034150 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:13:14.038959 in-header: 03 07 00 00 08 00 00 00
559 11:13:14.042054 in-data: aa e4 47 04 13 02 00 00
560 11:13:14.045840 Chrome EC: UHEPI supported
561 11:13:14.052671 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:13:14.056525 in-header: 03 95 00 00 08 00 00 00
563 11:13:14.060269 in-data: 18 20 20 08 00 00 00 00
564 11:13:14.060704 MRC: failed to locate region type 0.
565 11:13:14.068012 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:13:14.071820 DRAM-K: Running full calibration
567 11:13:14.079301 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:13:14.079809 header.status = 0x0
569 11:13:14.082868 header.version = 0x6 (expected: 0x6)
570 11:13:14.086683 header.size = 0xd00 (expected: 0xd00)
571 11:13:14.087174 header.flags = 0x0
572 11:13:14.094040 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:13:14.112705 read SPI 0x72590 0x1c583: 12495 us, 9291 KB/s, 74.328 Mbps
574 11:13:14.119439 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:13:14.123547 dram_init: ddr_geometry: 2
576 11:13:14.124056 [EMI] MDL number = 2
577 11:13:14.126690 [EMI] Get MDL freq = 0
578 11:13:14.127119 dram_init: ddr_type: 0
579 11:13:14.130043 is_discrete_lpddr4: 1
580 11:13:14.134123 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:13:14.134910
582 11:13:14.135560
583 11:13:14.137370 [Bian_co] ETT version 0.0.0.1
584 11:13:14.141714 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:13:14.142290
586 11:13:14.145477 dramc_set_vcore_voltage set vcore to 650000
587 11:13:14.145947 Read voltage for 800, 4
588 11:13:14.149348 Vio18 = 0
589 11:13:14.149659 Vcore = 650000
590 11:13:14.149956 Vdram = 0
591 11:13:14.150197 Vddq = 0
592 11:13:14.153079 Vmddr = 0
593 11:13:14.153314 dram_init: config_dvfs: 1
594 11:13:14.160527 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:13:14.164271 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:13:14.168118 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 11:13:14.171357 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 11:13:14.175269 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 11:13:14.178542 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 11:13:14.181803 MEM_TYPE=3, freq_sel=18
601 11:13:14.185108 sv_algorithm_assistance_LP4_1600
602 11:13:14.188487 ============ PULL DRAM RESETB DOWN ============
603 11:13:14.191723 ========== PULL DRAM RESETB DOWN end =========
604 11:13:14.198911 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:13:14.202716 ===================================
606 11:13:14.202806 LPDDR4 DRAM CONFIGURATION
607 11:13:14.206551 ===================================
608 11:13:14.210565 EX_ROW_EN[0] = 0x0
609 11:13:14.210654 EX_ROW_EN[1] = 0x0
610 11:13:14.213956 LP4Y_EN = 0x0
611 11:13:14.214044 WORK_FSP = 0x0
612 11:13:14.217946 WL = 0x2
613 11:13:14.218038 RL = 0x2
614 11:13:14.218109 BL = 0x2
615 11:13:14.221303 RPST = 0x0
616 11:13:14.221391 RD_PRE = 0x0
617 11:13:14.224635 WR_PRE = 0x1
618 11:13:14.227973 WR_PST = 0x0
619 11:13:14.228070 DBI_WR = 0x0
620 11:13:14.231280 DBI_RD = 0x0
621 11:13:14.231373 OTF = 0x1
622 11:13:14.234528 ===================================
623 11:13:14.237828 ===================================
624 11:13:14.237929 ANA top config
625 11:13:14.241193 ===================================
626 11:13:14.245100 DLL_ASYNC_EN = 0
627 11:13:14.248838 ALL_SLAVE_EN = 1
628 11:13:14.248918 NEW_RANK_MODE = 1
629 11:13:14.252097 DLL_IDLE_MODE = 1
630 11:13:14.255276 LP45_APHY_COMB_EN = 1
631 11:13:14.258524 TX_ODT_DIS = 1
632 11:13:14.262682 NEW_8X_MODE = 1
633 11:13:14.262788 ===================================
634 11:13:14.266088 ===================================
635 11:13:14.269194 data_rate = 1600
636 11:13:14.272951 CKR = 1
637 11:13:14.276008 DQ_P2S_RATIO = 8
638 11:13:14.279360 ===================================
639 11:13:14.283054 CA_P2S_RATIO = 8
640 11:13:14.283209 DQ_CA_OPEN = 0
641 11:13:14.286453 DQ_SEMI_OPEN = 0
642 11:13:14.289816 CA_SEMI_OPEN = 0
643 11:13:14.292986 CA_FULL_RATE = 0
644 11:13:14.296180 DQ_CKDIV4_EN = 1
645 11:13:14.299548 CA_CKDIV4_EN = 1
646 11:13:14.299792 CA_PREDIV_EN = 0
647 11:13:14.302974 PH8_DLY = 0
648 11:13:14.306272 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:13:14.310152 DQ_AAMCK_DIV = 4
650 11:13:14.313356 CA_AAMCK_DIV = 4
651 11:13:14.316787 CA_ADMCK_DIV = 4
652 11:13:14.317223 DQ_TRACK_CA_EN = 0
653 11:13:14.319914 CA_PICK = 800
654 11:13:14.323143 CA_MCKIO = 800
655 11:13:14.327152 MCKIO_SEMI = 0
656 11:13:14.330543 PLL_FREQ = 3068
657 11:13:14.331053 DQ_UI_PI_RATIO = 32
658 11:13:14.335230 CA_UI_PI_RATIO = 0
659 11:13:14.339045 ===================================
660 11:13:14.342262 ===================================
661 11:13:14.346425 memory_type:LPDDR4
662 11:13:14.346961 GP_NUM : 10
663 11:13:14.349823 SRAM_EN : 1
664 11:13:14.350262 MD32_EN : 0
665 11:13:14.353745 ===================================
666 11:13:14.357604 [ANA_INIT] >>>>>>>>>>>>>>
667 11:13:14.358118 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:13:14.361123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:13:14.364193 ===================================
670 11:13:14.367540 data_rate = 1600,PCW = 0X7600
671 11:13:14.370978 ===================================
672 11:13:14.374804 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:13:14.381095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:13:14.384678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:13:14.391613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:13:14.394615 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:13:14.397769 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:13:14.398379 [ANA_INIT] flow start
679 11:13:14.401638 [ANA_INIT] PLL >>>>>>>>
680 11:13:14.404498 [ANA_INIT] PLL <<<<<<<<
681 11:13:14.405098 [ANA_INIT] MIDPI >>>>>>>>
682 11:13:14.407847 [ANA_INIT] MIDPI <<<<<<<<
683 11:13:14.411865 [ANA_INIT] DLL >>>>>>>>
684 11:13:14.412414 [ANA_INIT] flow end
685 11:13:14.418129 ============ LP4 DIFF to SE enter ============
686 11:13:14.421468 ============ LP4 DIFF to SE exit ============
687 11:13:14.424610 [ANA_INIT] <<<<<<<<<<<<<
688 11:13:14.427877 [Flow] Enable top DCM control >>>>>
689 11:13:14.431306 [Flow] Enable top DCM control <<<<<
690 11:13:14.431788 Enable DLL master slave shuffle
691 11:13:14.438497 ==============================================================
692 11:13:14.441692 Gating Mode config
693 11:13:14.445046 ==============================================================
694 11:13:14.448360 Config description:
695 11:13:14.458199 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:13:14.464851 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:13:14.468570 SELPH_MODE 0: By rank 1: By Phase
698 11:13:14.474758 ==============================================================
699 11:13:14.478162 GAT_TRACK_EN = 1
700 11:13:14.481474 RX_GATING_MODE = 2
701 11:13:14.485186 RX_GATING_TRACK_MODE = 2
702 11:13:14.485624 SELPH_MODE = 1
703 11:13:14.488502 PICG_EARLY_EN = 1
704 11:13:14.491538 VALID_LAT_VALUE = 1
705 11:13:14.498395 ==============================================================
706 11:13:14.501545 Enter into Gating configuration >>>>
707 11:13:14.504979 Exit from Gating configuration <<<<
708 11:13:14.508573 Enter into DVFS_PRE_config >>>>>
709 11:13:14.518273 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:13:14.521562 Exit from DVFS_PRE_config <<<<<
711 11:13:14.524823 Enter into PICG configuration >>>>
712 11:13:14.528231 Exit from PICG configuration <<<<
713 11:13:14.532285 [RX_INPUT] configuration >>>>>
714 11:13:14.535003 [RX_INPUT] configuration <<<<<
715 11:13:14.538287 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:13:14.544989 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:13:14.551603 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:13:14.555641 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:13:14.561748 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:13:14.568342 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:13:14.572298 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:13:14.575372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:13:14.582324 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:13:14.585574 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:13:14.588792 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:13:14.595286 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:13:14.598547 ===================================
728 11:13:14.599166 LPDDR4 DRAM CONFIGURATION
729 11:13:14.602281 ===================================
730 11:13:14.605377 EX_ROW_EN[0] = 0x0
731 11:13:14.605955 EX_ROW_EN[1] = 0x0
732 11:13:14.608639 LP4Y_EN = 0x0
733 11:13:14.609231 WORK_FSP = 0x0
734 11:13:14.611890 WL = 0x2
735 11:13:14.612523 RL = 0x2
736 11:13:14.615048 BL = 0x2
737 11:13:14.618876 RPST = 0x0
738 11:13:14.619511 RD_PRE = 0x0
739 11:13:14.622049 WR_PRE = 0x1
740 11:13:14.622482 WR_PST = 0x0
741 11:13:14.625320 DBI_WR = 0x0
742 11:13:14.625756 DBI_RD = 0x0
743 11:13:14.628549 OTF = 0x1
744 11:13:14.632246 ===================================
745 11:13:14.635484 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:13:14.638702 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:13:14.642094 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:13:14.645303 ===================================
749 11:13:14.648641 LPDDR4 DRAM CONFIGURATION
750 11:13:14.651655 ===================================
751 11:13:14.654974 EX_ROW_EN[0] = 0x10
752 11:13:14.655058 EX_ROW_EN[1] = 0x0
753 11:13:14.658321 LP4Y_EN = 0x0
754 11:13:14.658406 WORK_FSP = 0x0
755 11:13:14.661692 WL = 0x2
756 11:13:14.661777 RL = 0x2
757 11:13:14.665783 BL = 0x2
758 11:13:14.665868 RPST = 0x0
759 11:13:14.668528 RD_PRE = 0x0
760 11:13:14.668613 WR_PRE = 0x1
761 11:13:14.671806 WR_PST = 0x0
762 11:13:14.671890 DBI_WR = 0x0
763 11:13:14.675158 DBI_RD = 0x0
764 11:13:14.675242 OTF = 0x1
765 11:13:14.678446 ===================================
766 11:13:14.685414 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:13:14.689763 nWR fixed to 40
768 11:13:14.693176 [ModeRegInit_LP4] CH0 RK0
769 11:13:14.693260 [ModeRegInit_LP4] CH0 RK1
770 11:13:14.696435 [ModeRegInit_LP4] CH1 RK0
771 11:13:14.700433 [ModeRegInit_LP4] CH1 RK1
772 11:13:14.700517 match AC timing 13
773 11:13:14.706957 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:13:14.709994 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:13:14.713566 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:13:14.719846 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:13:14.723695 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:13:14.723780 [EMI DOE] emi_dcm 0
779 11:13:14.730192 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:13:14.730277 ==
781 11:13:14.733336 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:13:14.736642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:13:14.736728 ==
784 11:13:14.743866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:13:14.747211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:13:14.757722 [CA 0] Center 36 (6~67) winsize 62
787 11:13:14.760908 [CA 1] Center 36 (6~67) winsize 62
788 11:13:14.764175 [CA 2] Center 34 (4~65) winsize 62
789 11:13:14.767364 [CA 3] Center 33 (3~64) winsize 62
790 11:13:14.770577 [CA 4] Center 33 (2~64) winsize 63
791 11:13:14.773838 [CA 5] Center 32 (2~62) winsize 61
792 11:13:14.773922
793 11:13:14.777240 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:13:14.777324
795 11:13:14.780607 [CATrainingPosCal] consider 1 rank data
796 11:13:14.783828 u2DelayCellTimex100 = 270/100 ps
797 11:13:14.787131 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 11:13:14.790372 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 11:13:14.797301 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 11:13:14.801038 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 11:13:14.803984 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
802 11:13:14.807167 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 11:13:14.807252
804 11:13:14.810438 CA PerBit enable=1, Macro0, CA PI delay=32
805 11:13:14.810522
806 11:13:14.813666 [CBTSetCACLKResult] CA Dly = 32
807 11:13:14.813751 CS Dly: 5 (0~36)
808 11:13:14.817582 ==
809 11:13:14.817712 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:13:14.823946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:13:14.824035 ==
812 11:13:14.827278 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:13:14.833814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:13:14.843334 [CA 0] Center 36 (6~67) winsize 62
815 11:13:14.847214 [CA 1] Center 36 (6~67) winsize 62
816 11:13:14.850345 [CA 2] Center 34 (4~65) winsize 62
817 11:13:14.853782 [CA 3] Center 33 (3~64) winsize 62
818 11:13:14.857141 [CA 4] Center 32 (2~63) winsize 62
819 11:13:14.860422 [CA 5] Center 32 (2~62) winsize 61
820 11:13:14.860507
821 11:13:14.863729 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 11:13:14.863814
823 11:13:14.867152 [CATrainingPosCal] consider 2 rank data
824 11:13:14.870419 u2DelayCellTimex100 = 270/100 ps
825 11:13:14.873816 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 11:13:14.877104 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 11:13:14.883660 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 11:13:14.886958 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 11:13:14.890392 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
830 11:13:14.893621 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 11:13:14.893705
832 11:13:14.896795 CA PerBit enable=1, Macro0, CA PI delay=32
833 11:13:14.896879
834 11:13:14.900724 [CBTSetCACLKResult] CA Dly = 32
835 11:13:14.900809 CS Dly: 5 (0~37)
836 11:13:14.900879
837 11:13:14.903994 ----->DramcWriteLeveling(PI) begin...
838 11:13:14.904082 ==
839 11:13:14.907787 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:13:14.911313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:13:14.914942 ==
842 11:13:14.915026 Write leveling (Byte 0): 35 => 35
843 11:13:14.918665 Write leveling (Byte 1): 33 => 33
844 11:13:14.922554 DramcWriteLeveling(PI) end<-----
845 11:13:14.922639
846 11:13:14.922706 ==
847 11:13:14.925745 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:13:14.928706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:13:14.928796 ==
850 11:13:14.932746 [Gating] SW mode calibration
851 11:13:14.939951 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:13:14.946497 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:13:14.949486 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:13:14.952744 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 11:13:14.959594 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 11:13:14.962993 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 11:13:14.966310 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:13:14.969616 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:13:14.976351 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:13:14.979783 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:13:14.983230 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:13:14.989883 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:13:14.993071 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:13:14.996384 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:13:15.002814 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:13:15.006699 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:13:15.009930 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:13:15.016422 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:13:15.019551 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:13:15.023287 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 11:13:15.029993 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 11:13:15.033258 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 11:13:15.036766 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:13:15.039968 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:13:15.046512 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:13:15.050361 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:13:15.053637 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:13:15.060398 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:13:15.063479 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
880 11:13:15.066621 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 11:13:15.073674 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:13:15.077131 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:13:15.080407 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:13:15.087073 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:13:15.090482 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:13:15.093707 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
887 11:13:15.100423 0 10 8 | B1->B0 | 3131 2828 | 1 0 | (1 1) (0 0)
888 11:13:15.103662 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 11:13:15.106804 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:13:15.113349 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:13:15.116786 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:13:15.120188 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:13:15.123420 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:13:15.130266 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
895 11:13:15.133893 0 11 8 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
896 11:13:15.136983 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
897 11:13:15.143881 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:13:15.147217 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:13:15.150679 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:13:15.157182 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:13:15.160362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:13:15.163606 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 11:13:15.170452 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 11:13:15.174164 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:13:15.177281 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:13:15.183986 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:13:15.187248 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:13:15.190640 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:13:15.194061 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:13:15.200533 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:13:15.203873 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:13:15.207139 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:13:15.213409 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:13:15.216748 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:13:15.220571 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:13:15.227417 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:13:15.230060 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:13:15.233403 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 11:13:15.240257 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 11:13:15.243362 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 11:13:15.247107 Total UI for P1: 0, mck2ui 16
922 11:13:15.250264 best dqsien dly found for B0: ( 0, 14, 6)
923 11:13:15.253390 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 11:13:15.256955 Total UI for P1: 0, mck2ui 16
925 11:13:15.260740 best dqsien dly found for B1: ( 0, 14, 10)
926 11:13:15.263898 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
927 11:13:15.267219 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 11:13:15.267309
929 11:13:15.271092 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 11:13:15.277929 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 11:13:15.278014 [Gating] SW calibration Done
932 11:13:15.278081 ==
933 11:13:15.281224 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:13:15.287795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:13:15.287880 ==
936 11:13:15.287955 RX Vref Scan: 0
937 11:13:15.288027
938 11:13:15.291213 RX Vref 0 -> 0, step: 1
939 11:13:15.291298
940 11:13:15.294571 RX Delay -130 -> 252, step: 16
941 11:13:15.297884 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
942 11:13:15.301280 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
943 11:13:15.304648 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
944 11:13:15.307479 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
945 11:13:15.314082 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
946 11:13:15.317764 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
947 11:13:15.321129 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
948 11:13:15.324404 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
949 11:13:15.327709 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
950 11:13:15.334417 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
951 11:13:15.337747 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
952 11:13:15.341169 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
953 11:13:15.344467 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
954 11:13:15.347532 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
955 11:13:15.354163 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
956 11:13:15.358152 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
957 11:13:15.358249 ==
958 11:13:15.361364 Dram Type= 6, Freq= 0, CH_0, rank 0
959 11:13:15.364563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 11:13:15.364649 ==
961 11:13:15.367654 DQS Delay:
962 11:13:15.367739 DQS0 = 0, DQS1 = 0
963 11:13:15.367807 DQM Delay:
964 11:13:15.371428 DQM0 = 89, DQM1 = 83
965 11:13:15.371520 DQ Delay:
966 11:13:15.374426 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
967 11:13:15.377704 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
968 11:13:15.381553 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
969 11:13:15.384834 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
970 11:13:15.384919
971 11:13:15.384985
972 11:13:15.385048 ==
973 11:13:15.387943 Dram Type= 6, Freq= 0, CH_0, rank 0
974 11:13:15.391186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 11:13:15.394621 ==
976 11:13:15.394705
977 11:13:15.394771
978 11:13:15.394833 TX Vref Scan disable
979 11:13:15.397860 == TX Byte 0 ==
980 11:13:15.401273 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
981 11:13:15.404715 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
982 11:13:15.408040 == TX Byte 1 ==
983 11:13:15.411914 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
984 11:13:15.414697 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
985 11:13:15.414782 ==
986 11:13:15.417863 Dram Type= 6, Freq= 0, CH_0, rank 0
987 11:13:15.424499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 11:13:15.424589 ==
989 11:13:15.437090 TX Vref=22, minBit 8, minWin=27, winSum=448
990 11:13:15.440499 TX Vref=24, minBit 8, minWin=27, winSum=450
991 11:13:15.443811 TX Vref=26, minBit 8, minWin=27, winSum=452
992 11:13:15.447053 TX Vref=28, minBit 5, minWin=28, winSum=455
993 11:13:15.450377 TX Vref=30, minBit 5, minWin=28, winSum=455
994 11:13:15.453651 TX Vref=32, minBit 10, minWin=27, winSum=450
995 11:13:15.460536 [TxChooseVref] Worse bit 5, Min win 28, Win sum 455, Final Vref 28
996 11:13:15.460622
997 11:13:15.463706 Final TX Range 1 Vref 28
998 11:13:15.463791
999 11:13:15.463859 ==
1000 11:13:15.466990 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 11:13:15.470101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 11:13:15.470214 ==
1003 11:13:15.470285
1004 11:13:15.473834
1005 11:13:15.473918 TX Vref Scan disable
1006 11:13:15.477187 == TX Byte 0 ==
1007 11:13:15.480066 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1008 11:13:15.483507 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1009 11:13:15.487101 == TX Byte 1 ==
1010 11:13:15.490450 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1011 11:13:15.493783 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1012 11:13:15.493920
1013 11:13:15.497317 [DATLAT]
1014 11:13:15.497455 Freq=800, CH0 RK0
1015 11:13:15.497574
1016 11:13:15.500562 DATLAT Default: 0xa
1017 11:13:15.500667 0, 0xFFFF, sum = 0
1018 11:13:15.503955 1, 0xFFFF, sum = 0
1019 11:13:15.504075 2, 0xFFFF, sum = 0
1020 11:13:15.507342 3, 0xFFFF, sum = 0
1021 11:13:15.507470 4, 0xFFFF, sum = 0
1022 11:13:15.510332 5, 0xFFFF, sum = 0
1023 11:13:15.510458 6, 0xFFFF, sum = 0
1024 11:13:15.513749 7, 0xFFFF, sum = 0
1025 11:13:15.513896 8, 0xFFFF, sum = 0
1026 11:13:15.517153 9, 0x0, sum = 1
1027 11:13:15.517309 10, 0x0, sum = 2
1028 11:13:15.520499 11, 0x0, sum = 3
1029 11:13:15.520657 12, 0x0, sum = 4
1030 11:13:15.523582 best_step = 10
1031 11:13:15.523756
1032 11:13:15.523895 ==
1033 11:13:15.527514 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 11:13:15.530735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 11:13:15.530946 ==
1036 11:13:15.534140 RX Vref Scan: 1
1037 11:13:15.534385
1038 11:13:15.534579 Set Vref Range= 32 -> 127
1039 11:13:15.534762
1040 11:13:15.537584 RX Vref 32 -> 127, step: 1
1041 11:13:15.537907
1042 11:13:15.540313 RX Delay -79 -> 252, step: 8
1043 11:13:15.540617
1044 11:13:15.544473 Set Vref, RX VrefLevel [Byte0]: 32
1045 11:13:15.547157 [Byte1]: 32
1046 11:13:15.547613
1047 11:13:15.550527 Set Vref, RX VrefLevel [Byte0]: 33
1048 11:13:15.553874 [Byte1]: 33
1049 11:13:15.557856
1050 11:13:15.558444 Set Vref, RX VrefLevel [Byte0]: 34
1051 11:13:15.560982 [Byte1]: 34
1052 11:13:15.564843
1053 11:13:15.565290 Set Vref, RX VrefLevel [Byte0]: 35
1054 11:13:15.568588 [Byte1]: 35
1055 11:13:15.572842
1056 11:13:15.573292 Set Vref, RX VrefLevel [Byte0]: 36
1057 11:13:15.575979 [Byte1]: 36
1058 11:13:15.580293
1059 11:13:15.580728 Set Vref, RX VrefLevel [Byte0]: 37
1060 11:13:15.583650 [Byte1]: 37
1061 11:13:15.588016
1062 11:13:15.588470 Set Vref, RX VrefLevel [Byte0]: 38
1063 11:13:15.591181 [Byte1]: 38
1064 11:13:15.595024
1065 11:13:15.595509 Set Vref, RX VrefLevel [Byte0]: 39
1066 11:13:15.598207 [Byte1]: 39
1067 11:13:15.603391
1068 11:13:15.603846 Set Vref, RX VrefLevel [Byte0]: 40
1069 11:13:15.606500 [Byte1]: 40
1070 11:13:15.610602
1071 11:13:15.611020 Set Vref, RX VrefLevel [Byte0]: 41
1072 11:13:15.613356 [Byte1]: 41
1073 11:13:15.617850
1074 11:13:15.618297 Set Vref, RX VrefLevel [Byte0]: 42
1075 11:13:15.621319 [Byte1]: 42
1076 11:13:15.625479
1077 11:13:15.625907 Set Vref, RX VrefLevel [Byte0]: 43
1078 11:13:15.628558 [Byte1]: 43
1079 11:13:15.633172
1080 11:13:15.633633 Set Vref, RX VrefLevel [Byte0]: 44
1081 11:13:15.636405 [Byte1]: 44
1082 11:13:15.640276
1083 11:13:15.640701 Set Vref, RX VrefLevel [Byte0]: 45
1084 11:13:15.643670 [Byte1]: 45
1085 11:13:15.648266
1086 11:13:15.648752 Set Vref, RX VrefLevel [Byte0]: 46
1087 11:13:15.651640 [Byte1]: 46
1088 11:13:15.655702
1089 11:13:15.656132 Set Vref, RX VrefLevel [Byte0]: 47
1090 11:13:15.658867 [Byte1]: 47
1091 11:13:15.662920
1092 11:13:15.663405 Set Vref, RX VrefLevel [Byte0]: 48
1093 11:13:15.666294 [Byte1]: 48
1094 11:13:15.670719
1095 11:13:15.671322 Set Vref, RX VrefLevel [Byte0]: 49
1096 11:13:15.674029 [Byte1]: 49
1097 11:13:15.678273
1098 11:13:15.678722 Set Vref, RX VrefLevel [Byte0]: 50
1099 11:13:15.681197 [Byte1]: 50
1100 11:13:15.685757
1101 11:13:15.686186 Set Vref, RX VrefLevel [Byte0]: 51
1102 11:13:15.688776 [Byte1]: 51
1103 11:13:15.693075
1104 11:13:15.696445 Set Vref, RX VrefLevel [Byte0]: 52
1105 11:13:15.699670 [Byte1]: 52
1106 11:13:15.700100
1107 11:13:15.703420 Set Vref, RX VrefLevel [Byte0]: 53
1108 11:13:15.706792 [Byte1]: 53
1109 11:13:15.707232
1110 11:13:15.710009 Set Vref, RX VrefLevel [Byte0]: 54
1111 11:13:15.713198 [Byte1]: 54
1112 11:13:15.713754
1113 11:13:15.716409 Set Vref, RX VrefLevel [Byte0]: 55
1114 11:13:15.719796 [Byte1]: 55
1115 11:13:15.723672
1116 11:13:15.724176 Set Vref, RX VrefLevel [Byte0]: 56
1117 11:13:15.727128 [Byte1]: 56
1118 11:13:15.730979
1119 11:13:15.731677 Set Vref, RX VrefLevel [Byte0]: 57
1120 11:13:15.734142 [Byte1]: 57
1121 11:13:15.738684
1122 11:13:15.739105 Set Vref, RX VrefLevel [Byte0]: 58
1123 11:13:15.742122 [Byte1]: 58
1124 11:13:15.746098
1125 11:13:15.746536 Set Vref, RX VrefLevel [Byte0]: 59
1126 11:13:15.749248 [Byte1]: 59
1127 11:13:15.753504
1128 11:13:15.753929 Set Vref, RX VrefLevel [Byte0]: 60
1129 11:13:15.756779 [Byte1]: 60
1130 11:13:15.761280
1131 11:13:15.761705 Set Vref, RX VrefLevel [Byte0]: 61
1132 11:13:15.764521 [Byte1]: 61
1133 11:13:15.768926
1134 11:13:15.769352 Set Vref, RX VrefLevel [Byte0]: 62
1135 11:13:15.772551 [Byte1]: 62
1136 11:13:15.776516
1137 11:13:15.776997 Set Vref, RX VrefLevel [Byte0]: 63
1138 11:13:15.779886 [Byte1]: 63
1139 11:13:15.783755
1140 11:13:15.784302 Set Vref, RX VrefLevel [Byte0]: 64
1141 11:13:15.786999 [Byte1]: 64
1142 11:13:15.791626
1143 11:13:15.792197 Set Vref, RX VrefLevel [Byte0]: 65
1144 11:13:15.794664 [Byte1]: 65
1145 11:13:15.798908
1146 11:13:15.799436 Set Vref, RX VrefLevel [Byte0]: 66
1147 11:13:15.802390 [Byte1]: 66
1148 11:13:15.806834
1149 11:13:15.807444 Set Vref, RX VrefLevel [Byte0]: 67
1150 11:13:15.809883 [Byte1]: 67
1151 11:13:15.814147
1152 11:13:15.814579 Set Vref, RX VrefLevel [Byte0]: 68
1153 11:13:15.817308 [Byte1]: 68
1154 11:13:15.821293
1155 11:13:15.821962 Set Vref, RX VrefLevel [Byte0]: 69
1156 11:13:15.825287 [Byte1]: 69
1157 11:13:15.829129
1158 11:13:15.829556 Set Vref, RX VrefLevel [Byte0]: 70
1159 11:13:15.832644 [Byte1]: 70
1160 11:13:15.836676
1161 11:13:15.837112 Set Vref, RX VrefLevel [Byte0]: 71
1162 11:13:15.839995 [Byte1]: 71
1163 11:13:15.844271
1164 11:13:15.844850 Set Vref, RX VrefLevel [Byte0]: 72
1165 11:13:15.847712 [Byte1]: 72
1166 11:13:15.852332
1167 11:13:15.852762 Set Vref, RX VrefLevel [Byte0]: 73
1168 11:13:15.855030 [Byte1]: 73
1169 11:13:15.859828
1170 11:13:15.860259 Set Vref, RX VrefLevel [Byte0]: 74
1171 11:13:15.862532 [Byte1]: 74
1172 11:13:15.867075
1173 11:13:15.867557 Set Vref, RX VrefLevel [Byte0]: 75
1174 11:13:15.870368 [Byte1]: 75
1175 11:13:15.874514
1176 11:13:15.874964 Set Vref, RX VrefLevel [Byte0]: 76
1177 11:13:15.878063 [Byte1]: 76
1178 11:13:15.881944
1179 11:13:15.882365 Set Vref, RX VrefLevel [Byte0]: 77
1180 11:13:15.885308 [Byte1]: 77
1181 11:13:15.889743
1182 11:13:15.890168 Set Vref, RX VrefLevel [Byte0]: 78
1183 11:13:15.893138 [Byte1]: 78
1184 11:13:15.897113
1185 11:13:15.897535 Final RX Vref Byte 0 = 51 to rank0
1186 11:13:15.900255 Final RX Vref Byte 1 = 61 to rank0
1187 11:13:15.904108 Final RX Vref Byte 0 = 51 to rank1
1188 11:13:15.907443 Final RX Vref Byte 1 = 61 to rank1==
1189 11:13:15.910686 Dram Type= 6, Freq= 0, CH_0, rank 0
1190 11:13:15.916999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1191 11:13:15.917462 ==
1192 11:13:15.917805 DQS Delay:
1193 11:13:15.918123 DQS0 = 0, DQS1 = 0
1194 11:13:15.920532 DQM Delay:
1195 11:13:15.920986 DQM0 = 91, DQM1 = 86
1196 11:13:15.923574 DQ Delay:
1197 11:13:15.926803 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1198 11:13:15.930502 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1199 11:13:15.933853 DQ8 =80, DQ9 =76, DQ10 =84, DQ11 =80
1200 11:13:15.937328 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1201 11:13:15.937750
1202 11:13:15.938096
1203 11:13:15.943716 [DQSOSCAuto] RK0, (LSB)MR18= 0x493e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
1204 11:13:15.947634 CH0 RK0: MR19=606, MR18=493E
1205 11:13:15.954017 CH0_RK0: MR19=0x606, MR18=0x493E, DQSOSC=391, MR23=63, INC=96, DEC=64
1206 11:13:15.954525
1207 11:13:15.957507 ----->DramcWriteLeveling(PI) begin...
1208 11:13:15.957945 ==
1209 11:13:15.960778 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 11:13:15.963987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 11:13:15.964458 ==
1212 11:13:15.967289 Write leveling (Byte 0): 32 => 32
1213 11:13:15.970506 Write leveling (Byte 1): 32 => 32
1214 11:13:15.974010 DramcWriteLeveling(PI) end<-----
1215 11:13:15.974541
1216 11:13:15.975020 ==
1217 11:13:15.977222 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 11:13:16.021505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 11:13:16.021602 ==
1220 11:13:16.021707 [Gating] SW mode calibration
1221 11:13:16.021956 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1222 11:13:16.022022 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1223 11:13:16.022082 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 11:13:16.022140 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1225 11:13:16.022745 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1226 11:13:16.023098 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:13:16.023187 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:13:16.023251 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:13:16.065325 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:13:16.066017 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:13:16.066380 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:13:16.066450 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:13:16.066513 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:13:16.066589 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:13:16.066691 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:13:16.066774 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:13:16.066863 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:13:16.066936 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:13:16.109026 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:13:16.109321 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:13:16.109445 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1242 11:13:16.109525 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:13:16.109589 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:13:16.109691 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:13:16.109950 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:13:16.110057 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:13:16.110125 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:13:16.110184 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:13:16.113913 0 9 8 | B1->B0 | 2c2c 2929 | 1 0 | (1 1) (0 0)
1250 11:13:16.120346 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 11:13:16.123604 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 11:13:16.126789 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 11:13:16.133460 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 11:13:16.136634 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 11:13:16.139805 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 11:13:16.146852 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1257 11:13:16.150694 0 10 8 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (0 0)
1258 11:13:16.154392 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:13:16.158220 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:13:16.162076 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 11:13:16.166233 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 11:13:16.172177 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 11:13:16.175566 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 11:13:16.179694 0 11 4 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
1265 11:13:16.186213 0 11 8 | B1->B0 | 4040 4242 | 0 0 | (0 0) (0 0)
1266 11:13:16.189517 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:13:16.192985 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:13:16.196249 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 11:13:16.203486 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 11:13:16.206694 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 11:13:16.210095 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 11:13:16.216658 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 11:13:16.219924 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1274 11:13:16.223200 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:13:16.230259 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:13:16.233447 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:13:16.236682 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:13:16.243448 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:13:16.246546 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:13:16.249748 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:13:16.256668 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:13:16.259875 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:13:16.263003 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:13:16.270003 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 11:13:16.273465 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 11:13:16.276744 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 11:13:16.282947 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 11:13:16.286737 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 11:13:16.289495 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1290 11:13:16.293315 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1291 11:13:16.296780 Total UI for P1: 0, mck2ui 16
1292 11:13:16.299570 best dqsien dly found for B0: ( 0, 14, 8)
1293 11:13:16.303555 Total UI for P1: 0, mck2ui 16
1294 11:13:16.306606 best dqsien dly found for B1: ( 0, 14, 8)
1295 11:13:16.309969 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1296 11:13:16.313479 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1297 11:13:16.316806
1298 11:13:16.319967 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1299 11:13:16.323316 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1300 11:13:16.326742 [Gating] SW calibration Done
1301 11:13:16.327263 ==
1302 11:13:16.329997 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 11:13:16.333740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 11:13:16.334205 ==
1305 11:13:16.334799 RX Vref Scan: 0
1306 11:13:16.335142
1307 11:13:16.336584 RX Vref 0 -> 0, step: 1
1308 11:13:16.337061
1309 11:13:16.340362 RX Delay -130 -> 252, step: 16
1310 11:13:16.343563 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1311 11:13:16.346942 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1312 11:13:16.353428 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1313 11:13:16.356822 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1314 11:13:16.360162 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1315 11:13:16.363294 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1316 11:13:16.367164 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1317 11:13:16.370334 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1318 11:13:16.376946 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1319 11:13:16.380218 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1320 11:13:16.383724 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1321 11:13:16.386893 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1322 11:13:16.390261 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1323 11:13:16.396848 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1324 11:13:16.400821 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1325 11:13:16.403402 iDelay=206, Bit 15, Center 85 (-18 ~ 189) 208
1326 11:13:16.403836 ==
1327 11:13:16.407000 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 11:13:16.410169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 11:13:16.410601 ==
1330 11:13:16.413546 DQS Delay:
1331 11:13:16.413977 DQS0 = 0, DQS1 = 0
1332 11:13:16.417183 DQM Delay:
1333 11:13:16.417613 DQM0 = 88, DQM1 = 82
1334 11:13:16.417977 DQ Delay:
1335 11:13:16.420389 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1336 11:13:16.423724 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1337 11:13:16.427038 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1338 11:13:16.430463 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1339 11:13:16.430938
1340 11:13:16.431300
1341 11:13:16.433684 ==
1342 11:13:16.434065 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 11:13:16.440758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 11:13:16.441346 ==
1345 11:13:16.441889
1346 11:13:16.442261
1347 11:13:16.443844 TX Vref Scan disable
1348 11:13:16.444272 == TX Byte 0 ==
1349 11:13:16.447458 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1350 11:13:16.453819 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1351 11:13:16.454249 == TX Byte 1 ==
1352 11:13:16.457220 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1353 11:13:16.463965 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1354 11:13:16.464393 ==
1355 11:13:16.467075 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 11:13:16.470158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 11:13:16.470589 ==
1358 11:13:16.483153 TX Vref=22, minBit 13, minWin=27, winSum=447
1359 11:13:16.487065 TX Vref=24, minBit 13, minWin=27, winSum=449
1360 11:13:16.489897 TX Vref=26, minBit 12, minWin=27, winSum=455
1361 11:13:16.493157 TX Vref=28, minBit 4, minWin=28, winSum=456
1362 11:13:16.497067 TX Vref=30, minBit 4, minWin=28, winSum=456
1363 11:13:16.503808 TX Vref=32, minBit 12, minWin=27, winSum=453
1364 11:13:16.506975 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 28
1365 11:13:16.507395
1366 11:13:16.510389 Final TX Range 1 Vref 28
1367 11:13:16.510687
1368 11:13:16.510920 ==
1369 11:13:16.512943 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 11:13:16.516918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 11:13:16.519942 ==
1372 11:13:16.520165
1373 11:13:16.520340
1374 11:13:16.520502 TX Vref Scan disable
1375 11:13:16.523264 == TX Byte 0 ==
1376 11:13:16.526577 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1377 11:13:16.529824 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1378 11:13:16.533312 == TX Byte 1 ==
1379 11:13:16.536675 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1380 11:13:16.543318 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1381 11:13:16.543569
1382 11:13:16.543746 [DATLAT]
1383 11:13:16.543912 Freq=800, CH0 RK1
1384 11:13:16.544070
1385 11:13:16.547153 DATLAT Default: 0xa
1386 11:13:16.547409 0, 0xFFFF, sum = 0
1387 11:13:16.550515 1, 0xFFFF, sum = 0
1388 11:13:16.550759 2, 0xFFFF, sum = 0
1389 11:13:16.553611 3, 0xFFFF, sum = 0
1390 11:13:16.553835 4, 0xFFFF, sum = 0
1391 11:13:16.556791 5, 0xFFFF, sum = 0
1392 11:13:16.557035 6, 0xFFFF, sum = 0
1393 11:13:16.559865 7, 0xFFFF, sum = 0
1394 11:13:16.563683 8, 0xFFFF, sum = 0
1395 11:13:16.563964 9, 0x0, sum = 1
1396 11:13:16.564183 10, 0x0, sum = 2
1397 11:13:16.566833 11, 0x0, sum = 3
1398 11:13:16.567120 12, 0x0, sum = 4
1399 11:13:16.569903 best_step = 10
1400 11:13:16.570172
1401 11:13:16.570420 ==
1402 11:13:16.573573 Dram Type= 6, Freq= 0, CH_0, rank 1
1403 11:13:16.577085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 11:13:16.577561 ==
1405 11:13:16.580466 RX Vref Scan: 0
1406 11:13:16.580919
1407 11:13:16.581424 RX Vref 0 -> 0, step: 1
1408 11:13:16.581753
1409 11:13:16.583360 RX Delay -79 -> 252, step: 8
1410 11:13:16.590474 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1411 11:13:16.593635 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1412 11:13:16.596868 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1413 11:13:16.600088 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1414 11:13:16.604041 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1415 11:13:16.610132 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1416 11:13:16.613511 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1417 11:13:16.616620 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1418 11:13:16.620136 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1419 11:13:16.623826 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1420 11:13:16.630136 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1421 11:13:16.633615 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1422 11:13:16.636974 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1423 11:13:16.640241 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1424 11:13:16.643750 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1425 11:13:16.650180 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1426 11:13:16.650764 ==
1427 11:13:16.653462 Dram Type= 6, Freq= 0, CH_0, rank 1
1428 11:13:16.657469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 11:13:16.657979 ==
1430 11:13:16.658391 DQS Delay:
1431 11:13:16.660352 DQS0 = 0, DQS1 = 0
1432 11:13:16.660819 DQM Delay:
1433 11:13:16.663447 DQM0 = 93, DQM1 = 84
1434 11:13:16.663991 DQ Delay:
1435 11:13:16.667311 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1436 11:13:16.670478 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1437 11:13:16.673471 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1438 11:13:16.676960 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1439 11:13:16.677378
1440 11:13:16.677706
1441 11:13:16.683399 [DQSOSCAuto] RK1, (LSB)MR18= 0x4617, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1442 11:13:16.687168 CH0 RK1: MR19=606, MR18=4617
1443 11:13:16.693455 CH0_RK1: MR19=0x606, MR18=0x4617, DQSOSC=392, MR23=63, INC=96, DEC=64
1444 11:13:16.697012 [RxdqsGatingPostProcess] freq 800
1445 11:13:16.703805 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1446 11:13:16.706869 Pre-setting of DQS Precalculation
1447 11:13:16.710242 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1448 11:13:16.710665 ==
1449 11:13:16.713467 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 11:13:16.717009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 11:13:16.717431 ==
1452 11:13:16.723670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 11:13:16.730320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 11:13:16.738446 [CA 0] Center 36 (6~67) winsize 62
1455 11:13:16.741934 [CA 1] Center 36 (6~67) winsize 62
1456 11:13:16.745279 [CA 2] Center 35 (5~65) winsize 61
1457 11:13:16.748705 [CA 3] Center 34 (4~65) winsize 62
1458 11:13:16.751886 [CA 4] Center 34 (4~65) winsize 62
1459 11:13:16.755533 [CA 5] Center 34 (4~64) winsize 61
1460 11:13:16.756027
1461 11:13:16.758715 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1462 11:13:16.759131
1463 11:13:16.762174 [CATrainingPosCal] consider 1 rank data
1464 11:13:16.765515 u2DelayCellTimex100 = 270/100 ps
1465 11:13:16.768764 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 11:13:16.771904 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 11:13:16.778635 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1468 11:13:16.781922 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1469 11:13:16.785707 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 11:13:16.789169 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1471 11:13:16.789595
1472 11:13:16.791880 CA PerBit enable=1, Macro0, CA PI delay=34
1473 11:13:16.792388
1474 11:13:16.795752 [CBTSetCACLKResult] CA Dly = 34
1475 11:13:16.796177 CS Dly: 6 (0~37)
1476 11:13:16.796512 ==
1477 11:13:16.798585 Dram Type= 6, Freq= 0, CH_1, rank 1
1478 11:13:16.805913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 11:13:16.806459 ==
1480 11:13:16.809015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1481 11:13:16.815707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1482 11:13:16.825015 [CA 0] Center 36 (6~67) winsize 62
1483 11:13:16.828917 [CA 1] Center 37 (6~68) winsize 63
1484 11:13:16.833210 [CA 2] Center 35 (4~66) winsize 63
1485 11:13:16.836258 [CA 3] Center 34 (4~65) winsize 62
1486 11:13:16.840243 [CA 4] Center 35 (4~66) winsize 63
1487 11:13:16.840722 [CA 5] Center 34 (4~65) winsize 62
1488 11:13:16.841082
1489 11:13:16.844050 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1490 11:13:16.844497
1491 11:13:16.848132 [CATrainingPosCal] consider 2 rank data
1492 11:13:16.851526 u2DelayCellTimex100 = 270/100 ps
1493 11:13:16.854856 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 11:13:16.858063 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1495 11:13:16.864517 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1496 11:13:16.868339 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 11:13:16.871378 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1498 11:13:16.875107 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1499 11:13:16.875650
1500 11:13:16.878319 CA PerBit enable=1, Macro0, CA PI delay=34
1501 11:13:16.878746
1502 11:13:16.881816 [CBTSetCACLKResult] CA Dly = 34
1503 11:13:16.882240 CS Dly: 7 (0~39)
1504 11:13:16.882580
1505 11:13:16.885085 ----->DramcWriteLeveling(PI) begin...
1506 11:13:16.885515 ==
1507 11:13:16.888176 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 11:13:16.894436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 11:13:16.894523 ==
1510 11:13:16.898180 Write leveling (Byte 0): 25 => 25
1511 11:13:16.901353 Write leveling (Byte 1): 27 => 27
1512 11:13:16.901436 DramcWriteLeveling(PI) end<-----
1513 11:13:16.904812
1514 11:13:16.904894 ==
1515 11:13:16.908196 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 11:13:16.911352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 11:13:16.911468 ==
1518 11:13:16.914583 [Gating] SW mode calibration
1519 11:13:16.921513 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1520 11:13:16.924833 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1521 11:13:16.931243 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1522 11:13:16.934724 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1523 11:13:16.938082 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:13:16.944769 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:13:16.948116 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:13:16.951384 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:13:16.958134 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:13:16.961444 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:13:16.964849 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:13:16.971943 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:13:16.974608 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:13:16.978658 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:13:16.981891 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:13:16.988796 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:13:16.991473 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:13:16.994774 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1537 11:13:17.001901 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1538 11:13:17.005447 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1539 11:13:17.008694 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:13:17.015285 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:13:17.018767 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:13:17.022011 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:13:17.028729 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:13:17.032046 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:13:17.035169 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:13:17.042016 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1547 11:13:17.045338 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1548 11:13:17.048358 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 11:13:17.055398 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 11:13:17.058513 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 11:13:17.062051 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 11:13:17.065468 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 11:13:17.071914 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 11:13:17.075115 0 10 4 | B1->B0 | 3131 2f2f | 1 0 | (0 0) (0 0)
1555 11:13:17.078423 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:13:17.085075 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:13:17.088630 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:13:17.092044 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 11:13:17.098549 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 11:13:17.102028 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 11:13:17.105129 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 11:13:17.112402 0 11 4 | B1->B0 | 2c2c 3636 | 0 0 | (0 0) (0 0)
1563 11:13:17.115429 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1564 11:13:17.118510 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 11:13:17.125182 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 11:13:17.128344 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 11:13:17.132021 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 11:13:17.138729 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 11:13:17.142222 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1570 11:13:17.144932 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1571 11:13:17.148263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:13:17.155526 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:13:17.158849 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:13:17.162251 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:13:17.168732 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:13:17.172068 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:13:17.175374 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:13:17.182064 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:13:17.185259 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:13:17.188608 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:13:17.195904 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:13:17.199282 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 11:13:17.202755 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 11:13:17.205421 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 11:13:17.212490 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 11:13:17.215929 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1587 11:13:17.219191 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1588 11:13:17.222277 Total UI for P1: 0, mck2ui 16
1589 11:13:17.225460 best dqsien dly found for B0: ( 0, 14, 4)
1590 11:13:17.228868 Total UI for P1: 0, mck2ui 16
1591 11:13:17.232814 best dqsien dly found for B1: ( 0, 14, 4)
1592 11:13:17.236123 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1593 11:13:17.239182 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1594 11:13:17.239630
1595 11:13:17.246021 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1596 11:13:17.249331 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1597 11:13:17.249750 [Gating] SW calibration Done
1598 11:13:17.252643 ==
1599 11:13:17.252953 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 11:13:17.259282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 11:13:17.259628 ==
1602 11:13:17.259876 RX Vref Scan: 0
1603 11:13:17.260108
1604 11:13:17.262568 RX Vref 0 -> 0, step: 1
1605 11:13:17.262983
1606 11:13:17.265910 RX Delay -130 -> 252, step: 16
1607 11:13:17.269394 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1608 11:13:17.272736 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1609 11:13:17.276192 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1610 11:13:17.282482 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1611 11:13:17.285690 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1612 11:13:17.289010 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1613 11:13:17.292373 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1614 11:13:17.295379 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1615 11:13:17.302149 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1616 11:13:17.305529 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1617 11:13:17.308890 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1618 11:13:17.312336 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1619 11:13:17.315471 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1620 11:13:17.322521 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1621 11:13:17.325341 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1622 11:13:17.328823 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1623 11:13:17.329106 ==
1624 11:13:17.332003 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 11:13:17.335317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 11:13:17.339292 ==
1627 11:13:17.339564 DQS Delay:
1628 11:13:17.339762 DQS0 = 0, DQS1 = 0
1629 11:13:17.342716 DQM Delay:
1630 11:13:17.343145 DQM0 = 94, DQM1 = 89
1631 11:13:17.343557 DQ Delay:
1632 11:13:17.345942 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1633 11:13:17.349480 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1634 11:13:17.352594 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1635 11:13:17.355928 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1636 11:13:17.359142
1637 11:13:17.359576
1638 11:13:17.359895 ==
1639 11:13:17.362378 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 11:13:17.365763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 11:13:17.366163 ==
1642 11:13:17.366479
1643 11:13:17.366825
1644 11:13:17.369189 TX Vref Scan disable
1645 11:13:17.369639 == TX Byte 0 ==
1646 11:13:17.375699 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1647 11:13:17.379258 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1648 11:13:17.379775 == TX Byte 1 ==
1649 11:13:17.385912 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1650 11:13:17.389096 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1651 11:13:17.389490 ==
1652 11:13:17.392897 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 11:13:17.396349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 11:13:17.396736 ==
1655 11:13:17.409672 TX Vref=22, minBit 0, minWin=26, winSum=432
1656 11:13:17.412052 TX Vref=24, minBit 0, minWin=26, winSum=437
1657 11:13:17.415571 TX Vref=26, minBit 3, minWin=26, winSum=441
1658 11:13:17.419528 TX Vref=28, minBit 0, minWin=26, winSum=440
1659 11:13:17.422141 TX Vref=30, minBit 3, minWin=26, winSum=440
1660 11:13:17.425476 TX Vref=32, minBit 0, minWin=26, winSum=440
1661 11:13:17.432716 [TxChooseVref] Worse bit 3, Min win 26, Win sum 441, Final Vref 26
1662 11:13:17.432847
1663 11:13:17.435898 Final TX Range 1 Vref 26
1664 11:13:17.436025
1665 11:13:17.436139 ==
1666 11:13:17.438701 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 11:13:17.442619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 11:13:17.442703 ==
1669 11:13:17.442769
1670 11:13:17.445864
1671 11:13:17.445947 TX Vref Scan disable
1672 11:13:17.449238 == TX Byte 0 ==
1673 11:13:17.452597 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1674 11:13:17.455806 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1675 11:13:17.458750 == TX Byte 1 ==
1676 11:13:17.462738 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1677 11:13:17.465940 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1678 11:13:17.468772
1679 11:13:17.468863 [DATLAT]
1680 11:13:17.468952 Freq=800, CH1 RK0
1681 11:13:17.469041
1682 11:13:17.472005 DATLAT Default: 0xa
1683 11:13:17.472101 0, 0xFFFF, sum = 0
1684 11:13:17.475478 1, 0xFFFF, sum = 0
1685 11:13:17.475578 2, 0xFFFF, sum = 0
1686 11:13:17.478885 3, 0xFFFF, sum = 0
1687 11:13:17.478981 4, 0xFFFF, sum = 0
1688 11:13:17.482271 5, 0xFFFF, sum = 0
1689 11:13:17.482374 6, 0xFFFF, sum = 0
1690 11:13:17.485829 7, 0xFFFF, sum = 0
1691 11:13:17.489080 8, 0xFFFF, sum = 0
1692 11:13:17.489210 9, 0x0, sum = 1
1693 11:13:17.489330 10, 0x0, sum = 2
1694 11:13:17.492049 11, 0x0, sum = 3
1695 11:13:17.492191 12, 0x0, sum = 4
1696 11:13:17.495281 best_step = 10
1697 11:13:17.495449
1698 11:13:17.495587 ==
1699 11:13:17.498811 Dram Type= 6, Freq= 0, CH_1, rank 0
1700 11:13:17.502197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1701 11:13:17.502429 ==
1702 11:13:17.506072 RX Vref Scan: 1
1703 11:13:17.506302
1704 11:13:17.506519 Set Vref Range= 32 -> 127
1705 11:13:17.506756
1706 11:13:17.509185 RX Vref 32 -> 127, step: 1
1707 11:13:17.509458
1708 11:13:17.512611 RX Delay -79 -> 252, step: 8
1709 11:13:17.512859
1710 11:13:17.515927 Set Vref, RX VrefLevel [Byte0]: 32
1711 11:13:17.519236 [Byte1]: 32
1712 11:13:17.519693
1713 11:13:17.522783 Set Vref, RX VrefLevel [Byte0]: 33
1714 11:13:17.526009 [Byte1]: 33
1715 11:13:17.529817
1716 11:13:17.530305 Set Vref, RX VrefLevel [Byte0]: 34
1717 11:13:17.533060 [Byte1]: 34
1718 11:13:17.537065
1719 11:13:17.537674 Set Vref, RX VrefLevel [Byte0]: 35
1720 11:13:17.540391 [Byte1]: 35
1721 11:13:17.544411
1722 11:13:17.544879 Set Vref, RX VrefLevel [Byte0]: 36
1723 11:13:17.548074 [Byte1]: 36
1724 11:13:17.552297
1725 11:13:17.552815 Set Vref, RX VrefLevel [Byte0]: 37
1726 11:13:17.555243 [Byte1]: 37
1727 11:13:17.559749
1728 11:13:17.560219 Set Vref, RX VrefLevel [Byte0]: 38
1729 11:13:17.563022 [Byte1]: 38
1730 11:13:17.567391
1731 11:13:17.567838 Set Vref, RX VrefLevel [Byte0]: 39
1732 11:13:17.570354 [Byte1]: 39
1733 11:13:17.574426
1734 11:13:17.574850 Set Vref, RX VrefLevel [Byte0]: 40
1735 11:13:17.577857 [Byte1]: 40
1736 11:13:17.582253
1737 11:13:17.582694 Set Vref, RX VrefLevel [Byte0]: 41
1738 11:13:17.585610 [Byte1]: 41
1739 11:13:17.589552
1740 11:13:17.590040 Set Vref, RX VrefLevel [Byte0]: 42
1741 11:13:17.593488 [Byte1]: 42
1742 11:13:17.597456
1743 11:13:17.597787 Set Vref, RX VrefLevel [Byte0]: 43
1744 11:13:17.600385 [Byte1]: 43
1745 11:13:17.604346
1746 11:13:17.604439 Set Vref, RX VrefLevel [Byte0]: 44
1747 11:13:17.607581 [Byte1]: 44
1748 11:13:17.612156
1749 11:13:17.612240 Set Vref, RX VrefLevel [Byte0]: 45
1750 11:13:17.615495 [Byte1]: 45
1751 11:13:17.619566
1752 11:13:17.619648 Set Vref, RX VrefLevel [Byte0]: 46
1753 11:13:17.622801 [Byte1]: 46
1754 11:13:17.626950
1755 11:13:17.627085 Set Vref, RX VrefLevel [Byte0]: 47
1756 11:13:17.630447 [Byte1]: 47
1757 11:13:17.635082
1758 11:13:17.635196 Set Vref, RX VrefLevel [Byte0]: 48
1759 11:13:17.638232 [Byte1]: 48
1760 11:13:17.642580
1761 11:13:17.642668 Set Vref, RX VrefLevel [Byte0]: 49
1762 11:13:17.645352 [Byte1]: 49
1763 11:13:17.649992
1764 11:13:17.650076 Set Vref, RX VrefLevel [Byte0]: 50
1765 11:13:17.653119 [Byte1]: 50
1766 11:13:17.657088
1767 11:13:17.657184 Set Vref, RX VrefLevel [Byte0]: 51
1768 11:13:17.660825 [Byte1]: 51
1769 11:13:17.664950
1770 11:13:17.665054 Set Vref, RX VrefLevel [Byte0]: 52
1771 11:13:17.668145 [Byte1]: 52
1772 11:13:17.672573
1773 11:13:17.672680 Set Vref, RX VrefLevel [Byte0]: 53
1774 11:13:17.675545 [Byte1]: 53
1775 11:13:17.679933
1776 11:13:17.680037 Set Vref, RX VrefLevel [Byte0]: 54
1777 11:13:17.683198 [Byte1]: 54
1778 11:13:17.687848
1779 11:13:17.687956 Set Vref, RX VrefLevel [Byte0]: 55
1780 11:13:17.691224 [Byte1]: 55
1781 11:13:17.695017
1782 11:13:17.695124 Set Vref, RX VrefLevel [Byte0]: 56
1783 11:13:17.698355 [Byte1]: 56
1784 11:13:17.702994
1785 11:13:17.703097 Set Vref, RX VrefLevel [Byte0]: 57
1786 11:13:17.706081 [Byte1]: 57
1787 11:13:17.709979
1788 11:13:17.710084 Set Vref, RX VrefLevel [Byte0]: 58
1789 11:13:17.713904 [Byte1]: 58
1790 11:13:17.717731
1791 11:13:17.717839 Set Vref, RX VrefLevel [Byte0]: 59
1792 11:13:17.721241 [Byte1]: 59
1793 11:13:17.725272
1794 11:13:17.725364 Set Vref, RX VrefLevel [Byte0]: 60
1795 11:13:17.728759 [Byte1]: 60
1796 11:13:17.732736
1797 11:13:17.732820 Set Vref, RX VrefLevel [Byte0]: 61
1798 11:13:17.736107 [Byte1]: 61
1799 11:13:17.740264
1800 11:13:17.740348 Set Vref, RX VrefLevel [Byte0]: 62
1801 11:13:17.743420 [Byte1]: 62
1802 11:13:17.747972
1803 11:13:17.748068 Set Vref, RX VrefLevel [Byte0]: 63
1804 11:13:17.751207 [Byte1]: 63
1805 11:13:17.755687
1806 11:13:17.755771 Set Vref, RX VrefLevel [Byte0]: 64
1807 11:13:17.758521 [Byte1]: 64
1808 11:13:17.762989
1809 11:13:17.763092 Set Vref, RX VrefLevel [Byte0]: 65
1810 11:13:17.766206 [Byte1]: 65
1811 11:13:17.770840
1812 11:13:17.770922 Set Vref, RX VrefLevel [Byte0]: 66
1813 11:13:17.774283 [Byte1]: 66
1814 11:13:17.777984
1815 11:13:17.778117 Set Vref, RX VrefLevel [Byte0]: 67
1816 11:13:17.781334 [Byte1]: 67
1817 11:13:17.785778
1818 11:13:17.785913 Set Vref, RX VrefLevel [Byte0]: 68
1819 11:13:17.788909 [Byte1]: 68
1820 11:13:17.793090
1821 11:13:17.796454 Set Vref, RX VrefLevel [Byte0]: 69
1822 11:13:17.796577 [Byte1]: 69
1823 11:13:17.801189
1824 11:13:17.801325 Set Vref, RX VrefLevel [Byte0]: 70
1825 11:13:17.804349 [Byte1]: 70
1826 11:13:17.808345
1827 11:13:17.808528 Set Vref, RX VrefLevel [Byte0]: 71
1828 11:13:17.811524 [Byte1]: 71
1829 11:13:17.816068
1830 11:13:17.816151 Final RX Vref Byte 0 = 58 to rank0
1831 11:13:17.819234 Final RX Vref Byte 1 = 55 to rank0
1832 11:13:17.822569 Final RX Vref Byte 0 = 58 to rank1
1833 11:13:17.826039 Final RX Vref Byte 1 = 55 to rank1==
1834 11:13:17.829375 Dram Type= 6, Freq= 0, CH_1, rank 0
1835 11:13:17.832881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 11:13:17.836202 ==
1837 11:13:17.836290 DQS Delay:
1838 11:13:17.836365 DQS0 = 0, DQS1 = 0
1839 11:13:17.839599 DQM Delay:
1840 11:13:17.839698 DQM0 = 96, DQM1 = 92
1841 11:13:17.842340 DQ Delay:
1842 11:13:17.845854 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1843 11:13:17.849251 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1844 11:13:17.849362 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =84
1845 11:13:17.856424 DQ12 =96, DQ13 =100, DQ14 =100, DQ15 =100
1846 11:13:17.856559
1847 11:13:17.856688
1848 11:13:17.862821 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1849 11:13:17.866375 CH1 RK0: MR19=606, MR18=2A47
1850 11:13:17.872944 CH1_RK0: MR19=0x606, MR18=0x2A47, DQSOSC=392, MR23=63, INC=96, DEC=64
1851 11:13:17.873256
1852 11:13:17.876302 ----->DramcWriteLeveling(PI) begin...
1853 11:13:17.876551 ==
1854 11:13:17.879549 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 11:13:17.883416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 11:13:17.883818 ==
1857 11:13:17.886689 Write leveling (Byte 0): 27 => 27
1858 11:13:17.889534 Write leveling (Byte 1): 29 => 29
1859 11:13:17.893350 DramcWriteLeveling(PI) end<-----
1860 11:13:17.893814
1861 11:13:17.894159 ==
1862 11:13:17.896477 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 11:13:17.899673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 11:13:17.900106 ==
1865 11:13:17.903351 [Gating] SW mode calibration
1866 11:13:17.909857 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1867 11:13:17.916282 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1868 11:13:17.919686 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1869 11:13:17.922851 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1870 11:13:17.930101 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:13:17.933445 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:13:17.936275 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:13:17.942831 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:13:17.946662 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:13:17.950060 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:13:17.957033 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:13:17.960220 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:13:17.963551 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:13:17.970088 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:13:17.973006 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:13:17.976429 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:13:17.980246 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:13:17.986646 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:13:17.989884 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1885 11:13:17.993195 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1886 11:13:17.999777 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:13:18.003090 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:13:18.006433 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:13:18.013215 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:13:18.016371 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:13:18.019654 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:13:18.026439 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:13:18.029604 0 9 4 | B1->B0 | 2727 2323 | 1 1 | (1 1) (1 1)
1894 11:13:18.033089 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1895 11:13:18.039804 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 11:13:18.043168 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 11:13:18.046497 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 11:13:18.049748 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 11:13:18.056952 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 11:13:18.060181 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 11:13:18.063464 0 10 4 | B1->B0 | 2727 3131 | 1 0 | (1 0) (0 1)
1902 11:13:18.070165 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1903 11:13:18.073434 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:13:18.076687 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:13:18.083276 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:13:18.086920 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:13:18.089594 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:13:18.096660 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1909 11:13:18.100015 0 11 4 | B1->B0 | 3a3a 2b2b | 0 0 | (0 0) (0 0)
1910 11:13:18.103261 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1911 11:13:18.109665 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 11:13:18.113061 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 11:13:18.116543 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 11:13:18.122859 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 11:13:18.126590 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 11:13:18.129667 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 11:13:18.136287 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 11:13:18.139834 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 11:13:18.143129 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 11:13:18.149869 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 11:13:18.153143 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 11:13:18.156686 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 11:13:18.160070 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 11:13:18.166651 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 11:13:18.170114 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:13:18.172879 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:13:18.179629 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:13:18.182859 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:13:18.186766 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:13:18.193211 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:13:18.196532 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:13:18.200384 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:13:18.207065 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1934 11:13:18.207154 Total UI for P1: 0, mck2ui 16
1935 11:13:18.213379 best dqsien dly found for B1: ( 0, 14, 2)
1936 11:13:18.216719 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 11:13:18.220000 Total UI for P1: 0, mck2ui 16
1938 11:13:18.223277 best dqsien dly found for B0: ( 0, 14, 4)
1939 11:13:18.226455 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1940 11:13:18.229630 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1941 11:13:18.229715
1942 11:13:18.232876 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1943 11:13:18.236458 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1944 11:13:18.239951 [Gating] SW calibration Done
1945 11:13:18.240035 ==
1946 11:13:18.243190 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 11:13:18.246482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 11:13:18.246599 ==
1949 11:13:18.249733 RX Vref Scan: 0
1950 11:13:18.249822
1951 11:13:18.253190 RX Vref 0 -> 0, step: 1
1952 11:13:18.253286
1953 11:13:18.253362 RX Delay -130 -> 252, step: 16
1954 11:13:18.259731 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1955 11:13:18.262944 iDelay=222, Bit 1, Center 93 (-2 ~ 189) 192
1956 11:13:18.266449 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1957 11:13:18.269696 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1958 11:13:18.273006 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1959 11:13:18.276346 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1960 11:13:18.283089 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1961 11:13:18.286842 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1962 11:13:18.290084 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1963 11:13:18.293409 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1964 11:13:18.296673 iDelay=222, Bit 10, Center 101 (-2 ~ 205) 208
1965 11:13:18.303240 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1966 11:13:18.307066 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1967 11:13:18.309701 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1968 11:13:18.313051 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1969 11:13:18.319949 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1970 11:13:18.320041 ==
1971 11:13:18.323460 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 11:13:18.326713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 11:13:18.326834 ==
1974 11:13:18.326933 DQS Delay:
1975 11:13:18.330226 DQS0 = 0, DQS1 = 0
1976 11:13:18.330330 DQM Delay:
1977 11:13:18.333267 DQM0 = 96, DQM1 = 93
1978 11:13:18.333367 DQ Delay:
1979 11:13:18.336835 DQ0 =101, DQ1 =93, DQ2 =77, DQ3 =93
1980 11:13:18.339982 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =101
1981 11:13:18.343107 DQ8 =77, DQ9 =77, DQ10 =101, DQ11 =85
1982 11:13:18.346885 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1983 11:13:18.346993
1984 11:13:18.347096
1985 11:13:18.347188 ==
1986 11:13:18.349817 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 11:13:18.353126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 11:13:18.356511 ==
1989 11:13:18.356592
1990 11:13:18.356657
1991 11:13:18.356717 TX Vref Scan disable
1992 11:13:18.359652 == TX Byte 0 ==
1993 11:13:18.363655 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1994 11:13:18.366449 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1995 11:13:18.369746 == TX Byte 1 ==
1996 11:13:18.373067 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1997 11:13:18.376635 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1998 11:13:18.376756 ==
1999 11:13:18.379948 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 11:13:18.386291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 11:13:18.386386 ==
2002 11:13:18.398809 TX Vref=22, minBit 0, minWin=26, winSum=439
2003 11:13:18.402291 TX Vref=24, minBit 3, minWin=26, winSum=443
2004 11:13:18.405601 TX Vref=26, minBit 1, minWin=27, winSum=449
2005 11:13:18.409175 TX Vref=28, minBit 1, minWin=27, winSum=450
2006 11:13:18.412650 TX Vref=30, minBit 4, minWin=27, winSum=454
2007 11:13:18.415709 TX Vref=32, minBit 1, minWin=27, winSum=449
2008 11:13:18.422551 [TxChooseVref] Worse bit 4, Min win 27, Win sum 454, Final Vref 30
2009 11:13:18.423005
2010 11:13:18.425801 Final TX Range 1 Vref 30
2011 11:13:18.426313
2012 11:13:18.426659 ==
2013 11:13:18.428964 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 11:13:18.432519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 11:13:18.432949 ==
2016 11:13:18.433282
2017 11:13:18.433630
2018 11:13:18.435723 TX Vref Scan disable
2019 11:13:18.438937 == TX Byte 0 ==
2020 11:13:18.442349 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2021 11:13:18.445912 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2022 11:13:18.449089 == TX Byte 1 ==
2023 11:13:18.452874 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 11:13:18.455853 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 11:13:18.456300
2026 11:13:18.459175 [DATLAT]
2027 11:13:18.459673 Freq=800, CH1 RK1
2028 11:13:18.460020
2029 11:13:18.462502 DATLAT Default: 0xa
2030 11:13:18.463068 0, 0xFFFF, sum = 0
2031 11:13:18.465953 1, 0xFFFF, sum = 0
2032 11:13:18.466418 2, 0xFFFF, sum = 0
2033 11:13:18.469378 3, 0xFFFF, sum = 0
2034 11:13:18.469959 4, 0xFFFF, sum = 0
2035 11:13:18.472733 5, 0xFFFF, sum = 0
2036 11:13:18.473290 6, 0xFFFF, sum = 0
2037 11:13:18.476194 7, 0xFFFF, sum = 0
2038 11:13:18.476716 8, 0xFFFF, sum = 0
2039 11:13:18.479618 9, 0x0, sum = 1
2040 11:13:18.480055 10, 0x0, sum = 2
2041 11:13:18.482458 11, 0x0, sum = 3
2042 11:13:18.482919 12, 0x0, sum = 4
2043 11:13:18.485619 best_step = 10
2044 11:13:18.486032
2045 11:13:18.486478 ==
2046 11:13:18.489196 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 11:13:18.492528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 11:13:18.492964 ==
2049 11:13:18.495820 RX Vref Scan: 0
2050 11:13:18.496282
2051 11:13:18.496631 RX Vref 0 -> 0, step: 1
2052 11:13:18.496993
2053 11:13:18.499051 RX Delay -79 -> 252, step: 8
2054 11:13:18.505552 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2055 11:13:18.509675 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2056 11:13:18.512551 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2057 11:13:18.515688 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2058 11:13:18.519465 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2059 11:13:18.522610 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2060 11:13:18.529245 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2061 11:13:18.532337 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2062 11:13:18.535563 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2063 11:13:18.539405 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2064 11:13:18.542724 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2065 11:13:18.549038 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2066 11:13:18.552011 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2067 11:13:18.555821 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2068 11:13:18.559139 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2069 11:13:18.562124 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2070 11:13:18.562208 ==
2071 11:13:18.565317 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 11:13:18.572081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 11:13:18.572188 ==
2074 11:13:18.572295 DQS Delay:
2075 11:13:18.576022 DQS0 = 0, DQS1 = 0
2076 11:13:18.576097 DQM Delay:
2077 11:13:18.576176 DQM0 = 97, DQM1 = 91
2078 11:13:18.579316 DQ Delay:
2079 11:13:18.582226 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2080 11:13:18.585596 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2081 11:13:18.588868 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2082 11:13:18.592348 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2083 11:13:18.592487
2084 11:13:18.592615
2085 11:13:18.599162 [DQSOSCAuto] RK1, (LSB)MR18= 0x4712, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2086 11:13:18.602700 CH1 RK1: MR19=606, MR18=4712
2087 11:13:18.609199 CH1_RK1: MR19=0x606, MR18=0x4712, DQSOSC=392, MR23=63, INC=96, DEC=64
2088 11:13:18.612458 [RxdqsGatingPostProcess] freq 800
2089 11:13:18.615714 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 11:13:18.619177 Pre-setting of DQS Precalculation
2091 11:13:18.625800 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 11:13:18.632584 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 11:13:18.639278 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 11:13:18.639413
2095 11:13:18.639497
2096 11:13:18.642791 [Calibration Summary] 1600 Mbps
2097 11:13:18.642871 CH 0, Rank 0
2098 11:13:18.645855 SW Impedance : PASS
2099 11:13:18.648992 DUTY Scan : NO K
2100 11:13:18.649072 ZQ Calibration : PASS
2101 11:13:18.652286 Jitter Meter : NO K
2102 11:13:18.655578 CBT Training : PASS
2103 11:13:18.655688 Write leveling : PASS
2104 11:13:18.658790 RX DQS gating : PASS
2105 11:13:18.662620 RX DQ/DQS(RDDQC) : PASS
2106 11:13:18.662704 TX DQ/DQS : PASS
2107 11:13:18.665690 RX DATLAT : PASS
2108 11:13:18.665773 RX DQ/DQS(Engine): PASS
2109 11:13:18.668890 TX OE : NO K
2110 11:13:18.668973 All Pass.
2111 11:13:18.669040
2112 11:13:18.672531 CH 0, Rank 1
2113 11:13:18.672615 SW Impedance : PASS
2114 11:13:18.675858 DUTY Scan : NO K
2115 11:13:18.679196 ZQ Calibration : PASS
2116 11:13:18.679305 Jitter Meter : NO K
2117 11:13:18.682626 CBT Training : PASS
2118 11:13:18.685972 Write leveling : PASS
2119 11:13:18.686056 RX DQS gating : PASS
2120 11:13:18.689294 RX DQ/DQS(RDDQC) : PASS
2121 11:13:18.692642 TX DQ/DQS : PASS
2122 11:13:18.692726 RX DATLAT : PASS
2123 11:13:18.696091 RX DQ/DQS(Engine): PASS
2124 11:13:18.698898 TX OE : NO K
2125 11:13:18.698997 All Pass.
2126 11:13:18.699066
2127 11:13:18.699132 CH 1, Rank 0
2128 11:13:18.702037 SW Impedance : PASS
2129 11:13:18.705531 DUTY Scan : NO K
2130 11:13:18.705615 ZQ Calibration : PASS
2131 11:13:18.709009 Jitter Meter : NO K
2132 11:13:18.712237 CBT Training : PASS
2133 11:13:18.712389 Write leveling : PASS
2134 11:13:18.715467 RX DQS gating : PASS
2135 11:13:18.715551 RX DQ/DQS(RDDQC) : PASS
2136 11:13:18.718814 TX DQ/DQS : PASS
2137 11:13:18.722189 RX DATLAT : PASS
2138 11:13:18.722272 RX DQ/DQS(Engine): PASS
2139 11:13:18.725554 TX OE : NO K
2140 11:13:18.725631 All Pass.
2141 11:13:18.725694
2142 11:13:18.728789 CH 1, Rank 1
2143 11:13:18.728865 SW Impedance : PASS
2144 11:13:18.732011 DUTY Scan : NO K
2145 11:13:18.735866 ZQ Calibration : PASS
2146 11:13:18.735944 Jitter Meter : NO K
2147 11:13:18.739189 CBT Training : PASS
2148 11:13:18.742706 Write leveling : PASS
2149 11:13:18.742785 RX DQS gating : PASS
2150 11:13:18.745739 RX DQ/DQS(RDDQC) : PASS
2151 11:13:18.748899 TX DQ/DQS : PASS
2152 11:13:18.748974 RX DATLAT : PASS
2153 11:13:18.752517 RX DQ/DQS(Engine): PASS
2154 11:13:18.752601 TX OE : NO K
2155 11:13:18.756109 All Pass.
2156 11:13:18.756192
2157 11:13:18.756278 DramC Write-DBI off
2158 11:13:18.759269 PER_BANK_REFRESH: Hybrid Mode
2159 11:13:18.762505 TX_TRACKING: ON
2160 11:13:18.765565 [GetDramInforAfterCalByMRR] Vendor 6.
2161 11:13:18.768854 [GetDramInforAfterCalByMRR] Revision 606.
2162 11:13:18.772567 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 11:13:18.772646 MR0 0x3b3b
2164 11:13:18.772728 MR8 0x5151
2165 11:13:18.778968 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 11:13:18.779074
2167 11:13:18.779188 MR0 0x3b3b
2168 11:13:18.779299 MR8 0x5151
2169 11:13:18.782120 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 11:13:18.782236
2171 11:13:18.792283 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 11:13:18.795681 [FAST_K] Save calibration result to emmc
2173 11:13:18.799089 [FAST_K] Save calibration result to emmc
2174 11:13:18.802433 dram_init: config_dvfs: 1
2175 11:13:18.805812 dramc_set_vcore_voltage set vcore to 662500
2176 11:13:18.809043 Read voltage for 1200, 2
2177 11:13:18.809129 Vio18 = 0
2178 11:13:18.809209 Vcore = 662500
2179 11:13:18.812387 Vdram = 0
2180 11:13:18.812461 Vddq = 0
2181 11:13:18.812550 Vmddr = 0
2182 11:13:18.818872 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 11:13:18.822630 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 11:13:18.825878 MEM_TYPE=3, freq_sel=15
2185 11:13:18.829009 sv_algorithm_assistance_LP4_1600
2186 11:13:18.832318 ============ PULL DRAM RESETB DOWN ============
2187 11:13:18.835669 ========== PULL DRAM RESETB DOWN end =========
2188 11:13:18.842388 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 11:13:18.845597 ===================================
2190 11:13:18.849518 LPDDR4 DRAM CONFIGURATION
2191 11:13:18.849628 ===================================
2192 11:13:18.852526 EX_ROW_EN[0] = 0x0
2193 11:13:18.855622 EX_ROW_EN[1] = 0x0
2194 11:13:18.855729 LP4Y_EN = 0x0
2195 11:13:18.859095 WORK_FSP = 0x0
2196 11:13:18.859180 WL = 0x4
2197 11:13:18.862586 RL = 0x4
2198 11:13:18.862659 BL = 0x2
2199 11:13:18.865931 RPST = 0x0
2200 11:13:18.866015 RD_PRE = 0x0
2201 11:13:18.869159 WR_PRE = 0x1
2202 11:13:18.869241 WR_PST = 0x0
2203 11:13:18.872392 DBI_WR = 0x0
2204 11:13:18.872474 DBI_RD = 0x0
2205 11:13:18.876025 OTF = 0x1
2206 11:13:18.878986 ===================================
2207 11:13:18.882431 ===================================
2208 11:13:18.882513 ANA top config
2209 11:13:18.885580 ===================================
2210 11:13:18.889239 DLL_ASYNC_EN = 0
2211 11:13:18.892440 ALL_SLAVE_EN = 0
2212 11:13:18.895691 NEW_RANK_MODE = 1
2213 11:13:18.895774 DLL_IDLE_MODE = 1
2214 11:13:18.899064 LP45_APHY_COMB_EN = 1
2215 11:13:18.902289 TX_ODT_DIS = 1
2216 11:13:18.906262 NEW_8X_MODE = 1
2217 11:13:18.909499 ===================================
2218 11:13:18.912207 ===================================
2219 11:13:18.916166 data_rate = 2400
2220 11:13:18.916276 CKR = 1
2221 11:13:18.919462 DQ_P2S_RATIO = 8
2222 11:13:18.922775 ===================================
2223 11:13:18.926099 CA_P2S_RATIO = 8
2224 11:13:18.929346 DQ_CA_OPEN = 0
2225 11:13:18.932517 DQ_SEMI_OPEN = 0
2226 11:13:18.935631 CA_SEMI_OPEN = 0
2227 11:13:18.935711 CA_FULL_RATE = 0
2228 11:13:18.938982 DQ_CKDIV4_EN = 0
2229 11:13:18.942776 CA_CKDIV4_EN = 0
2230 11:13:18.946373 CA_PREDIV_EN = 0
2231 11:13:18.949375 PH8_DLY = 17
2232 11:13:18.949477 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 11:13:18.952865 DQ_AAMCK_DIV = 4
2234 11:13:18.955971 CA_AAMCK_DIV = 4
2235 11:13:18.959187 CA_ADMCK_DIV = 4
2236 11:13:18.962303 DQ_TRACK_CA_EN = 0
2237 11:13:18.965978 CA_PICK = 1200
2238 11:13:18.968989 CA_MCKIO = 1200
2239 11:13:18.969062 MCKIO_SEMI = 0
2240 11:13:18.972704 PLL_FREQ = 2366
2241 11:13:18.975754 DQ_UI_PI_RATIO = 32
2242 11:13:18.979015 CA_UI_PI_RATIO = 0
2243 11:13:18.982774 ===================================
2244 11:13:18.985894 ===================================
2245 11:13:18.989501 memory_type:LPDDR4
2246 11:13:18.989578 GP_NUM : 10
2247 11:13:18.992374 SRAM_EN : 1
2248 11:13:18.992474 MD32_EN : 0
2249 11:13:18.996101 ===================================
2250 11:13:18.999058 [ANA_INIT] >>>>>>>>>>>>>>
2251 11:13:19.002369 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 11:13:19.005689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 11:13:19.009610 ===================================
2254 11:13:19.012987 data_rate = 2400,PCW = 0X5b00
2255 11:13:19.015576 ===================================
2256 11:13:19.019586 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 11:13:19.025627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 11:13:19.028989 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 11:13:19.036149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 11:13:19.039400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 11:13:19.042596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 11:13:19.042704 [ANA_INIT] flow start
2263 11:13:19.045773 [ANA_INIT] PLL >>>>>>>>
2264 11:13:19.049108 [ANA_INIT] PLL <<<<<<<<
2265 11:13:19.049197 [ANA_INIT] MIDPI >>>>>>>>
2266 11:13:19.052578 [ANA_INIT] MIDPI <<<<<<<<
2267 11:13:19.055933 [ANA_INIT] DLL >>>>>>>>
2268 11:13:19.056031 [ANA_INIT] DLL <<<<<<<<
2269 11:13:19.059038 [ANA_INIT] flow end
2270 11:13:19.063037 ============ LP4 DIFF to SE enter ============
2271 11:13:19.066143 ============ LP4 DIFF to SE exit ============
2272 11:13:19.069378 [ANA_INIT] <<<<<<<<<<<<<
2273 11:13:19.072721 [Flow] Enable top DCM control >>>>>
2274 11:13:19.075958 [Flow] Enable top DCM control <<<<<
2275 11:13:19.079638 Enable DLL master slave shuffle
2276 11:13:19.086255 ==============================================================
2277 11:13:19.086357 Gating Mode config
2278 11:13:19.092901 ==============================================================
2279 11:13:19.093006 Config description:
2280 11:13:19.102863 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 11:13:19.109694 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 11:13:19.116179 SELPH_MODE 0: By rank 1: By Phase
2283 11:13:19.119320 ==============================================================
2284 11:13:19.122618 GAT_TRACK_EN = 1
2285 11:13:19.126051 RX_GATING_MODE = 2
2286 11:13:19.129444 RX_GATING_TRACK_MODE = 2
2287 11:13:19.132774 SELPH_MODE = 1
2288 11:13:19.136007 PICG_EARLY_EN = 1
2289 11:13:19.139501 VALID_LAT_VALUE = 1
2290 11:13:19.142732 ==============================================================
2291 11:13:19.146586 Enter into Gating configuration >>>>
2292 11:13:19.149700 Exit from Gating configuration <<<<
2293 11:13:19.153035 Enter into DVFS_PRE_config >>>>>
2294 11:13:19.166241 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 11:13:19.169398 Exit from DVFS_PRE_config <<<<<
2296 11:13:19.172603 Enter into PICG configuration >>>>
2297 11:13:19.172705 Exit from PICG configuration <<<<
2298 11:13:19.176576 [RX_INPUT] configuration >>>>>
2299 11:13:19.179859 [RX_INPUT] configuration <<<<<
2300 11:13:19.186507 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 11:13:19.189434 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 11:13:19.195989 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 11:13:19.202999 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 11:13:19.210095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 11:13:19.216097 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 11:13:19.219788 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 11:13:19.223142 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 11:13:19.226503 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 11:13:19.233149 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 11:13:19.236608 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 11:13:19.239982 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 11:13:19.243242 ===================================
2313 11:13:19.246577 LPDDR4 DRAM CONFIGURATION
2314 11:13:19.249710 ===================================
2315 11:13:19.249818 EX_ROW_EN[0] = 0x0
2316 11:13:19.252941 EX_ROW_EN[1] = 0x0
2317 11:13:19.256126 LP4Y_EN = 0x0
2318 11:13:19.256198 WORK_FSP = 0x0
2319 11:13:19.260022 WL = 0x4
2320 11:13:19.260132 RL = 0x4
2321 11:13:19.263312 BL = 0x2
2322 11:13:19.263447 RPST = 0x0
2323 11:13:19.266573 RD_PRE = 0x0
2324 11:13:19.266679 WR_PRE = 0x1
2325 11:13:19.269829 WR_PST = 0x0
2326 11:13:19.269929 DBI_WR = 0x0
2327 11:13:19.273141 DBI_RD = 0x0
2328 11:13:19.273235 OTF = 0x1
2329 11:13:19.276233 ===================================
2330 11:13:19.279495 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 11:13:19.286601 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 11:13:19.290038 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 11:13:19.293261 ===================================
2334 11:13:19.296612 LPDDR4 DRAM CONFIGURATION
2335 11:13:19.299620 ===================================
2336 11:13:19.299710 EX_ROW_EN[0] = 0x10
2337 11:13:19.303133 EX_ROW_EN[1] = 0x0
2338 11:13:19.303235 LP4Y_EN = 0x0
2339 11:13:19.306150 WORK_FSP = 0x0
2340 11:13:19.306253 WL = 0x4
2341 11:13:19.309616 RL = 0x4
2342 11:13:19.309716 BL = 0x2
2343 11:13:19.313052 RPST = 0x0
2344 11:13:19.316258 RD_PRE = 0x0
2345 11:13:19.316332 WR_PRE = 0x1
2346 11:13:19.319437 WR_PST = 0x0
2347 11:13:19.319510 DBI_WR = 0x0
2348 11:13:19.323070 DBI_RD = 0x0
2349 11:13:19.323171 OTF = 0x1
2350 11:13:19.326091 ===================================
2351 11:13:19.333136 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 11:13:19.333242 ==
2353 11:13:19.336356 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 11:13:19.339635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 11:13:19.339710 ==
2356 11:13:19.342971 [Duty_Offset_Calibration]
2357 11:13:19.343071 B0:2 B1:1 CA:1
2358 11:13:19.343161
2359 11:13:19.346272 [DutyScan_Calibration_Flow] k_type=0
2360 11:13:19.357342
2361 11:13:19.357444 ==CLK 0==
2362 11:13:19.360707 Final CLK duty delay cell = 0
2363 11:13:19.364465 [0] MAX Duty = 5156%(X100), DQS PI = 22
2364 11:13:19.367175 [0] MIN Duty = 4844%(X100), DQS PI = 48
2365 11:13:19.367278 [0] AVG Duty = 5000%(X100)
2366 11:13:19.371026
2367 11:13:19.374118 CH0 CLK Duty spec in!! Max-Min= 312%
2368 11:13:19.377584 [DutyScan_Calibration_Flow] ====Done====
2369 11:13:19.377684
2370 11:13:19.380764 [DutyScan_Calibration_Flow] k_type=1
2371 11:13:19.396084
2372 11:13:19.396167 ==DQS 0 ==
2373 11:13:19.399350 Final DQS duty delay cell = -4
2374 11:13:19.402609 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2375 11:13:19.405740 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2376 11:13:19.409500 [-4] AVG Duty = 4953%(X100)
2377 11:13:19.409585
2378 11:13:19.409649 ==DQS 1 ==
2379 11:13:19.413156 Final DQS duty delay cell = 0
2380 11:13:19.416048 [0] MAX Duty = 5156%(X100), DQS PI = 0
2381 11:13:19.419589 [0] MIN Duty = 5031%(X100), DQS PI = 32
2382 11:13:19.422878 [0] AVG Duty = 5093%(X100)
2383 11:13:19.422954
2384 11:13:19.426110 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2385 11:13:19.426193
2386 11:13:19.429704 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2387 11:13:19.432731 [DutyScan_Calibration_Flow] ====Done====
2388 11:13:19.432819
2389 11:13:19.436332 [DutyScan_Calibration_Flow] k_type=3
2390 11:13:19.453004
2391 11:13:19.453084 ==DQM 0 ==
2392 11:13:19.456393 Final DQM duty delay cell = 0
2393 11:13:19.459639 [0] MAX Duty = 5156%(X100), DQS PI = 30
2394 11:13:19.463046 [0] MIN Duty = 4906%(X100), DQS PI = 58
2395 11:13:19.466321 [0] AVG Duty = 5031%(X100)
2396 11:13:19.466432
2397 11:13:19.466530 ==DQM 1 ==
2398 11:13:19.469446 Final DQM duty delay cell = 0
2399 11:13:19.472643 [0] MAX Duty = 5093%(X100), DQS PI = 0
2400 11:13:19.475983 [0] MIN Duty = 5031%(X100), DQS PI = 14
2401 11:13:19.476093 [0] AVG Duty = 5062%(X100)
2402 11:13:19.479358
2403 11:13:19.482534 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2404 11:13:19.482654
2405 11:13:19.486353 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2406 11:13:19.489657 [DutyScan_Calibration_Flow] ====Done====
2407 11:13:19.489764
2408 11:13:19.492964 [DutyScan_Calibration_Flow] k_type=2
2409 11:13:19.509537
2410 11:13:19.509651 ==DQ 0 ==
2411 11:13:19.512752 Final DQ duty delay cell = 0
2412 11:13:19.516054 [0] MAX Duty = 5031%(X100), DQS PI = 24
2413 11:13:19.519243 [0] MIN Duty = 4875%(X100), DQS PI = 62
2414 11:13:19.519391 [0] AVG Duty = 4953%(X100)
2415 11:13:19.522348
2416 11:13:19.522517 ==DQ 1 ==
2417 11:13:19.526147 Final DQ duty delay cell = 0
2418 11:13:19.529254 [0] MAX Duty = 5093%(X100), DQS PI = 10
2419 11:13:19.532490 [0] MIN Duty = 4969%(X100), DQS PI = 2
2420 11:13:19.532573 [0] AVG Duty = 5031%(X100)
2421 11:13:19.532655
2422 11:13:19.536245 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2423 11:13:19.536337
2424 11:13:19.542525 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2425 11:13:19.545771 [DutyScan_Calibration_Flow] ====Done====
2426 11:13:19.545848 ==
2427 11:13:19.549574 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 11:13:19.552745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 11:13:19.552830 ==
2430 11:13:19.555884 [Duty_Offset_Calibration]
2431 11:13:19.555960 B0:1 B1:0 CA:1
2432 11:13:19.556047
2433 11:13:19.559215 [DutyScan_Calibration_Flow] k_type=0
2434 11:13:19.568475
2435 11:13:19.568562 ==CLK 0==
2436 11:13:19.571752 Final CLK duty delay cell = -4
2437 11:13:19.575047 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2438 11:13:19.578131 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2439 11:13:19.581822 [-4] AVG Duty = 4969%(X100)
2440 11:13:19.581927
2441 11:13:19.585252 CH1 CLK Duty spec in!! Max-Min= 124%
2442 11:13:19.588445 [DutyScan_Calibration_Flow] ====Done====
2443 11:13:19.588543
2444 11:13:19.591651 [DutyScan_Calibration_Flow] k_type=1
2445 11:13:19.608512
2446 11:13:19.608594 ==DQS 0 ==
2447 11:13:19.611354 Final DQS duty delay cell = 0
2448 11:13:19.614670 [0] MAX Duty = 5062%(X100), DQS PI = 24
2449 11:13:19.618008 [0] MIN Duty = 4844%(X100), DQS PI = 0
2450 11:13:19.618086 [0] AVG Duty = 4953%(X100)
2451 11:13:19.621309
2452 11:13:19.621394 ==DQS 1 ==
2453 11:13:19.625255 Final DQS duty delay cell = 0
2454 11:13:19.627957 [0] MAX Duty = 5218%(X100), DQS PI = 20
2455 11:13:19.631295 [0] MIN Duty = 4969%(X100), DQS PI = 10
2456 11:13:19.631412 [0] AVG Duty = 5093%(X100)
2457 11:13:19.634987
2458 11:13:19.638145 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2459 11:13:19.638229
2460 11:13:19.641323 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2461 11:13:19.645041 [DutyScan_Calibration_Flow] ====Done====
2462 11:13:19.645124
2463 11:13:19.648212 [DutyScan_Calibration_Flow] k_type=3
2464 11:13:19.665085
2465 11:13:19.665168 ==DQM 0 ==
2466 11:13:19.668371 Final DQM duty delay cell = 0
2467 11:13:19.671746 [0] MAX Duty = 5156%(X100), DQS PI = 6
2468 11:13:19.675066 [0] MIN Duty = 5031%(X100), DQS PI = 0
2469 11:13:19.675149 [0] AVG Duty = 5093%(X100)
2470 11:13:19.675214
2471 11:13:19.678349 ==DQM 1 ==
2472 11:13:19.681716 Final DQM duty delay cell = 0
2473 11:13:19.684705 [0] MAX Duty = 5031%(X100), DQS PI = 16
2474 11:13:19.687891 [0] MIN Duty = 4907%(X100), DQS PI = 36
2475 11:13:19.687974 [0] AVG Duty = 4969%(X100)
2476 11:13:19.691743
2477 11:13:19.694815 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2478 11:13:19.694901
2479 11:13:19.698075 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2480 11:13:19.701344 [DutyScan_Calibration_Flow] ====Done====
2481 11:13:19.701427
2482 11:13:19.704630 [DutyScan_Calibration_Flow] k_type=2
2483 11:13:19.720550
2484 11:13:19.720632 ==DQ 0 ==
2485 11:13:19.723786 Final DQ duty delay cell = -4
2486 11:13:19.727050 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2487 11:13:19.730773 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2488 11:13:19.730848 [-4] AVG Duty = 4984%(X100)
2489 11:13:19.733731
2490 11:13:19.733834 ==DQ 1 ==
2491 11:13:19.737611 Final DQ duty delay cell = 0
2492 11:13:19.740811 [0] MAX Duty = 5125%(X100), DQS PI = 20
2493 11:13:19.743936 [0] MIN Duty = 4938%(X100), DQS PI = 34
2494 11:13:19.744038 [0] AVG Duty = 5031%(X100)
2495 11:13:19.744135
2496 11:13:19.747224 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2497 11:13:19.750984
2498 11:13:19.754276 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2499 11:13:19.757411 [DutyScan_Calibration_Flow] ====Done====
2500 11:13:19.761022 nWR fixed to 30
2501 11:13:19.761122 [ModeRegInit_LP4] CH0 RK0
2502 11:13:19.764307 [ModeRegInit_LP4] CH0 RK1
2503 11:13:19.767572 [ModeRegInit_LP4] CH1 RK0
2504 11:13:19.767643 [ModeRegInit_LP4] CH1 RK1
2505 11:13:19.770649 match AC timing 7
2506 11:13:19.773980 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 11:13:19.777383 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 11:13:19.784061 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 11:13:19.787251 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 11:13:19.794389 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 11:13:19.794471 ==
2512 11:13:19.797519 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 11:13:19.800621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 11:13:19.800700 ==
2515 11:13:19.807204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 11:13:19.810527 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 11:13:19.821124 [CA 0] Center 39 (8~70) winsize 63
2518 11:13:19.824348 [CA 1] Center 39 (8~70) winsize 63
2519 11:13:19.827617 [CA 2] Center 35 (5~66) winsize 62
2520 11:13:19.830938 [CA 3] Center 34 (4~65) winsize 62
2521 11:13:19.834180 [CA 4] Center 33 (3~64) winsize 62
2522 11:13:19.837349 [CA 5] Center 32 (3~62) winsize 60
2523 11:13:19.837427
2524 11:13:19.840392 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2525 11:13:19.840469
2526 11:13:19.844410 [CATrainingPosCal] consider 1 rank data
2527 11:13:19.847627 u2DelayCellTimex100 = 270/100 ps
2528 11:13:19.850811 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2529 11:13:19.854103 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2530 11:13:19.861065 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2531 11:13:19.864244 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2532 11:13:19.867498 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2533 11:13:19.870729 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2534 11:13:19.870812
2535 11:13:19.874456 CA PerBit enable=1, Macro0, CA PI delay=32
2536 11:13:19.874544
2537 11:13:19.877885 [CBTSetCACLKResult] CA Dly = 32
2538 11:13:19.877980 CS Dly: 6 (0~37)
2539 11:13:19.878056 ==
2540 11:13:19.881256 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 11:13:19.887884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 11:13:19.888010 ==
2543 11:13:19.891177 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 11:13:19.897672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2545 11:13:19.906506 [CA 0] Center 38 (8~69) winsize 62
2546 11:13:19.909649 [CA 1] Center 38 (8~69) winsize 62
2547 11:13:19.913357 [CA 2] Center 35 (4~66) winsize 63
2548 11:13:19.916633 [CA 3] Center 34 (4~65) winsize 62
2549 11:13:19.919492 [CA 4] Center 33 (3~64) winsize 62
2550 11:13:19.923394 [CA 5] Center 32 (2~62) winsize 61
2551 11:13:19.923477
2552 11:13:19.926589 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2553 11:13:19.926672
2554 11:13:19.930008 [CATrainingPosCal] consider 2 rank data
2555 11:13:19.933180 u2DelayCellTimex100 = 270/100 ps
2556 11:13:19.936432 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2557 11:13:19.939779 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2558 11:13:19.946251 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2559 11:13:19.949639 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2560 11:13:19.953454 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2561 11:13:19.956606 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2562 11:13:19.956689
2563 11:13:19.959685 CA PerBit enable=1, Macro0, CA PI delay=32
2564 11:13:19.959768
2565 11:13:19.963075 [CBTSetCACLKResult] CA Dly = 32
2566 11:13:19.963182 CS Dly: 6 (0~38)
2567 11:13:19.963277
2568 11:13:19.966161 ----->DramcWriteLeveling(PI) begin...
2569 11:13:19.969942 ==
2570 11:13:19.973072 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 11:13:19.976671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 11:13:19.976754 ==
2573 11:13:19.980083 Write leveling (Byte 0): 33 => 33
2574 11:13:19.983243 Write leveling (Byte 1): 29 => 29
2575 11:13:19.986495 DramcWriteLeveling(PI) end<-----
2576 11:13:19.986578
2577 11:13:19.986643 ==
2578 11:13:19.989747 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 11:13:19.993115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 11:13:19.993198 ==
2581 11:13:19.996386 [Gating] SW mode calibration
2582 11:13:20.003606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 11:13:20.006786 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 11:13:20.013612 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2585 11:13:20.016644 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2586 11:13:20.019807 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 11:13:20.026968 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 11:13:20.030068 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 11:13:20.033331 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 11:13:20.039937 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2591 11:13:20.043284 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2592 11:13:20.046415 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2593 11:13:20.052909 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 11:13:20.056163 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 11:13:20.060016 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 11:13:20.066243 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 11:13:20.070084 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 11:13:20.073184 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2599 11:13:20.079932 1 0 28 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
2600 11:13:20.083067 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2601 11:13:20.086121 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 11:13:20.093183 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 11:13:20.096588 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 11:13:20.099831 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 11:13:20.103299 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 11:13:20.109943 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 11:13:20.113207 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 11:13:20.116539 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 11:13:20.123217 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2610 11:13:20.126138 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 11:13:20.129839 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 11:13:20.136383 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 11:13:20.139733 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 11:13:20.142993 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 11:13:20.149571 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 11:13:20.153405 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 11:13:20.156134 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:13:20.163312 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:13:20.166552 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:13:20.169625 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:13:20.176264 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:13:20.180078 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:13:20.183136 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 11:13:20.190060 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2625 11:13:20.190144 Total UI for P1: 0, mck2ui 16
2626 11:13:20.193153 best dqsien dly found for B0: ( 1, 3, 28)
2627 11:13:20.199606 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 11:13:20.203097 Total UI for P1: 0, mck2ui 16
2629 11:13:20.206314 best dqsien dly found for B1: ( 1, 4, 0)
2630 11:13:20.209628 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2631 11:13:20.213041 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2632 11:13:20.213124
2633 11:13:20.216453 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2634 11:13:20.219809 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2635 11:13:20.223094 [Gating] SW calibration Done
2636 11:13:20.223176 ==
2637 11:13:20.226328 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 11:13:20.230159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 11:13:20.230267 ==
2640 11:13:20.233162 RX Vref Scan: 0
2641 11:13:20.233258
2642 11:13:20.233333 RX Vref 0 -> 0, step: 1
2643 11:13:20.233402
2644 11:13:20.236292 RX Delay -40 -> 252, step: 8
2645 11:13:20.240024 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2646 11:13:20.247150 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2647 11:13:20.249787 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2648 11:13:20.253200 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2649 11:13:20.256451 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2650 11:13:20.259920 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2651 11:13:20.266638 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2652 11:13:20.270013 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2653 11:13:20.273278 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2654 11:13:20.277102 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2655 11:13:20.280560 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2656 11:13:20.287063 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2657 11:13:20.290042 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2658 11:13:20.293764 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2659 11:13:20.296898 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2660 11:13:20.300642 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2661 11:13:20.301237 ==
2662 11:13:20.303513 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 11:13:20.310674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 11:13:20.311102 ==
2665 11:13:20.311488 DQS Delay:
2666 11:13:20.314040 DQS0 = 0, DQS1 = 0
2667 11:13:20.314466 DQM Delay:
2668 11:13:20.314804 DQM0 = 121, DQM1 = 113
2669 11:13:20.317365 DQ Delay:
2670 11:13:20.320692 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2671 11:13:20.324117 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2672 11:13:20.326876 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2673 11:13:20.330727 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2674 11:13:20.331173
2675 11:13:20.331561
2676 11:13:20.331881 ==
2677 11:13:20.333980 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 11:13:20.337306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 11:13:20.340474 ==
2680 11:13:20.340947
2681 11:13:20.341335
2682 11:13:20.341651 TX Vref Scan disable
2683 11:13:20.343471 == TX Byte 0 ==
2684 11:13:20.347080 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2685 11:13:20.350171 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2686 11:13:20.354007 == TX Byte 1 ==
2687 11:13:20.357191 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2688 11:13:20.360543 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2689 11:13:20.363747 ==
2690 11:13:20.364179 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 11:13:20.370825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 11:13:20.371465 ==
2693 11:13:20.381366 TX Vref=22, minBit 0, minWin=25, winSum=408
2694 11:13:20.384674 TX Vref=24, minBit 0, minWin=25, winSum=414
2695 11:13:20.388093 TX Vref=26, minBit 7, minWin=25, winSum=421
2696 11:13:20.391092 TX Vref=28, minBit 0, minWin=26, winSum=423
2697 11:13:20.394280 TX Vref=30, minBit 3, minWin=26, winSum=425
2698 11:13:20.397661 TX Vref=32, minBit 0, minWin=26, winSum=423
2699 11:13:20.404983 [TxChooseVref] Worse bit 3, Min win 26, Win sum 425, Final Vref 30
2700 11:13:20.405078
2701 11:13:20.407865 Final TX Range 1 Vref 30
2702 11:13:20.407973
2703 11:13:20.408066 ==
2704 11:13:20.411487 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 11:13:20.414867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 11:13:20.414955 ==
2707 11:13:20.415021
2708 11:13:20.417966
2709 11:13:20.418048 TX Vref Scan disable
2710 11:13:20.421358 == TX Byte 0 ==
2711 11:13:20.424526 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2712 11:13:20.427735 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2713 11:13:20.431096 == TX Byte 1 ==
2714 11:13:20.434482 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2715 11:13:20.437798 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2716 11:13:20.437877
2717 11:13:20.441123 [DATLAT]
2718 11:13:20.441197 Freq=1200, CH0 RK0
2719 11:13:20.441260
2720 11:13:20.444491 DATLAT Default: 0xd
2721 11:13:20.444563 0, 0xFFFF, sum = 0
2722 11:13:20.447650 1, 0xFFFF, sum = 0
2723 11:13:20.447728 2, 0xFFFF, sum = 0
2724 11:13:20.451022 3, 0xFFFF, sum = 0
2725 11:13:20.451095 4, 0xFFFF, sum = 0
2726 11:13:20.454219 5, 0xFFFF, sum = 0
2727 11:13:20.454292 6, 0xFFFF, sum = 0
2728 11:13:20.458023 7, 0xFFFF, sum = 0
2729 11:13:20.458097 8, 0xFFFF, sum = 0
2730 11:13:20.461688 9, 0xFFFF, sum = 0
2731 11:13:20.461762 10, 0xFFFF, sum = 0
2732 11:13:20.464945 11, 0xFFFF, sum = 0
2733 11:13:20.465038 12, 0x0, sum = 1
2734 11:13:20.468185 13, 0x0, sum = 2
2735 11:13:20.468272 14, 0x0, sum = 3
2736 11:13:20.471532 15, 0x0, sum = 4
2737 11:13:20.471620 best_step = 13
2738 11:13:20.471691
2739 11:13:20.471761 ==
2740 11:13:20.474901 Dram Type= 6, Freq= 0, CH_0, rank 0
2741 11:13:20.481676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2742 11:13:20.481766 ==
2743 11:13:20.481837 RX Vref Scan: 1
2744 11:13:20.481900
2745 11:13:20.485022 Set Vref Range= 32 -> 127
2746 11:13:20.485096
2747 11:13:20.488110 RX Vref 32 -> 127, step: 1
2748 11:13:20.488191
2749 11:13:20.491359 RX Delay -13 -> 252, step: 4
2750 11:13:20.491432
2751 11:13:20.494545 Set Vref, RX VrefLevel [Byte0]: 32
2752 11:13:20.497681 [Byte1]: 32
2753 11:13:20.497766
2754 11:13:20.501029 Set Vref, RX VrefLevel [Byte0]: 33
2755 11:13:20.504375 [Byte1]: 33
2756 11:13:20.504462
2757 11:13:20.507701 Set Vref, RX VrefLevel [Byte0]: 34
2758 11:13:20.510974 [Byte1]: 34
2759 11:13:20.515033
2760 11:13:20.515116 Set Vref, RX VrefLevel [Byte0]: 35
2761 11:13:20.518212 [Byte1]: 35
2762 11:13:20.523180
2763 11:13:20.523262 Set Vref, RX VrefLevel [Byte0]: 36
2764 11:13:20.526840 [Byte1]: 36
2765 11:13:20.530714
2766 11:13:20.530800 Set Vref, RX VrefLevel [Byte0]: 37
2767 11:13:20.534063 [Byte1]: 37
2768 11:13:20.539301
2769 11:13:20.539413 Set Vref, RX VrefLevel [Byte0]: 38
2770 11:13:20.542002 [Byte1]: 38
2771 11:13:20.546585
2772 11:13:20.546672 Set Vref, RX VrefLevel [Byte0]: 39
2773 11:13:20.549861 [Byte1]: 39
2774 11:13:20.554999
2775 11:13:20.555084 Set Vref, RX VrefLevel [Byte0]: 40
2776 11:13:20.557683 [Byte1]: 40
2777 11:13:20.562885
2778 11:13:20.562972 Set Vref, RX VrefLevel [Byte0]: 41
2779 11:13:20.566168 [Byte1]: 41
2780 11:13:20.570384
2781 11:13:20.570519 Set Vref, RX VrefLevel [Byte0]: 42
2782 11:13:20.574150 [Byte1]: 42
2783 11:13:20.578528
2784 11:13:20.578610 Set Vref, RX VrefLevel [Byte0]: 43
2785 11:13:20.581789 [Byte1]: 43
2786 11:13:20.586495
2787 11:13:20.586574 Set Vref, RX VrefLevel [Byte0]: 44
2788 11:13:20.589728 [Byte1]: 44
2789 11:13:20.594089
2790 11:13:20.594170 Set Vref, RX VrefLevel [Byte0]: 45
2791 11:13:20.597243 [Byte1]: 45
2792 11:13:20.602135
2793 11:13:20.602217 Set Vref, RX VrefLevel [Byte0]: 46
2794 11:13:20.605444 [Byte1]: 46
2795 11:13:20.610015
2796 11:13:20.610096 Set Vref, RX VrefLevel [Byte0]: 47
2797 11:13:20.613198 [Byte1]: 47
2798 11:13:20.618007
2799 11:13:20.618089 Set Vref, RX VrefLevel [Byte0]: 48
2800 11:13:20.621157 [Byte1]: 48
2801 11:13:20.625684
2802 11:13:20.625765 Set Vref, RX VrefLevel [Byte0]: 49
2803 11:13:20.628924 [Byte1]: 49
2804 11:13:20.633774
2805 11:13:20.633856 Set Vref, RX VrefLevel [Byte0]: 50
2806 11:13:20.636842 [Byte1]: 50
2807 11:13:20.641407
2808 11:13:20.641490 Set Vref, RX VrefLevel [Byte0]: 51
2809 11:13:20.644803 [Byte1]: 51
2810 11:13:20.649548
2811 11:13:20.649631 Set Vref, RX VrefLevel [Byte0]: 52
2812 11:13:20.652926 [Byte1]: 52
2813 11:13:20.657321
2814 11:13:20.657402 Set Vref, RX VrefLevel [Byte0]: 53
2815 11:13:20.660543 [Byte1]: 53
2816 11:13:20.665281
2817 11:13:20.665366 Set Vref, RX VrefLevel [Byte0]: 54
2818 11:13:20.668658 [Byte1]: 54
2819 11:13:20.673325
2820 11:13:20.673399 Set Vref, RX VrefLevel [Byte0]: 55
2821 11:13:20.676320 [Byte1]: 55
2822 11:13:20.681122
2823 11:13:20.681208 Set Vref, RX VrefLevel [Byte0]: 56
2824 11:13:20.684164 [Byte1]: 56
2825 11:13:20.688983
2826 11:13:20.689072 Set Vref, RX VrefLevel [Byte0]: 57
2827 11:13:20.692362 [Byte1]: 57
2828 11:13:20.696933
2829 11:13:20.697015 Set Vref, RX VrefLevel [Byte0]: 58
2830 11:13:20.699920 [Byte1]: 58
2831 11:13:20.704438
2832 11:13:20.704521 Set Vref, RX VrefLevel [Byte0]: 59
2833 11:13:20.708044 [Byte1]: 59
2834 11:13:20.712302
2835 11:13:20.712385 Set Vref, RX VrefLevel [Byte0]: 60
2836 11:13:20.715616 [Byte1]: 60
2837 11:13:20.720347
2838 11:13:20.720429 Set Vref, RX VrefLevel [Byte0]: 61
2839 11:13:20.723583 [Byte1]: 61
2840 11:13:20.728313
2841 11:13:20.728398 Set Vref, RX VrefLevel [Byte0]: 62
2842 11:13:20.731658 [Byte1]: 62
2843 11:13:20.736352
2844 11:13:20.736462 Set Vref, RX VrefLevel [Byte0]: 63
2845 11:13:20.739526 [Byte1]: 63
2846 11:13:20.743797
2847 11:13:20.743880 Set Vref, RX VrefLevel [Byte0]: 64
2848 11:13:20.747233 [Byte1]: 64
2849 11:13:20.751795
2850 11:13:20.751877 Set Vref, RX VrefLevel [Byte0]: 65
2851 11:13:20.755086 [Byte1]: 65
2852 11:13:20.759711
2853 11:13:20.759793 Set Vref, RX VrefLevel [Byte0]: 66
2854 11:13:20.762925 [Byte1]: 66
2855 11:13:20.767525
2856 11:13:20.767608 Set Vref, RX VrefLevel [Byte0]: 67
2857 11:13:20.770689 [Byte1]: 67
2858 11:13:20.775446
2859 11:13:20.775531 Set Vref, RX VrefLevel [Byte0]: 68
2860 11:13:20.778632 [Byte1]: 68
2861 11:13:20.783645
2862 11:13:20.783728 Final RX Vref Byte 0 = 55 to rank0
2863 11:13:20.786770 Final RX Vref Byte 1 = 47 to rank0
2864 11:13:20.789921 Final RX Vref Byte 0 = 55 to rank1
2865 11:13:20.793875 Final RX Vref Byte 1 = 47 to rank1==
2866 11:13:20.797046 Dram Type= 6, Freq= 0, CH_0, rank 0
2867 11:13:20.803587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 11:13:20.803671 ==
2869 11:13:20.803738 DQS Delay:
2870 11:13:20.803799 DQS0 = 0, DQS1 = 0
2871 11:13:20.806649 DQM Delay:
2872 11:13:20.806732 DQM0 = 120, DQM1 = 111
2873 11:13:20.810408 DQ Delay:
2874 11:13:20.813399 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2875 11:13:20.816718 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2876 11:13:20.820410 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
2877 11:13:20.823707 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2878 11:13:20.823790
2879 11:13:20.823855
2880 11:13:20.830277 [DQSOSCAuto] RK0, (LSB)MR18= 0x1710, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2881 11:13:20.833505 CH0 RK0: MR19=404, MR18=1710
2882 11:13:20.840294 CH0_RK0: MR19=0x404, MR18=0x1710, DQSOSC=401, MR23=63, INC=40, DEC=27
2883 11:13:20.840380
2884 11:13:20.843669 ----->DramcWriteLeveling(PI) begin...
2885 11:13:20.843754 ==
2886 11:13:20.847520 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 11:13:20.850650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 11:13:20.850751 ==
2889 11:13:20.853673 Write leveling (Byte 0): 33 => 33
2890 11:13:20.856889 Write leveling (Byte 1): 29 => 29
2891 11:13:20.860214 DramcWriteLeveling(PI) end<-----
2892 11:13:20.860298
2893 11:13:20.860364 ==
2894 11:13:20.863507 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 11:13:20.870569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 11:13:20.870654 ==
2897 11:13:20.870721 [Gating] SW mode calibration
2898 11:13:20.880643 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2899 11:13:20.883759 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2900 11:13:20.887103 0 15 0 | B1->B0 | 3333 3030 | 1 0 | (1 1) (0 0)
2901 11:13:20.894037 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 11:13:20.897205 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 11:13:20.900547 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 11:13:20.907219 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 11:13:20.910352 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 11:13:20.914087 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 11:13:20.920932 0 15 28 | B1->B0 | 2f2f 2b2b | 1 0 | (1 0) (1 0)
2908 11:13:20.923839 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 11:13:20.927371 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 11:13:20.933902 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 11:13:20.937214 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 11:13:20.940596 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 11:13:20.943934 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 11:13:20.950522 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2915 11:13:20.954351 1 0 28 | B1->B0 | 3939 3838 | 0 0 | (0 0) (0 0)
2916 11:13:20.957495 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2917 11:13:20.963986 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 11:13:20.967670 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 11:13:20.970860 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 11:13:20.977346 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 11:13:20.980574 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:13:20.984034 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 11:13:20.990898 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2924 11:13:20.994299 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 11:13:20.997455 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 11:13:21.004241 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 11:13:21.007594 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:13:21.010900 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:13:21.014369 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:13:21.020850 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:13:21.024535 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:13:21.027398 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:13:21.034339 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:13:21.037496 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:13:21.041453 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:13:21.047485 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:13:21.050982 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:13:21.054242 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:13:21.061141 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2940 11:13:21.064600 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2941 11:13:21.067853 Total UI for P1: 0, mck2ui 16
2942 11:13:21.071173 best dqsien dly found for B1: ( 1, 3, 28)
2943 11:13:21.074329 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 11:13:21.077456 Total UI for P1: 0, mck2ui 16
2945 11:13:21.080879 best dqsien dly found for B0: ( 1, 3, 30)
2946 11:13:21.084162 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2947 11:13:21.087494 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2948 11:13:21.087567
2949 11:13:21.091457 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2950 11:13:21.098170 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2951 11:13:21.098247 [Gating] SW calibration Done
2952 11:13:21.098311 ==
2953 11:13:21.100763 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 11:13:21.107867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 11:13:21.107952 ==
2956 11:13:21.108024 RX Vref Scan: 0
2957 11:13:21.108088
2958 11:13:21.111024 RX Vref 0 -> 0, step: 1
2959 11:13:21.111107
2960 11:13:21.114786 RX Delay -40 -> 252, step: 8
2961 11:13:21.118118 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2962 11:13:21.121182 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2963 11:13:21.124576 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2964 11:13:21.131284 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2965 11:13:21.134336 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2966 11:13:21.137584 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2967 11:13:21.141292 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2968 11:13:21.144371 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2969 11:13:21.147617 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2970 11:13:21.154141 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2971 11:13:21.157535 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2972 11:13:21.161445 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2973 11:13:21.164245 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2974 11:13:21.167793 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2975 11:13:21.174574 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2976 11:13:21.177748 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2977 11:13:21.177832 ==
2978 11:13:21.181127 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 11:13:21.184823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 11:13:21.184907 ==
2981 11:13:21.187701 DQS Delay:
2982 11:13:21.187793 DQS0 = 0, DQS1 = 0
2983 11:13:21.187861 DQM Delay:
2984 11:13:21.191583 DQM0 = 122, DQM1 = 111
2985 11:13:21.191667 DQ Delay:
2986 11:13:21.194949 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2987 11:13:21.197648 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2988 11:13:21.201642 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
2989 11:13:21.208158 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2990 11:13:21.208242
2991 11:13:21.208307
2992 11:13:21.208370 ==
2993 11:13:21.211439 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 11:13:21.214653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 11:13:21.214736 ==
2996 11:13:21.214802
2997 11:13:21.214863
2998 11:13:21.217866 TX Vref Scan disable
2999 11:13:21.217949 == TX Byte 0 ==
3000 11:13:21.224678 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3001 11:13:21.227965 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3002 11:13:21.228049 == TX Byte 1 ==
3003 11:13:21.234334 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3004 11:13:21.237792 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3005 11:13:21.237876 ==
3006 11:13:21.241487 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 11:13:21.244586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 11:13:21.244670 ==
3009 11:13:21.257952 TX Vref=22, minBit 1, minWin=25, winSum=412
3010 11:13:21.261292 TX Vref=24, minBit 3, minWin=25, winSum=417
3011 11:13:21.264630 TX Vref=26, minBit 0, minWin=26, winSum=423
3012 11:13:21.267756 TX Vref=28, minBit 3, minWin=25, winSum=426
3013 11:13:21.270882 TX Vref=30, minBit 0, minWin=26, winSum=428
3014 11:13:21.274404 TX Vref=32, minBit 0, minWin=26, winSum=425
3015 11:13:21.281030 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
3016 11:13:21.281121
3017 11:13:21.284313 Final TX Range 1 Vref 30
3018 11:13:21.284397
3019 11:13:21.284463 ==
3020 11:13:21.288116 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 11:13:21.291176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 11:13:21.291286 ==
3023 11:13:21.291405
3024 11:13:21.291469
3025 11:13:21.294214 TX Vref Scan disable
3026 11:13:21.297608 == TX Byte 0 ==
3027 11:13:21.300990 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3028 11:13:21.304480 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3029 11:13:21.307831 == TX Byte 1 ==
3030 11:13:21.311215 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3031 11:13:21.314524 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3032 11:13:21.314623
3033 11:13:21.317934 [DATLAT]
3034 11:13:21.318016 Freq=1200, CH0 RK1
3035 11:13:21.318083
3036 11:13:21.321184 DATLAT Default: 0xd
3037 11:13:21.321268 0, 0xFFFF, sum = 0
3038 11:13:21.325071 1, 0xFFFF, sum = 0
3039 11:13:21.325157 2, 0xFFFF, sum = 0
3040 11:13:21.328218 3, 0xFFFF, sum = 0
3041 11:13:21.328376 4, 0xFFFF, sum = 0
3042 11:13:21.331576 5, 0xFFFF, sum = 0
3043 11:13:21.331655 6, 0xFFFF, sum = 0
3044 11:13:21.334724 7, 0xFFFF, sum = 0
3045 11:13:21.334800 8, 0xFFFF, sum = 0
3046 11:13:21.338050 9, 0xFFFF, sum = 0
3047 11:13:21.338131 10, 0xFFFF, sum = 0
3048 11:13:21.341545 11, 0xFFFF, sum = 0
3049 11:13:21.341631 12, 0x0, sum = 1
3050 11:13:21.344750 13, 0x0, sum = 2
3051 11:13:21.344860 14, 0x0, sum = 3
3052 11:13:21.348038 15, 0x0, sum = 4
3053 11:13:21.348123 best_step = 13
3054 11:13:21.348190
3055 11:13:21.348260 ==
3056 11:13:21.351827 Dram Type= 6, Freq= 0, CH_0, rank 1
3057 11:13:21.358698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 11:13:21.358809 ==
3059 11:13:21.358879 RX Vref Scan: 0
3060 11:13:21.358943
3061 11:13:21.361819 RX Vref 0 -> 0, step: 1
3062 11:13:21.361930
3063 11:13:21.364694 RX Delay -13 -> 252, step: 4
3064 11:13:21.368730 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3065 11:13:21.372127 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3066 11:13:21.375225 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3067 11:13:21.381943 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3068 11:13:21.385490 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3069 11:13:21.388826 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3070 11:13:21.391982 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3071 11:13:21.394947 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3072 11:13:21.401806 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3073 11:13:21.405037 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3074 11:13:21.408378 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3075 11:13:21.411671 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3076 11:13:21.414970 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3077 11:13:21.421537 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3078 11:13:21.424930 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3079 11:13:21.428832 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3080 11:13:21.428917 ==
3081 11:13:21.432073 Dram Type= 6, Freq= 0, CH_0, rank 1
3082 11:13:21.435198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 11:13:21.435278 ==
3084 11:13:21.438279 DQS Delay:
3085 11:13:21.438365 DQS0 = 0, DQS1 = 0
3086 11:13:21.442191 DQM Delay:
3087 11:13:21.442268 DQM0 = 120, DQM1 = 109
3088 11:13:21.442341 DQ Delay:
3089 11:13:21.445591 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3090 11:13:21.448297 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3091 11:13:21.455423 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3092 11:13:21.458514 DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =118
3093 11:13:21.458593
3094 11:13:21.458657
3095 11:13:21.465437 [DQSOSCAuto] RK1, (LSB)MR18= 0xfef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3096 11:13:21.468658 CH0 RK1: MR19=403, MR18=FEF
3097 11:13:21.475249 CH0_RK1: MR19=0x403, MR18=0xFEF, DQSOSC=404, MR23=63, INC=40, DEC=26
3098 11:13:21.478521 [RxdqsGatingPostProcess] freq 1200
3099 11:13:21.481721 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3100 11:13:21.485604 best DQS0 dly(2T, 0.5T) = (0, 11)
3101 11:13:21.488266 best DQS1 dly(2T, 0.5T) = (0, 12)
3102 11:13:21.491682 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3103 11:13:21.495100 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3104 11:13:21.498462 best DQS0 dly(2T, 0.5T) = (0, 11)
3105 11:13:21.501615 best DQS1 dly(2T, 0.5T) = (0, 11)
3106 11:13:21.505435 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3107 11:13:21.508611 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3108 11:13:21.511990 Pre-setting of DQS Precalculation
3109 11:13:21.515432 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3110 11:13:21.515512 ==
3111 11:13:21.518818 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 11:13:21.525171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 11:13:21.525253 ==
3114 11:13:21.528503 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3115 11:13:21.535207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3116 11:13:21.543716 [CA 0] Center 37 (7~68) winsize 62
3117 11:13:21.547056 [CA 1] Center 37 (7~68) winsize 62
3118 11:13:21.550130 [CA 2] Center 35 (5~65) winsize 61
3119 11:13:21.553412 [CA 3] Center 34 (4~64) winsize 61
3120 11:13:21.556927 [CA 4] Center 34 (4~64) winsize 61
3121 11:13:21.560180 [CA 5] Center 33 (3~63) winsize 61
3122 11:13:21.560277
3123 11:13:21.563425 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3124 11:13:21.563510
3125 11:13:21.566649 [CATrainingPosCal] consider 1 rank data
3126 11:13:21.570368 u2DelayCellTimex100 = 270/100 ps
3127 11:13:21.573605 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3128 11:13:21.576909 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3129 11:13:21.583444 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3130 11:13:21.587107 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3131 11:13:21.590551 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 11:13:21.593853 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3133 11:13:21.593937
3134 11:13:21.597144 CA PerBit enable=1, Macro0, CA PI delay=33
3135 11:13:21.597228
3136 11:13:21.600498 [CBTSetCACLKResult] CA Dly = 33
3137 11:13:21.600575 CS Dly: 8 (0~39)
3138 11:13:21.600639 ==
3139 11:13:21.603765 Dram Type= 6, Freq= 0, CH_1, rank 1
3140 11:13:21.610072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 11:13:21.610157 ==
3142 11:13:21.613708 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3143 11:13:21.620368 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3144 11:13:21.629615 [CA 0] Center 37 (7~68) winsize 62
3145 11:13:21.632860 [CA 1] Center 37 (7~68) winsize 62
3146 11:13:21.636043 [CA 2] Center 35 (5~65) winsize 61
3147 11:13:21.639270 [CA 3] Center 34 (4~65) winsize 62
3148 11:13:21.642589 [CA 4] Center 34 (4~65) winsize 62
3149 11:13:21.646102 [CA 5] Center 34 (4~64) winsize 61
3150 11:13:21.646207
3151 11:13:21.649335 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3152 11:13:21.649418
3153 11:13:21.653182 [CATrainingPosCal] consider 2 rank data
3154 11:13:21.656296 u2DelayCellTimex100 = 270/100 ps
3155 11:13:21.659698 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3156 11:13:21.662981 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3157 11:13:21.666360 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3158 11:13:21.672760 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 11:13:21.675989 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 11:13:21.679597 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3161 11:13:21.679679
3162 11:13:21.682766 CA PerBit enable=1, Macro0, CA PI delay=33
3163 11:13:21.682848
3164 11:13:21.686520 [CBTSetCACLKResult] CA Dly = 33
3165 11:13:21.686602 CS Dly: 9 (0~41)
3166 11:13:21.686668
3167 11:13:21.689651 ----->DramcWriteLeveling(PI) begin...
3168 11:13:21.689734 ==
3169 11:13:21.692937 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 11:13:21.699744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 11:13:21.699827 ==
3172 11:13:21.703048 Write leveling (Byte 0): 25 => 25
3173 11:13:21.706445 Write leveling (Byte 1): 27 => 27
3174 11:13:21.706527 DramcWriteLeveling(PI) end<-----
3175 11:13:21.706593
3176 11:13:21.709705 ==
3177 11:13:21.712858 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 11:13:21.716094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 11:13:21.716177 ==
3180 11:13:21.719798 [Gating] SW mode calibration
3181 11:13:21.726254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3182 11:13:21.729603 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3183 11:13:21.736085 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 11:13:21.739309 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 11:13:21.742711 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 11:13:21.749731 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 11:13:21.752870 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 11:13:21.756223 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 11:13:21.762803 0 15 24 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
3190 11:13:21.766533 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 11:13:21.769717 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 11:13:21.776376 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 11:13:21.779489 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 11:13:21.782758 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 11:13:21.789710 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 11:13:21.792567 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3197 11:13:21.796381 1 0 24 | B1->B0 | 3434 4040 | 0 0 | (0 0) (0 0)
3198 11:13:21.799597 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 11:13:21.806240 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 11:13:21.809496 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 11:13:21.813519 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 11:13:21.819531 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:13:21.823435 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 11:13:21.826590 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 11:13:21.832922 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:13:21.836700 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3207 11:13:21.839894 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 11:13:21.846380 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 11:13:21.849606 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 11:13:21.853017 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:13:21.856942 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:13:21.863438 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:13:21.866251 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:13:21.870092 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:13:21.876402 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:13:21.880333 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:13:21.883570 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:13:21.890154 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:13:21.893167 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:13:21.897002 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:13:21.903370 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3222 11:13:21.906473 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 11:13:21.909778 Total UI for P1: 0, mck2ui 16
3224 11:13:21.913107 best dqsien dly found for B0: ( 1, 3, 24)
3225 11:13:21.916605 Total UI for P1: 0, mck2ui 16
3226 11:13:21.919746 best dqsien dly found for B1: ( 1, 3, 24)
3227 11:13:21.923141 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3228 11:13:21.927021 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3229 11:13:21.927096
3230 11:13:21.930296 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3231 11:13:21.933521 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3232 11:13:21.936596 [Gating] SW calibration Done
3233 11:13:21.936679 ==
3234 11:13:21.940589 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 11:13:21.943794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 11:13:21.943878 ==
3237 11:13:21.946956 RX Vref Scan: 0
3238 11:13:21.947038
3239 11:13:21.950074 RX Vref 0 -> 0, step: 1
3240 11:13:21.950157
3241 11:13:21.950225 RX Delay -40 -> 252, step: 8
3242 11:13:21.956764 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3243 11:13:21.960163 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3244 11:13:21.963538 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3245 11:13:21.966839 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3246 11:13:21.970125 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3247 11:13:21.976813 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3248 11:13:21.980064 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3249 11:13:21.983392 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3250 11:13:21.986649 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3251 11:13:21.990520 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3252 11:13:21.996573 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3253 11:13:22.000061 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3254 11:13:22.003717 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3255 11:13:22.006620 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3256 11:13:22.010329 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3257 11:13:22.016779 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3258 11:13:22.016862 ==
3259 11:13:22.020291 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 11:13:22.023710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 11:13:22.023804 ==
3262 11:13:22.023886 DQS Delay:
3263 11:13:22.027134 DQS0 = 0, DQS1 = 0
3264 11:13:22.027217 DQM Delay:
3265 11:13:22.030447 DQM0 = 120, DQM1 = 116
3266 11:13:22.030530 DQ Delay:
3267 11:13:22.033746 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3268 11:13:22.037040 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3269 11:13:22.040510 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3270 11:13:22.043666 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3271 11:13:22.043763
3272 11:13:22.043863
3273 11:13:22.043930 ==
3274 11:13:22.046923 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 11:13:22.053946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 11:13:22.054031 ==
3277 11:13:22.054098
3278 11:13:22.054161
3279 11:13:22.054220 TX Vref Scan disable
3280 11:13:22.057580 == TX Byte 0 ==
3281 11:13:22.061028 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3282 11:13:22.064343 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3283 11:13:22.067804 == TX Byte 1 ==
3284 11:13:22.070547 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3285 11:13:22.074534 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3286 11:13:22.077820 ==
3287 11:13:22.081036 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 11:13:22.084383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 11:13:22.084467 ==
3290 11:13:22.094807 TX Vref=22, minBit 9, minWin=24, winSum=409
3291 11:13:22.098945 TX Vref=24, minBit 9, minWin=25, winSum=423
3292 11:13:22.101570 TX Vref=26, minBit 0, minWin=26, winSum=424
3293 11:13:22.105456 TX Vref=28, minBit 1, minWin=26, winSum=427
3294 11:13:22.108739 TX Vref=30, minBit 9, minWin=25, winSum=430
3295 11:13:22.111941 TX Vref=32, minBit 9, minWin=25, winSum=431
3296 11:13:22.118557 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3297 11:13:22.118662
3298 11:13:22.121772 Final TX Range 1 Vref 28
3299 11:13:22.121856
3300 11:13:22.121926 ==
3301 11:13:22.125259 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 11:13:22.128534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 11:13:22.128617 ==
3304 11:13:22.128683
3305 11:13:22.128755
3306 11:13:22.131990 TX Vref Scan disable
3307 11:13:22.135170 == TX Byte 0 ==
3308 11:13:22.138936 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3309 11:13:22.142357 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3310 11:13:22.145519 == TX Byte 1 ==
3311 11:13:22.148856 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3312 11:13:22.152266 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3313 11:13:22.152371
3314 11:13:22.155299 [DATLAT]
3315 11:13:22.155419 Freq=1200, CH1 RK0
3316 11:13:22.155483
3317 11:13:22.158622 DATLAT Default: 0xd
3318 11:13:22.158692 0, 0xFFFF, sum = 0
3319 11:13:22.162220 1, 0xFFFF, sum = 0
3320 11:13:22.162320 2, 0xFFFF, sum = 0
3321 11:13:22.165383 3, 0xFFFF, sum = 0
3322 11:13:22.165482 4, 0xFFFF, sum = 0
3323 11:13:22.168741 5, 0xFFFF, sum = 0
3324 11:13:22.168825 6, 0xFFFF, sum = 0
3325 11:13:22.171949 7, 0xFFFF, sum = 0
3326 11:13:22.172031 8, 0xFFFF, sum = 0
3327 11:13:22.175924 9, 0xFFFF, sum = 0
3328 11:13:22.176008 10, 0xFFFF, sum = 0
3329 11:13:22.179321 11, 0xFFFF, sum = 0
3330 11:13:22.179474 12, 0x0, sum = 1
3331 11:13:22.182074 13, 0x0, sum = 2
3332 11:13:22.182160 14, 0x0, sum = 3
3333 11:13:22.185579 15, 0x0, sum = 4
3334 11:13:22.185676 best_step = 13
3335 11:13:22.185742
3336 11:13:22.185803 ==
3337 11:13:22.188833 Dram Type= 6, Freq= 0, CH_1, rank 0
3338 11:13:22.195266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3339 11:13:22.195377 ==
3340 11:13:22.195475 RX Vref Scan: 1
3341 11:13:22.195568
3342 11:13:22.199273 Set Vref Range= 32 -> 127
3343 11:13:22.199364
3344 11:13:22.202016 RX Vref 32 -> 127, step: 1
3345 11:13:22.202098
3346 11:13:22.202163 RX Delay -5 -> 252, step: 4
3347 11:13:22.202223
3348 11:13:22.205549 Set Vref, RX VrefLevel [Byte0]: 32
3349 11:13:22.208889 [Byte1]: 32
3350 11:13:22.213419
3351 11:13:22.213500 Set Vref, RX VrefLevel [Byte0]: 33
3352 11:13:22.216395 [Byte1]: 33
3353 11:13:22.220750
3354 11:13:22.220832 Set Vref, RX VrefLevel [Byte0]: 34
3355 11:13:22.224625 [Byte1]: 34
3356 11:13:22.229230
3357 11:13:22.229327 Set Vref, RX VrefLevel [Byte0]: 35
3358 11:13:22.232795 [Byte1]: 35
3359 11:13:22.236733
3360 11:13:22.236821 Set Vref, RX VrefLevel [Byte0]: 36
3361 11:13:22.239893 [Byte1]: 36
3362 11:13:22.244734
3363 11:13:22.244827 Set Vref, RX VrefLevel [Byte0]: 37
3364 11:13:22.248012 [Byte1]: 37
3365 11:13:22.252593
3366 11:13:22.252709 Set Vref, RX VrefLevel [Byte0]: 38
3367 11:13:22.255886 [Byte1]: 38
3368 11:13:22.260730
3369 11:13:22.260810 Set Vref, RX VrefLevel [Byte0]: 39
3370 11:13:22.263621 [Byte1]: 39
3371 11:13:22.267927
3372 11:13:22.268007 Set Vref, RX VrefLevel [Byte0]: 40
3373 11:13:22.271316 [Byte1]: 40
3374 11:13:22.276364
3375 11:13:22.276444 Set Vref, RX VrefLevel [Byte0]: 41
3376 11:13:22.279119 [Byte1]: 41
3377 11:13:22.283674
3378 11:13:22.283753 Set Vref, RX VrefLevel [Byte0]: 42
3379 11:13:22.286879 [Byte1]: 42
3380 11:13:22.291597
3381 11:13:22.291677 Set Vref, RX VrefLevel [Byte0]: 43
3382 11:13:22.294815 [Byte1]: 43
3383 11:13:22.299541
3384 11:13:22.299622 Set Vref, RX VrefLevel [Byte0]: 44
3385 11:13:22.302714 [Byte1]: 44
3386 11:13:22.307234
3387 11:13:22.307376 Set Vref, RX VrefLevel [Byte0]: 45
3388 11:13:22.310721 [Byte1]: 45
3389 11:13:22.315321
3390 11:13:22.315448 Set Vref, RX VrefLevel [Byte0]: 46
3391 11:13:22.318619 [Byte1]: 46
3392 11:13:22.323849
3393 11:13:22.323930 Set Vref, RX VrefLevel [Byte0]: 47
3394 11:13:22.326437 [Byte1]: 47
3395 11:13:22.330838
3396 11:13:22.330919 Set Vref, RX VrefLevel [Byte0]: 48
3397 11:13:22.334346 [Byte1]: 48
3398 11:13:22.339024
3399 11:13:22.339106 Set Vref, RX VrefLevel [Byte0]: 49
3400 11:13:22.342314 [Byte1]: 49
3401 11:13:22.346647
3402 11:13:22.346728 Set Vref, RX VrefLevel [Byte0]: 50
3403 11:13:22.349905 [Byte1]: 50
3404 11:13:22.354639
3405 11:13:22.354720 Set Vref, RX VrefLevel [Byte0]: 51
3406 11:13:22.358091 [Byte1]: 51
3407 11:13:22.362690
3408 11:13:22.362770 Set Vref, RX VrefLevel [Byte0]: 52
3409 11:13:22.365982 [Byte1]: 52
3410 11:13:22.370440
3411 11:13:22.370530 Set Vref, RX VrefLevel [Byte0]: 53
3412 11:13:22.373495 [Byte1]: 53
3413 11:13:22.377837
3414 11:13:22.377916 Set Vref, RX VrefLevel [Byte0]: 54
3415 11:13:22.381622 [Byte1]: 54
3416 11:13:22.386200
3417 11:13:22.386282 Set Vref, RX VrefLevel [Byte0]: 55
3418 11:13:22.389636 [Byte1]: 55
3419 11:13:22.393690
3420 11:13:22.393772 Set Vref, RX VrefLevel [Byte0]: 56
3421 11:13:22.397062 [Byte1]: 56
3422 11:13:22.401772
3423 11:13:22.401854 Set Vref, RX VrefLevel [Byte0]: 57
3424 11:13:22.405084 [Byte1]: 57
3425 11:13:22.409646
3426 11:13:22.409758 Set Vref, RX VrefLevel [Byte0]: 58
3427 11:13:22.412730 [Byte1]: 58
3428 11:13:22.417458
3429 11:13:22.417575 Set Vref, RX VrefLevel [Byte0]: 59
3430 11:13:22.420761 [Byte1]: 59
3431 11:13:22.425367
3432 11:13:22.425471 Set Vref, RX VrefLevel [Byte0]: 60
3433 11:13:22.428365 [Byte1]: 60
3434 11:13:22.432852
3435 11:13:22.432959 Set Vref, RX VrefLevel [Byte0]: 61
3436 11:13:22.435982 [Byte1]: 61
3437 11:13:22.441203
3438 11:13:22.441290 Set Vref, RX VrefLevel [Byte0]: 62
3439 11:13:22.443926 [Byte1]: 62
3440 11:13:22.448576
3441 11:13:22.448662 Set Vref, RX VrefLevel [Byte0]: 63
3442 11:13:22.452192 [Byte1]: 63
3443 11:13:22.456898
3444 11:13:22.456984 Set Vref, RX VrefLevel [Byte0]: 64
3445 11:13:22.460158 [Byte1]: 64
3446 11:13:22.464193
3447 11:13:22.464279 Set Vref, RX VrefLevel [Byte0]: 65
3448 11:13:22.467578 [Byte1]: 65
3449 11:13:22.472066
3450 11:13:22.475500 Set Vref, RX VrefLevel [Byte0]: 66
3451 11:13:22.475606 [Byte1]: 66
3452 11:13:22.480539
3453 11:13:22.480616 Set Vref, RX VrefLevel [Byte0]: 67
3454 11:13:22.483594 [Byte1]: 67
3455 11:13:22.487899
3456 11:13:22.488004 Set Vref, RX VrefLevel [Byte0]: 68
3457 11:13:22.491140 [Byte1]: 68
3458 11:13:22.496027
3459 11:13:22.496137 Set Vref, RX VrefLevel [Byte0]: 69
3460 11:13:22.499230 [Byte1]: 69
3461 11:13:22.503878
3462 11:13:22.503955 Final RX Vref Byte 0 = 54 to rank0
3463 11:13:22.507232 Final RX Vref Byte 1 = 48 to rank0
3464 11:13:22.510517 Final RX Vref Byte 0 = 54 to rank1
3465 11:13:22.513705 Final RX Vref Byte 1 = 48 to rank1==
3466 11:13:22.517016 Dram Type= 6, Freq= 0, CH_1, rank 0
3467 11:13:22.523523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 11:13:22.523599 ==
3469 11:13:22.523665 DQS Delay:
3470 11:13:22.523726 DQS0 = 0, DQS1 = 0
3471 11:13:22.526881 DQM Delay:
3472 11:13:22.526979 DQM0 = 119, DQM1 = 116
3473 11:13:22.530130 DQ Delay:
3474 11:13:22.533994 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =116
3475 11:13:22.536969 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3476 11:13:22.540168 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3477 11:13:22.543820 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3478 11:13:22.543898
3479 11:13:22.543963
3480 11:13:22.550523 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3481 11:13:22.553568 CH1 RK0: MR19=404, MR18=215
3482 11:13:22.560557 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3483 11:13:22.560641
3484 11:13:22.563867 ----->DramcWriteLeveling(PI) begin...
3485 11:13:22.563940 ==
3486 11:13:22.567396 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 11:13:22.570711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 11:13:22.570798 ==
3489 11:13:22.574062 Write leveling (Byte 0): 26 => 26
3490 11:13:22.577349 Write leveling (Byte 1): 29 => 29
3491 11:13:22.580572 DramcWriteLeveling(PI) end<-----
3492 11:13:22.580656
3493 11:13:22.580729 ==
3494 11:13:22.583822 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 11:13:22.587057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 11:13:22.590758 ==
3497 11:13:22.590834 [Gating] SW mode calibration
3498 11:13:22.600929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3499 11:13:22.604175 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3500 11:13:22.607457 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 11:13:22.614146 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 11:13:22.617443 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 11:13:22.620686 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 11:13:22.627087 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 11:13:22.630831 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3506 11:13:22.634193 0 15 24 | B1->B0 | 2a2a 3333 | 0 1 | (1 0) (1 0)
3507 11:13:22.637436 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3508 11:13:22.644230 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 11:13:22.647556 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 11:13:22.650529 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 11:13:22.657173 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 11:13:22.660803 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 11:13:22.664065 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3514 11:13:22.670877 1 0 24 | B1->B0 | 4242 2828 | 0 0 | (0 0) (0 0)
3515 11:13:22.674197 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3516 11:13:22.677519 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 11:13:22.684187 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 11:13:22.687586 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 11:13:22.690405 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 11:13:22.697092 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 11:13:22.700642 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 11:13:22.703711 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3523 11:13:22.710299 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3524 11:13:22.714190 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 11:13:22.716892 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 11:13:22.723602 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 11:13:22.727035 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 11:13:22.730314 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 11:13:22.736714 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 11:13:22.740132 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 11:13:22.744167 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 11:13:22.750621 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 11:13:22.753632 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 11:13:22.757364 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 11:13:22.760490 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 11:13:22.767075 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 11:13:22.770766 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3538 11:13:22.773991 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3539 11:13:22.780639 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3540 11:13:22.783993 Total UI for P1: 0, mck2ui 16
3541 11:13:22.787489 best dqsien dly found for B1: ( 1, 3, 22)
3542 11:13:22.790895 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 11:13:22.793966 Total UI for P1: 0, mck2ui 16
3544 11:13:22.797210 best dqsien dly found for B0: ( 1, 3, 26)
3545 11:13:22.800500 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3546 11:13:22.803691 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3547 11:13:22.803787
3548 11:13:22.807289 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3549 11:13:22.810628 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3550 11:13:22.813999 [Gating] SW calibration Done
3551 11:13:22.814092 ==
3552 11:13:22.817070 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 11:13:22.823945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 11:13:22.824034 ==
3555 11:13:22.824101 RX Vref Scan: 0
3556 11:13:22.824163
3557 11:13:22.827321 RX Vref 0 -> 0, step: 1
3558 11:13:22.827443
3559 11:13:22.830671 RX Delay -40 -> 252, step: 8
3560 11:13:22.834029 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3561 11:13:22.836683 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3562 11:13:22.840647 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3563 11:13:22.843887 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3564 11:13:22.849961 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3565 11:13:22.853955 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3566 11:13:22.857257 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3567 11:13:22.859966 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3568 11:13:22.863795 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3569 11:13:22.870108 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3570 11:13:22.873899 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3571 11:13:22.877101 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3572 11:13:22.880029 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3573 11:13:22.883655 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3574 11:13:22.890194 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3575 11:13:22.893378 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3576 11:13:22.893470 ==
3577 11:13:22.897096 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 11:13:22.900447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 11:13:22.900535 ==
3580 11:13:22.903555 DQS Delay:
3581 11:13:22.903644 DQS0 = 0, DQS1 = 0
3582 11:13:22.903743 DQM Delay:
3583 11:13:22.906751 DQM0 = 120, DQM1 = 118
3584 11:13:22.906840 DQ Delay:
3585 11:13:22.910107 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3586 11:13:22.913195 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3587 11:13:22.920100 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3588 11:13:22.923196 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3589 11:13:22.923310
3590 11:13:22.923427
3591 11:13:22.923490 ==
3592 11:13:22.926606 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 11:13:22.929976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 11:13:22.930083 ==
3595 11:13:22.930175
3596 11:13:22.930263
3597 11:13:22.933176 TX Vref Scan disable
3598 11:13:22.936512 == TX Byte 0 ==
3599 11:13:22.939756 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3600 11:13:22.943060 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3601 11:13:22.946481 == TX Byte 1 ==
3602 11:13:22.949649 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3603 11:13:22.952961 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3604 11:13:22.953042 ==
3605 11:13:22.956989 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 11:13:22.960232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 11:13:22.960313 ==
3608 11:13:22.972696 TX Vref=22, minBit 9, minWin=25, winSum=418
3609 11:13:22.976475 TX Vref=24, minBit 10, minWin=25, winSum=423
3610 11:13:22.979509 TX Vref=26, minBit 2, minWin=26, winSum=427
3611 11:13:22.982667 TX Vref=28, minBit 9, minWin=26, winSum=433
3612 11:13:22.986032 TX Vref=30, minBit 9, minWin=26, winSum=435
3613 11:13:22.992794 TX Vref=32, minBit 9, minWin=26, winSum=437
3614 11:13:22.996133 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 32
3615 11:13:22.996217
3616 11:13:22.999189 Final TX Range 1 Vref 32
3617 11:13:22.999273
3618 11:13:22.999376 ==
3619 11:13:23.003150 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 11:13:23.006531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 11:13:23.006616 ==
3622 11:13:23.009857
3623 11:13:23.009940
3624 11:13:23.010006 TX Vref Scan disable
3625 11:13:23.012468 == TX Byte 0 ==
3626 11:13:23.015872 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3627 11:13:23.019557 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3628 11:13:23.022698 == TX Byte 1 ==
3629 11:13:23.025930 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3630 11:13:23.029173 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3631 11:13:23.032463
3632 11:13:23.032554 [DATLAT]
3633 11:13:23.032624 Freq=1200, CH1 RK1
3634 11:13:23.032691
3635 11:13:23.036377 DATLAT Default: 0xd
3636 11:13:23.036467 0, 0xFFFF, sum = 0
3637 11:13:23.039646 1, 0xFFFF, sum = 0
3638 11:13:23.039735 2, 0xFFFF, sum = 0
3639 11:13:23.042410 3, 0xFFFF, sum = 0
3640 11:13:23.045707 4, 0xFFFF, sum = 0
3641 11:13:23.045796 5, 0xFFFF, sum = 0
3642 11:13:23.048974 6, 0xFFFF, sum = 0
3643 11:13:23.049060 7, 0xFFFF, sum = 0
3644 11:13:23.052822 8, 0xFFFF, sum = 0
3645 11:13:23.052908 9, 0xFFFF, sum = 0
3646 11:13:23.056097 10, 0xFFFF, sum = 0
3647 11:13:23.056183 11, 0xFFFF, sum = 0
3648 11:13:23.059384 12, 0x0, sum = 1
3649 11:13:23.059481 13, 0x0, sum = 2
3650 11:13:23.062632 14, 0x0, sum = 3
3651 11:13:23.062718 15, 0x0, sum = 4
3652 11:13:23.062785 best_step = 13
3653 11:13:23.065778
3654 11:13:23.065861 ==
3655 11:13:23.069081 Dram Type= 6, Freq= 0, CH_1, rank 1
3656 11:13:23.072322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3657 11:13:23.072408 ==
3658 11:13:23.072475 RX Vref Scan: 0
3659 11:13:23.072537
3660 11:13:23.075646 RX Vref 0 -> 0, step: 1
3661 11:13:23.075731
3662 11:13:23.078924 RX Delay -5 -> 252, step: 4
3663 11:13:23.082167 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3664 11:13:23.088921 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3665 11:13:23.092121 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3666 11:13:23.095858 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3667 11:13:23.098903 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3668 11:13:23.101993 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3669 11:13:23.109119 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3670 11:13:23.112291 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3671 11:13:23.115573 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3672 11:13:23.119027 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3673 11:13:23.122264 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3674 11:13:23.128651 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3675 11:13:23.131843 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3676 11:13:23.135051 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3677 11:13:23.138850 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3678 11:13:23.145039 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3679 11:13:23.145153 ==
3680 11:13:23.148326 Dram Type= 6, Freq= 0, CH_1, rank 1
3681 11:13:23.151799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3682 11:13:23.151883 ==
3683 11:13:23.151949 DQS Delay:
3684 11:13:23.154947 DQS0 = 0, DQS1 = 0
3685 11:13:23.155030 DQM Delay:
3686 11:13:23.158717 DQM0 = 120, DQM1 = 116
3687 11:13:23.158829 DQ Delay:
3688 11:13:23.162027 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3689 11:13:23.165273 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3690 11:13:23.168513 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3691 11:13:23.171916 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3692 11:13:23.172014
3693 11:13:23.172090
3694 11:13:23.181544 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3695 11:13:23.185050 CH1 RK1: MR19=403, MR18=12F0
3696 11:13:23.188389 CH1_RK1: MR19=0x403, MR18=0x12F0, DQSOSC=403, MR23=63, INC=40, DEC=26
3697 11:13:23.191602 [RxdqsGatingPostProcess] freq 1200
3698 11:13:23.198392 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3699 11:13:23.201691 best DQS0 dly(2T, 0.5T) = (0, 11)
3700 11:13:23.204777 best DQS1 dly(2T, 0.5T) = (0, 11)
3701 11:13:23.208546 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3702 11:13:23.211621 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3703 11:13:23.215354 best DQS0 dly(2T, 0.5T) = (0, 11)
3704 11:13:23.218761 best DQS1 dly(2T, 0.5T) = (0, 11)
3705 11:13:23.221893 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3706 11:13:23.225377 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3707 11:13:23.227956 Pre-setting of DQS Precalculation
3708 11:13:23.231923 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3709 11:13:23.238241 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3710 11:13:23.245258 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3711 11:13:23.245348
3712 11:13:23.245413
3713 11:13:23.248621 [Calibration Summary] 2400 Mbps
3714 11:13:23.251281 CH 0, Rank 0
3715 11:13:23.251401 SW Impedance : PASS
3716 11:13:23.255239 DUTY Scan : NO K
3717 11:13:23.258617 ZQ Calibration : PASS
3718 11:13:23.258700 Jitter Meter : NO K
3719 11:13:23.262074 CBT Training : PASS
3720 11:13:23.265330 Write leveling : PASS
3721 11:13:23.265413 RX DQS gating : PASS
3722 11:13:23.268513 RX DQ/DQS(RDDQC) : PASS
3723 11:13:23.271578 TX DQ/DQS : PASS
3724 11:13:23.271683 RX DATLAT : PASS
3725 11:13:23.275069 RX DQ/DQS(Engine): PASS
3726 11:13:23.275165 TX OE : NO K
3727 11:13:23.278268 All Pass.
3728 11:13:23.278350
3729 11:13:23.278415 CH 0, Rank 1
3730 11:13:23.281391 SW Impedance : PASS
3731 11:13:23.281474 DUTY Scan : NO K
3732 11:13:23.284659 ZQ Calibration : PASS
3733 11:13:23.287954 Jitter Meter : NO K
3734 11:13:23.288062 CBT Training : PASS
3735 11:13:23.291954 Write leveling : PASS
3736 11:13:23.295138 RX DQS gating : PASS
3737 11:13:23.295221 RX DQ/DQS(RDDQC) : PASS
3738 11:13:23.297866 TX DQ/DQS : PASS
3739 11:13:23.301858 RX DATLAT : PASS
3740 11:13:23.301941 RX DQ/DQS(Engine): PASS
3741 11:13:23.304871 TX OE : NO K
3742 11:13:23.304980 All Pass.
3743 11:13:23.305169
3744 11:13:23.308100 CH 1, Rank 0
3745 11:13:23.308183 SW Impedance : PASS
3746 11:13:23.311163 DUTY Scan : NO K
3747 11:13:23.314892 ZQ Calibration : PASS
3748 11:13:23.314975 Jitter Meter : NO K
3749 11:13:23.318021 CBT Training : PASS
3750 11:13:23.321824 Write leveling : PASS
3751 11:13:23.321918 RX DQS gating : PASS
3752 11:13:23.324556 RX DQ/DQS(RDDQC) : PASS
3753 11:13:23.327906 TX DQ/DQS : PASS
3754 11:13:23.328004 RX DATLAT : PASS
3755 11:13:23.331228 RX DQ/DQS(Engine): PASS
3756 11:13:23.331380 TX OE : NO K
3757 11:13:23.334390 All Pass.
3758 11:13:23.334505
3759 11:13:23.334601 CH 1, Rank 1
3760 11:13:23.337731 SW Impedance : PASS
3761 11:13:23.337871 DUTY Scan : NO K
3762 11:13:23.341715 ZQ Calibration : PASS
3763 11:13:23.344453 Jitter Meter : NO K
3764 11:13:23.344602 CBT Training : PASS
3765 11:13:23.347895 Write leveling : PASS
3766 11:13:23.351531 RX DQS gating : PASS
3767 11:13:23.351671 RX DQ/DQS(RDDQC) : PASS
3768 11:13:23.354790 TX DQ/DQS : PASS
3769 11:13:23.358146 RX DATLAT : PASS
3770 11:13:23.358318 RX DQ/DQS(Engine): PASS
3771 11:13:23.361516 TX OE : NO K
3772 11:13:23.361696 All Pass.
3773 11:13:23.361811
3774 11:13:23.364962 DramC Write-DBI off
3775 11:13:23.368242 PER_BANK_REFRESH: Hybrid Mode
3776 11:13:23.368327 TX_TRACKING: ON
3777 11:13:23.378360 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3778 11:13:23.381653 [FAST_K] Save calibration result to emmc
3779 11:13:23.384736 dramc_set_vcore_voltage set vcore to 650000
3780 11:13:23.387779 Read voltage for 600, 5
3781 11:13:23.387891 Vio18 = 0
3782 11:13:23.387988 Vcore = 650000
3783 11:13:23.391559 Vdram = 0
3784 11:13:23.391640 Vddq = 0
3785 11:13:23.391705 Vmddr = 0
3786 11:13:23.398176 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3787 11:13:23.401498 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3788 11:13:23.404820 MEM_TYPE=3, freq_sel=19
3789 11:13:23.408201 sv_algorithm_assistance_LP4_1600
3790 11:13:23.411412 ============ PULL DRAM RESETB DOWN ============
3791 11:13:23.414577 ========== PULL DRAM RESETB DOWN end =========
3792 11:13:23.421362 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3793 11:13:23.424665 ===================================
3794 11:13:23.424771 LPDDR4 DRAM CONFIGURATION
3795 11:13:23.427728 ===================================
3796 11:13:23.431053 EX_ROW_EN[0] = 0x0
3797 11:13:23.434756 EX_ROW_EN[1] = 0x0
3798 11:13:23.434846 LP4Y_EN = 0x0
3799 11:13:23.438110 WORK_FSP = 0x0
3800 11:13:23.438208 WL = 0x2
3801 11:13:23.441502 RL = 0x2
3802 11:13:23.441599 BL = 0x2
3803 11:13:23.444322 RPST = 0x0
3804 11:13:23.444430 RD_PRE = 0x0
3805 11:13:23.448303 WR_PRE = 0x1
3806 11:13:23.448418 WR_PST = 0x0
3807 11:13:23.451449 DBI_WR = 0x0
3808 11:13:23.451562 DBI_RD = 0x0
3809 11:13:23.454811 OTF = 0x1
3810 11:13:23.457939 ===================================
3811 11:13:23.461150 ===================================
3812 11:13:23.461333 ANA top config
3813 11:13:23.464471 ===================================
3814 11:13:23.467844 DLL_ASYNC_EN = 0
3815 11:13:23.471114 ALL_SLAVE_EN = 1
3816 11:13:23.471292 NEW_RANK_MODE = 1
3817 11:13:23.474458 DLL_IDLE_MODE = 1
3818 11:13:23.478213 LP45_APHY_COMB_EN = 1
3819 11:13:23.481444 TX_ODT_DIS = 1
3820 11:13:23.484708 NEW_8X_MODE = 1
3821 11:13:23.487941 ===================================
3822 11:13:23.491217 ===================================
3823 11:13:23.491322 data_rate = 1200
3824 11:13:23.494414 CKR = 1
3825 11:13:23.498178 DQ_P2S_RATIO = 8
3826 11:13:23.501604 ===================================
3827 11:13:23.504991 CA_P2S_RATIO = 8
3828 11:13:23.508374 DQ_CA_OPEN = 0
3829 11:13:23.511001 DQ_SEMI_OPEN = 0
3830 11:13:23.511086 CA_SEMI_OPEN = 0
3831 11:13:23.514865 CA_FULL_RATE = 0
3832 11:13:23.518093 DQ_CKDIV4_EN = 1
3833 11:13:23.521239 CA_CKDIV4_EN = 1
3834 11:13:23.524272 CA_PREDIV_EN = 0
3835 11:13:23.527911 PH8_DLY = 0
3836 11:13:23.527994 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3837 11:13:23.531081 DQ_AAMCK_DIV = 4
3838 11:13:23.534325 CA_AAMCK_DIV = 4
3839 11:13:23.537412 CA_ADMCK_DIV = 4
3840 11:13:23.540715 DQ_TRACK_CA_EN = 0
3841 11:13:23.544557 CA_PICK = 600
3842 11:13:23.547959 CA_MCKIO = 600
3843 11:13:23.548042 MCKIO_SEMI = 0
3844 11:13:23.551269 PLL_FREQ = 2288
3845 11:13:23.554566 DQ_UI_PI_RATIO = 32
3846 11:13:23.557885 CA_UI_PI_RATIO = 0
3847 11:13:23.561169 ===================================
3848 11:13:23.564293 ===================================
3849 11:13:23.567601 memory_type:LPDDR4
3850 11:13:23.567686 GP_NUM : 10
3851 11:13:23.570936 SRAM_EN : 1
3852 11:13:23.574219 MD32_EN : 0
3853 11:13:23.577494 ===================================
3854 11:13:23.577578 [ANA_INIT] >>>>>>>>>>>>>>
3855 11:13:23.580696 <<<<<< [CONFIGURE PHASE]: ANA_TX
3856 11:13:23.583921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3857 11:13:23.586933 ===================================
3858 11:13:23.590692 data_rate = 1200,PCW = 0X5800
3859 11:13:23.594359 ===================================
3860 11:13:23.597100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3861 11:13:23.603502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3862 11:13:23.606920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 11:13:23.613580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3864 11:13:23.617051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3865 11:13:23.620310 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3866 11:13:23.620393 [ANA_INIT] flow start
3867 11:13:23.623594 [ANA_INIT] PLL >>>>>>>>
3868 11:13:23.626857 [ANA_INIT] PLL <<<<<<<<
3869 11:13:23.630114 [ANA_INIT] MIDPI >>>>>>>>
3870 11:13:23.630197 [ANA_INIT] MIDPI <<<<<<<<
3871 11:13:23.633831 [ANA_INIT] DLL >>>>>>>>
3872 11:13:23.633915 [ANA_INIT] flow end
3873 11:13:23.640267 ============ LP4 DIFF to SE enter ============
3874 11:13:23.643244 ============ LP4 DIFF to SE exit ============
3875 11:13:23.647100 [ANA_INIT] <<<<<<<<<<<<<
3876 11:13:23.650438 [Flow] Enable top DCM control >>>>>
3877 11:13:23.653809 [Flow] Enable top DCM control <<<<<
3878 11:13:23.653893 Enable DLL master slave shuffle
3879 11:13:23.660315 ==============================================================
3880 11:13:23.663567 Gating Mode config
3881 11:13:23.666861 ==============================================================
3882 11:13:23.670197 Config description:
3883 11:13:23.680138 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3884 11:13:23.686768 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3885 11:13:23.689853 SELPH_MODE 0: By rank 1: By Phase
3886 11:13:23.696700 ==============================================================
3887 11:13:23.699849 GAT_TRACK_EN = 1
3888 11:13:23.703131 RX_GATING_MODE = 2
3889 11:13:23.706980 RX_GATING_TRACK_MODE = 2
3890 11:13:23.709635 SELPH_MODE = 1
3891 11:13:23.713531 PICG_EARLY_EN = 1
3892 11:13:23.713615 VALID_LAT_VALUE = 1
3893 11:13:23.720046 ==============================================================
3894 11:13:23.723345 Enter into Gating configuration >>>>
3895 11:13:23.726747 Exit from Gating configuration <<<<
3896 11:13:23.729928 Enter into DVFS_PRE_config >>>>>
3897 11:13:23.739524 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3898 11:13:23.743370 Exit from DVFS_PRE_config <<<<<
3899 11:13:23.746571 Enter into PICG configuration >>>>
3900 11:13:23.749735 Exit from PICG configuration <<<<
3901 11:13:23.753043 [RX_INPUT] configuration >>>>>
3902 11:13:23.756207 [RX_INPUT] configuration <<<<<
3903 11:13:23.760114 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3904 11:13:23.766624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3905 11:13:23.773215 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 11:13:23.779542 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 11:13:23.786381 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 11:13:23.789612 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 11:13:23.796103 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3910 11:13:23.799509 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3911 11:13:23.803194 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3912 11:13:23.806460 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3913 11:13:23.812991 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3914 11:13:23.816201 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3915 11:13:23.819567 ===================================
3916 11:13:23.822941 LPDDR4 DRAM CONFIGURATION
3917 11:13:23.826280 ===================================
3918 11:13:23.826384 EX_ROW_EN[0] = 0x0
3919 11:13:23.829029 EX_ROW_EN[1] = 0x0
3920 11:13:23.829131 LP4Y_EN = 0x0
3921 11:13:23.832391 WORK_FSP = 0x0
3922 11:13:23.832467 WL = 0x2
3923 11:13:23.836209 RL = 0x2
3924 11:13:23.839583 BL = 0x2
3925 11:13:23.839689 RPST = 0x0
3926 11:13:23.842841 RD_PRE = 0x0
3927 11:13:23.842926 WR_PRE = 0x1
3928 11:13:23.846080 WR_PST = 0x0
3929 11:13:23.846165 DBI_WR = 0x0
3930 11:13:23.849241 DBI_RD = 0x0
3931 11:13:23.849326 OTF = 0x1
3932 11:13:23.853018 ===================================
3933 11:13:23.856300 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3934 11:13:23.859479 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3935 11:13:23.866092 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3936 11:13:23.869340 ===================================
3937 11:13:23.872546 LPDDR4 DRAM CONFIGURATION
3938 11:13:23.876000 ===================================
3939 11:13:23.876086 EX_ROW_EN[0] = 0x10
3940 11:13:23.879373 EX_ROW_EN[1] = 0x0
3941 11:13:23.879458 LP4Y_EN = 0x0
3942 11:13:23.882542 WORK_FSP = 0x0
3943 11:13:23.882627 WL = 0x2
3944 11:13:23.886360 RL = 0x2
3945 11:13:23.886444 BL = 0x2
3946 11:13:23.889626 RPST = 0x0
3947 11:13:23.889710 RD_PRE = 0x0
3948 11:13:23.892973 WR_PRE = 0x1
3949 11:13:23.893057 WR_PST = 0x0
3950 11:13:23.896172 DBI_WR = 0x0
3951 11:13:23.896256 DBI_RD = 0x0
3952 11:13:23.899318 OTF = 0x1
3953 11:13:23.902578 ===================================
3954 11:13:23.909626 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3955 11:13:23.912562 nWR fixed to 30
3956 11:13:23.915916 [ModeRegInit_LP4] CH0 RK0
3957 11:13:23.916000 [ModeRegInit_LP4] CH0 RK1
3958 11:13:23.919172 [ModeRegInit_LP4] CH1 RK0
3959 11:13:23.922490 [ModeRegInit_LP4] CH1 RK1
3960 11:13:23.922573 match AC timing 17
3961 11:13:23.929137 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3962 11:13:23.932482 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3963 11:13:23.935850 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3964 11:13:23.942503 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3965 11:13:23.945803 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3966 11:13:23.945887 ==
3967 11:13:23.949099 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 11:13:23.952177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 11:13:23.952263 ==
3970 11:13:23.958992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3971 11:13:23.965803 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3972 11:13:23.969102 [CA 0] Center 35 (4~66) winsize 63
3973 11:13:23.972362 [CA 1] Center 35 (5~66) winsize 62
3974 11:13:23.975636 [CA 2] Center 33 (3~64) winsize 62
3975 11:13:23.978960 [CA 3] Center 33 (2~64) winsize 63
3976 11:13:23.982207 [CA 4] Center 33 (2~64) winsize 63
3977 11:13:23.985517 [CA 5] Center 32 (2~63) winsize 62
3978 11:13:23.985615
3979 11:13:23.989016 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3980 11:13:23.989092
3981 11:13:23.992129 [CATrainingPosCal] consider 1 rank data
3982 11:13:23.996018 u2DelayCellTimex100 = 270/100 ps
3983 11:13:23.999278 CA0 delay=35 (4~66),Diff = 3 PI (28 cell)
3984 11:13:24.002416 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3985 11:13:24.005603 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3986 11:13:24.008975 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3987 11:13:24.012105 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3988 11:13:24.015920 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3989 11:13:24.018974
3990 11:13:24.022178 CA PerBit enable=1, Macro0, CA PI delay=32
3991 11:13:24.022267
3992 11:13:24.025503 [CBTSetCACLKResult] CA Dly = 32
3993 11:13:24.025576 CS Dly: 4 (0~35)
3994 11:13:24.025637 ==
3995 11:13:24.028725 Dram Type= 6, Freq= 0, CH_0, rank 1
3996 11:13:24.032105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 11:13:24.032182 ==
3998 11:13:24.038681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3999 11:13:24.045295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4000 11:13:24.048601 [CA 0] Center 35 (5~66) winsize 62
4001 11:13:24.051994 [CA 1] Center 35 (5~66) winsize 62
4002 11:13:24.055226 [CA 2] Center 34 (3~65) winsize 63
4003 11:13:24.058605 [CA 3] Center 33 (3~64) winsize 62
4004 11:13:24.061983 [CA 4] Center 32 (2~63) winsize 62
4005 11:13:24.065361 [CA 5] Center 32 (2~63) winsize 62
4006 11:13:24.065437
4007 11:13:24.068904 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4008 11:13:24.069005
4009 11:13:24.072167 [CATrainingPosCal] consider 2 rank data
4010 11:13:24.075395 u2DelayCellTimex100 = 270/100 ps
4011 11:13:24.078579 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4012 11:13:24.081894 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4013 11:13:24.085326 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4014 11:13:24.088573 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4015 11:13:24.091992 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4016 11:13:24.098742 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4017 11:13:24.098846
4018 11:13:24.101890 CA PerBit enable=1, Macro0, CA PI delay=32
4019 11:13:24.101966
4020 11:13:24.105158 [CBTSetCACLKResult] CA Dly = 32
4021 11:13:24.105229 CS Dly: 4 (0~36)
4022 11:13:24.105290
4023 11:13:24.108354 ----->DramcWriteLeveling(PI) begin...
4024 11:13:24.108426 ==
4025 11:13:24.112227 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 11:13:24.115657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 11:13:24.118774 ==
4028 11:13:24.118878 Write leveling (Byte 0): 35 => 35
4029 11:13:24.121824 Write leveling (Byte 1): 31 => 31
4030 11:13:24.125243 DramcWriteLeveling(PI) end<-----
4031 11:13:24.125315
4032 11:13:24.125376 ==
4033 11:13:24.128510 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 11:13:24.135223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 11:13:24.135302 ==
4036 11:13:24.138439 [Gating] SW mode calibration
4037 11:13:24.145402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4038 11:13:24.148619 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4039 11:13:24.155319 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 11:13:24.158674 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 11:13:24.162097 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 11:13:24.168713 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
4043 11:13:24.171910 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4044 11:13:24.175105 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 11:13:24.178640 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 11:13:24.184778 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 11:13:24.188075 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 11:13:24.191575 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 11:13:24.198085 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 11:13:24.201583 0 10 12 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
4051 11:13:24.204716 0 10 16 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
4052 11:13:24.211432 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 11:13:24.215074 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 11:13:24.218304 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 11:13:24.225085 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 11:13:24.228166 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 11:13:24.231846 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 11:13:24.238258 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4059 11:13:24.241761 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4060 11:13:24.244926 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:13:24.251630 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:13:24.255047 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 11:13:24.258346 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:13:24.265002 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 11:13:24.268353 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 11:13:24.271647 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 11:13:24.278478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 11:13:24.281632 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 11:13:24.284934 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 11:13:24.291734 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 11:13:24.294833 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 11:13:24.298466 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 11:13:24.301843 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:13:24.308556 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4075 11:13:24.311730 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4076 11:13:24.314956 Total UI for P1: 0, mck2ui 16
4077 11:13:24.318184 best dqsien dly found for B0: ( 0, 13, 12)
4078 11:13:24.321418 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 11:13:24.324588 Total UI for P1: 0, mck2ui 16
4080 11:13:24.328453 best dqsien dly found for B1: ( 0, 13, 18)
4081 11:13:24.331365 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4082 11:13:24.338531 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4083 11:13:24.338984
4084 11:13:24.341649 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4085 11:13:24.344965 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4086 11:13:24.348330 [Gating] SW calibration Done
4087 11:13:24.348762 ==
4088 11:13:24.351431 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 11:13:24.354970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 11:13:24.355437 ==
4091 11:13:24.358472 RX Vref Scan: 0
4092 11:13:24.358898
4093 11:13:24.359240 RX Vref 0 -> 0, step: 1
4094 11:13:24.359604
4095 11:13:24.361586 RX Delay -230 -> 252, step: 16
4096 11:13:24.364926 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4097 11:13:24.371760 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4098 11:13:24.374926 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4099 11:13:24.378183 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4100 11:13:24.381386 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4101 11:13:24.387962 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4102 11:13:24.391106 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4103 11:13:24.394391 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4104 11:13:24.397740 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4105 11:13:24.401346 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4106 11:13:24.407772 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4107 11:13:24.411094 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4108 11:13:24.414356 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4109 11:13:24.417627 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4110 11:13:24.424693 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4111 11:13:24.428026 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4112 11:13:24.428621 ==
4113 11:13:24.431107 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 11:13:24.434660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 11:13:24.435131 ==
4116 11:13:24.437781 DQS Delay:
4117 11:13:24.438373 DQS0 = 0, DQS1 = 0
4118 11:13:24.438881 DQM Delay:
4119 11:13:24.441156 DQM0 = 52, DQM1 = 44
4120 11:13:24.441783 DQ Delay:
4121 11:13:24.444255 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4122 11:13:24.447820 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =57
4123 11:13:24.450891 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4124 11:13:24.454706 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4125 11:13:24.455135
4126 11:13:24.455692
4127 11:13:24.456041 ==
4128 11:13:24.457511 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 11:13:24.464217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 11:13:24.464644 ==
4131 11:13:24.464985
4132 11:13:24.465297
4133 11:13:24.465598 TX Vref Scan disable
4134 11:13:24.467577 == TX Byte 0 ==
4135 11:13:24.471430 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4136 11:13:24.477815 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4137 11:13:24.478256 == TX Byte 1 ==
4138 11:13:24.480974 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4139 11:13:24.487606 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4140 11:13:24.488047 ==
4141 11:13:24.490999 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 11:13:24.494818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 11:13:24.495355 ==
4144 11:13:24.495726
4145 11:13:24.496101
4146 11:13:24.497601 TX Vref Scan disable
4147 11:13:24.500893 == TX Byte 0 ==
4148 11:13:24.504221 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4149 11:13:24.508070 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4150 11:13:24.511165 == TX Byte 1 ==
4151 11:13:24.514251 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4152 11:13:24.517842 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4153 11:13:24.518376
4154 11:13:24.518720 [DATLAT]
4155 11:13:24.520911 Freq=600, CH0 RK0
4156 11:13:24.521339
4157 11:13:24.521679 DATLAT Default: 0x9
4158 11:13:24.524200 0, 0xFFFF, sum = 0
4159 11:13:24.527397 1, 0xFFFF, sum = 0
4160 11:13:24.527832 2, 0xFFFF, sum = 0
4161 11:13:24.531137 3, 0xFFFF, sum = 0
4162 11:13:24.531696 4, 0xFFFF, sum = 0
4163 11:13:24.534160 5, 0xFFFF, sum = 0
4164 11:13:24.534595 6, 0xFFFF, sum = 0
4165 11:13:24.537292 7, 0xFFFF, sum = 0
4166 11:13:24.537726 8, 0x0, sum = 1
4167 11:13:24.540956 9, 0x0, sum = 2
4168 11:13:24.541420 10, 0x0, sum = 3
4169 11:13:24.541795 11, 0x0, sum = 4
4170 11:13:24.544061 best_step = 9
4171 11:13:24.544564
4172 11:13:24.544925 ==
4173 11:13:24.547186 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 11:13:24.551020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 11:13:24.551501 ==
4176 11:13:24.554163 RX Vref Scan: 1
4177 11:13:24.554599
4178 11:13:24.555029 RX Vref 0 -> 0, step: 1
4179 11:13:24.555390
4180 11:13:24.557848 RX Delay -179 -> 252, step: 8
4181 11:13:24.558350
4182 11:13:24.560764 Set Vref, RX VrefLevel [Byte0]: 55
4183 11:13:24.564291 [Byte1]: 47
4184 11:13:24.568248
4185 11:13:24.568679 Final RX Vref Byte 0 = 55 to rank0
4186 11:13:24.571467 Final RX Vref Byte 1 = 47 to rank0
4187 11:13:24.575378 Final RX Vref Byte 0 = 55 to rank1
4188 11:13:24.578702 Final RX Vref Byte 1 = 47 to rank1==
4189 11:13:24.581485 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 11:13:24.588073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 11:13:24.588633 ==
4192 11:13:24.589126 DQS Delay:
4193 11:13:24.589500 DQS0 = 0, DQS1 = 0
4194 11:13:24.591320 DQM Delay:
4195 11:13:24.591937 DQM0 = 53, DQM1 = 45
4196 11:13:24.595315 DQ Delay:
4197 11:13:24.598549 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4198 11:13:24.598997 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4199 11:13:24.601590 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4200 11:13:24.604847 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4201 11:13:24.608241
4202 11:13:24.608671
4203 11:13:24.615424 [DQSOSCAuto] RK0, (LSB)MR18= 0x7164, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4204 11:13:24.618613 CH0 RK0: MR19=808, MR18=7164
4205 11:13:24.624895 CH0_RK0: MR19=0x808, MR18=0x7164, DQSOSC=388, MR23=63, INC=174, DEC=116
4206 11:13:24.625329
4207 11:13:24.628163 ----->DramcWriteLeveling(PI) begin...
4208 11:13:24.628599 ==
4209 11:13:24.632185 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 11:13:24.635225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 11:13:24.635822 ==
4212 11:13:24.638403 Write leveling (Byte 0): 35 => 35
4213 11:13:24.641566 Write leveling (Byte 1): 30 => 30
4214 11:13:24.645124 DramcWriteLeveling(PI) end<-----
4215 11:13:24.645555
4216 11:13:24.645921 ==
4217 11:13:24.648483 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 11:13:24.651465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 11:13:24.651892 ==
4220 11:13:24.655259 [Gating] SW mode calibration
4221 11:13:24.661907 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4222 11:13:24.668060 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4223 11:13:24.671428 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 11:13:24.674783 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 11:13:24.681503 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 11:13:24.684853 0 9 12 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 0)
4227 11:13:24.688122 0 9 16 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
4228 11:13:24.694837 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 11:13:24.698151 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 11:13:24.701492 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 11:13:24.707851 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 11:13:24.711152 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 11:13:24.714377 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 11:13:24.720915 0 10 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
4235 11:13:24.724870 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4236 11:13:24.727845 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 11:13:24.734288 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 11:13:24.737552 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 11:13:24.740858 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 11:13:24.747482 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 11:13:24.750672 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 11:13:24.753901 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 11:13:24.760951 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:13:24.764286 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:13:24.767217 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:13:24.773920 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:13:24.777292 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:13:24.780500 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:13:24.787167 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:13:24.790502 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:13:24.793821 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:13:24.797124 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:13:24.803818 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:13:24.807019 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 11:13:24.810829 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 11:13:24.817037 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:13:24.820352 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:13:24.824134 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4259 11:13:24.827484 Total UI for P1: 0, mck2ui 16
4260 11:13:24.830739 best dqsien dly found for B0: ( 0, 13, 10)
4261 11:13:24.836873 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4262 11:13:24.840239 Total UI for P1: 0, mck2ui 16
4263 11:13:24.844098 best dqsien dly found for B1: ( 0, 13, 12)
4264 11:13:24.847299 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4265 11:13:24.850367 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4266 11:13:24.850449
4267 11:13:24.853487 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4268 11:13:24.856789 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4269 11:13:24.860442 [Gating] SW calibration Done
4270 11:13:24.860524 ==
4271 11:13:24.863627 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 11:13:24.866783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 11:13:24.866865 ==
4274 11:13:24.870405 RX Vref Scan: 0
4275 11:13:24.870488
4276 11:13:24.873439 RX Vref 0 -> 0, step: 1
4277 11:13:24.873522
4278 11:13:24.873587 RX Delay -230 -> 252, step: 16
4279 11:13:24.880116 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4280 11:13:24.883128 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4281 11:13:24.886418 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4282 11:13:24.889679 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4283 11:13:24.896307 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4284 11:13:24.899648 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4285 11:13:24.903133 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4286 11:13:24.906395 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4287 11:13:24.909802 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4288 11:13:24.916356 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4289 11:13:24.919680 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4290 11:13:24.923019 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4291 11:13:24.926168 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4292 11:13:24.933303 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4293 11:13:24.936544 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4294 11:13:24.939863 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4295 11:13:24.939939 ==
4296 11:13:24.943031 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 11:13:24.949346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 11:13:24.949426 ==
4299 11:13:24.949491 DQS Delay:
4300 11:13:24.949551 DQS0 = 0, DQS1 = 0
4301 11:13:24.953402 DQM Delay:
4302 11:13:24.953476 DQM0 = 52, DQM1 = 43
4303 11:13:24.955975 DQ Delay:
4304 11:13:24.959688 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4305 11:13:24.959842 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =65
4306 11:13:24.962873 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4307 11:13:24.969391 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4308 11:13:24.969475
4309 11:13:24.969542
4310 11:13:24.969603 ==
4311 11:13:24.972538 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 11:13:24.976258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 11:13:24.976342 ==
4314 11:13:24.976408
4315 11:13:24.976470
4316 11:13:24.979286 TX Vref Scan disable
4317 11:13:24.979414 == TX Byte 0 ==
4318 11:13:24.985923 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4319 11:13:24.989143 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4320 11:13:24.989226 == TX Byte 1 ==
4321 11:13:24.995620 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4322 11:13:24.998959 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4323 11:13:24.999042 ==
4324 11:13:25.002954 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 11:13:25.006262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 11:13:25.006346 ==
4327 11:13:25.006412
4328 11:13:25.006474
4329 11:13:25.009521 TX Vref Scan disable
4330 11:13:25.012796 == TX Byte 0 ==
4331 11:13:25.016007 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4332 11:13:25.022740 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4333 11:13:25.022824 == TX Byte 1 ==
4334 11:13:25.026094 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4335 11:13:25.032598 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4336 11:13:25.032708
4337 11:13:25.032811 [DATLAT]
4338 11:13:25.032906 Freq=600, CH0 RK1
4339 11:13:25.033001
4340 11:13:25.035727 DATLAT Default: 0x9
4341 11:13:25.035814 0, 0xFFFF, sum = 0
4342 11:13:25.039030 1, 0xFFFF, sum = 0
4343 11:13:25.039136 2, 0xFFFF, sum = 0
4344 11:13:25.042351 3, 0xFFFF, sum = 0
4345 11:13:25.045711 4, 0xFFFF, sum = 0
4346 11:13:25.045798 5, 0xFFFF, sum = 0
4347 11:13:25.048891 6, 0xFFFF, sum = 0
4348 11:13:25.048977 7, 0xFFFF, sum = 0
4349 11:13:25.052163 8, 0x0, sum = 1
4350 11:13:25.052248 9, 0x0, sum = 2
4351 11:13:25.052316 10, 0x0, sum = 3
4352 11:13:25.055855 11, 0x0, sum = 4
4353 11:13:25.055943 best_step = 9
4354 11:13:25.056010
4355 11:13:25.056071 ==
4356 11:13:25.059212 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 11:13:25.065754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 11:13:25.065839 ==
4359 11:13:25.065906 RX Vref Scan: 0
4360 11:13:25.065966
4361 11:13:25.068708 RX Vref 0 -> 0, step: 1
4362 11:13:25.068804
4363 11:13:25.072490 RX Delay -163 -> 252, step: 8
4364 11:13:25.075609 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4365 11:13:25.082241 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4366 11:13:25.086170 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4367 11:13:25.089072 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4368 11:13:25.092749 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4369 11:13:25.095888 iDelay=205, Bit 5, Center 48 (-91 ~ 188) 280
4370 11:13:25.099059 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4371 11:13:25.105644 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4372 11:13:25.108985 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4373 11:13:25.112384 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4374 11:13:25.115645 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4375 11:13:25.122220 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4376 11:13:25.125526 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4377 11:13:25.128892 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4378 11:13:25.132205 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4379 11:13:25.135485 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4380 11:13:25.138677 ==
4381 11:13:25.141931 Dram Type= 6, Freq= 0, CH_0, rank 1
4382 11:13:25.145417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 11:13:25.145503 ==
4384 11:13:25.145567 DQS Delay:
4385 11:13:25.148659 DQS0 = 0, DQS1 = 0
4386 11:13:25.148739 DQM Delay:
4387 11:13:25.152115 DQM0 = 54, DQM1 = 45
4388 11:13:25.152194 DQ Delay:
4389 11:13:25.155357 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4390 11:13:25.159113 DQ4 =56, DQ5 =48, DQ6 =56, DQ7 =60
4391 11:13:25.162232 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =36
4392 11:13:25.165668 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4393 11:13:25.165748
4394 11:13:25.165811
4395 11:13:25.172087 [DQSOSCAuto] RK1, (LSB)MR18= 0x6625, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4396 11:13:25.175223 CH0 RK1: MR19=808, MR18=6625
4397 11:13:25.181682 CH0_RK1: MR19=0x808, MR18=0x6625, DQSOSC=390, MR23=63, INC=172, DEC=114
4398 11:13:25.184845 [RxdqsGatingPostProcess] freq 600
4399 11:13:25.191978 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4400 11:13:25.195280 Pre-setting of DQS Precalculation
4401 11:13:25.197990 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4402 11:13:25.198100 ==
4403 11:13:25.201875 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 11:13:25.205019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 11:13:25.205103 ==
4406 11:13:25.211741 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4407 11:13:25.218474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4408 11:13:25.221734 [CA 0] Center 35 (5~66) winsize 62
4409 11:13:25.225030 [CA 1] Center 36 (5~67) winsize 63
4410 11:13:25.228358 [CA 2] Center 34 (4~65) winsize 62
4411 11:13:25.231607 [CA 3] Center 34 (4~65) winsize 62
4412 11:13:25.235027 [CA 4] Center 34 (4~65) winsize 62
4413 11:13:25.238275 [CA 5] Center 34 (3~65) winsize 63
4414 11:13:25.238357
4415 11:13:25.241361 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4416 11:13:25.241443
4417 11:13:25.244668 [CATrainingPosCal] consider 1 rank data
4418 11:13:25.247948 u2DelayCellTimex100 = 270/100 ps
4419 11:13:25.251250 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4420 11:13:25.254888 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4421 11:13:25.258100 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4422 11:13:25.261329 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4423 11:13:25.264659 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4424 11:13:25.268361 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4425 11:13:25.271536
4426 11:13:25.274748 CA PerBit enable=1, Macro0, CA PI delay=34
4427 11:13:25.274821
4428 11:13:25.278133 [CBTSetCACLKResult] CA Dly = 34
4429 11:13:25.278205 CS Dly: 5 (0~36)
4430 11:13:25.278268 ==
4431 11:13:25.281199 Dram Type= 6, Freq= 0, CH_1, rank 1
4432 11:13:25.284913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 11:13:25.284987 ==
4434 11:13:25.291598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4435 11:13:25.298004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4436 11:13:25.301738 [CA 0] Center 36 (6~67) winsize 62
4437 11:13:25.305053 [CA 1] Center 36 (5~67) winsize 63
4438 11:13:25.308122 [CA 2] Center 34 (4~65) winsize 62
4439 11:13:25.311247 [CA 3] Center 34 (4~65) winsize 62
4440 11:13:25.314554 [CA 4] Center 34 (4~65) winsize 62
4441 11:13:25.318559 [CA 5] Center 34 (4~65) winsize 62
4442 11:13:25.318642
4443 11:13:25.321162 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4444 11:13:25.321245
4445 11:13:25.324438 [CATrainingPosCal] consider 2 rank data
4446 11:13:25.327793 u2DelayCellTimex100 = 270/100 ps
4447 11:13:25.331634 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4448 11:13:25.334928 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4449 11:13:25.338283 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4450 11:13:25.341664 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4451 11:13:25.344850 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4452 11:13:25.351399 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4453 11:13:25.351482
4454 11:13:25.354638 CA PerBit enable=1, Macro0, CA PI delay=34
4455 11:13:25.354725
4456 11:13:25.357977 [CBTSetCACLKResult] CA Dly = 34
4457 11:13:25.358060 CS Dly: 5 (0~37)
4458 11:13:25.358127
4459 11:13:25.361166 ----->DramcWriteLeveling(PI) begin...
4460 11:13:25.361250 ==
4461 11:13:25.364559 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 11:13:25.367855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 11:13:25.371235 ==
4464 11:13:25.374810 Write leveling (Byte 0): 29 => 29
4465 11:13:25.374893 Write leveling (Byte 1): 30 => 30
4466 11:13:25.378037 DramcWriteLeveling(PI) end<-----
4467 11:13:25.378146
4468 11:13:25.378241 ==
4469 11:13:25.381279 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 11:13:25.387780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 11:13:25.387886 ==
4472 11:13:25.387982 [Gating] SW mode calibration
4473 11:13:25.398052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4474 11:13:25.401169 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4475 11:13:25.408135 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4476 11:13:25.411455 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4477 11:13:25.414682 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 11:13:25.417788 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (0 1) (1 0)
4479 11:13:25.424719 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4480 11:13:25.428109 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 11:13:25.431468 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 11:13:25.437925 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 11:13:25.441152 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 11:13:25.444374 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 11:13:25.451467 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 11:13:25.454624 0 10 12 | B1->B0 | 3636 3c3c | 0 0 | (0 0) (0 0)
4487 11:13:25.457923 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 11:13:25.464642 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 11:13:25.468123 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 11:13:25.471275 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 11:13:25.478157 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 11:13:25.481328 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 11:13:25.484619 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 11:13:25.490838 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 11:13:25.494832 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 11:13:25.497529 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 11:13:25.504122 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 11:13:25.507966 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:13:25.510923 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 11:13:25.517930 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 11:13:25.521094 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:13:25.524133 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 11:13:25.528030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 11:13:25.534043 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 11:13:25.537780 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 11:13:25.541141 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 11:13:25.547826 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 11:13:25.550519 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:13:25.554462 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:13:25.560942 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4511 11:13:25.564158 Total UI for P1: 0, mck2ui 16
4512 11:13:25.567210 best dqsien dly found for B0: ( 0, 13, 10)
4513 11:13:25.570660 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 11:13:25.574057 Total UI for P1: 0, mck2ui 16
4515 11:13:25.577411 best dqsien dly found for B1: ( 0, 13, 12)
4516 11:13:25.580694 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4517 11:13:25.584015 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4518 11:13:25.584097
4519 11:13:25.587498 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4520 11:13:25.593780 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4521 11:13:25.593864 [Gating] SW calibration Done
4522 11:13:25.593930 ==
4523 11:13:25.597538 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 11:13:25.603898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 11:13:25.603982 ==
4526 11:13:25.604048 RX Vref Scan: 0
4527 11:13:25.604109
4528 11:13:25.607315 RX Vref 0 -> 0, step: 1
4529 11:13:25.607436
4530 11:13:25.610479 RX Delay -230 -> 252, step: 16
4531 11:13:25.613739 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4532 11:13:25.617067 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4533 11:13:25.620968 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4534 11:13:25.627501 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4535 11:13:25.630445 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4536 11:13:25.633732 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4537 11:13:25.637071 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4538 11:13:25.640409 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4539 11:13:25.647448 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4540 11:13:25.650746 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4541 11:13:25.653526 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4542 11:13:25.656856 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4543 11:13:25.664069 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4544 11:13:25.666807 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4545 11:13:25.670130 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4546 11:13:25.674131 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4547 11:13:25.674214 ==
4548 11:13:25.677420 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 11:13:25.683360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 11:13:25.683444 ==
4551 11:13:25.683510 DQS Delay:
4552 11:13:25.683572 DQS0 = 0, DQS1 = 0
4553 11:13:25.686728 DQM Delay:
4554 11:13:25.686811 DQM0 = 52, DQM1 = 50
4555 11:13:25.690065 DQ Delay:
4556 11:13:25.693994 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4557 11:13:25.697256 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4558 11:13:25.700388 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4559 11:13:25.703387 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4560 11:13:25.703472
4561 11:13:25.703538
4562 11:13:25.703599 ==
4563 11:13:25.706978 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 11:13:25.710393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 11:13:25.710477 ==
4566 11:13:25.710544
4567 11:13:25.710606
4568 11:13:25.713737 TX Vref Scan disable
4569 11:13:25.713821 == TX Byte 0 ==
4570 11:13:25.720469 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4571 11:13:25.723558 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4572 11:13:25.723642 == TX Byte 1 ==
4573 11:13:25.730042 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4574 11:13:25.733626 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4575 11:13:25.733712 ==
4576 11:13:25.736736 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 11:13:25.740544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 11:13:25.740628 ==
4579 11:13:25.740695
4580 11:13:25.740756
4581 11:13:25.743433 TX Vref Scan disable
4582 11:13:25.746510 == TX Byte 0 ==
4583 11:13:25.750405 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4584 11:13:25.753689 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4585 11:13:25.756984 == TX Byte 1 ==
4586 11:13:25.760476 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4587 11:13:25.763551 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4588 11:13:25.766825
4589 11:13:25.766909 [DATLAT]
4590 11:13:25.766975 Freq=600, CH1 RK0
4591 11:13:25.767038
4592 11:13:25.770035 DATLAT Default: 0x9
4593 11:13:25.770122 0, 0xFFFF, sum = 0
4594 11:13:25.773445 1, 0xFFFF, sum = 0
4595 11:13:25.773531 2, 0xFFFF, sum = 0
4596 11:13:25.776734 3, 0xFFFF, sum = 0
4597 11:13:25.776824 4, 0xFFFF, sum = 0
4598 11:13:25.780218 5, 0xFFFF, sum = 0
4599 11:13:25.783431 6, 0xFFFF, sum = 0
4600 11:13:25.783535 7, 0xFFFF, sum = 0
4601 11:13:25.783632 8, 0x0, sum = 1
4602 11:13:25.786682 9, 0x0, sum = 2
4603 11:13:25.786792 10, 0x0, sum = 3
4604 11:13:25.790137 11, 0x0, sum = 4
4605 11:13:25.790223 best_step = 9
4606 11:13:25.790289
4607 11:13:25.790351 ==
4608 11:13:25.793517 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 11:13:25.800137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 11:13:25.800229 ==
4611 11:13:25.800297 RX Vref Scan: 1
4612 11:13:25.800359
4613 11:13:25.803399 RX Vref 0 -> 0, step: 1
4614 11:13:25.803483
4615 11:13:25.806603 RX Delay -163 -> 252, step: 8
4616 11:13:25.806702
4617 11:13:25.810373 Set Vref, RX VrefLevel [Byte0]: 54
4618 11:13:25.813400 [Byte1]: 48
4619 11:13:25.813485
4620 11:13:25.816551 Final RX Vref Byte 0 = 54 to rank0
4621 11:13:25.819983 Final RX Vref Byte 1 = 48 to rank0
4622 11:13:25.823206 Final RX Vref Byte 0 = 54 to rank1
4623 11:13:25.826471 Final RX Vref Byte 1 = 48 to rank1==
4624 11:13:25.829667 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 11:13:25.833560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 11:13:25.833644 ==
4627 11:13:25.836803 DQS Delay:
4628 11:13:25.836886 DQS0 = 0, DQS1 = 0
4629 11:13:25.836953 DQM Delay:
4630 11:13:25.839933 DQM0 = 47, DQM1 = 45
4631 11:13:25.840017 DQ Delay:
4632 11:13:25.843583 DQ0 =48, DQ1 =40, DQ2 =36, DQ3 =44
4633 11:13:25.846577 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4634 11:13:25.850377 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4635 11:13:25.853396 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =60
4636 11:13:25.853479
4637 11:13:25.853545
4638 11:13:25.863239 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4639 11:13:25.863328 CH1 RK0: MR19=808, MR18=4D72
4640 11:13:25.870393 CH1_RK0: MR19=0x808, MR18=0x4D72, DQSOSC=388, MR23=63, INC=174, DEC=116
4641 11:13:25.870478
4642 11:13:25.873369 ----->DramcWriteLeveling(PI) begin...
4643 11:13:25.873453 ==
4644 11:13:25.876561 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 11:13:25.883282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 11:13:25.883404 ==
4647 11:13:25.886338 Write leveling (Byte 0): 30 => 30
4648 11:13:25.889704 Write leveling (Byte 1): 30 => 30
4649 11:13:25.893006 DramcWriteLeveling(PI) end<-----
4650 11:13:25.893090
4651 11:13:25.893156 ==
4652 11:13:25.896411 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 11:13:25.899670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 11:13:25.899753 ==
4655 11:13:25.902965 [Gating] SW mode calibration
4656 11:13:25.909510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4657 11:13:25.913351 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4658 11:13:25.919675 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4659 11:13:25.923634 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4660 11:13:25.926544 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 0)
4661 11:13:25.933103 0 9 12 | B1->B0 | 2d2d 2f2f | 1 0 | (1 0) (0 1)
4662 11:13:25.936307 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 11:13:25.939436 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 11:13:25.946001 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 11:13:25.949385 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 11:13:25.952486 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 11:13:25.959209 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 11:13:25.962959 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 11:13:25.965777 0 10 12 | B1->B0 | 3838 3737 | 0 0 | (0 0) (0 0)
4670 11:13:25.972919 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 11:13:25.976066 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 11:13:25.979260 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 11:13:25.985874 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 11:13:25.989231 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 11:13:25.992711 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 11:13:25.999290 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4677 11:13:26.002626 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4678 11:13:26.005861 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 11:13:26.012433 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 11:13:26.015602 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 11:13:26.018932 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 11:13:26.025474 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 11:13:26.029564 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 11:13:26.032509 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 11:13:26.039093 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 11:13:26.042238 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 11:13:26.045309 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 11:13:26.052689 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 11:13:26.055947 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 11:13:26.059032 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 11:13:26.065372 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:13:26.069056 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4693 11:13:26.072254 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4694 11:13:26.078713 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 11:13:26.078797 Total UI for P1: 0, mck2ui 16
4696 11:13:26.081902 best dqsien dly found for B0: ( 0, 13, 12)
4697 11:13:26.085724 Total UI for P1: 0, mck2ui 16
4698 11:13:26.088615 best dqsien dly found for B1: ( 0, 13, 10)
4699 11:13:26.095240 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4700 11:13:26.098739 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4701 11:13:26.098822
4702 11:13:26.102081 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4703 11:13:26.105478 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4704 11:13:26.108791 [Gating] SW calibration Done
4705 11:13:26.108875 ==
4706 11:13:26.112171 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 11:13:26.115283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 11:13:26.115414 ==
4709 11:13:26.118873 RX Vref Scan: 0
4710 11:13:26.118955
4711 11:13:26.119021 RX Vref 0 -> 0, step: 1
4712 11:13:26.119083
4713 11:13:26.121563 RX Delay -230 -> 252, step: 16
4714 11:13:26.125287 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4715 11:13:26.131842 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4716 11:13:26.135373 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4717 11:13:26.138329 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4718 11:13:26.141522 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4719 11:13:26.144799 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4720 11:13:26.151855 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4721 11:13:26.155041 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4722 11:13:26.158370 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4723 11:13:26.161657 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4724 11:13:26.168650 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4725 11:13:26.171847 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4726 11:13:26.175065 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4727 11:13:26.178103 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4728 11:13:26.181926 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4729 11:13:26.188208 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4730 11:13:26.188300 ==
4731 11:13:26.192221 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 11:13:26.194568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 11:13:26.194652 ==
4734 11:13:26.194719 DQS Delay:
4735 11:13:26.198655 DQS0 = 0, DQS1 = 0
4736 11:13:26.198737 DQM Delay:
4737 11:13:26.201214 DQM0 = 52, DQM1 = 51
4738 11:13:26.201299 DQ Delay:
4739 11:13:26.205270 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =49
4740 11:13:26.207909 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49
4741 11:13:26.211200 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4742 11:13:26.215309 DQ12 =65, DQ13 =65, DQ14 =57, DQ15 =65
4743 11:13:26.215406
4744 11:13:26.215473
4745 11:13:26.215534 ==
4746 11:13:26.218065 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 11:13:26.221366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 11:13:26.221449 ==
4749 11:13:26.224642
4750 11:13:26.224724
4751 11:13:26.224790 TX Vref Scan disable
4752 11:13:26.228003 == TX Byte 0 ==
4753 11:13:26.231236 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4754 11:13:26.234623 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4755 11:13:26.238148 == TX Byte 1 ==
4756 11:13:26.241456 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4757 11:13:26.244455 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4758 11:13:26.248346 ==
4759 11:13:26.248430 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 11:13:26.254837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 11:13:26.254921 ==
4762 11:13:26.254987
4763 11:13:26.255049
4764 11:13:26.257845 TX Vref Scan disable
4765 11:13:26.257929 == TX Byte 0 ==
4766 11:13:26.264627 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4767 11:13:26.267793 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4768 11:13:26.267896 == TX Byte 1 ==
4769 11:13:26.274445 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4770 11:13:26.277831 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4771 11:13:26.277908
4772 11:13:26.277972 [DATLAT]
4773 11:13:26.281130 Freq=600, CH1 RK1
4774 11:13:26.281227
4775 11:13:26.281316 DATLAT Default: 0x9
4776 11:13:26.284419 0, 0xFFFF, sum = 0
4777 11:13:26.284525 1, 0xFFFF, sum = 0
4778 11:13:26.287697 2, 0xFFFF, sum = 0
4779 11:13:26.287798 3, 0xFFFF, sum = 0
4780 11:13:26.291319 4, 0xFFFF, sum = 0
4781 11:13:26.291439 5, 0xFFFF, sum = 0
4782 11:13:26.294331 6, 0xFFFF, sum = 0
4783 11:13:26.294412 7, 0xFFFF, sum = 0
4784 11:13:26.298016 8, 0x0, sum = 1
4785 11:13:26.298104 9, 0x0, sum = 2
4786 11:13:26.301185 10, 0x0, sum = 3
4787 11:13:26.301259 11, 0x0, sum = 4
4788 11:13:26.304433 best_step = 9
4789 11:13:26.304510
4790 11:13:26.304572 ==
4791 11:13:26.307769 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 11:13:26.310989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 11:13:26.311089 ==
4794 11:13:26.314297 RX Vref Scan: 0
4795 11:13:26.314371
4796 11:13:26.314436 RX Vref 0 -> 0, step: 1
4797 11:13:26.314495
4798 11:13:26.317733 RX Delay -163 -> 252, step: 8
4799 11:13:26.324381 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4800 11:13:26.327797 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4801 11:13:26.331525 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4802 11:13:26.334900 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4803 11:13:26.337979 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4804 11:13:26.344747 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4805 11:13:26.347892 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4806 11:13:26.351052 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4807 11:13:26.354355 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4808 11:13:26.357723 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4809 11:13:26.364226 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4810 11:13:26.367744 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4811 11:13:26.371357 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4812 11:13:26.374610 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4813 11:13:26.381261 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4814 11:13:26.384463 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4815 11:13:26.384563 ==
4816 11:13:26.387594 Dram Type= 6, Freq= 0, CH_1, rank 1
4817 11:13:26.390851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4818 11:13:26.390933 ==
4819 11:13:26.394060 DQS Delay:
4820 11:13:26.394142 DQS0 = 0, DQS1 = 0
4821 11:13:26.394208 DQM Delay:
4822 11:13:26.397737 DQM0 = 49, DQM1 = 44
4823 11:13:26.397819 DQ Delay:
4824 11:13:26.401112 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4825 11:13:26.404388 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4826 11:13:26.407605 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =36
4827 11:13:26.411361 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4828 11:13:26.411456
4829 11:13:26.411521
4830 11:13:26.421275 [DQSOSCAuto] RK1, (LSB)MR18= 0x691f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4831 11:13:26.421359 CH1 RK1: MR19=808, MR18=691F
4832 11:13:26.427827 CH1_RK1: MR19=0x808, MR18=0x691F, DQSOSC=390, MR23=63, INC=172, DEC=114
4833 11:13:26.431060 [RxdqsGatingPostProcess] freq 600
4834 11:13:26.437842 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4835 11:13:26.440960 Pre-setting of DQS Precalculation
4836 11:13:26.444220 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4837 11:13:26.450921 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4838 11:13:26.460675 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4839 11:13:26.460757
4840 11:13:26.460822
4841 11:13:26.464032 [Calibration Summary] 1200 Mbps
4842 11:13:26.464114 CH 0, Rank 0
4843 11:13:26.467112 SW Impedance : PASS
4844 11:13:26.467195 DUTY Scan : NO K
4845 11:13:26.470969 ZQ Calibration : PASS
4846 11:13:26.474182 Jitter Meter : NO K
4847 11:13:26.474264 CBT Training : PASS
4848 11:13:26.477378 Write leveling : PASS
4849 11:13:26.477486 RX DQS gating : PASS
4850 11:13:26.480446 RX DQ/DQS(RDDQC) : PASS
4851 11:13:26.484202 TX DQ/DQS : PASS
4852 11:13:26.484296 RX DATLAT : PASS
4853 11:13:26.487436 RX DQ/DQS(Engine): PASS
4854 11:13:26.490704 TX OE : NO K
4855 11:13:26.490787 All Pass.
4856 11:13:26.490852
4857 11:13:26.490912 CH 0, Rank 1
4858 11:13:26.493794 SW Impedance : PASS
4859 11:13:26.496995 DUTY Scan : NO K
4860 11:13:26.497078 ZQ Calibration : PASS
4861 11:13:26.500869 Jitter Meter : NO K
4862 11:13:26.504191 CBT Training : PASS
4863 11:13:26.504287 Write leveling : PASS
4864 11:13:26.507448 RX DQS gating : PASS
4865 11:13:26.510591 RX DQ/DQS(RDDQC) : PASS
4866 11:13:26.510675 TX DQ/DQS : PASS
4867 11:13:26.513765 RX DATLAT : PASS
4868 11:13:26.516906 RX DQ/DQS(Engine): PASS
4869 11:13:26.516991 TX OE : NO K
4870 11:13:26.520772 All Pass.
4871 11:13:26.520856
4872 11:13:26.520923 CH 1, Rank 0
4873 11:13:26.524038 SW Impedance : PASS
4874 11:13:26.524122 DUTY Scan : NO K
4875 11:13:26.527425 ZQ Calibration : PASS
4876 11:13:26.527518 Jitter Meter : NO K
4877 11:13:26.530754 CBT Training : PASS
4878 11:13:26.534009 Write leveling : PASS
4879 11:13:26.534108 RX DQS gating : PASS
4880 11:13:26.537399 RX DQ/DQS(RDDQC) : PASS
4881 11:13:26.540615 TX DQ/DQS : PASS
4882 11:13:26.540714 RX DATLAT : PASS
4883 11:13:26.543987 RX DQ/DQS(Engine): PASS
4884 11:13:26.547444 TX OE : NO K
4885 11:13:26.547529 All Pass.
4886 11:13:26.547596
4887 11:13:26.547658 CH 1, Rank 1
4888 11:13:26.550658 SW Impedance : PASS
4889 11:13:26.553981 DUTY Scan : NO K
4890 11:13:26.554066 ZQ Calibration : PASS
4891 11:13:26.557326 Jitter Meter : NO K
4892 11:13:26.560578 CBT Training : PASS
4893 11:13:26.560667 Write leveling : PASS
4894 11:13:26.563732 RX DQS gating : PASS
4895 11:13:26.566770 RX DQ/DQS(RDDQC) : PASS
4896 11:13:26.566878 TX DQ/DQS : PASS
4897 11:13:26.570155 RX DATLAT : PASS
4898 11:13:26.573442 RX DQ/DQS(Engine): PASS
4899 11:13:26.573539 TX OE : NO K
4900 11:13:26.573624 All Pass.
4901 11:13:26.573703
4902 11:13:26.576704 DramC Write-DBI off
4903 11:13:26.580035 PER_BANK_REFRESH: Hybrid Mode
4904 11:13:26.580136 TX_TRACKING: ON
4905 11:13:26.590108 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4906 11:13:26.593239 [FAST_K] Save calibration result to emmc
4907 11:13:26.596914 dramc_set_vcore_voltage set vcore to 662500
4908 11:13:26.599997 Read voltage for 933, 3
4909 11:13:26.600081 Vio18 = 0
4910 11:13:26.603682 Vcore = 662500
4911 11:13:26.603767 Vdram = 0
4912 11:13:26.603833 Vddq = 0
4913 11:13:26.603895 Vmddr = 0
4914 11:13:26.610225 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4915 11:13:26.616535 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4916 11:13:26.616620 MEM_TYPE=3, freq_sel=17
4917 11:13:26.620248 sv_algorithm_assistance_LP4_1600
4918 11:13:26.623437 ============ PULL DRAM RESETB DOWN ============
4919 11:13:26.630028 ========== PULL DRAM RESETB DOWN end =========
4920 11:13:26.633226 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4921 11:13:26.636576 ===================================
4922 11:13:26.639864 LPDDR4 DRAM CONFIGURATION
4923 11:13:26.643232 ===================================
4924 11:13:26.643318 EX_ROW_EN[0] = 0x0
4925 11:13:26.646533 EX_ROW_EN[1] = 0x0
4926 11:13:26.646619 LP4Y_EN = 0x0
4927 11:13:26.649783 WORK_FSP = 0x0
4928 11:13:26.649907 WL = 0x3
4929 11:13:26.653044 RL = 0x3
4930 11:13:26.653153 BL = 0x2
4931 11:13:26.656432 RPST = 0x0
4932 11:13:26.659652 RD_PRE = 0x0
4933 11:13:26.659769 WR_PRE = 0x1
4934 11:13:26.663002 WR_PST = 0x0
4935 11:13:26.663126 DBI_WR = 0x0
4936 11:13:26.666299 DBI_RD = 0x0
4937 11:13:26.666403 OTF = 0x1
4938 11:13:26.670017 ===================================
4939 11:13:26.673222 ===================================
4940 11:13:26.673333 ANA top config
4941 11:13:26.676634 ===================================
4942 11:13:26.679791 DLL_ASYNC_EN = 0
4943 11:13:26.683063 ALL_SLAVE_EN = 1
4944 11:13:26.686327 NEW_RANK_MODE = 1
4945 11:13:26.689683 DLL_IDLE_MODE = 1
4946 11:13:26.689768 LP45_APHY_COMB_EN = 1
4947 11:13:26.693412 TX_ODT_DIS = 1
4948 11:13:26.696613 NEW_8X_MODE = 1
4949 11:13:26.699802 ===================================
4950 11:13:26.703067 ===================================
4951 11:13:26.706624 data_rate = 1866
4952 11:13:26.709512 CKR = 1
4953 11:13:26.709597 DQ_P2S_RATIO = 8
4954 11:13:26.713230 ===================================
4955 11:13:26.716457 CA_P2S_RATIO = 8
4956 11:13:26.719670 DQ_CA_OPEN = 0
4957 11:13:26.722808 DQ_SEMI_OPEN = 0
4958 11:13:26.726432 CA_SEMI_OPEN = 0
4959 11:13:26.729615 CA_FULL_RATE = 0
4960 11:13:26.729700 DQ_CKDIV4_EN = 1
4961 11:13:26.733159 CA_CKDIV4_EN = 1
4962 11:13:26.736409 CA_PREDIV_EN = 0
4963 11:13:26.739480 PH8_DLY = 0
4964 11:13:26.742698 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4965 11:13:26.745992 DQ_AAMCK_DIV = 4
4966 11:13:26.746077 CA_AAMCK_DIV = 4
4967 11:13:26.750011 CA_ADMCK_DIV = 4
4968 11:13:26.753221 DQ_TRACK_CA_EN = 0
4969 11:13:26.756408 CA_PICK = 933
4970 11:13:26.759721 CA_MCKIO = 933
4971 11:13:26.762981 MCKIO_SEMI = 0
4972 11:13:26.766417 PLL_FREQ = 3732
4973 11:13:26.766501 DQ_UI_PI_RATIO = 32
4974 11:13:26.769627 CA_UI_PI_RATIO = 0
4975 11:13:26.773045 ===================================
4976 11:13:26.776092 ===================================
4977 11:13:26.779839 memory_type:LPDDR4
4978 11:13:26.783227 GP_NUM : 10
4979 11:13:26.783339 SRAM_EN : 1
4980 11:13:26.786296 MD32_EN : 0
4981 11:13:26.789216 ===================================
4982 11:13:26.793135 [ANA_INIT] >>>>>>>>>>>>>>
4983 11:13:26.793261 <<<<<< [CONFIGURE PHASE]: ANA_TX
4984 11:13:26.796281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4985 11:13:26.799540 ===================================
4986 11:13:26.802868 data_rate = 1866,PCW = 0X8f00
4987 11:13:26.806205 ===================================
4988 11:13:26.809475 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4989 11:13:26.816381 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4990 11:13:26.823031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4991 11:13:26.826096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4992 11:13:26.829526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4993 11:13:26.832665 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4994 11:13:26.836355 [ANA_INIT] flow start
4995 11:13:26.836785 [ANA_INIT] PLL >>>>>>>>
4996 11:13:26.839436 [ANA_INIT] PLL <<<<<<<<
4997 11:13:26.843026 [ANA_INIT] MIDPI >>>>>>>>
4998 11:13:26.843492 [ANA_INIT] MIDPI <<<<<<<<
4999 11:13:26.846236 [ANA_INIT] DLL >>>>>>>>
5000 11:13:26.849824 [ANA_INIT] flow end
5001 11:13:26.853056 ============ LP4 DIFF to SE enter ============
5002 11:13:26.855773 ============ LP4 DIFF to SE exit ============
5003 11:13:26.859100 [ANA_INIT] <<<<<<<<<<<<<
5004 11:13:26.862433 [Flow] Enable top DCM control >>>>>
5005 11:13:26.865745 [Flow] Enable top DCM control <<<<<
5006 11:13:26.869170 Enable DLL master slave shuffle
5007 11:13:26.872432 ==============================================================
5008 11:13:26.875845 Gating Mode config
5009 11:13:26.883017 ==============================================================
5010 11:13:26.883554 Config description:
5011 11:13:26.892446 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5012 11:13:26.899070 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5013 11:13:26.906092 SELPH_MODE 0: By rank 1: By Phase
5014 11:13:26.909395 ==============================================================
5015 11:13:26.912922 GAT_TRACK_EN = 1
5016 11:13:26.915469 RX_GATING_MODE = 2
5017 11:13:26.918799 RX_GATING_TRACK_MODE = 2
5018 11:13:26.922706 SELPH_MODE = 1
5019 11:13:26.925864 PICG_EARLY_EN = 1
5020 11:13:26.929359 VALID_LAT_VALUE = 1
5021 11:13:26.932307 ==============================================================
5022 11:13:26.935768 Enter into Gating configuration >>>>
5023 11:13:26.938894 Exit from Gating configuration <<<<
5024 11:13:26.942680 Enter into DVFS_PRE_config >>>>>
5025 11:13:26.955616 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5026 11:13:26.959185 Exit from DVFS_PRE_config <<<<<
5027 11:13:26.959814 Enter into PICG configuration >>>>
5028 11:13:26.962410 Exit from PICG configuration <<<<
5029 11:13:26.965823 [RX_INPUT] configuration >>>>>
5030 11:13:26.969061 [RX_INPUT] configuration <<<<<
5031 11:13:26.975806 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5032 11:13:26.978963 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5033 11:13:26.985576 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5034 11:13:26.992519 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5035 11:13:26.998744 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5036 11:13:27.005313 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5037 11:13:27.008775 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5038 11:13:27.012449 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5039 11:13:27.015746 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5040 11:13:27.021752 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5041 11:13:27.025112 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5042 11:13:27.029116 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5043 11:13:27.032444 ===================================
5044 11:13:27.035591 LPDDR4 DRAM CONFIGURATION
5045 11:13:27.038579 ===================================
5046 11:13:27.042037 EX_ROW_EN[0] = 0x0
5047 11:13:27.042413 EX_ROW_EN[1] = 0x0
5048 11:13:27.045242 LP4Y_EN = 0x0
5049 11:13:27.045872 WORK_FSP = 0x0
5050 11:13:27.048734 WL = 0x3
5051 11:13:27.049180 RL = 0x3
5052 11:13:27.052543 BL = 0x2
5053 11:13:27.052973 RPST = 0x0
5054 11:13:27.055652 RD_PRE = 0x0
5055 11:13:27.056092 WR_PRE = 0x1
5056 11:13:27.058838 WR_PST = 0x0
5057 11:13:27.059408 DBI_WR = 0x0
5058 11:13:27.061920 DBI_RD = 0x0
5059 11:13:27.062380 OTF = 0x1
5060 11:13:27.065621 ===================================
5061 11:13:27.068616 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5062 11:13:27.075282 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5063 11:13:27.079147 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5064 11:13:27.081891 ===================================
5065 11:13:27.085277 LPDDR4 DRAM CONFIGURATION
5066 11:13:27.088505 ===================================
5067 11:13:27.088988 EX_ROW_EN[0] = 0x10
5068 11:13:27.091839 EX_ROW_EN[1] = 0x0
5069 11:13:27.095184 LP4Y_EN = 0x0
5070 11:13:27.095666 WORK_FSP = 0x0
5071 11:13:27.098474 WL = 0x3
5072 11:13:27.098904 RL = 0x3
5073 11:13:27.101978 BL = 0x2
5074 11:13:27.102401 RPST = 0x0
5075 11:13:27.105526 RD_PRE = 0x0
5076 11:13:27.106039 WR_PRE = 0x1
5077 11:13:27.108999 WR_PST = 0x0
5078 11:13:27.109458 DBI_WR = 0x0
5079 11:13:27.112234 DBI_RD = 0x0
5080 11:13:27.112667 OTF = 0x1
5081 11:13:27.115320 ===================================
5082 11:13:27.121685 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5083 11:13:27.126488 nWR fixed to 30
5084 11:13:27.129068 [ModeRegInit_LP4] CH0 RK0
5085 11:13:27.129492 [ModeRegInit_LP4] CH0 RK1
5086 11:13:27.132357 [ModeRegInit_LP4] CH1 RK0
5087 11:13:27.135670 [ModeRegInit_LP4] CH1 RK1
5088 11:13:27.136095 match AC timing 9
5089 11:13:27.142915 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5090 11:13:27.145701 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5091 11:13:27.148871 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5092 11:13:27.155988 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5093 11:13:27.158961 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5094 11:13:27.159458 ==
5095 11:13:27.162138 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 11:13:27.165906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 11:13:27.166365 ==
5098 11:13:27.172302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5099 11:13:27.178966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5100 11:13:27.182385 [CA 0] Center 37 (6~68) winsize 63
5101 11:13:27.185547 [CA 1] Center 37 (7~68) winsize 62
5102 11:13:27.188788 [CA 2] Center 34 (4~65) winsize 62
5103 11:13:27.192127 [CA 3] Center 33 (3~64) winsize 62
5104 11:13:27.195444 [CA 4] Center 33 (3~64) winsize 62
5105 11:13:27.198729 [CA 5] Center 32 (2~62) winsize 61
5106 11:13:27.199278
5107 11:13:27.202046 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5108 11:13:27.202605
5109 11:13:27.205365 [CATrainingPosCal] consider 1 rank data
5110 11:13:27.208473 u2DelayCellTimex100 = 270/100 ps
5111 11:13:27.211908 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5112 11:13:27.215167 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5113 11:13:27.218117 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5114 11:13:27.221802 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5115 11:13:27.224955 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5116 11:13:27.231431 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5117 11:13:27.231517
5118 11:13:27.234775 CA PerBit enable=1, Macro0, CA PI delay=32
5119 11:13:27.234859
5120 11:13:27.238521 [CBTSetCACLKResult] CA Dly = 32
5121 11:13:27.238604 CS Dly: 5 (0~36)
5122 11:13:27.238670 ==
5123 11:13:27.241383 Dram Type= 6, Freq= 0, CH_0, rank 1
5124 11:13:27.244518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 11:13:27.247900 ==
5126 11:13:27.251152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5127 11:13:27.257779 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5128 11:13:27.261714 [CA 0] Center 37 (6~68) winsize 63
5129 11:13:27.264811 [CA 1] Center 37 (7~68) winsize 62
5130 11:13:27.268337 [CA 2] Center 34 (4~65) winsize 62
5131 11:13:27.271225 [CA 3] Center 34 (3~65) winsize 63
5132 11:13:27.274702 [CA 4] Center 33 (3~63) winsize 61
5133 11:13:27.277980 [CA 5] Center 32 (2~62) winsize 61
5134 11:13:27.278063
5135 11:13:27.281128 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5136 11:13:27.281210
5137 11:13:27.284893 [CATrainingPosCal] consider 2 rank data
5138 11:13:27.288130 u2DelayCellTimex100 = 270/100 ps
5139 11:13:27.291537 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5140 11:13:27.294833 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5141 11:13:27.298086 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5142 11:13:27.301397 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5143 11:13:27.308108 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5144 11:13:27.311288 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5145 11:13:27.311440
5146 11:13:27.314479 CA PerBit enable=1, Macro0, CA PI delay=32
5147 11:13:27.314561
5148 11:13:27.317714 [CBTSetCACLKResult] CA Dly = 32
5149 11:13:27.317798 CS Dly: 6 (0~38)
5150 11:13:27.317919
5151 11:13:27.321509 ----->DramcWriteLeveling(PI) begin...
5152 11:13:27.321593 ==
5153 11:13:27.324516 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 11:13:27.331484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 11:13:27.331568 ==
5156 11:13:27.334738 Write leveling (Byte 0): 34 => 34
5157 11:13:27.337881 Write leveling (Byte 1): 30 => 30
5158 11:13:27.337964 DramcWriteLeveling(PI) end<-----
5159 11:13:27.338060
5160 11:13:27.341075 ==
5161 11:13:27.341159 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 11:13:27.347864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 11:13:27.347949 ==
5164 11:13:27.351184 [Gating] SW mode calibration
5165 11:13:27.357740 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5166 11:13:27.361016 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5167 11:13:27.367669 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5168 11:13:27.371651 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 11:13:27.374650 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 11:13:27.380914 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 11:13:27.384774 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 11:13:27.387939 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5173 11:13:27.394658 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5174 11:13:27.397999 0 14 28 | B1->B0 | 3333 2424 | 1 0 | (1 1) (1 0)
5175 11:13:27.401485 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5176 11:13:27.407590 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 11:13:27.411452 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 11:13:27.414763 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 11:13:27.418058 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 11:13:27.424421 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 11:13:27.427676 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 11:13:27.430906 0 15 28 | B1->B0 | 2424 4242 | 0 1 | (0 0) (0 0)
5183 11:13:27.437789 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5184 11:13:27.440816 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 11:13:27.444605 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 11:13:27.451176 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 11:13:27.454356 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 11:13:27.457728 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 11:13:27.464082 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 11:13:27.467462 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5191 11:13:27.470808 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5192 11:13:27.477702 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 11:13:27.480816 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 11:13:27.484077 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 11:13:27.491353 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 11:13:27.494447 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 11:13:27.497533 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 11:13:27.504552 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 11:13:27.507970 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 11:13:27.511268 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 11:13:27.517914 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 11:13:27.521250 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 11:13:27.524559 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 11:13:27.527557 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:13:27.534125 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5206 11:13:27.538004 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5207 11:13:27.541219 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 11:13:27.544338 Total UI for P1: 0, mck2ui 16
5209 11:13:27.547950 best dqsien dly found for B0: ( 1, 2, 26)
5210 11:13:27.551023 Total UI for P1: 0, mck2ui 16
5211 11:13:27.554380 best dqsien dly found for B1: ( 1, 2, 28)
5212 11:13:27.557654 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5213 11:13:27.560802 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5214 11:13:27.560878
5215 11:13:27.567441 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5216 11:13:27.570762 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5217 11:13:27.574044 [Gating] SW calibration Done
5218 11:13:27.574114 ==
5219 11:13:27.577553 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 11:13:27.580856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 11:13:27.580929 ==
5222 11:13:27.580993 RX Vref Scan: 0
5223 11:13:27.581054
5224 11:13:27.584144 RX Vref 0 -> 0, step: 1
5225 11:13:27.584221
5226 11:13:27.587400 RX Delay -80 -> 252, step: 8
5227 11:13:27.591219 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5228 11:13:27.594508 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5229 11:13:27.600906 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5230 11:13:27.604225 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5231 11:13:27.607605 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5232 11:13:27.610788 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5233 11:13:27.614068 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5234 11:13:27.617399 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5235 11:13:27.620723 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5236 11:13:27.627294 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5237 11:13:27.630627 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5238 11:13:27.634368 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5239 11:13:27.637729 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5240 11:13:27.640447 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5241 11:13:27.647088 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5242 11:13:27.650937 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5243 11:13:27.651017 ==
5244 11:13:27.654091 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 11:13:27.657234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 11:13:27.657320 ==
5247 11:13:27.657390 DQS Delay:
5248 11:13:27.660877 DQS0 = 0, DQS1 = 0
5249 11:13:27.660974 DQM Delay:
5250 11:13:27.664327 DQM0 = 104, DQM1 = 95
5251 11:13:27.664410 DQ Delay:
5252 11:13:27.667117 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5253 11:13:27.670521 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5254 11:13:27.673754 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5255 11:13:27.677744 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5256 11:13:27.677827
5257 11:13:27.677893
5258 11:13:27.677951 ==
5259 11:13:27.680924 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 11:13:27.687607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 11:13:27.687691 ==
5262 11:13:27.687756
5263 11:13:27.687816
5264 11:13:27.687873 TX Vref Scan disable
5265 11:13:27.691372 == TX Byte 0 ==
5266 11:13:27.694474 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5267 11:13:27.701381 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5268 11:13:27.701465 == TX Byte 1 ==
5269 11:13:27.704373 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5270 11:13:27.711077 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5271 11:13:27.711156 ==
5272 11:13:27.714209 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 11:13:27.717502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 11:13:27.717585 ==
5275 11:13:27.717651
5276 11:13:27.717713
5277 11:13:27.720741 TX Vref Scan disable
5278 11:13:27.720825 == TX Byte 0 ==
5279 11:13:27.727626 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5280 11:13:27.730908 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5281 11:13:27.730997 == TX Byte 1 ==
5282 11:13:27.737939 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5283 11:13:27.741240 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5284 11:13:27.741357
5285 11:13:27.741440 [DATLAT]
5286 11:13:27.744646 Freq=933, CH0 RK0
5287 11:13:27.744760
5288 11:13:27.744849 DATLAT Default: 0xd
5289 11:13:27.747982 0, 0xFFFF, sum = 0
5290 11:13:27.748110 1, 0xFFFF, sum = 0
5291 11:13:27.751431 2, 0xFFFF, sum = 0
5292 11:13:27.751560 3, 0xFFFF, sum = 0
5293 11:13:27.754776 4, 0xFFFF, sum = 0
5294 11:13:27.754915 5, 0xFFFF, sum = 0
5295 11:13:27.757838 6, 0xFFFF, sum = 0
5296 11:13:27.757995 7, 0xFFFF, sum = 0
5297 11:13:27.760939 8, 0xFFFF, sum = 0
5298 11:13:27.764575 9, 0xFFFF, sum = 0
5299 11:13:27.764754 10, 0x0, sum = 1
5300 11:13:27.764895 11, 0x0, sum = 2
5301 11:13:27.767671 12, 0x0, sum = 3
5302 11:13:27.767886 13, 0x0, sum = 4
5303 11:13:27.770816 best_step = 11
5304 11:13:27.770898
5305 11:13:27.770963 ==
5306 11:13:27.774161 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 11:13:27.777533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 11:13:27.777617 ==
5309 11:13:27.780834 RX Vref Scan: 1
5310 11:13:27.780916
5311 11:13:27.780983 RX Vref 0 -> 0, step: 1
5312 11:13:27.781045
5313 11:13:27.784211 RX Delay -53 -> 252, step: 4
5314 11:13:27.784284
5315 11:13:27.787546 Set Vref, RX VrefLevel [Byte0]: 55
5316 11:13:27.791009 [Byte1]: 47
5317 11:13:27.795042
5318 11:13:27.795115 Final RX Vref Byte 0 = 55 to rank0
5319 11:13:27.798240 Final RX Vref Byte 1 = 47 to rank0
5320 11:13:27.801707 Final RX Vref Byte 0 = 55 to rank1
5321 11:13:27.805175 Final RX Vref Byte 1 = 47 to rank1==
5322 11:13:27.808174 Dram Type= 6, Freq= 0, CH_0, rank 0
5323 11:13:27.815154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 11:13:27.815232 ==
5325 11:13:27.815297 DQS Delay:
5326 11:13:27.815392 DQS0 = 0, DQS1 = 0
5327 11:13:27.818445 DQM Delay:
5328 11:13:27.818512 DQM0 = 104, DQM1 = 95
5329 11:13:27.821683 DQ Delay:
5330 11:13:27.824873 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =104
5331 11:13:27.828272 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5332 11:13:27.831574 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =88
5333 11:13:27.834866 DQ12 =100, DQ13 =102, DQ14 =104, DQ15 =104
5334 11:13:27.834940
5335 11:13:27.835003
5336 11:13:27.841425 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5337 11:13:27.844713 CH0 RK0: MR19=505, MR18=3129
5338 11:13:27.851230 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5339 11:13:27.851316
5340 11:13:27.854585 ----->DramcWriteLeveling(PI) begin...
5341 11:13:27.854669 ==
5342 11:13:27.858578 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 11:13:27.861868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 11:13:27.861953 ==
5345 11:13:27.865094 Write leveling (Byte 0): 33 => 33
5346 11:13:27.868210 Write leveling (Byte 1): 29 => 29
5347 11:13:27.871471 DramcWriteLeveling(PI) end<-----
5348 11:13:27.871554
5349 11:13:27.871631 ==
5350 11:13:27.874750 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 11:13:27.881400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 11:13:27.881495 ==
5353 11:13:27.881562 [Gating] SW mode calibration
5354 11:13:27.891357 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5355 11:13:27.894641 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5356 11:13:27.897951 0 14 0 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5357 11:13:27.904631 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 11:13:27.907869 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 11:13:27.911591 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 11:13:27.918034 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 11:13:27.921662 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 11:13:27.924905 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 11:13:27.931255 0 14 28 | B1->B0 | 2a2a 2c2c | 0 0 | (0 1) (1 0)
5364 11:13:27.934518 0 15 0 | B1->B0 | 2424 2626 | 0 0 | (0 0) (1 1)
5365 11:13:27.938286 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 11:13:27.944828 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 11:13:27.947979 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 11:13:27.951199 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 11:13:27.957758 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 11:13:27.961042 0 15 24 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
5371 11:13:27.964373 0 15 28 | B1->B0 | 3939 3736 | 0 1 | (0 0) (0 0)
5372 11:13:27.970844 1 0 0 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5373 11:13:27.974729 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 11:13:27.977775 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 11:13:27.984279 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 11:13:27.987510 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 11:13:27.991530 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 11:13:27.998164 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 11:13:28.001436 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5380 11:13:28.004885 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:13:28.007647 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:13:28.014542 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 11:13:28.017909 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:13:28.021345 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 11:13:28.027629 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 11:13:28.030867 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:13:28.034775 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:13:28.040985 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 11:13:28.044096 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 11:13:28.048003 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 11:13:28.054286 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:13:28.057566 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 11:13:28.060770 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:13:28.067465 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:13:28.070744 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:13:28.074036 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5397 11:13:28.077990 Total UI for P1: 0, mck2ui 16
5398 11:13:28.081138 best dqsien dly found for B1: ( 1, 2, 30)
5399 11:13:28.087425 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 11:13:28.087501 Total UI for P1: 0, mck2ui 16
5401 11:13:28.091304 best dqsien dly found for B0: ( 1, 3, 0)
5402 11:13:28.094398 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5403 11:13:28.101028 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5404 11:13:28.101110
5405 11:13:28.104341 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5406 11:13:28.107602 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5407 11:13:28.110855 [Gating] SW calibration Done
5408 11:13:28.110935 ==
5409 11:13:28.114207 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 11:13:28.117373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 11:13:28.117454 ==
5412 11:13:28.117518 RX Vref Scan: 0
5413 11:13:28.121307
5414 11:13:28.121402 RX Vref 0 -> 0, step: 1
5415 11:13:28.121465
5416 11:13:28.124602 RX Delay -80 -> 252, step: 8
5417 11:13:28.127905 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5418 11:13:28.131135 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5419 11:13:28.137934 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5420 11:13:28.141152 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5421 11:13:28.144334 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5422 11:13:28.147398 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5423 11:13:28.151029 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5424 11:13:28.157457 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5425 11:13:28.160635 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5426 11:13:28.164602 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5427 11:13:28.167785 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5428 11:13:28.170920 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5429 11:13:28.174237 iDelay=208, Bit 12, Center 99 (16 ~ 183) 168
5430 11:13:28.180768 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5431 11:13:28.184085 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5432 11:13:28.187299 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5433 11:13:28.187421 ==
5434 11:13:28.190432 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 11:13:28.194095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 11:13:28.194178 ==
5437 11:13:28.197479 DQS Delay:
5438 11:13:28.197561 DQS0 = 0, DQS1 = 0
5439 11:13:28.201102 DQM Delay:
5440 11:13:28.201184 DQM0 = 105, DQM1 = 95
5441 11:13:28.201249 DQ Delay:
5442 11:13:28.203771 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =99
5443 11:13:28.206987 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =111
5444 11:13:28.210983 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5445 11:13:28.217641 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =103
5446 11:13:28.217749
5447 11:13:28.217881
5448 11:13:28.217969 ==
5449 11:13:28.220864 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 11:13:28.224007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 11:13:28.224091 ==
5452 11:13:28.224155
5453 11:13:28.224215
5454 11:13:28.227263 TX Vref Scan disable
5455 11:13:28.227382 == TX Byte 0 ==
5456 11:13:28.233925 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5457 11:13:28.237202 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5458 11:13:28.237282 == TX Byte 1 ==
5459 11:13:28.244328 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5460 11:13:28.247468 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5461 11:13:28.247551 ==
5462 11:13:28.250448 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 11:13:28.254262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 11:13:28.254370 ==
5465 11:13:28.254464
5466 11:13:28.254552
5467 11:13:28.257598 TX Vref Scan disable
5468 11:13:28.260684 == TX Byte 0 ==
5469 11:13:28.263847 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5470 11:13:28.267495 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5471 11:13:28.270675 == TX Byte 1 ==
5472 11:13:28.274249 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5473 11:13:28.277283 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5474 11:13:28.277382
5475 11:13:28.280369 [DATLAT]
5476 11:13:28.280480 Freq=933, CH0 RK1
5477 11:13:28.280550
5478 11:13:28.283707 DATLAT Default: 0xb
5479 11:13:28.283789 0, 0xFFFF, sum = 0
5480 11:13:28.287527 1, 0xFFFF, sum = 0
5481 11:13:28.287611 2, 0xFFFF, sum = 0
5482 11:13:28.290781 3, 0xFFFF, sum = 0
5483 11:13:28.290864 4, 0xFFFF, sum = 0
5484 11:13:28.294021 5, 0xFFFF, sum = 0
5485 11:13:28.294105 6, 0xFFFF, sum = 0
5486 11:13:28.297246 7, 0xFFFF, sum = 0
5487 11:13:28.297329 8, 0xFFFF, sum = 0
5488 11:13:28.300796 9, 0xFFFF, sum = 0
5489 11:13:28.300879 10, 0x0, sum = 1
5490 11:13:28.303955 11, 0x0, sum = 2
5491 11:13:28.304039 12, 0x0, sum = 3
5492 11:13:28.307211 13, 0x0, sum = 4
5493 11:13:28.307320 best_step = 11
5494 11:13:28.307424
5495 11:13:28.307486 ==
5496 11:13:28.310467 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 11:13:28.317083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 11:13:28.317171 ==
5499 11:13:28.317238 RX Vref Scan: 0
5500 11:13:28.317299
5501 11:13:28.320468 RX Vref 0 -> 0, step: 1
5502 11:13:28.320551
5503 11:13:28.323720 RX Delay -45 -> 252, step: 4
5504 11:13:28.327421 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5505 11:13:28.330777 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5506 11:13:28.337160 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5507 11:13:28.340453 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5508 11:13:28.343683 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5509 11:13:28.346858 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5510 11:13:28.350069 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5511 11:13:28.356908 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5512 11:13:28.359977 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5513 11:13:28.363888 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5514 11:13:28.367070 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5515 11:13:28.370524 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5516 11:13:28.373691 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5517 11:13:28.380196 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5518 11:13:28.383525 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5519 11:13:28.386860 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5520 11:13:28.386971 ==
5521 11:13:28.390361 Dram Type= 6, Freq= 0, CH_0, rank 1
5522 11:13:28.393600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 11:13:28.396914 ==
5524 11:13:28.397024 DQS Delay:
5525 11:13:28.397117 DQS0 = 0, DQS1 = 0
5526 11:13:28.400278 DQM Delay:
5527 11:13:28.400389 DQM0 = 104, DQM1 = 94
5528 11:13:28.403246 DQ Delay:
5529 11:13:28.406458 DQ0 =104, DQ1 =108, DQ2 =102, DQ3 =102
5530 11:13:28.410188 DQ4 =106, DQ5 =96, DQ6 =108, DQ7 =112
5531 11:13:28.413323 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5532 11:13:28.416523 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5533 11:13:28.416600
5534 11:13:28.416664
5535 11:13:28.423691 [DQSOSCAuto] RK1, (LSB)MR18= 0x2903, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5536 11:13:28.426968 CH0 RK1: MR19=505, MR18=2903
5537 11:13:28.433317 CH0_RK1: MR19=0x505, MR18=0x2903, DQSOSC=408, MR23=63, INC=65, DEC=43
5538 11:13:28.436646 [RxdqsGatingPostProcess] freq 933
5539 11:13:28.443110 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5540 11:13:28.443214 best DQS0 dly(2T, 0.5T) = (0, 10)
5541 11:13:28.447019 best DQS1 dly(2T, 0.5T) = (0, 10)
5542 11:13:28.449726 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5543 11:13:28.452996 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5544 11:13:28.457055 best DQS0 dly(2T, 0.5T) = (0, 11)
5545 11:13:28.459568 best DQS1 dly(2T, 0.5T) = (0, 10)
5546 11:13:28.463145 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5547 11:13:28.466206 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5548 11:13:28.469999 Pre-setting of DQS Precalculation
5549 11:13:28.476378 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5550 11:13:28.476493 ==
5551 11:13:28.479459 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 11:13:28.483026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 11:13:28.483132 ==
5554 11:13:28.486289 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5555 11:13:28.493022 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5556 11:13:28.497007 [CA 0] Center 36 (6~67) winsize 62
5557 11:13:28.500449 [CA 1] Center 37 (6~68) winsize 63
5558 11:13:28.503663 [CA 2] Center 35 (5~65) winsize 61
5559 11:13:28.506829 [CA 3] Center 34 (4~65) winsize 62
5560 11:13:28.510094 [CA 4] Center 34 (4~65) winsize 62
5561 11:13:28.513638 [CA 5] Center 33 (3~64) winsize 62
5562 11:13:28.513742
5563 11:13:28.516791 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5564 11:13:28.516901
5565 11:13:28.519792 [CATrainingPosCal] consider 1 rank data
5566 11:13:28.522995 u2DelayCellTimex100 = 270/100 ps
5567 11:13:28.526316 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5568 11:13:28.533506 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5569 11:13:28.536712 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5570 11:13:28.540150 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5571 11:13:28.543485 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5572 11:13:28.546691 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5573 11:13:28.546850
5574 11:13:28.550071 CA PerBit enable=1, Macro0, CA PI delay=33
5575 11:13:28.550179
5576 11:13:28.553113 [CBTSetCACLKResult] CA Dly = 33
5577 11:13:28.553214 CS Dly: 6 (0~37)
5578 11:13:28.556461 ==
5579 11:13:28.559776 Dram Type= 6, Freq= 0, CH_1, rank 1
5580 11:13:28.563083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 11:13:28.563186 ==
5582 11:13:28.567016 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5583 11:13:28.572867 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5584 11:13:28.576574 [CA 0] Center 36 (6~67) winsize 62
5585 11:13:28.580007 [CA 1] Center 37 (6~68) winsize 63
5586 11:13:28.583699 [CA 2] Center 35 (5~65) winsize 61
5587 11:13:28.586716 [CA 3] Center 34 (4~65) winsize 62
5588 11:13:28.590125 [CA 4] Center 34 (4~65) winsize 62
5589 11:13:28.593687 [CA 5] Center 34 (4~64) winsize 61
5590 11:13:28.593795
5591 11:13:28.596829 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5592 11:13:28.596930
5593 11:13:28.600238 [CATrainingPosCal] consider 2 rank data
5594 11:13:28.603438 u2DelayCellTimex100 = 270/100 ps
5595 11:13:28.606767 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5596 11:13:28.610193 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5597 11:13:28.616663 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5598 11:13:28.619930 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5599 11:13:28.623288 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5600 11:13:28.626933 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5601 11:13:28.627043
5602 11:13:28.629826 CA PerBit enable=1, Macro0, CA PI delay=34
5603 11:13:28.629927
5604 11:13:28.633775 [CBTSetCACLKResult] CA Dly = 34
5605 11:13:28.633883 CS Dly: 7 (0~40)
5606 11:13:28.633978
5607 11:13:28.636438 ----->DramcWriteLeveling(PI) begin...
5608 11:13:28.640237 ==
5609 11:13:28.643443 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 11:13:28.646750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 11:13:28.646860 ==
5612 11:13:28.649905 Write leveling (Byte 0): 25 => 25
5613 11:13:28.653195 Write leveling (Byte 1): 27 => 27
5614 11:13:28.657054 DramcWriteLeveling(PI) end<-----
5615 11:13:28.657159
5616 11:13:28.657259 ==
5617 11:13:28.659713 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 11:13:28.663502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 11:13:28.663581 ==
5620 11:13:28.666993 [Gating] SW mode calibration
5621 11:13:28.673526 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5622 11:13:28.676844 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5623 11:13:28.683138 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 11:13:28.686533 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 11:13:28.689932 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 11:13:28.696765 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 11:13:28.699723 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 11:13:28.703533 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 11:13:28.709988 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
5630 11:13:28.713360 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5631 11:13:28.716541 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 11:13:28.723248 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 11:13:28.726653 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 11:13:28.729711 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 11:13:28.736673 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 11:13:28.740073 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 11:13:28.743236 0 15 24 | B1->B0 | 2424 3232 | 0 1 | (0 0) (0 0)
5638 11:13:28.749707 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5639 11:13:28.753028 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 11:13:28.756378 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 11:13:28.763268 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 11:13:28.766455 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 11:13:28.769797 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 11:13:28.776339 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 11:13:28.779557 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5646 11:13:28.782808 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 11:13:28.789483 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:13:28.792789 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:13:28.796143 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:13:28.802639 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 11:13:28.805990 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 11:13:28.809217 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:13:28.816116 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 11:13:28.819241 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 11:13:28.822520 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:13:28.829327 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:13:28.832636 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 11:13:28.835772 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:13:28.839215 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:13:28.846142 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5661 11:13:28.849254 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5662 11:13:28.852178 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5663 11:13:28.859578 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 11:13:28.862263 Total UI for P1: 0, mck2ui 16
5665 11:13:28.866066 best dqsien dly found for B0: ( 1, 2, 24)
5666 11:13:28.869322 Total UI for P1: 0, mck2ui 16
5667 11:13:28.872437 best dqsien dly found for B1: ( 1, 2, 24)
5668 11:13:28.875711 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5669 11:13:28.878962 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5670 11:13:28.879045
5671 11:13:28.883000 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5672 11:13:28.885640 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5673 11:13:28.889000 [Gating] SW calibration Done
5674 11:13:28.889083 ==
5675 11:13:28.892756 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 11:13:28.895859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 11:13:28.895943 ==
5678 11:13:28.898980 RX Vref Scan: 0
5679 11:13:28.899061
5680 11:13:28.899126 RX Vref 0 -> 0, step: 1
5681 11:13:28.902151
5682 11:13:28.902233 RX Delay -80 -> 252, step: 8
5683 11:13:28.908593 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5684 11:13:28.912598 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5685 11:13:28.915753 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5686 11:13:28.918947 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5687 11:13:28.922100 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5688 11:13:28.925857 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5689 11:13:28.931961 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5690 11:13:28.935291 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5691 11:13:28.938641 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5692 11:13:28.942429 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5693 11:13:28.945721 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5694 11:13:28.948843 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5695 11:13:28.955702 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5696 11:13:28.958770 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5697 11:13:28.962080 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5698 11:13:28.965429 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5699 11:13:28.965520 ==
5700 11:13:28.968615 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 11:13:28.975566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 11:13:28.975651 ==
5703 11:13:28.975718 DQS Delay:
5704 11:13:28.975780 DQS0 = 0, DQS1 = 0
5705 11:13:28.979034 DQM Delay:
5706 11:13:28.979132 DQM0 = 103, DQM1 = 98
5707 11:13:28.982180 DQ Delay:
5708 11:13:28.985445 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5709 11:13:28.988735 DQ4 =99, DQ5 =119, DQ6 =115, DQ7 =103
5710 11:13:28.992045 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5711 11:13:28.995397 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5712 11:13:28.995480
5713 11:13:28.995546
5714 11:13:28.995607 ==
5715 11:13:28.998703 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 11:13:29.001853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 11:13:29.001930 ==
5718 11:13:29.001995
5719 11:13:29.002055
5720 11:13:29.005457 TX Vref Scan disable
5721 11:13:29.008748 == TX Byte 0 ==
5722 11:13:29.011788 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5723 11:13:29.015050 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5724 11:13:29.018397 == TX Byte 1 ==
5725 11:13:29.021693 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5726 11:13:29.025098 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5727 11:13:29.025196 ==
5728 11:13:29.028202 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 11:13:29.032071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 11:13:29.034876 ==
5731 11:13:29.034959
5732 11:13:29.035059
5733 11:13:29.035150 TX Vref Scan disable
5734 11:13:29.038820 == TX Byte 0 ==
5735 11:13:29.042157 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5736 11:13:29.048650 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5737 11:13:29.048735 == TX Byte 1 ==
5738 11:13:29.052040 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5739 11:13:29.055110 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5740 11:13:29.058310
5741 11:13:29.058424 [DATLAT]
5742 11:13:29.058496 Freq=933, CH1 RK0
5743 11:13:29.058559
5744 11:13:29.061736 DATLAT Default: 0xd
5745 11:13:29.061818 0, 0xFFFF, sum = 0
5746 11:13:29.065420 1, 0xFFFF, sum = 0
5747 11:13:29.065505 2, 0xFFFF, sum = 0
5748 11:13:29.068676 3, 0xFFFF, sum = 0
5749 11:13:29.068809 4, 0xFFFF, sum = 0
5750 11:13:29.071859 5, 0xFFFF, sum = 0
5751 11:13:29.071944 6, 0xFFFF, sum = 0
5752 11:13:29.075576 7, 0xFFFF, sum = 0
5753 11:13:29.078714 8, 0xFFFF, sum = 0
5754 11:13:29.078824 9, 0xFFFF, sum = 0
5755 11:13:29.081716 10, 0x0, sum = 1
5756 11:13:29.081800 11, 0x0, sum = 2
5757 11:13:29.081867 12, 0x0, sum = 3
5758 11:13:29.085056 13, 0x0, sum = 4
5759 11:13:29.085143 best_step = 11
5760 11:13:29.085209
5761 11:13:29.088466 ==
5762 11:13:29.088550 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 11:13:29.100481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 11:13:29.100566 ==
5765 11:13:29.100632 RX Vref Scan: 1
5766 11:13:29.100694
5767 11:13:29.100753 RX Vref 0 -> 0, step: 1
5768 11:13:29.100809
5769 11:13:29.102063 RX Delay -45 -> 252, step: 4
5770 11:13:29.102145
5771 11:13:29.105321 Set Vref, RX VrefLevel [Byte0]: 54
5772 11:13:29.108369 [Byte1]: 48
5773 11:13:29.108453
5774 11:13:29.112060 Final RX Vref Byte 0 = 54 to rank0
5775 11:13:29.115074 Final RX Vref Byte 1 = 48 to rank0
5776 11:13:29.118748 Final RX Vref Byte 0 = 54 to rank1
5777 11:13:29.121702 Final RX Vref Byte 1 = 48 to rank1==
5778 11:13:29.125056 Dram Type= 6, Freq= 0, CH_1, rank 0
5779 11:13:29.128963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 11:13:29.129040 ==
5781 11:13:29.132218 DQS Delay:
5782 11:13:29.132296 DQS0 = 0, DQS1 = 0
5783 11:13:29.135307 DQM Delay:
5784 11:13:29.135496 DQM0 = 103, DQM1 = 99
5785 11:13:29.135590 DQ Delay:
5786 11:13:29.138372 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =102
5787 11:13:29.141567 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5788 11:13:29.145487 DQ8 =86, DQ9 =92, DQ10 =98, DQ11 =94
5789 11:13:29.151838 DQ12 =106, DQ13 =102, DQ14 =108, DQ15 =108
5790 11:13:29.151921
5791 11:13:29.151996
5792 11:13:29.158415 [DQSOSCAuto] RK0, (LSB)MR18= 0x1930, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5793 11:13:29.161615 CH1 RK0: MR19=505, MR18=1930
5794 11:13:29.168426 CH1_RK0: MR19=0x505, MR18=0x1930, DQSOSC=406, MR23=63, INC=65, DEC=43
5795 11:13:29.168510
5796 11:13:29.171464 ----->DramcWriteLeveling(PI) begin...
5797 11:13:29.171539 ==
5798 11:13:29.175188 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 11:13:29.178288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 11:13:29.178370 ==
5801 11:13:29.181764 Write leveling (Byte 0): 24 => 24
5802 11:13:29.184821 Write leveling (Byte 1): 27 => 27
5803 11:13:29.188620 DramcWriteLeveling(PI) end<-----
5804 11:13:29.188696
5805 11:13:29.188775 ==
5806 11:13:29.191811 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 11:13:29.195130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 11:13:29.195220 ==
5809 11:13:29.198459 [Gating] SW mode calibration
5810 11:13:29.205014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5811 11:13:29.211595 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5812 11:13:29.214764 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 11:13:29.221704 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 11:13:29.224846 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 11:13:29.227733 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 11:13:29.234680 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 11:13:29.237761 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5818 11:13:29.241521 0 14 24 | B1->B0 | 3030 3131 | 1 1 | (0 1) (0 1)
5819 11:13:29.248073 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
5820 11:13:29.251296 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 11:13:29.254511 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 11:13:29.257626 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 11:13:29.264826 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 11:13:29.267533 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 11:13:29.271267 0 15 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5826 11:13:29.277838 0 15 24 | B1->B0 | 3b3b 2f2f | 0 0 | (0 0) (1 1)
5827 11:13:29.281010 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5828 11:13:29.284087 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 11:13:29.291227 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 11:13:29.294485 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 11:13:29.297699 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 11:13:29.304252 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 11:13:29.307540 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 11:13:29.310755 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5835 11:13:29.317330 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 11:13:29.321068 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 11:13:29.324292 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 11:13:29.331123 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 11:13:29.334134 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 11:13:29.337206 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 11:13:29.343725 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 11:13:29.347377 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 11:13:29.350658 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 11:13:29.356973 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 11:13:29.360866 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 11:13:29.364015 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 11:13:29.370532 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:13:29.373709 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:13:29.377011 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5850 11:13:29.384305 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:13:29.387318 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5852 11:13:29.390722 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 11:13:29.394135 Total UI for P1: 0, mck2ui 16
5854 11:13:29.396980 best dqsien dly found for B0: ( 1, 2, 28)
5855 11:13:29.400484 Total UI for P1: 0, mck2ui 16
5856 11:13:29.404234 best dqsien dly found for B1: ( 1, 2, 28)
5857 11:13:29.407345 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5858 11:13:29.410509 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5859 11:13:29.410591
5860 11:13:29.413648 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5861 11:13:29.420805 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5862 11:13:29.420886 [Gating] SW calibration Done
5863 11:13:29.420975 ==
5864 11:13:29.423948 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 11:13:29.430496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 11:13:29.430579 ==
5867 11:13:29.430665 RX Vref Scan: 0
5868 11:13:29.430745
5869 11:13:29.433673 RX Vref 0 -> 0, step: 1
5870 11:13:29.433754
5871 11:13:29.437463 RX Delay -80 -> 252, step: 8
5872 11:13:29.440637 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5873 11:13:29.443833 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5874 11:13:29.447154 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5875 11:13:29.450351 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5876 11:13:29.457182 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5877 11:13:29.460355 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5878 11:13:29.463544 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5879 11:13:29.467347 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5880 11:13:29.470563 iDelay=208, Bit 8, Center 87 (-8 ~ 183) 192
5881 11:13:29.473868 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5882 11:13:29.480490 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5883 11:13:29.483698 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5884 11:13:29.486840 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5885 11:13:29.490524 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5886 11:13:29.493443 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5887 11:13:29.500116 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5888 11:13:29.500196 ==
5889 11:13:29.503839 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 11:13:29.506842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 11:13:29.506933 ==
5892 11:13:29.507000 DQS Delay:
5893 11:13:29.510357 DQS0 = 0, DQS1 = 0
5894 11:13:29.510430 DQM Delay:
5895 11:13:29.513425 DQM0 = 103, DQM1 = 99
5896 11:13:29.513500 DQ Delay:
5897 11:13:29.517288 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5898 11:13:29.520457 DQ4 =95, DQ5 =119, DQ6 =119, DQ7 =99
5899 11:13:29.523855 DQ8 =87, DQ9 =91, DQ10 =103, DQ11 =91
5900 11:13:29.527061 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5901 11:13:29.527160
5902 11:13:29.527261
5903 11:13:29.527363 ==
5904 11:13:29.530360 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 11:13:29.536981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 11:13:29.537061 ==
5907 11:13:29.537127
5908 11:13:29.537188
5909 11:13:29.537256 TX Vref Scan disable
5910 11:13:29.540107 == TX Byte 0 ==
5911 11:13:29.543281 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5912 11:13:29.550314 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5913 11:13:29.550405 == TX Byte 1 ==
5914 11:13:29.553512 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5915 11:13:29.560056 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5916 11:13:29.560139 ==
5917 11:13:29.563229 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 11:13:29.567038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 11:13:29.567121 ==
5920 11:13:29.567187
5921 11:13:29.567248
5922 11:13:29.570351 TX Vref Scan disable
5923 11:13:29.570434 == TX Byte 0 ==
5924 11:13:29.576834 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5925 11:13:29.580081 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5926 11:13:29.580168 == TX Byte 1 ==
5927 11:13:29.586722 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5928 11:13:29.589944 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5929 11:13:29.590021
5930 11:13:29.590087 [DATLAT]
5931 11:13:29.593166 Freq=933, CH1 RK1
5932 11:13:29.593240
5933 11:13:29.593309 DATLAT Default: 0xb
5934 11:13:29.596842 0, 0xFFFF, sum = 0
5935 11:13:29.596919 1, 0xFFFF, sum = 0
5936 11:13:29.600053 2, 0xFFFF, sum = 0
5937 11:13:29.600128 3, 0xFFFF, sum = 0
5938 11:13:29.603224 4, 0xFFFF, sum = 0
5939 11:13:29.603332 5, 0xFFFF, sum = 0
5940 11:13:29.606808 6, 0xFFFF, sum = 0
5941 11:13:29.609784 7, 0xFFFF, sum = 0
5942 11:13:29.609866 8, 0xFFFF, sum = 0
5943 11:13:29.613012 9, 0xFFFF, sum = 0
5944 11:13:29.613084 10, 0x0, sum = 1
5945 11:13:29.616537 11, 0x0, sum = 2
5946 11:13:29.616615 12, 0x0, sum = 3
5947 11:13:29.616688 13, 0x0, sum = 4
5948 11:13:29.620060 best_step = 11
5949 11:13:29.620155
5950 11:13:29.620249 ==
5951 11:13:29.623025 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 11:13:29.626482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 11:13:29.626558 ==
5954 11:13:29.629861 RX Vref Scan: 0
5955 11:13:29.629931
5956 11:13:29.629994 RX Vref 0 -> 0, step: 1
5957 11:13:29.633151
5958 11:13:29.633226 RX Delay -53 -> 252, step: 4
5959 11:13:29.640891 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5960 11:13:29.644137 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5961 11:13:29.647417 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5962 11:13:29.650512 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5963 11:13:29.654156 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5964 11:13:29.660182 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5965 11:13:29.664058 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5966 11:13:29.667265 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5967 11:13:29.670315 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5968 11:13:29.674162 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5969 11:13:29.676706 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5970 11:13:29.683759 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5971 11:13:29.687008 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5972 11:13:29.690326 iDelay=203, Bit 13, Center 102 (19 ~ 186) 168
5973 11:13:29.693576 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5974 11:13:29.700152 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5975 11:13:29.700227 ==
5976 11:13:29.703428 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 11:13:29.706696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 11:13:29.706768 ==
5979 11:13:29.706829 DQS Delay:
5980 11:13:29.710462 DQS0 = 0, DQS1 = 0
5981 11:13:29.710534 DQM Delay:
5982 11:13:29.713593 DQM0 = 104, DQM1 = 99
5983 11:13:29.713668 DQ Delay:
5984 11:13:29.716667 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5985 11:13:29.720360 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =102
5986 11:13:29.723414 DQ8 =90, DQ9 =88, DQ10 =98, DQ11 =94
5987 11:13:29.726985 DQ12 =108, DQ13 =102, DQ14 =106, DQ15 =108
5988 11:13:29.727068
5989 11:13:29.727173
5990 11:13:29.736688 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5991 11:13:29.739963 CH1 RK1: MR19=505, MR18=2F02
5992 11:13:29.743122 CH1_RK1: MR19=0x505, MR18=0x2F02, DQSOSC=407, MR23=63, INC=65, DEC=43
5993 11:13:29.746340 [RxdqsGatingPostProcess] freq 933
5994 11:13:29.752945 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5995 11:13:29.756621 best DQS0 dly(2T, 0.5T) = (0, 10)
5996 11:13:29.759768 best DQS1 dly(2T, 0.5T) = (0, 10)
5997 11:13:29.763428 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5998 11:13:29.766355 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5999 11:13:29.770058 best DQS0 dly(2T, 0.5T) = (0, 10)
6000 11:13:29.773201 best DQS1 dly(2T, 0.5T) = (0, 10)
6001 11:13:29.776196 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6002 11:13:29.779950 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6003 11:13:29.780033 Pre-setting of DQS Precalculation
6004 11:13:29.786636 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6005 11:13:29.793288 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6006 11:13:29.799850 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6007 11:13:29.799933
6008 11:13:29.799998
6009 11:13:29.802977 [Calibration Summary] 1866 Mbps
6010 11:13:29.805980 CH 0, Rank 0
6011 11:13:29.806084 SW Impedance : PASS
6012 11:13:29.809929 DUTY Scan : NO K
6013 11:13:29.813169 ZQ Calibration : PASS
6014 11:13:29.813252 Jitter Meter : NO K
6015 11:13:29.816132 CBT Training : PASS
6016 11:13:29.816246 Write leveling : PASS
6017 11:13:29.819860 RX DQS gating : PASS
6018 11:13:29.822938 RX DQ/DQS(RDDQC) : PASS
6019 11:13:29.823021 TX DQ/DQS : PASS
6020 11:13:29.826456 RX DATLAT : PASS
6021 11:13:29.829388 RX DQ/DQS(Engine): PASS
6022 11:13:29.829471 TX OE : NO K
6023 11:13:29.833117 All Pass.
6024 11:13:29.833200
6025 11:13:29.833265 CH 0, Rank 1
6026 11:13:29.836228 SW Impedance : PASS
6027 11:13:29.836311 DUTY Scan : NO K
6028 11:13:29.839357 ZQ Calibration : PASS
6029 11:13:29.842572 Jitter Meter : NO K
6030 11:13:29.842654 CBT Training : PASS
6031 11:13:29.846425 Write leveling : PASS
6032 11:13:29.849676 RX DQS gating : PASS
6033 11:13:29.849764 RX DQ/DQS(RDDQC) : PASS
6034 11:13:29.852990 TX DQ/DQS : PASS
6035 11:13:29.856219 RX DATLAT : PASS
6036 11:13:29.856296 RX DQ/DQS(Engine): PASS
6037 11:13:29.859462 TX OE : NO K
6038 11:13:29.859551 All Pass.
6039 11:13:29.859618
6040 11:13:29.862577 CH 1, Rank 0
6041 11:13:29.862651 SW Impedance : PASS
6042 11:13:29.866278 DUTY Scan : NO K
6043 11:13:29.869366 ZQ Calibration : PASS
6044 11:13:29.869472 Jitter Meter : NO K
6045 11:13:29.872463 CBT Training : PASS
6046 11:13:29.872540 Write leveling : PASS
6047 11:13:29.876363 RX DQS gating : PASS
6048 11:13:29.879552 RX DQ/DQS(RDDQC) : PASS
6049 11:13:29.879628 TX DQ/DQS : PASS
6050 11:13:29.882770 RX DATLAT : PASS
6051 11:13:29.885854 RX DQ/DQS(Engine): PASS
6052 11:13:29.885934 TX OE : NO K
6053 11:13:29.889551 All Pass.
6054 11:13:29.889629
6055 11:13:29.889694 CH 1, Rank 1
6056 11:13:29.892822 SW Impedance : PASS
6057 11:13:29.892894 DUTY Scan : NO K
6058 11:13:29.896067 ZQ Calibration : PASS
6059 11:13:29.899202 Jitter Meter : NO K
6060 11:13:29.899310 CBT Training : PASS
6061 11:13:29.902501 Write leveling : PASS
6062 11:13:29.905611 RX DQS gating : PASS
6063 11:13:29.905692 RX DQ/DQS(RDDQC) : PASS
6064 11:13:29.909360 TX DQ/DQS : PASS
6065 11:13:29.912501 RX DATLAT : PASS
6066 11:13:29.912589 RX DQ/DQS(Engine): PASS
6067 11:13:29.915792 TX OE : NO K
6068 11:13:29.915868 All Pass.
6069 11:13:29.915933
6070 11:13:29.918969 DramC Write-DBI off
6071 11:13:29.922107 PER_BANK_REFRESH: Hybrid Mode
6072 11:13:29.922186 TX_TRACKING: ON
6073 11:13:29.932422 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6074 11:13:29.935568 [FAST_K] Save calibration result to emmc
6075 11:13:29.938876 dramc_set_vcore_voltage set vcore to 650000
6076 11:13:29.942599 Read voltage for 400, 6
6077 11:13:29.942675 Vio18 = 0
6078 11:13:29.942739 Vcore = 650000
6079 11:13:29.945583 Vdram = 0
6080 11:13:29.945655 Vddq = 0
6081 11:13:29.945741 Vmddr = 0
6082 11:13:29.952623 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6083 11:13:29.955858 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6084 11:13:29.959147 MEM_TYPE=3, freq_sel=20
6085 11:13:29.962364 sv_algorithm_assistance_LP4_800
6086 11:13:29.965561 ============ PULL DRAM RESETB DOWN ============
6087 11:13:29.969325 ========== PULL DRAM RESETB DOWN end =========
6088 11:13:29.975553 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6089 11:13:29.978688 ===================================
6090 11:13:29.978768 LPDDR4 DRAM CONFIGURATION
6091 11:13:29.982514 ===================================
6092 11:13:29.985234 EX_ROW_EN[0] = 0x0
6093 11:13:29.989140 EX_ROW_EN[1] = 0x0
6094 11:13:29.989217 LP4Y_EN = 0x0
6095 11:13:29.992234 WORK_FSP = 0x0
6096 11:13:29.992314 WL = 0x2
6097 11:13:29.995470 RL = 0x2
6098 11:13:29.995547 BL = 0x2
6099 11:13:29.998550 RPST = 0x0
6100 11:13:29.998631 RD_PRE = 0x0
6101 11:13:30.001912 WR_PRE = 0x1
6102 11:13:30.001991 WR_PST = 0x0
6103 11:13:30.005756 DBI_WR = 0x0
6104 11:13:30.005831 DBI_RD = 0x0
6105 11:13:30.008796 OTF = 0x1
6106 11:13:30.012270 ===================================
6107 11:13:30.015437 ===================================
6108 11:13:30.015514 ANA top config
6109 11:13:30.018677 ===================================
6110 11:13:30.021946 DLL_ASYNC_EN = 0
6111 11:13:30.025679 ALL_SLAVE_EN = 1
6112 11:13:30.025756 NEW_RANK_MODE = 1
6113 11:13:30.028930 DLL_IDLE_MODE = 1
6114 11:13:30.032029 LP45_APHY_COMB_EN = 1
6115 11:13:30.035614 TX_ODT_DIS = 1
6116 11:13:30.038725 NEW_8X_MODE = 1
6117 11:13:30.041873 ===================================
6118 11:13:30.045022 ===================================
6119 11:13:30.045104 data_rate = 800
6120 11:13:30.048652 CKR = 1
6121 11:13:30.051857 DQ_P2S_RATIO = 4
6122 11:13:30.055621 ===================================
6123 11:13:30.058851 CA_P2S_RATIO = 4
6124 11:13:30.062117 DQ_CA_OPEN = 0
6125 11:13:30.065360 DQ_SEMI_OPEN = 1
6126 11:13:30.065436 CA_SEMI_OPEN = 1
6127 11:13:30.068776 CA_FULL_RATE = 0
6128 11:13:30.071876 DQ_CKDIV4_EN = 0
6129 11:13:30.075597 CA_CKDIV4_EN = 1
6130 11:13:30.078726 CA_PREDIV_EN = 0
6131 11:13:30.082010 PH8_DLY = 0
6132 11:13:30.082106 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6133 11:13:30.085087 DQ_AAMCK_DIV = 0
6134 11:13:30.088683 CA_AAMCK_DIV = 0
6135 11:13:30.092012 CA_ADMCK_DIV = 4
6136 11:13:30.095099 DQ_TRACK_CA_EN = 0
6137 11:13:30.098803 CA_PICK = 800
6138 11:13:30.098886 CA_MCKIO = 400
6139 11:13:30.102041 MCKIO_SEMI = 400
6140 11:13:30.105114 PLL_FREQ = 3016
6141 11:13:30.108769 DQ_UI_PI_RATIO = 32
6142 11:13:30.112146 CA_UI_PI_RATIO = 32
6143 11:13:30.115281 ===================================
6144 11:13:30.118497 ===================================
6145 11:13:30.121726 memory_type:LPDDR4
6146 11:13:30.121830 GP_NUM : 10
6147 11:13:30.124955 SRAM_EN : 1
6148 11:13:30.128754 MD32_EN : 0
6149 11:13:30.131516 ===================================
6150 11:13:30.131610 [ANA_INIT] >>>>>>>>>>>>>>
6151 11:13:30.135135 <<<<<< [CONFIGURE PHASE]: ANA_TX
6152 11:13:30.138184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6153 11:13:30.141412 ===================================
6154 11:13:30.145029 data_rate = 800,PCW = 0X7400
6155 11:13:30.148121 ===================================
6156 11:13:30.151838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6157 11:13:30.158516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 11:13:30.168219 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 11:13:30.171416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6160 11:13:30.174645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6161 11:13:30.181580 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6162 11:13:30.181685 [ANA_INIT] flow start
6163 11:13:30.184800 [ANA_INIT] PLL >>>>>>>>
6164 11:13:30.184901 [ANA_INIT] PLL <<<<<<<<
6165 11:13:30.187985 [ANA_INIT] MIDPI >>>>>>>>
6166 11:13:30.191753 [ANA_INIT] MIDPI <<<<<<<<
6167 11:13:30.194900 [ANA_INIT] DLL >>>>>>>>
6168 11:13:30.195002 [ANA_INIT] flow end
6169 11:13:30.197979 ============ LP4 DIFF to SE enter ============
6170 11:13:30.204976 ============ LP4 DIFF to SE exit ============
6171 11:13:30.205053 [ANA_INIT] <<<<<<<<<<<<<
6172 11:13:30.208211 [Flow] Enable top DCM control >>>>>
6173 11:13:30.211310 [Flow] Enable top DCM control <<<<<
6174 11:13:30.214971 Enable DLL master slave shuffle
6175 11:13:30.221486 ==============================================================
6176 11:13:30.221589 Gating Mode config
6177 11:13:30.228002 ==============================================================
6178 11:13:30.231125 Config description:
6179 11:13:30.241464 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6180 11:13:30.248093 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6181 11:13:30.251183 SELPH_MODE 0: By rank 1: By Phase
6182 11:13:30.257955 ==============================================================
6183 11:13:30.261527 GAT_TRACK_EN = 0
6184 11:13:30.261611 RX_GATING_MODE = 2
6185 11:13:30.264524 RX_GATING_TRACK_MODE = 2
6186 11:13:30.267740 SELPH_MODE = 1
6187 11:13:30.271688 PICG_EARLY_EN = 1
6188 11:13:30.274955 VALID_LAT_VALUE = 1
6189 11:13:30.281428 ==============================================================
6190 11:13:30.284408 Enter into Gating configuration >>>>
6191 11:13:30.287727 Exit from Gating configuration <<<<
6192 11:13:30.291580 Enter into DVFS_PRE_config >>>>>
6193 11:13:30.301549 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6194 11:13:30.304792 Exit from DVFS_PRE_config <<<<<
6195 11:13:30.308108 Enter into PICG configuration >>>>
6196 11:13:30.311298 Exit from PICG configuration <<<<
6197 11:13:30.314358 [RX_INPUT] configuration >>>>>
6198 11:13:30.318140 [RX_INPUT] configuration <<<<<
6199 11:13:30.321466 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6200 11:13:30.327618 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6201 11:13:30.334643 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 11:13:30.337952 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 11:13:30.344402 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 11:13:30.350960 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 11:13:30.354257 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6206 11:13:30.360975 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6207 11:13:30.364755 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6208 11:13:30.367687 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6209 11:13:30.370721 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6210 11:13:30.377788 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 11:13:30.381035 ===================================
6212 11:13:30.381118 LPDDR4 DRAM CONFIGURATION
6213 11:13:30.384351 ===================================
6214 11:13:30.387587 EX_ROW_EN[0] = 0x0
6215 11:13:30.387670 EX_ROW_EN[1] = 0x0
6216 11:13:30.391318 LP4Y_EN = 0x0
6217 11:13:30.394640 WORK_FSP = 0x0
6218 11:13:30.394722 WL = 0x2
6219 11:13:30.397920 RL = 0x2
6220 11:13:30.398003 BL = 0x2
6221 11:13:30.401033 RPST = 0x0
6222 11:13:30.401116 RD_PRE = 0x0
6223 11:13:30.404205 WR_PRE = 0x1
6224 11:13:30.404287 WR_PST = 0x0
6225 11:13:30.407791 DBI_WR = 0x0
6226 11:13:30.407874 DBI_RD = 0x0
6227 11:13:30.410985 OTF = 0x1
6228 11:13:30.414314 ===================================
6229 11:13:30.418150 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6230 11:13:30.421297 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6231 11:13:30.424563 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6232 11:13:30.427839 ===================================
6233 11:13:30.430929 LPDDR4 DRAM CONFIGURATION
6234 11:13:30.434636 ===================================
6235 11:13:30.437752 EX_ROW_EN[0] = 0x10
6236 11:13:30.437844 EX_ROW_EN[1] = 0x0
6237 11:13:30.441006 LP4Y_EN = 0x0
6238 11:13:30.441093 WORK_FSP = 0x0
6239 11:13:30.444666 WL = 0x2
6240 11:13:30.444764 RL = 0x2
6241 11:13:30.448001 BL = 0x2
6242 11:13:30.448083 RPST = 0x0
6243 11:13:30.451118 RD_PRE = 0x0
6244 11:13:30.451200 WR_PRE = 0x1
6245 11:13:30.454449 WR_PST = 0x0
6246 11:13:30.457496 DBI_WR = 0x0
6247 11:13:30.457579 DBI_RD = 0x0
6248 11:13:30.460732 OTF = 0x1
6249 11:13:30.464086 ===================================
6250 11:13:30.467740 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6251 11:13:30.472744 nWR fixed to 30
6252 11:13:30.476428 [ModeRegInit_LP4] CH0 RK0
6253 11:13:30.476537 [ModeRegInit_LP4] CH0 RK1
6254 11:13:30.479369 [ModeRegInit_LP4] CH1 RK0
6255 11:13:30.482658 [ModeRegInit_LP4] CH1 RK1
6256 11:13:30.482758 match AC timing 19
6257 11:13:30.489671 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6258 11:13:30.492691 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6259 11:13:30.495925 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6260 11:13:30.502953 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6261 11:13:30.506170 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6262 11:13:30.506277 ==
6263 11:13:30.509337 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 11:13:30.512810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 11:13:30.512911 ==
6266 11:13:30.519741 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 11:13:30.526234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6268 11:13:30.529532 [CA 0] Center 36 (8~64) winsize 57
6269 11:13:30.532686 [CA 1] Center 36 (8~64) winsize 57
6270 11:13:30.535955 [CA 2] Center 36 (8~64) winsize 57
6271 11:13:30.536029 [CA 3] Center 36 (8~64) winsize 57
6272 11:13:30.539572 [CA 4] Center 36 (8~64) winsize 57
6273 11:13:30.542702 [CA 5] Center 36 (8~64) winsize 57
6274 11:13:30.542788
6275 11:13:30.549416 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6276 11:13:30.549501
6277 11:13:30.552754 [CATrainingPosCal] consider 1 rank data
6278 11:13:30.552839 u2DelayCellTimex100 = 270/100 ps
6279 11:13:30.559351 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 11:13:30.562584 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 11:13:30.565814 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 11:13:30.568985 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 11:13:30.572802 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 11:13:30.575819 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 11:13:30.575907
6286 11:13:30.579022 CA PerBit enable=1, Macro0, CA PI delay=36
6287 11:13:30.579109
6288 11:13:30.582714 [CBTSetCACLKResult] CA Dly = 36
6289 11:13:30.585646 CS Dly: 1 (0~32)
6290 11:13:30.585786 ==
6291 11:13:30.588782 Dram Type= 6, Freq= 0, CH_0, rank 1
6292 11:13:30.592682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 11:13:30.592768 ==
6294 11:13:30.599032 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6295 11:13:30.602371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6296 11:13:30.605548 [CA 0] Center 36 (8~64) winsize 57
6297 11:13:30.608847 [CA 1] Center 36 (8~64) winsize 57
6298 11:13:30.612148 [CA 2] Center 36 (8~64) winsize 57
6299 11:13:30.615918 [CA 3] Center 36 (8~64) winsize 57
6300 11:13:30.619015 [CA 4] Center 36 (8~64) winsize 57
6301 11:13:30.622119 [CA 5] Center 36 (8~64) winsize 57
6302 11:13:30.622237
6303 11:13:30.625517 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6304 11:13:30.625617
6305 11:13:30.629072 [CATrainingPosCal] consider 2 rank data
6306 11:13:30.632396 u2DelayCellTimex100 = 270/100 ps
6307 11:13:30.635664 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 11:13:30.638878 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 11:13:30.646272 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 11:13:30.648682 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 11:13:30.652425 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 11:13:30.655479 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 11:13:30.655562
6314 11:13:30.658628 CA PerBit enable=1, Macro0, CA PI delay=36
6315 11:13:30.658704
6316 11:13:30.661782 [CBTSetCACLKResult] CA Dly = 36
6317 11:13:30.661886 CS Dly: 1 (0~32)
6318 11:13:30.661978
6319 11:13:30.665785 ----->DramcWriteLeveling(PI) begin...
6320 11:13:30.668505 ==
6321 11:13:30.671692 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 11:13:30.675565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 11:13:30.675639 ==
6324 11:13:30.678736 Write leveling (Byte 0): 40 => 8
6325 11:13:30.681839 Write leveling (Byte 1): 40 => 8
6326 11:13:30.684893 DramcWriteLeveling(PI) end<-----
6327 11:13:30.684993
6328 11:13:30.685087 ==
6329 11:13:30.688692 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 11:13:30.692200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 11:13:30.692279 ==
6332 11:13:30.695439 [Gating] SW mode calibration
6333 11:13:30.701855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6334 11:13:30.704970 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6335 11:13:30.712101 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 11:13:30.715346 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 11:13:30.718538 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 11:13:30.724861 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 11:13:30.728498 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 11:13:30.731539 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 11:13:30.738365 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 11:13:30.741720 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 11:13:30.745086 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 11:13:30.748233 Total UI for P1: 0, mck2ui 16
6345 11:13:30.751507 best dqsien dly found for B0: ( 0, 14, 24)
6346 11:13:30.754981 Total UI for P1: 0, mck2ui 16
6347 11:13:30.758141 best dqsien dly found for B1: ( 0, 14, 24)
6348 11:13:30.761897 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6349 11:13:30.764635 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6350 11:13:30.768470
6351 11:13:30.771878 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 11:13:30.775139 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 11:13:30.778351 [Gating] SW calibration Done
6354 11:13:30.778458 ==
6355 11:13:30.781617 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 11:13:30.785004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 11:13:30.785079 ==
6358 11:13:30.785143 RX Vref Scan: 0
6359 11:13:30.785217
6360 11:13:30.788664 RX Vref 0 -> 0, step: 1
6361 11:13:30.788807
6362 11:13:30.791657 RX Delay -410 -> 252, step: 16
6363 11:13:30.794685 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6364 11:13:30.801563 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6365 11:13:30.804802 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6366 11:13:30.808524 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6367 11:13:30.811629 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6368 11:13:30.818327 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6369 11:13:30.821506 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6370 11:13:30.824782 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6371 11:13:30.828666 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6372 11:13:30.831792 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6373 11:13:30.838469 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6374 11:13:30.841735 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6375 11:13:30.844789 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6376 11:13:30.848565 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6377 11:13:30.855084 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6378 11:13:30.858365 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6379 11:13:30.858449 ==
6380 11:13:30.861545 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 11:13:30.865086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 11:13:30.865185 ==
6383 11:13:30.868116 DQS Delay:
6384 11:13:30.868213 DQS0 = 27, DQS1 = 35
6385 11:13:30.871270 DQM Delay:
6386 11:13:30.871395 DQM0 = 12, DQM1 = 11
6387 11:13:30.871496 DQ Delay:
6388 11:13:30.874528 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6389 11:13:30.878376 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6390 11:13:30.881609 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6391 11:13:30.884924 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6392 11:13:30.885033
6393 11:13:30.885123
6394 11:13:30.885221 ==
6395 11:13:30.888256 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 11:13:30.894562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 11:13:30.894677 ==
6398 11:13:30.894769
6399 11:13:30.894865
6400 11:13:30.894959 TX Vref Scan disable
6401 11:13:30.898204 == TX Byte 0 ==
6402 11:13:30.901215 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 11:13:30.904740 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 11:13:30.907946 == TX Byte 1 ==
6405 11:13:30.911575 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 11:13:30.914775 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 11:13:30.914916 ==
6408 11:13:30.918067 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 11:13:30.924493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 11:13:30.924597 ==
6411 11:13:30.924689
6412 11:13:30.924781
6413 11:13:30.924868 TX Vref Scan disable
6414 11:13:30.927709 == TX Byte 0 ==
6415 11:13:30.931691 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 11:13:30.934344 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 11:13:30.938169 == TX Byte 1 ==
6418 11:13:30.941374 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 11:13:30.944460 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 11:13:30.944537
6421 11:13:30.948218 [DATLAT]
6422 11:13:30.948323 Freq=400, CH0 RK0
6423 11:13:30.948423
6424 11:13:30.951185 DATLAT Default: 0xf
6425 11:13:30.951285 0, 0xFFFF, sum = 0
6426 11:13:30.954499 1, 0xFFFF, sum = 0
6427 11:13:30.954614 2, 0xFFFF, sum = 0
6428 11:13:30.957686 3, 0xFFFF, sum = 0
6429 11:13:30.957792 4, 0xFFFF, sum = 0
6430 11:13:30.960894 5, 0xFFFF, sum = 0
6431 11:13:30.960973 6, 0xFFFF, sum = 0
6432 11:13:30.964896 7, 0xFFFF, sum = 0
6433 11:13:30.965003 8, 0xFFFF, sum = 0
6434 11:13:30.968065 9, 0xFFFF, sum = 0
6435 11:13:30.971200 10, 0xFFFF, sum = 0
6436 11:13:30.971315 11, 0xFFFF, sum = 0
6437 11:13:30.974438 12, 0xFFFF, sum = 0
6438 11:13:30.974553 13, 0x0, sum = 1
6439 11:13:30.977999 14, 0x0, sum = 2
6440 11:13:30.978114 15, 0x0, sum = 3
6441 11:13:30.978211 16, 0x0, sum = 4
6442 11:13:30.980803 best_step = 14
6443 11:13:30.980906
6444 11:13:30.980973 ==
6445 11:13:30.984469 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 11:13:30.987793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 11:13:30.987878 ==
6448 11:13:30.990988 RX Vref Scan: 1
6449 11:13:30.991100
6450 11:13:30.994263 RX Vref 0 -> 0, step: 1
6451 11:13:30.994367
6452 11:13:30.994460 RX Delay -311 -> 252, step: 8
6453 11:13:30.994561
6454 11:13:30.997513 Set Vref, RX VrefLevel [Byte0]: 55
6455 11:13:31.000890 [Byte1]: 47
6456 11:13:31.006013
6457 11:13:31.006121 Final RX Vref Byte 0 = 55 to rank0
6458 11:13:31.009650 Final RX Vref Byte 1 = 47 to rank0
6459 11:13:31.012806 Final RX Vref Byte 0 = 55 to rank1
6460 11:13:31.015720 Final RX Vref Byte 1 = 47 to rank1==
6461 11:13:31.019297 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 11:13:31.025724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 11:13:31.025829 ==
6464 11:13:31.025929 DQS Delay:
6465 11:13:31.029639 DQS0 = 28, DQS1 = 36
6466 11:13:31.029714 DQM Delay:
6467 11:13:31.029781 DQM0 = 10, DQM1 = 12
6468 11:13:31.032234 DQ Delay:
6469 11:13:31.036268 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6470 11:13:31.036375 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =12
6471 11:13:31.039239 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6472 11:13:31.042482 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6473 11:13:31.042560
6474 11:13:31.045701
6475 11:13:31.052459 [DQSOSCAuto] RK0, (LSB)MR18= 0xd2bf, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 383 ps
6476 11:13:31.055962 CH0 RK0: MR19=C0C, MR18=D2BF
6477 11:13:31.062579 CH0_RK0: MR19=0xC0C, MR18=0xD2BF, DQSOSC=383, MR23=63, INC=402, DEC=268
6478 11:13:31.062661 ==
6479 11:13:31.066354 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 11:13:31.069697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 11:13:31.069783 ==
6482 11:13:31.073021 [Gating] SW mode calibration
6483 11:13:31.079293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 11:13:31.086044 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6485 11:13:31.089144 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 11:13:31.092292 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 11:13:31.096230 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 11:13:31.102769 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 11:13:31.105921 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 11:13:31.109179 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 11:13:31.115925 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 11:13:31.118826 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 11:13:31.122298 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 11:13:31.126210 Total UI for P1: 0, mck2ui 16
6495 11:13:31.129356 best dqsien dly found for B0: ( 0, 14, 24)
6496 11:13:31.132715 Total UI for P1: 0, mck2ui 16
6497 11:13:31.135935 best dqsien dly found for B1: ( 0, 14, 24)
6498 11:13:31.138958 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6499 11:13:31.142268 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6500 11:13:31.145548
6501 11:13:31.148773 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 11:13:31.152165 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 11:13:31.156044 [Gating] SW calibration Done
6504 11:13:31.156130 ==
6505 11:13:31.159112 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 11:13:31.162345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 11:13:31.162443 ==
6508 11:13:31.162540 RX Vref Scan: 0
6509 11:13:31.162603
6510 11:13:31.165938 RX Vref 0 -> 0, step: 1
6511 11:13:31.166021
6512 11:13:31.169007 RX Delay -410 -> 252, step: 16
6513 11:13:31.172409 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6514 11:13:31.178999 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6515 11:13:31.182153 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6516 11:13:31.185214 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6517 11:13:31.188540 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6518 11:13:31.195577 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6519 11:13:31.198839 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6520 11:13:31.202091 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6521 11:13:31.205400 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6522 11:13:31.212446 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6523 11:13:31.215691 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6524 11:13:31.218875 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6525 11:13:31.222050 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6526 11:13:31.228683 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6527 11:13:31.231702 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6528 11:13:31.235165 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6529 11:13:31.235266 ==
6530 11:13:31.238698 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 11:13:31.241705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 11:13:31.245172 ==
6533 11:13:31.245300 DQS Delay:
6534 11:13:31.245395 DQS0 = 19, DQS1 = 35
6535 11:13:31.248488 DQM Delay:
6536 11:13:31.248603 DQM0 = 5, DQM1 = 12
6537 11:13:31.251626 DQ Delay:
6538 11:13:31.251705 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6539 11:13:31.254985 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6540 11:13:31.258198 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6541 11:13:31.261540 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6542 11:13:31.261642
6543 11:13:31.261736
6544 11:13:31.261825 ==
6545 11:13:31.264768 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 11:13:31.271667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 11:13:31.271787 ==
6548 11:13:31.271851
6549 11:13:31.271912
6550 11:13:31.274955 TX Vref Scan disable
6551 11:13:31.275057 == TX Byte 0 ==
6552 11:13:31.278075 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6553 11:13:31.281718 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6554 11:13:31.284825 == TX Byte 1 ==
6555 11:13:31.288490 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6556 11:13:31.291781 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6557 11:13:31.294849 ==
6558 11:13:31.294998 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 11:13:31.301233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 11:13:31.301346 ==
6561 11:13:31.301454
6562 11:13:31.301585
6563 11:13:31.305059 TX Vref Scan disable
6564 11:13:31.305166 == TX Byte 0 ==
6565 11:13:31.308282 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6566 11:13:31.314902 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6567 11:13:31.315016 == TX Byte 1 ==
6568 11:13:31.318239 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6569 11:13:31.321318 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6570 11:13:31.324550
6571 11:13:31.324633 [DATLAT]
6572 11:13:31.324698 Freq=400, CH0 RK1
6573 11:13:31.324801
6574 11:13:31.328412 DATLAT Default: 0xe
6575 11:13:31.328511 0, 0xFFFF, sum = 0
6576 11:13:31.331467 1, 0xFFFF, sum = 0
6577 11:13:31.331600 2, 0xFFFF, sum = 0
6578 11:13:31.334672 3, 0xFFFF, sum = 0
6579 11:13:31.334826 4, 0xFFFF, sum = 0
6580 11:13:31.338402 5, 0xFFFF, sum = 0
6581 11:13:31.341596 6, 0xFFFF, sum = 0
6582 11:13:31.341682 7, 0xFFFF, sum = 0
6583 11:13:31.344337 8, 0xFFFF, sum = 0
6584 11:13:31.344422 9, 0xFFFF, sum = 0
6585 11:13:31.347825 10, 0xFFFF, sum = 0
6586 11:13:31.347940 11, 0xFFFF, sum = 0
6587 11:13:31.351604 12, 0xFFFF, sum = 0
6588 11:13:31.351690 13, 0x0, sum = 1
6589 11:13:31.354739 14, 0x0, sum = 2
6590 11:13:31.354848 15, 0x0, sum = 3
6591 11:13:31.357954 16, 0x0, sum = 4
6592 11:13:31.358057 best_step = 14
6593 11:13:31.358157
6594 11:13:31.358247 ==
6595 11:13:31.361229 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 11:13:31.364454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 11:13:31.364558 ==
6598 11:13:31.367790 RX Vref Scan: 0
6599 11:13:31.367890
6600 11:13:31.370867 RX Vref 0 -> 0, step: 1
6601 11:13:31.370967
6602 11:13:31.374637 RX Delay -311 -> 252, step: 8
6603 11:13:31.377797 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6604 11:13:31.384752 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6605 11:13:31.387655 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6606 11:13:31.390887 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6607 11:13:31.394108 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6608 11:13:31.401046 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6609 11:13:31.404283 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6610 11:13:31.407490 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6611 11:13:31.410539 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6612 11:13:31.417784 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6613 11:13:31.421148 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6614 11:13:31.424300 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6615 11:13:31.427675 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6616 11:13:31.433857 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6617 11:13:31.437292 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6618 11:13:31.441121 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6619 11:13:31.441197 ==
6620 11:13:31.444180 Dram Type= 6, Freq= 0, CH_0, rank 1
6621 11:13:31.450827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 11:13:31.450918 ==
6623 11:13:31.450987 DQS Delay:
6624 11:13:31.454224 DQS0 = 24, DQS1 = 36
6625 11:13:31.454311 DQM Delay:
6626 11:13:31.454378 DQM0 = 9, DQM1 = 13
6627 11:13:31.457313 DQ Delay:
6628 11:13:31.461000 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6629 11:13:31.461089 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6630 11:13:31.464125 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6631 11:13:31.467319 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6632 11:13:31.467411
6633 11:13:31.467479
6634 11:13:31.476913 [DQSOSCAuto] RK1, (LSB)MR18= 0xc161, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 385 ps
6635 11:13:31.480637 CH0 RK1: MR19=C0C, MR18=C161
6636 11:13:31.487093 CH0_RK1: MR19=0xC0C, MR18=0xC161, DQSOSC=385, MR23=63, INC=398, DEC=265
6637 11:13:31.490373 [RxdqsGatingPostProcess] freq 400
6638 11:13:31.493595 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6639 11:13:31.497160 best DQS0 dly(2T, 0.5T) = (0, 10)
6640 11:13:31.500438 best DQS1 dly(2T, 0.5T) = (0, 10)
6641 11:13:31.503317 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6642 11:13:31.507180 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6643 11:13:31.509853 best DQS0 dly(2T, 0.5T) = (0, 10)
6644 11:13:31.513681 best DQS1 dly(2T, 0.5T) = (0, 10)
6645 11:13:31.516773 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6646 11:13:31.520002 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6647 11:13:31.523240 Pre-setting of DQS Precalculation
6648 11:13:31.527007 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6649 11:13:31.527093 ==
6650 11:13:31.530279 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 11:13:31.537171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 11:13:31.537264 ==
6653 11:13:31.540435 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 11:13:31.546964 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6655 11:13:31.550224 [CA 0] Center 36 (8~64) winsize 57
6656 11:13:31.553662 [CA 1] Center 36 (8~64) winsize 57
6657 11:13:31.556694 [CA 2] Center 36 (8~64) winsize 57
6658 11:13:31.559768 [CA 3] Center 36 (8~64) winsize 57
6659 11:13:31.563742 [CA 4] Center 36 (8~64) winsize 57
6660 11:13:31.566934 [CA 5] Center 36 (8~64) winsize 57
6661 11:13:31.567017
6662 11:13:31.569935 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6663 11:13:31.570008
6664 11:13:31.573199 [CATrainingPosCal] consider 1 rank data
6665 11:13:31.576377 u2DelayCellTimex100 = 270/100 ps
6666 11:13:31.580299 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 11:13:31.583394 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 11:13:31.586579 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 11:13:31.589827 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 11:13:31.592990 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 11:13:31.596292 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 11:13:31.596366
6673 11:13:31.603222 CA PerBit enable=1, Macro0, CA PI delay=36
6674 11:13:31.603300
6675 11:13:31.606157 [CBTSetCACLKResult] CA Dly = 36
6676 11:13:31.606237 CS Dly: 1 (0~32)
6677 11:13:31.606302 ==
6678 11:13:31.609843 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 11:13:31.613104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 11:13:31.613173 ==
6681 11:13:31.619674 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6682 11:13:31.626511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6683 11:13:31.629202 [CA 0] Center 36 (8~64) winsize 57
6684 11:13:31.632595 [CA 1] Center 36 (8~64) winsize 57
6685 11:13:31.636392 [CA 2] Center 36 (8~64) winsize 57
6686 11:13:31.639599 [CA 3] Center 36 (8~64) winsize 57
6687 11:13:31.642949 [CA 4] Center 36 (8~64) winsize 57
6688 11:13:31.643034 [CA 5] Center 36 (8~64) winsize 57
6689 11:13:31.643100
6690 11:13:31.649357 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6691 11:13:31.649477
6692 11:13:31.652628 [CATrainingPosCal] consider 2 rank data
6693 11:13:31.655885 u2DelayCellTimex100 = 270/100 ps
6694 11:13:31.659495 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 11:13:31.662460 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 11:13:31.666397 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 11:13:31.669379 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 11:13:31.672432 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 11:13:31.675756 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 11:13:31.675840
6701 11:13:31.678962 CA PerBit enable=1, Macro0, CA PI delay=36
6702 11:13:31.679045
6703 11:13:31.682981 [CBTSetCACLKResult] CA Dly = 36
6704 11:13:31.686166 CS Dly: 1 (0~32)
6705 11:13:31.686250
6706 11:13:31.689556 ----->DramcWriteLeveling(PI) begin...
6707 11:13:31.689669 ==
6708 11:13:31.692721 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 11:13:31.695902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 11:13:31.695986 ==
6711 11:13:31.699188 Write leveling (Byte 0): 40 => 8
6712 11:13:31.702327 Write leveling (Byte 1): 40 => 8
6713 11:13:31.705715 DramcWriteLeveling(PI) end<-----
6714 11:13:31.705818
6715 11:13:31.705911 ==
6716 11:13:31.709393 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 11:13:31.712430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 11:13:31.712535 ==
6719 11:13:31.716069 [Gating] SW mode calibration
6720 11:13:31.722583 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6721 11:13:31.729015 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6722 11:13:31.732275 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 11:13:31.736023 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 11:13:31.742613 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 11:13:31.745798 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 11:13:31.749118 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 11:13:31.755532 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 11:13:31.758796 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 11:13:31.762092 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 11:13:31.769040 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 11:13:31.771988 Total UI for P1: 0, mck2ui 16
6732 11:13:31.775600 best dqsien dly found for B0: ( 0, 14, 24)
6733 11:13:31.775683 Total UI for P1: 0, mck2ui 16
6734 11:13:31.782332 best dqsien dly found for B1: ( 0, 14, 24)
6735 11:13:31.785487 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6736 11:13:31.788745 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6737 11:13:31.788829
6738 11:13:31.792048 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 11:13:31.795199 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 11:13:31.798545 [Gating] SW calibration Done
6741 11:13:31.798643 ==
6742 11:13:31.802505 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 11:13:31.805621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 11:13:31.805735 ==
6745 11:13:31.808911 RX Vref Scan: 0
6746 11:13:31.808987
6747 11:13:31.809052 RX Vref 0 -> 0, step: 1
6748 11:13:31.812190
6749 11:13:31.812266 RX Delay -410 -> 252, step: 16
6750 11:13:31.818498 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6751 11:13:31.821568 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6752 11:13:31.825069 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6753 11:13:31.828666 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6754 11:13:31.835272 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6755 11:13:31.838403 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6756 11:13:31.841489 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6757 11:13:31.845378 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6758 11:13:31.851709 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6759 11:13:31.855020 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6760 11:13:31.858346 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6761 11:13:31.864775 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6762 11:13:31.868126 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6763 11:13:31.871283 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6764 11:13:31.874504 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6765 11:13:31.881674 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6766 11:13:31.881756 ==
6767 11:13:31.884662 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 11:13:31.888186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 11:13:31.888265 ==
6770 11:13:31.888331 DQS Delay:
6771 11:13:31.891122 DQS0 = 27, DQS1 = 35
6772 11:13:31.891229 DQM Delay:
6773 11:13:31.894324 DQM0 = 10, DQM1 = 14
6774 11:13:31.894398 DQ Delay:
6775 11:13:31.898103 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6776 11:13:31.901368 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6777 11:13:31.904538 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6778 11:13:31.907863 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =32
6779 11:13:31.907944
6780 11:13:31.908018
6781 11:13:31.908080 ==
6782 11:13:31.911471 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 11:13:31.914616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 11:13:31.914705 ==
6785 11:13:31.914778
6786 11:13:31.914841
6787 11:13:31.917994 TX Vref Scan disable
6788 11:13:31.918092 == TX Byte 0 ==
6789 11:13:31.924168 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 11:13:31.927927 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 11:13:31.928003 == TX Byte 1 ==
6792 11:13:31.934189 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 11:13:31.937784 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 11:13:31.937865 ==
6795 11:13:31.941040 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 11:13:31.944288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 11:13:31.944391 ==
6798 11:13:31.944489
6799 11:13:31.944577
6800 11:13:31.947449 TX Vref Scan disable
6801 11:13:31.947552 == TX Byte 0 ==
6802 11:13:31.954377 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 11:13:31.957663 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 11:13:31.957747 == TX Byte 1 ==
6805 11:13:31.964221 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 11:13:31.967469 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 11:13:31.967580
6808 11:13:31.967647 [DATLAT]
6809 11:13:31.970939 Freq=400, CH1 RK0
6810 11:13:31.971041
6811 11:13:31.971129 DATLAT Default: 0xf
6812 11:13:31.974190 0, 0xFFFF, sum = 0
6813 11:13:31.974295 1, 0xFFFF, sum = 0
6814 11:13:31.977520 2, 0xFFFF, sum = 0
6815 11:13:31.977644 3, 0xFFFF, sum = 0
6816 11:13:31.980705 4, 0xFFFF, sum = 0
6817 11:13:31.980811 5, 0xFFFF, sum = 0
6818 11:13:31.984448 6, 0xFFFF, sum = 0
6819 11:13:31.984532 7, 0xFFFF, sum = 0
6820 11:13:31.987491 8, 0xFFFF, sum = 0
6821 11:13:31.991170 9, 0xFFFF, sum = 0
6822 11:13:31.991296 10, 0xFFFF, sum = 0
6823 11:13:31.994043 11, 0xFFFF, sum = 0
6824 11:13:31.994126 12, 0xFFFF, sum = 0
6825 11:13:31.997466 13, 0x0, sum = 1
6826 11:13:31.997551 14, 0x0, sum = 2
6827 11:13:32.000721 15, 0x0, sum = 3
6828 11:13:32.000832 16, 0x0, sum = 4
6829 11:13:32.000931 best_step = 14
6830 11:13:32.004405
6831 11:13:32.004488 ==
6832 11:13:32.007619 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 11:13:32.010838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 11:13:32.010936 ==
6835 11:13:32.011003 RX Vref Scan: 1
6836 11:13:32.011077
6837 11:13:32.014223 RX Vref 0 -> 0, step: 1
6838 11:13:32.014305
6839 11:13:32.017460 RX Delay -311 -> 252, step: 8
6840 11:13:32.017542
6841 11:13:32.020706 Set Vref, RX VrefLevel [Byte0]: 54
6842 11:13:32.024044 [Byte1]: 48
6843 11:13:32.027967
6844 11:13:32.028082 Final RX Vref Byte 0 = 54 to rank0
6845 11:13:32.030807 Final RX Vref Byte 1 = 48 to rank0
6846 11:13:32.033988 Final RX Vref Byte 0 = 54 to rank1
6847 11:13:32.037749 Final RX Vref Byte 1 = 48 to rank1==
6848 11:13:32.040921 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 11:13:32.047960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 11:13:32.048066 ==
6851 11:13:32.048169 DQS Delay:
6852 11:13:32.051087 DQS0 = 32, DQS1 = 32
6853 11:13:32.051240 DQM Delay:
6854 11:13:32.051310 DQM0 = 13, DQM1 = 11
6855 11:13:32.054223 DQ Delay:
6856 11:13:32.057311 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6857 11:13:32.061035 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6858 11:13:32.061115 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6859 11:13:32.064241 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6860 11:13:32.067427
6861 11:13:32.067502
6862 11:13:32.074054 [DQSOSCAuto] RK0, (LSB)MR18= 0x92ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6863 11:13:32.077310 CH1 RK0: MR19=C0C, MR18=92CA
6864 11:13:32.084030 CH1_RK0: MR19=0xC0C, MR18=0x92CA, DQSOSC=384, MR23=63, INC=400, DEC=267
6865 11:13:32.084106 ==
6866 11:13:32.087202 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 11:13:32.090919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 11:13:32.091001 ==
6869 11:13:32.093932 [Gating] SW mode calibration
6870 11:13:32.100671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6871 11:13:32.107281 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6872 11:13:32.110443 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 11:13:32.114147 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 11:13:32.120530 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 11:13:32.123779 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 11:13:32.127038 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 11:13:32.133584 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 11:13:32.137162 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 11:13:32.140458 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 11:13:32.146897 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 11:13:32.146980 Total UI for P1: 0, mck2ui 16
6882 11:13:32.150443 best dqsien dly found for B0: ( 0, 14, 24)
6883 11:13:32.153709 Total UI for P1: 0, mck2ui 16
6884 11:13:32.156902 best dqsien dly found for B1: ( 0, 14, 24)
6885 11:13:32.163858 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6886 11:13:32.166611 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6887 11:13:32.166703
6888 11:13:32.170398 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 11:13:32.173871 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 11:13:32.177230 [Gating] SW calibration Done
6891 11:13:32.177307 ==
6892 11:13:32.180467 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 11:13:32.183809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 11:13:32.183885 ==
6895 11:13:32.187056 RX Vref Scan: 0
6896 11:13:32.187137
6897 11:13:32.187202 RX Vref 0 -> 0, step: 1
6898 11:13:32.187261
6899 11:13:32.190251 RX Delay -410 -> 252, step: 16
6900 11:13:32.193589 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6901 11:13:32.200474 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6902 11:13:32.203389 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6903 11:13:32.207104 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6904 11:13:32.210216 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6905 11:13:32.217125 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6906 11:13:32.220392 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6907 11:13:32.223579 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6908 11:13:32.226885 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6909 11:13:32.233535 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6910 11:13:32.237319 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6911 11:13:32.240456 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6912 11:13:32.243644 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6913 11:13:32.250216 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6914 11:13:32.253287 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6915 11:13:32.257132 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6916 11:13:32.257216 ==
6917 11:13:32.259862 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 11:13:32.266828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 11:13:32.266924 ==
6920 11:13:32.266992 DQS Delay:
6921 11:13:32.269814 DQS0 = 35, DQS1 = 35
6922 11:13:32.269885 DQM Delay:
6923 11:13:32.269946 DQM0 = 18, DQM1 = 14
6924 11:13:32.273474 DQ Delay:
6925 11:13:32.276682 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6926 11:13:32.279967 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6927 11:13:32.280051 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6928 11:13:32.286599 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6929 11:13:32.286692
6930 11:13:32.286760
6931 11:13:32.286823 ==
6932 11:13:32.289836 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 11:13:32.293136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 11:13:32.293219 ==
6935 11:13:32.293285
6936 11:13:32.293345
6937 11:13:32.296390 TX Vref Scan disable
6938 11:13:32.296473 == TX Byte 0 ==
6939 11:13:32.300132 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6940 11:13:32.306565 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6941 11:13:32.306648 == TX Byte 1 ==
6942 11:13:32.309984 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6943 11:13:32.316841 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6944 11:13:32.316925 ==
6945 11:13:32.319744 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 11:13:32.322884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 11:13:32.323011 ==
6948 11:13:32.323077
6949 11:13:32.323137
6950 11:13:32.326506 TX Vref Scan disable
6951 11:13:32.326592 == TX Byte 0 ==
6952 11:13:32.329649 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6953 11:13:32.336251 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6954 11:13:32.336335 == TX Byte 1 ==
6955 11:13:32.339441 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6956 11:13:32.346310 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6957 11:13:32.346393
6958 11:13:32.346459 [DATLAT]
6959 11:13:32.349649 Freq=400, CH1 RK1
6960 11:13:32.349732
6961 11:13:32.349798 DATLAT Default: 0xe
6962 11:13:32.352980 0, 0xFFFF, sum = 0
6963 11:13:32.353068 1, 0xFFFF, sum = 0
6964 11:13:32.356329 2, 0xFFFF, sum = 0
6965 11:13:32.356413 3, 0xFFFF, sum = 0
6966 11:13:32.359521 4, 0xFFFF, sum = 0
6967 11:13:32.359606 5, 0xFFFF, sum = 0
6968 11:13:32.363398 6, 0xFFFF, sum = 0
6969 11:13:32.363482 7, 0xFFFF, sum = 0
6970 11:13:32.366629 8, 0xFFFF, sum = 0
6971 11:13:32.366714 9, 0xFFFF, sum = 0
6972 11:13:32.369754 10, 0xFFFF, sum = 0
6973 11:13:32.369839 11, 0xFFFF, sum = 0
6974 11:13:32.372891 12, 0xFFFF, sum = 0
6975 11:13:32.372975 13, 0x0, sum = 1
6976 11:13:32.376508 14, 0x0, sum = 2
6977 11:13:32.376593 15, 0x0, sum = 3
6978 11:13:32.379416 16, 0x0, sum = 4
6979 11:13:32.379501 best_step = 14
6980 11:13:32.379566
6981 11:13:32.379627 ==
6982 11:13:32.383068 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 11:13:32.389621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 11:13:32.389705 ==
6985 11:13:32.389771 RX Vref Scan: 0
6986 11:13:32.389833
6987 11:13:32.392806 RX Vref 0 -> 0, step: 1
6988 11:13:32.392888
6989 11:13:32.396428 RX Delay -311 -> 252, step: 8
6990 11:13:32.402886 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6991 11:13:32.406218 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6992 11:13:32.409478 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6993 11:13:32.412629 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6994 11:13:32.419521 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6995 11:13:32.423210 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6996 11:13:32.426282 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6997 11:13:32.429484 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6998 11:13:32.432506 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6999 11:13:32.439491 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7000 11:13:32.442770 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7001 11:13:32.445966 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7002 11:13:32.452245 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7003 11:13:32.455662 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7004 11:13:32.458967 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7005 11:13:32.462880 iDelay=217, Bit 15, Center -8 (-231 ~ 216) 448
7006 11:13:32.462979 ==
7007 11:13:32.466042 Dram Type= 6, Freq= 0, CH_1, rank 1
7008 11:13:32.472358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7009 11:13:32.472443 ==
7010 11:13:32.472509 DQS Delay:
7011 11:13:32.475709 DQS0 = 28, DQS1 = 32
7012 11:13:32.475791 DQM Delay:
7013 11:13:32.475876 DQM0 = 10, DQM1 = 11
7014 11:13:32.479594 DQ Delay:
7015 11:13:32.482729 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7016 11:13:32.485737 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7017 11:13:32.485820 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7018 11:13:32.489364 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7019 11:13:32.492296
7020 11:13:32.492383
7021 11:13:32.499160 [DQSOSCAuto] RK1, (LSB)MR18= 0xca5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
7022 11:13:32.502614 CH1 RK1: MR19=C0C, MR18=CA5B
7023 11:13:32.509296 CH1_RK1: MR19=0xC0C, MR18=0xCA5B, DQSOSC=384, MR23=63, INC=400, DEC=267
7024 11:13:32.512575 [RxdqsGatingPostProcess] freq 400
7025 11:13:32.515715 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7026 11:13:32.519134 best DQS0 dly(2T, 0.5T) = (0, 10)
7027 11:13:32.522155 best DQS1 dly(2T, 0.5T) = (0, 10)
7028 11:13:32.525768 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7029 11:13:32.528683 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7030 11:13:32.532578 best DQS0 dly(2T, 0.5T) = (0, 10)
7031 11:13:32.535573 best DQS1 dly(2T, 0.5T) = (0, 10)
7032 11:13:32.539279 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7033 11:13:32.542312 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7034 11:13:32.546093 Pre-setting of DQS Precalculation
7035 11:13:32.549400 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7036 11:13:32.555658 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7037 11:13:32.566074 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7038 11:13:32.566162
7039 11:13:32.566230
7040 11:13:32.566299 [Calibration Summary] 800 Mbps
7041 11:13:32.569425 CH 0, Rank 0
7042 11:13:32.569508 SW Impedance : PASS
7043 11:13:32.572656 DUTY Scan : NO K
7044 11:13:32.575766 ZQ Calibration : PASS
7045 11:13:32.575853 Jitter Meter : NO K
7046 11:13:32.578963 CBT Training : PASS
7047 11:13:32.582125 Write leveling : PASS
7048 11:13:32.582223 RX DQS gating : PASS
7049 11:13:32.585548 RX DQ/DQS(RDDQC) : PASS
7050 11:13:32.589307 TX DQ/DQS : PASS
7051 11:13:32.589384 RX DATLAT : PASS
7052 11:13:32.592355 RX DQ/DQS(Engine): PASS
7053 11:13:32.595493 TX OE : NO K
7054 11:13:32.595594 All Pass.
7055 11:13:32.595685
7056 11:13:32.595773 CH 0, Rank 1
7057 11:13:32.599196 SW Impedance : PASS
7058 11:13:32.602354 DUTY Scan : NO K
7059 11:13:32.602426 ZQ Calibration : PASS
7060 11:13:32.605322 Jitter Meter : NO K
7061 11:13:32.609042 CBT Training : PASS
7062 11:13:32.609140 Write leveling : NO K
7063 11:13:32.612435 RX DQS gating : PASS
7064 11:13:32.615607 RX DQ/DQS(RDDQC) : PASS
7065 11:13:32.615690 TX DQ/DQS : PASS
7066 11:13:32.618777 RX DATLAT : PASS
7067 11:13:32.618844 RX DQ/DQS(Engine): PASS
7068 11:13:32.622094 TX OE : NO K
7069 11:13:32.622168 All Pass.
7070 11:13:32.622230
7071 11:13:32.625907 CH 1, Rank 0
7072 11:13:32.626006 SW Impedance : PASS
7073 11:13:32.629054 DUTY Scan : NO K
7074 11:13:32.632087 ZQ Calibration : PASS
7075 11:13:32.632210 Jitter Meter : NO K
7076 11:13:32.635628 CBT Training : PASS
7077 11:13:32.638661 Write leveling : PASS
7078 11:13:32.638808 RX DQS gating : PASS
7079 11:13:32.642240 RX DQ/DQS(RDDQC) : PASS
7080 11:13:32.645735 TX DQ/DQS : PASS
7081 11:13:32.645838 RX DATLAT : PASS
7082 11:13:32.648913 RX DQ/DQS(Engine): PASS
7083 11:13:32.648994 TX OE : NO K
7084 11:13:32.651994 All Pass.
7085 11:13:32.652076
7086 11:13:32.652169 CH 1, Rank 1
7087 11:13:32.655259 SW Impedance : PASS
7088 11:13:32.659169 DUTY Scan : NO K
7089 11:13:32.659273 ZQ Calibration : PASS
7090 11:13:32.662386 Jitter Meter : NO K
7091 11:13:32.662459 CBT Training : PASS
7092 11:13:32.665499 Write leveling : NO K
7093 11:13:32.668803 RX DQS gating : PASS
7094 11:13:32.668875 RX DQ/DQS(RDDQC) : PASS
7095 11:13:32.672090 TX DQ/DQS : PASS
7096 11:13:32.675229 RX DATLAT : PASS
7097 11:13:32.675358 RX DQ/DQS(Engine): PASS
7098 11:13:32.678983 TX OE : NO K
7099 11:13:32.679087 All Pass.
7100 11:13:32.679179
7101 11:13:32.681963 DramC Write-DBI off
7102 11:13:32.685611 PER_BANK_REFRESH: Hybrid Mode
7103 11:13:32.685690 TX_TRACKING: ON
7104 11:13:32.695532 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7105 11:13:32.698744 [FAST_K] Save calibration result to emmc
7106 11:13:32.701787 dramc_set_vcore_voltage set vcore to 725000
7107 11:13:32.705583 Read voltage for 1600, 0
7108 11:13:32.705660 Vio18 = 0
7109 11:13:32.705724 Vcore = 725000
7110 11:13:32.708580 Vdram = 0
7111 11:13:32.708652 Vddq = 0
7112 11:13:32.708712 Vmddr = 0
7113 11:13:32.715584 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7114 11:13:32.718623 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7115 11:13:32.722396 MEM_TYPE=3, freq_sel=13
7116 11:13:32.725623 sv_algorithm_assistance_LP4_3733
7117 11:13:32.728797 ============ PULL DRAM RESETB DOWN ============
7118 11:13:32.732038 ========== PULL DRAM RESETB DOWN end =========
7119 11:13:32.738443 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7120 11:13:32.742166 ===================================
7121 11:13:32.745390 LPDDR4 DRAM CONFIGURATION
7122 11:13:32.748311 ===================================
7123 11:13:32.748409 EX_ROW_EN[0] = 0x0
7124 11:13:32.751763 EX_ROW_EN[1] = 0x0
7125 11:13:32.751840 LP4Y_EN = 0x0
7126 11:13:32.755405 WORK_FSP = 0x1
7127 11:13:32.755487 WL = 0x5
7128 11:13:32.758579 RL = 0x5
7129 11:13:32.758657 BL = 0x2
7130 11:13:32.761899 RPST = 0x0
7131 11:13:32.761975 RD_PRE = 0x0
7132 11:13:32.765193 WR_PRE = 0x1
7133 11:13:32.765264 WR_PST = 0x1
7134 11:13:32.768266 DBI_WR = 0x0
7135 11:13:32.768338 DBI_RD = 0x0
7136 11:13:32.772178 OTF = 0x1
7137 11:13:32.775474 ===================================
7138 11:13:32.778770 ===================================
7139 11:13:32.778869 ANA top config
7140 11:13:32.781959 ===================================
7141 11:13:32.785205 DLL_ASYNC_EN = 0
7142 11:13:32.788997 ALL_SLAVE_EN = 0
7143 11:13:32.792015 NEW_RANK_MODE = 1
7144 11:13:32.792099 DLL_IDLE_MODE = 1
7145 11:13:32.795171 LP45_APHY_COMB_EN = 1
7146 11:13:32.798443 TX_ODT_DIS = 0
7147 11:13:32.801745 NEW_8X_MODE = 1
7148 11:13:32.804823 ===================================
7149 11:13:32.808543 ===================================
7150 11:13:32.811740 data_rate = 3200
7151 11:13:32.811815 CKR = 1
7152 11:13:32.815440 DQ_P2S_RATIO = 8
7153 11:13:32.818537 ===================================
7154 11:13:32.821651 CA_P2S_RATIO = 8
7155 11:13:32.825527 DQ_CA_OPEN = 0
7156 11:13:32.828099 DQ_SEMI_OPEN = 0
7157 11:13:32.831514 CA_SEMI_OPEN = 0
7158 11:13:32.831617 CA_FULL_RATE = 0
7159 11:13:32.835502 DQ_CKDIV4_EN = 0
7160 11:13:32.838653 CA_CKDIV4_EN = 0
7161 11:13:32.841316 CA_PREDIV_EN = 0
7162 11:13:32.845075 PH8_DLY = 12
7163 11:13:32.848168 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7164 11:13:32.848274 DQ_AAMCK_DIV = 4
7165 11:13:32.851747 CA_AAMCK_DIV = 4
7166 11:13:32.854736 CA_ADMCK_DIV = 4
7167 11:13:32.858437 DQ_TRACK_CA_EN = 0
7168 11:13:32.861568 CA_PICK = 1600
7169 11:13:32.864765 CA_MCKIO = 1600
7170 11:13:32.868386 MCKIO_SEMI = 0
7171 11:13:32.868462 PLL_FREQ = 3068
7172 11:13:32.872107 DQ_UI_PI_RATIO = 32
7173 11:13:32.875275 CA_UI_PI_RATIO = 0
7174 11:13:32.878552 ===================================
7175 11:13:32.881780 ===================================
7176 11:13:32.884972 memory_type:LPDDR4
7177 11:13:32.885045 GP_NUM : 10
7178 11:13:32.888751 SRAM_EN : 1
7179 11:13:32.891553 MD32_EN : 0
7180 11:13:32.895244 ===================================
7181 11:13:32.895317 [ANA_INIT] >>>>>>>>>>>>>>
7182 11:13:32.898362 <<<<<< [CONFIGURE PHASE]: ANA_TX
7183 11:13:32.901533 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7184 11:13:32.905275 ===================================
7185 11:13:32.908493 data_rate = 3200,PCW = 0X7600
7186 11:13:32.911692 ===================================
7187 11:13:32.914778 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7188 11:13:32.921993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 11:13:32.925032 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 11:13:32.931555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7191 11:13:32.934678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7192 11:13:32.937934 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7193 11:13:32.938044 [ANA_INIT] flow start
7194 11:13:32.941227 [ANA_INIT] PLL >>>>>>>>
7195 11:13:32.944511 [ANA_INIT] PLL <<<<<<<<
7196 11:13:32.948445 [ANA_INIT] MIDPI >>>>>>>>
7197 11:13:32.948621 [ANA_INIT] MIDPI <<<<<<<<
7198 11:13:32.951562 [ANA_INIT] DLL >>>>>>>>
7199 11:13:32.954536 [ANA_INIT] DLL <<<<<<<<
7200 11:13:32.954655 [ANA_INIT] flow end
7201 11:13:32.957728 ============ LP4 DIFF to SE enter ============
7202 11:13:32.964465 ============ LP4 DIFF to SE exit ============
7203 11:13:32.964610 [ANA_INIT] <<<<<<<<<<<<<
7204 11:13:32.968227 [Flow] Enable top DCM control >>>>>
7205 11:13:32.971414 [Flow] Enable top DCM control <<<<<
7206 11:13:32.975009 Enable DLL master slave shuffle
7207 11:13:32.981489 ==============================================================
7208 11:13:32.981615 Gating Mode config
7209 11:13:32.987839 ==============================================================
7210 11:13:32.991598 Config description:
7211 11:13:33.001446 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7212 11:13:33.008389 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7213 11:13:33.011660 SELPH_MODE 0: By rank 1: By Phase
7214 11:13:33.017792 ==============================================================
7215 11:13:33.021118 GAT_TRACK_EN = 1
7216 11:13:33.021226 RX_GATING_MODE = 2
7217 11:13:33.024918 RX_GATING_TRACK_MODE = 2
7218 11:13:33.028153 SELPH_MODE = 1
7219 11:13:33.031381 PICG_EARLY_EN = 1
7220 11:13:33.034537 VALID_LAT_VALUE = 1
7221 11:13:33.041078 ==============================================================
7222 11:13:33.044427 Enter into Gating configuration >>>>
7223 11:13:33.048292 Exit from Gating configuration <<<<
7224 11:13:33.051522 Enter into DVFS_PRE_config >>>>>
7225 11:13:33.061480 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7226 11:13:33.064935 Exit from DVFS_PRE_config <<<<<
7227 11:13:33.067834 Enter into PICG configuration >>>>
7228 11:13:33.070978 Exit from PICG configuration <<<<
7229 11:13:33.074553 [RX_INPUT] configuration >>>>>
7230 11:13:33.078010 [RX_INPUT] configuration <<<<<
7231 11:13:33.080928 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7232 11:13:33.087948 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7233 11:13:33.094500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 11:13:33.097775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 11:13:33.104277 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 11:13:33.111361 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 11:13:33.114193 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7238 11:13:33.117985 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7239 11:13:33.124304 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7240 11:13:33.127439 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7241 11:13:33.130779 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7242 11:13:33.137321 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 11:13:33.141001 ===================================
7244 11:13:33.141104 LPDDR4 DRAM CONFIGURATION
7245 11:13:33.144354 ===================================
7246 11:13:33.147633 EX_ROW_EN[0] = 0x0
7247 11:13:33.150859 EX_ROW_EN[1] = 0x0
7248 11:13:33.150960 LP4Y_EN = 0x0
7249 11:13:33.154189 WORK_FSP = 0x1
7250 11:13:33.154294 WL = 0x5
7251 11:13:33.157475 RL = 0x5
7252 11:13:33.157587 BL = 0x2
7253 11:13:33.160782 RPST = 0x0
7254 11:13:33.160882 RD_PRE = 0x0
7255 11:13:33.164071 WR_PRE = 0x1
7256 11:13:33.164147 WR_PST = 0x1
7257 11:13:33.167779 DBI_WR = 0x0
7258 11:13:33.167858 DBI_RD = 0x0
7259 11:13:33.171073 OTF = 0x1
7260 11:13:33.174006 ===================================
7261 11:13:33.177605 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7262 11:13:33.180569 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7263 11:13:33.187181 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7264 11:13:33.190748 ===================================
7265 11:13:33.190858 LPDDR4 DRAM CONFIGURATION
7266 11:13:33.194133 ===================================
7267 11:13:33.197318 EX_ROW_EN[0] = 0x10
7268 11:13:33.197419 EX_ROW_EN[1] = 0x0
7269 11:13:33.200641 LP4Y_EN = 0x0
7270 11:13:33.203896 WORK_FSP = 0x1
7271 11:13:33.203976 WL = 0x5
7272 11:13:33.207209 RL = 0x5
7273 11:13:33.207310 BL = 0x2
7274 11:13:33.210611 RPST = 0x0
7275 11:13:33.210712 RD_PRE = 0x0
7276 11:13:33.213806 WR_PRE = 0x1
7277 11:13:33.213907 WR_PST = 0x1
7278 11:13:33.217546 DBI_WR = 0x0
7279 11:13:33.217650 DBI_RD = 0x0
7280 11:13:33.220712 OTF = 0x1
7281 11:13:33.223712 ===================================
7282 11:13:33.230549 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7283 11:13:33.230654 ==
7284 11:13:33.234013 Dram Type= 6, Freq= 0, CH_0, rank 0
7285 11:13:33.237185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7286 11:13:33.237288 ==
7287 11:13:33.240441 [Duty_Offset_Calibration]
7288 11:13:33.240541 B0:2 B1:1 CA:1
7289 11:13:33.240637
7290 11:13:33.243603 [DutyScan_Calibration_Flow] k_type=0
7291 11:13:33.253882
7292 11:13:33.253987 ==CLK 0==
7293 11:13:33.257112 Final CLK duty delay cell = 0
7294 11:13:33.260434 [0] MAX Duty = 5156%(X100), DQS PI = 22
7295 11:13:33.263715 [0] MIN Duty = 4875%(X100), DQS PI = 0
7296 11:13:33.263793 [0] AVG Duty = 5015%(X100)
7297 11:13:33.266928
7298 11:13:33.270825 CH0 CLK Duty spec in!! Max-Min= 281%
7299 11:13:33.273960 [DutyScan_Calibration_Flow] ====Done====
7300 11:13:33.274061
7301 11:13:33.277161 [DutyScan_Calibration_Flow] k_type=1
7302 11:13:33.293242
7303 11:13:33.293347 ==DQS 0 ==
7304 11:13:33.296136 Final DQS duty delay cell = -4
7305 11:13:33.299603 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7306 11:13:33.303101 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7307 11:13:33.306307 [-4] AVG Duty = 4891%(X100)
7308 11:13:33.306408
7309 11:13:33.306506 ==DQS 1 ==
7310 11:13:33.309488 Final DQS duty delay cell = 0
7311 11:13:33.312966 [0] MAX Duty = 5187%(X100), DQS PI = 4
7312 11:13:33.316153 [0] MIN Duty = 5031%(X100), DQS PI = 52
7313 11:13:33.319439 [0] AVG Duty = 5109%(X100)
7314 11:13:33.319517
7315 11:13:33.323132 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7316 11:13:33.323237
7317 11:13:33.326232 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7318 11:13:33.329330 [DutyScan_Calibration_Flow] ====Done====
7319 11:13:33.329430
7320 11:13:33.332986 [DutyScan_Calibration_Flow] k_type=3
7321 11:13:33.349609
7322 11:13:33.349695 ==DQM 0 ==
7323 11:13:33.353342 Final DQM duty delay cell = 0
7324 11:13:33.356726 [0] MAX Duty = 5218%(X100), DQS PI = 32
7325 11:13:33.359944 [0] MIN Duty = 4907%(X100), DQS PI = 56
7326 11:13:33.363195 [0] AVG Duty = 5062%(X100)
7327 11:13:33.363301
7328 11:13:33.363415 ==DQM 1 ==
7329 11:13:33.366494 Final DQM duty delay cell = -4
7330 11:13:33.369846 [-4] MAX Duty = 4969%(X100), DQS PI = 6
7331 11:13:33.373134 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7332 11:13:33.376357 [-4] AVG Duty = 4891%(X100)
7333 11:13:33.376444
7334 11:13:33.379629 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7335 11:13:33.379714
7336 11:13:33.383017 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7337 11:13:33.386090 [DutyScan_Calibration_Flow] ====Done====
7338 11:13:33.386174
7339 11:13:33.389245 [DutyScan_Calibration_Flow] k_type=2
7340 11:13:33.407068
7341 11:13:33.407151 ==DQ 0 ==
7342 11:13:33.410534 Final DQ duty delay cell = 0
7343 11:13:33.413669 [0] MAX Duty = 5062%(X100), DQS PI = 26
7344 11:13:33.417415 [0] MIN Duty = 4907%(X100), DQS PI = 0
7345 11:13:33.417513 [0] AVG Duty = 4984%(X100)
7346 11:13:33.417579
7347 11:13:33.420692 ==DQ 1 ==
7348 11:13:33.423856 Final DQ duty delay cell = 0
7349 11:13:33.426986 [0] MAX Duty = 5156%(X100), DQS PI = 22
7350 11:13:33.430206 [0] MIN Duty = 4938%(X100), DQS PI = 34
7351 11:13:33.430290 [0] AVG Duty = 5047%(X100)
7352 11:13:33.430356
7353 11:13:33.434149 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7354 11:13:33.437350
7355 11:13:33.440427 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7356 11:13:33.443613 [DutyScan_Calibration_Flow] ====Done====
7357 11:13:33.443697 ==
7358 11:13:33.446631 Dram Type= 6, Freq= 0, CH_1, rank 0
7359 11:13:33.450001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7360 11:13:33.450098 ==
7361 11:13:33.453241 [Duty_Offset_Calibration]
7362 11:13:33.453322 B0:1 B1:0 CA:1
7363 11:13:33.453387
7364 11:13:33.456464 [DutyScan_Calibration_Flow] k_type=0
7365 11:13:33.466683
7366 11:13:33.466772 ==CLK 0==
7367 11:13:33.469999 Final CLK duty delay cell = -4
7368 11:13:33.473181 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7369 11:13:33.476520 [-4] MIN Duty = 4876%(X100), DQS PI = 2
7370 11:13:33.479775 [-4] AVG Duty = 4938%(X100)
7371 11:13:33.479853
7372 11:13:33.483049 CH1 CLK Duty spec in!! Max-Min= 124%
7373 11:13:33.486345 [DutyScan_Calibration_Flow] ====Done====
7374 11:13:33.486424
7375 11:13:33.489404 [DutyScan_Calibration_Flow] k_type=1
7376 11:13:33.506286
7377 11:13:33.506363 ==DQS 0 ==
7378 11:13:33.509877 Final DQS duty delay cell = 0
7379 11:13:33.512867 [0] MAX Duty = 5094%(X100), DQS PI = 28
7380 11:13:33.516548 [0] MIN Duty = 4844%(X100), DQS PI = 48
7381 11:13:33.519713 [0] AVG Duty = 4969%(X100)
7382 11:13:33.519787
7383 11:13:33.519857 ==DQS 1 ==
7384 11:13:33.523151 Final DQS duty delay cell = 0
7385 11:13:33.526274 [0] MAX Duty = 5249%(X100), DQS PI = 16
7386 11:13:33.529975 [0] MIN Duty = 4969%(X100), DQS PI = 6
7387 11:13:33.533370 [0] AVG Duty = 5109%(X100)
7388 11:13:33.533451
7389 11:13:33.536466 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7390 11:13:33.536548
7391 11:13:33.539781 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7392 11:13:33.542976 [DutyScan_Calibration_Flow] ====Done====
7393 11:13:33.543058
7394 11:13:33.546538 [DutyScan_Calibration_Flow] k_type=3
7395 11:13:33.563770
7396 11:13:33.563857 ==DQM 0 ==
7397 11:13:33.566936 Final DQM duty delay cell = 0
7398 11:13:33.570245 [0] MAX Duty = 5187%(X100), DQS PI = 10
7399 11:13:33.573446 [0] MIN Duty = 4969%(X100), DQS PI = 48
7400 11:13:33.576854 [0] AVG Duty = 5078%(X100)
7401 11:13:33.576934
7402 11:13:33.576995 ==DQM 1 ==
7403 11:13:33.579984 Final DQM duty delay cell = 0
7404 11:13:33.583329 [0] MAX Duty = 5093%(X100), DQS PI = 16
7405 11:13:33.586511 [0] MIN Duty = 4907%(X100), DQS PI = 34
7406 11:13:33.590468 [0] AVG Duty = 5000%(X100)
7407 11:13:33.590550
7408 11:13:33.593708 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7409 11:13:33.593821
7410 11:13:33.596858 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7411 11:13:33.600021 [DutyScan_Calibration_Flow] ====Done====
7412 11:13:33.600103
7413 11:13:33.603221 [DutyScan_Calibration_Flow] k_type=2
7414 11:13:33.619709
7415 11:13:33.619791 ==DQ 0 ==
7416 11:13:33.623501 Final DQ duty delay cell = -4
7417 11:13:33.626525 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7418 11:13:33.629571 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7419 11:13:33.633193 [-4] AVG Duty = 4968%(X100)
7420 11:13:33.633266
7421 11:13:33.633338 ==DQ 1 ==
7422 11:13:33.636386 Final DQ duty delay cell = 0
7423 11:13:33.639782 [0] MAX Duty = 5124%(X100), DQS PI = 16
7424 11:13:33.643042 [0] MIN Duty = 4938%(X100), DQS PI = 10
7425 11:13:33.646274 [0] AVG Duty = 5031%(X100)
7426 11:13:33.646345
7427 11:13:33.649466 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7428 11:13:33.649539
7429 11:13:33.652621 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7430 11:13:33.656087 [DutyScan_Calibration_Flow] ====Done====
7431 11:13:33.659242 nWR fixed to 30
7432 11:13:33.662483 [ModeRegInit_LP4] CH0 RK0
7433 11:13:33.662562 [ModeRegInit_LP4] CH0 RK1
7434 11:13:33.666383 [ModeRegInit_LP4] CH1 RK0
7435 11:13:33.669006 [ModeRegInit_LP4] CH1 RK1
7436 11:13:33.669078 match AC timing 5
7437 11:13:33.676168 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7438 11:13:33.679452 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7439 11:13:33.682780 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7440 11:13:33.689159 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7441 11:13:33.692482 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7442 11:13:33.692555 [MiockJmeterHQA]
7443 11:13:33.692625
7444 11:13:33.695670 [DramcMiockJmeter] u1RxGatingPI = 0
7445 11:13:33.699001 0 : 4258, 4029
7446 11:13:33.699080 4 : 4252, 4027
7447 11:13:33.702202 8 : 4255, 4029
7448 11:13:33.702272 12 : 4252, 4026
7449 11:13:33.702342 16 : 4252, 4027
7450 11:13:33.706188 20 : 4252, 4027
7451 11:13:33.706260 24 : 4253, 4027
7452 11:13:33.709294 28 : 4366, 4140
7453 11:13:33.709377 32 : 4252, 4027
7454 11:13:33.712345 36 : 4255, 4029
7455 11:13:33.712416 40 : 4252, 4027
7456 11:13:33.716072 44 : 4363, 4138
7457 11:13:33.716144 48 : 4253, 4027
7458 11:13:33.716205 52 : 4363, 4137
7459 11:13:33.719030 56 : 4250, 4026
7460 11:13:33.719103 60 : 4252, 4027
7461 11:13:33.722689 64 : 4250, 4027
7462 11:13:33.722764 68 : 4253, 4029
7463 11:13:33.725862 72 : 4360, 4137
7464 11:13:33.725936 76 : 4250, 4027
7465 11:13:33.729425 80 : 4361, 4138
7466 11:13:33.729497 84 : 4250, 4027
7467 11:13:33.729560 88 : 4250, 142
7468 11:13:33.732411 92 : 4362, 0
7469 11:13:33.732485 96 : 4250, 0
7470 11:13:33.735564 100 : 4252, 0
7471 11:13:33.735638 104 : 4250, 0
7472 11:13:33.735699 108 : 4250, 0
7473 11:13:33.739173 112 : 4363, 0
7474 11:13:33.739285 116 : 4250, 0
7475 11:13:33.739410 120 : 4250, 0
7476 11:13:33.742416 124 : 4250, 0
7477 11:13:33.742493 128 : 4253, 0
7478 11:13:33.745652 132 : 4250, 0
7479 11:13:33.745731 136 : 4250, 0
7480 11:13:33.745794 140 : 4253, 0
7481 11:13:33.748772 144 : 4250, 0
7482 11:13:33.748845 148 : 4361, 0
7483 11:13:33.752040 152 : 4360, 0
7484 11:13:33.752120 156 : 4250, 0
7485 11:13:33.752183 160 : 4250, 0
7486 11:13:33.755487 164 : 4250, 0
7487 11:13:33.755560 168 : 4253, 0
7488 11:13:33.759181 172 : 4250, 0
7489 11:13:33.759294 176 : 4250, 0
7490 11:13:33.759412 180 : 4252, 0
7491 11:13:33.762252 184 : 4250, 0
7492 11:13:33.762326 188 : 4250, 0
7493 11:13:33.762388 192 : 4252, 0
7494 11:13:33.765912 196 : 4250, 0
7495 11:13:33.765990 200 : 4361, 0
7496 11:13:33.769107 204 : 4250, 1353
7497 11:13:33.769181 208 : 4250, 3996
7498 11:13:33.772391 212 : 4250, 4027
7499 11:13:33.772466 216 : 4250, 4026
7500 11:13:33.776059 220 : 4250, 4027
7501 11:13:33.776135 224 : 4250, 4026
7502 11:13:33.776198 228 : 4250, 4027
7503 11:13:33.779457 232 : 4250, 4026
7504 11:13:33.779533 236 : 4253, 4029
7505 11:13:33.782127 240 : 4250, 4026
7506 11:13:33.782198 244 : 4361, 4137
7507 11:13:33.786020 248 : 4360, 4138
7508 11:13:33.786096 252 : 4250, 4027
7509 11:13:33.789294 256 : 4362, 4140
7510 11:13:33.789365 260 : 4250, 4026
7511 11:13:33.792615 264 : 4250, 4027
7512 11:13:33.792686 268 : 4250, 4027
7513 11:13:33.795820 272 : 4253, 4029
7514 11:13:33.795889 276 : 4250, 4026
7515 11:13:33.799239 280 : 4250, 4027
7516 11:13:33.799357 284 : 4250, 4027
7517 11:13:33.799422 288 : 4252, 4029
7518 11:13:33.802533 292 : 4250, 4026
7519 11:13:33.802601 296 : 4361, 4137
7520 11:13:33.805649 300 : 4360, 4138
7521 11:13:33.805718 304 : 4250, 4027
7522 11:13:33.808921 308 : 4363, 4108
7523 11:13:33.809006 312 : 4250, 2127
7524 11:13:33.812190 316 : 4250, 1
7525 11:13:33.812268
7526 11:13:33.812332 MIOCK jitter meter ch=0
7527 11:13:33.812392
7528 11:13:33.815500 1T = (316-88) = 228 dly cells
7529 11:13:33.822328 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7530 11:13:33.822430 ==
7531 11:13:33.825407 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 11:13:33.828599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 11:13:33.828684 ==
7534 11:13:33.835500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 11:13:33.838592 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 11:13:33.842273 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 11:13:33.849088 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 11:13:33.858738 [CA 0] Center 43 (12~74) winsize 63
7539 11:13:33.862073 [CA 1] Center 43 (12~74) winsize 63
7540 11:13:33.865436 [CA 2] Center 38 (9~68) winsize 60
7541 11:13:33.868397 [CA 3] Center 38 (8~68) winsize 61
7542 11:13:33.872086 [CA 4] Center 37 (7~67) winsize 61
7543 11:13:33.875258 [CA 5] Center 35 (6~65) winsize 60
7544 11:13:33.875364
7545 11:13:33.878875 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 11:13:33.878958
7547 11:13:33.882099 [CATrainingPosCal] consider 1 rank data
7548 11:13:33.885520 u2DelayCellTimex100 = 285/100 ps
7549 11:13:33.888637 CA0 delay=43 (12~74),Diff = 8 PI (27 cell)
7550 11:13:33.895314 CA1 delay=43 (12~74),Diff = 8 PI (27 cell)
7551 11:13:33.898583 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7552 11:13:33.901840 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7553 11:13:33.905024 CA4 delay=37 (7~67),Diff = 2 PI (6 cell)
7554 11:13:33.908333 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7555 11:13:33.908417
7556 11:13:33.911490 CA PerBit enable=1, Macro0, CA PI delay=35
7557 11:13:33.911573
7558 11:13:33.914773 [CBTSetCACLKResult] CA Dly = 35
7559 11:13:33.918644 CS Dly: 9 (0~40)
7560 11:13:33.922040 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 11:13:33.925197 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 11:13:33.925280 ==
7563 11:13:33.928421 Dram Type= 6, Freq= 0, CH_0, rank 1
7564 11:13:33.931486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 11:13:33.934984 ==
7566 11:13:33.937920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7567 11:13:33.941595 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7568 11:13:33.948315 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7569 11:13:33.954545 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7570 11:13:33.962210 [CA 0] Center 42 (12~73) winsize 62
7571 11:13:33.965417 [CA 1] Center 42 (12~73) winsize 62
7572 11:13:33.968669 [CA 2] Center 38 (8~68) winsize 61
7573 11:13:33.971994 [CA 3] Center 37 (8~67) winsize 60
7574 11:13:33.975800 [CA 4] Center 36 (6~66) winsize 61
7575 11:13:33.978781 [CA 5] Center 35 (5~65) winsize 61
7576 11:13:33.978863
7577 11:13:33.981816 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7578 11:13:33.981899
7579 11:13:33.985501 [CATrainingPosCal] consider 2 rank data
7580 11:13:33.988772 u2DelayCellTimex100 = 285/100 ps
7581 11:13:33.992104 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7582 11:13:33.998760 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7583 11:13:34.002061 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7584 11:13:34.005219 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7585 11:13:34.008487 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7586 11:13:34.012320 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7587 11:13:34.012402
7588 11:13:34.015434 CA PerBit enable=1, Macro0, CA PI delay=35
7589 11:13:34.015517
7590 11:13:34.018441 [CBTSetCACLKResult] CA Dly = 35
7591 11:13:34.021674 CS Dly: 10 (0~42)
7592 11:13:34.025589 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7593 11:13:34.028840 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7594 11:13:34.028923
7595 11:13:34.031572 ----->DramcWriteLeveling(PI) begin...
7596 11:13:34.031656 ==
7597 11:13:34.035529 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 11:13:34.038622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 11:13:34.042193 ==
7600 11:13:34.042276 Write leveling (Byte 0): 35 => 35
7601 11:13:34.045396 Write leveling (Byte 1): 30 => 30
7602 11:13:34.048863 DramcWriteLeveling(PI) end<-----
7603 11:13:34.048946
7604 11:13:34.049041 ==
7605 11:13:34.051786 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 11:13:34.058619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 11:13:34.058703 ==
7608 11:13:34.058768 [Gating] SW mode calibration
7609 11:13:34.068565 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7610 11:13:34.071679 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7611 11:13:34.074995 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 11:13:34.086500 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 11:13:34.086586 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7614 11:13:34.088468 1 4 12 | B1->B0 | 2323 3736 | 0 1 | (0 0) (1 1)
7615 11:13:34.095253 1 4 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7616 11:13:34.098338 1 4 20 | B1->B0 | 3333 3636 | 0 0 | (0 0) (0 0)
7617 11:13:34.102002 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7618 11:13:34.108475 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7619 11:13:34.112408 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7620 11:13:34.115568 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7621 11:13:34.121689 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7622 11:13:34.125500 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7623 11:13:34.128630 1 5 16 | B1->B0 | 3434 2625 | 1 1 | (1 0) (0 0)
7624 11:13:34.135164 1 5 20 | B1->B0 | 2727 2424 | 0 0 | (0 1) (0 0)
7625 11:13:34.138390 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 11:13:34.141559 1 5 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
7627 11:13:34.148450 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7628 11:13:34.151515 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7629 11:13:34.155222 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7630 11:13:34.161456 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7631 11:13:34.164749 1 6 16 | B1->B0 | 2b2b 4645 | 0 1 | (0 0) (0 0)
7632 11:13:34.168538 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7633 11:13:34.175035 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7634 11:13:34.178008 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 11:13:34.181675 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 11:13:34.187989 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 11:13:34.191739 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7638 11:13:34.194950 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7639 11:13:34.201491 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7640 11:13:34.204980 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7641 11:13:34.207958 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 11:13:34.214356 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 11:13:34.218148 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 11:13:34.221342 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 11:13:34.224424 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 11:13:34.231437 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 11:13:34.234618 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 11:13:34.237810 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 11:13:34.244904 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 11:13:34.248135 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 11:13:34.251463 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 11:13:34.257784 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 11:13:34.261534 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 11:13:34.264348 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7655 11:13:34.270909 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7656 11:13:34.274370 Total UI for P1: 0, mck2ui 16
7657 11:13:34.278133 best dqsien dly found for B0: ( 1, 9, 12)
7658 11:13:34.280971 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7659 11:13:34.284507 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 11:13:34.287589 Total UI for P1: 0, mck2ui 16
7661 11:13:34.290655 best dqsien dly found for B1: ( 1, 9, 20)
7662 11:13:34.294430 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7663 11:13:34.297736 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7664 11:13:34.297821
7665 11:13:34.304082 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7666 11:13:34.307865 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7667 11:13:34.310868 [Gating] SW calibration Done
7668 11:13:34.310957 ==
7669 11:13:34.314061 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 11:13:34.317625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 11:13:34.317713 ==
7672 11:13:34.317798 RX Vref Scan: 0
7673 11:13:34.317879
7674 11:13:34.320740 RX Vref 0 -> 0, step: 1
7675 11:13:34.320826
7676 11:13:34.324000 RX Delay 0 -> 252, step: 8
7677 11:13:34.327862 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7678 11:13:34.330673 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7679 11:13:34.337844 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7680 11:13:34.340446 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7681 11:13:34.344188 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7682 11:13:34.347455 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7683 11:13:34.350527 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7684 11:13:34.353758 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7685 11:13:34.360359 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7686 11:13:34.364113 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7687 11:13:34.367285 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7688 11:13:34.370516 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7689 11:13:34.374177 iDelay=200, Bit 12, Center 135 (88 ~ 183) 96
7690 11:13:34.380786 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7691 11:13:34.383676 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7692 11:13:34.387321 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7693 11:13:34.387429 ==
7694 11:13:34.390891 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 11:13:34.393909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 11:13:34.397490 ==
7697 11:13:34.397580 DQS Delay:
7698 11:13:34.397666 DQS0 = 0, DQS1 = 0
7699 11:13:34.400528 DQM Delay:
7700 11:13:34.400613 DQM0 = 137, DQM1 = 130
7701 11:13:34.404235 DQ Delay:
7702 11:13:34.407486 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7703 11:13:34.410569 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7704 11:13:34.413804 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7705 11:13:34.417395 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7706 11:13:34.417483
7707 11:13:34.417567
7708 11:13:34.417646 ==
7709 11:13:34.420472 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 11:13:34.423624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 11:13:34.423710 ==
7712 11:13:34.423795
7713 11:13:34.423875
7714 11:13:34.427396 TX Vref Scan disable
7715 11:13:34.430709 == TX Byte 0 ==
7716 11:13:34.434027 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7717 11:13:34.437041 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7718 11:13:34.440174 == TX Byte 1 ==
7719 11:13:34.443466 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7720 11:13:34.447312 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7721 11:13:34.447423 ==
7722 11:13:34.450479 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 11:13:34.456984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 11:13:34.457072 ==
7725 11:13:34.467807
7726 11:13:34.470971 TX Vref early break, caculate TX vref
7727 11:13:34.474132 TX Vref=16, minBit 4, minWin=22, winSum=377
7728 11:13:34.477998 TX Vref=18, minBit 0, minWin=24, winSum=392
7729 11:13:34.481177 TX Vref=20, minBit 1, minWin=23, winSum=402
7730 11:13:34.484455 TX Vref=22, minBit 0, minWin=24, winSum=412
7731 11:13:34.487483 TX Vref=24, minBit 7, minWin=25, winSum=422
7732 11:13:34.494344 TX Vref=26, minBit 0, minWin=26, winSum=429
7733 11:13:34.498026 TX Vref=28, minBit 6, minWin=24, winSum=423
7734 11:13:34.501019 TX Vref=30, minBit 1, minWin=24, winSum=414
7735 11:13:34.504627 TX Vref=32, minBit 1, minWin=24, winSum=405
7736 11:13:34.511238 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 26
7737 11:13:34.511377
7738 11:13:34.514245 Final TX Range 0 Vref 26
7739 11:13:34.514323
7740 11:13:34.514386 ==
7741 11:13:34.518033 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 11:13:34.521175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 11:13:34.521252 ==
7744 11:13:34.521316
7745 11:13:34.521377
7746 11:13:34.524263 TX Vref Scan disable
7747 11:13:34.527787 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7748 11:13:34.530822 == TX Byte 0 ==
7749 11:13:34.533976 u2DelayCellOfst[0]=10 cells (3 PI)
7750 11:13:34.537754 u2DelayCellOfst[1]=13 cells (4 PI)
7751 11:13:34.540880 u2DelayCellOfst[2]=10 cells (3 PI)
7752 11:13:34.544120 u2DelayCellOfst[3]=6 cells (2 PI)
7753 11:13:34.547170 u2DelayCellOfst[4]=6 cells (2 PI)
7754 11:13:34.547276 u2DelayCellOfst[5]=0 cells (0 PI)
7755 11:13:34.550967 u2DelayCellOfst[6]=17 cells (5 PI)
7756 11:13:34.554130 u2DelayCellOfst[7]=17 cells (5 PI)
7757 11:13:34.560424 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7758 11:13:34.563660 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7759 11:13:34.563787 == TX Byte 1 ==
7760 11:13:34.567339 u2DelayCellOfst[8]=0 cells (0 PI)
7761 11:13:34.570673 u2DelayCellOfst[9]=0 cells (0 PI)
7762 11:13:34.573929 u2DelayCellOfst[10]=6 cells (2 PI)
7763 11:13:34.577086 u2DelayCellOfst[11]=3 cells (1 PI)
7764 11:13:34.580273 u2DelayCellOfst[12]=10 cells (3 PI)
7765 11:13:34.583490 u2DelayCellOfst[13]=10 cells (3 PI)
7766 11:13:34.587233 u2DelayCellOfst[14]=13 cells (4 PI)
7767 11:13:34.590377 u2DelayCellOfst[15]=10 cells (3 PI)
7768 11:13:34.593621 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7769 11:13:34.597213 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7770 11:13:34.600338 DramC Write-DBI on
7771 11:13:34.600439 ==
7772 11:13:34.603819 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 11:13:34.606728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 11:13:34.606878 ==
7775 11:13:34.606978
7776 11:13:34.610017
7777 11:13:34.610144 TX Vref Scan disable
7778 11:13:34.613516 == TX Byte 0 ==
7779 11:13:34.617167 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7780 11:13:34.620114 == TX Byte 1 ==
7781 11:13:34.623723 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7782 11:13:34.623806 DramC Write-DBI off
7783 11:13:34.623873
7784 11:13:34.626843 [DATLAT]
7785 11:13:34.626926 Freq=1600, CH0 RK0
7786 11:13:34.626993
7787 11:13:34.629908 DATLAT Default: 0xf
7788 11:13:34.629990 0, 0xFFFF, sum = 0
7789 11:13:34.633013 1, 0xFFFF, sum = 0
7790 11:13:34.633127 2, 0xFFFF, sum = 0
7791 11:13:34.636761 3, 0xFFFF, sum = 0
7792 11:13:34.636846 4, 0xFFFF, sum = 0
7793 11:13:34.639878 5, 0xFFFF, sum = 0
7794 11:13:34.643128 6, 0xFFFF, sum = 0
7795 11:13:34.643230 7, 0xFFFF, sum = 0
7796 11:13:34.646769 8, 0xFFFF, sum = 0
7797 11:13:34.646854 9, 0xFFFF, sum = 0
7798 11:13:34.650128 10, 0xFFFF, sum = 0
7799 11:13:34.650237 11, 0xFFFF, sum = 0
7800 11:13:34.653316 12, 0xFFFF, sum = 0
7801 11:13:34.653401 13, 0xFFFF, sum = 0
7802 11:13:34.656497 14, 0x0, sum = 1
7803 11:13:34.656585 15, 0x0, sum = 2
7804 11:13:34.659771 16, 0x0, sum = 3
7805 11:13:34.659942 17, 0x0, sum = 4
7806 11:13:34.662951 best_step = 15
7807 11:13:34.663034
7808 11:13:34.663100 ==
7809 11:13:34.666254 Dram Type= 6, Freq= 0, CH_0, rank 0
7810 11:13:34.670052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7811 11:13:34.670136 ==
7812 11:13:34.670203 RX Vref Scan: 1
7813 11:13:34.673218
7814 11:13:34.673300 Set Vref Range= 24 -> 127
7815 11:13:34.673366
7816 11:13:34.676456 RX Vref 24 -> 127, step: 1
7817 11:13:34.676540
7818 11:13:34.679626 RX Delay 19 -> 252, step: 4
7819 11:13:34.679732
7820 11:13:34.682795 Set Vref, RX VrefLevel [Byte0]: 24
7821 11:13:34.686183 [Byte1]: 24
7822 11:13:34.686267
7823 11:13:34.689297 Set Vref, RX VrefLevel [Byte0]: 25
7824 11:13:34.692561 [Byte1]: 25
7825 11:13:34.692645
7826 11:13:34.696486 Set Vref, RX VrefLevel [Byte0]: 26
7827 11:13:34.699561 [Byte1]: 26
7828 11:13:34.703462
7829 11:13:34.703546 Set Vref, RX VrefLevel [Byte0]: 27
7830 11:13:34.706529 [Byte1]: 27
7831 11:13:34.710985
7832 11:13:34.711070 Set Vref, RX VrefLevel [Byte0]: 28
7833 11:13:34.713920 [Byte1]: 28
7834 11:13:34.718786
7835 11:13:34.718870 Set Vref, RX VrefLevel [Byte0]: 29
7836 11:13:34.721927 [Byte1]: 29
7837 11:13:34.726201
7838 11:13:34.726316 Set Vref, RX VrefLevel [Byte0]: 30
7839 11:13:34.729322 [Byte1]: 30
7840 11:13:34.733594
7841 11:13:34.733705 Set Vref, RX VrefLevel [Byte0]: 31
7842 11:13:34.736851 [Byte1]: 31
7843 11:13:34.741206
7844 11:13:34.741290 Set Vref, RX VrefLevel [Byte0]: 32
7845 11:13:34.744847 [Byte1]: 32
7846 11:13:34.748632
7847 11:13:34.748716 Set Vref, RX VrefLevel [Byte0]: 33
7848 11:13:34.751863 [Byte1]: 33
7849 11:13:34.756313
7850 11:13:34.756397 Set Vref, RX VrefLevel [Byte0]: 34
7851 11:13:34.759560 [Byte1]: 34
7852 11:13:34.764006
7853 11:13:34.764092 Set Vref, RX VrefLevel [Byte0]: 35
7854 11:13:34.767181 [Byte1]: 35
7855 11:13:34.771578
7856 11:13:34.771662 Set Vref, RX VrefLevel [Byte0]: 36
7857 11:13:34.774767 [Byte1]: 36
7858 11:13:34.779239
7859 11:13:34.779369 Set Vref, RX VrefLevel [Byte0]: 37
7860 11:13:34.782450 [Byte1]: 37
7861 11:13:34.786924
7862 11:13:34.787008 Set Vref, RX VrefLevel [Byte0]: 38
7863 11:13:34.790120 [Byte1]: 38
7864 11:13:34.794009
7865 11:13:34.794162 Set Vref, RX VrefLevel [Byte0]: 39
7866 11:13:34.797275 [Byte1]: 39
7867 11:13:34.801795
7868 11:13:34.801878 Set Vref, RX VrefLevel [Byte0]: 40
7869 11:13:34.804817 [Byte1]: 40
7870 11:13:34.809334
7871 11:13:34.809420 Set Vref, RX VrefLevel [Byte0]: 41
7872 11:13:34.812527 [Byte1]: 41
7873 11:13:34.816838
7874 11:13:34.816920 Set Vref, RX VrefLevel [Byte0]: 42
7875 11:13:34.820026 [Byte1]: 42
7876 11:13:34.824337
7877 11:13:34.824451 Set Vref, RX VrefLevel [Byte0]: 43
7878 11:13:34.827526 [Byte1]: 43
7879 11:13:34.832436
7880 11:13:34.832528 Set Vref, RX VrefLevel [Byte0]: 44
7881 11:13:34.835210 [Byte1]: 44
7882 11:13:34.839400
7883 11:13:34.839473 Set Vref, RX VrefLevel [Byte0]: 45
7884 11:13:34.843189 [Byte1]: 45
7885 11:13:34.847455
7886 11:13:34.847529 Set Vref, RX VrefLevel [Byte0]: 46
7887 11:13:34.850736 [Byte1]: 46
7888 11:13:34.854978
7889 11:13:34.855063 Set Vref, RX VrefLevel [Byte0]: 47
7890 11:13:34.858165 [Byte1]: 47
7891 11:13:34.862518
7892 11:13:34.862662 Set Vref, RX VrefLevel [Byte0]: 48
7893 11:13:34.865688 [Byte1]: 48
7894 11:13:34.870105
7895 11:13:34.870234 Set Vref, RX VrefLevel [Byte0]: 49
7896 11:13:34.873414 [Byte1]: 49
7897 11:13:34.877326
7898 11:13:34.877449 Set Vref, RX VrefLevel [Byte0]: 50
7899 11:13:34.881116 [Byte1]: 50
7900 11:13:34.884848
7901 11:13:34.884931 Set Vref, RX VrefLevel [Byte0]: 51
7902 11:13:34.888680 [Byte1]: 51
7903 11:13:34.892660
7904 11:13:34.892731 Set Vref, RX VrefLevel [Byte0]: 52
7905 11:13:34.895847 [Byte1]: 52
7906 11:13:34.900314
7907 11:13:34.900384 Set Vref, RX VrefLevel [Byte0]: 53
7908 11:13:34.903493 [Byte1]: 53
7909 11:13:34.907967
7910 11:13:34.908043 Set Vref, RX VrefLevel [Byte0]: 54
7911 11:13:34.910965 [Byte1]: 54
7912 11:13:34.915276
7913 11:13:34.915385 Set Vref, RX VrefLevel [Byte0]: 55
7914 11:13:34.918588 [Byte1]: 55
7915 11:13:34.922966
7916 11:13:34.923038 Set Vref, RX VrefLevel [Byte0]: 56
7917 11:13:34.926009 [Byte1]: 56
7918 11:13:34.931024
7919 11:13:34.931115 Set Vref, RX VrefLevel [Byte0]: 57
7920 11:13:34.933764 [Byte1]: 57
7921 11:13:34.938061
7922 11:13:34.938142 Set Vref, RX VrefLevel [Byte0]: 58
7923 11:13:34.941546 [Byte1]: 58
7924 11:13:34.945823
7925 11:13:34.945899 Set Vref, RX VrefLevel [Byte0]: 59
7926 11:13:34.948720 [Byte1]: 59
7927 11:13:34.953280
7928 11:13:34.953388 Set Vref, RX VrefLevel [Byte0]: 60
7929 11:13:34.956346 [Byte1]: 60
7930 11:13:34.960618
7931 11:13:34.960700 Set Vref, RX VrefLevel [Byte0]: 61
7932 11:13:34.964399 [Byte1]: 61
7933 11:13:34.968634
7934 11:13:34.968717 Set Vref, RX VrefLevel [Byte0]: 62
7935 11:13:34.971751 [Byte1]: 62
7936 11:13:34.976162
7937 11:13:34.976264 Set Vref, RX VrefLevel [Byte0]: 63
7938 11:13:34.979510 [Byte1]: 63
7939 11:13:34.983294
7940 11:13:34.983387 Set Vref, RX VrefLevel [Byte0]: 64
7941 11:13:34.987202 [Byte1]: 64
7942 11:13:34.991092
7943 11:13:34.991175 Set Vref, RX VrefLevel [Byte0]: 65
7944 11:13:34.994325 [Byte1]: 65
7945 11:13:34.999102
7946 11:13:34.999199 Set Vref, RX VrefLevel [Byte0]: 66
7947 11:13:35.002143 [Byte1]: 66
7948 11:13:35.006076
7949 11:13:35.006160 Set Vref, RX VrefLevel [Byte0]: 67
7950 11:13:35.010038 [Byte1]: 67
7951 11:13:35.013727
7952 11:13:35.013810 Set Vref, RX VrefLevel [Byte0]: 68
7953 11:13:35.017538 [Byte1]: 68
7954 11:13:35.021558
7955 11:13:35.021640 Set Vref, RX VrefLevel [Byte0]: 69
7956 11:13:35.024712 [Byte1]: 69
7957 11:13:35.029239
7958 11:13:35.029321 Set Vref, RX VrefLevel [Byte0]: 70
7959 11:13:35.032211 [Byte1]: 70
7960 11:13:35.036645
7961 11:13:35.036728 Set Vref, RX VrefLevel [Byte0]: 71
7962 11:13:35.039675 [Byte1]: 71
7963 11:13:35.043960
7964 11:13:35.044042 Set Vref, RX VrefLevel [Byte0]: 72
7965 11:13:35.047522 [Byte1]: 72
7966 11:13:35.051622
7967 11:13:35.051735 Set Vref, RX VrefLevel [Byte0]: 73
7968 11:13:35.055284 [Byte1]: 73
7969 11:13:35.059057
7970 11:13:35.059140 Set Vref, RX VrefLevel [Byte0]: 74
7971 11:13:35.062929 [Byte1]: 74
7972 11:13:35.067029
7973 11:13:35.067111 Set Vref, RX VrefLevel [Byte0]: 75
7974 11:13:35.070106 [Byte1]: 75
7975 11:13:35.074235
7976 11:13:35.074318 Set Vref, RX VrefLevel [Byte0]: 76
7977 11:13:35.077834 [Byte1]: 76
7978 11:13:35.081841
7979 11:13:35.081924 Set Vref, RX VrefLevel [Byte0]: 77
7980 11:13:35.085732 [Byte1]: 77
7981 11:13:35.089493
7982 11:13:35.089602 Final RX Vref Byte 0 = 53 to rank0
7983 11:13:35.092823 Final RX Vref Byte 1 = 61 to rank0
7984 11:13:35.096050 Final RX Vref Byte 0 = 53 to rank1
7985 11:13:35.099913 Final RX Vref Byte 1 = 61 to rank1==
7986 11:13:35.103061 Dram Type= 6, Freq= 0, CH_0, rank 0
7987 11:13:35.109306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 11:13:35.109390 ==
7989 11:13:35.109457 DQS Delay:
7990 11:13:35.112560 DQS0 = 0, DQS1 = 0
7991 11:13:35.112675 DQM Delay:
7992 11:13:35.112809 DQM0 = 133, DQM1 = 127
7993 11:13:35.116295 DQ Delay:
7994 11:13:35.119208 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =130
7995 11:13:35.123036 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =138
7996 11:13:35.126281 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7997 11:13:35.129528 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7998 11:13:35.129614
7999 11:13:35.129680
8000 11:13:35.129740
8001 11:13:35.132723 [DramC_TX_OE_Calibration] TA2
8002 11:13:35.135839 Original DQ_B0 (3 6) =30, OEN = 27
8003 11:13:35.139556 Original DQ_B1 (3 6) =30, OEN = 27
8004 11:13:35.142604 24, 0x0, End_B0=24 End_B1=24
8005 11:13:35.142688 25, 0x0, End_B0=25 End_B1=25
8006 11:13:35.146161 26, 0x0, End_B0=26 End_B1=26
8007 11:13:35.149173 27, 0x0, End_B0=27 End_B1=27
8008 11:13:35.152745 28, 0x0, End_B0=28 End_B1=28
8009 11:13:35.155779 29, 0x0, End_B0=29 End_B1=29
8010 11:13:35.155863 30, 0x0, End_B0=30 End_B1=30
8011 11:13:35.159550 31, 0x5151, End_B0=30 End_B1=30
8012 11:13:35.162591 Byte0 end_step=30 best_step=27
8013 11:13:35.165835 Byte1 end_step=30 best_step=27
8014 11:13:35.169537 Byte0 TX OE(2T, 0.5T) = (3, 3)
8015 11:13:35.169621 Byte1 TX OE(2T, 0.5T) = (3, 3)
8016 11:13:35.172661
8017 11:13:35.172744
8018 11:13:35.179458 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
8019 11:13:35.182326 CH0 RK0: MR19=303, MR18=2723
8020 11:13:35.189301 CH0_RK0: MR19=0x303, MR18=0x2723, DQSOSC=390, MR23=63, INC=24, DEC=16
8021 11:13:35.189386
8022 11:13:35.192369 ----->DramcWriteLeveling(PI) begin...
8023 11:13:35.192455 ==
8024 11:13:35.195623 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 11:13:35.199469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 11:13:35.199553 ==
8027 11:13:35.202752 Write leveling (Byte 0): 36 => 36
8028 11:13:35.205944 Write leveling (Byte 1): 27 => 27
8029 11:13:35.209158 DramcWriteLeveling(PI) end<-----
8030 11:13:35.209240
8031 11:13:35.209305 ==
8032 11:13:35.212426 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 11:13:35.215661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 11:13:35.215744 ==
8035 11:13:35.218875 [Gating] SW mode calibration
8036 11:13:35.225521 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8037 11:13:35.231998 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8038 11:13:35.236002 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8039 11:13:35.239018 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 11:13:35.245441 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8041 11:13:35.248584 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8042 11:13:35.252062 1 4 16 | B1->B0 | 2d2d 3636 | 1 0 | (1 1) (0 0)
8043 11:13:35.259004 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8044 11:13:35.262545 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
8045 11:13:35.265567 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8046 11:13:35.272117 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8047 11:13:35.275778 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8048 11:13:35.278916 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 0) (0 0)
8049 11:13:35.285615 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8050 11:13:35.288515 1 5 16 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)
8051 11:13:35.292097 1 5 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8052 11:13:35.298384 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8053 11:13:35.302280 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8054 11:13:35.305572 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8055 11:13:35.312054 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 11:13:35.315268 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8057 11:13:35.318550 1 6 12 | B1->B0 | 2525 3d3c | 0 1 | (0 0) (1 1)
8058 11:13:35.325594 1 6 16 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
8059 11:13:35.328656 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 11:13:35.331791 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8061 11:13:35.338832 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 11:13:35.341985 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 11:13:35.345288 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 11:13:35.351684 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 11:13:35.355432 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8066 11:13:35.358566 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8067 11:13:35.365198 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 11:13:35.368085 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 11:13:35.371826 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 11:13:35.378211 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 11:13:35.381625 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 11:13:35.384717 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 11:13:35.388348 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 11:13:35.394779 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 11:13:35.398496 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 11:13:35.401831 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 11:13:35.408118 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 11:13:35.411206 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 11:13:35.414521 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 11:13:35.421526 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8081 11:13:35.424729 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8082 11:13:35.427967 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8083 11:13:35.434772 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 11:13:35.438056 Total UI for P1: 0, mck2ui 16
8085 11:13:35.441209 best dqsien dly found for B0: ( 1, 9, 12)
8086 11:13:35.444496 Total UI for P1: 0, mck2ui 16
8087 11:13:35.447721 best dqsien dly found for B1: ( 1, 9, 14)
8088 11:13:35.451608 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8089 11:13:35.454595 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8090 11:13:35.454684
8091 11:13:35.457851 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8092 11:13:35.461068 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8093 11:13:35.464270 [Gating] SW calibration Done
8094 11:13:35.464357 ==
8095 11:13:35.467994 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 11:13:35.471250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 11:13:35.471395 ==
8098 11:13:35.474337 RX Vref Scan: 0
8099 11:13:35.474428
8100 11:13:35.477902 RX Vref 0 -> 0, step: 1
8101 11:13:35.477986
8102 11:13:35.478052 RX Delay 0 -> 252, step: 8
8103 11:13:35.484462 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8104 11:13:35.487682 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8105 11:13:35.491248 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8106 11:13:35.494206 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8107 11:13:35.497433 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8108 11:13:35.504133 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8109 11:13:35.507827 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8110 11:13:35.510807 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8111 11:13:35.514077 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8112 11:13:35.517941 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8113 11:13:35.521199 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8114 11:13:35.527420 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8115 11:13:35.530650 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8116 11:13:35.533908 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8117 11:13:35.537643 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8118 11:13:35.544306 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8119 11:13:35.544394 ==
8120 11:13:35.547449 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 11:13:35.550629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 11:13:35.550739 ==
8123 11:13:35.550888 DQS Delay:
8124 11:13:35.554574 DQS0 = 0, DQS1 = 0
8125 11:13:35.554667 DQM Delay:
8126 11:13:35.557424 DQM0 = 136, DQM1 = 128
8127 11:13:35.557507 DQ Delay:
8128 11:13:35.560541 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8129 11:13:35.563848 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8130 11:13:35.567606 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8131 11:13:35.570743 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8132 11:13:35.570826
8133 11:13:35.570892
8134 11:13:35.574029 ==
8135 11:13:35.577079 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 11:13:35.580964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 11:13:35.581048 ==
8138 11:13:35.581114
8139 11:13:35.581176
8140 11:13:35.583864 TX Vref Scan disable
8141 11:13:35.583949 == TX Byte 0 ==
8142 11:13:35.587006 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8143 11:13:35.593547 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8144 11:13:35.593631 == TX Byte 1 ==
8145 11:13:35.600317 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8146 11:13:35.603511 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8147 11:13:35.603595 ==
8148 11:13:35.606961 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 11:13:35.610547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 11:13:35.610640 ==
8151 11:13:35.624861
8152 11:13:35.628138 TX Vref early break, caculate TX vref
8153 11:13:35.631267 TX Vref=16, minBit 3, minWin=22, winSum=384
8154 11:13:35.634589 TX Vref=18, minBit 1, minWin=23, winSum=398
8155 11:13:35.638308 TX Vref=20, minBit 1, minWin=23, winSum=405
8156 11:13:35.641489 TX Vref=22, minBit 1, minWin=24, winSum=408
8157 11:13:35.644465 TX Vref=24, minBit 1, minWin=24, winSum=416
8158 11:13:35.651264 TX Vref=26, minBit 0, minWin=26, winSum=427
8159 11:13:35.654503 TX Vref=28, minBit 3, minWin=24, winSum=420
8160 11:13:35.657694 TX Vref=30, minBit 3, minWin=25, winSum=416
8161 11:13:35.661442 TX Vref=32, minBit 1, minWin=24, winSum=407
8162 11:13:35.664667 TX Vref=34, minBit 0, minWin=23, winSum=401
8163 11:13:35.671703 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
8164 11:13:35.671779
8165 11:13:35.674783 Final TX Range 0 Vref 26
8166 11:13:35.674856
8167 11:13:35.674918 ==
8168 11:13:35.678397 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 11:13:35.681451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 11:13:35.681530 ==
8171 11:13:35.681591
8172 11:13:35.681649
8173 11:13:35.684571 TX Vref Scan disable
8174 11:13:35.691350 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8175 11:13:35.691444 == TX Byte 0 ==
8176 11:13:35.694390 u2DelayCellOfst[0]=13 cells (4 PI)
8177 11:13:35.698104 u2DelayCellOfst[1]=17 cells (5 PI)
8178 11:13:35.701154 u2DelayCellOfst[2]=13 cells (4 PI)
8179 11:13:35.704244 u2DelayCellOfst[3]=10 cells (3 PI)
8180 11:13:35.707973 u2DelayCellOfst[4]=10 cells (3 PI)
8181 11:13:35.710889 u2DelayCellOfst[5]=0 cells (0 PI)
8182 11:13:35.714793 u2DelayCellOfst[6]=17 cells (5 PI)
8183 11:13:35.717706 u2DelayCellOfst[7]=20 cells (6 PI)
8184 11:13:35.721303 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8185 11:13:35.724283 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8186 11:13:35.728153 == TX Byte 1 ==
8187 11:13:35.728233 u2DelayCellOfst[8]=3 cells (1 PI)
8188 11:13:35.731298 u2DelayCellOfst[9]=0 cells (0 PI)
8189 11:13:35.734579 u2DelayCellOfst[10]=6 cells (2 PI)
8190 11:13:35.737806 u2DelayCellOfst[11]=3 cells (1 PI)
8191 11:13:35.741046 u2DelayCellOfst[12]=10 cells (3 PI)
8192 11:13:35.744281 u2DelayCellOfst[13]=10 cells (3 PI)
8193 11:13:35.747910 u2DelayCellOfst[14]=17 cells (5 PI)
8194 11:13:35.751003 u2DelayCellOfst[15]=10 cells (3 PI)
8195 11:13:35.754275 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8196 11:13:35.761288 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8197 11:13:35.761370 DramC Write-DBI on
8198 11:13:35.761440 ==
8199 11:13:35.764511 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 11:13:35.767687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 11:13:35.767765 ==
8202 11:13:35.770927
8203 11:13:35.770998
8204 11:13:35.771059 TX Vref Scan disable
8205 11:13:35.774120 == TX Byte 0 ==
8206 11:13:35.777346 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8207 11:13:35.780972 == TX Byte 1 ==
8208 11:13:35.784285 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8209 11:13:35.787487 DramC Write-DBI off
8210 11:13:35.787570
8211 11:13:35.787637 [DATLAT]
8212 11:13:35.787699 Freq=1600, CH0 RK1
8213 11:13:35.787759
8214 11:13:35.791227 DATLAT Default: 0xf
8215 11:13:35.791379 0, 0xFFFF, sum = 0
8216 11:13:35.794337 1, 0xFFFF, sum = 0
8217 11:13:35.797459 2, 0xFFFF, sum = 0
8218 11:13:35.797585 3, 0xFFFF, sum = 0
8219 11:13:35.800981 4, 0xFFFF, sum = 0
8220 11:13:35.801067 5, 0xFFFF, sum = 0
8221 11:13:35.804154 6, 0xFFFF, sum = 0
8222 11:13:35.804248 7, 0xFFFF, sum = 0
8223 11:13:35.807603 8, 0xFFFF, sum = 0
8224 11:13:35.807688 9, 0xFFFF, sum = 0
8225 11:13:35.810768 10, 0xFFFF, sum = 0
8226 11:13:35.810853 11, 0xFFFF, sum = 0
8227 11:13:35.814548 12, 0xFFFF, sum = 0
8228 11:13:35.814633 13, 0xFFFF, sum = 0
8229 11:13:35.817544 14, 0x0, sum = 1
8230 11:13:35.817629 15, 0x0, sum = 2
8231 11:13:35.820685 16, 0x0, sum = 3
8232 11:13:35.820770 17, 0x0, sum = 4
8233 11:13:35.823783 best_step = 15
8234 11:13:35.823866
8235 11:13:35.823933 ==
8236 11:13:35.827246 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 11:13:35.830925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 11:13:35.831003 ==
8239 11:13:35.834003 RX Vref Scan: 0
8240 11:13:35.834076
8241 11:13:35.834141 RX Vref 0 -> 0, step: 1
8242 11:13:35.834201
8243 11:13:35.837203 RX Delay 19 -> 252, step: 4
8244 11:13:35.840388 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8245 11:13:35.847488 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8246 11:13:35.850474 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8247 11:13:35.854136 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8248 11:13:35.857126 iDelay=191, Bit 4, Center 138 (87 ~ 190) 104
8249 11:13:35.860348 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8250 11:13:35.867460 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8251 11:13:35.870673 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8252 11:13:35.873775 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8253 11:13:35.876992 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8254 11:13:35.880779 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8255 11:13:35.887379 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8256 11:13:35.890651 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8257 11:13:35.893660 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8258 11:13:35.896871 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8259 11:13:35.900656 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8260 11:13:35.903963 ==
8261 11:13:35.904065 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 11:13:35.910276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 11:13:35.910361 ==
8264 11:13:35.910427 DQS Delay:
8265 11:13:35.913459 DQS0 = 0, DQS1 = 0
8266 11:13:35.913541 DQM Delay:
8267 11:13:35.917000 DQM0 = 134, DQM1 = 127
8268 11:13:35.917082 DQ Delay:
8269 11:13:35.920596 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8270 11:13:35.923556 DQ4 =138, DQ5 =124, DQ6 =138, DQ7 =142
8271 11:13:35.927310 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8272 11:13:35.930423 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8273 11:13:35.930535
8274 11:13:35.930628
8275 11:13:35.930726
8276 11:13:35.933602 [DramC_TX_OE_Calibration] TA2
8277 11:13:35.937152 Original DQ_B0 (3 6) =30, OEN = 27
8278 11:13:35.940739 Original DQ_B1 (3 6) =30, OEN = 27
8279 11:13:35.943747 24, 0x0, End_B0=24 End_B1=24
8280 11:13:35.946966 25, 0x0, End_B0=25 End_B1=25
8281 11:13:35.947070 26, 0x0, End_B0=26 End_B1=26
8282 11:13:35.950341 27, 0x0, End_B0=27 End_B1=27
8283 11:13:35.953530 28, 0x0, End_B0=28 End_B1=28
8284 11:13:35.957227 29, 0x0, End_B0=29 End_B1=29
8285 11:13:35.957334 30, 0x0, End_B0=30 End_B1=30
8286 11:13:35.960050 31, 0x4545, End_B0=30 End_B1=30
8287 11:13:35.963365 Byte0 end_step=30 best_step=27
8288 11:13:35.967118 Byte1 end_step=30 best_step=27
8289 11:13:35.970283 Byte0 TX OE(2T, 0.5T) = (3, 3)
8290 11:13:35.973633 Byte1 TX OE(2T, 0.5T) = (3, 3)
8291 11:13:35.973707
8292 11:13:35.973770
8293 11:13:35.980057 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8294 11:13:35.983306 CH0 RK1: MR19=303, MR18=1F07
8295 11:13:35.990292 CH0_RK1: MR19=0x303, MR18=0x1F07, DQSOSC=394, MR23=63, INC=23, DEC=15
8296 11:13:35.993495 [RxdqsGatingPostProcess] freq 1600
8297 11:13:35.997299 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8298 11:13:36.000531 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 11:13:36.003700 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 11:13:36.006871 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 11:13:36.010037 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 11:13:36.013833 best DQS0 dly(2T, 0.5T) = (1, 1)
8303 11:13:36.016801 best DQS1 dly(2T, 0.5T) = (1, 1)
8304 11:13:36.019945 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8305 11:13:36.023576 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8306 11:13:36.026546 Pre-setting of DQS Precalculation
8307 11:13:36.030159 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8308 11:13:36.030233 ==
8309 11:13:36.033310 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 11:13:36.037159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 11:13:36.040227 ==
8312 11:13:36.043338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 11:13:36.046925 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 11:13:36.053396 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 11:13:36.056655 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 11:13:36.067234 [CA 0] Center 41 (11~71) winsize 61
8317 11:13:36.070447 [CA 1] Center 41 (12~71) winsize 60
8318 11:13:36.073690 [CA 2] Center 38 (9~68) winsize 60
8319 11:13:36.076943 [CA 3] Center 37 (8~66) winsize 59
8320 11:13:36.080244 [CA 4] Center 38 (9~67) winsize 59
8321 11:13:36.083507 [CA 5] Center 36 (7~66) winsize 60
8322 11:13:36.083582
8323 11:13:36.087207 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8324 11:13:36.087307
8325 11:13:36.090481 [CATrainingPosCal] consider 1 rank data
8326 11:13:36.093638 u2DelayCellTimex100 = 285/100 ps
8327 11:13:36.097348 CA0 delay=41 (11~71),Diff = 5 PI (17 cell)
8328 11:13:36.103728 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8329 11:13:36.106943 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8330 11:13:36.110185 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8331 11:13:36.113519 CA4 delay=38 (9~67),Diff = 2 PI (6 cell)
8332 11:13:36.117250 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8333 11:13:36.117348
8334 11:13:36.120434 CA PerBit enable=1, Macro0, CA PI delay=36
8335 11:13:36.120530
8336 11:13:36.123461 [CBTSetCACLKResult] CA Dly = 36
8337 11:13:36.127195 CS Dly: 10 (0~41)
8338 11:13:36.130159 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 11:13:36.133735 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 11:13:36.133844 ==
8341 11:13:36.136769 Dram Type= 6, Freq= 0, CH_1, rank 1
8342 11:13:36.139970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 11:13:36.143196 ==
8344 11:13:36.146942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8345 11:13:36.149938 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8346 11:13:36.157011 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8347 11:13:36.160084 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8348 11:13:36.170673 [CA 0] Center 42 (13~72) winsize 60
8349 11:13:36.173840 [CA 1] Center 42 (13~72) winsize 60
8350 11:13:36.177146 [CA 2] Center 39 (10~69) winsize 60
8351 11:13:36.180423 [CA 3] Center 38 (9~68) winsize 60
8352 11:13:36.183710 [CA 4] Center 39 (9~69) winsize 61
8353 11:13:36.186861 [CA 5] Center 38 (9~68) winsize 60
8354 11:13:36.186970
8355 11:13:36.190798 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8356 11:13:36.190902
8357 11:13:36.193974 [CATrainingPosCal] consider 2 rank data
8358 11:13:36.197096 u2DelayCellTimex100 = 285/100 ps
8359 11:13:36.200136 CA0 delay=42 (13~71),Diff = 5 PI (17 cell)
8360 11:13:36.207239 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8361 11:13:36.210449 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8362 11:13:36.213620 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8363 11:13:36.216875 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8364 11:13:36.219997 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8365 11:13:36.220070
8366 11:13:36.223790 CA PerBit enable=1, Macro0, CA PI delay=37
8367 11:13:36.223865
8368 11:13:36.226933 [CBTSetCACLKResult] CA Dly = 37
8369 11:13:36.230080 CS Dly: 11 (0~44)
8370 11:13:36.233623 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8371 11:13:36.236754 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8372 11:13:36.236854
8373 11:13:36.240323 ----->DramcWriteLeveling(PI) begin...
8374 11:13:36.240404 ==
8375 11:13:36.243358 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 11:13:36.250278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 11:13:36.250382 ==
8378 11:13:36.253374 Write leveling (Byte 0): 26 => 26
8379 11:13:36.253473 Write leveling (Byte 1): 28 => 28
8380 11:13:36.256457 DramcWriteLeveling(PI) end<-----
8381 11:13:36.256528
8382 11:13:36.260082 ==
8383 11:13:36.260186 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 11:13:36.266843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 11:13:36.266952 ==
8386 11:13:36.269811 [Gating] SW mode calibration
8387 11:13:36.276572 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8388 11:13:36.279804 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8389 11:13:36.286882 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 11:13:36.290192 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 11:13:36.293370 1 4 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8392 11:13:36.300329 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8393 11:13:36.303535 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 11:13:36.306554 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 11:13:36.313569 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 11:13:36.316667 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 11:13:36.319941 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 11:13:36.323112 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 11:13:36.330198 1 5 8 | B1->B0 | 3434 3333 | 0 0 | (1 0) (0 1)
8400 11:13:36.333287 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8401 11:13:36.336422 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 11:13:36.343499 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 11:13:36.346531 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 11:13:36.350143 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 11:13:36.356399 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 11:13:36.359639 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 11:13:36.363296 1 6 8 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8408 11:13:36.369927 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8409 11:13:36.372942 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 11:13:36.376072 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 11:13:36.382687 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 11:13:36.386501 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 11:13:36.389709 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 11:13:36.396220 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 11:13:36.399445 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8416 11:13:36.402659 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8417 11:13:36.409477 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 11:13:36.412491 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 11:13:36.415534 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 11:13:36.422633 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 11:13:36.425771 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 11:13:36.429082 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 11:13:36.435575 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 11:13:36.438675 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 11:13:36.442509 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 11:13:36.449149 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 11:13:36.452270 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 11:13:36.455911 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 11:13:36.462502 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 11:13:36.465778 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 11:13:36.469109 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 11:13:36.475747 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8433 11:13:36.478910 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 11:13:36.481971 Total UI for P1: 0, mck2ui 16
8435 11:13:36.485445 best dqsien dly found for B0: ( 1, 9, 12)
8436 11:13:36.489323 Total UI for P1: 0, mck2ui 16
8437 11:13:36.492556 best dqsien dly found for B1: ( 1, 9, 12)
8438 11:13:36.495516 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8439 11:13:36.498913 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8440 11:13:36.498997
8441 11:13:36.502080 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8442 11:13:36.505296 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8443 11:13:36.509164 [Gating] SW calibration Done
8444 11:13:36.509248 ==
8445 11:13:36.512347 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 11:13:36.515433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 11:13:36.515517 ==
8448 11:13:36.519107 RX Vref Scan: 0
8449 11:13:36.519223
8450 11:13:36.522305 RX Vref 0 -> 0, step: 1
8451 11:13:36.522420
8452 11:13:36.522517 RX Delay 0 -> 252, step: 8
8453 11:13:36.528723 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8454 11:13:36.531892 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8455 11:13:36.535250 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8456 11:13:36.538587 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8457 11:13:36.541804 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8458 11:13:36.548946 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8459 11:13:36.552117 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8460 11:13:36.555086 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8461 11:13:36.558734 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8462 11:13:36.562267 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8463 11:13:36.568712 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8464 11:13:36.571989 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8465 11:13:36.575098 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8466 11:13:36.578962 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8467 11:13:36.582080 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8468 11:13:36.588492 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8469 11:13:36.588571 ==
8470 11:13:36.592194 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 11:13:36.595046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 11:13:36.595146 ==
8473 11:13:36.595237 DQS Delay:
8474 11:13:36.598965 DQS0 = 0, DQS1 = 0
8475 11:13:36.599071 DQM Delay:
8476 11:13:36.602071 DQM0 = 136, DQM1 = 132
8477 11:13:36.602145 DQ Delay:
8478 11:13:36.605305 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8479 11:13:36.608562 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8480 11:13:36.611689 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8481 11:13:36.615549 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8482 11:13:36.615656
8483 11:13:36.615746
8484 11:13:36.618668 ==
8485 11:13:36.621662 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 11:13:36.625357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 11:13:36.625459 ==
8488 11:13:36.625552
8489 11:13:36.625639
8490 11:13:36.628679 TX Vref Scan disable
8491 11:13:36.628774 == TX Byte 0 ==
8492 11:13:36.631947 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8493 11:13:36.638911 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8494 11:13:36.639009 == TX Byte 1 ==
8495 11:13:36.642134 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8496 11:13:36.648518 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8497 11:13:36.648601 ==
8498 11:13:36.651810 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 11:13:36.654900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 11:13:36.654997 ==
8501 11:13:36.667622
8502 11:13:36.671417 TX Vref early break, caculate TX vref
8503 11:13:36.674296 TX Vref=16, minBit 1, minWin=22, winSum=376
8504 11:13:36.677514 TX Vref=18, minBit 1, minWin=23, winSum=386
8505 11:13:36.681241 TX Vref=20, minBit 1, minWin=23, winSum=394
8506 11:13:36.684426 TX Vref=22, minBit 9, minWin=24, winSum=408
8507 11:13:36.687515 TX Vref=24, minBit 0, minWin=24, winSum=414
8508 11:13:36.694215 TX Vref=26, minBit 1, minWin=25, winSum=427
8509 11:13:36.697683 TX Vref=28, minBit 0, minWin=25, winSum=424
8510 11:13:36.701209 TX Vref=30, minBit 0, minWin=25, winSum=417
8511 11:13:36.704231 TX Vref=32, minBit 0, minWin=24, winSum=409
8512 11:13:36.708158 TX Vref=34, minBit 0, minWin=24, winSum=403
8513 11:13:36.714567 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 26
8514 11:13:36.714645
8515 11:13:36.717682 Final TX Range 0 Vref 26
8516 11:13:36.717783
8517 11:13:36.717872 ==
8518 11:13:36.721053 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 11:13:36.724724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 11:13:36.724801 ==
8521 11:13:36.724866
8522 11:13:36.724946
8523 11:13:36.727947 TX Vref Scan disable
8524 11:13:36.734325 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8525 11:13:36.734403 == TX Byte 0 ==
8526 11:13:36.738094 u2DelayCellOfst[0]=17 cells (5 PI)
8527 11:13:36.741335 u2DelayCellOfst[1]=13 cells (4 PI)
8528 11:13:36.744485 u2DelayCellOfst[2]=0 cells (0 PI)
8529 11:13:36.747650 u2DelayCellOfst[3]=6 cells (2 PI)
8530 11:13:36.751524 u2DelayCellOfst[4]=10 cells (3 PI)
8531 11:13:36.754195 u2DelayCellOfst[5]=20 cells (6 PI)
8532 11:13:36.754266 u2DelayCellOfst[6]=20 cells (6 PI)
8533 11:13:36.758025 u2DelayCellOfst[7]=10 cells (3 PI)
8534 11:13:36.764360 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8535 11:13:36.768017 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8536 11:13:36.768089 == TX Byte 1 ==
8537 11:13:36.770996 u2DelayCellOfst[8]=0 cells (0 PI)
8538 11:13:36.774427 u2DelayCellOfst[9]=3 cells (1 PI)
8539 11:13:36.778269 u2DelayCellOfst[10]=13 cells (4 PI)
8540 11:13:36.781273 u2DelayCellOfst[11]=3 cells (1 PI)
8541 11:13:36.784181 u2DelayCellOfst[12]=13 cells (4 PI)
8542 11:13:36.787979 u2DelayCellOfst[13]=13 cells (4 PI)
8543 11:13:36.791172 u2DelayCellOfst[14]=17 cells (5 PI)
8544 11:13:36.794297 u2DelayCellOfst[15]=17 cells (5 PI)
8545 11:13:36.798081 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8546 11:13:36.800975 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8547 11:13:36.804108 DramC Write-DBI on
8548 11:13:36.804184 ==
8549 11:13:36.807812 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 11:13:36.811243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 11:13:36.811351 ==
8552 11:13:36.811438
8553 11:13:36.811499
8554 11:13:36.814386 TX Vref Scan disable
8555 11:13:36.817595 == TX Byte 0 ==
8556 11:13:36.820815 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8557 11:13:36.824057 == TX Byte 1 ==
8558 11:13:36.827923 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8559 11:13:36.828025 DramC Write-DBI off
8560 11:13:36.828097
8561 11:13:36.831139 [DATLAT]
8562 11:13:36.831237 Freq=1600, CH1 RK0
8563 11:13:36.831391
8564 11:13:36.834254 DATLAT Default: 0xf
8565 11:13:36.834328 0, 0xFFFF, sum = 0
8566 11:13:36.837441 1, 0xFFFF, sum = 0
8567 11:13:36.837541 2, 0xFFFF, sum = 0
8568 11:13:36.840629 3, 0xFFFF, sum = 0
8569 11:13:36.840729 4, 0xFFFF, sum = 0
8570 11:13:36.843920 5, 0xFFFF, sum = 0
8571 11:13:36.843990 6, 0xFFFF, sum = 0
8572 11:13:36.847835 7, 0xFFFF, sum = 0
8573 11:13:36.851062 8, 0xFFFF, sum = 0
8574 11:13:36.851164 9, 0xFFFF, sum = 0
8575 11:13:36.854247 10, 0xFFFF, sum = 0
8576 11:13:36.854350 11, 0xFFFF, sum = 0
8577 11:13:36.857554 12, 0xFFFF, sum = 0
8578 11:13:36.857660 13, 0xFFFF, sum = 0
8579 11:13:36.860905 14, 0x0, sum = 1
8580 11:13:36.861004 15, 0x0, sum = 2
8581 11:13:36.864007 16, 0x0, sum = 3
8582 11:13:36.864089 17, 0x0, sum = 4
8583 11:13:36.864157 best_step = 15
8584 11:13:36.867246
8585 11:13:36.867390 ==
8586 11:13:36.870566 Dram Type= 6, Freq= 0, CH_1, rank 0
8587 11:13:36.873724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8588 11:13:36.873795 ==
8589 11:13:36.873900 RX Vref Scan: 1
8590 11:13:36.873961
8591 11:13:36.877322 Set Vref Range= 24 -> 127
8592 11:13:36.877390
8593 11:13:36.880774 RX Vref 24 -> 127, step: 1
8594 11:13:36.880885
8595 11:13:36.884198 RX Delay 27 -> 252, step: 4
8596 11:13:36.884270
8597 11:13:36.887218 Set Vref, RX VrefLevel [Byte0]: 24
8598 11:13:36.890301 [Byte1]: 24
8599 11:13:36.890400
8600 11:13:36.893805 Set Vref, RX VrefLevel [Byte0]: 25
8601 11:13:36.897488 [Byte1]: 25
8602 11:13:36.897564
8603 11:13:36.900491 Set Vref, RX VrefLevel [Byte0]: 26
8604 11:13:36.903458 [Byte1]: 26
8605 11:13:36.907082
8606 11:13:36.907181 Set Vref, RX VrefLevel [Byte0]: 27
8607 11:13:36.910521 [Byte1]: 27
8608 11:13:36.915105
8609 11:13:36.915208 Set Vref, RX VrefLevel [Byte0]: 28
8610 11:13:36.918142 [Byte1]: 28
8611 11:13:36.922368
8612 11:13:36.922442 Set Vref, RX VrefLevel [Byte0]: 29
8613 11:13:36.925600 [Byte1]: 29
8614 11:13:36.930093
8615 11:13:36.930193 Set Vref, RX VrefLevel [Byte0]: 30
8616 11:13:36.933304 [Byte1]: 30
8617 11:13:36.937724
8618 11:13:36.937824 Set Vref, RX VrefLevel [Byte0]: 31
8619 11:13:36.940926 [Byte1]: 31
8620 11:13:36.944660
8621 11:13:36.944732 Set Vref, RX VrefLevel [Byte0]: 32
8622 11:13:36.948554 [Byte1]: 32
8623 11:13:36.952374
8624 11:13:36.952446 Set Vref, RX VrefLevel [Byte0]: 33
8625 11:13:36.955592 [Byte1]: 33
8626 11:13:36.960103
8627 11:13:36.960174 Set Vref, RX VrefLevel [Byte0]: 34
8628 11:13:36.963391 [Byte1]: 34
8629 11:13:36.967815
8630 11:13:36.967881 Set Vref, RX VrefLevel [Byte0]: 35
8631 11:13:36.971034 [Byte1]: 35
8632 11:13:36.974947
8633 11:13:36.975018 Set Vref, RX VrefLevel [Byte0]: 36
8634 11:13:36.978164 [Byte1]: 36
8635 11:13:36.982558
8636 11:13:36.982624 Set Vref, RX VrefLevel [Byte0]: 37
8637 11:13:36.985692 [Byte1]: 37
8638 11:13:36.990529
8639 11:13:36.990636 Set Vref, RX VrefLevel [Byte0]: 38
8640 11:13:36.993592 [Byte1]: 38
8641 11:13:36.997545
8642 11:13:36.997645 Set Vref, RX VrefLevel [Byte0]: 39
8643 11:13:37.000936 [Byte1]: 39
8644 11:13:37.005414
8645 11:13:37.005496 Set Vref, RX VrefLevel [Byte0]: 40
8646 11:13:37.008601 [Byte1]: 40
8647 11:13:37.012586
8648 11:13:37.012668 Set Vref, RX VrefLevel [Byte0]: 41
8649 11:13:37.016308 [Byte1]: 41
8650 11:13:37.020546
8651 11:13:37.020645 Set Vref, RX VrefLevel [Byte0]: 42
8652 11:13:37.023491 [Byte1]: 42
8653 11:13:37.027596
8654 11:13:37.027677 Set Vref, RX VrefLevel [Byte0]: 43
8655 11:13:37.031284 [Byte1]: 43
8656 11:13:37.035138
8657 11:13:37.035220 Set Vref, RX VrefLevel [Byte0]: 44
8658 11:13:37.038961 [Byte1]: 44
8659 11:13:37.042624
8660 11:13:37.042706 Set Vref, RX VrefLevel [Byte0]: 45
8661 11:13:37.046630 [Byte1]: 45
8662 11:13:37.050442
8663 11:13:37.050551 Set Vref, RX VrefLevel [Byte0]: 46
8664 11:13:37.053563 [Byte1]: 46
8665 11:13:37.058014
8666 11:13:37.058095 Set Vref, RX VrefLevel [Byte0]: 47
8667 11:13:37.061174 [Byte1]: 47
8668 11:13:37.065760
8669 11:13:37.065842 Set Vref, RX VrefLevel [Byte0]: 48
8670 11:13:37.068906 [Byte1]: 48
8671 11:13:37.073280
8672 11:13:37.073361 Set Vref, RX VrefLevel [Byte0]: 49
8673 11:13:37.076415 [Byte1]: 49
8674 11:13:37.080287
8675 11:13:37.080368 Set Vref, RX VrefLevel [Byte0]: 50
8676 11:13:37.084046 [Byte1]: 50
8677 11:13:37.088299
8678 11:13:37.088381 Set Vref, RX VrefLevel [Byte0]: 51
8679 11:13:37.091216 [Byte1]: 51
8680 11:13:37.095494
8681 11:13:37.095576 Set Vref, RX VrefLevel [Byte0]: 52
8682 11:13:37.099215 [Byte1]: 52
8683 11:13:37.103410
8684 11:13:37.103492 Set Vref, RX VrefLevel [Byte0]: 53
8685 11:13:37.106304 [Byte1]: 53
8686 11:13:37.110647
8687 11:13:37.110729 Set Vref, RX VrefLevel [Byte0]: 54
8688 11:13:37.113844 [Byte1]: 54
8689 11:13:37.118077
8690 11:13:37.118159 Set Vref, RX VrefLevel [Byte0]: 55
8691 11:13:37.121647 [Byte1]: 55
8692 11:13:37.125724
8693 11:13:37.125806 Set Vref, RX VrefLevel [Byte0]: 56
8694 11:13:37.128751 [Byte1]: 56
8695 11:13:37.133503
8696 11:13:37.133585 Set Vref, RX VrefLevel [Byte0]: 57
8697 11:13:37.136779 [Byte1]: 57
8698 11:13:37.140594
8699 11:13:37.140676 Set Vref, RX VrefLevel [Byte0]: 58
8700 11:13:37.144395 [Byte1]: 58
8701 11:13:37.148079
8702 11:13:37.148187 Set Vref, RX VrefLevel [Byte0]: 59
8703 11:13:37.151471 [Byte1]: 59
8704 11:13:37.156135
8705 11:13:37.156219 Set Vref, RX VrefLevel [Byte0]: 60
8706 11:13:37.159271 [Byte1]: 60
8707 11:13:37.163655
8708 11:13:37.163737 Set Vref, RX VrefLevel [Byte0]: 61
8709 11:13:37.166899 [Byte1]: 61
8710 11:13:37.171288
8711 11:13:37.171394 Set Vref, RX VrefLevel [Byte0]: 62
8712 11:13:37.173953 [Byte1]: 62
8713 11:13:37.178463
8714 11:13:37.178545 Set Vref, RX VrefLevel [Byte0]: 63
8715 11:13:37.181681 [Byte1]: 63
8716 11:13:37.186264
8717 11:13:37.186349 Set Vref, RX VrefLevel [Byte0]: 64
8718 11:13:37.189457 [Byte1]: 64
8719 11:13:37.193383
8720 11:13:37.193465 Set Vref, RX VrefLevel [Byte0]: 65
8721 11:13:37.196583 [Byte1]: 65
8722 11:13:37.201367
8723 11:13:37.201450 Set Vref, RX VrefLevel [Byte0]: 66
8724 11:13:37.204226 [Byte1]: 66
8725 11:13:37.208670
8726 11:13:37.208751 Set Vref, RX VrefLevel [Byte0]: 67
8727 11:13:37.212189 [Byte1]: 67
8728 11:13:37.216435
8729 11:13:37.216518 Set Vref, RX VrefLevel [Byte0]: 68
8730 11:13:37.219251 [Byte1]: 68
8731 11:13:37.223782
8732 11:13:37.223864 Set Vref, RX VrefLevel [Byte0]: 69
8733 11:13:37.226801 [Byte1]: 69
8734 11:13:37.231012
8735 11:13:37.231095 Set Vref, RX VrefLevel [Byte0]: 70
8736 11:13:37.234365 [Byte1]: 70
8737 11:13:37.238680
8738 11:13:37.238792 Set Vref, RX VrefLevel [Byte0]: 71
8739 11:13:37.241719 [Byte1]: 71
8740 11:13:37.246017
8741 11:13:37.246100 Set Vref, RX VrefLevel [Byte0]: 72
8742 11:13:37.249639 [Byte1]: 72
8743 11:13:37.253993
8744 11:13:37.254075 Set Vref, RX VrefLevel [Byte0]: 73
8745 11:13:37.257133 [Byte1]: 73
8746 11:13:37.261605
8747 11:13:37.261689 Set Vref, RX VrefLevel [Byte0]: 74
8748 11:13:37.264893 [Byte1]: 74
8749 11:13:37.268734
8750 11:13:37.268816 Set Vref, RX VrefLevel [Byte0]: 75
8751 11:13:37.272119 [Byte1]: 75
8752 11:13:37.276609
8753 11:13:37.276691 Set Vref, RX VrefLevel [Byte0]: 76
8754 11:13:37.279785 [Byte1]: 76
8755 11:13:37.284218
8756 11:13:37.284300 Set Vref, RX VrefLevel [Byte0]: 77
8757 11:13:37.287498 [Byte1]: 77
8758 11:13:37.291253
8759 11:13:37.291358 Set Vref, RX VrefLevel [Byte0]: 78
8760 11:13:37.294468 [Byte1]: 78
8761 11:13:37.298963
8762 11:13:37.299045 Final RX Vref Byte 0 = 57 to rank0
8763 11:13:37.302221 Final RX Vref Byte 1 = 55 to rank0
8764 11:13:37.305493 Final RX Vref Byte 0 = 57 to rank1
8765 11:13:37.309216 Final RX Vref Byte 1 = 55 to rank1==
8766 11:13:37.312069 Dram Type= 6, Freq= 0, CH_1, rank 0
8767 11:13:37.318626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 11:13:37.318714 ==
8769 11:13:37.318782 DQS Delay:
8770 11:13:37.322267 DQS0 = 0, DQS1 = 0
8771 11:13:37.322351 DQM Delay:
8772 11:13:37.322417 DQM0 = 134, DQM1 = 131
8773 11:13:37.325267 DQ Delay:
8774 11:13:37.329031 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8775 11:13:37.332081 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8776 11:13:37.335714 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8777 11:13:37.338608 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8778 11:13:37.338692
8779 11:13:37.338758
8780 11:13:37.338819
8781 11:13:37.342074 [DramC_TX_OE_Calibration] TA2
8782 11:13:37.345499 Original DQ_B0 (3 6) =30, OEN = 27
8783 11:13:37.348455 Original DQ_B1 (3 6) =30, OEN = 27
8784 11:13:37.351904 24, 0x0, End_B0=24 End_B1=24
8785 11:13:37.351995 25, 0x0, End_B0=25 End_B1=25
8786 11:13:37.355058 26, 0x0, End_B0=26 End_B1=26
8787 11:13:37.358861 27, 0x0, End_B0=27 End_B1=27
8788 11:13:37.361743 28, 0x0, End_B0=28 End_B1=28
8789 11:13:37.365518 29, 0x0, End_B0=29 End_B1=29
8790 11:13:37.365602 30, 0x0, End_B0=30 End_B1=30
8791 11:13:37.368633 31, 0x5151, End_B0=30 End_B1=30
8792 11:13:37.371906 Byte0 end_step=30 best_step=27
8793 11:13:37.375196 Byte1 end_step=30 best_step=27
8794 11:13:37.378415 Byte0 TX OE(2T, 0.5T) = (3, 3)
8795 11:13:37.381632 Byte1 TX OE(2T, 0.5T) = (3, 3)
8796 11:13:37.381716
8797 11:13:37.381781
8798 11:13:37.388755 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8799 11:13:37.392028 CH1 RK0: MR19=303, MR18=1624
8800 11:13:37.398487 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8801 11:13:37.398571
8802 11:13:37.401606 ----->DramcWriteLeveling(PI) begin...
8803 11:13:37.401691 ==
8804 11:13:37.404856 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 11:13:37.408622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 11:13:37.408718 ==
8807 11:13:37.411817 Write leveling (Byte 0): 27 => 27
8808 11:13:37.415026 Write leveling (Byte 1): 29 => 29
8809 11:13:37.417955 DramcWriteLeveling(PI) end<-----
8810 11:13:37.418044
8811 11:13:37.418110 ==
8812 11:13:37.421568 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 11:13:37.425114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 11:13:37.425201 ==
8815 11:13:37.428172 [Gating] SW mode calibration
8816 11:13:37.434985 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8817 11:13:37.441269 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8818 11:13:37.444458 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 11:13:37.451450 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 11:13:37.454892 1 4 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8821 11:13:37.457890 1 4 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8822 11:13:37.464441 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 11:13:37.468132 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 11:13:37.471258 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 11:13:37.474438 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 11:13:37.481488 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 11:13:37.484649 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8828 11:13:37.487940 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (1 0) (1 0)
8829 11:13:37.494486 1 5 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 0)
8830 11:13:37.498415 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 11:13:37.501493 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 11:13:37.507981 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 11:13:37.511227 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 11:13:37.514472 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 11:13:37.521015 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8836 11:13:37.524225 1 6 8 | B1->B0 | 3131 2323 | 1 0 | (0 0) (0 0)
8837 11:13:37.527730 1 6 12 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (1 1)
8838 11:13:37.534308 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 11:13:37.537900 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 11:13:37.540926 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 11:13:37.547913 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 11:13:37.551170 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 11:13:37.554247 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8844 11:13:37.560711 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8845 11:13:37.564137 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8846 11:13:37.567474 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 11:13:37.574062 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 11:13:37.577553 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 11:13:37.581145 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 11:13:37.587488 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 11:13:37.590625 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 11:13:37.593910 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 11:13:37.601165 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 11:13:37.604435 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 11:13:37.607613 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 11:13:37.610951 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 11:13:37.617314 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:13:37.620484 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 11:13:37.624402 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8860 11:13:37.630672 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8861 11:13:37.633823 Total UI for P1: 0, mck2ui 16
8862 11:13:37.637357 best dqsien dly found for B1: ( 1, 9, 4)
8863 11:13:37.641040 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8864 11:13:37.643746 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 11:13:37.647270 Total UI for P1: 0, mck2ui 16
8866 11:13:37.650930 best dqsien dly found for B0: ( 1, 9, 10)
8867 11:13:37.654125 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8868 11:13:37.657638 best DQS1 dly(MCK, UI, PI) = (1, 9, 4)
8869 11:13:37.658132
8870 11:13:37.664343 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8871 11:13:37.667568 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 4)
8872 11:13:37.670712 [Gating] SW calibration Done
8873 11:13:37.671159 ==
8874 11:13:37.674353 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 11:13:37.677964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 11:13:37.678444 ==
8877 11:13:37.678791 RX Vref Scan: 0
8878 11:13:37.679128
8879 11:13:37.680948 RX Vref 0 -> 0, step: 1
8880 11:13:37.681370
8881 11:13:37.684652 RX Delay 0 -> 252, step: 8
8882 11:13:37.687387 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8883 11:13:37.691120 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8884 11:13:37.697471 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8885 11:13:37.700733 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8886 11:13:37.704608 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8887 11:13:37.707851 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8888 11:13:37.711024 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8889 11:13:37.714218 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8890 11:13:37.720518 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8891 11:13:37.723874 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8892 11:13:37.727109 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8893 11:13:37.730849 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8894 11:13:37.737363 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8895 11:13:37.740577 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8896 11:13:37.744206 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8897 11:13:37.747070 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8898 11:13:37.747539 ==
8899 11:13:37.750415 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 11:13:37.757374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 11:13:37.757987 ==
8902 11:13:37.758532 DQS Delay:
8903 11:13:37.758871 DQS0 = 0, DQS1 = 0
8904 11:13:37.760407 DQM Delay:
8905 11:13:37.760921 DQM0 = 136, DQM1 = 133
8906 11:13:37.763535 DQ Delay:
8907 11:13:37.767186 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8908 11:13:37.770765 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8909 11:13:37.774152 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8910 11:13:37.777252 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8911 11:13:37.777678
8912 11:13:37.778010
8913 11:13:37.778319 ==
8914 11:13:37.780495 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 11:13:37.783912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 11:13:37.784334 ==
8917 11:13:37.786998
8918 11:13:37.787454
8919 11:13:37.787813 TX Vref Scan disable
8920 11:13:37.790701 == TX Byte 0 ==
8921 11:13:37.793603 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8922 11:13:37.797401 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8923 11:13:37.800502 == TX Byte 1 ==
8924 11:13:37.803760 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8925 11:13:37.807420 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8926 11:13:37.807843 ==
8927 11:13:37.810762 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 11:13:37.816974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 11:13:37.817400 ==
8930 11:13:37.829742
8931 11:13:37.832967 TX Vref early break, caculate TX vref
8932 11:13:37.836776 TX Vref=16, minBit 1, minWin=23, winSum=384
8933 11:13:37.839931 TX Vref=18, minBit 1, minWin=23, winSum=393
8934 11:13:37.843208 TX Vref=20, minBit 0, minWin=24, winSum=403
8935 11:13:37.846367 TX Vref=22, minBit 0, minWin=25, winSum=411
8936 11:13:37.849481 TX Vref=24, minBit 0, minWin=25, winSum=415
8937 11:13:37.856392 TX Vref=26, minBit 6, minWin=25, winSum=422
8938 11:13:37.859411 TX Vref=28, minBit 0, minWin=26, winSum=425
8939 11:13:37.862794 TX Vref=30, minBit 0, minWin=26, winSum=421
8940 11:13:37.866188 TX Vref=32, minBit 0, minWin=25, winSum=410
8941 11:13:37.869358 TX Vref=34, minBit 6, minWin=24, winSum=405
8942 11:13:37.872969 TX Vref=36, minBit 0, minWin=24, winSum=396
8943 11:13:37.879815 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8944 11:13:37.880294
8945 11:13:37.882820 Final TX Range 0 Vref 28
8946 11:13:37.883294
8947 11:13:37.883718 ==
8948 11:13:37.885865 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 11:13:37.889571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 11:13:37.890169 ==
8951 11:13:37.890563
8952 11:13:37.890895
8953 11:13:37.893180 TX Vref Scan disable
8954 11:13:37.899875 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8955 11:13:37.900354 == TX Byte 0 ==
8956 11:13:37.902964 u2DelayCellOfst[0]=17 cells (5 PI)
8957 11:13:37.906158 u2DelayCellOfst[1]=10 cells (3 PI)
8958 11:13:37.909416 u2DelayCellOfst[2]=0 cells (0 PI)
8959 11:13:37.912465 u2DelayCellOfst[3]=6 cells (2 PI)
8960 11:13:37.915814 u2DelayCellOfst[4]=6 cells (2 PI)
8961 11:13:37.919648 u2DelayCellOfst[5]=17 cells (5 PI)
8962 11:13:37.922857 u2DelayCellOfst[6]=17 cells (5 PI)
8963 11:13:37.926031 u2DelayCellOfst[7]=6 cells (2 PI)
8964 11:13:37.929207 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8965 11:13:37.932415 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8966 11:13:37.936079 == TX Byte 1 ==
8967 11:13:37.939316 u2DelayCellOfst[8]=0 cells (0 PI)
8968 11:13:37.939792 u2DelayCellOfst[9]=3 cells (1 PI)
8969 11:13:37.942496 u2DelayCellOfst[10]=13 cells (4 PI)
8970 11:13:37.945743 u2DelayCellOfst[11]=3 cells (1 PI)
8971 11:13:37.948986 u2DelayCellOfst[12]=13 cells (4 PI)
8972 11:13:37.952219 u2DelayCellOfst[13]=17 cells (5 PI)
8973 11:13:37.956010 u2DelayCellOfst[14]=17 cells (5 PI)
8974 11:13:37.959269 u2DelayCellOfst[15]=17 cells (5 PI)
8975 11:13:37.962414 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8976 11:13:37.968905 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8977 11:13:37.969334 DramC Write-DBI on
8978 11:13:37.969668 ==
8979 11:13:37.972393 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 11:13:37.978741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 11:13:37.979170 ==
8982 11:13:37.979578
8983 11:13:37.979901
8984 11:13:37.980206 TX Vref Scan disable
8985 11:13:37.983039 == TX Byte 0 ==
8986 11:13:37.985953 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8987 11:13:37.989361 == TX Byte 1 ==
8988 11:13:37.993214 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8989 11:13:37.996139 DramC Write-DBI off
8990 11:13:37.996558
8991 11:13:37.996893 [DATLAT]
8992 11:13:37.997204 Freq=1600, CH1 RK1
8993 11:13:37.997510
8994 11:13:37.999836 DATLAT Default: 0xf
8995 11:13:38.000278 0, 0xFFFF, sum = 0
8996 11:13:38.003100 1, 0xFFFF, sum = 0
8997 11:13:38.003575 2, 0xFFFF, sum = 0
8998 11:13:38.006274 3, 0xFFFF, sum = 0
8999 11:13:38.009389 4, 0xFFFF, sum = 0
9000 11:13:38.009868 5, 0xFFFF, sum = 0
9001 11:13:38.013101 6, 0xFFFF, sum = 0
9002 11:13:38.013528 7, 0xFFFF, sum = 0
9003 11:13:38.016450 8, 0xFFFF, sum = 0
9004 11:13:38.016876 9, 0xFFFF, sum = 0
9005 11:13:38.019523 10, 0xFFFF, sum = 0
9006 11:13:38.019951 11, 0xFFFF, sum = 0
9007 11:13:38.022750 12, 0xFFFF, sum = 0
9008 11:13:38.023177 13, 0xFFFF, sum = 0
9009 11:13:38.025929 14, 0x0, sum = 1
9010 11:13:38.026357 15, 0x0, sum = 2
9011 11:13:38.029646 16, 0x0, sum = 3
9012 11:13:38.030073 17, 0x0, sum = 4
9013 11:13:38.032902 best_step = 15
9014 11:13:38.033320
9015 11:13:38.033655 ==
9016 11:13:38.035815 Dram Type= 6, Freq= 0, CH_1, rank 1
9017 11:13:38.039684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9018 11:13:38.040110 ==
9019 11:13:38.040448 RX Vref Scan: 0
9020 11:13:38.042859
9021 11:13:38.043278 RX Vref 0 -> 0, step: 1
9022 11:13:38.043656
9023 11:13:38.046120 RX Delay 19 -> 252, step: 4
9024 11:13:38.049294 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9025 11:13:38.056253 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9026 11:13:38.059595 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9027 11:13:38.062681 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9028 11:13:38.065608 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9029 11:13:38.068811 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9030 11:13:38.072128 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9031 11:13:38.079164 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
9032 11:13:38.082348 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9033 11:13:38.085653 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9034 11:13:38.089210 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9035 11:13:38.092124 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9036 11:13:38.099201 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9037 11:13:38.102391 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9038 11:13:38.105927 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9039 11:13:38.108843 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9040 11:13:38.109267 ==
9041 11:13:38.112109 Dram Type= 6, Freq= 0, CH_1, rank 1
9042 11:13:38.119354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9043 11:13:38.119847 ==
9044 11:13:38.120203 DQS Delay:
9045 11:13:38.122274 DQS0 = 0, DQS1 = 0
9046 11:13:38.122753 DQM Delay:
9047 11:13:38.126214 DQM0 = 133, DQM1 = 130
9048 11:13:38.126644 DQ Delay:
9049 11:13:38.129293 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9050 11:13:38.132465 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =130
9051 11:13:38.135739 DQ8 =116, DQ9 =120, DQ10 =130, DQ11 =124
9052 11:13:38.138950 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
9053 11:13:38.139447
9054 11:13:38.139884
9055 11:13:38.140247
9056 11:13:38.142636 [DramC_TX_OE_Calibration] TA2
9057 11:13:38.146078 Original DQ_B0 (3 6) =30, OEN = 27
9058 11:13:38.149174 Original DQ_B1 (3 6) =30, OEN = 27
9059 11:13:38.152442 24, 0x0, End_B0=24 End_B1=24
9060 11:13:38.152926 25, 0x0, End_B0=25 End_B1=25
9061 11:13:38.155590 26, 0x0, End_B0=26 End_B1=26
9062 11:13:38.158664 27, 0x0, End_B0=27 End_B1=27
9063 11:13:38.162646 28, 0x0, End_B0=28 End_B1=28
9064 11:13:38.165835 29, 0x0, End_B0=29 End_B1=29
9065 11:13:38.166351 30, 0x0, End_B0=30 End_B1=30
9066 11:13:38.168979 31, 0x4141, End_B0=30 End_B1=30
9067 11:13:38.172311 Byte0 end_step=30 best_step=27
9068 11:13:38.175380 Byte1 end_step=30 best_step=27
9069 11:13:38.179005 Byte0 TX OE(2T, 0.5T) = (3, 3)
9070 11:13:38.182277 Byte1 TX OE(2T, 0.5T) = (3, 3)
9071 11:13:38.182759
9072 11:13:38.183136
9073 11:13:38.188766 [DQSOSCAuto] RK1, (LSB)MR18= 0x250a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
9074 11:13:38.192325 CH1 RK1: MR19=303, MR18=250A
9075 11:13:38.198860 CH1_RK1: MR19=0x303, MR18=0x250A, DQSOSC=391, MR23=63, INC=24, DEC=16
9076 11:13:38.202334 [RxdqsGatingPostProcess] freq 1600
9077 11:13:38.205811 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9078 11:13:38.208874 best DQS0 dly(2T, 0.5T) = (1, 1)
9079 11:13:38.212020 best DQS1 dly(2T, 0.5T) = (1, 1)
9080 11:13:38.215670 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9081 11:13:38.218683 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9082 11:13:38.222092 best DQS0 dly(2T, 0.5T) = (1, 1)
9083 11:13:38.225630 best DQS1 dly(2T, 0.5T) = (1, 1)
9084 11:13:38.228730 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9085 11:13:38.231815 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9086 11:13:38.235423 Pre-setting of DQS Precalculation
9087 11:13:38.238608 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9088 11:13:38.245509 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9089 11:13:38.255217 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9090 11:13:38.255764
9091 11:13:38.256144
9092 11:13:38.256491 [Calibration Summary] 3200 Mbps
9093 11:13:38.258432 CH 0, Rank 0
9094 11:13:38.261318 SW Impedance : PASS
9095 11:13:38.261401 DUTY Scan : NO K
9096 11:13:38.265235 ZQ Calibration : PASS
9097 11:13:38.265319 Jitter Meter : NO K
9098 11:13:38.268363 CBT Training : PASS
9099 11:13:38.271639 Write leveling : PASS
9100 11:13:38.271722 RX DQS gating : PASS
9101 11:13:38.274745 RX DQ/DQS(RDDQC) : PASS
9102 11:13:38.277994 TX DQ/DQS : PASS
9103 11:13:38.278077 RX DATLAT : PASS
9104 11:13:38.281136 RX DQ/DQS(Engine): PASS
9105 11:13:38.284826 TX OE : PASS
9106 11:13:38.284909 All Pass.
9107 11:13:38.284975
9108 11:13:38.285035 CH 0, Rank 1
9109 11:13:38.288051 SW Impedance : PASS
9110 11:13:38.291246 DUTY Scan : NO K
9111 11:13:38.291334 ZQ Calibration : PASS
9112 11:13:38.294492 Jitter Meter : NO K
9113 11:13:38.298157 CBT Training : PASS
9114 11:13:38.298240 Write leveling : PASS
9115 11:13:38.301161 RX DQS gating : PASS
9116 11:13:38.304289 RX DQ/DQS(RDDQC) : PASS
9117 11:13:38.304372 TX DQ/DQS : PASS
9118 11:13:38.308047 RX DATLAT : PASS
9119 11:13:38.311144 RX DQ/DQS(Engine): PASS
9120 11:13:38.311227 TX OE : PASS
9121 11:13:38.311294 All Pass.
9122 11:13:38.311397
9123 11:13:38.314701 CH 1, Rank 0
9124 11:13:38.314783 SW Impedance : PASS
9125 11:13:38.317752 DUTY Scan : NO K
9126 11:13:38.321031 ZQ Calibration : PASS
9127 11:13:38.321113 Jitter Meter : NO K
9128 11:13:38.324847 CBT Training : PASS
9129 11:13:38.327668 Write leveling : PASS
9130 11:13:38.327751 RX DQS gating : PASS
9131 11:13:38.331146 RX DQ/DQS(RDDQC) : PASS
9132 11:13:38.334561 TX DQ/DQS : PASS
9133 11:13:38.334644 RX DATLAT : PASS
9134 11:13:38.337994 RX DQ/DQS(Engine): PASS
9135 11:13:38.341448 TX OE : PASS
9136 11:13:38.341530 All Pass.
9137 11:13:38.341597
9138 11:13:38.341658 CH 1, Rank 1
9139 11:13:38.344437 SW Impedance : PASS
9140 11:13:38.348161 DUTY Scan : NO K
9141 11:13:38.348243 ZQ Calibration : PASS
9142 11:13:38.351267 Jitter Meter : NO K
9143 11:13:38.354559 CBT Training : PASS
9144 11:13:38.354641 Write leveling : PASS
9145 11:13:38.357693 RX DQS gating : PASS
9146 11:13:38.360911 RX DQ/DQS(RDDQC) : PASS
9147 11:13:38.360994 TX DQ/DQS : PASS
9148 11:13:38.364038 RX DATLAT : PASS
9149 11:13:38.367291 RX DQ/DQS(Engine): PASS
9150 11:13:38.367410 TX OE : PASS
9151 11:13:38.367476 All Pass.
9152 11:13:38.367536
9153 11:13:38.371161 DramC Write-DBI on
9154 11:13:38.374343 PER_BANK_REFRESH: Hybrid Mode
9155 11:13:38.374432 TX_TRACKING: ON
9156 11:13:38.384566 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9157 11:13:38.390761 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9158 11:13:38.401128 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9159 11:13:38.404187 [FAST_K] Save calibration result to emmc
9160 11:13:38.408011 sync common calibartion params.
9161 11:13:38.408186 sync cbt_mode0:1, 1:1
9162 11:13:38.410637 dram_init: ddr_geometry: 2
9163 11:13:38.414369 dram_init: ddr_geometry: 2
9164 11:13:38.414572 dram_init: ddr_geometry: 2
9165 11:13:38.417376 0:dram_rank_size:100000000
9166 11:13:38.421056 1:dram_rank_size:100000000
9167 11:13:38.423953 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9168 11:13:38.427942 DFS_SHUFFLE_HW_MODE: ON
9169 11:13:38.431246 dramc_set_vcore_voltage set vcore to 725000
9170 11:13:38.434312 Read voltage for 1600, 0
9171 11:13:38.434742 Vio18 = 0
9172 11:13:38.437823 Vcore = 725000
9173 11:13:38.438249 Vdram = 0
9174 11:13:38.438589 Vddq = 0
9175 11:13:38.438903 Vmddr = 0
9176 11:13:38.440688 switch to 3200 Mbps bootup
9177 11:13:38.444135 [DramcRunTimeConfig]
9178 11:13:38.444560 PHYPLL
9179 11:13:38.447403 DPM_CONTROL_AFTERK: ON
9180 11:13:38.447852 PER_BANK_REFRESH: ON
9181 11:13:38.451063 REFRESH_OVERHEAD_REDUCTION: ON
9182 11:13:38.453821 CMD_PICG_NEW_MODE: OFF
9183 11:13:38.454248 XRTWTW_NEW_MODE: ON
9184 11:13:38.457625 XRTRTR_NEW_MODE: ON
9185 11:13:38.458048 TX_TRACKING: ON
9186 11:13:38.460797 RDSEL_TRACKING: OFF
9187 11:13:38.464063 DQS Precalculation for DVFS: ON
9188 11:13:38.464494 RX_TRACKING: OFF
9189 11:13:38.467256 HW_GATING DBG: ON
9190 11:13:38.467725 ZQCS_ENABLE_LP4: ON
9191 11:13:38.470480 RX_PICG_NEW_MODE: ON
9192 11:13:38.470904 TX_PICG_NEW_MODE: ON
9193 11:13:38.473675 ENABLE_RX_DCM_DPHY: ON
9194 11:13:38.477564 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9195 11:13:38.480661 DUMMY_READ_FOR_TRACKING: OFF
9196 11:13:38.481087 !!! SPM_CONTROL_AFTERK: OFF
9197 11:13:38.483913 !!! SPM could not control APHY
9198 11:13:38.487093 IMPEDANCE_TRACKING: ON
9199 11:13:38.487540 TEMP_SENSOR: ON
9200 11:13:38.490204 HW_SAVE_FOR_SR: OFF
9201 11:13:38.493739 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9202 11:13:38.496880 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9203 11:13:38.497309 Read ODT Tracking: ON
9204 11:13:38.500708 Refresh Rate DeBounce: ON
9205 11:13:38.503842 DFS_NO_QUEUE_FLUSH: ON
9206 11:13:38.506909 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9207 11:13:38.507492 ENABLE_DFS_RUNTIME_MRW: OFF
9208 11:13:38.510454 DDR_RESERVE_NEW_MODE: ON
9209 11:13:38.513630 MR_CBT_SWITCH_FREQ: ON
9210 11:13:38.514214 =========================
9211 11:13:38.534022 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9212 11:13:38.537021 dram_init: ddr_geometry: 2
9213 11:13:38.555427 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9214 11:13:38.558826 dram_init: dram init end (result: 0)
9215 11:13:38.565530 DRAM-K: Full calibration passed in 24482 msecs
9216 11:13:38.568561 MRC: failed to locate region type 0.
9217 11:13:38.568994 DRAM rank0 size:0x100000000,
9218 11:13:38.572424 DRAM rank1 size=0x100000000
9219 11:13:38.582042 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9220 11:13:38.589097 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9221 11:13:38.595369 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9222 11:13:38.602368 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9223 11:13:38.605585 DRAM rank0 size:0x100000000,
9224 11:13:38.608773 DRAM rank1 size=0x100000000
9225 11:13:38.609239 CBMEM:
9226 11:13:38.611839 IMD: root @ 0xfffff000 254 entries.
9227 11:13:38.615517 IMD: root @ 0xffffec00 62 entries.
9228 11:13:38.618521 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9229 11:13:38.621812 WARNING: RO_VPD is uninitialized or empty.
9230 11:13:38.628686 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9231 11:13:38.635645 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9232 11:13:38.648353 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9233 11:13:38.659438 BS: romstage times (exec / console): total (unknown) / 24012 ms
9234 11:13:38.659981
9235 11:13:38.660334
9236 11:13:38.669936 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9237 11:13:38.672958 ARM64: Exception handlers installed.
9238 11:13:38.676527 ARM64: Testing exception
9239 11:13:38.679759 ARM64: Done test exception
9240 11:13:38.680191 Enumerating buses...
9241 11:13:38.682974 Show all devs... Before device enumeration.
9242 11:13:38.686249 Root Device: enabled 1
9243 11:13:38.689364 CPU_CLUSTER: 0: enabled 1
9244 11:13:38.689796 CPU: 00: enabled 1
9245 11:13:38.692502 Compare with tree...
9246 11:13:38.692935 Root Device: enabled 1
9247 11:13:38.695861 CPU_CLUSTER: 0: enabled 1
9248 11:13:38.699600 CPU: 00: enabled 1
9249 11:13:38.700029 Root Device scanning...
9250 11:13:38.702690 scan_static_bus for Root Device
9251 11:13:38.705961 CPU_CLUSTER: 0 enabled
9252 11:13:38.709183 scan_static_bus for Root Device done
9253 11:13:38.712520 scan_bus: bus Root Device finished in 8 msecs
9254 11:13:38.712954 done
9255 11:13:38.719133 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9256 11:13:38.722770 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9257 11:13:38.729095 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9258 11:13:38.732467 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9259 11:13:38.736313 Allocating resources...
9260 11:13:38.739312 Reading resources...
9261 11:13:38.742283 Root Device read_resources bus 0 link: 0
9262 11:13:38.742754 DRAM rank0 size:0x100000000,
9263 11:13:38.745975 DRAM rank1 size=0x100000000
9264 11:13:38.749088 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9265 11:13:38.752804 CPU: 00 missing read_resources
9266 11:13:38.758973 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9267 11:13:38.762697 Root Device read_resources bus 0 link: 0 done
9268 11:13:38.763122 Done reading resources.
9269 11:13:38.769275 Show resources in subtree (Root Device)...After reading.
9270 11:13:38.772546 Root Device child on link 0 CPU_CLUSTER: 0
9271 11:13:38.775436 CPU_CLUSTER: 0 child on link 0 CPU: 00
9272 11:13:38.785743 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9273 11:13:38.786284 CPU: 00
9274 11:13:38.788956 Root Device assign_resources, bus 0 link: 0
9275 11:13:38.792210 CPU_CLUSTER: 0 missing set_resources
9276 11:13:38.798827 Root Device assign_resources, bus 0 link: 0 done
9277 11:13:38.799385 Done setting resources.
9278 11:13:38.806027 Show resources in subtree (Root Device)...After assigning values.
9279 11:13:38.809060 Root Device child on link 0 CPU_CLUSTER: 0
9280 11:13:38.812317 CPU_CLUSTER: 0 child on link 0 CPU: 00
9281 11:13:38.822475 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9282 11:13:38.822925 CPU: 00
9283 11:13:38.825455 Done allocating resources.
9284 11:13:38.828548 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9285 11:13:38.832303 Enabling resources...
9286 11:13:38.832783 done.
9287 11:13:38.838969 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9288 11:13:38.839478 Initializing devices...
9289 11:13:38.842028 Root Device init
9290 11:13:38.842512 init hardware done!
9291 11:13:38.845243 0x00000018: ctrlr->caps
9292 11:13:38.848823 52.000 MHz: ctrlr->f_max
9293 11:13:38.849357 0.400 MHz: ctrlr->f_min
9294 11:13:38.851811 0x40ff8080: ctrlr->voltages
9295 11:13:38.852315 sclk: 390625
9296 11:13:38.855131 Bus Width = 1
9297 11:13:38.855662 sclk: 390625
9298 11:13:38.858411 Bus Width = 1
9299 11:13:38.858853 Early init status = 3
9300 11:13:38.865074 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9301 11:13:38.868670 in-header: 03 fc 00 00 01 00 00 00
9302 11:13:38.871936 in-data: 00
9303 11:13:38.875145 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9304 11:13:38.879632 in-header: 03 fd 00 00 00 00 00 00
9305 11:13:38.883468 in-data:
9306 11:13:38.886366 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9307 11:13:38.890615 in-header: 03 fc 00 00 01 00 00 00
9308 11:13:38.894209 in-data: 00
9309 11:13:38.897497 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9310 11:13:38.903095 in-header: 03 fd 00 00 00 00 00 00
9311 11:13:38.906153 in-data:
9312 11:13:38.909476 [SSUSB] Setting up USB HOST controller...
9313 11:13:38.913045 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9314 11:13:38.916201 [SSUSB] phy power-on done.
9315 11:13:38.919411 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9316 11:13:38.925926 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9317 11:13:38.929688 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9318 11:13:38.935873 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9319 11:13:38.942903 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9320 11:13:38.949460 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9321 11:13:38.955972 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9322 11:13:38.962692 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9323 11:13:38.966130 SPM: binary array size = 0x9dc
9324 11:13:38.968867 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9325 11:13:38.975967 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9326 11:13:38.982339 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9327 11:13:38.985522 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9328 11:13:38.992401 configure_display: Starting display init
9329 11:13:39.026155 anx7625_power_on_init: Init interface.
9330 11:13:39.029319 anx7625_disable_pd_protocol: Disabled PD feature.
9331 11:13:39.032989 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9332 11:13:39.060754 anx7625_start_dp_work: Secure OCM version=00
9333 11:13:39.063965 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9334 11:13:39.078620 sp_tx_get_edid_block: EDID Block = 1
9335 11:13:39.181366 Extracted contents:
9336 11:13:39.184890 header: 00 ff ff ff ff ff ff 00
9337 11:13:39.187736 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9338 11:13:39.190783 version: 01 04
9339 11:13:39.194149 basic params: 95 1f 11 78 0a
9340 11:13:39.197564 chroma info: 76 90 94 55 54 90 27 21 50 54
9341 11:13:39.201074 established: 00 00 00
9342 11:13:39.207250 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9343 11:13:39.210812 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9344 11:13:39.217550 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9345 11:13:39.224362 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9346 11:13:39.230519 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9347 11:13:39.234280 extensions: 00
9348 11:13:39.234391 checksum: fb
9349 11:13:39.234475
9350 11:13:39.237327 Manufacturer: IVO Model 57d Serial Number 0
9351 11:13:39.240564 Made week 0 of 2020
9352 11:13:39.240657 EDID version: 1.4
9353 11:13:39.243780 Digital display
9354 11:13:39.247488 6 bits per primary color channel
9355 11:13:39.247583 DisplayPort interface
9356 11:13:39.250622 Maximum image size: 31 cm x 17 cm
9357 11:13:39.253881 Gamma: 220%
9358 11:13:39.253974 Check DPMS levels
9359 11:13:39.257016 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9360 11:13:39.260952 First detailed timing is preferred timing
9361 11:13:39.264004 Established timings supported:
9362 11:13:39.267006 Standard timings supported:
9363 11:13:39.267133 Detailed timings
9364 11:13:39.273667 Hex of detail: 383680a07038204018303c0035ae10000019
9365 11:13:39.277532 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9366 11:13:39.283737 0780 0798 07c8 0820 hborder 0
9367 11:13:39.287615 0438 043b 0447 0458 vborder 0
9368 11:13:39.290732 -hsync -vsync
9369 11:13:39.290877 Did detailed timing
9370 11:13:39.293852 Hex of detail: 000000000000000000000000000000000000
9371 11:13:39.296923 Manufacturer-specified data, tag 0
9372 11:13:39.304199 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9373 11:13:39.304425 ASCII string: InfoVision
9374 11:13:39.310316 Hex of detail: 000000fe00523134304e574635205248200a
9375 11:13:39.314116 ASCII string: R140NWF5 RH
9376 11:13:39.314472 Checksum
9377 11:13:39.314753 Checksum: 0xfb (valid)
9378 11:13:39.320940 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9379 11:13:39.324068 DSI data_rate: 832800000 bps
9380 11:13:39.327310 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9381 11:13:39.334258 anx7625_parse_edid: pixelclock(138800).
9382 11:13:39.337223 hactive(1920), hsync(48), hfp(24), hbp(88)
9383 11:13:39.340387 vactive(1080), vsync(12), vfp(3), vbp(17)
9384 11:13:39.343555 anx7625_dsi_config: config dsi.
9385 11:13:39.350638 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9386 11:13:39.363514 anx7625_dsi_config: success to config DSI
9387 11:13:39.366623 anx7625_dp_start: MIPI phy setup OK.
9388 11:13:39.369920 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9389 11:13:39.373057 mtk_ddp_mode_set invalid vrefresh 60
9390 11:13:39.376393 main_disp_path_setup
9391 11:13:39.376811 ovl_layer_smi_id_en
9392 11:13:39.380158 ovl_layer_smi_id_en
9393 11:13:39.380576 ccorr_config
9394 11:13:39.380903 aal_config
9395 11:13:39.383281 gamma_config
9396 11:13:39.383814 postmask_config
9397 11:13:39.386484 dither_config
9398 11:13:39.389596 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9399 11:13:39.396598 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9400 11:13:39.399770 Root Device init finished in 554 msecs
9401 11:13:39.400189 CPU_CLUSTER: 0 init
9402 11:13:39.410120 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9403 11:13:39.413219 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9404 11:13:39.416293 APU_MBOX 0x190000b0 = 0x10001
9405 11:13:39.419695 APU_MBOX 0x190001b0 = 0x10001
9406 11:13:39.423608 APU_MBOX 0x190005b0 = 0x10001
9407 11:13:39.426590 APU_MBOX 0x190006b0 = 0x10001
9408 11:13:39.429852 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9409 11:13:39.442374 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9410 11:13:39.454466 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9411 11:13:39.461133 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9412 11:13:39.472768 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9413 11:13:39.482297 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9414 11:13:39.485600 CPU_CLUSTER: 0 init finished in 81 msecs
9415 11:13:39.488871 Devices initialized
9416 11:13:39.491839 Show all devs... After init.
9417 11:13:39.492353 Root Device: enabled 1
9418 11:13:39.495437 CPU_CLUSTER: 0: enabled 1
9419 11:13:39.498750 CPU: 00: enabled 1
9420 11:13:39.501871 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9421 11:13:39.505189 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9422 11:13:39.508978 ELOG: NV offset 0x57f000 size 0x1000
9423 11:13:39.515575 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9424 11:13:39.522090 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9425 11:13:39.525417 ELOG: Event(17) added with size 13 at 2023-06-05 11:13:27 UTC
9426 11:13:39.528519 out: cmd=0x121: 03 db 21 01 00 00 00 00
9427 11:13:39.532426 in-header: 03 c0 00 00 2c 00 00 00
9428 11:13:39.545781 in-data: 9f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9429 11:13:39.551977 ELOG: Event(A1) added with size 10 at 2023-06-05 11:13:27 UTC
9430 11:13:39.559055 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9431 11:13:39.565371 ELOG: Event(A0) added with size 9 at 2023-06-05 11:13:27 UTC
9432 11:13:39.569406 elog_add_boot_reason: Logged dev mode boot
9433 11:13:39.571924 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9434 11:13:39.575838 Finalize devices...
9435 11:13:39.576295 Devices finalized
9436 11:13:39.582444 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9437 11:13:39.585815 Writing coreboot table at 0xffe64000
9438 11:13:39.588890 0. 000000000010a000-0000000000113fff: RAMSTAGE
9439 11:13:39.592115 1. 0000000040000000-00000000400fffff: RAM
9440 11:13:39.595823 2. 0000000040100000-000000004032afff: RAMSTAGE
9441 11:13:39.602384 3. 000000004032b000-00000000545fffff: RAM
9442 11:13:39.605538 4. 0000000054600000-000000005465ffff: BL31
9443 11:13:39.608762 5. 0000000054660000-00000000ffe63fff: RAM
9444 11:13:39.615142 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9445 11:13:39.618936 7. 0000000100000000-000000023fffffff: RAM
9446 11:13:39.619392 Passing 5 GPIOs to payload:
9447 11:13:39.625616 NAME | PORT | POLARITY | VALUE
9448 11:13:39.628724 EC in RW | 0x000000aa | low | undefined
9449 11:13:39.635071 EC interrupt | 0x00000005 | low | undefined
9450 11:13:39.638472 TPM interrupt | 0x000000ab | high | undefined
9451 11:13:39.641754 SD card detect | 0x00000011 | high | undefined
9452 11:13:39.648354 speaker enable | 0x00000093 | high | undefined
9453 11:13:39.651431 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9454 11:13:39.655107 in-header: 03 f9 00 00 02 00 00 00
9455 11:13:39.655646 in-data: 02 00
9456 11:13:39.658310 ADC[4]: Raw value=904726 ID=7
9457 11:13:39.661612 ADC[3]: Raw value=213810 ID=1
9458 11:13:39.664888 RAM Code: 0x71
9459 11:13:39.665315 ADC[6]: Raw value=75332 ID=0
9460 11:13:39.668031 ADC[5]: Raw value=212703 ID=1
9461 11:13:39.671740 SKU Code: 0x1
9462 11:13:39.674823 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98
9463 11:13:39.678150 coreboot table: 964 bytes.
9464 11:13:39.681521 IMD ROOT 0. 0xfffff000 0x00001000
9465 11:13:39.684685 IMD SMALL 1. 0xffffe000 0x00001000
9466 11:13:39.687912 RO MCACHE 2. 0xffffc000 0x00001104
9467 11:13:39.691699 CONSOLE 3. 0xfff7c000 0x00080000
9468 11:13:39.694906 FMAP 4. 0xfff7b000 0x00000452
9469 11:13:39.698104 TIME STAMP 5. 0xfff7a000 0x00000910
9470 11:13:39.701397 VBOOT WORK 6. 0xfff66000 0x00014000
9471 11:13:39.704834 RAMOOPS 7. 0xffe66000 0x00100000
9472 11:13:39.707786 COREBOOT 8. 0xffe64000 0x00002000
9473 11:13:39.708219 IMD small region:
9474 11:13:39.711220 IMD ROOT 0. 0xffffec00 0x00000400
9475 11:13:39.714475 VPD 1. 0xffffeba0 0x0000004c
9476 11:13:39.718111 MMC STATUS 2. 0xffffeb80 0x00000004
9477 11:13:39.724714 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9478 11:13:39.728320 Probing TPM: done!
9479 11:13:39.731289 Connected to device vid:did:rid of 1ae0:0028:00
9480 11:13:39.741253 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9481 11:13:39.744887 Initialized TPM device CR50 revision 0
9482 11:13:39.748976 Checking cr50 for pending updates
9483 11:13:39.752061 Reading cr50 TPM mode
9484 11:13:39.760493 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9485 11:13:39.767391 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9486 11:13:39.807473 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9487 11:13:39.810472 Checking segment from ROM address 0x40100000
9488 11:13:39.814293 Checking segment from ROM address 0x4010001c
9489 11:13:39.820631 Loading segment from ROM address 0x40100000
9490 11:13:39.821064 code (compression=0)
9491 11:13:39.830786 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9492 11:13:39.837001 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9493 11:13:39.837435 it's not compressed!
9494 11:13:39.844256 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9495 11:13:39.847392 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9496 11:13:39.867397 Loading segment from ROM address 0x4010001c
9497 11:13:39.867990 Entry Point 0x80000000
9498 11:13:39.870981 Loaded segments
9499 11:13:39.874076 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9500 11:13:39.880919 Jumping to boot code at 0x80000000(0xffe64000)
9501 11:13:39.887365 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9502 11:13:39.894402 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9503 11:13:39.902389 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9504 11:13:39.905566 Checking segment from ROM address 0x40100000
9505 11:13:39.908857 Checking segment from ROM address 0x4010001c
9506 11:13:39.915448 Loading segment from ROM address 0x40100000
9507 11:13:39.915878 code (compression=1)
9508 11:13:39.922465 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9509 11:13:39.932419 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9510 11:13:39.932940 using LZMA
9511 11:13:39.940665 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9512 11:13:39.946912 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9513 11:13:39.950608 Loading segment from ROM address 0x4010001c
9514 11:13:39.951047 Entry Point 0x54601000
9515 11:13:39.953755 Loaded segments
9516 11:13:39.957495 NOTICE: MT8192 bl31_setup
9517 11:13:39.964121 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9518 11:13:39.967199 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9519 11:13:39.970785 WARNING: region 0:
9520 11:13:39.973963 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 11:13:39.974397 WARNING: region 1:
9522 11:13:39.980723 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9523 11:13:39.984402 WARNING: region 2:
9524 11:13:39.987651 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9525 11:13:39.990876 WARNING: region 3:
9526 11:13:39.994013 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9527 11:13:39.997915 WARNING: region 4:
9528 11:13:40.004318 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9529 11:13:40.004753 WARNING: region 5:
9530 11:13:40.007424 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9531 11:13:40.010609 WARNING: region 6:
9532 11:13:40.014454 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 11:13:40.014888 WARNING: region 7:
9534 11:13:40.021194 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 11:13:40.027365 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9536 11:13:40.030628 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9537 11:13:40.034041 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9538 11:13:40.041315 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9539 11:13:40.044339 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9540 11:13:40.047684 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9541 11:13:40.054034 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9542 11:13:40.057569 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9543 11:13:40.061268 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9544 11:13:40.067564 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9545 11:13:40.071150 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9546 11:13:40.074056 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9547 11:13:40.080830 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9548 11:13:40.084397 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9549 11:13:40.091090 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9550 11:13:40.094118 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9551 11:13:40.097755 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9552 11:13:40.104710 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9553 11:13:40.107930 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9554 11:13:40.111053 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9555 11:13:40.118283 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9556 11:13:40.121421 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9557 11:13:40.128171 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9558 11:13:40.131123 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9559 11:13:40.134299 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9560 11:13:40.141514 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9561 11:13:40.144724 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9562 11:13:40.151156 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9563 11:13:40.155036 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9564 11:13:40.158192 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9565 11:13:40.164991 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9566 11:13:40.167965 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9567 11:13:40.171726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9568 11:13:40.178206 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9569 11:13:40.181448 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9570 11:13:40.185192 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9571 11:13:40.188245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9572 11:13:40.191397 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9573 11:13:40.198076 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9574 11:13:40.201530 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9575 11:13:40.204991 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9576 11:13:40.208116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9577 11:13:40.215135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9578 11:13:40.218487 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9579 11:13:40.221650 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9580 11:13:40.224911 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9581 11:13:40.231535 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9582 11:13:40.235168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9583 11:13:40.238325 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9584 11:13:40.245301 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9585 11:13:40.248486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9586 11:13:40.254882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9587 11:13:40.258241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9588 11:13:40.265221 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9589 11:13:40.268266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9590 11:13:40.272404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9591 11:13:40.278180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9592 11:13:40.282039 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9593 11:13:40.288085 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9594 11:13:40.291962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9595 11:13:40.298722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9596 11:13:40.301936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9597 11:13:40.305453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9598 11:13:40.312070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9599 11:13:40.315043 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9600 11:13:40.321659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9601 11:13:40.324929 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9602 11:13:40.331905 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9603 11:13:40.335068 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9604 11:13:40.338749 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9605 11:13:40.345414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9606 11:13:40.348574 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9607 11:13:40.355178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9608 11:13:40.358405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9609 11:13:40.365395 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9610 11:13:40.368654 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9611 11:13:40.371738 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9612 11:13:40.378273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9613 11:13:40.381873 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9614 11:13:40.388283 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9615 11:13:40.391363 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9616 11:13:40.398541 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9617 11:13:40.401605 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9618 11:13:40.405099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9619 11:13:40.412006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9620 11:13:40.414958 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9621 11:13:40.421556 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9622 11:13:40.425427 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9623 11:13:40.431804 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9624 11:13:40.434929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9625 11:13:40.438885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9626 11:13:40.444976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9627 11:13:40.448770 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9628 11:13:40.455158 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9629 11:13:40.458422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9630 11:13:40.465272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9631 11:13:40.468502 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9632 11:13:40.471811 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9633 11:13:40.475061 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9634 11:13:40.481903 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9635 11:13:40.486036 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9636 11:13:40.489126 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9637 11:13:40.495560 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9638 11:13:40.499206 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9639 11:13:40.502241 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9640 11:13:40.509101 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9641 11:13:40.512060 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9642 11:13:40.518671 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9643 11:13:40.521992 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9644 11:13:40.525409 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9645 11:13:40.532018 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9646 11:13:40.535840 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9647 11:13:40.542275 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9648 11:13:40.545569 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9649 11:13:40.549132 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9650 11:13:40.556065 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9651 11:13:40.559226 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9652 11:13:40.562644 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9653 11:13:40.569023 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9654 11:13:40.572138 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9655 11:13:40.575362 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9656 11:13:40.579193 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9657 11:13:40.582400 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9658 11:13:40.589199 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9659 11:13:40.592137 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9660 11:13:40.599283 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9661 11:13:40.602436 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9662 11:13:40.605458 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9663 11:13:40.612412 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9664 11:13:40.615375 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9665 11:13:40.619125 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9666 11:13:40.625759 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9667 11:13:40.628854 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9668 11:13:40.635443 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9669 11:13:40.639151 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9670 11:13:40.642380 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9671 11:13:40.649341 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9672 11:13:40.652349 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9673 11:13:40.659173 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9674 11:13:40.662514 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9675 11:13:40.665582 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9676 11:13:40.672817 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9677 11:13:40.676128 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9678 11:13:40.679279 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9679 11:13:40.686217 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9680 11:13:40.689393 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9681 11:13:40.696128 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9682 11:13:40.699240 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9683 11:13:40.702599 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9684 11:13:40.709309 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9685 11:13:40.712536 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9686 11:13:40.716225 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9687 11:13:40.722611 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9688 11:13:40.726509 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9689 11:13:40.732878 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9690 11:13:40.735900 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9691 11:13:40.739573 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9692 11:13:40.746239 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9693 11:13:40.749619 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9694 11:13:40.753011 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9695 11:13:40.759428 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9696 11:13:40.762692 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9697 11:13:40.769705 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9698 11:13:40.772907 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9699 11:13:40.776066 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9700 11:13:40.782518 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9701 11:13:40.786452 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9702 11:13:40.792695 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9703 11:13:40.795968 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9704 11:13:40.799084 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9705 11:13:40.806003 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9706 11:13:40.809215 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9707 11:13:40.812574 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9708 11:13:40.819731 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9709 11:13:40.822688 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9710 11:13:40.829695 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9711 11:13:40.832939 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9712 11:13:40.835992 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9713 11:13:40.842581 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9714 11:13:40.845624 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9715 11:13:40.852735 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9716 11:13:40.855701 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9717 11:13:40.859041 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9718 11:13:40.865636 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9719 11:13:40.869373 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9720 11:13:40.875883 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9721 11:13:40.879033 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9722 11:13:40.882229 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9723 11:13:40.889347 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9724 11:13:40.892379 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9725 11:13:40.898960 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9726 11:13:40.902229 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9727 11:13:40.909113 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9728 11:13:40.912464 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9729 11:13:40.915395 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9730 11:13:40.922180 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9731 11:13:40.925978 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9732 11:13:40.932131 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9733 11:13:40.936028 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9734 11:13:40.939297 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9735 11:13:40.945727 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9736 11:13:40.948888 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9737 11:13:40.955605 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9738 11:13:40.959041 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9739 11:13:40.962116 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9740 11:13:40.968634 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9741 11:13:40.972237 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9742 11:13:40.979039 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9743 11:13:40.982159 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9744 11:13:40.988600 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9745 11:13:40.992369 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9746 11:13:40.995690 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9747 11:13:41.001982 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9748 11:13:41.005252 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9749 11:13:41.012319 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9750 11:13:41.015567 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9751 11:13:41.018677 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9752 11:13:41.025089 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9753 11:13:41.028360 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9754 11:13:41.035188 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9755 11:13:41.038167 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9756 11:13:41.045036 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9757 11:13:41.048722 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9758 11:13:41.051864 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9759 11:13:41.058837 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9760 11:13:41.061673 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9761 11:13:41.068404 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9762 11:13:41.071746 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9763 11:13:41.074889 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9764 11:13:41.081651 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9765 11:13:41.085269 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9766 11:13:41.088573 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9767 11:13:41.091729 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9768 11:13:41.095427 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9769 11:13:41.102012 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9770 11:13:41.105424 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9771 11:13:41.111863 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9772 11:13:41.114855 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9773 11:13:41.118754 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9774 11:13:41.125207 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9775 11:13:41.128287 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9776 11:13:41.131690 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9777 11:13:41.138159 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9778 11:13:41.141876 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9779 11:13:41.144863 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9780 11:13:41.151619 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9781 11:13:41.155396 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9782 11:13:41.161694 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9783 11:13:41.164708 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9784 11:13:41.168550 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9785 11:13:41.175024 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9786 11:13:41.178018 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9787 11:13:41.184816 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9788 11:13:41.188306 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9789 11:13:41.191182 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9790 11:13:41.198160 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9791 11:13:41.201405 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9792 11:13:41.204572 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9793 11:13:41.211803 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9794 11:13:41.214946 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9795 11:13:41.218176 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9796 11:13:41.225190 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9797 11:13:41.228312 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9798 11:13:41.231563 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9799 11:13:41.238196 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9800 11:13:41.241531 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9801 11:13:41.247992 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9802 11:13:41.251201 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9803 11:13:41.254802 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9804 11:13:41.257935 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9805 11:13:41.264645 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9806 11:13:41.268451 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9807 11:13:41.271769 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9808 11:13:41.274702 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9809 11:13:41.281470 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9810 11:13:41.284416 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9811 11:13:41.287975 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9812 11:13:41.291212 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9813 11:13:41.297869 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9814 11:13:41.301561 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9815 11:13:41.304279 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9816 11:13:41.308105 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9817 11:13:41.314499 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9818 11:13:41.317850 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9819 11:13:41.324493 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9820 11:13:41.328297 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9821 11:13:41.331541 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9822 11:13:41.337997 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9823 11:13:41.341272 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9824 11:13:41.347899 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9825 11:13:41.351103 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9826 11:13:41.354973 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9827 11:13:41.361021 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9828 11:13:41.364689 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9829 11:13:41.371473 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9830 11:13:41.374594 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9831 11:13:41.380759 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9832 11:13:41.384706 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9833 11:13:41.387930 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9834 11:13:41.394476 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9835 11:13:41.397973 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9836 11:13:41.404039 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9837 11:13:41.407707 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9838 11:13:41.411163 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9839 11:13:41.418168 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9840 11:13:41.421184 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9841 11:13:41.428077 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9842 11:13:41.431054 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9843 11:13:41.434701 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9844 11:13:41.441120 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9845 11:13:41.444368 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9846 11:13:41.450914 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9847 11:13:41.454110 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9848 11:13:41.457394 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9849 11:13:41.464403 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9850 11:13:41.467447 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9851 11:13:41.474054 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9852 11:13:41.477758 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9853 11:13:41.480731 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9854 11:13:41.487243 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9855 11:13:41.491026 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9856 11:13:41.497194 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9857 11:13:41.500892 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9858 11:13:41.503996 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9859 11:13:41.510562 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9860 11:13:41.514130 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9861 11:13:41.520725 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9862 11:13:41.523939 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9863 11:13:41.530434 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9864 11:13:41.533615 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9865 11:13:41.537058 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9866 11:13:41.544140 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9867 11:13:41.547366 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9868 11:13:41.553628 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9869 11:13:41.556812 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9870 11:13:41.559976 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9871 11:13:41.566758 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9872 11:13:41.570528 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9873 11:13:41.577380 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9874 11:13:41.580321 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9875 11:13:41.583574 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9876 11:13:41.590524 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9877 11:13:41.593702 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9878 11:13:41.600803 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9879 11:13:41.603901 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9880 11:13:41.606707 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9881 11:13:41.613310 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9882 11:13:41.617025 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9883 11:13:41.623605 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9884 11:13:41.626645 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9885 11:13:41.633174 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9886 11:13:41.636404 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9887 11:13:41.640068 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9888 11:13:41.646975 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9889 11:13:41.650518 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9890 11:13:41.656850 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9891 11:13:41.660191 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9892 11:13:41.663309 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9893 11:13:41.669878 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9894 11:13:41.673650 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9895 11:13:41.679963 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9896 11:13:41.683193 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9897 11:13:41.689738 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9898 11:13:41.693469 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9899 11:13:41.699875 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9900 11:13:41.702985 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9901 11:13:41.706150 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9902 11:13:41.712984 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9903 11:13:41.716440 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9904 11:13:41.722919 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9905 11:13:41.726555 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9906 11:13:41.733346 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9907 11:13:41.736588 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9908 11:13:41.739831 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9909 11:13:41.746762 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9910 11:13:41.749672 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9911 11:13:41.756915 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9912 11:13:41.760029 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9913 11:13:41.766401 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9914 11:13:41.769657 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9915 11:13:41.773014 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9916 11:13:41.780027 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9917 11:13:41.783209 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9918 11:13:41.789600 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9919 11:13:41.793389 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9920 11:13:41.796150 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9921 11:13:41.802990 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9922 11:13:41.806497 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9923 11:13:41.813012 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9924 11:13:41.816304 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9925 11:13:41.823073 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9926 11:13:41.826673 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9927 11:13:41.833420 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9928 11:13:41.836499 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9929 11:13:41.839965 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9930 11:13:41.846379 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9931 11:13:41.849451 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9932 11:13:41.856346 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9933 11:13:41.859596 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9934 11:13:41.865863 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9935 11:13:41.869777 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9936 11:13:41.873025 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9937 11:13:41.879508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9938 11:13:41.882513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9939 11:13:41.889721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9940 11:13:41.892842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9941 11:13:41.899029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9942 11:13:41.902311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9943 11:13:41.909615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9944 11:13:41.912460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9945 11:13:41.918890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9946 11:13:41.922199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9947 11:13:41.929086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9948 11:13:41.932205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9949 11:13:41.938704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9950 11:13:41.942514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9951 11:13:41.945386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9952 11:13:41.952543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9953 11:13:41.955804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9954 11:13:41.962526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9955 11:13:41.965933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9956 11:13:41.972199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9957 11:13:41.975686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9958 11:13:41.982162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9959 11:13:41.985897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9960 11:13:41.992179 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9961 11:13:41.995452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9962 11:13:42.002618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9963 11:13:42.005852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9964 11:13:42.012800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9965 11:13:42.015705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9966 11:13:42.022345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9967 11:13:42.026006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9968 11:13:42.032521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9969 11:13:42.035609 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9970 11:13:42.038766 INFO: [APUAPC] vio 0
9971 11:13:42.042211 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9972 11:13:42.048838 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9973 11:13:42.052504 INFO: [APUAPC] D0_APC_0: 0x400510
9974 11:13:42.052948 INFO: [APUAPC] D0_APC_1: 0x0
9975 11:13:42.055524 INFO: [APUAPC] D0_APC_2: 0x1540
9976 11:13:42.059130 INFO: [APUAPC] D0_APC_3: 0x0
9977 11:13:42.062128 INFO: [APUAPC] D1_APC_0: 0xffffffff
9978 11:13:42.065716 INFO: [APUAPC] D1_APC_1: 0xffffffff
9979 11:13:42.068907 INFO: [APUAPC] D1_APC_2: 0x3fffff
9980 11:13:42.072867 INFO: [APUAPC] D1_APC_3: 0x0
9981 11:13:42.075930 INFO: [APUAPC] D2_APC_0: 0xffffffff
9982 11:13:42.079190 INFO: [APUAPC] D2_APC_1: 0xffffffff
9983 11:13:42.082172 INFO: [APUAPC] D2_APC_2: 0x3fffff
9984 11:13:42.085471 INFO: [APUAPC] D2_APC_3: 0x0
9985 11:13:42.089327 INFO: [APUAPC] D3_APC_0: 0xffffffff
9986 11:13:42.092527 INFO: [APUAPC] D3_APC_1: 0xffffffff
9987 11:13:42.095821 INFO: [APUAPC] D3_APC_2: 0x3fffff
9988 11:13:42.099051 INFO: [APUAPC] D3_APC_3: 0x0
9989 11:13:42.102331 INFO: [APUAPC] D4_APC_0: 0xffffffff
9990 11:13:42.105625 INFO: [APUAPC] D4_APC_1: 0xffffffff
9991 11:13:42.109393 INFO: [APUAPC] D4_APC_2: 0x3fffff
9992 11:13:42.112639 INFO: [APUAPC] D4_APC_3: 0x0
9993 11:13:42.115720 INFO: [APUAPC] D5_APC_0: 0xffffffff
9994 11:13:42.118843 INFO: [APUAPC] D5_APC_1: 0xffffffff
9995 11:13:42.122559 INFO: [APUAPC] D5_APC_2: 0x3fffff
9996 11:13:42.126050 INFO: [APUAPC] D5_APC_3: 0x0
9997 11:13:42.129108 INFO: [APUAPC] D6_APC_0: 0xffffffff
9998 11:13:42.132746 INFO: [APUAPC] D6_APC_1: 0xffffffff
9999 11:13:42.135889 INFO: [APUAPC] D6_APC_2: 0x3fffff
10000 11:13:42.139191 INFO: [APUAPC] D6_APC_3: 0x0
10001 11:13:42.142393 INFO: [APUAPC] D7_APC_0: 0xffffffff
10002 11:13:42.146007 INFO: [APUAPC] D7_APC_1: 0xffffffff
10003 11:13:42.149090 INFO: [APUAPC] D7_APC_2: 0x3fffff
10004 11:13:42.149521 INFO: [APUAPC] D7_APC_3: 0x0
10005 11:13:42.152541 INFO: [APUAPC] D8_APC_0: 0xffffffff
10006 11:13:42.159653 INFO: [APUAPC] D8_APC_1: 0xffffffff
10007 11:13:42.160107 INFO: [APUAPC] D8_APC_2: 0x3fffff
10008 11:13:42.162332 INFO: [APUAPC] D8_APC_3: 0x0
10009 11:13:42.165711 INFO: [APUAPC] D9_APC_0: 0xffffffff
10010 11:13:42.169367 INFO: [APUAPC] D9_APC_1: 0xffffffff
10011 11:13:42.172333 INFO: [APUAPC] D9_APC_2: 0x3fffff
10012 11:13:42.175854 INFO: [APUAPC] D9_APC_3: 0x0
10013 11:13:42.179223 INFO: [APUAPC] D10_APC_0: 0xffffffff
10014 11:13:42.182481 INFO: [APUAPC] D10_APC_1: 0xffffffff
10015 11:13:42.185709 INFO: [APUAPC] D10_APC_2: 0x3fffff
10016 11:13:42.188907 INFO: [APUAPC] D10_APC_3: 0x0
10017 11:13:42.192123 INFO: [APUAPC] D11_APC_0: 0xffffffff
10018 11:13:42.195917 INFO: [APUAPC] D11_APC_1: 0xffffffff
10019 11:13:42.199043 INFO: [APUAPC] D11_APC_2: 0x3fffff
10020 11:13:42.202337 INFO: [APUAPC] D11_APC_3: 0x0
10021 11:13:42.205407 INFO: [APUAPC] D12_APC_0: 0xffffffff
10022 11:13:42.209451 INFO: [APUAPC] D12_APC_1: 0xffffffff
10023 11:13:42.212546 INFO: [APUAPC] D12_APC_2: 0x3fffff
10024 11:13:42.215944 INFO: [APUAPC] D12_APC_3: 0x0
10025 11:13:42.219186 INFO: [APUAPC] D13_APC_0: 0xffffffff
10026 11:13:42.222387 INFO: [APUAPC] D13_APC_1: 0xffffffff
10027 11:13:42.225514 INFO: [APUAPC] D13_APC_2: 0x3fffff
10028 11:13:42.229251 INFO: [APUAPC] D13_APC_3: 0x0
10029 11:13:42.232169 INFO: [APUAPC] D14_APC_0: 0xffffffff
10030 11:13:42.235798 INFO: [APUAPC] D14_APC_1: 0xffffffff
10031 11:13:42.238906 INFO: [APUAPC] D14_APC_2: 0x3fffff
10032 11:13:42.242726 INFO: [APUAPC] D14_APC_3: 0x0
10033 11:13:42.245882 INFO: [APUAPC] D15_APC_0: 0xffffffff
10034 11:13:42.249217 INFO: [APUAPC] D15_APC_1: 0xffffffff
10035 11:13:42.252272 INFO: [APUAPC] D15_APC_2: 0x3fffff
10036 11:13:42.255286 INFO: [APUAPC] D15_APC_3: 0x0
10037 11:13:42.259055 INFO: [APUAPC] APC_CON: 0x4
10038 11:13:42.261988 INFO: [NOCDAPC] D0_APC_0: 0x0
10039 11:13:42.265512 INFO: [NOCDAPC] D0_APC_1: 0x0
10040 11:13:42.268985 INFO: [NOCDAPC] D1_APC_0: 0x0
10041 11:13:42.272018 INFO: [NOCDAPC] D1_APC_1: 0xfff
10042 11:13:42.275507 INFO: [NOCDAPC] D2_APC_0: 0x0
10043 11:13:42.279026 INFO: [NOCDAPC] D2_APC_1: 0xfff
10044 11:13:42.279488 INFO: [NOCDAPC] D3_APC_0: 0x0
10045 11:13:42.282352 INFO: [NOCDAPC] D3_APC_1: 0xfff
10046 11:13:42.285510 INFO: [NOCDAPC] D4_APC_0: 0x0
10047 11:13:42.289214 INFO: [NOCDAPC] D4_APC_1: 0xfff
10048 11:13:42.292557 INFO: [NOCDAPC] D5_APC_0: 0x0
10049 11:13:42.295809 INFO: [NOCDAPC] D5_APC_1: 0xfff
10050 11:13:42.299083 INFO: [NOCDAPC] D6_APC_0: 0x0
10051 11:13:42.302163 INFO: [NOCDAPC] D6_APC_1: 0xfff
10052 11:13:42.305435 INFO: [NOCDAPC] D7_APC_0: 0x0
10053 11:13:42.309341 INFO: [NOCDAPC] D7_APC_1: 0xfff
10054 11:13:42.309768 INFO: [NOCDAPC] D8_APC_0: 0x0
10055 11:13:42.312631 INFO: [NOCDAPC] D8_APC_1: 0xfff
10056 11:13:42.315858 INFO: [NOCDAPC] D9_APC_0: 0x0
10057 11:13:42.319047 INFO: [NOCDAPC] D9_APC_1: 0xfff
10058 11:13:42.322232 INFO: [NOCDAPC] D10_APC_0: 0x0
10059 11:13:42.325440 INFO: [NOCDAPC] D10_APC_1: 0xfff
10060 11:13:42.328821 INFO: [NOCDAPC] D11_APC_0: 0x0
10061 11:13:42.331921 INFO: [NOCDAPC] D11_APC_1: 0xfff
10062 11:13:42.335693 INFO: [NOCDAPC] D12_APC_0: 0x0
10063 11:13:42.338745 INFO: [NOCDAPC] D12_APC_1: 0xfff
10064 11:13:42.342360 INFO: [NOCDAPC] D13_APC_0: 0x0
10065 11:13:42.345435 INFO: [NOCDAPC] D13_APC_1: 0xfff
10066 11:13:42.348628 INFO: [NOCDAPC] D14_APC_0: 0x0
10067 11:13:42.351980 INFO: [NOCDAPC] D14_APC_1: 0xfff
10068 11:13:42.355131 INFO: [NOCDAPC] D15_APC_0: 0x0
10069 11:13:42.355685 INFO: [NOCDAPC] D15_APC_1: 0xfff
10070 11:13:42.358406 INFO: [NOCDAPC] APC_CON: 0x4
10071 11:13:42.362060 INFO: [APUAPC] set_apusys_apc done
10072 11:13:42.365265 INFO: [DEVAPC] devapc_init done
10073 11:13:42.371870 INFO: GICv3 without legacy support detected.
10074 11:13:42.375396 INFO: ARM GICv3 driver initialized in EL3
10075 11:13:42.378585 INFO: Maximum SPI INTID supported: 639
10076 11:13:42.381647 INFO: BL31: Initializing runtime services
10077 11:13:42.388434 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10078 11:13:42.392160 INFO: SPM: enable CPC mode
10079 11:13:42.395113 INFO: mcdi ready for mcusys-off-idle and system suspend
10080 11:13:42.401515 INFO: BL31: Preparing for EL3 exit to normal world
10081 11:13:42.405260 INFO: Entry point address = 0x80000000
10082 11:13:42.405688 INFO: SPSR = 0x8
10083 11:13:42.411767
10084 11:13:42.412189
10085 11:13:42.412533
10086 11:13:42.414915 Starting depthcharge on Spherion...
10087 11:13:42.415455
10088 11:13:42.415909 Wipe memory regions:
10089 11:13:42.416264
10090 11:13:42.418559 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10091 11:13:42.419058 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10092 11:13:42.419504 Setting prompt string to ['asurada:']
10093 11:13:42.419916 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10094 11:13:42.420564 [0x00000040000000, 0x00000054600000)
10095 11:13:42.541124
10096 11:13:42.541637 [0x00000054660000, 0x00000080000000)
10097 11:13:42.801470
10098 11:13:42.801984 [0x000000821a7280, 0x000000ffe64000)
10099 11:13:43.546616
10100 11:13:43.547134 [0x00000100000000, 0x00000240000000)
10101 11:13:45.436861
10102 11:13:45.439996 Initializing XHCI USB controller at 0x11200000.
10103 11:13:46.478052
10104 11:13:46.481161 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10105 11:13:46.481605
10106 11:13:46.482055
10107 11:13:46.482463
10108 11:13:46.483382 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10110 11:13:46.584550 asurada: tftpboot 192.168.201.1 10591219/tftp-deploy-nqwh2nxw/kernel/image.itb 10591219/tftp-deploy-nqwh2nxw/kernel/cmdline
10111 11:13:46.585135 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10112 11:13:46.585600 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10113 11:13:46.590059 tftpboot 192.168.201.1 10591219/tftp-deploy-nqwh2nxw/kernel/image.itp-deploy-nqwh2nxw/kernel/cmdline
10114 11:13:46.590519
10115 11:13:46.590941 Waiting for link
10116 11:13:46.750987
10117 11:13:46.751568 R8152: Initializing
10118 11:13:46.752019
10119 11:13:46.753563 Version 9 (ocp_data = 6010)
10120 11:13:46.753946
10121 11:13:46.757387 R8152: Done initializing
10122 11:13:46.757786
10123 11:13:46.758188 Adding net device
10124 11:13:48.699264
10125 11:13:48.699447 done.
10126 11:13:48.699575
10127 11:13:48.699690 MAC: 00:e0:4c:78:7a:aa
10128 11:13:48.699799
10129 11:13:48.702355 Sending DHCP discover... done.
10130 11:13:48.702464
10131 11:13:48.705758 Waiting for reply... done.
10132 11:13:48.705875
10133 11:13:48.708978 Sending DHCP request... done.
10134 11:13:48.709089
10135 11:13:48.709202 Waiting for reply... done.
10136 11:13:48.709319
10137 11:13:48.712896 My ip is 192.168.201.12
10138 11:13:48.713008
10139 11:13:48.715976 The DHCP server ip is 192.168.201.1
10140 11:13:48.716117
10141 11:13:48.719192 TFTP server IP predefined by user: 192.168.201.1
10142 11:13:48.719357
10143 11:13:48.725742 Bootfile predefined by user: 10591219/tftp-deploy-nqwh2nxw/kernel/image.itb
10144 11:13:48.725881
10145 11:13:48.728958 Sending tftp read request... done.
10146 11:13:48.729090
10147 11:13:48.732790 Waiting for the transfer...
10148 11:13:48.732935
10149 11:13:48.993290 00000000 ################################################################
10150 11:13:48.993436
10151 11:13:49.242742 00080000 ################################################################
10152 11:13:49.242891
10153 11:13:49.494018 00100000 ################################################################
10154 11:13:49.494173
10155 11:13:49.745786 00180000 ################################################################
10156 11:13:49.745938
10157 11:13:49.998678 00200000 ################################################################
10158 11:13:49.998931
10159 11:13:50.249048 00280000 ################################################################
10160 11:13:50.249221
10161 11:13:50.507668 00300000 ################################################################
10162 11:13:50.507818
10163 11:13:50.785631 00380000 ################################################################
10164 11:13:50.785766
10165 11:13:51.059258 00400000 ################################################################
10166 11:13:51.059455
10167 11:13:51.331206 00480000 ################################################################
10168 11:13:51.331407
10169 11:13:51.595456 00500000 ################################################################
10170 11:13:51.595680
10171 11:13:51.887289 00580000 ################################################################
10172 11:13:51.887450
10173 11:13:52.151073 00600000 ################################################################
10174 11:13:52.151251
10175 11:13:52.438082 00680000 ################################################################
10176 11:13:52.438260
10177 11:13:52.725937 00700000 ################################################################
10178 11:13:52.726073
10179 11:13:53.016142 00780000 ################################################################
10180 11:13:53.016307
10181 11:13:53.278873 00800000 ################################################################
10182 11:13:53.279044
10183 11:13:53.547199 00880000 ################################################################
10184 11:13:53.547384
10185 11:13:53.820211 00900000 ################################################################
10186 11:13:53.820359
10187 11:13:54.109436 00980000 ################################################################
10188 11:13:54.109613
10189 11:13:54.392922 00a00000 ################################################################
10190 11:13:54.393058
10191 11:13:54.679421 00a80000 ################################################################
10192 11:13:54.679558
10193 11:13:54.973686 00b00000 ################################################################
10194 11:13:54.973838
10195 11:13:55.272284 00b80000 ################################################################
10196 11:13:55.272421
10197 11:13:55.540031 00c00000 ################################################################
10198 11:13:55.540203
10199 11:13:55.809229 00c80000 ################################################################
10200 11:13:55.809391
10201 11:13:56.091700 00d00000 ################################################################
10202 11:13:56.091861
10203 11:13:56.382656 00d80000 ################################################################
10204 11:13:56.382830
10205 11:13:56.659187 00e00000 ################################################################
10206 11:13:56.659390
10207 11:13:56.939619 00e80000 ################################################################
10208 11:13:56.939783
10209 11:13:57.228155 00f00000 ################################################################
10210 11:13:57.228288
10211 11:13:57.495622 00f80000 ################################################################
10212 11:13:57.495767
10213 11:13:57.762917 01000000 ################################################################
10214 11:13:57.763053
10215 11:13:58.026123 01080000 ################################################################
10216 11:13:58.026292
10217 11:13:58.321101 01100000 ################################################################
10218 11:13:58.321249
10219 11:13:58.611300 01180000 ################################################################
10220 11:13:58.611506
10221 11:13:58.888291 01200000 ################################################################
10222 11:13:58.888434
10223 11:13:59.159936 01280000 ################################################################
10224 11:13:59.160087
10225 11:13:59.458222 01300000 ################################################################
10226 11:13:59.458374
10227 11:13:59.731531 01380000 ################################################################
10228 11:13:59.731695
10229 11:14:00.007352 01400000 ################################################################
10230 11:14:00.007513
10231 11:14:00.276350 01480000 ################################################################
10232 11:14:00.276500
10233 11:14:00.544204 01500000 ################################################################
10234 11:14:00.544358
10235 11:14:00.822913 01580000 ################################################################
10236 11:14:00.823061
10237 11:14:01.091980 01600000 ################################################################
10238 11:14:01.092128
10239 11:14:01.389683 01680000 ################################################################
10240 11:14:01.389856
10241 11:14:01.657635 01700000 ################################################################
10242 11:14:01.657780
10243 11:14:01.927703 01780000 ################################################################
10244 11:14:01.927851
10245 11:14:02.198386 01800000 ################################################################
10246 11:14:02.198539
10247 11:14:02.462396 01880000 ################################################################
10248 11:14:02.462564
10249 11:14:02.751138 01900000 ################################################################
10250 11:14:02.751308
10251 11:14:03.015759 01980000 ################################################################
10252 11:14:03.015903
10253 11:14:03.267231 01a00000 ############################################################### done.
10254 11:14:03.267400
10255 11:14:03.270261 The bootfile was 27774654 bytes long.
10256 11:14:03.270338
10257 11:14:03.273743 Sending tftp read request... done.
10258 11:14:03.273831
10259 11:14:03.277483 Waiting for the transfer...
10260 11:14:03.277569
10261 11:14:03.277635 00000000 # done.
10262 11:14:03.280651
10263 11:14:03.287158 Command line loaded dynamically from TFTP file: 10591219/tftp-deploy-nqwh2nxw/kernel/cmdline
10264 11:14:03.287271
10265 11:14:03.303680 The command line is: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591219/extract-nfsrootfs-1v2va2w7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10266 11:14:03.303784
10267 11:14:03.303854 Loading FIT.
10268 11:14:03.303916
10269 11:14:03.306905 Image ramdisk-1 has 17639676 bytes.
10270 11:14:03.306989
10271 11:14:03.310709 Image fdt-1 has 46924 bytes.
10272 11:14:03.310794
10273 11:14:03.314025 Image kernel-1 has 10086024 bytes.
10274 11:14:03.314109
10275 11:14:03.324081 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10276 11:14:03.324169
10277 11:14:03.340118 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10278 11:14:03.340244
10279 11:14:03.346935 Choosing best match conf-1 for compat google,spherion-rev2.
10280 11:14:03.347025
10281 11:14:03.354598 Connected to device vid:did:rid of 1ae0:0028:00
10282 11:14:03.362525
10283 11:14:03.366059 tpm_get_response: command 0x17b, return code 0x0
10284 11:14:03.366144
10285 11:14:03.369079 ec_init: CrosEC protocol v3 supported (256, 248)
10286 11:14:03.373203
10287 11:14:03.376170 tpm_cleanup: add release locality here.
10288 11:14:03.376255
10289 11:14:03.376321 Shutting down all USB controllers.
10290 11:14:03.379657
10291 11:14:03.379741 Removing current net device
10292 11:14:03.379807
10293 11:14:03.386471 Exiting depthcharge with code 4 at timestamp: 50277991
10294 11:14:03.386567
10295 11:14:03.389676 LZMA decompressing kernel-1 to 0x821a6718
10296 11:14:03.389760
10297 11:14:03.392889 LZMA decompressing kernel-1 to 0x40000000
10298 11:14:04.659530
10299 11:14:04.659686 jumping to kernel
10300 11:14:04.660090 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10301 11:14:04.660191 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10302 11:14:04.660267 Setting prompt string to ['Linux version [0-9]']
10303 11:14:04.660337 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10304 11:14:04.660407 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10305 11:14:05.206423
10306 11:14:05.209960 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10307 11:14:05.213094 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10308 11:14:05.213220 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10309 11:14:05.213318 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10310 11:14:05.213397 Using line separator: #'\n'#
10311 11:14:05.213460 No login prompt set.
10312 11:14:05.213559 Parsing kernel messages
10313 11:14:05.213617 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10314 11:14:05.213719 [login-action] Waiting for messages, (timeout 00:04:02)
10315 11:14:05.233517 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10316 11:14:05.236639 [ 0.000000] random: crng init done
10317 11:14:05.239890 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10318 11:14:05.243038 [ 0.000000] efi: UEFI not found.
10319 11:14:05.253196 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10320 11:14:05.259497 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10321 11:14:05.269902 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10322 11:14:05.279158 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10323 11:14:05.282936 [ 0.000000] NUMA: No NUMA configuration found
10324 11:14:05.289459 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10325 11:14:05.296333 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10326 11:14:05.299251 [ 0.000000] Zone ranges:
10327 11:14:05.305982 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10328 11:14:05.309688 [ 0.000000] DMA32 empty
10329 11:14:05.312392 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10330 11:14:05.318999 [ 0.000000] Movable zone start for each node
10331 11:14:05.322694 [ 0.000000] Early memory node ranges
10332 11:14:05.329140 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10333 11:14:05.335712 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10334 11:14:05.338761 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10335 11:14:05.345620 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10336 11:14:05.352103 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10337 11:14:05.358566 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10338 11:14:05.365505 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10339 11:14:05.372115 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10340 11:14:05.378560 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10341 11:14:05.381651 [ 0.000000] psci: probing for conduit method from DT.
10342 11:14:05.388277 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10343 11:14:05.392071 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10344 11:14:05.398428 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10345 11:14:05.401653 [ 0.000000] psci: SMC Calling Convention v1.2
10346 11:14:05.408178 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10347 11:14:05.411218 [ 0.000000] Detected VIPT I-cache on CPU0
10348 11:14:05.418099 [ 0.000000] CPU features: detected: GIC system register CPU interface
10349 11:14:05.424566 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10350 11:14:05.431672 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10351 11:14:05.438070 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10352 11:14:05.444686 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10353 11:14:05.451436 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10354 11:14:05.457826 [ 0.000000] alternatives: applying boot alternatives
10355 11:14:05.461544 [ 0.000000] Fallback order for Node 0: 0
10356 11:14:05.468038 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10357 11:14:05.471074 [ 0.000000] Policy zone: Normal
10358 11:14:05.490932 [ 0.000000] Kernel command line: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591219/extract-nfsrootfs-1v2va2w7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10359 11:14:05.501383 [ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10360 11:14:05.507674 [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10361 11:14:05.514531 [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10362 11:14:05.521224 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10363 11:14:05.524421 [ 0.000000] software IO TLB: area num 8.
10364 11:14:05.534344 [ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10365 11:14:05.547523 [ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10366 11:14:05.554220 [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10367 11:14:05.561053 [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10368 11:14:05.564241 [ 0.000000] rcu: RCU event tracing is enabled.
10369 11:14:05.570456 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10370 11:14:05.577199 [ 0.000000] Trampoline variant of Tasks RCU enabled.
10371 11:14:05.580690 [ 0.000000] Tracing variant of Tasks RCU enabled.
10372 11:14:05.587230 [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10373 11:14:05.593628 [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10374 11:14:05.600941 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10375 11:14:05.607314 [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10376 11:14:05.610460 [ 0.000000] GICv3: 608 SPIs implemented
10377 11:14:05.613605 [ 0.000000] GICv3: 0 Extended SPIs implemented
10378 11:14:05.616842 [ 0.000000] Root IRQ handler: gic_handle_irq
10379 11:14:05.623365 [ 0.000000] GICv3: GICv3 features: 16 PPIs
10380 11:14:05.630311 [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10381 11:14:05.640378 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10382 11:14:05.653118 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10383 11:14:05.659787 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10384 11:14:05.666473 [ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10385 11:14:05.676845 [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10386 11:14:05.686436 [ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10387 11:14:05.689547 [ 0.000950] Console: colour dummy device 80x25
10388 11:14:05.699824 [ 0.001018] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10389 11:14:05.703094 [ 0.001026] pid_max: default: 32768 minimum: 301
10390 11:14:05.709440 [ 0.001068] LSM: Security Framework initializing
10391 11:14:05.715917 [ 0.001175] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10392 11:14:05.726266 [ 0.001226] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10393 11:14:05.732855 [ 0.002469] cblist_init_generic: Setting adjustable number of callback queues.
10394 11:14:05.739743 [ 0.002479] cblist_init_generic: Setting shift to 3 and lim to 1.
10395 11:14:05.742755 [ 0.002520] cblist_init_generic: Setting shift to 3 and lim to 1.
10396 11:14:05.749144 [ 0.002627] rcu: Hierarchical SRCU implementation.
10397 11:14:05.752351 [ 0.002629] rcu: Max phase no-delay instances is 1000.
10398 11:14:05.759080 [ 0.004259] EFI services will not be available.
10399 11:14:05.762577 [ 0.004477] smp: Bringing up secondary CPUs ...
10400 11:14:05.765769 [ 0.004774] Detected VIPT I-cache on CPU1
10401 11:14:05.772282 [ 0.004847] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10402 11:14:05.779205 [ 0.004878] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10403 11:14:05.785631 [ 0.005214] Detected VIPT I-cache on CPU2
10404 11:14:05.792401 [ 0.005263] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10405 11:14:05.798993 [ 0.005279] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10406 11:14:05.802260 [ 0.005541] Detected VIPT I-cache on CPU3
10407 11:14:05.808716 [ 0.005588] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10408 11:14:05.815193 [ 0.005602] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10409 11:14:05.819146 [ 0.005908] CPU features: detected: Spectre-v4
10410 11:14:05.825384 [ 0.005913] CPU features: detected: Spectre-BHB
10411 11:14:05.828690 [ 0.005918] Detected PIPT I-cache on CPU4
10412 11:14:05.835598 [ 0.005968] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10413 11:14:05.842103 [ 0.005983] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10414 11:14:05.844877 [ 0.006265] Detected PIPT I-cache on CPU5
10415 11:14:05.852137 [ 0.006322] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10416 11:14:05.858436 [ 0.006338] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10417 11:14:05.864704 [ 0.006626] Detected PIPT I-cache on CPU6
10418 11:14:05.871843 [ 0.006689] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10419 11:14:05.878043 [ 0.006706] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10420 11:14:05.881545 [ 0.007005] Detected PIPT I-cache on CPU7
10421 11:14:05.888291 [ 0.007069] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10422 11:14:05.894667 [ 0.007085] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10423 11:14:05.897833 [ 0.007134] smp: Brought up 1 node, 8 CPUs
10424 11:14:05.904931 [ 0.007139] SMP: Total of 8 processors activated.
10425 11:14:05.908138 [ 0.007142] CPU features: detected: 32-bit EL0 Support
10426 11:14:05.918205 [ 0.007145] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10427 11:14:05.924680 [ 0.007147] CPU features: detected: Common not Private translations
10428 11:14:05.927883 [ 0.007149] CPU features: detected: CRC32 instructions
10429 11:14:05.934312 [ 0.007152] CPU features: detected: RCpc load-acquire (LDAPR)
10430 11:14:05.941400 [ 0.007154] CPU features: detected: LSE atomic instructions
10431 11:14:05.944572 [ 0.007156] CPU features: detected: Privileged Access Never
10432 11:14:05.951224 [ 0.007157] CPU features: detected: RAS Extension Support
10433 11:14:05.957573 [ 0.007160] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10434 11:14:05.961130 [ 0.007231] CPU: All CPU(s) started at EL2
10435 11:14:05.967546 [ 0.007233] alternatives: applying system-wide alternatives
10436 11:14:05.971274 [ 0.012210] devtmpfs: initialized
10437 11:14:05.981201 [ 0.017435] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10438 11:14:05.987853 [ 0.017451] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10439 11:14:05.993847 [ 0.018533] pinctrl core: initialized pinctrl subsystem
10440 11:14:05.997478 [ 0.019738] DMI not present or invalid.
10441 11:14:06.003984 [ 0.020071] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10442 11:14:06.010976 [ 0.020798] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10443 11:14:06.017426 [ 0.021025] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10444 11:14:06.023751 [ 0.021204] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10445 11:14:06.030748 [ 0.021229] audit: initializing netlink subsys (disabled)
10446 11:14:06.037099 [ 0.021300] audit: type=2000 audit(0.016:1): state=initialized audit_enabled=0 res=1
10447 11:14:06.043607 [ 0.021999] thermal_sys: Registered thermal governor 'step_wise'
10448 11:14:06.050460 [ 0.022003] thermal_sys: Registered thermal governor 'power_allocator'
10449 11:14:06.053559 [ 0.022030] cpuidle: using governor menu
10450 11:14:06.060385 [ 0.022093] NET: Registered PF_QIPCRTR protocol family
10451 11:14:06.067052 [ 0.022210] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10452 11:14:06.073352 [ 0.022301] ASID allocator initialised with 32768 entries
10453 11:14:06.077097 [ 0.023217] Serial: AMBA PL011 UART driver
10454 11:14:06.080313 [ 0.027569] Trying to register duplicate clock ID: 134
10455 11:14:06.083519 [ 0.079375] KASLR enabled
10456 11:14:06.090239 [ 0.084283] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10457 11:14:06.097056 [ 0.084287] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10458 11:14:06.103235 [ 0.084291] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10459 11:14:06.109698 [ 0.084294] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10460 11:14:06.116499 [ 0.084297] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10461 11:14:06.123308 [ 0.084299] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10462 11:14:06.129393 [ 0.084302] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10463 11:14:06.136467 [ 0.084304] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10464 11:14:06.139812 [ 0.085429] ACPI: Interpreter disabled.
10465 11:14:06.146246 [ 0.087735] iommu: Default domain type: Translated
10466 11:14:06.149535 [ 0.087739] iommu: DMA domain TLB invalidation policy: strict mode
10467 11:14:06.156198 [ 0.087913] SCSI subsystem initialized
10468 11:14:06.159483 [ 0.088083] usbcore: registered new interface driver usbfs
10469 11:14:06.165897 [ 0.088103] usbcore: registered new interface driver hub
10470 11:14:06.169524 [ 0.088116] usbcore: registered new device driver usb
10471 11:14:06.176145 [ 0.088916] pps_core: LinuxPPS API ver. 1 registered
10472 11:14:06.185993 [ 0.088918] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10473 11:14:06.189399 [ 0.088924] PTP clock support registered
10474 11:14:06.192406 [ 0.089007] EDAC MC: Ver: 3.0.0
10475 11:14:06.196049 [ 0.090719] FPGA manager framework
10476 11:14:06.202720 [ 0.090769] Advanced Linux Sound Architecture Driver Initialized.
10477 11:14:06.202837 [ 0.091211] vgaarb: loaded
10478 11:14:06.209098 [ 0.091453] clocksource: Switched to clocksource arch_sys_counter
10479 11:14:06.212361 [ 0.091575] VFS: Disk quotas dquot_6.6.0
10480 11:14:06.219279 [ 0.091603] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10481 11:14:06.225997 [ 0.091698] pnp: PnP ACPI: disabled
10482 11:14:06.229383 [ 0.094397] NET: Registered PF_INET protocol family
10483 11:14:06.235840 [ 0.094905] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10484 11:14:06.245475 [ 0.099409] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10485 11:14:06.252510 [ 0.099489] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10486 11:14:06.261813 [ 0.099505] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10487 11:14:06.268881 [ 0.100077] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10488 11:14:06.275151 [ 0.102209] TCP: Hash tables configured (established 65536 bind 65536)
10489 11:14:06.281738 [ 0.102319] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10490 11:14:06.288251 [ 0.102510] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10491 11:14:06.295217 [ 0.102777] NET: Registered PF_UNIX/PF_LOCAL protocol family
10492 11:14:06.301627 [ 0.103013] RPC: Registered named UNIX socket transport module.
10493 11:14:06.305170 [ 0.103017] RPC: Registered udp transport module.
10494 11:14:06.308676 [ 0.103019] RPC: Registered tcp transport module.
10495 11:14:06.315246 [ 0.103020] RPC: Registered tcp NFSv4.1 backchannel transport module.
10496 11:14:06.318534 [ 0.103028] PCI: CLS 0 bytes, default 64
10497 11:14:06.324901 [ 0.103268] Unpacking initramfs...
10498 11:14:06.331948 [ 0.112010] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10499 11:14:06.338210 [ 0.112241] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10500 11:14:06.345176 [ 0.112674] kvm [1]: IPA Size Limit: 40 bits
10501 11:14:06.347887 [ 0.112701] kvm [1]: GICv3: no GICV resource entry
10502 11:14:06.354767 [ 0.112705] kvm [1]: disabling GICv2 emulation
10503 11:14:06.358022 [ 0.112719] kvm [1]: GIC system register CPU interface enabled
10504 11:14:06.361249 [ 0.112814] kvm [1]: vgic interrupt IRQ18
10505 11:14:06.368034 [ 0.112919] kvm [1]: VHE mode initialized successfully
10506 11:14:06.371357 [ 0.113836] Initialise system trusted keyrings
10507 11:14:06.377911 [ 0.113928] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10508 11:14:06.384559 [ 0.117201] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10509 11:14:06.391024 [ 0.117495] NFS: Registering the id_resolver key type
10510 11:14:06.394582 [ 0.117512] Key type id_resolver registered
10511 11:14:06.397547 [ 0.117514] Key type id_legacy registered
10512 11:14:06.404703 [ 0.117550] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10513 11:14:06.411016 [ 0.117555] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10514 11:14:06.417421 [ 0.117629] 9p: Installing v9fs 9p2000 file system support
10515 11:14:06.420773 [ 0.149631] Key type asymmetric registered
10516 11:14:06.427351 [ 0.149637] Asymmetric key parser 'x509' registered
10517 11:14:06.434433 [ 0.149682] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10518 11:14:06.437494 [ 0.149687] io scheduler mq-deadline registered
10519 11:14:06.440680 [ 0.149689] io scheduler kyber registered
10520 11:14:06.443834 [ 0.162216] EINJ: ACPI disabled.
10521 11:14:06.457576 [ 0.184127] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10522 11:14:06.467209 [ 0.184291] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10523 11:14:06.474144 [ 0.194178] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10524 11:14:06.477353 [ 0.195612] printk: console [ttyS0] disabled
10525 11:14:06.487184 [ 0.215766] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10526 11:14:06.490303 [ 0.840555] Freeing initrd memory: 17220K
10527 11:14:06.493395 [ 0.846746] printk: console [ttyS0] enabled
10528 11:14:06.500517 [ 1.506226] SuperH (H)SCI(F) driver initialized
10529 11:14:06.503276 [ 1.511230] msm_serial: driver initialized
10530 11:14:06.517008 [ 1.519821] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10531 11:14:06.523304 [ 1.528103] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10532 11:14:06.533592 [ 1.536385] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10533 11:14:06.543338 [ 1.544758] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10534 11:14:06.550134 [ 1.553203] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10535 11:14:06.560188 [ 1.561655] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10536 11:14:06.566514 [ 1.569935] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10537 11:14:06.576745 [ 1.578469] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10538 11:14:06.583298 [ 1.586751] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10539 11:14:06.591683 [ 1.601475] loop: module loaded
10540 11:14:06.601105 [ 1.607095] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10541 11:14:06.623358 [ 1.629588] mtk-pmic-keys: Failed to locate of_node [id: -1]
10542 11:14:06.626586 [ 1.635878] megasas: 07.719.03.00-rc1
10543 11:14:06.638931 [ 1.645158] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10544 11:14:06.650482 [ 1.654851] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10545 11:14:06.656673 [ 1.656086] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10546 11:14:06.666074 [ 1.671855] tun: Universal TUN/TAP device driver, 1.6
10547 11:14:06.673869 [ 1.672600] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10548 11:14:06.677502 [ 1.677659] thunder_xcv, ver 1.0
10549 11:14:06.677590 [ 1.686319] thunder_bgx, ver 1.0
10550 11:14:06.681338 [ 1.689555] nicpf, ver 1.0
10551 11:14:06.691811 [ 1.693304] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10552 11:14:06.703100 [ 1.700519] hns3: Copyright (c) 2017 Huawei Corporation.
10553 11:14:06.703198 [ 1.705846] hclge is initializing
10554 11:14:06.703704 [ 1.709165] e1000: Intel(R) PRO/1000 Network Driver
10555 11:14:06.707358 [ 1.714034] e1000: Copyright (c) 1999-2006 Intel Corporation.
10556 11:14:06.713857 [ 1.719786] e1000e: Intel(R) PRO/1000 Network Driver
10557 11:14:06.720864 [ 1.724742] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10558 11:14:06.725639 [ 1.730665] igb: Intel(R) Gigabit Ethernet Network Driver
10559 11:14:06.729260 [ 1.736055] igb: Copyright (c) 2007-2014 Intel Corporation.
10560 11:14:06.742724 [ 1.738368] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10561 11:14:06.745919 [ 1.741630] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10562 11:14:06.752521 [ 1.758642] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10563 11:14:06.756029 [ 1.764843] sky2: driver version 1.30
10564 11:14:06.763348 [ 1.769558] VFIO - User Level meta-driver version: 0.3
10565 11:14:06.771187 [ 1.777409] usbcore: registered new interface driver usb-storage
10566 11:14:06.777723 [ 1.783591] usbcore: registered new device driver onboard-usb-hub
10567 11:14:06.786609 [ 1.792356] mt6397-rtc mt6359-rtc: registered as rtc0
10568 11:14:06.796248 [ 1.797559] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:13:54 UTC (1685963634)
10569 11:14:06.799351 [ 1.806870] i2c_dev: i2c /dev entries driver
10570 11:14:06.815283 [ 1.818195] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10571 11:14:06.821709 [ 1.828144] sdhci: Secure Digital Host Controller Interface driver
10572 11:14:06.828771 [ 1.834320] sdhci: Copyright(c) Pierre Ossman
10573 11:14:06.835462 [ 1.839480] Synopsys Designware Multimedia Card Interface Driver
10574 11:14:06.838622 [ 1.845938] mmc0: CQHCI version 5.10
10575 11:14:06.845480 [ 1.846369] sdhci-pltfm: SDHCI platform and OF driver helper
10576 11:14:06.852369 [ 1.857260] ledtrig-cpu: registered to indicate activity on CPUs
10577 11:14:06.858304 [ 1.864313] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10578 11:14:06.865442 [ 1.871447] usbcore: registered new interface driver usbhid
10579 11:14:06.868659 [ 1.877013] usbhid: USB HID core driver
10580 11:14:06.875277 [ 1.881005] spi_master spi0: will run message pump with realtime priority
10581 11:14:06.918242 [ 1.917725] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10582 11:14:06.933979 [ 1.933198] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10583 11:14:06.941201 [ 1.947499] mmc0: Command Queue Engine enabled
10584 11:14:06.944941 [ 1.947762] cros-ec-spi spi0.0: Chrome EC device registered
10585 11:14:06.951522 [ 1.951960] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10586 11:14:06.958282 [ 1.964568] mmcblk0: mmc0:0001 DA4128 116 GiB
10587 11:14:06.971013 [ 1.973795] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10588 11:14:06.977435 [ 1.974058] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10589 11:14:06.981134 [ 1.984938] NET: Registered PF_PACKET protocol family
10590 11:14:06.987654 [ 1.991244] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10591 11:14:06.990660 [ 1.993687] 9pnet: Installing 9P2000 support
10592 11:14:06.997796 [ 1.999484] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10593 11:14:07.000852 [ 2.002843] Key type dns_resolver registered
10594 11:14:07.007898 [ 2.008734] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10595 11:14:07.011024 [ 2.012523] registered taskstats version 1
10596 11:14:07.017395 [ 2.022433] Loading compiled-in X.509 certificates
10597 11:14:07.048561 [ 2.048258] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 11:14:07.058803 [ 2.058659] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10599 11:14:07.068586 [ 2.070929] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10600 11:14:07.079528 [ 2.085508] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10601 11:14:07.085665 [ 2.092014] xhci-mtk 11200000.usb: xHCI Host Controller
10602 11:14:07.092419 [ 2.097252] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10603 11:14:07.102491 [ 2.104834] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10604 11:14:07.109066 [ 2.114001] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10605 11:14:07.112312 [ 2.119837] xhci-mtk 11200000.usb: xHCI Host Controller
10606 11:14:07.122295 [ 2.125061] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10607 11:14:07.129269 [ 2.132453] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10608 11:14:07.132539 [ 2.140069] hub 1-0:1.0: USB hub found
10609 11:14:07.135804 [ 2.143840] hub 1-0:1.0: 1 port detected
10610 11:14:07.145979 [ 2.147923] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10611 11:14:07.149209 [ 2.156289] hub 2-0:1.0: USB hub found
10612 11:14:07.152235 [ 2.160045] hub 2-0:1.0: 1 port detected
10613 11:14:07.160908 [ 2.166966] mtk-msdc 11f70000.mmc: Got CD GPIO
10614 11:14:07.177145 [ 2.180114] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10615 11:14:07.183848 [ 2.187878] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10616 11:14:07.193612 [ 2.195600] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10617 11:14:07.200162 [ 2.205001] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10618 11:14:07.210447 [ 2.212822] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10619 11:14:07.217500 [ 2.220577] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10620 11:14:07.223923 [ 2.228231] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10621 11:14:07.230323 [ 2.235791] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10622 11:14:07.240604 [ 2.243353] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10623 11:14:07.250851 [ 2.253832] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10624 11:14:07.257900 [ 2.261940] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10625 11:14:07.268039 [ 2.270036] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10626 11:14:07.274170 [ 2.278119] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10627 11:14:07.284501 [ 2.286201] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10628 11:14:07.290969 [ 2.294282] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10629 11:14:07.297549 [ 2.302364] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10630 11:14:07.307645 [ 2.310445] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10631 11:14:07.314132 [ 2.318527] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10632 11:14:07.324319 [ 2.326609] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10633 11:14:07.331181 [ 2.334691] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10634 11:14:07.340938 [ 2.342773] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10635 11:14:07.347730 [ 2.350855] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10636 11:14:07.354050 [ 2.358937] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10637 11:14:07.364382 [ 2.367021] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10638 11:14:07.370670 [ 2.375674] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10639 11:14:07.377443 [ 2.382831] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10640 11:14:07.384523 [ 2.389613] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10641 11:14:07.390684 [ 2.396461] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10642 11:14:07.397636 [ 2.403487] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10643 11:14:07.407455 [ 2.410127] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10644 11:14:07.417656 [ 2.419007] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10645 11:14:07.424066 [ 2.427872] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10646 11:14:07.434272 [ 2.436915] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10647 11:14:07.444522 [ 2.446129] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10648 11:14:07.454035 [ 2.455343] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10649 11:14:07.460839 [ 2.464209] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10650 11:14:07.470413 [ 2.473423] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10651 11:14:07.481065 [ 2.482289] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10652 11:14:07.490928 [ 2.491329] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10653 11:14:07.500866 [ 2.501234] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10654 11:14:07.510702 [ 2.512782] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10655 11:14:07.517127 [ 2.522431] Trying to probe devices needed for running init ...
10656 11:14:07.561162 [ 2.567690] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10657 11:14:07.717433 [ 2.723713] hub 1-1:1.0: USB hub found
10658 11:14:07.720522 [ 2.727806] hub 1-1:1.0: 4 ports detected
10659 11:14:07.841945 [ 2.847938] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10660 11:14:07.869692 [ 2.876203] hub 2-1:1.0: USB hub found
10661 11:14:07.872864 [ 2.880337] hub 2-1:1.0: 3 ports detected
10662 11:14:08.040539 [ 3.043714] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10663 11:14:08.173786 [ 3.179819] hub 1-1.4:1.0: USB hub found
10664 11:14:08.176828 [ 3.184256] hub 1-1.4:1.0: 2 ports detected
10665 11:14:08.253109 [ 3.255958] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10666 11:14:08.472608 [ 3.475718] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10667 11:14:08.664885 [ 3.667716] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10668 11:14:19.805416 [ 14.816267] ALSA device list:
10669 11:14:19.808604 [ 14.819242] No soundcards found.
10670 11:14:19.823948 [ 14.831422] Freeing unused kernel memory: 8384K
10671 11:14:19.826995 [ 14.836098] Run /init as init process
10672 11:14:19.835939 Loading, please wait...
10673 11:14:19.855870 Starting version 247.3-7+deb11u2
10674 11:14:20.169959 [ 15.174370] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10675 11:14:20.180938 [ 15.188379] remoteproc remoteproc0: scp is available
10676 11:14:20.190903 [ 15.194043] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10677 11:14:20.197314 [ 15.203763] remoteproc remoteproc0: powering up scp
10678 11:14:20.207697 [ 15.211822] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10679 11:14:20.213847 [ 15.221491] remoteproc remoteproc0: request_firmware failed: -2
10680 11:14:20.224815 [ 15.229258] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10681 11:14:20.231680 [ 15.237495] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10682 11:14:20.241268 [ 15.245998] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10683 11:14:20.253824 [ 15.258409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 11:14:20.260332 [ 15.263552] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10685 11:14:20.267202 [ 15.266304] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 11:14:20.274045 [ 15.269373] usbcore: registered new interface driver r8152
10687 11:14:20.280537 [ 15.287032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 11:14:20.287090 [ 15.288367] mc: Linux media interface: v0.10
10689 11:14:20.294269 [ 15.288776] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10690 11:14:20.300814 [ 15.288776] Fallback method does not support PEC.
10691 11:14:20.307296 [ 15.296516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 11:14:20.314206 [ 15.296700] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10693 11:14:20.321071 [ 15.299099] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10694 11:14:20.331203 [ 15.305779] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10695 11:14:20.338082 [ 15.312362] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 11:14:20.347913 [ 15.341534] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10697 11:14:20.354208 [ 15.342830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 11:14:20.361343 [ 15.367036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 11:14:20.368044 [ 15.367185] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10700 11:14:20.378042 [ 15.374896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 11:14:20.387866 [ 15.376769] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10702 11:14:20.394567 [ 15.376792] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10703 11:14:20.397885 [ 15.376805] pci_bus 0000:00: root bus resource [bus 00-ff]
10704 11:14:20.404500 [ 15.376814] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10705 11:14:20.413997 [ 15.376820] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10706 11:14:20.420939 [ 15.376862] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10707 11:14:20.427261 [ 15.376887] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10708 11:14:20.434732 [ 15.376978] pci 0000:00:00.0: supports D1 D2
10709 11:14:20.440476 [ 15.376982] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10710 11:14:20.447777 [ 15.377243] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10711 11:14:20.457449 [ 15.378643] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10712 11:14:20.460449 [ 15.378749] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10713 11:14:20.470876 [ 15.378779] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10714 11:14:20.477402 [ 15.378799] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10715 11:14:20.484186 [ 15.378818] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10716 11:14:20.487274 [ 15.378931] pci 0000:01:00.0: supports D1 D2
10717 11:14:20.493762 [ 15.378933] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10718 11:14:20.500610 [ 15.391546] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10719 11:14:20.510206 [ 15.399418] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 11:14:20.517275 [ 15.406050] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10721 11:14:20.523787 [ 15.411509] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 11:14:20.533739 [ 15.418352] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10723 11:14:20.540120 [ 15.427980] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 11:14:20.550179 [ 15.427986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 11:14:20.557192 [ 15.428050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 11:14:20.563058 [ 15.434013] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10727 11:14:20.573249 [ 15.441198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 11:14:20.580154 [ 15.441205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 11:14:20.586577 [ 15.441211] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 11:14:20.596293 [ 15.445609] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10731 11:14:20.603241 [ 15.447615] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10732 11:14:20.613086 [ 15.448583] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10733 11:14:20.619633 [ 15.448598] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10734 11:14:20.629855 [ 15.452079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 11:14:20.636257 [ 15.452654] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 11:14:20.642551 [ 15.460985] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10737 11:14:20.649357 [ 15.462132] videodev: Linux video capture interface: v2.00
10738 11:14:20.656189 [ 15.469400] usbcore: registered new interface driver cdc_ether
10739 11:14:20.659186 [ 15.475053] pci 0000:00:00.0: PCI bridge to [bus 01]
10740 11:14:20.666302 [ 15.489913] usbcore: registered new interface driver r8153_ecm
10741 11:14:20.672594 [ 15.496904] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10742 11:14:20.679517 [ 15.497773] Bluetooth: Core ver 2.22
10743 11:14:20.682541 [ 15.497833] NET: Registered PF_BLUETOOTH protocol family
10744 11:14:20.689095 [ 15.497836] Bluetooth: HCI device and connection manager initialized
10745 11:14:20.695624 [ 15.497862] Bluetooth: HCI socket layer initialized
10746 11:14:20.699162 [ 15.497867] Bluetooth: L2CAP socket layer initialized
10747 11:14:20.705933 [ 15.497898] Bluetooth: SCO socket layer initialized
10748 11:14:20.712358 [ 15.502875] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10749 11:14:20.715439 [ 15.508780] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10750 11:14:20.728962 [ 15.515958] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10751 11:14:20.735494 [ 15.523422] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10752 11:14:20.742037 [ 15.523603] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10753 11:14:20.745862 [ 15.524244] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10754 11:14:20.752235 [ 15.530477] usbcore: registered new interface driver uvcvideo
10755 11:14:20.755931 [ 15.531644] r8152 2-1.3:1.0 eth0: v1.12.13
10756 11:14:20.762343 [ 15.540803] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10757 11:14:20.769065 [ 15.548135] usbcore: registered new interface driver btusb
10758 11:14:20.778505 [ 15.549061] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10759 11:14:20.785264 [ 15.549073] Bluetooth: hci0: Failed to load firmware file (-2)
10760 11:14:20.788498 [ 15.549078] Bluetooth: hci0: Failed to set up firmware (-2)
10761 11:14:20.798696 [ 15.549082] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10762 11:14:20.821142 [ 15.825289] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10763 11:14:20.835867 [ 15.843892] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10764 11:14:20.845955 [ 15.850533] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10765 11:14:20.852834 [ 15.859153] cfg80211: failed to load regulatory.db
10766 11:14:20.897163 [ 15.901484] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10767 11:14:20.900365 [ 15.908736] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10768 11:14:20.927264 [ 15.935161] mt7921e 0000:01:00.0: ASIC revision: 79610010
10769 11:14:21.034155 [ 16.035084] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10770 11:14:21.051855 Begin: Loading essential drivers ... done.
10771 11:14:21.054680 Begin: Running /scripts/init-premount ... done.
10772 11:14:21.061705 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10773 11:14:21.071157 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10774 11:14:21.074433 Device /sys/class/net/enx00e04c787aaa found
10775 11:14:21.074576 done.
10776 11:14:21.152544 [ 16.154086] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 11:14:21.168097 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10778 11:14:21.271961 [ 16.273546] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 11:14:21.388047 [ 16.389294] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 11:14:21.503795 [ 16.505206] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 11:14:21.619844 [ 16.621104] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 11:14:21.735759 [ 16.737131] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 11:14:21.851696 [ 16.853015] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 11:14:21.967728 [ 16.968997] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 11:14:22.084065 [ 17.085091] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 11:14:22.160420 [ 17.168053] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10787 11:14:22.191175 [ 17.198985] mt7921e 0000:01:00.0: hardware init failed
10788 11:14:22.289575 IP-Config: no response after 2 secs - giving up
10789 11:14:22.322882 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10790 11:14:23.428064 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10791 11:14:23.434517 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10792 11:14:23.441209 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10793 11:14:23.447829 host : mt8192-asurada-spherion-r0-cbg-0
10794 11:14:23.454926 domain : lava-rack
10795 11:14:23.458068 rootserver: 192.168.201.1 rootpath:
10796 11:14:23.461265 filename :
10797 11:14:23.498197 done.
10798 11:14:23.504462 Begin: Running /scripts/nfs-bottom ... done.
10799 11:14:23.521380 Begin: Running /scripts/init-bottom ... done.
10800 11:14:24.589649 [ 19.597656] NET: Registered PF_INET6 protocol family
10801 11:14:24.596245 [ 19.604074] Segment Routing with IPv6
10802 11:14:24.599099 [ 19.607798] In-situ OAM (IOAM) with IPv6
10803 11:14:24.698726 [ 19.690360] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10804 11:14:24.705161 [ 19.713773] systemd[1]: Detected architecture arm64.
10805 11:14:24.721997
10806 11:14:24.725758 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10807 11:14:24.725865
10808 11:14:24.740935 [ 19.749254] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10809 11:14:25.190937 [ 20.195708] systemd[1]: Queued start job for default target Graphical Interface.
10810 11:14:25.212579 [ 20.220793] systemd[1]: Created slice system-getty.slice.
10811 11:14:25.219031 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10812 11:14:25.235778 [ 20.244365] systemd[1]: Created slice system-modprobe.slice.
10813 11:14:25.242400 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10814 11:14:25.260147 [ 20.268311] systemd[1]: Created slice system-serial\x2dgetty.slice.
10815 11:14:25.266838 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10816 11:14:25.284246 [ 20.292746] systemd[1]: Created slice User and Session Slice.
10817 11:14:25.291222 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10818 11:14:25.311118 [ 20.316278] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10819 11:14:25.317896 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10820 11:14:25.338856 [ 20.343788] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10821 11:14:25.345571 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10822 11:14:25.366465 [ 20.367803] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10823 11:14:25.373154 [ 20.379497] systemd[1]: Reached target Local Encrypted Volumes.
10824 11:14:25.379794 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10825 11:14:25.391695 [ 20.399969] systemd[1]: Reached target Paths.
10826 11:14:25.394983 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10827 11:14:25.411573 [ 20.419766] systemd[1]: Reached target Remote File Systems.
10828 11:14:25.418537 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10829 11:14:25.431314 [ 20.439742] systemd[1]: Reached target Slices.
10830 11:14:25.434580 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10831 11:14:25.451287 [ 20.459757] systemd[1]: Reached target Swap.
10832 11:14:25.454919 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10833 11:14:25.471653 [ 20.480075] systemd[1]: Listening on initctl Compatibility Named Pipe.
10834 11:14:25.481510 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10835 11:14:25.488325 [ 20.495108] systemd[1]: Listening on Journal Audit Socket.
10836 11:14:25.495199 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10837 11:14:25.508018 [ 20.516608] systemd[1]: Listening on Journal Socket (/dev/log).
10838 11:14:25.515085 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10839 11:14:25.532081 [ 20.540104] systemd[1]: Listening on Journal Socket.
10840 11:14:25.538180 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10841 11:14:25.552406 [ 20.560669] systemd[1]: Listening on Network Service Netlink Socket.
10842 11:14:25.561845 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10843 11:14:25.578148 [ 20.586354] systemd[1]: Listening on udev Control Socket.
10844 11:14:25.585035 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10845 11:14:25.599802 [ 20.608019] systemd[1]: Listening on udev Kernel Socket.
10846 11:14:25.606303 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10847 11:14:25.655513 [ 20.664011] systemd[1]: Mounting Huge Pages File System...
10848 11:14:25.662321 Mounting [0;1;39mHuge Pages File System[0m...
10849 11:14:25.677409 [ 20.685770] systemd[1]: Mounting POSIX Message Queue File System...
10850 11:14:25.683820 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10851 11:14:25.702056 [ 20.710196] systemd[1]: Mounting Kernel Debug File System...
10852 11:14:25.708684 Mounting [0;1;39mKernel Debug File System[0m...
10853 11:14:25.726907 [ 20.731927] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10854 11:14:25.745641 [ 20.751180] systemd[1]: Starting Create list of static device nodes for the current kernel...
10855 11:14:25.752490 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10856 11:14:25.769941 [ 20.778421] systemd[1]: Starting Load Kernel Module configfs...
10857 11:14:25.776628 Starting [0;1;39mLoad Kernel Module configfs[0m...
10858 11:14:25.794024 [ 20.802443] systemd[1]: Starting Load Kernel Module drm...
10859 11:14:25.800823 Starting [0;1;39mLoad Kernel Module drm[0m...
10860 11:14:25.818030 [ 20.826365] systemd[1]: Starting Load Kernel Module fuse...
10861 11:14:25.824431 Starting [0;1;39mLoad Kernel Module fuse[0m...
10862 11:14:25.851856 [ 20.860280] fuse: init (API version 7.37)
10863 11:14:25.858796 [ 20.860913] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10864 11:14:25.869518 [ 20.877840] systemd[1]: Starting Journal Service...
10865 11:14:25.872667 Starting [0;1;39mJournal Service[0m...
10866 11:14:25.893546 [ 20.901938] systemd[1]: Starting Load Kernel Modules...
10867 11:14:25.899874 Starting [0;1;39mLoad Kernel Modules[0m...
10868 11:14:25.921821 [ 20.926808] systemd[1]: Starting Remount Root and Kernel File Systems...
10869 11:14:25.924886 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10870 11:14:25.942924 [ 20.950814] systemd[1]: Starting Coldplug All udev Devices...
10871 11:14:25.949257 Starting [0;1;39mColdplug All udev Devices[0m...
10872 11:14:25.966557 [ 20.974865] systemd[1]: Mounted Huge Pages File System.
10873 11:14:25.973116 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10874 11:14:25.987883 [ 20.996223] systemd[1]: Mounted POSIX Message Queue File System.
10875 11:14:25.994312 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10876 11:14:26.016107 [ 21.024184] systemd[1]: Mounted Kernel Debug File System.
10877 11:14:26.023059 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10878 11:14:26.029560 [ 21.036206] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 11:14:26.041049 [ 21.045903] systemd[1]: Finished Create list of static device nodes for the current kernel.
10880 11:14:26.047904 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10881 11:14:26.059609 [ 21.064589] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 11:14:26.065839 [ 21.074252] systemd[1]: modprobe@configfs.service: Succeeded.
10883 11:14:26.072850 [ 21.080760] systemd[1]: Finished Load Kernel Module configfs.
10884 11:14:26.079170 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10885 11:14:26.096557 [ 21.104510] systemd[1]: modprobe@drm.service: Succeeded.
10886 11:14:26.103569 [ 21.110372] systemd[1]: Finished Load Kernel Module drm.
10887 11:14:26.110404 [ 21.111318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 11:14:26.116701 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10889 11:14:26.133403 [ 21.140777] systemd[1]: modprobe@fuse.service: Succeeded.
10890 11:14:26.143237 [ 21.146327] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 11:14:26.146378 [ 21.147040] systemd[1]: Finished Load Kernel Module fuse.
10892 11:14:26.153441 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10893 11:14:26.170783 [ 21.175908] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 11:14:26.177392 [ 21.176958] systemd[1]: Finished Load Kernel Modules.
10895 11:14:26.180685 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10896 11:14:26.196713 [ 21.205340] systemd[1]: Finished Remount Root and Kernel File Systems.
10897 11:14:26.207094 [ 21.205489] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 11:14:26.213374 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10899 11:14:26.235934 [ 21.241024] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 11:14:26.252257 [ 21.260341] systemd[1]: Mounting FUSE Control File System...
10901 11:14:26.266213 Mounting [0;1;39mFUSE Control File Sys[ 21.270323] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 11:14:26.266343 tem[0m...
10903 11:14:26.286978 [ 21.294387] systemd[1]: Mounting Kernel Configuration File System...
10904 11:14:26.296452 [ 21.300371] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 11:14:26.303469 Mounting [0;1;39mKernel Configuration File System[0m...
10906 11:14:26.323125 [ 21.327353] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10907 11:14:26.329612 [ 21.329944] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 11:14:26.339375 [ 21.335982] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10909 11:14:26.348374 [ 21.356141] systemd[1]: Starting Load/Save Random Seed...
10910 11:14:26.351407 Starting [0;1;39mLoad/Save Random Seed[0m...
10911 11:14:26.370652 [ 21.378807] systemd[1]: Starting Apply Kernel Variables...
10912 11:14:26.377786 Starting [0;1;39mApply Kernel Variables[0m...
10913 11:14:26.395996 [ 21.404230] systemd[1]: Starting Create System Users...
10914 11:14:26.402362 Starting [0;1;39mCreate System Users[0m...
10915 11:14:26.417742 [ 21.425922] systemd[1]: Started Journal Service.
10916 11:14:26.420904 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10917 11:14:26.439491 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10918 11:14:26.456351 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10919 11:14:26.473081 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10920 11:14:26.488439 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10921 11:14:26.504899 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10922 11:14:26.548268 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10923 11:14:26.566615 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10924 11:14:26.587319 [ 21.592426] systemd-journald[294]: Received client request to flush runtime journal.
10925 11:14:26.643627 [ 21.642243] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10926 11:14:26.650244 [ 21.657665] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10927 11:14:26.680827 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10928 11:14:26.699356 See 'systemctl status systemd-udev-trigger.service' for details.
10929 11:14:27.662616 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10930 11:14:27.676067 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10931 11:14:27.691366 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10932 11:14:27.763199 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10933 11:14:27.978445 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10934 11:14:28.023893 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10935 11:14:28.052950 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10936 11:14:28.121219 Starting [0;1;39mNetwork Service[0m...
10937 11:14:28.271422 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10938 11:14:28.447892 Starting [0;1;39mNetwork Time Synchronization[0m...
10939 11:14:28.469165 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10940 11:14:28.620704 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10941 11:14:28.677328 [ 23.685818] remoteproc remoteproc0: powering up scp
10942 11:14:28.713820 [ 23.718901] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10943 11:14:28.720280 [ 23.728594] remoteproc remoteproc0: request_firmware failed: -2
10944 11:14:28.726902 [ 23.734516] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10945 11:14:28.842572 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10946 11:14:28.884525 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10947 11:14:28.919662 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10948 11:14:28.935283 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10949 11:14:28.954725 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10950 11:14:29.007245 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10951 11:14:29.033061 Starting [0;1;39mNetwork Name Resolution[0m...
10952 11:14:29.047727 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10953 11:14:29.068239 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10954 11:14:29.083582 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10955 11:14:29.102484 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10956 11:14:29.115588 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10957 11:14:29.131353 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10958 11:14:29.174380 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10959 11:14:29.197368 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10960 11:14:29.226046 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10961 11:14:29.271290 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10962 11:14:29.283322 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10963 11:14:29.312363 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10964 11:14:29.327268 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10965 11:14:29.342966 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10966 11:14:29.387616 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10967 11:14:29.531346 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10968 11:14:29.635555 Starting [0;1;39mUser Login Management[0m...
10969 11:14:29.653947 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10970 11:14:29.859696 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10971 11:14:29.875571 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10972 11:14:29.898338 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10973 11:14:29.931335 Starting [0;1;39mPermit User Sessions[0m...
10974 11:14:29.947784 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10975 11:14:29.968928 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10976 11:14:29.989769 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10977 11:14:30.039885 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10978 11:14:30.062599 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10979 11:14:30.083184 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10980 11:14:30.099759 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10981 11:14:30.115743 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10982 11:14:30.131213 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10983 11:14:30.166996 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10984 11:14:30.205492 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10985 11:14:30.274772
10986 11:14:30.274896
10987 11:14:30.278303 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10988 11:14:30.278422
10989 11:14:30.281451 debian-bullseye-arm64 login: root (automatic login)
10990 11:14:30.281536
10991 11:14:30.281602
10992 11:14:30.549348 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023 aarch64
10993 11:14:30.549496
10994 11:14:30.555900 The programs included with the Debian GNU/Linux system are free software;
10995 11:14:30.562023 the exact distribution terms for each program are described in the
10996 11:14:30.565881 individual files in /usr/share/doc/*/copyright.
10997 11:14:30.565962
10998 11:14:30.572361 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10999 11:14:30.572460 permitted by applicable law.
11000 11:14:31.265698 Matched prompt #10: / #
11002 11:14:31.265974 Setting prompt string to ['/ #']
11003 11:14:31.266071 end: 2.2.5.1 login-action (duration 00:00:26) [common]
11005 11:14:31.266266 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11006 11:14:31.266356 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11007 11:14:31.266430 Setting prompt string to ['/ #']
11008 11:14:31.266492 Forcing a shell prompt, looking for ['/ #']
11010 11:14:31.316739 / #
11011 11:14:31.317008 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11012 11:14:31.317157 Waiting using forced prompt support (timeout 00:02:30)
11013 11:14:31.322139
11014 11:14:31.322549 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11015 11:14:31.322752 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11017 11:14:31.423501 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591219/extract-nfsrootfs-1v2va2w7'
11018 11:14:31.429193 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591219/extract-nfsrootfs-1v2va2w7'
11020 11:14:31.530560 / # export NFS_SERVER_IP='192.168.201.1'
11021 11:14:31.537250 export NFS_SERVER_IP='192.168.201.1'
11022 11:14:31.538039 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11023 11:14:31.538543 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11024 11:14:31.539014 end: 2 depthcharge-action (duration 00:01:24) [common]
11025 11:14:31.539516 start: 3 lava-test-retry (timeout 00:07:52) [common]
11026 11:14:31.539987 start: 3.1 lava-test-shell (timeout 00:07:52) [common]
11027 11:14:31.540452 Using namespace: common
11029 11:14:31.641534 / # #
11030 11:14:31.642105 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11031 11:14:31.647159 #
11032 11:14:31.647935 Using /lava-10591219
11034 11:14:31.749042 / # export SHELL=/bin/bash
11035 11:14:31.755264 export SHELL=/bin/bash
11037 11:14:31.856825 / # . /lava-10591219/environment
11038 11:14:31.862835 . /lava-10591219/environment
11040 11:14:31.968516 / # /lava-10591219/bin/lava-test-runner /lava-10591219/0
11041 11:14:31.969068 Test shell timeout: 10s (minimum of the action and connection timeout)
11042 11:14:31.974285 /lava-10591219/bin/lava-test-runner /lava-10591219/0
11043 11:14:32.193496 + export TESTRUN_ID=0_timesync-off
11044 11:14:32.196874 + TESTRUN_ID=0_timesync-off
11045 11:14:32.200060 + cd /lava-10591219/0/tests/0_timesync-off
11046 11:14:32.203490 ++ cat uuid
11047 11:14:32.203574 + UUID=10591219_1.6.2.3.1
11048 11:14:32.206386 + set +x
11049 11:14:32.210114 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10591219_1.6.2.3.1>
11050 11:14:32.210376 Received signal: <STARTRUN> 0_timesync-off 10591219_1.6.2.3.1
11051 11:14:32.210452 Starting test lava.0_timesync-off (10591219_1.6.2.3.1)
11052 11:14:32.210543 Skipping test definition patterns.
11053 11:14:32.213234 + systemctl stop systemd-timesyncd
11054 11:14:32.236688 + set +x
11055 11:14:32.240256 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10591219_1.6.2.3.1>
11056 11:14:32.240513 Received signal: <ENDRUN> 0_timesync-off 10591219_1.6.2.3.1
11057 11:14:32.240598 Ending use of test pattern.
11058 11:14:32.240662 Ending test lava.0_timesync-off (10591219_1.6.2.3.1), duration 0.03
11060 11:14:32.285394 + export TESTRUN_ID=1_kselftest-rtc
11061 11:14:32.288597 + TESTRUN_ID=1_kselftest-rtc
11062 11:14:32.292284 + cd /lava-10591219/0/tests/1_kselftest-rtc
11063 11:14:32.295208 ++ cat uuid
11064 11:14:32.295315 + UUID=10591219_1.6.2.3.5
11065 11:14:32.298827 + set +x
11066 11:14:32.302363 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 10591219_1.6.2.3.5>
11067 11:14:32.302616 Received signal: <STARTRUN> 1_kselftest-rtc 10591219_1.6.2.3.5
11068 11:14:32.302686 Starting test lava.1_kselftest-rtc (10591219_1.6.2.3.5)
11069 11:14:32.302778 Skipping test definition patterns.
11070 11:14:32.305397 + cd ./automated/linux/kselftest/
11071 11:14:32.331856 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11072 11:14:32.343918 INFO: install_deps skipped
11073 11:14:32.442980 --2023-06-05 11:14:20-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11074 11:14:32.446009 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11075 11:14:32.587745 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11076 11:14:32.733963 HTTP request sent, awaiting response... 200 OK
11077 11:14:32.737052 Length: 2714204 (2.6M) [application/octet-stream]
11078 11:14:32.741407 Saving to: 'kselftest.tar.xz'
11079 11:14:32.741843
11080 11:14:32.742240
11081 11:14:33.033413 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11082 11:14:33.327387 kselftest.tar.xz 1%[ ] 47.81K 164KB/s
11083 11:14:33.815607 kselftest.tar.xz 8%[> ] 214.67K 367KB/s
11084 11:14:34.060882 kselftest.tar.xz 31%[=====> ] 825.06K 768KB/s
11085 11:14:34.120982 kselftest.tar.xz 93%[=================> ] 2.41M 1.83MB/s
11086 11:14:34.127451 kselftest.tar.xz 100%[===================>] 2.59M 1.88MB/s in 1.4s
11087 11:14:34.127577
11088 11:14:34.361850 2023-06-05 11:14:22 (1.88 MB/s) - 'kselftest.tar.xz' saved [2714204/2714204]
11089 11:14:34.361990
11090 11:14:38.805097 skiplist:
11091 11:14:38.808307 ========================================
11092 11:14:38.811700 ========================================
11093 11:14:38.846810 rtc:rtctest
11094 11:14:38.862124 ============== Tests to run ===============
11095 11:14:38.862219 rtc:rtctest
11096 11:14:38.865601 ===========End Tests to run ===============
11097 11:14:38.940237 [ 33.949884] kselftest: Running tests in rtc
11098 11:14:38.948593 TAP version 13
11099 11:14:38.960245 1..1
11100 11:14:38.988200 # selftests: rtc: rtctest
11101 11:14:39.336019 # TAP version 13
11102 11:14:39.336162 # 1..8
11103 11:14:39.339214 # # Starting 8 tests from 2 test cases.
11104 11:14:39.342531 # # RUN rtc.date_read ...
11105 11:14:39.349202 # # rtctest.c:49:date_read:Current RTC date/time is 05/06/2023 11:14:27.
11106 11:14:39.352318 # # OK rtc.date_read
11107 11:14:39.355755 # ok 1 rtc.date_read
11108 11:14:39.359072 # # RUN rtc.date_read_loop ...
11109 11:14:39.368759 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11110 11:14:51.033156 [ 46.047642] vpu: disabling
11111 11:14:51.036243 [ 46.050429] vproc2: disabling
11112 11:14:51.039468 [ 46.053441] vproc1: disabling
11113 11:14:51.042805 [ 46.056439] vaud18: disabling
11114 11:14:51.046074 [ 46.059590] vsram_others: disabling
11115 11:14:51.049280 [ 46.063192] va09: disabling
11116 11:14:51.052598 [ 46.066036] vsram_md: disabling
11117 11:14:51.055912 [ 46.069268] Vgpu: disabling
11118 11:15:09.868078 # # rtctest.c:115:date_read_loop:Performed 2726 RTC time reads.
11119 11:15:09.871081 # # OK rtc.date_read_loop
11120 11:15:09.874462 # ok 2 rtc.date_read_loop
11121 11:15:09.877705 # # RUN rtc.uie_read ...
11122 11:15:12.848671 # # OK rtc.uie_read
11123 11:15:12.851870 # ok 3 rtc.uie_read
11124 11:15:12.855150 # # RUN rtc.uie_select ...
11125 11:15:15.847723 # # OK rtc.uie_select
11126 11:15:15.851200 # ok 4 rtc.uie_select
11127 11:15:15.854309 # # RUN rtc.alarm_alm_set ...
11128 11:15:15.860701 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 11:15:07.
11129 11:15:15.864598 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11130 11:15:15.870721 # # alarm_alm_set: Test terminated by assertion
11131 11:15:15.874444 # # FAIL rtc.alarm_alm_set
11132 11:15:15.874547 # not ok 5 rtc.alarm_alm_set
11133 11:15:15.880941 # # RUN rtc.alarm_wkalm_set ...
11134 11:15:15.887369 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 05/06/2023 11:15:07.
11135 11:15:18.850109 # # OK rtc.alarm_wkalm_set
11136 11:15:18.850670 # ok 6 rtc.alarm_wkalm_set
11137 11:15:18.857243 # # RUN rtc.alarm_alm_set_minute ...
11138 11:15:18.859952 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 11:16:00.
11139 11:15:18.867164 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11140 11:15:18.873456 # # alarm_alm_set_minute: Test terminated by assertion
11141 11:15:18.876697 # # FAIL rtc.alarm_alm_set_minute
11142 11:15:18.879919 # not ok 7 rtc.alarm_alm_set_minute
11143 11:15:18.883126 # # RUN rtc.alarm_wkalm_set_minute ...
11144 11:15:18.889634 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 05/06/2023 11:16:00.
11145 11:16:11.844165 # # OK rtc.alarm_wkalm_set_minute
11146 11:16:11.847550 # ok 8 rtc.alarm_wkalm_set_minute
11147 11:16:11.847673 # # FAILED: 6 / 8 tests passed.
11148 11:16:11.854359 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11149 11:16:11.857441 not ok 1 selftests: rtc: rtctest # exit=1
11150 11:16:12.355913 rtc_rtctest_rtc_date_read pass
11151 11:16:12.359421 rtc_rtctest_rtc_date_read_loop pass
11152 11:16:12.362450 rtc_rtctest_rtc_uie_read pass
11153 11:16:12.365703 rtc_rtctest_rtc_uie_select pass
11154 11:16:12.368989 rtc_rtctest_rtc_alarm_alm_set fail
11155 11:16:12.372709 rtc_rtctest_rtc_alarm_wkalm_set pass
11156 11:16:12.375768 rtc_rtctest_rtc_alarm_alm_set_minute fail
11157 11:16:12.379363 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11158 11:16:12.382317 rtc_rtctest fail
11159 11:16:12.385817 + ../../utils/send-to-lava.sh ./output/result.txt
11160 11:16:12.427203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11161 11:16:12.427495 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11163 11:16:12.458335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11164 11:16:12.458598 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11166 11:16:12.496254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11167 11:16:12.496512 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11169 11:16:12.537101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11170 11:16:12.537366 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11172 11:16:12.574344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11173 11:16:12.574613 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11175 11:16:12.609487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11176 11:16:12.609746 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11178 11:16:12.641804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11179 11:16:12.642061 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11181 11:16:12.676516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11182 11:16:12.676781 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11184 11:16:12.714075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11185 11:16:12.714185 + set +x
11186 11:16:12.714425 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11188 11:16:12.720983 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 10591219_1.6.2.3.5>
11189 11:16:12.721236 Received signal: <ENDRUN> 1_kselftest-rtc 10591219_1.6.2.3.5
11190 11:16:12.721310 Ending use of test pattern.
11191 11:16:12.721374 Ending test lava.1_kselftest-rtc (10591219_1.6.2.3.5), duration 100.42
11193 11:16:12.724147 <LAVA_TEST_RUNNER EXIT>
11194 11:16:12.724402 ok: lava_test_shell seems to have completed
11195 11:16:12.724541 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
11196 11:16:12.724637 end: 3.1 lava-test-shell (duration 00:01:41) [common]
11197 11:16:12.724723 end: 3 lava-test-retry (duration 00:01:41) [common]
11198 11:16:12.724808 start: 4 finalize (timeout 00:06:11) [common]
11199 11:16:12.724899 start: 4.1 power-off (timeout 00:00:30) [common]
11200 11:16:12.725056 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11201 11:16:12.801969 >> Command sent successfully.
11202 11:16:12.804366 Returned 0 in 0 seconds
11203 11:16:12.904719 end: 4.1 power-off (duration 00:00:00) [common]
11205 11:16:12.905037 start: 4.2 read-feedback (timeout 00:06:11) [common]
11206 11:16:12.905287 Listened to connection for namespace 'common' for up to 1s
11207 11:16:13.906254 Finalising connection for namespace 'common'
11208 11:16:13.906423 Disconnecting from shell: Finalise
11209 11:16:13.906511 / #
11210 11:16:14.006836 end: 4.2 read-feedback (duration 00:00:01) [common]
11211 11:16:14.006991 end: 4 finalize (duration 00:00:01) [common]
11212 11:16:14.007107 Cleaning after the job
11213 11:16:14.007204 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/ramdisk
11214 11:16:14.009385 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/kernel
11215 11:16:14.018138 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/dtb
11216 11:16:14.018303 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/nfsrootfs
11217 11:16:14.083821 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591219/tftp-deploy-nqwh2nxw/modules
11218 11:16:14.089196 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591219
11219 11:16:14.590017 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591219
11220 11:16:14.590190 Job finished correctly