Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 11:11:44.424020 lava-dispatcher, installed at version: 2023.05.1
2 11:11:44.424254 start: 0 validate
3 11:11:44.424403 Start time: 2023-06-05 11:11:44.424395+00:00 (UTC)
4 11:11:44.424572 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:11:44.424761 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 11:11:44.713352 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:11:44.713544 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:11:45.010821 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:11:45.011009 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:12:10.484743 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:12:10.484914 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:12:11.072555 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:12:11.072760 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:12:11.368293 validate duration: 26.94
16 11:12:11.368590 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:12:11.368686 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:12:11.368774 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:12:11.368898 Not decompressing ramdisk as can be used compressed.
20 11:12:11.369043 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/initrd.cpio.gz
21 11:12:11.369173 saving as /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/ramdisk/initrd.cpio.gz
22 11:12:11.369264 total size: 4665273 (4MB)
23 11:12:16.340350 progress 0% (0MB)
24 11:12:16.341792 progress 5% (0MB)
25 11:12:16.343016 progress 10% (0MB)
26 11:12:16.344272 progress 15% (0MB)
27 11:12:16.345476 progress 20% (0MB)
28 11:12:16.346680 progress 25% (1MB)
29 11:12:16.347911 progress 30% (1MB)
30 11:12:16.349103 progress 35% (1MB)
31 11:12:16.350290 progress 40% (1MB)
32 11:12:16.351670 progress 45% (2MB)
33 11:12:16.352888 progress 50% (2MB)
34 11:12:16.354068 progress 55% (2MB)
35 11:12:16.355266 progress 60% (2MB)
36 11:12:16.356501 progress 65% (2MB)
37 11:12:16.357689 progress 70% (3MB)
38 11:12:16.358870 progress 75% (3MB)
39 11:12:16.360081 progress 80% (3MB)
40 11:12:16.361481 progress 85% (3MB)
41 11:12:16.362674 progress 90% (4MB)
42 11:12:16.363999 progress 95% (4MB)
43 11:12:16.365238 progress 100% (4MB)
44 11:12:16.365384 4MB downloaded in 5.00s (0.89MB/s)
45 11:12:16.365530 end: 1.1.1 http-download (duration 00:00:05) [common]
47 11:12:16.365767 end: 1.1 download-retry (duration 00:00:05) [common]
48 11:12:16.365851 start: 1.2 download-retry (timeout 00:09:55) [common]
49 11:12:16.365932 start: 1.2.1 http-download (timeout 00:09:55) [common]
50 11:12:16.366062 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:12:16.366129 saving as /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/kernel/Image
52 11:12:16.366188 total size: 45746688 (43MB)
53 11:12:16.366246 No compression specified
54 11:12:16.367309 progress 0% (0MB)
55 11:12:16.378744 progress 5% (2MB)
56 11:12:16.390222 progress 10% (4MB)
57 11:12:16.401719 progress 15% (6MB)
58 11:12:16.413189 progress 20% (8MB)
59 11:12:16.424694 progress 25% (10MB)
60 11:12:16.436101 progress 30% (13MB)
61 11:12:16.447563 progress 35% (15MB)
62 11:12:16.459124 progress 40% (17MB)
63 11:12:16.470709 progress 45% (19MB)
64 11:12:16.482323 progress 50% (21MB)
65 11:12:16.493670 progress 55% (24MB)
66 11:12:16.505252 progress 60% (26MB)
67 11:12:16.517007 progress 65% (28MB)
68 11:12:16.528978 progress 70% (30MB)
69 11:12:16.542071 progress 75% (32MB)
70 11:12:16.554478 progress 80% (34MB)
71 11:12:16.567010 progress 85% (37MB)
72 11:12:16.579341 progress 90% (39MB)
73 11:12:16.591500 progress 95% (41MB)
74 11:12:16.602963 progress 100% (43MB)
75 11:12:16.603118 43MB downloaded in 0.24s (184.14MB/s)
76 11:12:16.603312 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:12:16.603577 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:12:16.603723 start: 1.3 download-retry (timeout 00:09:55) [common]
80 11:12:16.603817 start: 1.3.1 http-download (timeout 00:09:55) [common]
81 11:12:16.603950 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:12:16.604020 saving as /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/dtb/mt8192-asurada-spherion-r0.dtb
83 11:12:16.604085 total size: 46924 (0MB)
84 11:12:16.604160 No compression specified
85 11:12:16.605240 progress 69% (0MB)
86 11:12:16.605514 progress 100% (0MB)
87 11:12:16.605669 0MB downloaded in 0.00s (28.31MB/s)
88 11:12:16.605792 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:12:16.606015 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:12:16.606101 start: 1.4 download-retry (timeout 00:09:55) [common]
92 11:12:16.606183 start: 1.4.1 http-download (timeout 00:09:55) [common]
93 11:12:16.606293 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/full.rootfs.tar.xz
94 11:12:16.606361 saving as /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/nfsrootfs/full.rootfs.tar
95 11:12:16.606421 total size: 89386020 (85MB)
96 11:12:16.606485 Using unxz to decompress xz
97 11:12:16.610037 progress 0% (0MB)
98 11:12:16.824694 progress 5% (4MB)
99 11:12:17.049689 progress 10% (8MB)
100 11:12:17.302703 progress 15% (12MB)
101 11:12:17.497184 progress 20% (17MB)
102 11:12:17.592401 progress 25% (21MB)
103 11:12:17.843179 progress 30% (25MB)
104 11:12:18.127680 progress 35% (29MB)
105 11:12:18.392856 progress 40% (34MB)
106 11:12:18.652008 progress 45% (38MB)
107 11:12:18.899789 progress 50% (42MB)
108 11:12:19.161477 progress 55% (46MB)
109 11:12:19.412020 progress 60% (51MB)
110 11:12:19.678345 progress 65% (55MB)
111 11:12:19.974449 progress 70% (59MB)
112 11:12:20.273671 progress 75% (63MB)
113 11:12:20.568132 progress 80% (68MB)
114 11:12:20.820284 progress 85% (72MB)
115 11:12:21.053826 progress 90% (76MB)
116 11:12:21.316940 progress 95% (81MB)
117 11:12:21.588702 progress 100% (85MB)
118 11:12:21.595297 85MB downloaded in 4.99s (17.09MB/s)
119 11:12:21.595666 end: 1.4.1 http-download (duration 00:00:05) [common]
121 11:12:21.595976 end: 1.4 download-retry (duration 00:00:05) [common]
122 11:12:21.596081 start: 1.5 download-retry (timeout 00:09:50) [common]
123 11:12:21.596167 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 11:12:21.596314 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:12:21.596384 saving as /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/modules/modules.tar
126 11:12:21.596444 total size: 8547328 (8MB)
127 11:12:21.596509 Using unxz to decompress xz
128 11:12:21.600429 progress 0% (0MB)
129 11:12:21.622788 progress 5% (0MB)
130 11:12:21.648075 progress 10% (0MB)
131 11:12:21.674596 progress 15% (1MB)
132 11:12:21.700018 progress 20% (1MB)
133 11:12:21.726604 progress 25% (2MB)
134 11:12:21.752634 progress 30% (2MB)
135 11:12:21.778706 progress 35% (2MB)
136 11:12:21.804777 progress 40% (3MB)
137 11:12:21.831401 progress 45% (3MB)
138 11:12:21.857149 progress 50% (4MB)
139 11:12:21.880582 progress 55% (4MB)
140 11:12:21.907504 progress 60% (4MB)
141 11:12:21.933688 progress 65% (5MB)
142 11:12:21.960143 progress 70% (5MB)
143 11:12:21.988929 progress 75% (6MB)
144 11:12:22.020710 progress 80% (6MB)
145 11:12:22.044618 progress 85% (6MB)
146 11:12:22.072567 progress 90% (7MB)
147 11:12:22.097259 progress 95% (7MB)
148 11:12:22.123006 progress 100% (8MB)
149 11:12:22.129225 8MB downloaded in 0.53s (15.30MB/s)
150 11:12:22.129592 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:12:22.129877 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:12:22.129973 start: 1.6 prepare-tftp-overlay (timeout 00:09:49) [common]
154 11:12:22.130067 start: 1.6.1 extract-nfsrootfs (timeout 00:09:49) [common]
155 11:12:23.732516 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10591224/extract-nfsrootfs-h4vi_uqd
156 11:12:23.732717 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:12:23.732826 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 11:12:23.732994 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77
159 11:12:23.733121 makedir: /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin
160 11:12:23.733223 makedir: /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/tests
161 11:12:23.733320 makedir: /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/results
162 11:12:23.733423 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-add-keys
163 11:12:23.733564 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-add-sources
164 11:12:23.733692 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-background-process-start
165 11:12:23.733822 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-background-process-stop
166 11:12:23.733947 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-common-functions
167 11:12:23.734071 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-echo-ipv4
168 11:12:23.734195 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-install-packages
169 11:12:23.734317 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-installed-packages
170 11:12:23.734440 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-os-build
171 11:12:23.734562 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-probe-channel
172 11:12:23.734683 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-probe-ip
173 11:12:23.734804 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-target-ip
174 11:12:23.734923 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-target-mac
175 11:12:23.735043 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-target-storage
176 11:12:23.735165 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-test-case
177 11:12:23.735286 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-test-event
178 11:12:23.735411 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-test-feedback
179 11:12:23.735531 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-test-raise
180 11:12:23.735651 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-test-reference
181 11:12:23.735771 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-test-runner
182 11:12:23.735891 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-test-set
183 11:12:23.736010 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-test-shell
184 11:12:23.736130 Updating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-install-packages (oe)
185 11:12:23.736276 Updating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/bin/lava-installed-packages (oe)
186 11:12:23.736402 Creating /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/environment
187 11:12:23.736505 LAVA metadata
188 11:12:23.736577 - LAVA_JOB_ID=10591224
189 11:12:23.736641 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:12:23.736746 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
191 11:12:23.736813 skipped lava-vland-overlay
192 11:12:23.736890 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:12:23.736971 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
194 11:12:23.737033 skipped lava-multinode-overlay
195 11:12:23.737107 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:12:23.737185 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
197 11:12:23.737260 Loading test definitions
198 11:12:23.737352 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
199 11:12:23.737424 Using /lava-10591224 at stage 0
200 11:12:23.737717 uuid=10591224_1.6.2.3.1 testdef=None
201 11:12:23.737808 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:12:23.737894 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
203 11:12:23.738379 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:12:23.738607 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
206 11:12:23.739212 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:12:23.739454 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
209 11:12:23.740043 runner path: /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/0/tests/0_lc-compliance test_uuid 10591224_1.6.2.3.1
210 11:12:23.740215 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:12:23.740443 Creating lava-test-runner.conf files
213 11:12:23.740508 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591224/lava-overlay-cbdalf77/lava-10591224/0 for stage 0
214 11:12:23.740596 - 0_lc-compliance
215 11:12:23.740693 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 11:12:23.740780 start: 1.6.2.4 compress-overlay (timeout 00:09:48) [common]
217 11:12:23.746591 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 11:12:23.746721 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:48) [common]
219 11:12:23.746812 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 11:12:23.746900 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 11:12:23.746987 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:48) [common]
222 11:12:23.864125 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 11:12:23.864496 start: 1.6.4 extract-modules (timeout 00:09:48) [common]
224 11:12:23.864613 extracting modules file /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591224/extract-nfsrootfs-h4vi_uqd
225 11:12:24.075853 extracting modules file /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591224/extract-overlay-ramdisk-nq5p36r0/ramdisk
226 11:12:24.331727 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 11:12:24.331895 start: 1.6.5 apply-overlay-tftp (timeout 00:09:47) [common]
228 11:12:24.332011 [common] Applying overlay to NFS
229 11:12:24.332098 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591224/compress-overlay-aj8vefv1/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591224/extract-nfsrootfs-h4vi_uqd
230 11:12:24.339511 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 11:12:24.339676 start: 1.6.6 configure-preseed-file (timeout 00:09:47) [common]
232 11:12:24.339779 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 11:12:24.339873 start: 1.6.7 compress-ramdisk (timeout 00:09:47) [common]
234 11:12:24.339960 Building ramdisk /var/lib/lava/dispatcher/tmp/10591224/extract-overlay-ramdisk-nq5p36r0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591224/extract-overlay-ramdisk-nq5p36r0/ramdisk
235 11:12:24.663451 >> 117801 blocks
236 11:12:26.758401 rename /var/lib/lava/dispatcher/tmp/10591224/extract-overlay-ramdisk-nq5p36r0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/ramdisk/ramdisk.cpio.gz
237 11:12:26.758906 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 11:12:26.759040 start: 1.6.8 prepare-kernel (timeout 00:09:45) [common]
239 11:12:26.759162 start: 1.6.8.1 prepare-fit (timeout 00:09:45) [common]
240 11:12:26.759273 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/kernel/Image'
241 11:12:39.784387 Returned 0 in 13 seconds
242 11:12:39.884986 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/kernel/image.itb
243 11:12:40.207867 output: FIT description: Kernel Image image with one or more FDT blobs
244 11:12:40.208237 output: Created: Mon Jun 5 12:12:40 2023
245 11:12:40.208317 output: Image 0 (kernel-1)
246 11:12:40.208391 output: Description:
247 11:12:40.208461 output: Created: Mon Jun 5 12:12:40 2023
248 11:12:40.208527 output: Type: Kernel Image
249 11:12:40.208589 output: Compression: lzma compressed
250 11:12:40.208652 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
251 11:12:40.208716 output: Architecture: AArch64
252 11:12:40.208777 output: OS: Linux
253 11:12:40.208837 output: Load Address: 0x00000000
254 11:12:40.208895 output: Entry Point: 0x00000000
255 11:12:40.208958 output: Hash algo: crc32
256 11:12:40.209023 output: Hash value: eb1cf9b8
257 11:12:40.209078 output: Image 1 (fdt-1)
258 11:12:40.209144 output: Description: mt8192-asurada-spherion-r0
259 11:12:40.209210 output: Created: Mon Jun 5 12:12:40 2023
260 11:12:40.209273 output: Type: Flat Device Tree
261 11:12:40.209334 output: Compression: uncompressed
262 11:12:40.209390 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
263 11:12:40.209445 output: Architecture: AArch64
264 11:12:40.209501 output: Hash algo: crc32
265 11:12:40.209556 output: Hash value: 1df858fa
266 11:12:40.209609 output: Image 2 (ramdisk-1)
267 11:12:40.209664 output: Description: unavailable
268 11:12:40.209727 output: Created: Mon Jun 5 12:12:40 2023
269 11:12:40.209805 output: Type: RAMDisk Image
270 11:12:40.209893 output: Compression: Unknown Compression
271 11:12:40.209982 output: Data Size: 17640522 Bytes = 17227.07 KiB = 16.82 MiB
272 11:12:40.210071 output: Architecture: AArch64
273 11:12:40.210155 output: OS: Linux
274 11:12:40.210249 output: Load Address: unavailable
275 11:12:40.210334 output: Entry Point: unavailable
276 11:12:40.210428 output: Hash algo: crc32
277 11:12:40.210488 output: Hash value: 1682d247
278 11:12:40.210546 output: Default Configuration: 'conf-1'
279 11:12:40.210609 output: Configuration 0 (conf-1)
280 11:12:40.210714 output: Description: mt8192-asurada-spherion-r0
281 11:12:40.210813 output: Kernel: kernel-1
282 11:12:40.210907 output: Init Ramdisk: ramdisk-1
283 11:12:40.210993 output: FDT: fdt-1
284 11:12:40.211080 output: Loadables: kernel-1
285 11:12:40.211193 output:
286 11:12:40.211463 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 11:12:40.211574 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 11:12:40.211688 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 11:12:40.211797 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
290 11:12:40.211878 No LXC device requested
291 11:12:40.211977 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 11:12:40.212074 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
293 11:12:40.212159 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 11:12:40.212232 Checking files for TFTP limit of 4294967296 bytes.
295 11:12:40.212754 end: 1 tftp-deploy (duration 00:00:29) [common]
296 11:12:40.212871 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 11:12:40.212968 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 11:12:40.213108 substitutions:
299 11:12:40.213200 - {DTB}: 10591224/tftp-deploy-8fgb2sfx/dtb/mt8192-asurada-spherion-r0.dtb
300 11:12:40.213276 - {INITRD}: 10591224/tftp-deploy-8fgb2sfx/ramdisk/ramdisk.cpio.gz
301 11:12:40.213339 - {KERNEL}: 10591224/tftp-deploy-8fgb2sfx/kernel/Image
302 11:12:40.213399 - {LAVA_MAC}: None
303 11:12:40.213457 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10591224/extract-nfsrootfs-h4vi_uqd
304 11:12:40.213517 - {NFS_SERVER_IP}: 192.168.201.1
305 11:12:40.213575 - {PRESEED_CONFIG}: None
306 11:12:40.213631 - {PRESEED_LOCAL}: None
307 11:12:40.213686 - {RAMDISK}: 10591224/tftp-deploy-8fgb2sfx/ramdisk/ramdisk.cpio.gz
308 11:12:40.213754 - {ROOT_PART}: None
309 11:12:40.213810 - {ROOT}: None
310 11:12:40.213872 - {SERVER_IP}: 192.168.201.1
311 11:12:40.213929 - {TEE}: None
312 11:12:40.213987 Parsed boot commands:
313 11:12:40.214043 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 11:12:40.214230 Parsed boot commands: tftpboot 192.168.201.1 10591224/tftp-deploy-8fgb2sfx/kernel/image.itb 10591224/tftp-deploy-8fgb2sfx/kernel/cmdline
315 11:12:40.214335 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 11:12:40.214426 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 11:12:40.214517 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 11:12:40.214619 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 11:12:40.214732 Not connected, no need to disconnect.
320 11:12:40.214848 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 11:12:40.214969 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 11:12:40.215078 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
323 11:12:40.218752 Setting prompt string to ['lava-test: # ']
324 11:12:40.219186 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 11:12:40.219331 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 11:12:40.219486 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 11:12:40.219588 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 11:12:40.219821 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
329 11:12:45.355149 >> Command sent successfully.
330 11:12:45.358028 Returned 0 in 5 seconds
331 11:12:45.458459 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 11:12:45.458791 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 11:12:45.458896 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 11:12:45.458990 Setting prompt string to 'Starting depthcharge on Spherion...'
336 11:12:45.459060 Changing prompt to 'Starting depthcharge on Spherion...'
337 11:12:45.459131 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 11:12:45.459409 [Enter `^Ec?' for help]
339 11:12:45.634007
340 11:12:45.634171
341 11:12:45.634243 F0: 102B 0000
342 11:12:45.634308
343 11:12:45.634370 F3: 1001 0000 [0200]
344 11:12:45.634431
345 11:12:45.637267 F3: 1001 0000
346 11:12:45.637354
347 11:12:45.637423 F7: 102D 0000
348 11:12:45.637491
349 11:12:45.637553 F1: 0000 0000
350 11:12:45.637614
351 11:12:45.641166 V0: 0000 0000 [0001]
352 11:12:45.641253
353 11:12:45.641322 00: 0007 8000
354 11:12:45.641390
355 11:12:45.645029 01: 0000 0000
356 11:12:45.645117
357 11:12:45.645185 BP: 0C00 0209 [0000]
358 11:12:45.645248
359 11:12:45.645309 G0: 1182 0000
360 11:12:45.649037
361 11:12:45.649123 EC: 0000 0021 [4000]
362 11:12:45.649192
363 11:12:45.652152 S7: 0000 0000 [0000]
364 11:12:45.652270
365 11:12:45.652379 CC: 0000 0000 [0001]
366 11:12:45.652484
367 11:12:45.655721 T0: 0000 0040 [010F]
368 11:12:45.655833
369 11:12:45.655938 Jump to BL
370 11:12:45.656042
371 11:12:45.680480
372 11:12:45.680601
373 11:12:45.680695
374 11:12:45.687647 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 11:12:45.691276 ARM64: Exception handlers installed.
376 11:12:45.694907 ARM64: Testing exception
377 11:12:45.698811 ARM64: Done test exception
378 11:12:45.705848 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 11:12:45.713497 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 11:12:45.723648 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 11:12:45.733570 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 11:12:45.740040 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 11:12:45.746395 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 11:12:45.757410 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 11:12:45.764228 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 11:12:45.783302 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 11:12:45.786608 WDT: Last reset was cold boot
388 11:12:45.789756 SPI1(PAD0) initialized at 2873684 Hz
389 11:12:45.793423 SPI5(PAD0) initialized at 992727 Hz
390 11:12:45.796507 VBOOT: Loading verstage.
391 11:12:45.803490 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 11:12:45.806767 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 11:12:45.810113 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 11:12:45.813305 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 11:12:45.820662 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 11:12:45.827538 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 11:12:45.838561 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
398 11:12:45.838649
399 11:12:45.838718
400 11:12:45.848427 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 11:12:45.851655 ARM64: Exception handlers installed.
402 11:12:45.854856 ARM64: Testing exception
403 11:12:45.854937 ARM64: Done test exception
404 11:12:45.862067 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 11:12:45.865304 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 11:12:45.879531 Probing TPM: . done!
407 11:12:45.879661 TPM ready after 0 ms
408 11:12:45.884349 Connected to device vid:did:rid of 1ae0:0028:00
409 11:12:45.895616 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
410 11:12:45.952467 Initialized TPM device CR50 revision 0
411 11:12:45.964323 tlcl_send_startup: Startup return code is 0
412 11:12:45.964449 TPM: setup succeeded
413 11:12:45.975771 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 11:12:45.984393 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 11:12:45.996844 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 11:12:46.005932 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 11:12:46.009774 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 11:12:46.014370 in-header: 03 07 00 00 08 00 00 00
419 11:12:46.017613 in-data: aa e4 47 04 13 02 00 00
420 11:12:46.020811 Chrome EC: UHEPI supported
421 11:12:46.027986 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 11:12:46.032298 in-header: 03 ad 00 00 08 00 00 00
423 11:12:46.035959 in-data: 00 20 20 08 00 00 00 00
424 11:12:46.036077 Phase 1
425 11:12:46.039312 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 11:12:46.046510 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 11:12:46.050476 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 11:12:46.054566 Recovery requested (1009000e)
429 11:12:46.063641 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 11:12:46.069914 tlcl_extend: response is 0
431 11:12:46.079106 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 11:12:46.084719 tlcl_extend: response is 0
433 11:12:46.091208 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 11:12:46.111264 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
435 11:12:46.118266 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 11:12:46.118380
437 11:12:46.118475
438 11:12:46.129175 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 11:12:46.132372 ARM64: Exception handlers installed.
440 11:12:46.132460 ARM64: Testing exception
441 11:12:46.136195 ARM64: Done test exception
442 11:12:46.156979 pmic_efuse_setting: Set efuses in 11 msecs
443 11:12:46.160278 pmwrap_interface_init: Select PMIF_VLD_RDY
444 11:12:46.167453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 11:12:46.170685 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 11:12:46.177813 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 11:12:46.180916 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 11:12:46.184806 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 11:12:46.192624 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 11:12:46.195834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 11:12:46.199851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 11:12:46.203538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 11:12:46.211094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 11:12:46.214159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 11:12:46.218324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 11:12:46.221496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 11:12:46.228914 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 11:12:46.236616 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 11:12:46.240523 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 11:12:46.247317 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 11:12:46.251220 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 11:12:46.258464 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 11:12:46.262351 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 11:12:46.269956 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 11:12:46.273417 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 11:12:46.280507 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 11:12:46.284337 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 11:12:46.292042 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 11:12:46.295934 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 11:12:46.303184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 11:12:46.307255 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 11:12:46.310312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 11:12:46.313853 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 11:12:46.321375 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 11:12:46.324921 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 11:12:46.331922 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 11:12:46.335448 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 11:12:46.339199 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 11:12:46.346785 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 11:12:46.349978 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 11:12:46.357725 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 11:12:46.361627 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 11:12:46.364862 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 11:12:46.368826 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 11:12:46.372006 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 11:12:46.379305 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 11:12:46.383102 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 11:12:46.386459 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 11:12:46.390372 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 11:12:46.394223 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 11:12:46.401383 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 11:12:46.404777 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 11:12:46.408630 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 11:12:46.411918 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 11:12:46.419464 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 11:12:46.427084 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 11:12:46.434446 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 11:12:46.441896 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 11:12:46.448997 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 11:12:46.452766 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 11:12:46.459323 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 11:12:46.463215 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 11:12:46.470971 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
504 11:12:46.474162 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 11:12:46.482068 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
506 11:12:46.485340 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 11:12:46.494399 [RTC]rtc_get_frequency_meter,154: input=15, output=790
508 11:12:46.504122 [RTC]rtc_get_frequency_meter,154: input=23, output=979
509 11:12:46.513320 [RTC]rtc_get_frequency_meter,154: input=19, output=885
510 11:12:46.523016 [RTC]rtc_get_frequency_meter,154: input=17, output=838
511 11:12:46.532144 [RTC]rtc_get_frequency_meter,154: input=16, output=813
512 11:12:46.541683 [RTC]rtc_get_frequency_meter,154: input=15, output=790
513 11:12:46.552024 [RTC]rtc_get_frequency_meter,154: input=16, output=814
514 11:12:46.555750 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
515 11:12:46.558966 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
516 11:12:46.567027 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 11:12:46.570664 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 11:12:46.574101 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 11:12:46.577748 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 11:12:46.581730 ADC[4]: Raw value=900590 ID=7
521 11:12:46.581838 ADC[3]: Raw value=213336 ID=1
522 11:12:46.585439 RAM Code: 0x71
523 11:12:46.589268 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 11:12:46.595651 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 11:12:46.602998 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 11:12:46.610160 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 11:12:46.614308 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 11:12:46.617569 in-header: 03 07 00 00 08 00 00 00
529 11:12:46.617684 in-data: aa e4 47 04 13 02 00 00
530 11:12:46.621505 Chrome EC: UHEPI supported
531 11:12:46.629183 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 11:12:46.632290 in-header: 03 ed 00 00 08 00 00 00
533 11:12:46.636620 in-data: 80 20 60 08 00 00 00 00
534 11:12:46.640193 MRC: failed to locate region type 0.
535 11:12:46.647147 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 11:12:46.647263 DRAM-K: Running full calibration
537 11:12:46.654424 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 11:12:46.658109 header.status = 0x0
539 11:12:46.661857 header.version = 0x6 (expected: 0x6)
540 11:12:46.661945 header.size = 0xd00 (expected: 0xd00)
541 11:12:46.665618 header.flags = 0x0
542 11:12:46.672845 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 11:12:46.689712 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
544 11:12:46.696685 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 11:12:46.700482 dram_init: ddr_geometry: 2
546 11:12:46.700574 [EMI] MDL number = 2
547 11:12:46.703877 [EMI] Get MDL freq = 0
548 11:12:46.703956 dram_init: ddr_type: 0
549 11:12:46.707765 is_discrete_lpddr4: 1
550 11:12:46.711779 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 11:12:46.711904
552 11:12:46.712003
553 11:12:46.712103 [Bian_co] ETT version 0.0.0.1
554 11:12:46.719213 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 11:12:46.719300
556 11:12:46.723000 dramc_set_vcore_voltage set vcore to 650000
557 11:12:46.723090 Read voltage for 800, 4
558 11:12:46.726284 Vio18 = 0
559 11:12:46.726373 Vcore = 650000
560 11:12:46.726456 Vdram = 0
561 11:12:46.726549 Vddq = 0
562 11:12:46.730014 Vmddr = 0
563 11:12:46.730154 dram_init: config_dvfs: 1
564 11:12:46.736411 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 11:12:46.743174 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 11:12:46.746306 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
567 11:12:46.750062 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
568 11:12:46.753066 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
569 11:12:46.756739 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
570 11:12:46.759779 MEM_TYPE=3, freq_sel=18
571 11:12:46.763321 sv_algorithm_assistance_LP4_1600
572 11:12:46.766395 ============ PULL DRAM RESETB DOWN ============
573 11:12:46.770159 ========== PULL DRAM RESETB DOWN end =========
574 11:12:46.776558 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 11:12:46.780009 ===================================
576 11:12:46.780098 LPDDR4 DRAM CONFIGURATION
577 11:12:46.783298 ===================================
578 11:12:46.786514 EX_ROW_EN[0] = 0x0
579 11:12:46.786600 EX_ROW_EN[1] = 0x0
580 11:12:46.790324 LP4Y_EN = 0x0
581 11:12:46.790411 WORK_FSP = 0x0
582 11:12:46.793585 WL = 0x2
583 11:12:46.793670 RL = 0x2
584 11:12:46.796753 BL = 0x2
585 11:12:46.796839 RPST = 0x0
586 11:12:46.800010 RD_PRE = 0x0
587 11:12:46.803196 WR_PRE = 0x1
588 11:12:46.803282 WR_PST = 0x0
589 11:12:46.806976 DBI_WR = 0x0
590 11:12:46.807062 DBI_RD = 0x0
591 11:12:46.810133 OTF = 0x1
592 11:12:46.813583 ===================================
593 11:12:46.816943 ===================================
594 11:12:46.817029 ANA top config
595 11:12:46.820202 ===================================
596 11:12:46.823506 DLL_ASYNC_EN = 0
597 11:12:46.823592 ALL_SLAVE_EN = 1
598 11:12:46.826702 NEW_RANK_MODE = 1
599 11:12:46.830399 DLL_IDLE_MODE = 1
600 11:12:46.833644 LP45_APHY_COMB_EN = 1
601 11:12:46.837105 TX_ODT_DIS = 1
602 11:12:46.837192 NEW_8X_MODE = 1
603 11:12:46.840198 ===================================
604 11:12:46.843480 ===================================
605 11:12:46.846613 data_rate = 1600
606 11:12:46.850398 CKR = 1
607 11:12:46.853281 DQ_P2S_RATIO = 8
608 11:12:46.857019 ===================================
609 11:12:46.860044 CA_P2S_RATIO = 8
610 11:12:46.863086 DQ_CA_OPEN = 0
611 11:12:46.863190 DQ_SEMI_OPEN = 0
612 11:12:46.866831 CA_SEMI_OPEN = 0
613 11:12:46.869802 CA_FULL_RATE = 0
614 11:12:46.873322 DQ_CKDIV4_EN = 1
615 11:12:46.876434 CA_CKDIV4_EN = 1
616 11:12:46.879827 CA_PREDIV_EN = 0
617 11:12:46.879914 PH8_DLY = 0
618 11:12:46.883047 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 11:12:46.886567 DQ_AAMCK_DIV = 4
620 11:12:46.890165 CA_AAMCK_DIV = 4
621 11:12:46.893353 CA_ADMCK_DIV = 4
622 11:12:46.896501 DQ_TRACK_CA_EN = 0
623 11:12:46.896577 CA_PICK = 800
624 11:12:46.899823 CA_MCKIO = 800
625 11:12:46.903175 MCKIO_SEMI = 0
626 11:12:46.907022 PLL_FREQ = 3068
627 11:12:46.910358 DQ_UI_PI_RATIO = 32
628 11:12:46.910446 CA_UI_PI_RATIO = 0
629 11:12:46.914313 ===================================
630 11:12:46.918210 ===================================
631 11:12:46.921597 memory_type:LPDDR4
632 11:12:46.925445 GP_NUM : 10
633 11:12:46.925532 SRAM_EN : 1
634 11:12:46.928692 MD32_EN : 0
635 11:12:46.932758 ===================================
636 11:12:46.932846 [ANA_INIT] >>>>>>>>>>>>>>
637 11:12:46.935929 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 11:12:46.939737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 11:12:46.943681 ===================================
640 11:12:46.946927 data_rate = 1600,PCW = 0X7600
641 11:12:46.950242 ===================================
642 11:12:46.953511 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 11:12:46.956466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 11:12:46.963158 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 11:12:46.966749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 11:12:46.969757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 11:12:46.973434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 11:12:46.976899 [ANA_INIT] flow start
649 11:12:46.980379 [ANA_INIT] PLL >>>>>>>>
650 11:12:46.980466 [ANA_INIT] PLL <<<<<<<<
651 11:12:46.983554 [ANA_INIT] MIDPI >>>>>>>>
652 11:12:46.987021 [ANA_INIT] MIDPI <<<<<<<<
653 11:12:46.987107 [ANA_INIT] DLL >>>>>>>>
654 11:12:46.989940 [ANA_INIT] flow end
655 11:12:46.993235 ============ LP4 DIFF to SE enter ============
656 11:12:46.996534 ============ LP4 DIFF to SE exit ============
657 11:12:46.999791 [ANA_INIT] <<<<<<<<<<<<<
658 11:12:47.003150 [Flow] Enable top DCM control >>>>>
659 11:12:47.007062 [Flow] Enable top DCM control <<<<<
660 11:12:47.010344 Enable DLL master slave shuffle
661 11:12:47.016415 ==============================================================
662 11:12:47.016501 Gating Mode config
663 11:12:47.023692 ==============================================================
664 11:12:47.023777 Config description:
665 11:12:47.033467 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 11:12:47.040061 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 11:12:47.047121 SELPH_MODE 0: By rank 1: By Phase
668 11:12:47.050300 ==============================================================
669 11:12:47.053505 GAT_TRACK_EN = 1
670 11:12:47.056650 RX_GATING_MODE = 2
671 11:12:47.059900 RX_GATING_TRACK_MODE = 2
672 11:12:47.063088 SELPH_MODE = 1
673 11:12:47.066768 PICG_EARLY_EN = 1
674 11:12:47.069841 VALID_LAT_VALUE = 1
675 11:12:47.076545 ==============================================================
676 11:12:47.079564 Enter into Gating configuration >>>>
677 11:12:47.083135 Exit from Gating configuration <<<<
678 11:12:47.083223 Enter into DVFS_PRE_config >>>>>
679 11:12:47.096466 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 11:12:47.099717 Exit from DVFS_PRE_config <<<<<
681 11:12:47.103021 Enter into PICG configuration >>>>
682 11:12:47.106321 Exit from PICG configuration <<<<
683 11:12:47.106418 [RX_INPUT] configuration >>>>>
684 11:12:47.110226 [RX_INPUT] configuration <<<<<
685 11:12:47.116650 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 11:12:47.119990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 11:12:47.127113 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 11:12:47.133717 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 11:12:47.140222 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 11:12:47.147382 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 11:12:47.150625 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 11:12:47.153923 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 11:12:47.157159 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 11:12:47.163504 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 11:12:47.167424 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 11:12:47.170613 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 11:12:47.173699 ===================================
698 11:12:47.177180 LPDDR4 DRAM CONFIGURATION
699 11:12:47.180331 ===================================
700 11:12:47.180422 EX_ROW_EN[0] = 0x0
701 11:12:47.184255 EX_ROW_EN[1] = 0x0
702 11:12:47.187173 LP4Y_EN = 0x0
703 11:12:47.187251 WORK_FSP = 0x0
704 11:12:47.190079 WL = 0x2
705 11:12:47.190154 RL = 0x2
706 11:12:47.193637 BL = 0x2
707 11:12:47.193719 RPST = 0x0
708 11:12:47.197130 RD_PRE = 0x0
709 11:12:47.197216 WR_PRE = 0x1
710 11:12:47.200192 WR_PST = 0x0
711 11:12:47.200285 DBI_WR = 0x0
712 11:12:47.203792 DBI_RD = 0x0
713 11:12:47.203879 OTF = 0x1
714 11:12:47.206785 ===================================
715 11:12:47.210691 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 11:12:47.217208 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 11:12:47.220600 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 11:12:47.223867 ===================================
719 11:12:47.227220 LPDDR4 DRAM CONFIGURATION
720 11:12:47.230376 ===================================
721 11:12:47.230493 EX_ROW_EN[0] = 0x10
722 11:12:47.233609 EX_ROW_EN[1] = 0x0
723 11:12:47.233729 LP4Y_EN = 0x0
724 11:12:47.236819 WORK_FSP = 0x0
725 11:12:47.236934 WL = 0x2
726 11:12:47.240700 RL = 0x2
727 11:12:47.240812 BL = 0x2
728 11:12:47.244031 RPST = 0x0
729 11:12:47.247065 RD_PRE = 0x0
730 11:12:47.247145 WR_PRE = 0x1
731 11:12:47.250406 WR_PST = 0x0
732 11:12:47.250518 DBI_WR = 0x0
733 11:12:47.253582 DBI_RD = 0x0
734 11:12:47.253688 OTF = 0x1
735 11:12:47.256855 ===================================
736 11:12:47.263800 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 11:12:47.267688 nWR fixed to 40
738 11:12:47.270831 [ModeRegInit_LP4] CH0 RK0
739 11:12:47.270907 [ModeRegInit_LP4] CH0 RK1
740 11:12:47.274129 [ModeRegInit_LP4] CH1 RK0
741 11:12:47.277341 [ModeRegInit_LP4] CH1 RK1
742 11:12:47.277423 match AC timing 13
743 11:12:47.284059 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 11:12:47.287856 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 11:12:47.290757 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 11:12:47.297504 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 11:12:47.300506 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 11:12:47.300620 [EMI DOE] emi_dcm 0
749 11:12:47.307290 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 11:12:47.307433 ==
751 11:12:47.310548 Dram Type= 6, Freq= 0, CH_0, rank 0
752 11:12:47.314136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 11:12:47.314248 ==
754 11:12:47.320650 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 11:12:47.327217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 11:12:47.335119 [CA 0] Center 37 (7~68) winsize 62
757 11:12:47.338179 [CA 1] Center 37 (6~68) winsize 63
758 11:12:47.341483 [CA 2] Center 35 (4~66) winsize 63
759 11:12:47.344803 [CA 3] Center 34 (4~65) winsize 62
760 11:12:47.348021 [CA 4] Center 34 (3~65) winsize 63
761 11:12:47.351841 [CA 5] Center 34 (4~64) winsize 61
762 11:12:47.351924
763 11:12:47.355024 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 11:12:47.355137
765 11:12:47.358276 [CATrainingPosCal] consider 1 rank data
766 11:12:47.361862 u2DelayCellTimex100 = 270/100 ps
767 11:12:47.364990 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
768 11:12:47.368247 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
769 11:12:47.374766 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
770 11:12:47.378699 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
771 11:12:47.381467 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
772 11:12:47.384860 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
773 11:12:47.384943
774 11:12:47.388097 CA PerBit enable=1, Macro0, CA PI delay=34
775 11:12:47.388180
776 11:12:47.391612 [CBTSetCACLKResult] CA Dly = 34
777 11:12:47.391695 CS Dly: 5 (0~36)
778 11:12:47.391762 ==
779 11:12:47.394663 Dram Type= 6, Freq= 0, CH_0, rank 1
780 11:12:47.401750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 11:12:47.401837 ==
782 11:12:47.404724 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 11:12:47.411503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 11:12:47.421267 [CA 0] Center 37 (6~68) winsize 63
785 11:12:47.424607 [CA 1] Center 37 (7~68) winsize 62
786 11:12:47.427913 [CA 2] Center 35 (5~66) winsize 62
787 11:12:47.431188 [CA 3] Center 35 (4~66) winsize 63
788 11:12:47.434376 [CA 4] Center 34 (3~65) winsize 63
789 11:12:47.437715 [CA 5] Center 33 (3~64) winsize 62
790 11:12:47.437830
791 11:12:47.441034 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 11:12:47.441116
793 11:12:47.444442 [CATrainingPosCal] consider 2 rank data
794 11:12:47.447556 u2DelayCellTimex100 = 270/100 ps
795 11:12:47.450862 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
796 11:12:47.454774 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
797 11:12:47.461073 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
798 11:12:47.464320 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
799 11:12:47.467589 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
800 11:12:47.470941 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
801 11:12:47.471043
802 11:12:47.474214 CA PerBit enable=1, Macro0, CA PI delay=34
803 11:12:47.474392
804 11:12:47.477459 [CBTSetCACLKResult] CA Dly = 34
805 11:12:47.477541 CS Dly: 5 (0~37)
806 11:12:47.477605
807 11:12:47.481304 ----->DramcWriteLeveling(PI) begin...
808 11:12:47.484617 ==
809 11:12:47.484693 Dram Type= 6, Freq= 0, CH_0, rank 0
810 11:12:47.491073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:12:47.491154 ==
812 11:12:47.494920 Write leveling (Byte 0): 28 => 28
813 11:12:47.495035 Write leveling (Byte 1): 29 => 29
814 11:12:47.498555 DramcWriteLeveling(PI) end<-----
815 11:12:47.498634
816 11:12:47.498698 ==
817 11:12:47.501763 Dram Type= 6, Freq= 0, CH_0, rank 0
818 11:12:47.509204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 11:12:47.509316 ==
820 11:12:47.509422 [Gating] SW mode calibration
821 11:12:47.515829 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 11:12:47.522640 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 11:12:47.526198 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 11:12:47.532577 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
825 11:12:47.535643 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
826 11:12:47.538972 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:12:47.546123 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:12:47.549519 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:12:47.552677 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:12:47.559572 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 11:12:47.562744 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 11:12:47.565909 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 11:12:47.569276 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 11:12:47.576115 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 11:12:47.579470 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 11:12:47.582692 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 11:12:47.589301 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 11:12:47.592517 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:12:47.595703 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 11:12:47.602728 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 11:12:47.605870 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
842 11:12:47.609526 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 11:12:47.616112 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:12:47.619192 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 11:12:47.622761 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 11:12:47.629217 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 11:12:47.632758 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 11:12:47.635687 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 11:12:47.642619 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
850 11:12:47.645958 0 9 12 | B1->B0 | 2c2c 3434 | 1 0 | (0 0) (0 0)
851 11:12:47.649219 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 11:12:47.652564 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 11:12:47.659061 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 11:12:47.662985 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 11:12:47.665629 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 11:12:47.672699 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
857 11:12:47.675989 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
858 11:12:47.679193 0 10 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
859 11:12:47.686174 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:12:47.689339 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:12:47.692591 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:12:47.699142 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:12:47.702395 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:12:47.706170 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:12:47.712600 0 11 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
866 11:12:47.715621 0 11 12 | B1->B0 | 3737 4343 | 0 1 | (0 0) (0 0)
867 11:12:47.719215 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 11:12:47.725829 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 11:12:47.729395 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 11:12:47.732529 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 11:12:47.739445 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 11:12:47.742359 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 11:12:47.745951 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
874 11:12:47.749096 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
875 11:12:47.756398 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 11:12:47.758923 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 11:12:47.762990 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 11:12:47.769176 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 11:12:47.772454 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 11:12:47.775713 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 11:12:47.782795 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 11:12:47.786181 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 11:12:47.789450 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 11:12:47.795880 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 11:12:47.799132 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 11:12:47.802401 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 11:12:47.809009 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 11:12:47.812856 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 11:12:47.816033 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
890 11:12:47.822320 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
891 11:12:47.822426 Total UI for P1: 0, mck2ui 16
892 11:12:47.828983 best dqsien dly found for B0: ( 0, 14, 8)
893 11:12:47.832640 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 11:12:47.835798 Total UI for P1: 0, mck2ui 16
895 11:12:47.839502 best dqsien dly found for B1: ( 0, 14, 10)
896 11:12:47.842501 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
897 11:12:47.845682 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
898 11:12:47.845786
899 11:12:47.849287 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
900 11:12:47.852405 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
901 11:12:47.856078 [Gating] SW calibration Done
902 11:12:47.856183 ==
903 11:12:47.859295 Dram Type= 6, Freq= 0, CH_0, rank 0
904 11:12:47.862517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
905 11:12:47.862592 ==
906 11:12:47.865788 RX Vref Scan: 0
907 11:12:47.865889
908 11:12:47.869497 RX Vref 0 -> 0, step: 1
909 11:12:47.869610
910 11:12:47.869715 RX Delay -130 -> 252, step: 16
911 11:12:47.876137 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
912 11:12:47.879468 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
913 11:12:47.882626 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
914 11:12:47.886370 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
915 11:12:47.889627 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
916 11:12:47.896158 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
917 11:12:47.899603 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
918 11:12:47.902558 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
919 11:12:47.905929 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
920 11:12:47.909346 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
921 11:12:47.916290 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
922 11:12:47.919454 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
923 11:12:47.922675 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
924 11:12:47.925973 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
925 11:12:47.928925 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
926 11:12:47.935618 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
927 11:12:47.935723 ==
928 11:12:47.939300 Dram Type= 6, Freq= 0, CH_0, rank 0
929 11:12:47.942387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 11:12:47.942488 ==
931 11:12:47.942580 DQS Delay:
932 11:12:47.945999 DQS0 = 0, DQS1 = 0
933 11:12:47.946104 DQM Delay:
934 11:12:47.949074 DQM0 = 85, DQM1 = 79
935 11:12:47.949177 DQ Delay:
936 11:12:47.952728 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
937 11:12:47.955751 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
938 11:12:47.959474 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
939 11:12:47.962458 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
940 11:12:47.962535
941 11:12:47.962606
942 11:12:47.962667 ==
943 11:12:47.965568 Dram Type= 6, Freq= 0, CH_0, rank 0
944 11:12:47.968830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 11:12:47.968910 ==
946 11:12:47.972673
947 11:12:47.972773
948 11:12:47.972865 TX Vref Scan disable
949 11:12:47.976013 == TX Byte 0 ==
950 11:12:47.979313 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
951 11:12:47.982556 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
952 11:12:47.985777 == TX Byte 1 ==
953 11:12:47.989223 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
954 11:12:47.992304 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
955 11:12:47.992457 ==
956 11:12:47.995570 Dram Type= 6, Freq= 0, CH_0, rank 0
957 11:12:48.002096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 11:12:48.002205 ==
959 11:12:48.014283 TX Vref=22, minBit 0, minWin=27, winSum=439
960 11:12:48.017507 TX Vref=24, minBit 0, minWin=27, winSum=440
961 11:12:48.020812 TX Vref=26, minBit 5, minWin=27, winSum=445
962 11:12:48.024060 TX Vref=28, minBit 12, minWin=27, winSum=452
963 11:12:48.027887 TX Vref=30, minBit 12, minWin=27, winSum=454
964 11:12:48.034386 TX Vref=32, minBit 2, minWin=28, winSum=452
965 11:12:48.037448 [TxChooseVref] Worse bit 2, Min win 28, Win sum 452, Final Vref 32
966 11:12:48.037560
967 11:12:48.041037 Final TX Range 1 Vref 32
968 11:12:48.041152
969 11:12:48.041247 ==
970 11:12:48.044219 Dram Type= 6, Freq= 0, CH_0, rank 0
971 11:12:48.047828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 11:12:48.047932 ==
973 11:12:48.048028
974 11:12:48.050868
975 11:12:48.050997 TX Vref Scan disable
976 11:12:48.053929 == TX Byte 0 ==
977 11:12:48.057614 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
978 11:12:48.061171 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
979 11:12:48.064221 == TX Byte 1 ==
980 11:12:48.067308 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
981 11:12:48.070952 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
982 11:12:48.074210
983 11:12:48.074332 [DATLAT]
984 11:12:48.074431 Freq=800, CH0 RK0
985 11:12:48.074526
986 11:12:48.077402 DATLAT Default: 0xa
987 11:12:48.077520 0, 0xFFFF, sum = 0
988 11:12:48.081443 1, 0xFFFF, sum = 0
989 11:12:48.081583 2, 0xFFFF, sum = 0
990 11:12:48.084501 3, 0xFFFF, sum = 0
991 11:12:48.084638 4, 0xFFFF, sum = 0
992 11:12:48.087587 5, 0xFFFF, sum = 0
993 11:12:48.090980 6, 0xFFFF, sum = 0
994 11:12:48.091085 7, 0xFFFF, sum = 0
995 11:12:48.094156 8, 0xFFFF, sum = 0
996 11:12:48.094268 9, 0x0, sum = 1
997 11:12:48.094363 10, 0x0, sum = 2
998 11:12:48.098005 11, 0x0, sum = 3
999 11:12:48.098129 12, 0x0, sum = 4
1000 11:12:48.101235 best_step = 10
1001 11:12:48.101338
1002 11:12:48.101435 ==
1003 11:12:48.104453 Dram Type= 6, Freq= 0, CH_0, rank 0
1004 11:12:48.107700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1005 11:12:48.107804 ==
1006 11:12:48.110882 RX Vref Scan: 1
1007 11:12:48.110985
1008 11:12:48.111084 Set Vref Range= 32 -> 127
1009 11:12:48.111182
1010 11:12:48.114196 RX Vref 32 -> 127, step: 1
1011 11:12:48.114296
1012 11:12:48.117457 RX Delay -95 -> 252, step: 8
1013 11:12:48.117562
1014 11:12:48.120684 Set Vref, RX VrefLevel [Byte0]: 32
1015 11:12:48.124592 [Byte1]: 32
1016 11:12:48.124698
1017 11:12:48.127790 Set Vref, RX VrefLevel [Byte0]: 33
1018 11:12:48.131686 [Byte1]: 33
1019 11:12:48.131793
1020 11:12:48.135042 Set Vref, RX VrefLevel [Byte0]: 34
1021 11:12:48.138265 [Byte1]: 34
1022 11:12:48.141987
1023 11:12:48.142095 Set Vref, RX VrefLevel [Byte0]: 35
1024 11:12:48.145626 [Byte1]: 35
1025 11:12:48.149998
1026 11:12:48.150110 Set Vref, RX VrefLevel [Byte0]: 36
1027 11:12:48.153008 [Byte1]: 36
1028 11:12:48.157964
1029 11:12:48.158051 Set Vref, RX VrefLevel [Byte0]: 37
1030 11:12:48.161090 [Byte1]: 37
1031 11:12:48.165593
1032 11:12:48.165678 Set Vref, RX VrefLevel [Byte0]: 38
1033 11:12:48.169159 [Byte1]: 38
1034 11:12:48.172772
1035 11:12:48.172865 Set Vref, RX VrefLevel [Byte0]: 39
1036 11:12:48.175831 [Byte1]: 39
1037 11:12:48.179829
1038 11:12:48.183641 Set Vref, RX VrefLevel [Byte0]: 40
1039 11:12:48.183727 [Byte1]: 40
1040 11:12:48.188160
1041 11:12:48.188241 Set Vref, RX VrefLevel [Byte0]: 41
1042 11:12:48.191465 [Byte1]: 41
1043 11:12:48.195382
1044 11:12:48.195468 Set Vref, RX VrefLevel [Byte0]: 42
1045 11:12:48.198663 [Byte1]: 42
1046 11:12:48.203286
1047 11:12:48.203416 Set Vref, RX VrefLevel [Byte0]: 43
1048 11:12:48.206489 [Byte1]: 43
1049 11:12:48.210475
1050 11:12:48.210560 Set Vref, RX VrefLevel [Byte0]: 44
1051 11:12:48.213628 [Byte1]: 44
1052 11:12:48.218344
1053 11:12:48.218419 Set Vref, RX VrefLevel [Byte0]: 45
1054 11:12:48.221553 [Byte1]: 45
1055 11:12:48.226154
1056 11:12:48.226238 Set Vref, RX VrefLevel [Byte0]: 46
1057 11:12:48.229351 [Byte1]: 46
1058 11:12:48.233373
1059 11:12:48.233460 Set Vref, RX VrefLevel [Byte0]: 47
1060 11:12:48.236590 [Byte1]: 47
1061 11:12:48.241133
1062 11:12:48.241219 Set Vref, RX VrefLevel [Byte0]: 48
1063 11:12:48.244384 [Byte1]: 48
1064 11:12:48.248996
1065 11:12:48.249083 Set Vref, RX VrefLevel [Byte0]: 49
1066 11:12:48.252000 [Byte1]: 49
1067 11:12:48.256270
1068 11:12:48.256361 Set Vref, RX VrefLevel [Byte0]: 50
1069 11:12:48.259391 [Byte1]: 50
1070 11:12:48.263606
1071 11:12:48.263715 Set Vref, RX VrefLevel [Byte0]: 51
1072 11:12:48.266744 [Byte1]: 51
1073 11:12:48.271292
1074 11:12:48.271385 Set Vref, RX VrefLevel [Byte0]: 52
1075 11:12:48.274650 [Byte1]: 52
1076 11:12:48.278883
1077 11:12:48.278995 Set Vref, RX VrefLevel [Byte0]: 53
1078 11:12:48.282421 [Byte1]: 53
1079 11:12:48.286790
1080 11:12:48.286896 Set Vref, RX VrefLevel [Byte0]: 54
1081 11:12:48.290025 [Byte1]: 54
1082 11:12:48.293963
1083 11:12:48.294066 Set Vref, RX VrefLevel [Byte0]: 55
1084 11:12:48.297303 [Byte1]: 55
1085 11:12:48.301951
1086 11:12:48.302026 Set Vref, RX VrefLevel [Byte0]: 56
1087 11:12:48.305161 [Byte1]: 56
1088 11:12:48.309083
1089 11:12:48.309191 Set Vref, RX VrefLevel [Byte0]: 57
1090 11:12:48.312343 [Byte1]: 57
1091 11:12:48.316960
1092 11:12:48.317031 Set Vref, RX VrefLevel [Byte0]: 58
1093 11:12:48.320276 [Byte1]: 58
1094 11:12:48.324297
1095 11:12:48.327447 Set Vref, RX VrefLevel [Byte0]: 59
1096 11:12:48.327554 [Byte1]: 59
1097 11:12:48.331998
1098 11:12:48.332075 Set Vref, RX VrefLevel [Byte0]: 60
1099 11:12:48.335192 [Byte1]: 60
1100 11:12:48.339598
1101 11:12:48.339679 Set Vref, RX VrefLevel [Byte0]: 61
1102 11:12:48.342955 [Byte1]: 61
1103 11:12:48.346971
1104 11:12:48.347078 Set Vref, RX VrefLevel [Byte0]: 62
1105 11:12:48.350927 [Byte1]: 62
1106 11:12:48.354941
1107 11:12:48.355013 Set Vref, RX VrefLevel [Byte0]: 63
1108 11:12:48.361688 [Byte1]: 63
1109 11:12:48.361770
1110 11:12:48.364536 Set Vref, RX VrefLevel [Byte0]: 64
1111 11:12:48.368406 [Byte1]: 64
1112 11:12:48.368480
1113 11:12:48.371259 Set Vref, RX VrefLevel [Byte0]: 65
1114 11:12:48.375110 [Byte1]: 65
1115 11:12:48.375218
1116 11:12:48.378250 Set Vref, RX VrefLevel [Byte0]: 66
1117 11:12:48.381070 [Byte1]: 66
1118 11:12:48.385258
1119 11:12:48.385344 Set Vref, RX VrefLevel [Byte0]: 67
1120 11:12:48.388334 [Byte1]: 67
1121 11:12:48.392716
1122 11:12:48.392803 Set Vref, RX VrefLevel [Byte0]: 68
1123 11:12:48.396536 [Byte1]: 68
1124 11:12:48.400561
1125 11:12:48.400647 Set Vref, RX VrefLevel [Byte0]: 69
1126 11:12:48.403549 [Byte1]: 69
1127 11:12:48.408106
1128 11:12:48.408190 Set Vref, RX VrefLevel [Byte0]: 70
1129 11:12:48.411326 [Byte1]: 70
1130 11:12:48.415940
1131 11:12:48.416024 Set Vref, RX VrefLevel [Byte0]: 71
1132 11:12:48.419244 [Byte1]: 71
1133 11:12:48.423177
1134 11:12:48.423287 Set Vref, RX VrefLevel [Byte0]: 72
1135 11:12:48.426516 [Byte1]: 72
1136 11:12:48.430501
1137 11:12:48.430585 Set Vref, RX VrefLevel [Byte0]: 73
1138 11:12:48.434446 [Byte1]: 73
1139 11:12:48.438262
1140 11:12:48.438346 Set Vref, RX VrefLevel [Byte0]: 74
1141 11:12:48.441492 [Byte1]: 74
1142 11:12:48.446004
1143 11:12:48.446087 Set Vref, RX VrefLevel [Byte0]: 75
1144 11:12:48.449254 [Byte1]: 75
1145 11:12:48.453775
1146 11:12:48.453858 Set Vref, RX VrefLevel [Byte0]: 76
1147 11:12:48.457074 [Byte1]: 76
1148 11:12:48.461069
1149 11:12:48.461153 Final RX Vref Byte 0 = 61 to rank0
1150 11:12:48.465122 Final RX Vref Byte 1 = 59 to rank0
1151 11:12:48.468178 Final RX Vref Byte 0 = 61 to rank1
1152 11:12:48.471301 Final RX Vref Byte 1 = 59 to rank1==
1153 11:12:48.475018 Dram Type= 6, Freq= 0, CH_0, rank 0
1154 11:12:48.478030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1155 11:12:48.481084 ==
1156 11:12:48.481214 DQS Delay:
1157 11:12:48.481312 DQS0 = 0, DQS1 = 0
1158 11:12:48.484852 DQM Delay:
1159 11:12:48.484966 DQM0 = 87, DQM1 = 80
1160 11:12:48.487864 DQ Delay:
1161 11:12:48.491572 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1162 11:12:48.491677 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1163 11:12:48.494523 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1164 11:12:48.497863 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1165 11:12:48.497946
1166 11:12:48.501313
1167 11:12:48.508326 [DQSOSCAuto] RK0, (LSB)MR18= 0x270e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1168 11:12:48.511743 CH0 RK0: MR19=606, MR18=270E
1169 11:12:48.518049 CH0_RK0: MR19=0x606, MR18=0x270E, DQSOSC=400, MR23=63, INC=92, DEC=61
1170 11:12:48.518148
1171 11:12:48.521232 ----->DramcWriteLeveling(PI) begin...
1172 11:12:48.521315 ==
1173 11:12:48.524530 Dram Type= 6, Freq= 0, CH_0, rank 1
1174 11:12:48.528357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1175 11:12:48.528441 ==
1176 11:12:48.531154 Write leveling (Byte 0): 29 => 29
1177 11:12:48.534819 Write leveling (Byte 1): 27 => 27
1178 11:12:48.538036 DramcWriteLeveling(PI) end<-----
1179 11:12:48.538118
1180 11:12:48.538184 ==
1181 11:12:48.541348 Dram Type= 6, Freq= 0, CH_0, rank 1
1182 11:12:48.544564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1183 11:12:48.544651 ==
1184 11:12:48.548462 [Gating] SW mode calibration
1185 11:12:48.555010 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1186 11:12:48.561505 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1187 11:12:48.564801 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1188 11:12:48.568080 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1189 11:12:48.611839 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1190 11:12:48.612186 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:12:48.612298 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:12:48.612417 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:12:48.612514 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:12:48.612607 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:12:48.612727 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:12:48.613101 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 11:12:48.613396 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 11:12:48.613496 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 11:12:48.655873 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 11:12:48.656542 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 11:12:48.656807 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:12:48.656911 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 11:12:48.656979 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 11:12:48.657064 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1205 11:12:48.657180 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1206 11:12:48.657273 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 11:12:48.657367 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 11:12:48.657472 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 11:12:48.667825 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 11:12:48.668088 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 11:12:48.671080 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 11:12:48.674350 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 11:12:48.678264 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
1214 11:12:48.684557 0 9 12 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
1215 11:12:48.688100 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1216 11:12:48.690992 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 11:12:48.697799 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 11:12:48.701362 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 11:12:48.704784 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 11:12:48.707959 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1221 11:12:48.714719 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
1222 11:12:48.717989 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1223 11:12:48.721596 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:12:48.728079 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:12:48.731341 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:12:48.734829 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:12:48.741663 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:12:48.745593 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1229 11:12:48.749492 0 11 8 | B1->B0 | 2f2f 4444 | 0 0 | (0 0) (0 0)
1230 11:12:48.752030 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1231 11:12:48.759186 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 11:12:48.762508 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 11:12:48.765833 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 11:12:48.772820 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 11:12:48.776897 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 11:12:48.779988 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 11:12:48.783097 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1238 11:12:48.789481 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1239 11:12:48.793533 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 11:12:48.796475 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 11:12:48.803247 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 11:12:48.806308 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 11:12:48.809784 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 11:12:48.816611 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 11:12:48.819725 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 11:12:48.822882 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 11:12:48.830031 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 11:12:48.833567 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 11:12:48.836632 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 11:12:48.839896 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 11:12:48.846299 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 11:12:48.849725 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1253 11:12:48.852966 Total UI for P1: 0, mck2ui 16
1254 11:12:48.856244 best dqsien dly found for B0: ( 0, 14, 2)
1255 11:12:48.860063 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1256 11:12:48.866611 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 11:12:48.869990 Total UI for P1: 0, mck2ui 16
1258 11:12:48.873162 best dqsien dly found for B1: ( 0, 14, 10)
1259 11:12:48.876078 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1260 11:12:48.880001 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1261 11:12:48.880092
1262 11:12:48.883305 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1263 11:12:48.886571 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1264 11:12:48.889818 [Gating] SW calibration Done
1265 11:12:48.889901 ==
1266 11:12:48.893123 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 11:12:48.896376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 11:12:48.896453 ==
1269 11:12:48.899622 RX Vref Scan: 0
1270 11:12:48.899695
1271 11:12:48.899758 RX Vref 0 -> 0, step: 1
1272 11:12:48.899818
1273 11:12:48.902693 RX Delay -130 -> 252, step: 16
1274 11:12:48.909478 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1275 11:12:48.912995 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1276 11:12:48.916046 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1277 11:12:48.920047 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1278 11:12:48.923009 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1279 11:12:48.926651 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1280 11:12:48.933000 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1281 11:12:48.936228 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1282 11:12:48.939518 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1283 11:12:48.942734 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1284 11:12:48.946008 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1285 11:12:48.953177 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1286 11:12:48.956460 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1287 11:12:48.959665 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1288 11:12:48.962857 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1289 11:12:48.969476 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1290 11:12:48.969554 ==
1291 11:12:48.972579 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 11:12:48.976448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 11:12:48.976536 ==
1294 11:12:48.976602 DQS Delay:
1295 11:12:48.979643 DQS0 = 0, DQS1 = 0
1296 11:12:48.979721 DQM Delay:
1297 11:12:48.982922 DQM0 = 86, DQM1 = 76
1298 11:12:48.982992 DQ Delay:
1299 11:12:48.986067 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1300 11:12:48.989454 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1301 11:12:48.992599 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1302 11:12:48.996432 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1303 11:12:48.996511
1304 11:12:48.996574
1305 11:12:48.996633 ==
1306 11:12:48.999683 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 11:12:49.002919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 11:12:49.003027 ==
1309 11:12:49.003124
1310 11:12:49.003212
1311 11:12:49.006125 TX Vref Scan disable
1312 11:12:49.009299 == TX Byte 0 ==
1313 11:12:49.013167 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1314 11:12:49.016094 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1315 11:12:49.019787 == TX Byte 1 ==
1316 11:12:49.022906 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1317 11:12:49.026057 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1318 11:12:49.026194 ==
1319 11:12:49.029653 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 11:12:49.036346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 11:12:49.036460 ==
1322 11:12:49.047843 TX Vref=22, minBit 12, minWin=26, winSum=436
1323 11:12:49.051645 TX Vref=24, minBit 3, minWin=27, winSum=442
1324 11:12:49.054851 TX Vref=26, minBit 7, minWin=27, winSum=446
1325 11:12:49.058039 TX Vref=28, minBit 9, minWin=27, winSum=451
1326 11:12:49.061371 TX Vref=30, minBit 13, minWin=27, winSum=448
1327 11:12:49.068374 TX Vref=32, minBit 2, minWin=27, winSum=450
1328 11:12:49.071710 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 28
1329 11:12:49.071799
1330 11:12:49.075042 Final TX Range 1 Vref 28
1331 11:12:49.075152
1332 11:12:49.075254 ==
1333 11:12:49.078033 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 11:12:49.081347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 11:12:49.081462 ==
1336 11:12:49.081558
1337 11:12:49.084488
1338 11:12:49.084589 TX Vref Scan disable
1339 11:12:49.087749 == TX Byte 0 ==
1340 11:12:49.091712 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1341 11:12:49.094942 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1342 11:12:49.098065 == TX Byte 1 ==
1343 11:12:49.101345 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1344 11:12:49.104579 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1345 11:12:49.107800
1346 11:12:49.107885 [DATLAT]
1347 11:12:49.107953 Freq=800, CH0 RK1
1348 11:12:49.108018
1349 11:12:49.111644 DATLAT Default: 0xa
1350 11:12:49.111720 0, 0xFFFF, sum = 0
1351 11:12:49.114976 1, 0xFFFF, sum = 0
1352 11:12:49.115079 2, 0xFFFF, sum = 0
1353 11:12:49.117913 3, 0xFFFF, sum = 0
1354 11:12:49.118020 4, 0xFFFF, sum = 0
1355 11:12:49.121571 5, 0xFFFF, sum = 0
1356 11:12:49.124742 6, 0xFFFF, sum = 0
1357 11:12:49.124849 7, 0xFFFF, sum = 0
1358 11:12:49.128545 8, 0xFFFF, sum = 0
1359 11:12:49.128652 9, 0x0, sum = 1
1360 11:12:49.128748 10, 0x0, sum = 2
1361 11:12:49.131507 11, 0x0, sum = 3
1362 11:12:49.131610 12, 0x0, sum = 4
1363 11:12:49.134612 best_step = 10
1364 11:12:49.134715
1365 11:12:49.134808 ==
1366 11:12:49.137736 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 11:12:49.141428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 11:12:49.141514 ==
1369 11:12:49.144876 RX Vref Scan: 0
1370 11:12:49.144976
1371 11:12:49.145077 RX Vref 0 -> 0, step: 1
1372 11:12:49.145166
1373 11:12:49.147868 RX Delay -95 -> 252, step: 8
1374 11:12:49.154934 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1375 11:12:49.158186 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1376 11:12:49.161453 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1377 11:12:49.164762 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1378 11:12:49.167929 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1379 11:12:49.174451 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1380 11:12:49.177851 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1381 11:12:49.181470 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1382 11:12:49.184714 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1383 11:12:49.187972 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1384 11:12:49.194414 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1385 11:12:49.198276 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1386 11:12:49.201572 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1387 11:12:49.204784 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1388 11:12:49.208001 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1389 11:12:49.214499 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1390 11:12:49.214579 ==
1391 11:12:49.217661 Dram Type= 6, Freq= 0, CH_0, rank 1
1392 11:12:49.221623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 11:12:49.221732 ==
1394 11:12:49.221831 DQS Delay:
1395 11:12:49.224860 DQS0 = 0, DQS1 = 0
1396 11:12:49.224963 DQM Delay:
1397 11:12:49.227814 DQM0 = 87, DQM1 = 78
1398 11:12:49.227914 DQ Delay:
1399 11:12:49.231563 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1400 11:12:49.234733 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1401 11:12:49.238178 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1402 11:12:49.241125 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1403 11:12:49.241230
1404 11:12:49.241332
1405 11:12:49.247860 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1406 11:12:49.251364 CH0 RK1: MR19=606, MR18=2D15
1407 11:12:49.257681 CH0_RK1: MR19=0x606, MR18=0x2D15, DQSOSC=398, MR23=63, INC=93, DEC=62
1408 11:12:49.260992 [RxdqsGatingPostProcess] freq 800
1409 11:12:49.268285 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1410 11:12:49.271536 Pre-setting of DQS Precalculation
1411 11:12:49.274753 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1412 11:12:49.274832 ==
1413 11:12:49.277987 Dram Type= 6, Freq= 0, CH_1, rank 0
1414 11:12:49.281154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 11:12:49.281268 ==
1416 11:12:49.288031 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1417 11:12:49.294786 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1418 11:12:49.303116 [CA 0] Center 36 (6~66) winsize 61
1419 11:12:49.306460 [CA 1] Center 36 (6~66) winsize 61
1420 11:12:49.309682 [CA 2] Center 34 (4~65) winsize 62
1421 11:12:49.312962 [CA 3] Center 34 (3~65) winsize 63
1422 11:12:49.316139 [CA 4] Center 34 (4~65) winsize 62
1423 11:12:49.319474 [CA 5] Center 34 (4~64) winsize 61
1424 11:12:49.319579
1425 11:12:49.322769 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1426 11:12:49.322871
1427 11:12:49.326672 [CATrainingPosCal] consider 1 rank data
1428 11:12:49.329748 u2DelayCellTimex100 = 270/100 ps
1429 11:12:49.332937 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1430 11:12:49.336628 CA1 delay=36 (6~66),Diff = 2 PI (14 cell)
1431 11:12:49.339664 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 11:12:49.346361 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1433 11:12:49.349417 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1434 11:12:49.352987 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1435 11:12:49.353065
1436 11:12:49.356774 CA PerBit enable=1, Macro0, CA PI delay=34
1437 11:12:49.356855
1438 11:12:49.359803 [CBTSetCACLKResult] CA Dly = 34
1439 11:12:49.359884 CS Dly: 5 (0~36)
1440 11:12:49.359949 ==
1441 11:12:49.363018 Dram Type= 6, Freq= 0, CH_1, rank 1
1442 11:12:49.369548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 11:12:49.369666 ==
1444 11:12:49.372910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1445 11:12:49.379334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1446 11:12:49.389014 [CA 0] Center 36 (6~66) winsize 61
1447 11:12:49.392247 [CA 1] Center 36 (6~66) winsize 61
1448 11:12:49.395438 [CA 2] Center 34 (4~65) winsize 62
1449 11:12:49.398682 [CA 3] Center 34 (4~65) winsize 62
1450 11:12:49.402076 [CA 4] Center 34 (4~65) winsize 62
1451 11:12:49.405907 [CA 5] Center 33 (3~64) winsize 62
1452 11:12:49.406016
1453 11:12:49.409342 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1454 11:12:49.409448
1455 11:12:49.413127 [CATrainingPosCal] consider 2 rank data
1456 11:12:49.417000 u2DelayCellTimex100 = 270/100 ps
1457 11:12:49.420818 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1458 11:12:49.424076 CA1 delay=36 (6~66),Diff = 2 PI (14 cell)
1459 11:12:49.428037 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1460 11:12:49.431955 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1461 11:12:49.435266 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1462 11:12:49.439119 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1463 11:12:49.439225
1464 11:12:49.442459 CA PerBit enable=1, Macro0, CA PI delay=34
1465 11:12:49.442574
1466 11:12:49.445967 [CBTSetCACLKResult] CA Dly = 34
1467 11:12:49.446081 CS Dly: 5 (0~37)
1468 11:12:49.446190
1469 11:12:49.449263 ----->DramcWriteLeveling(PI) begin...
1470 11:12:49.449373 ==
1471 11:12:49.452282 Dram Type= 6, Freq= 0, CH_1, rank 0
1472 11:12:49.458995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1473 11:12:49.459107 ==
1474 11:12:49.462030 Write leveling (Byte 0): 27 => 27
1475 11:12:49.465818 Write leveling (Byte 1): 27 => 27
1476 11:12:49.465904 DramcWriteLeveling(PI) end<-----
1477 11:12:49.469047
1478 11:12:49.469130 ==
1479 11:12:49.472291 Dram Type= 6, Freq= 0, CH_1, rank 0
1480 11:12:49.475553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1481 11:12:49.475646 ==
1482 11:12:49.478849 [Gating] SW mode calibration
1483 11:12:49.485921 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1484 11:12:49.489209 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1485 11:12:49.495586 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1486 11:12:49.498855 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1487 11:12:49.502151 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1488 11:12:49.508792 0 6 12 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1489 11:12:49.512121 0 6 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1490 11:12:49.515423 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:12:49.521934 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:12:49.525848 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:12:49.528995 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:12:49.535610 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 11:12:49.539013 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 11:12:49.542345 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1497 11:12:49.549120 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:12:49.552168 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1499 11:12:49.555237 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 11:12:49.562334 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:12:49.565461 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 11:12:49.569039 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1503 11:12:49.572043 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1504 11:12:49.579187 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 11:12:49.582412 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 11:12:49.585762 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 11:12:49.592183 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 11:12:49.595523 0 8 28 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1509 11:12:49.598696 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 11:12:49.605843 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1511 11:12:49.609100 0 9 8 | B1->B0 | 2828 2b2b | 1 1 | (1 1) (1 1)
1512 11:12:49.612425 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1513 11:12:49.618948 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1514 11:12:49.622286 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 11:12:49.625526 0 9 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1516 11:12:49.632051 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 11:12:49.635282 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 11:12:49.639178 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1519 11:12:49.645569 0 10 8 | B1->B0 | 2b2b 3030 | 1 1 | (1 0) (1 0)
1520 11:12:49.648668 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1521 11:12:49.651902 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:12:49.659000 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1523 11:12:49.661982 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:12:49.665786 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:12:49.668829 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:12:49.675601 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:12:49.678612 0 11 8 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
1528 11:12:49.682272 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 11:12:49.688592 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 11:12:49.692434 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 11:12:49.695717 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 11:12:49.702133 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 11:12:49.705527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 11:12:49.708667 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 11:12:49.715760 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1536 11:12:49.719058 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1537 11:12:49.722172 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 11:12:49.728630 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 11:12:49.732496 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 11:12:49.735899 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 11:12:49.742387 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 11:12:49.745643 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 11:12:49.748894 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 11:12:49.752369 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 11:12:49.758760 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 11:12:49.762625 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 11:12:49.765596 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 11:12:49.772548 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 11:12:49.775575 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 11:12:49.779234 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 11:12:49.785847 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1552 11:12:49.789073 Total UI for P1: 0, mck2ui 16
1553 11:12:49.792583 best dqsien dly found for B0: ( 0, 14, 6)
1554 11:12:49.795551 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 11:12:49.798783 Total UI for P1: 0, mck2ui 16
1556 11:12:49.802683 best dqsien dly found for B1: ( 0, 14, 8)
1557 11:12:49.805846 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1558 11:12:49.809022 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1559 11:12:49.809108
1560 11:12:49.812202 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1561 11:12:49.815524 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1562 11:12:49.818799 [Gating] SW calibration Done
1563 11:12:49.818899 ==
1564 11:12:49.822158 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 11:12:49.825908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 11:12:49.826018 ==
1567 11:12:49.829293 RX Vref Scan: 0
1568 11:12:49.829402
1569 11:12:49.832001 RX Vref 0 -> 0, step: 1
1570 11:12:49.832102
1571 11:12:49.835773 RX Delay -130 -> 252, step: 16
1572 11:12:49.838980 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1573 11:12:49.842203 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1574 11:12:49.845562 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1575 11:12:49.848909 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1576 11:12:49.852566 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1577 11:12:49.858922 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1578 11:12:49.862247 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1579 11:12:49.865522 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1580 11:12:49.868947 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1581 11:12:49.872534 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1582 11:12:49.879100 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1583 11:12:49.882174 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1584 11:12:49.885800 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1585 11:12:49.888922 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1586 11:12:49.895766 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1587 11:12:49.898683 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1588 11:12:49.898784 ==
1589 11:12:49.902185 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 11:12:49.905508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 11:12:49.905616 ==
1592 11:12:49.905711 DQS Delay:
1593 11:12:49.909174 DQS0 = 0, DQS1 = 0
1594 11:12:49.909288 DQM Delay:
1595 11:12:49.912398 DQM0 = 84, DQM1 = 76
1596 11:12:49.912484 DQ Delay:
1597 11:12:49.915671 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1598 11:12:49.918992 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1599 11:12:49.922196 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1600 11:12:49.925466 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1601 11:12:49.925573
1602 11:12:49.925668
1603 11:12:49.925761 ==
1604 11:12:49.929370 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 11:12:49.932652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 11:12:49.932739 ==
1607 11:12:49.935841
1608 11:12:49.935927
1609 11:12:49.935998 TX Vref Scan disable
1610 11:12:49.939125 == TX Byte 0 ==
1611 11:12:49.942357 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1612 11:12:49.945598 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1613 11:12:49.948957 == TX Byte 1 ==
1614 11:12:49.952664 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1615 11:12:49.955886 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1616 11:12:49.955978 ==
1617 11:12:49.959107 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 11:12:49.965810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 11:12:49.965924 ==
1620 11:12:49.977721 TX Vref=22, minBit 0, minWin=27, winSum=435
1621 11:12:49.980604 TX Vref=24, minBit 0, minWin=27, winSum=441
1622 11:12:49.984191 TX Vref=26, minBit 3, minWin=27, winSum=445
1623 11:12:49.987820 TX Vref=28, minBit 11, minWin=27, winSum=449
1624 11:12:49.990894 TX Vref=30, minBit 9, minWin=27, winSum=452
1625 11:12:49.994523 TX Vref=32, minBit 0, minWin=28, winSum=452
1626 11:12:50.001233 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 32
1627 11:12:50.001324
1628 11:12:50.004255 Final TX Range 1 Vref 32
1629 11:12:50.004339
1630 11:12:50.004405 ==
1631 11:12:50.007915 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 11:12:50.010766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 11:12:50.010873 ==
1634 11:12:50.010965
1635 11:12:50.014287
1636 11:12:50.014390 TX Vref Scan disable
1637 11:12:50.017400 == TX Byte 0 ==
1638 11:12:50.021377 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1639 11:12:50.024573 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1640 11:12:50.028173 == TX Byte 1 ==
1641 11:12:50.031059 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1642 11:12:50.034277 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1643 11:12:50.037359
1644 11:12:50.037469 [DATLAT]
1645 11:12:50.037565 Freq=800, CH1 RK0
1646 11:12:50.037659
1647 11:12:50.041245 DATLAT Default: 0xa
1648 11:12:50.041354 0, 0xFFFF, sum = 0
1649 11:12:50.044395 1, 0xFFFF, sum = 0
1650 11:12:50.044481 2, 0xFFFF, sum = 0
1651 11:12:50.047529 3, 0xFFFF, sum = 0
1652 11:12:50.047614 4, 0xFFFF, sum = 0
1653 11:12:50.050841 5, 0xFFFF, sum = 0
1654 11:12:50.050919 6, 0xFFFF, sum = 0
1655 11:12:50.054230 7, 0xFFFF, sum = 0
1656 11:12:50.054311 8, 0xFFFF, sum = 0
1657 11:12:50.057996 9, 0x0, sum = 1
1658 11:12:50.058075 10, 0x0, sum = 2
1659 11:12:50.061349 11, 0x0, sum = 3
1660 11:12:50.061425 12, 0x0, sum = 4
1661 11:12:50.064634 best_step = 10
1662 11:12:50.064708
1663 11:12:50.064771 ==
1664 11:12:50.067859 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 11:12:50.071192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 11:12:50.071295 ==
1667 11:12:50.074301 RX Vref Scan: 1
1668 11:12:50.074375
1669 11:12:50.074438 Set Vref Range= 32 -> 127
1670 11:12:50.074499
1671 11:12:50.077656 RX Vref 32 -> 127, step: 1
1672 11:12:50.077740
1673 11:12:50.080951 RX Delay -111 -> 252, step: 8
1674 11:12:50.081035
1675 11:12:50.084351 Set Vref, RX VrefLevel [Byte0]: 32
1676 11:12:50.087525 [Byte1]: 32
1677 11:12:50.087610
1678 11:12:50.091185 Set Vref, RX VrefLevel [Byte0]: 33
1679 11:12:50.094108 [Byte1]: 33
1680 11:12:50.098069
1681 11:12:50.098148 Set Vref, RX VrefLevel [Byte0]: 34
1682 11:12:50.101575 [Byte1]: 34
1683 11:12:50.105553
1684 11:12:50.105664 Set Vref, RX VrefLevel [Byte0]: 35
1685 11:12:50.109168 [Byte1]: 35
1686 11:12:50.113264
1687 11:12:50.113350 Set Vref, RX VrefLevel [Byte0]: 36
1688 11:12:50.116646 [Byte1]: 36
1689 11:12:50.120843
1690 11:12:50.120957 Set Vref, RX VrefLevel [Byte0]: 37
1691 11:12:50.124276 [Byte1]: 37
1692 11:12:50.128340
1693 11:12:50.128417 Set Vref, RX VrefLevel [Byte0]: 38
1694 11:12:50.134824 [Byte1]: 38
1695 11:12:50.134935
1696 11:12:50.137934 Set Vref, RX VrefLevel [Byte0]: 39
1697 11:12:50.141856 [Byte1]: 39
1698 11:12:50.141968
1699 11:12:50.145035 Set Vref, RX VrefLevel [Byte0]: 40
1700 11:12:50.148272 [Byte1]: 40
1701 11:12:50.151622
1702 11:12:50.151731 Set Vref, RX VrefLevel [Byte0]: 41
1703 11:12:50.154881 [Byte1]: 41
1704 11:12:50.159393
1705 11:12:50.159473 Set Vref, RX VrefLevel [Byte0]: 42
1706 11:12:50.162558 [Byte1]: 42
1707 11:12:50.166419
1708 11:12:50.166525 Set Vref, RX VrefLevel [Byte0]: 43
1709 11:12:50.170357 [Byte1]: 43
1710 11:12:50.174258
1711 11:12:50.174363 Set Vref, RX VrefLevel [Byte0]: 44
1712 11:12:50.177484 [Byte1]: 44
1713 11:12:50.182187
1714 11:12:50.182304 Set Vref, RX VrefLevel [Byte0]: 45
1715 11:12:50.185421 [Byte1]: 45
1716 11:12:50.189834
1717 11:12:50.189943 Set Vref, RX VrefLevel [Byte0]: 46
1718 11:12:50.193148 [Byte1]: 46
1719 11:12:50.197064
1720 11:12:50.197171 Set Vref, RX VrefLevel [Byte0]: 47
1721 11:12:50.200716 [Byte1]: 47
1722 11:12:50.205008
1723 11:12:50.205117 Set Vref, RX VrefLevel [Byte0]: 48
1724 11:12:50.208408 [Byte1]: 48
1725 11:12:50.212630
1726 11:12:50.212735 Set Vref, RX VrefLevel [Byte0]: 49
1727 11:12:50.215949 [Byte1]: 49
1728 11:12:50.220071
1729 11:12:50.220177 Set Vref, RX VrefLevel [Byte0]: 50
1730 11:12:50.223638 [Byte1]: 50
1731 11:12:50.227652
1732 11:12:50.227737 Set Vref, RX VrefLevel [Byte0]: 51
1733 11:12:50.231173 [Byte1]: 51
1734 11:12:50.235310
1735 11:12:50.235406 Set Vref, RX VrefLevel [Byte0]: 52
1736 11:12:50.239001 [Byte1]: 52
1737 11:12:50.243375
1738 11:12:50.243458 Set Vref, RX VrefLevel [Byte0]: 53
1739 11:12:50.246550 [Byte1]: 53
1740 11:12:50.250993
1741 11:12:50.251096 Set Vref, RX VrefLevel [Byte0]: 54
1742 11:12:50.254406 [Byte1]: 54
1743 11:12:50.258814
1744 11:12:50.258917 Set Vref, RX VrefLevel [Byte0]: 55
1745 11:12:50.262046 [Byte1]: 55
1746 11:12:50.266082
1747 11:12:50.266188 Set Vref, RX VrefLevel [Byte0]: 56
1748 11:12:50.269396 [Byte1]: 56
1749 11:12:50.273884
1750 11:12:50.273993 Set Vref, RX VrefLevel [Byte0]: 57
1751 11:12:50.277115 [Byte1]: 57
1752 11:12:50.281637
1753 11:12:50.281749 Set Vref, RX VrefLevel [Byte0]: 58
1754 11:12:50.285053 [Byte1]: 58
1755 11:12:50.288777
1756 11:12:50.288883 Set Vref, RX VrefLevel [Byte0]: 59
1757 11:12:50.292708 [Byte1]: 59
1758 11:12:50.296598
1759 11:12:50.296710 Set Vref, RX VrefLevel [Byte0]: 60
1760 11:12:50.299932 [Byte1]: 60
1761 11:12:50.304315
1762 11:12:50.304424 Set Vref, RX VrefLevel [Byte0]: 61
1763 11:12:50.308235 [Byte1]: 61
1764 11:12:50.311986
1765 11:12:50.312094 Set Vref, RX VrefLevel [Byte0]: 62
1766 11:12:50.315492 [Byte1]: 62
1767 11:12:50.319686
1768 11:12:50.319796 Set Vref, RX VrefLevel [Byte0]: 63
1769 11:12:50.323249 [Byte1]: 63
1770 11:12:50.327599
1771 11:12:50.327707 Set Vref, RX VrefLevel [Byte0]: 64
1772 11:12:50.330629 [Byte1]: 64
1773 11:12:50.334828
1774 11:12:50.334936 Set Vref, RX VrefLevel [Byte0]: 65
1775 11:12:50.338525 [Byte1]: 65
1776 11:12:50.342740
1777 11:12:50.342850 Set Vref, RX VrefLevel [Byte0]: 66
1778 11:12:50.345920 [Byte1]: 66
1779 11:12:50.350186
1780 11:12:50.350294 Set Vref, RX VrefLevel [Byte0]: 67
1781 11:12:50.353499 [Byte1]: 67
1782 11:12:50.357956
1783 11:12:50.358063 Set Vref, RX VrefLevel [Byte0]: 68
1784 11:12:50.361261 [Byte1]: 68
1785 11:12:50.365878
1786 11:12:50.365984 Set Vref, RX VrefLevel [Byte0]: 69
1787 11:12:50.369150 [Byte1]: 69
1788 11:12:50.373080
1789 11:12:50.373190 Set Vref, RX VrefLevel [Byte0]: 70
1790 11:12:50.376457 [Byte1]: 70
1791 11:12:50.380900
1792 11:12:50.381020 Set Vref, RX VrefLevel [Byte0]: 71
1793 11:12:50.384155 [Byte1]: 71
1794 11:12:50.388646
1795 11:12:50.388754 Set Vref, RX VrefLevel [Byte0]: 72
1796 11:12:50.391828 [Byte1]: 72
1797 11:12:50.396420
1798 11:12:50.396529 Set Vref, RX VrefLevel [Byte0]: 73
1799 11:12:50.399581 [Byte1]: 73
1800 11:12:50.403491
1801 11:12:50.403599 Set Vref, RX VrefLevel [Byte0]: 74
1802 11:12:50.407364 [Byte1]: 74
1803 11:12:50.411968
1804 11:12:50.412079 Set Vref, RX VrefLevel [Byte0]: 75
1805 11:12:50.414853 [Byte1]: 75
1806 11:12:50.419270
1807 11:12:50.419390 Set Vref, RX VrefLevel [Byte0]: 76
1808 11:12:50.422460 [Byte1]: 76
1809 11:12:50.426725
1810 11:12:50.426836 Set Vref, RX VrefLevel [Byte0]: 77
1811 11:12:50.429786 [Byte1]: 77
1812 11:12:50.434605
1813 11:12:50.434721 Set Vref, RX VrefLevel [Byte0]: 78
1814 11:12:50.437500 [Byte1]: 78
1815 11:12:50.442302
1816 11:12:50.442412 Set Vref, RX VrefLevel [Byte0]: 79
1817 11:12:50.445402 [Byte1]: 79
1818 11:12:50.449468
1819 11:12:50.449574 Final RX Vref Byte 0 = 65 to rank0
1820 11:12:50.453157 Final RX Vref Byte 1 = 58 to rank0
1821 11:12:50.456315 Final RX Vref Byte 0 = 65 to rank1
1822 11:12:50.459528 Final RX Vref Byte 1 = 58 to rank1==
1823 11:12:50.462628 Dram Type= 6, Freq= 0, CH_1, rank 0
1824 11:12:50.469768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1825 11:12:50.469880 ==
1826 11:12:50.469978 DQS Delay:
1827 11:12:50.470070 DQS0 = 0, DQS1 = 0
1828 11:12:50.472914 DQM Delay:
1829 11:12:50.473024 DQM0 = 84, DQM1 = 74
1830 11:12:50.476259 DQ Delay:
1831 11:12:50.479473 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1832 11:12:50.479581 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =76
1833 11:12:50.482807 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1834 11:12:50.489386 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1835 11:12:50.489496
1836 11:12:50.489593
1837 11:12:50.496534 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fa, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1838 11:12:50.499883 CH1 RK0: MR19=605, MR18=26FA
1839 11:12:50.506551 CH1_RK0: MR19=0x605, MR18=0x26FA, DQSOSC=400, MR23=63, INC=92, DEC=61
1840 11:12:50.506637
1841 11:12:50.509726 ----->DramcWriteLeveling(PI) begin...
1842 11:12:50.509833 ==
1843 11:12:50.512863 Dram Type= 6, Freq= 0, CH_1, rank 1
1844 11:12:50.515932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1845 11:12:50.516012 ==
1846 11:12:50.519717 Write leveling (Byte 0): 27 => 27
1847 11:12:50.522731 Write leveling (Byte 1): 29 => 29
1848 11:12:50.525983 DramcWriteLeveling(PI) end<-----
1849 11:12:50.526087
1850 11:12:50.526180 ==
1851 11:12:50.529802 Dram Type= 6, Freq= 0, CH_1, rank 1
1852 11:12:50.533005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1853 11:12:50.533091 ==
1854 11:12:50.536096 [Gating] SW mode calibration
1855 11:12:50.542780 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1856 11:12:50.549962 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1857 11:12:50.552921 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1858 11:12:50.556572 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1859 11:12:50.563140 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1860 11:12:50.566209 0 6 12 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1861 11:12:50.569466 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:12:50.576738 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:12:50.579974 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 11:12:50.583198 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 11:12:50.589705 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 11:12:50.592902 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 11:12:50.596128 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:12:50.602788 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1869 11:12:50.606725 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 11:12:50.609997 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:12:50.613122 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:12:50.620069 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:12:50.623125 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (1 1)
1874 11:12:50.626360 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
1875 11:12:50.633108 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:12:50.636400 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:12:50.639704 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:12:50.646305 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:12:50.650005 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:12:50.652865 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:12:50.659995 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:12:50.662879 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1883 11:12:50.666554 0 9 8 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
1884 11:12:50.673175 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 11:12:50.676453 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 11:12:50.679619 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 11:12:50.686206 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 11:12:50.690119 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 11:12:50.693365 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1890 11:12:50.696614 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
1891 11:12:50.703201 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1892 11:12:50.706534 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:12:50.709859 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:12:50.716417 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:12:50.719565 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:12:50.722918 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:12:50.729540 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:12:50.732632 0 11 4 | B1->B0 | 2a2a 2f2f | 0 1 | (0 0) (0 0)
1899 11:12:50.736515 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1900 11:12:50.742948 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 11:12:50.746310 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 11:12:50.749597 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 11:12:50.756296 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 11:12:50.759981 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 11:12:50.763000 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1906 11:12:50.769619 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1907 11:12:50.773228 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 11:12:50.776212 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 11:12:50.783181 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 11:12:50.786380 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 11:12:50.789675 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 11:12:50.796245 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 11:12:50.799548 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 11:12:50.802846 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 11:12:50.809458 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 11:12:50.812644 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 11:12:50.815907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 11:12:50.819148 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 11:12:50.826377 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 11:12:50.829658 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 11:12:50.832757 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 11:12:50.839619 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1923 11:12:50.842815 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 11:12:50.846182 Total UI for P1: 0, mck2ui 16
1925 11:12:50.849417 best dqsien dly found for B0: ( 0, 14, 4)
1926 11:12:50.852786 Total UI for P1: 0, mck2ui 16
1927 11:12:50.855925 best dqsien dly found for B1: ( 0, 14, 6)
1928 11:12:50.859768 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1929 11:12:50.862733 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1930 11:12:50.862809
1931 11:12:50.866407 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1932 11:12:50.869712 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1933 11:12:50.872620 [Gating] SW calibration Done
1934 11:12:50.872730 ==
1935 11:12:50.876262 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 11:12:50.879307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 11:12:50.879405 ==
1938 11:12:50.883008 RX Vref Scan: 0
1939 11:12:50.883099
1940 11:12:50.886235 RX Vref 0 -> 0, step: 1
1941 11:12:50.886320
1942 11:12:50.886388 RX Delay -130 -> 252, step: 16
1943 11:12:50.893303 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1944 11:12:50.896579 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1945 11:12:50.899696 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1946 11:12:50.902975 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1947 11:12:50.906285 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1948 11:12:50.913438 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1949 11:12:50.916088 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1950 11:12:50.920005 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1951 11:12:50.923468 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1952 11:12:50.926586 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1953 11:12:50.932913 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1954 11:12:50.936808 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1955 11:12:50.939714 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1956 11:12:50.943257 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1957 11:12:50.946603 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1958 11:12:50.953525 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1959 11:12:50.953627 ==
1960 11:12:50.956876 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 11:12:50.960218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 11:12:50.960303 ==
1963 11:12:50.960370 DQS Delay:
1964 11:12:50.963508 DQS0 = 0, DQS1 = 0
1965 11:12:50.963582 DQM Delay:
1966 11:12:50.966695 DQM0 = 81, DQM1 = 77
1967 11:12:50.966767 DQ Delay:
1968 11:12:50.969823 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1969 11:12:50.973199 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1970 11:12:50.976247 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1971 11:12:50.979894 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1972 11:12:50.979997
1973 11:12:50.980065
1974 11:12:50.980127 ==
1975 11:12:50.983025 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 11:12:50.986569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 11:12:50.986680 ==
1978 11:12:50.986770
1979 11:12:50.989652
1980 11:12:50.989736 TX Vref Scan disable
1981 11:12:50.993311 == TX Byte 0 ==
1982 11:12:50.996634 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1983 11:12:50.999808 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1984 11:12:51.003132 == TX Byte 1 ==
1985 11:12:51.006478 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1986 11:12:51.009725 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1987 11:12:51.009813 ==
1988 11:12:51.012851 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 11:12:51.020107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 11:12:51.020195 ==
1991 11:12:51.030980 TX Vref=22, minBit 8, minWin=27, winSum=443
1992 11:12:51.034830 TX Vref=24, minBit 15, minWin=27, winSum=448
1993 11:12:51.038023 TX Vref=26, minBit 0, minWin=28, winSum=448
1994 11:12:51.041242 TX Vref=28, minBit 0, minWin=28, winSum=450
1995 11:12:51.044333 TX Vref=30, minBit 0, minWin=28, winSum=454
1996 11:12:51.051304 TX Vref=32, minBit 0, minWin=28, winSum=454
1997 11:12:51.054415 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1998 11:12:51.054499
1999 11:12:51.057772 Final TX Range 1 Vref 30
2000 11:12:51.057851
2001 11:12:51.057916 ==
2002 11:12:51.061645 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 11:12:51.064889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 11:12:51.064974 ==
2005 11:12:51.068179
2006 11:12:51.068254
2007 11:12:51.068326 TX Vref Scan disable
2008 11:12:51.071526 == TX Byte 0 ==
2009 11:12:51.074641 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2010 11:12:51.081206 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2011 11:12:51.081291 == TX Byte 1 ==
2012 11:12:51.084958 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2013 11:12:51.088110 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2014 11:12:51.091692
2015 11:12:51.091805 [DATLAT]
2016 11:12:51.091908 Freq=800, CH1 RK1
2017 11:12:51.092002
2018 11:12:51.094663 DATLAT Default: 0xa
2019 11:12:51.094764 0, 0xFFFF, sum = 0
2020 11:12:51.098341 1, 0xFFFF, sum = 0
2021 11:12:51.098470 2, 0xFFFF, sum = 0
2022 11:12:51.101474 3, 0xFFFF, sum = 0
2023 11:12:51.101580 4, 0xFFFF, sum = 0
2024 11:12:51.104672 5, 0xFFFF, sum = 0
2025 11:12:51.107932 6, 0xFFFF, sum = 0
2026 11:12:51.108045 7, 0xFFFF, sum = 0
2027 11:12:51.111194 8, 0xFFFF, sum = 0
2028 11:12:51.111294 9, 0x0, sum = 1
2029 11:12:51.111404 10, 0x0, sum = 2
2030 11:12:51.114458 11, 0x0, sum = 3
2031 11:12:51.114536 12, 0x0, sum = 4
2032 11:12:51.117724 best_step = 10
2033 11:12:51.117816
2034 11:12:51.117888 ==
2035 11:12:51.121583 Dram Type= 6, Freq= 0, CH_1, rank 1
2036 11:12:51.124863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2037 11:12:51.124942 ==
2038 11:12:51.128173 RX Vref Scan: 0
2039 11:12:51.128267
2040 11:12:51.128336 RX Vref 0 -> 0, step: 1
2041 11:12:51.128398
2042 11:12:51.131300 RX Delay -95 -> 252, step: 8
2043 11:12:51.137882 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2044 11:12:51.141090 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2045 11:12:51.144888 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2046 11:12:51.148174 iDelay=201, Bit 3, Center 80 (-31 ~ 192) 224
2047 11:12:51.151362 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2048 11:12:51.158245 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2049 11:12:51.161419 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2050 11:12:51.164771 iDelay=201, Bit 7, Center 72 (-39 ~ 184) 224
2051 11:12:51.168006 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2052 11:12:51.171298 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2053 11:12:51.177704 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2054 11:12:51.181031 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2055 11:12:51.184687 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2056 11:12:51.187726 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2057 11:12:51.194269 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2058 11:12:51.197896 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2059 11:12:51.198009 ==
2060 11:12:51.200923 Dram Type= 6, Freq= 0, CH_1, rank 1
2061 11:12:51.204499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2062 11:12:51.204603 ==
2063 11:12:51.204700 DQS Delay:
2064 11:12:51.207606 DQS0 = 0, DQS1 = 0
2065 11:12:51.207730 DQM Delay:
2066 11:12:51.210895 DQM0 = 79, DQM1 = 75
2067 11:12:51.210980 DQ Delay:
2068 11:12:51.214238 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =80
2069 11:12:51.217597 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =72
2070 11:12:51.220965 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2071 11:12:51.224245 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2072 11:12:51.224347
2073 11:12:51.224443
2074 11:12:51.234619 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2075 11:12:51.234737 CH1 RK1: MR19=606, MR18=1F2A
2076 11:12:51.241021 CH1_RK1: MR19=0x606, MR18=0x1F2A, DQSOSC=399, MR23=63, INC=92, DEC=61
2077 11:12:51.244102 [RxdqsGatingPostProcess] freq 800
2078 11:12:51.251427 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2079 11:12:51.254524 Pre-setting of DQS Precalculation
2080 11:12:51.257672 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2081 11:12:51.264523 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2082 11:12:51.270925 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2083 11:12:51.274436
2084 11:12:51.274551
2085 11:12:51.274660 [Calibration Summary] 1600 Mbps
2086 11:12:51.277441 CH 0, Rank 0
2087 11:12:51.277526 SW Impedance : PASS
2088 11:12:51.280746 DUTY Scan : NO K
2089 11:12:51.284530 ZQ Calibration : PASS
2090 11:12:51.284622 Jitter Meter : NO K
2091 11:12:51.287702 CBT Training : PASS
2092 11:12:51.290907 Write leveling : PASS
2093 11:12:51.291020 RX DQS gating : PASS
2094 11:12:51.294099 RX DQ/DQS(RDDQC) : PASS
2095 11:12:51.297778 TX DQ/DQS : PASS
2096 11:12:51.297859 RX DATLAT : PASS
2097 11:12:51.300820 RX DQ/DQS(Engine): PASS
2098 11:12:51.304643 TX OE : NO K
2099 11:12:51.304724 All Pass.
2100 11:12:51.304791
2101 11:12:51.304868 CH 0, Rank 1
2102 11:12:51.307676 SW Impedance : PASS
2103 11:12:51.310793 DUTY Scan : NO K
2104 11:12:51.310873 ZQ Calibration : PASS
2105 11:12:51.314573 Jitter Meter : NO K
2106 11:12:51.314653 CBT Training : PASS
2107 11:12:51.317908 Write leveling : PASS
2108 11:12:51.321276 RX DQS gating : PASS
2109 11:12:51.321356 RX DQ/DQS(RDDQC) : PASS
2110 11:12:51.324607 TX DQ/DQS : PASS
2111 11:12:51.327755 RX DATLAT : PASS
2112 11:12:51.327864 RX DQ/DQS(Engine): PASS
2113 11:12:51.331068 TX OE : NO K
2114 11:12:51.331153 All Pass.
2115 11:12:51.331218
2116 11:12:51.334426 CH 1, Rank 0
2117 11:12:51.334523 SW Impedance : PASS
2118 11:12:51.337540 DUTY Scan : NO K
2119 11:12:51.340850 ZQ Calibration : PASS
2120 11:12:51.340926 Jitter Meter : NO K
2121 11:12:51.344040 CBT Training : PASS
2122 11:12:51.347922 Write leveling : PASS
2123 11:12:51.348013 RX DQS gating : PASS
2124 11:12:51.351129 RX DQ/DQS(RDDQC) : PASS
2125 11:12:51.354321 TX DQ/DQS : PASS
2126 11:12:51.354438 RX DATLAT : PASS
2127 11:12:51.357619 RX DQ/DQS(Engine): PASS
2128 11:12:51.357702 TX OE : NO K
2129 11:12:51.360735 All Pass.
2130 11:12:51.360843
2131 11:12:51.360940 CH 1, Rank 1
2132 11:12:51.364498 SW Impedance : PASS
2133 11:12:51.364635 DUTY Scan : NO K
2134 11:12:51.367645 ZQ Calibration : PASS
2135 11:12:51.370796 Jitter Meter : NO K
2136 11:12:51.370911 CBT Training : PASS
2137 11:12:51.374719 Write leveling : PASS
2138 11:12:51.377791 RX DQS gating : PASS
2139 11:12:51.377901 RX DQ/DQS(RDDQC) : PASS
2140 11:12:51.381078 TX DQ/DQS : PASS
2141 11:12:51.384383 RX DATLAT : PASS
2142 11:12:51.384468 RX DQ/DQS(Engine): PASS
2143 11:12:51.387689 TX OE : NO K
2144 11:12:51.387802 All Pass.
2145 11:12:51.387904
2146 11:12:51.390747 DramC Write-DBI off
2147 11:12:51.394673 PER_BANK_REFRESH: Hybrid Mode
2148 11:12:51.394757 TX_TRACKING: ON
2149 11:12:51.397968 [GetDramInforAfterCalByMRR] Vendor 6.
2150 11:12:51.401218 [GetDramInforAfterCalByMRR] Revision 606.
2151 11:12:51.404429 [GetDramInforAfterCalByMRR] Revision 2 0.
2152 11:12:51.407847 MR0 0x3b3b
2153 11:12:51.407932 MR8 0x5151
2154 11:12:51.410898 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2155 11:12:51.411012
2156 11:12:51.411151 MR0 0x3b3b
2157 11:12:51.414684 MR8 0x5151
2158 11:12:51.417661 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2159 11:12:51.417745
2160 11:12:51.424606 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2161 11:12:51.430949 [FAST_K] Save calibration result to emmc
2162 11:12:51.434176 [FAST_K] Save calibration result to emmc
2163 11:12:51.434259 dram_init: config_dvfs: 1
2164 11:12:51.441184 dramc_set_vcore_voltage set vcore to 662500
2165 11:12:51.441267 Read voltage for 1200, 2
2166 11:12:51.441333 Vio18 = 0
2167 11:12:51.444573 Vcore = 662500
2168 11:12:51.444656 Vdram = 0
2169 11:12:51.444721 Vddq = 0
2170 11:12:51.447636 Vmddr = 0
2171 11:12:51.450961 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2172 11:12:51.458087 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2173 11:12:51.458202 MEM_TYPE=3, freq_sel=15
2174 11:12:51.461254 sv_algorithm_assistance_LP4_1600
2175 11:12:51.467669 ============ PULL DRAM RESETB DOWN ============
2176 11:12:51.471462 ========== PULL DRAM RESETB DOWN end =========
2177 11:12:51.474567 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2178 11:12:51.477672 ===================================
2179 11:12:51.480979 LPDDR4 DRAM CONFIGURATION
2180 11:12:51.484388 ===================================
2181 11:12:51.487681 EX_ROW_EN[0] = 0x0
2182 11:12:51.487764 EX_ROW_EN[1] = 0x0
2183 11:12:51.490875 LP4Y_EN = 0x0
2184 11:12:51.490982 WORK_FSP = 0x0
2185 11:12:51.494004 WL = 0x4
2186 11:12:51.494112 RL = 0x4
2187 11:12:51.497943 BL = 0x2
2188 11:12:51.498026 RPST = 0x0
2189 11:12:51.501087 RD_PRE = 0x0
2190 11:12:51.501213 WR_PRE = 0x1
2191 11:12:51.504367 WR_PST = 0x0
2192 11:12:51.504450 DBI_WR = 0x0
2193 11:12:51.507755 DBI_RD = 0x0
2194 11:12:51.507838 OTF = 0x1
2195 11:12:51.511034 ===================================
2196 11:12:51.514566 ===================================
2197 11:12:51.518190 ANA top config
2198 11:12:51.521045 ===================================
2199 11:12:51.521156 DLL_ASYNC_EN = 0
2200 11:12:51.524493 ALL_SLAVE_EN = 0
2201 11:12:51.527499 NEW_RANK_MODE = 1
2202 11:12:51.530722 DLL_IDLE_MODE = 1
2203 11:12:51.534185 LP45_APHY_COMB_EN = 1
2204 11:12:51.534269 TX_ODT_DIS = 1
2205 11:12:51.538124 NEW_8X_MODE = 1
2206 11:12:51.541185 ===================================
2207 11:12:51.544416 ===================================
2208 11:12:51.547639 data_rate = 2400
2209 11:12:51.550886 CKR = 1
2210 11:12:51.554094 DQ_P2S_RATIO = 8
2211 11:12:51.557329 ===================================
2212 11:12:51.557438 CA_P2S_RATIO = 8
2213 11:12:51.561070 DQ_CA_OPEN = 0
2214 11:12:51.564419 DQ_SEMI_OPEN = 0
2215 11:12:51.567664 CA_SEMI_OPEN = 0
2216 11:12:51.570783 CA_FULL_RATE = 0
2217 11:12:51.574379 DQ_CKDIV4_EN = 0
2218 11:12:51.574491 CA_CKDIV4_EN = 0
2219 11:12:51.577277 CA_PREDIV_EN = 0
2220 11:12:51.581221 PH8_DLY = 17
2221 11:12:51.584339 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2222 11:12:51.587730 DQ_AAMCK_DIV = 4
2223 11:12:51.590811 CA_AAMCK_DIV = 4
2224 11:12:51.590896 CA_ADMCK_DIV = 4
2225 11:12:51.594047 DQ_TRACK_CA_EN = 0
2226 11:12:51.597191 CA_PICK = 1200
2227 11:12:51.600429 CA_MCKIO = 1200
2228 11:12:51.604419 MCKIO_SEMI = 0
2229 11:12:51.607742 PLL_FREQ = 2366
2230 11:12:51.611011 DQ_UI_PI_RATIO = 32
2231 11:12:51.614234 CA_UI_PI_RATIO = 0
2232 11:12:51.617435 ===================================
2233 11:12:51.620573 ===================================
2234 11:12:51.620673 memory_type:LPDDR4
2235 11:12:51.624335 GP_NUM : 10
2236 11:12:51.624419 SRAM_EN : 1
2237 11:12:51.627492 MD32_EN : 0
2238 11:12:51.630400 ===================================
2239 11:12:51.634000 [ANA_INIT] >>>>>>>>>>>>>>
2240 11:12:51.637013 <<<<<< [CONFIGURE PHASE]: ANA_TX
2241 11:12:51.640651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2242 11:12:51.643840 ===================================
2243 11:12:51.647211 data_rate = 2400,PCW = 0X5b00
2244 11:12:51.650332 ===================================
2245 11:12:51.653552 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2246 11:12:51.656857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2247 11:12:51.663479 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2248 11:12:51.666644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2249 11:12:51.669926 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2250 11:12:51.673910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2251 11:12:51.676949 [ANA_INIT] flow start
2252 11:12:51.680047 [ANA_INIT] PLL >>>>>>>>
2253 11:12:51.680155 [ANA_INIT] PLL <<<<<<<<
2254 11:12:51.684026 [ANA_INIT] MIDPI >>>>>>>>
2255 11:12:51.687144 [ANA_INIT] MIDPI <<<<<<<<
2256 11:12:51.687238 [ANA_INIT] DLL >>>>>>>>
2257 11:12:51.690513 [ANA_INIT] DLL <<<<<<<<
2258 11:12:51.693794 [ANA_INIT] flow end
2259 11:12:51.697028 ============ LP4 DIFF to SE enter ============
2260 11:12:51.700183 ============ LP4 DIFF to SE exit ============
2261 11:12:51.703473 [ANA_INIT] <<<<<<<<<<<<<
2262 11:12:51.706719 [Flow] Enable top DCM control >>>>>
2263 11:12:51.709992 [Flow] Enable top DCM control <<<<<
2264 11:12:51.713299 Enable DLL master slave shuffle
2265 11:12:51.717269 ==============================================================
2266 11:12:51.720563 Gating Mode config
2267 11:12:51.726901 ==============================================================
2268 11:12:51.727014 Config description:
2269 11:12:51.736631 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2270 11:12:51.743236 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2271 11:12:51.746877 SELPH_MODE 0: By rank 1: By Phase
2272 11:12:51.753537 ==============================================================
2273 11:12:51.757131 GAT_TRACK_EN = 1
2274 11:12:51.759712 RX_GATING_MODE = 2
2275 11:12:51.763490 RX_GATING_TRACK_MODE = 2
2276 11:12:51.766644 SELPH_MODE = 1
2277 11:12:51.769845 PICG_EARLY_EN = 1
2278 11:12:51.773118 VALID_LAT_VALUE = 1
2279 11:12:51.776483 ==============================================================
2280 11:12:51.780333 Enter into Gating configuration >>>>
2281 11:12:51.783547 Exit from Gating configuration <<<<
2282 11:12:51.786531 Enter into DVFS_PRE_config >>>>>
2283 11:12:51.796874 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2284 11:12:51.800127 Exit from DVFS_PRE_config <<<<<
2285 11:12:51.803295 Enter into PICG configuration >>>>
2286 11:12:51.806789 Exit from PICG configuration <<<<
2287 11:12:51.809968 [RX_INPUT] configuration >>>>>
2288 11:12:51.813364 [RX_INPUT] configuration <<<<<
2289 11:12:51.819944 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2290 11:12:51.823152 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2291 11:12:51.830165 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2292 11:12:51.836860 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2293 11:12:51.843382 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2294 11:12:51.849953 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2295 11:12:51.853429 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2296 11:12:51.857207 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2297 11:12:51.860073 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2298 11:12:51.863485 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2299 11:12:51.870354 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2300 11:12:51.873479 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2301 11:12:51.876747 ===================================
2302 11:12:51.880634 LPDDR4 DRAM CONFIGURATION
2303 11:12:51.883708 ===================================
2304 11:12:51.883824 EX_ROW_EN[0] = 0x0
2305 11:12:51.886969 EX_ROW_EN[1] = 0x0
2306 11:12:51.887071 LP4Y_EN = 0x0
2307 11:12:51.890089 WORK_FSP = 0x0
2308 11:12:51.890198 WL = 0x4
2309 11:12:51.893805 RL = 0x4
2310 11:12:51.893909 BL = 0x2
2311 11:12:51.897116 RPST = 0x0
2312 11:12:51.897223 RD_PRE = 0x0
2313 11:12:51.900301 WR_PRE = 0x1
2314 11:12:51.903505 WR_PST = 0x0
2315 11:12:51.903614 DBI_WR = 0x0
2316 11:12:51.906759 DBI_RD = 0x0
2317 11:12:51.906865 OTF = 0x1
2318 11:12:51.910539 ===================================
2319 11:12:51.913889 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2320 11:12:51.917096 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2321 11:12:51.923880 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2322 11:12:51.926914 ===================================
2323 11:12:51.930144 LPDDR4 DRAM CONFIGURATION
2324 11:12:51.933350 ===================================
2325 11:12:51.933461 EX_ROW_EN[0] = 0x10
2326 11:12:51.937264 EX_ROW_EN[1] = 0x0
2327 11:12:51.937364 LP4Y_EN = 0x0
2328 11:12:51.940537 WORK_FSP = 0x0
2329 11:12:51.940644 WL = 0x4
2330 11:12:51.943672 RL = 0x4
2331 11:12:51.943778 BL = 0x2
2332 11:12:51.946781 RPST = 0x0
2333 11:12:51.946886 RD_PRE = 0x0
2334 11:12:51.950198 WR_PRE = 0x1
2335 11:12:51.950300 WR_PST = 0x0
2336 11:12:51.953947 DBI_WR = 0x0
2337 11:12:51.954065 DBI_RD = 0x0
2338 11:12:51.956905 OTF = 0x1
2339 11:12:51.960155 ===================================
2340 11:12:51.967010 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2341 11:12:51.967119 ==
2342 11:12:51.970774 Dram Type= 6, Freq= 0, CH_0, rank 0
2343 11:12:51.973573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2344 11:12:51.973681 ==
2345 11:12:51.977092 [Duty_Offset_Calibration]
2346 11:12:51.977197 B0:2 B1:-1 CA:1
2347 11:12:51.977291
2348 11:12:51.980805 [DutyScan_Calibration_Flow] k_type=0
2349 11:12:51.990266
2350 11:12:51.990375 ==CLK 0==
2351 11:12:51.993597 Final CLK duty delay cell = -4
2352 11:12:51.996595 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2353 11:12:51.999918 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2354 11:12:52.003190 [-4] AVG Duty = 4953%(X100)
2355 11:12:52.003293
2356 11:12:52.006342 CH0 CLK Duty spec in!! Max-Min= 156%
2357 11:12:52.010366 [DutyScan_Calibration_Flow] ====Done====
2358 11:12:52.010470
2359 11:12:52.013340 [DutyScan_Calibration_Flow] k_type=1
2360 11:12:52.028891
2361 11:12:52.028994 ==DQS 0 ==
2362 11:12:52.032142 Final DQS duty delay cell = 0
2363 11:12:52.035363 [0] MAX Duty = 5125%(X100), DQS PI = 48
2364 11:12:52.039080 [0] MIN Duty = 5000%(X100), DQS PI = 12
2365 11:12:52.042409 [0] AVG Duty = 5062%(X100)
2366 11:12:52.042515
2367 11:12:52.042611 ==DQS 1 ==
2368 11:12:52.045640 Final DQS duty delay cell = -4
2369 11:12:52.048849 [-4] MAX Duty = 5124%(X100), DQS PI = 4
2370 11:12:52.052165 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2371 11:12:52.055445 [-4] AVG Duty = 5062%(X100)
2372 11:12:52.055529
2373 11:12:52.058565 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2374 11:12:52.058662
2375 11:12:52.062198 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2376 11:12:52.065160 [DutyScan_Calibration_Flow] ====Done====
2377 11:12:52.065262
2378 11:12:52.068271 [DutyScan_Calibration_Flow] k_type=3
2379 11:12:52.085702
2380 11:12:52.085829 ==DQM 0 ==
2381 11:12:52.089140 Final DQM duty delay cell = 0
2382 11:12:52.092679 [0] MAX Duty = 5000%(X100), DQS PI = 54
2383 11:12:52.095418 [0] MIN Duty = 4907%(X100), DQS PI = 2
2384 11:12:52.095491 [0] AVG Duty = 4953%(X100)
2385 11:12:52.098917
2386 11:12:52.099019 ==DQM 1 ==
2387 11:12:52.102061 Final DQM duty delay cell = 0
2388 11:12:52.105880 [0] MAX Duty = 5124%(X100), DQS PI = 32
2389 11:12:52.109067 [0] MIN Duty = 4969%(X100), DQS PI = 10
2390 11:12:52.109171 [0] AVG Duty = 5046%(X100)
2391 11:12:52.112482
2392 11:12:52.115526 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2393 11:12:52.115631
2394 11:12:52.118836 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2395 11:12:52.122133 [DutyScan_Calibration_Flow] ====Done====
2396 11:12:52.122216
2397 11:12:52.125322 [DutyScan_Calibration_Flow] k_type=2
2398 11:12:52.141460
2399 11:12:52.141568 ==DQ 0 ==
2400 11:12:52.144768 Final DQ duty delay cell = -4
2401 11:12:52.148044 [-4] MAX Duty = 5062%(X100), DQS PI = 56
2402 11:12:52.151241 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2403 11:12:52.155062 [-4] AVG Duty = 4984%(X100)
2404 11:12:52.155171
2405 11:12:52.155271 ==DQ 1 ==
2406 11:12:52.157728 Final DQ duty delay cell = 0
2407 11:12:52.160998 [0] MAX Duty = 5031%(X100), DQS PI = 26
2408 11:12:52.164994 [0] MIN Duty = 4907%(X100), DQS PI = 46
2409 11:12:52.167804 [0] AVG Duty = 4969%(X100)
2410 11:12:52.167888
2411 11:12:52.171036 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2412 11:12:52.171120
2413 11:12:52.174350 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2414 11:12:52.177818 [DutyScan_Calibration_Flow] ====Done====
2415 11:12:52.177901 ==
2416 11:12:52.181143 Dram Type= 6, Freq= 0, CH_1, rank 0
2417 11:12:52.184566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2418 11:12:52.184679 ==
2419 11:12:52.187650 [Duty_Offset_Calibration]
2420 11:12:52.187734 B0:1 B1:1 CA:2
2421 11:12:52.187800
2422 11:12:52.190993 [DutyScan_Calibration_Flow] k_type=0
2423 11:12:52.201626
2424 11:12:52.201713 ==CLK 0==
2425 11:12:52.205259 Final CLK duty delay cell = 0
2426 11:12:52.208378 [0] MAX Duty = 5156%(X100), DQS PI = 24
2427 11:12:52.211342 [0] MIN Duty = 4938%(X100), DQS PI = 46
2428 11:12:52.211430 [0] AVG Duty = 5047%(X100)
2429 11:12:52.215105
2430 11:12:52.218349 CH1 CLK Duty spec in!! Max-Min= 218%
2431 11:12:52.221539 [DutyScan_Calibration_Flow] ====Done====
2432 11:12:52.221626
2433 11:12:52.224860 [DutyScan_Calibration_Flow] k_type=1
2434 11:12:52.241158
2435 11:12:52.241245 ==DQS 0 ==
2436 11:12:52.244289 Final DQS duty delay cell = 0
2437 11:12:52.248056 [0] MAX Duty = 5031%(X100), DQS PI = 18
2438 11:12:52.251273 [0] MIN Duty = 4813%(X100), DQS PI = 50
2439 11:12:52.254572 [0] AVG Duty = 4922%(X100)
2440 11:12:52.254658
2441 11:12:52.254727 ==DQS 1 ==
2442 11:12:52.257232 Final DQS duty delay cell = 0
2443 11:12:52.260471 [0] MAX Duty = 5062%(X100), DQS PI = 36
2444 11:12:52.264421 [0] MIN Duty = 4907%(X100), DQS PI = 0
2445 11:12:52.267495 [0] AVG Duty = 4984%(X100)
2446 11:12:52.267574
2447 11:12:52.270525 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2448 11:12:52.270600
2449 11:12:52.274171 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2450 11:12:52.277528 [DutyScan_Calibration_Flow] ====Done====
2451 11:12:52.277607
2452 11:12:52.280674 [DutyScan_Calibration_Flow] k_type=3
2453 11:12:52.297393
2454 11:12:52.297486 ==DQM 0 ==
2455 11:12:52.300732 Final DQM duty delay cell = 0
2456 11:12:52.304137 [0] MAX Duty = 5093%(X100), DQS PI = 16
2457 11:12:52.307766 [0] MIN Duty = 4875%(X100), DQS PI = 48
2458 11:12:52.310945 [0] AVG Duty = 4984%(X100)
2459 11:12:52.311062
2460 11:12:52.311166 ==DQM 1 ==
2461 11:12:52.314338 Final DQM duty delay cell = 0
2462 11:12:52.317324 [0] MAX Duty = 5156%(X100), DQS PI = 60
2463 11:12:52.320955 [0] MIN Duty = 4938%(X100), DQS PI = 22
2464 11:12:52.324040 [0] AVG Duty = 5047%(X100)
2465 11:12:52.324126
2466 11:12:52.327327 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2467 11:12:52.327447
2468 11:12:52.330586 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2469 11:12:52.334480 [DutyScan_Calibration_Flow] ====Done====
2470 11:12:52.334564
2471 11:12:52.337786 [DutyScan_Calibration_Flow] k_type=2
2472 11:12:52.354070
2473 11:12:52.354156 ==DQ 0 ==
2474 11:12:52.357345 Final DQ duty delay cell = 0
2475 11:12:52.360705 [0] MAX Duty = 5125%(X100), DQS PI = 18
2476 11:12:52.363948 [0] MIN Duty = 4938%(X100), DQS PI = 50
2477 11:12:52.364061 [0] AVG Duty = 5031%(X100)
2478 11:12:52.367159
2479 11:12:52.367264 ==DQ 1 ==
2480 11:12:52.371099 Final DQ duty delay cell = 0
2481 11:12:52.374069 [0] MAX Duty = 5124%(X100), DQS PI = 58
2482 11:12:52.377311 [0] MIN Duty = 5031%(X100), DQS PI = 2
2483 11:12:52.377417 [0] AVG Duty = 5077%(X100)
2484 11:12:52.377524
2485 11:12:52.381081 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2486 11:12:52.384328
2487 11:12:52.387631 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2488 11:12:52.390818 [DutyScan_Calibration_Flow] ====Done====
2489 11:12:52.394169 nWR fixed to 30
2490 11:12:52.394281 [ModeRegInit_LP4] CH0 RK0
2491 11:12:52.397360 [ModeRegInit_LP4] CH0 RK1
2492 11:12:52.400916 [ModeRegInit_LP4] CH1 RK0
2493 11:12:52.401033 [ModeRegInit_LP4] CH1 RK1
2494 11:12:52.404093 match AC timing 7
2495 11:12:52.407266 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2496 11:12:52.410624 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2497 11:12:52.417149 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2498 11:12:52.420854 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2499 11:12:52.427270 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2500 11:12:52.427395 ==
2501 11:12:52.430434 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 11:12:52.434448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 11:12:52.434536 ==
2504 11:12:52.440943 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2505 11:12:52.444151 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2506 11:12:52.453896 [CA 0] Center 40 (10~71) winsize 62
2507 11:12:52.457589 [CA 1] Center 39 (9~70) winsize 62
2508 11:12:52.460919 [CA 2] Center 36 (6~67) winsize 62
2509 11:12:52.464175 [CA 3] Center 36 (5~67) winsize 63
2510 11:12:52.467472 [CA 4] Center 35 (5~65) winsize 61
2511 11:12:52.470666 [CA 5] Center 34 (4~64) winsize 61
2512 11:12:52.470743
2513 11:12:52.473963 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2514 11:12:52.474040
2515 11:12:52.477778 [CATrainingPosCal] consider 1 rank data
2516 11:12:52.480727 u2DelayCellTimex100 = 270/100 ps
2517 11:12:52.483953 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2518 11:12:52.490526 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2519 11:12:52.494536 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2520 11:12:52.497143 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2521 11:12:52.500882 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2522 11:12:52.504017 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2523 11:12:52.504098
2524 11:12:52.507433 CA PerBit enable=1, Macro0, CA PI delay=34
2525 11:12:52.507520
2526 11:12:52.510491 [CBTSetCACLKResult] CA Dly = 34
2527 11:12:52.510567 CS Dly: 7 (0~38)
2528 11:12:52.514298 ==
2529 11:12:52.514388 Dram Type= 6, Freq= 0, CH_0, rank 1
2530 11:12:52.521056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 11:12:52.521137 ==
2532 11:12:52.523949 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2533 11:12:52.530716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2534 11:12:52.539893 [CA 0] Center 39 (9~70) winsize 62
2535 11:12:52.543289 [CA 1] Center 39 (9~70) winsize 62
2536 11:12:52.546614 [CA 2] Center 36 (6~67) winsize 62
2537 11:12:52.550415 [CA 3] Center 36 (5~67) winsize 63
2538 11:12:52.553639 [CA 4] Center 34 (4~65) winsize 62
2539 11:12:52.556919 [CA 5] Center 34 (4~64) winsize 61
2540 11:12:52.557006
2541 11:12:52.559904 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2542 11:12:52.559987
2543 11:12:52.563755 [CATrainingPosCal] consider 2 rank data
2544 11:12:52.567009 u2DelayCellTimex100 = 270/100 ps
2545 11:12:52.570317 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2546 11:12:52.573616 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2547 11:12:52.580070 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2548 11:12:52.583828 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2549 11:12:52.586910 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2550 11:12:52.590152 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2551 11:12:52.590268
2552 11:12:52.593444 CA PerBit enable=1, Macro0, CA PI delay=34
2553 11:12:52.593526
2554 11:12:52.596689 [CBTSetCACLKResult] CA Dly = 34
2555 11:12:52.596775 CS Dly: 8 (0~41)
2556 11:12:52.596841
2557 11:12:52.600013 ----->DramcWriteLeveling(PI) begin...
2558 11:12:52.600093 ==
2559 11:12:52.603827 Dram Type= 6, Freq= 0, CH_0, rank 0
2560 11:12:52.609969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2561 11:12:52.610060 ==
2562 11:12:52.613721 Write leveling (Byte 0): 33 => 33
2563 11:12:52.616983 Write leveling (Byte 1): 29 => 29
2564 11:12:52.617063 DramcWriteLeveling(PI) end<-----
2565 11:12:52.620158
2566 11:12:52.620238 ==
2567 11:12:52.623616 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 11:12:52.626556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 11:12:52.626671 ==
2570 11:12:52.630138 [Gating] SW mode calibration
2571 11:12:52.636784 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2572 11:12:52.639987 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2573 11:12:52.646619 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 11:12:52.650568 0 15 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2575 11:12:52.653755 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2576 11:12:52.660121 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 11:12:52.663249 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 11:12:52.667061 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 11:12:52.673610 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 11:12:52.676904 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 11:12:52.680015 1 0 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2582 11:12:52.687028 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2583 11:12:52.690047 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 11:12:52.693774 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 11:12:52.700376 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 11:12:52.703474 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 11:12:52.706596 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 11:12:52.710459 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 11:12:52.716696 1 1 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2590 11:12:52.720330 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2591 11:12:52.723646 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 11:12:52.730096 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 11:12:52.733565 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 11:12:52.737194 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 11:12:52.743951 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 11:12:52.746953 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 11:12:52.750502 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2598 11:12:52.757065 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 11:12:52.760369 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 11:12:52.763547 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 11:12:52.770628 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 11:12:52.773851 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 11:12:52.777133 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 11:12:52.783583 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 11:12:52.787477 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 11:12:52.790584 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 11:12:52.793637 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 11:12:52.800651 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 11:12:52.803946 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 11:12:52.807127 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 11:12:52.813625 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 11:12:52.816916 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 11:12:52.820622 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2614 11:12:52.827273 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2615 11:12:52.830530 Total UI for P1: 0, mck2ui 16
2616 11:12:52.833740 best dqsien dly found for B0: ( 1, 4, 0)
2617 11:12:52.836936 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 11:12:52.840099 Total UI for P1: 0, mck2ui 16
2619 11:12:52.844126 best dqsien dly found for B1: ( 1, 4, 2)
2620 11:12:52.847054 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2621 11:12:52.850153 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2622 11:12:52.850258
2623 11:12:52.853799 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2624 11:12:52.856972 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2625 11:12:52.860256 [Gating] SW calibration Done
2626 11:12:52.860334 ==
2627 11:12:52.863485 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 11:12:52.866809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 11:12:52.866884 ==
2630 11:12:52.870578 RX Vref Scan: 0
2631 11:12:52.870654
2632 11:12:52.873676 RX Vref 0 -> 0, step: 1
2633 11:12:52.873750
2634 11:12:52.873813 RX Delay -40 -> 252, step: 8
2635 11:12:52.880718 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2636 11:12:52.883503 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2637 11:12:52.886656 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2638 11:12:52.890588 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2639 11:12:52.893807 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2640 11:12:52.900149 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2641 11:12:52.903487 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2642 11:12:52.906754 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2643 11:12:52.909968 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2644 11:12:52.913250 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2645 11:12:52.920454 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2646 11:12:52.923710 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2647 11:12:52.926872 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2648 11:12:52.930030 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2649 11:12:52.933562 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2650 11:12:52.939902 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2651 11:12:52.939971 ==
2652 11:12:52.943548 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 11:12:52.947293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 11:12:52.947369 ==
2655 11:12:52.947432 DQS Delay:
2656 11:12:52.950353 DQS0 = 0, DQS1 = 0
2657 11:12:52.950423 DQM Delay:
2658 11:12:52.953419 DQM0 = 115, DQM1 = 107
2659 11:12:52.953491 DQ Delay:
2660 11:12:52.956878 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2661 11:12:52.960509 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2662 11:12:52.963785 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2663 11:12:52.966933 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2664 11:12:52.967030
2665 11:12:52.967120
2666 11:12:52.967207 ==
2667 11:12:52.970133 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 11:12:52.976912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 11:12:52.977015 ==
2670 11:12:52.977114
2671 11:12:52.977203
2672 11:12:52.977291 TX Vref Scan disable
2673 11:12:52.980852 == TX Byte 0 ==
2674 11:12:52.984129 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2675 11:12:52.990698 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2676 11:12:52.990811 == TX Byte 1 ==
2677 11:12:52.993815 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2678 11:12:53.000292 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2679 11:12:53.000423 ==
2680 11:12:53.003656 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 11:12:53.007485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 11:12:53.007586 ==
2683 11:12:53.018895 TX Vref=22, minBit 1, minWin=24, winSum=415
2684 11:12:53.022077 TX Vref=24, minBit 7, minWin=25, winSum=423
2685 11:12:53.025265 TX Vref=26, minBit 0, minWin=26, winSum=427
2686 11:12:53.029132 TX Vref=28, minBit 0, minWin=26, winSum=431
2687 11:12:53.032357 TX Vref=30, minBit 0, minWin=26, winSum=432
2688 11:12:53.035569 TX Vref=32, minBit 0, minWin=26, winSum=432
2689 11:12:53.042639 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 30
2690 11:12:53.042736
2691 11:12:53.045652 Final TX Range 1 Vref 30
2692 11:12:53.045735
2693 11:12:53.045800 ==
2694 11:12:53.048918 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 11:12:53.052247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 11:12:53.052348 ==
2697 11:12:53.052429
2698 11:12:53.055706
2699 11:12:53.055790 TX Vref Scan disable
2700 11:12:53.058878 == TX Byte 0 ==
2701 11:12:53.062446 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2702 11:12:53.065515 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2703 11:12:53.069248 == TX Byte 1 ==
2704 11:12:53.072252 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2705 11:12:53.075591 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2706 11:12:53.075666
2707 11:12:53.078904 [DATLAT]
2708 11:12:53.079005 Freq=1200, CH0 RK0
2709 11:12:53.079125
2710 11:12:53.081872 DATLAT Default: 0xd
2711 11:12:53.081976 0, 0xFFFF, sum = 0
2712 11:12:53.085811 1, 0xFFFF, sum = 0
2713 11:12:53.085914 2, 0xFFFF, sum = 0
2714 11:12:53.089007 3, 0xFFFF, sum = 0
2715 11:12:53.089147 4, 0xFFFF, sum = 0
2716 11:12:53.092267 5, 0xFFFF, sum = 0
2717 11:12:53.092377 6, 0xFFFF, sum = 0
2718 11:12:53.095292 7, 0xFFFF, sum = 0
2719 11:12:53.095439 8, 0xFFFF, sum = 0
2720 11:12:53.098560 9, 0xFFFF, sum = 0
2721 11:12:53.102406 10, 0xFFFF, sum = 0
2722 11:12:53.102512 11, 0xFFFF, sum = 0
2723 11:12:53.105644 12, 0x0, sum = 1
2724 11:12:53.105757 13, 0x0, sum = 2
2725 11:12:53.105856 14, 0x0, sum = 3
2726 11:12:53.108874 15, 0x0, sum = 4
2727 11:12:53.108985 best_step = 13
2728 11:12:53.109078
2729 11:12:53.111983 ==
2730 11:12:53.112087 Dram Type= 6, Freq= 0, CH_0, rank 0
2731 11:12:53.118852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2732 11:12:53.118961 ==
2733 11:12:53.119056 RX Vref Scan: 1
2734 11:12:53.119152
2735 11:12:53.122368 Set Vref Range= 32 -> 127
2736 11:12:53.122453
2737 11:12:53.125375 RX Vref 32 -> 127, step: 1
2738 11:12:53.125459
2739 11:12:53.128683 RX Delay -21 -> 252, step: 4
2740 11:12:53.128767
2741 11:12:53.131898 Set Vref, RX VrefLevel [Byte0]: 32
2742 11:12:53.135172 [Byte1]: 32
2743 11:12:53.135256
2744 11:12:53.138914 Set Vref, RX VrefLevel [Byte0]: 33
2745 11:12:53.141963 [Byte1]: 33
2746 11:12:53.142047
2747 11:12:53.145594 Set Vref, RX VrefLevel [Byte0]: 34
2748 11:12:53.148855 [Byte1]: 34
2749 11:12:53.152724
2750 11:12:53.156529 Set Vref, RX VrefLevel [Byte0]: 35
2751 11:12:53.156615 [Byte1]: 35
2752 11:12:53.161031
2753 11:12:53.161114 Set Vref, RX VrefLevel [Byte0]: 36
2754 11:12:53.164163 [Byte1]: 36
2755 11:12:53.169049
2756 11:12:53.169134 Set Vref, RX VrefLevel [Byte0]: 37
2757 11:12:53.171973 [Byte1]: 37
2758 11:12:53.176975
2759 11:12:53.177059 Set Vref, RX VrefLevel [Byte0]: 38
2760 11:12:53.180347 [Byte1]: 38
2761 11:12:53.184703
2762 11:12:53.184788 Set Vref, RX VrefLevel [Byte0]: 39
2763 11:12:53.187951 [Byte1]: 39
2764 11:12:53.192380
2765 11:12:53.192503 Set Vref, RX VrefLevel [Byte0]: 40
2766 11:12:53.195667 [Byte1]: 40
2767 11:12:53.200297
2768 11:12:53.200381 Set Vref, RX VrefLevel [Byte0]: 41
2769 11:12:53.203595 [Byte1]: 41
2770 11:12:53.208167
2771 11:12:53.208251 Set Vref, RX VrefLevel [Byte0]: 42
2772 11:12:53.211485 [Byte1]: 42
2773 11:12:53.216519
2774 11:12:53.216636 Set Vref, RX VrefLevel [Byte0]: 43
2775 11:12:53.223029 [Byte1]: 43
2776 11:12:53.223120
2777 11:12:53.226345 Set Vref, RX VrefLevel [Byte0]: 44
2778 11:12:53.229518 [Byte1]: 44
2779 11:12:53.229603
2780 11:12:53.232910 Set Vref, RX VrefLevel [Byte0]: 45
2781 11:12:53.235939 [Byte1]: 45
2782 11:12:53.240605
2783 11:12:53.240692 Set Vref, RX VrefLevel [Byte0]: 46
2784 11:12:53.243628 [Byte1]: 46
2785 11:12:53.247684
2786 11:12:53.247792 Set Vref, RX VrefLevel [Byte0]: 47
2787 11:12:53.251523 [Byte1]: 47
2788 11:12:53.256143
2789 11:12:53.256229 Set Vref, RX VrefLevel [Byte0]: 48
2790 11:12:53.259251 [Byte1]: 48
2791 11:12:53.263808
2792 11:12:53.263919 Set Vref, RX VrefLevel [Byte0]: 49
2793 11:12:53.267216 [Byte1]: 49
2794 11:12:53.271753
2795 11:12:53.271878 Set Vref, RX VrefLevel [Byte0]: 50
2796 11:12:53.275368 [Byte1]: 50
2797 11:12:53.279426
2798 11:12:53.279512 Set Vref, RX VrefLevel [Byte0]: 51
2799 11:12:53.283080 [Byte1]: 51
2800 11:12:53.287586
2801 11:12:53.287682 Set Vref, RX VrefLevel [Byte0]: 52
2802 11:12:53.290791 [Byte1]: 52
2803 11:12:53.295302
2804 11:12:53.295407 Set Vref, RX VrefLevel [Byte0]: 53
2805 11:12:53.298633 [Byte1]: 53
2806 11:12:53.303158
2807 11:12:53.303274 Set Vref, RX VrefLevel [Byte0]: 54
2808 11:12:53.307086 [Byte1]: 54
2809 11:12:53.311089
2810 11:12:53.311199 Set Vref, RX VrefLevel [Byte0]: 55
2811 11:12:53.315010 [Byte1]: 55
2812 11:12:53.319486
2813 11:12:53.322381 Set Vref, RX VrefLevel [Byte0]: 56
2814 11:12:53.322489 [Byte1]: 56
2815 11:12:53.327527
2816 11:12:53.327641 Set Vref, RX VrefLevel [Byte0]: 57
2817 11:12:53.330654 [Byte1]: 57
2818 11:12:53.335329
2819 11:12:53.335422 Set Vref, RX VrefLevel [Byte0]: 58
2820 11:12:53.338432 [Byte1]: 58
2821 11:12:53.342954
2822 11:12:53.343038 Set Vref, RX VrefLevel [Byte0]: 59
2823 11:12:53.346856 [Byte1]: 59
2824 11:12:53.351081
2825 11:12:53.351194 Set Vref, RX VrefLevel [Byte0]: 60
2826 11:12:53.354159 [Byte1]: 60
2827 11:12:53.358681
2828 11:12:53.358765 Set Vref, RX VrefLevel [Byte0]: 61
2829 11:12:53.362594 [Byte1]: 61
2830 11:12:53.367080
2831 11:12:53.367192 Set Vref, RX VrefLevel [Byte0]: 62
2832 11:12:53.370353 [Byte1]: 62
2833 11:12:53.374898
2834 11:12:53.375004 Set Vref, RX VrefLevel [Byte0]: 63
2835 11:12:53.378099 [Byte1]: 63
2836 11:12:53.382552
2837 11:12:53.382636 Set Vref, RX VrefLevel [Byte0]: 64
2838 11:12:53.389321 [Byte1]: 64
2839 11:12:53.389460
2840 11:12:53.392596 Set Vref, RX VrefLevel [Byte0]: 65
2841 11:12:53.395604 [Byte1]: 65
2842 11:12:53.395731
2843 11:12:53.399062 Set Vref, RX VrefLevel [Byte0]: 66
2844 11:12:53.402333 [Byte1]: 66
2845 11:12:53.406924
2846 11:12:53.407044 Set Vref, RX VrefLevel [Byte0]: 67
2847 11:12:53.410016 [Byte1]: 67
2848 11:12:53.414718
2849 11:12:53.414816 Set Vref, RX VrefLevel [Byte0]: 68
2850 11:12:53.417878 [Byte1]: 68
2851 11:12:53.422400
2852 11:12:53.422506 Set Vref, RX VrefLevel [Byte0]: 69
2853 11:12:53.425448 [Byte1]: 69
2854 11:12:53.430363
2855 11:12:53.430455 Final RX Vref Byte 0 = 55 to rank0
2856 11:12:53.433621 Final RX Vref Byte 1 = 50 to rank0
2857 11:12:53.436897 Final RX Vref Byte 0 = 55 to rank1
2858 11:12:53.440494 Final RX Vref Byte 1 = 50 to rank1==
2859 11:12:53.443882 Dram Type= 6, Freq= 0, CH_0, rank 0
2860 11:12:53.450393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 11:12:53.450517 ==
2862 11:12:53.450621 DQS Delay:
2863 11:12:53.450714 DQS0 = 0, DQS1 = 0
2864 11:12:53.453414 DQM Delay:
2865 11:12:53.453519 DQM0 = 115, DQM1 = 104
2866 11:12:53.457132 DQ Delay:
2867 11:12:53.460225 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2868 11:12:53.463485 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2869 11:12:53.466730 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2870 11:12:53.470622 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2871 11:12:53.470750
2872 11:12:53.470837
2873 11:12:53.477199 [DQSOSCAuto] RK0, (LSB)MR18= 0xef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2874 11:12:53.480491 CH0 RK0: MR19=403, MR18=EF
2875 11:12:53.486903 CH0_RK0: MR19=0x403, MR18=0xEF, DQSOSC=410, MR23=63, INC=39, DEC=26
2876 11:12:53.487129
2877 11:12:53.490875 ----->DramcWriteLeveling(PI) begin...
2878 11:12:53.491041 ==
2879 11:12:53.493738 Dram Type= 6, Freq= 0, CH_0, rank 1
2880 11:12:53.497255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2881 11:12:53.497421 ==
2882 11:12:53.500210 Write leveling (Byte 0): 30 => 30
2883 11:12:53.503860 Write leveling (Byte 1): 29 => 29
2884 11:12:53.506873 DramcWriteLeveling(PI) end<-----
2885 11:12:53.507070
2886 11:12:53.507246 ==
2887 11:12:53.510463 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 11:12:53.513756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 11:12:53.514005 ==
2890 11:12:53.517067 [Gating] SW mode calibration
2891 11:12:53.523695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2892 11:12:53.530584 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2893 11:12:53.533479 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2894 11:12:53.540740 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2895 11:12:53.543886 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 11:12:53.547088 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 11:12:53.553525 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 11:12:53.557429 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 11:12:53.560405 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 11:12:53.564040 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
2901 11:12:53.570509 1 0 0 | B1->B0 | 2a2a 2424 | 0 0 | (0 1) (0 0)
2902 11:12:53.573752 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2903 11:12:53.577131 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 11:12:53.583944 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 11:12:53.587101 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 11:12:53.590246 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 11:12:53.597248 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2908 11:12:53.600624 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2909 11:12:53.603898 1 1 0 | B1->B0 | 2626 3838 | 0 0 | (1 1) (0 0)
2910 11:12:53.610430 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 11:12:53.613964 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 11:12:53.616887 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 11:12:53.623687 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 11:12:53.626911 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 11:12:53.630760 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 11:12:53.637044 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2917 11:12:53.640726 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2918 11:12:53.643957 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2919 11:12:53.647271 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 11:12:53.653664 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 11:12:53.656907 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 11:12:53.660180 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 11:12:53.667017 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 11:12:53.670221 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 11:12:53.674083 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 11:12:53.680579 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 11:12:53.683906 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:12:53.687158 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:12:53.693678 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:12:53.696825 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:12:53.700720 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2932 11:12:53.706905 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2933 11:12:53.710730 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2934 11:12:53.713977 Total UI for P1: 0, mck2ui 16
2935 11:12:53.716995 best dqsien dly found for B0: ( 1, 3, 26)
2936 11:12:53.720648 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 11:12:53.723707 Total UI for P1: 0, mck2ui 16
2938 11:12:53.726811 best dqsien dly found for B1: ( 1, 4, 0)
2939 11:12:53.730400 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2940 11:12:53.733636 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2941 11:12:53.733746
2942 11:12:53.736828 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2943 11:12:53.743870 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2944 11:12:53.743959 [Gating] SW calibration Done
2945 11:12:53.744040 ==
2946 11:12:53.746733 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 11:12:53.753274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 11:12:53.753388 ==
2949 11:12:53.753506 RX Vref Scan: 0
2950 11:12:53.753607
2951 11:12:53.757014 RX Vref 0 -> 0, step: 1
2952 11:12:53.757132
2953 11:12:53.760363 RX Delay -40 -> 252, step: 8
2954 11:12:53.763553 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2955 11:12:53.766875 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2956 11:12:53.770005 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2957 11:12:53.776689 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2958 11:12:53.779873 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2959 11:12:53.783161 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2960 11:12:53.786553 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2961 11:12:53.789859 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2962 11:12:53.793820 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2963 11:12:53.800444 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2964 11:12:53.803345 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2965 11:12:53.806603 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2966 11:12:53.810383 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2967 11:12:53.813436 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2968 11:12:53.820024 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2969 11:12:53.823802 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2970 11:12:53.823881 ==
2971 11:12:53.826783 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 11:12:53.830129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 11:12:53.830208 ==
2974 11:12:53.833249 DQS Delay:
2975 11:12:53.833331 DQS0 = 0, DQS1 = 0
2976 11:12:53.833399 DQM Delay:
2977 11:12:53.836416 DQM0 = 116, DQM1 = 105
2978 11:12:53.836506 DQ Delay:
2979 11:12:53.840085 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2980 11:12:53.843301 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2981 11:12:53.846522 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2982 11:12:53.853483 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2983 11:12:53.853575
2984 11:12:53.853643
2985 11:12:53.853709 ==
2986 11:12:53.856637 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 11:12:53.860016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 11:12:53.860100 ==
2989 11:12:53.860170
2990 11:12:53.860235
2991 11:12:53.863305 TX Vref Scan disable
2992 11:12:53.863381 == TX Byte 0 ==
2993 11:12:53.870309 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2994 11:12:53.873722 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2995 11:12:53.873795 == TX Byte 1 ==
2996 11:12:53.879845 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2997 11:12:53.883194 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2998 11:12:53.883305 ==
2999 11:12:53.886441 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 11:12:53.889731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 11:12:53.889820 ==
3002 11:12:53.903091 TX Vref=22, minBit 5, minWin=25, winSum=423
3003 11:12:53.906298 TX Vref=24, minBit 0, minWin=26, winSum=427
3004 11:12:53.909516 TX Vref=26, minBit 0, minWin=27, winSum=439
3005 11:12:53.912974 TX Vref=28, minBit 5, minWin=26, winSum=437
3006 11:12:53.915874 TX Vref=30, minBit 12, minWin=26, winSum=439
3007 11:12:53.923013 TX Vref=32, minBit 12, minWin=26, winSum=436
3008 11:12:53.926301 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 26
3009 11:12:53.926419
3010 11:12:53.929703 Final TX Range 1 Vref 26
3011 11:12:53.929783
3012 11:12:53.929856 ==
3013 11:12:53.932716 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 11:12:53.936276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 11:12:53.936354 ==
3016 11:12:53.939372
3017 11:12:53.939449
3018 11:12:53.939514 TX Vref Scan disable
3019 11:12:53.942938 == TX Byte 0 ==
3020 11:12:53.946516 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3021 11:12:53.949723 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3022 11:12:53.952742 == TX Byte 1 ==
3023 11:12:53.955903 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3024 11:12:53.959661 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3025 11:12:53.959751
3026 11:12:53.962835 [DATLAT]
3027 11:12:53.962942 Freq=1200, CH0 RK1
3028 11:12:53.963053
3029 11:12:53.966131 DATLAT Default: 0xd
3030 11:12:53.966264 0, 0xFFFF, sum = 0
3031 11:12:53.969494 1, 0xFFFF, sum = 0
3032 11:12:53.969606 2, 0xFFFF, sum = 0
3033 11:12:53.972635 3, 0xFFFF, sum = 0
3034 11:12:53.972714 4, 0xFFFF, sum = 0
3035 11:12:53.976507 5, 0xFFFF, sum = 0
3036 11:12:53.976630 6, 0xFFFF, sum = 0
3037 11:12:53.979579 7, 0xFFFF, sum = 0
3038 11:12:53.979680 8, 0xFFFF, sum = 0
3039 11:12:53.982851 9, 0xFFFF, sum = 0
3040 11:12:53.986079 10, 0xFFFF, sum = 0
3041 11:12:53.986200 11, 0xFFFF, sum = 0
3042 11:12:53.989452 12, 0x0, sum = 1
3043 11:12:53.989532 13, 0x0, sum = 2
3044 11:12:53.989610 14, 0x0, sum = 3
3045 11:12:53.992815 15, 0x0, sum = 4
3046 11:12:53.992896 best_step = 13
3047 11:12:53.992961
3048 11:12:53.995977 ==
3049 11:12:53.996056 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 11:12:54.003153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 11:12:54.003271 ==
3052 11:12:54.003375 RX Vref Scan: 0
3053 11:12:54.003440
3054 11:12:54.006371 RX Vref 0 -> 0, step: 1
3055 11:12:54.006441
3056 11:12:54.009455 RX Delay -21 -> 252, step: 4
3057 11:12:54.012628 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3058 11:12:54.015913 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3059 11:12:54.022731 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3060 11:12:54.025996 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3061 11:12:54.029717 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3062 11:12:54.032960 iDelay=195, Bit 5, Center 106 (39 ~ 174) 136
3063 11:12:54.036187 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3064 11:12:54.042706 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3065 11:12:54.046348 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3066 11:12:54.049260 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3067 11:12:54.052820 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3068 11:12:54.056479 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3069 11:12:54.063151 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3070 11:12:54.066274 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3071 11:12:54.069396 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3072 11:12:54.072721 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3073 11:12:54.072830 ==
3074 11:12:54.076099 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 11:12:54.079544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 11:12:54.082780 ==
3077 11:12:54.082892 DQS Delay:
3078 11:12:54.083001 DQS0 = 0, DQS1 = 0
3079 11:12:54.085886 DQM Delay:
3080 11:12:54.085995 DQM0 = 114, DQM1 = 104
3081 11:12:54.089808 DQ Delay:
3082 11:12:54.092946 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3083 11:12:54.096336 DQ4 =112, DQ5 =106, DQ6 =120, DQ7 =122
3084 11:12:54.099505 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3085 11:12:54.102719 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3086 11:12:54.102831
3087 11:12:54.102924
3088 11:12:54.109107 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3089 11:12:54.112927 CH0 RK1: MR19=403, MR18=5F6
3090 11:12:54.119221 CH0_RK1: MR19=0x403, MR18=0x5F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3091 11:12:54.122489 [RxdqsGatingPostProcess] freq 1200
3092 11:12:54.129543 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3093 11:12:54.129650 best DQS0 dly(2T, 0.5T) = (0, 12)
3094 11:12:54.132709 best DQS1 dly(2T, 0.5T) = (0, 12)
3095 11:12:54.135928 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3096 11:12:54.139769 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3097 11:12:54.142953 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 11:12:54.146156 best DQS1 dly(2T, 0.5T) = (0, 12)
3099 11:12:54.149303 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 11:12:54.152898 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3101 11:12:54.156054 Pre-setting of DQS Precalculation
3102 11:12:54.159737 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3103 11:12:54.162724 ==
3104 11:12:54.165806 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 11:12:54.169521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 11:12:54.169634 ==
3107 11:12:54.173296 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 11:12:54.179573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3109 11:12:54.188624 [CA 0] Center 37 (8~67) winsize 60
3110 11:12:54.191800 [CA 1] Center 38 (8~68) winsize 61
3111 11:12:54.195043 [CA 2] Center 35 (5~65) winsize 61
3112 11:12:54.198461 [CA 3] Center 34 (3~65) winsize 63
3113 11:12:54.201811 [CA 4] Center 34 (4~65) winsize 62
3114 11:12:54.205070 [CA 5] Center 33 (4~63) winsize 60
3115 11:12:54.205182
3116 11:12:54.208351 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3117 11:12:54.208426
3118 11:12:54.211748 [CATrainingPosCal] consider 1 rank data
3119 11:12:54.214987 u2DelayCellTimex100 = 270/100 ps
3120 11:12:54.218122 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3121 11:12:54.221777 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3122 11:12:54.228372 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3123 11:12:54.231487 CA3 delay=34 (3~65),Diff = 1 PI (4 cell)
3124 11:12:54.235242 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3125 11:12:54.238499 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3126 11:12:54.238601
3127 11:12:54.241656 CA PerBit enable=1, Macro0, CA PI delay=33
3128 11:12:54.241760
3129 11:12:54.244894 [CBTSetCACLKResult] CA Dly = 33
3130 11:12:54.244996 CS Dly: 6 (0~37)
3131 11:12:54.245096 ==
3132 11:12:54.248059 Dram Type= 6, Freq= 0, CH_1, rank 1
3133 11:12:54.255397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 11:12:54.255479 ==
3135 11:12:54.258596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3136 11:12:54.265047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3137 11:12:54.273725 [CA 0] Center 38 (8~68) winsize 61
3138 11:12:54.277340 [CA 1] Center 38 (8~68) winsize 61
3139 11:12:54.280240 [CA 2] Center 35 (5~65) winsize 61
3140 11:12:54.284098 [CA 3] Center 34 (4~65) winsize 62
3141 11:12:54.287294 [CA 4] Center 34 (4~65) winsize 62
3142 11:12:54.290666 [CA 5] Center 33 (3~63) winsize 61
3143 11:12:54.290751
3144 11:12:54.293650 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3145 11:12:54.293761
3146 11:12:54.296960 [CATrainingPosCal] consider 2 rank data
3147 11:12:54.300866 u2DelayCellTimex100 = 270/100 ps
3148 11:12:54.304097 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3149 11:12:54.307264 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3150 11:12:54.313805 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3151 11:12:54.317152 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3152 11:12:54.320493 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3153 11:12:54.323595 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3154 11:12:54.323675
3155 11:12:54.327135 CA PerBit enable=1, Macro0, CA PI delay=33
3156 11:12:54.327251
3157 11:12:54.330491 [CBTSetCACLKResult] CA Dly = 33
3158 11:12:54.330578 CS Dly: 7 (0~40)
3159 11:12:54.330644
3160 11:12:54.333625 ----->DramcWriteLeveling(PI) begin...
3161 11:12:54.336835 ==
3162 11:12:54.340581 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 11:12:54.343748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 11:12:54.343827 ==
3165 11:12:54.347008 Write leveling (Byte 0): 25 => 25
3166 11:12:54.350442 Write leveling (Byte 1): 29 => 29
3167 11:12:54.353484 DramcWriteLeveling(PI) end<-----
3168 11:12:54.353589
3169 11:12:54.353684 ==
3170 11:12:54.357399 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 11:12:54.360719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 11:12:54.360830 ==
3173 11:12:54.363955 [Gating] SW mode calibration
3174 11:12:54.370950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3175 11:12:54.373675 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3176 11:12:54.380437 0 15 0 | B1->B0 | 2828 2323 | 1 0 | (1 1) (0 0)
3177 11:12:54.383704 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 11:12:54.387229 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 11:12:54.394051 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 11:12:54.397241 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 11:12:54.400494 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 11:12:54.406980 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 11:12:54.410256 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3184 11:12:54.414225 1 0 0 | B1->B0 | 2323 2d2d | 0 1 | (1 0) (0 0)
3185 11:12:54.420726 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 11:12:54.424078 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 11:12:54.427233 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 11:12:54.433946 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 11:12:54.437177 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 11:12:54.440951 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 11:12:54.444055 1 0 28 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
3192 11:12:54.450469 1 1 0 | B1->B0 | 3f3f 3030 | 0 0 | (0 0) (1 1)
3193 11:12:54.454323 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 11:12:54.457596 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 11:12:54.464258 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 11:12:54.467480 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 11:12:54.470575 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 11:12:54.477732 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 11:12:54.480774 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 11:12:54.484396 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3201 11:12:54.490815 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 11:12:54.493915 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 11:12:54.497859 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 11:12:54.504096 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 11:12:54.507371 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 11:12:54.510556 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 11:12:54.517309 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 11:12:54.521162 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 11:12:54.524466 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 11:12:54.530880 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:12:54.534536 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:12:54.537729 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:12:54.541088 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:12:54.547448 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:12:54.551069 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3216 11:12:54.554315 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 11:12:54.557637 Total UI for P1: 0, mck2ui 16
3218 11:12:54.561017 best dqsien dly found for B0: ( 1, 3, 28)
3219 11:12:54.564197 Total UI for P1: 0, mck2ui 16
3220 11:12:54.567590 best dqsien dly found for B1: ( 1, 3, 30)
3221 11:12:54.570734 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3222 11:12:54.574793 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3223 11:12:54.574902
3224 11:12:54.581305 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3225 11:12:54.584227 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3226 11:12:54.584338 [Gating] SW calibration Done
3227 11:12:54.587356 ==
3228 11:12:54.591103 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 11:12:54.594340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 11:12:54.594427 ==
3231 11:12:54.594493 RX Vref Scan: 0
3232 11:12:54.594554
3233 11:12:54.597656 RX Vref 0 -> 0, step: 1
3234 11:12:54.597761
3235 11:12:54.600704 RX Delay -40 -> 252, step: 8
3236 11:12:54.604400 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3237 11:12:54.607530 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3238 11:12:54.610739 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3239 11:12:54.617897 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3240 11:12:54.621149 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3241 11:12:54.624424 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3242 11:12:54.627934 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3243 11:12:54.630943 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3244 11:12:54.637453 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3245 11:12:54.641193 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3246 11:12:54.644268 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3247 11:12:54.647497 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3248 11:12:54.650708 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3249 11:12:54.657126 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3250 11:12:54.661109 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3251 11:12:54.664333 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3252 11:12:54.664436 ==
3253 11:12:54.667501 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 11:12:54.670601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 11:12:54.670705 ==
3256 11:12:54.673933 DQS Delay:
3257 11:12:54.674008 DQS0 = 0, DQS1 = 0
3258 11:12:54.677919 DQM Delay:
3259 11:12:54.678034 DQM0 = 115, DQM1 = 108
3260 11:12:54.680507 DQ Delay:
3261 11:12:54.684424 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3262 11:12:54.687738 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =111
3263 11:12:54.690855 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3264 11:12:54.693903 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3265 11:12:54.694008
3266 11:12:54.694103
3267 11:12:54.694193 ==
3268 11:12:54.697543 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 11:12:54.700634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 11:12:54.700737 ==
3271 11:12:54.700828
3272 11:12:54.700931
3273 11:12:54.704143 TX Vref Scan disable
3274 11:12:54.707125 == TX Byte 0 ==
3275 11:12:54.710780 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3276 11:12:54.713866 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3277 11:12:54.717168 == TX Byte 1 ==
3278 11:12:54.720406 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3279 11:12:54.724283 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3280 11:12:54.724368 ==
3281 11:12:54.727089 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 11:12:54.730777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 11:12:54.734057 ==
3284 11:12:54.744343 TX Vref=22, minBit 0, minWin=25, winSum=414
3285 11:12:54.747326 TX Vref=24, minBit 1, minWin=26, winSum=417
3286 11:12:54.750515 TX Vref=26, minBit 0, minWin=26, winSum=420
3287 11:12:54.753853 TX Vref=28, minBit 0, minWin=26, winSum=424
3288 11:12:54.757651 TX Vref=30, minBit 0, minWin=26, winSum=428
3289 11:12:54.763740 TX Vref=32, minBit 15, minWin=25, winSum=424
3290 11:12:54.767626 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
3291 11:12:54.767711
3292 11:12:54.770849 Final TX Range 1 Vref 30
3293 11:12:54.770963
3294 11:12:54.771068 ==
3295 11:12:54.774115 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 11:12:54.777376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 11:12:54.777477 ==
3298 11:12:54.780533
3299 11:12:54.780608
3300 11:12:54.780674 TX Vref Scan disable
3301 11:12:54.783705 == TX Byte 0 ==
3302 11:12:54.787618 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3303 11:12:54.790729 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3304 11:12:54.793888 == TX Byte 1 ==
3305 11:12:54.796966 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3306 11:12:54.800763 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3307 11:12:54.803895
3308 11:12:54.803995 [DATLAT]
3309 11:12:54.804091 Freq=1200, CH1 RK0
3310 11:12:54.804184
3311 11:12:54.807529 DATLAT Default: 0xd
3312 11:12:54.807632 0, 0xFFFF, sum = 0
3313 11:12:54.810700 1, 0xFFFF, sum = 0
3314 11:12:54.810801 2, 0xFFFF, sum = 0
3315 11:12:54.813779 3, 0xFFFF, sum = 0
3316 11:12:54.816805 4, 0xFFFF, sum = 0
3317 11:12:54.816890 5, 0xFFFF, sum = 0
3318 11:12:54.820490 6, 0xFFFF, sum = 0
3319 11:12:54.820578 7, 0xFFFF, sum = 0
3320 11:12:54.823766 8, 0xFFFF, sum = 0
3321 11:12:54.823851 9, 0xFFFF, sum = 0
3322 11:12:54.827089 10, 0xFFFF, sum = 0
3323 11:12:54.827174 11, 0xFFFF, sum = 0
3324 11:12:54.830368 12, 0x0, sum = 1
3325 11:12:54.830452 13, 0x0, sum = 2
3326 11:12:54.833736 14, 0x0, sum = 3
3327 11:12:54.833827 15, 0x0, sum = 4
3328 11:12:54.836885 best_step = 13
3329 11:12:54.836995
3330 11:12:54.837089 ==
3331 11:12:54.840280 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 11:12:54.844179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 11:12:54.844257 ==
3334 11:12:54.844321 RX Vref Scan: 1
3335 11:12:54.844381
3336 11:12:54.847321 Set Vref Range= 32 -> 127
3337 11:12:54.847421
3338 11:12:54.850319 RX Vref 32 -> 127, step: 1
3339 11:12:54.850394
3340 11:12:54.853967 RX Delay -21 -> 252, step: 4
3341 11:12:54.854044
3342 11:12:54.857119 Set Vref, RX VrefLevel [Byte0]: 32
3343 11:12:54.860342 [Byte1]: 32
3344 11:12:54.860419
3345 11:12:54.863476 Set Vref, RX VrefLevel [Byte0]: 33
3346 11:12:54.866608 [Byte1]: 33
3347 11:12:54.870594
3348 11:12:54.870694 Set Vref, RX VrefLevel [Byte0]: 34
3349 11:12:54.874145 [Byte1]: 34
3350 11:12:54.878525
3351 11:12:54.878602 Set Vref, RX VrefLevel [Byte0]: 35
3352 11:12:54.881713 [Byte1]: 35
3353 11:12:54.885945
3354 11:12:54.886019 Set Vref, RX VrefLevel [Byte0]: 36
3355 11:12:54.889783 [Byte1]: 36
3356 11:12:54.894335
3357 11:12:54.894416 Set Vref, RX VrefLevel [Byte0]: 37
3358 11:12:54.897477 [Byte1]: 37
3359 11:12:54.902039
3360 11:12:54.902120 Set Vref, RX VrefLevel [Byte0]: 38
3361 11:12:54.905338 [Byte1]: 38
3362 11:12:54.909837
3363 11:12:54.909918 Set Vref, RX VrefLevel [Byte0]: 39
3364 11:12:54.913534 [Byte1]: 39
3365 11:12:54.917741
3366 11:12:54.917822 Set Vref, RX VrefLevel [Byte0]: 40
3367 11:12:54.921278 [Byte1]: 40
3368 11:12:54.925706
3369 11:12:54.925815 Set Vref, RX VrefLevel [Byte0]: 41
3370 11:12:54.929447 [Byte1]: 41
3371 11:12:54.933883
3372 11:12:54.933964 Set Vref, RX VrefLevel [Byte0]: 42
3373 11:12:54.937146 [Byte1]: 42
3374 11:12:54.941675
3375 11:12:54.941763 Set Vref, RX VrefLevel [Byte0]: 43
3376 11:12:54.944872 [Byte1]: 43
3377 11:12:54.949406
3378 11:12:54.949489 Set Vref, RX VrefLevel [Byte0]: 44
3379 11:12:54.952694 [Byte1]: 44
3380 11:12:54.957646
3381 11:12:54.957717 Set Vref, RX VrefLevel [Byte0]: 45
3382 11:12:54.960608 [Byte1]: 45
3383 11:12:54.965808
3384 11:12:54.965889 Set Vref, RX VrefLevel [Byte0]: 46
3385 11:12:54.968831 [Byte1]: 46
3386 11:12:54.973285
3387 11:12:54.973366 Set Vref, RX VrefLevel [Byte0]: 47
3388 11:12:54.976443 [Byte1]: 47
3389 11:12:54.980944
3390 11:12:54.981026 Set Vref, RX VrefLevel [Byte0]: 48
3391 11:12:54.984891 [Byte1]: 48
3392 11:12:54.989333
3393 11:12:54.989405 Set Vref, RX VrefLevel [Byte0]: 49
3394 11:12:54.992635 [Byte1]: 49
3395 11:12:54.997248
3396 11:12:54.997332 Set Vref, RX VrefLevel [Byte0]: 50
3397 11:12:55.000383 [Byte1]: 50
3398 11:12:55.004917
3399 11:12:55.005001 Set Vref, RX VrefLevel [Byte0]: 51
3400 11:12:55.008184 [Byte1]: 51
3401 11:12:55.012784
3402 11:12:55.016447 Set Vref, RX VrefLevel [Byte0]: 52
3403 11:12:55.016531 [Byte1]: 52
3404 11:12:55.020833
3405 11:12:55.020916 Set Vref, RX VrefLevel [Byte0]: 53
3406 11:12:55.024508 [Byte1]: 53
3407 11:12:55.028736
3408 11:12:55.028820 Set Vref, RX VrefLevel [Byte0]: 54
3409 11:12:55.032355 [Byte1]: 54
3410 11:12:55.036940
3411 11:12:55.037023 Set Vref, RX VrefLevel [Byte0]: 55
3412 11:12:55.040241 [Byte1]: 55
3413 11:12:55.044679
3414 11:12:55.044762 Set Vref, RX VrefLevel [Byte0]: 56
3415 11:12:55.048026 [Byte1]: 56
3416 11:12:55.052534
3417 11:12:55.052617 Set Vref, RX VrefLevel [Byte0]: 57
3418 11:12:55.055676 [Byte1]: 57
3419 11:12:55.060753
3420 11:12:55.060837 Set Vref, RX VrefLevel [Byte0]: 58
3421 11:12:55.063755 [Byte1]: 58
3422 11:12:55.068334
3423 11:12:55.068418 Set Vref, RX VrefLevel [Byte0]: 59
3424 11:12:55.071611 [Byte1]: 59
3425 11:12:55.075952
3426 11:12:55.076063 Set Vref, RX VrefLevel [Byte0]: 60
3427 11:12:55.082376 [Byte1]: 60
3428 11:12:55.082461
3429 11:12:55.086181 Set Vref, RX VrefLevel [Byte0]: 61
3430 11:12:55.089448 [Byte1]: 61
3431 11:12:55.089533
3432 11:12:55.092674 Set Vref, RX VrefLevel [Byte0]: 62
3433 11:12:55.095845 [Byte1]: 62
3434 11:12:55.100226
3435 11:12:55.100310 Set Vref, RX VrefLevel [Byte0]: 63
3436 11:12:55.103470 [Byte1]: 63
3437 11:12:55.107883
3438 11:12:55.107967 Set Vref, RX VrefLevel [Byte0]: 64
3439 11:12:55.111049 [Byte1]: 64
3440 11:12:55.115920
3441 11:12:55.116004 Set Vref, RX VrefLevel [Byte0]: 65
3442 11:12:55.119247 [Byte1]: 65
3443 11:12:55.124107
3444 11:12:55.124215 Set Vref, RX VrefLevel [Byte0]: 66
3445 11:12:55.127169 [Byte1]: 66
3446 11:12:55.131445
3447 11:12:55.131526 Set Vref, RX VrefLevel [Byte0]: 67
3448 11:12:55.135291 [Byte1]: 67
3449 11:12:55.140028
3450 11:12:55.140104 Set Vref, RX VrefLevel [Byte0]: 68
3451 11:12:55.143231 [Byte1]: 68
3452 11:12:55.147829
3453 11:12:55.147932 Set Vref, RX VrefLevel [Byte0]: 69
3454 11:12:55.151011 [Byte1]: 69
3455 11:12:55.155549
3456 11:12:55.155653 Set Vref, RX VrefLevel [Byte0]: 70
3457 11:12:55.158905 [Byte1]: 70
3458 11:12:55.163440
3459 11:12:55.163523 Set Vref, RX VrefLevel [Byte0]: 71
3460 11:12:55.166576 [Byte1]: 71
3461 11:12:55.171368
3462 11:12:55.171483 Set Vref, RX VrefLevel [Byte0]: 72
3463 11:12:55.174772 [Byte1]: 72
3464 11:12:55.179201
3465 11:12:55.182221 Final RX Vref Byte 0 = 59 to rank0
3466 11:12:55.182321 Final RX Vref Byte 1 = 52 to rank0
3467 11:12:55.186121 Final RX Vref Byte 0 = 59 to rank1
3468 11:12:55.189275 Final RX Vref Byte 1 = 52 to rank1==
3469 11:12:55.192456 Dram Type= 6, Freq= 0, CH_1, rank 0
3470 11:12:55.199437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 11:12:55.199516 ==
3472 11:12:55.199618 DQS Delay:
3473 11:12:55.199703 DQS0 = 0, DQS1 = 0
3474 11:12:55.202747 DQM Delay:
3475 11:12:55.202843 DQM0 = 116, DQM1 = 109
3476 11:12:55.205884 DQ Delay:
3477 11:12:55.209023 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3478 11:12:55.212317 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =112
3479 11:12:55.215650 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3480 11:12:55.218977 DQ12 =116, DQ13 =118, DQ14 =116, DQ15 =114
3481 11:12:55.219077
3482 11:12:55.219167
3483 11:12:55.225711 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe4, (MSB)MR19= 0x303, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3484 11:12:55.229314 CH1 RK0: MR19=303, MR18=FFE4
3485 11:12:55.236007 CH1_RK0: MR19=0x303, MR18=0xFFE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3486 11:12:55.236090
3487 11:12:55.239159 ----->DramcWriteLeveling(PI) begin...
3488 11:12:55.239261 ==
3489 11:12:55.242317 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 11:12:55.246223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 11:12:55.249287 ==
3492 11:12:55.249387 Write leveling (Byte 0): 27 => 27
3493 11:12:55.252600 Write leveling (Byte 1): 30 => 30
3494 11:12:55.255791 DramcWriteLeveling(PI) end<-----
3495 11:12:55.255866
3496 11:12:55.255929 ==
3497 11:12:55.258994 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 11:12:55.265504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 11:12:55.265617 ==
3500 11:12:55.265714 [Gating] SW mode calibration
3501 11:12:55.275499 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3502 11:12:55.278848 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3503 11:12:55.285793 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3504 11:12:55.288938 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 11:12:55.292096 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 11:12:55.295998 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3507 11:12:55.302580 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 11:12:55.305857 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3509 11:12:55.309110 0 15 24 | B1->B0 | 3333 2b2b | 1 1 | (1 1) (1 0)
3510 11:12:55.315533 0 15 28 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
3511 11:12:55.318878 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 11:12:55.322151 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 11:12:55.329291 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 11:12:55.332686 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 11:12:55.335583 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 11:12:55.342424 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3517 11:12:55.345505 1 0 24 | B1->B0 | 2525 4242 | 0 0 | (0 0) (0 0)
3518 11:12:55.349562 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3519 11:12:55.355780 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 11:12:55.358943 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 11:12:55.362132 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 11:12:55.369319 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 11:12:55.372499 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 11:12:55.375682 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3525 11:12:55.382051 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3526 11:12:55.385876 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3527 11:12:55.389072 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 11:12:55.395239 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 11:12:55.399063 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 11:12:55.402258 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 11:12:55.405502 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 11:12:55.411991 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 11:12:55.415188 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 11:12:55.418420 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 11:12:55.425586 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 11:12:55.428788 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 11:12:55.432073 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 11:12:55.438625 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 11:12:55.442518 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:12:55.445492 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 11:12:55.452117 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3542 11:12:55.455268 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3543 11:12:55.459115 Total UI for P1: 0, mck2ui 16
3544 11:12:55.462144 best dqsien dly found for B0: ( 1, 3, 24)
3545 11:12:55.465152 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 11:12:55.468982 Total UI for P1: 0, mck2ui 16
3547 11:12:55.472150 best dqsien dly found for B1: ( 1, 3, 28)
3548 11:12:55.475318 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3549 11:12:55.478631 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3550 11:12:55.478707
3551 11:12:55.485484 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3552 11:12:55.488593 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3553 11:12:55.488673 [Gating] SW calibration Done
3554 11:12:55.491722 ==
3555 11:12:55.495577 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 11:12:55.499036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 11:12:55.499155 ==
3558 11:12:55.499221 RX Vref Scan: 0
3559 11:12:55.499283
3560 11:12:55.502077 RX Vref 0 -> 0, step: 1
3561 11:12:55.502174
3562 11:12:55.505256 RX Delay -40 -> 252, step: 8
3563 11:12:55.508788 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3564 11:12:55.511878 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3565 11:12:55.515001 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3566 11:12:55.522185 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3567 11:12:55.525563 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3568 11:12:55.528799 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3569 11:12:55.532073 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3570 11:12:55.535262 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3571 11:12:55.541626 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3572 11:12:55.545554 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3573 11:12:55.548774 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3574 11:12:55.551873 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3575 11:12:55.555280 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3576 11:12:55.561806 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3577 11:12:55.565363 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3578 11:12:55.568266 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3579 11:12:55.568351 ==
3580 11:12:55.571758 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 11:12:55.575534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 11:12:55.578451 ==
3583 11:12:55.578552 DQS Delay:
3584 11:12:55.578630 DQS0 = 0, DQS1 = 0
3585 11:12:55.581574 DQM Delay:
3586 11:12:55.581657 DQM0 = 112, DQM1 = 110
3587 11:12:55.585278 DQ Delay:
3588 11:12:55.588348 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3589 11:12:55.591515 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3590 11:12:55.595343 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3591 11:12:55.598619 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3592 11:12:55.598704
3593 11:12:55.598771
3594 11:12:55.598835 ==
3595 11:12:55.601695 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 11:12:55.604905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 11:12:55.604990 ==
3598 11:12:55.605057
3599 11:12:55.605116
3600 11:12:55.608207 TX Vref Scan disable
3601 11:12:55.611524 == TX Byte 0 ==
3602 11:12:55.614698 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3603 11:12:55.618550 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3604 11:12:55.621784 == TX Byte 1 ==
3605 11:12:55.624981 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3606 11:12:55.628377 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3607 11:12:55.628461 ==
3608 11:12:55.631643 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 11:12:55.638173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 11:12:55.638262 ==
3611 11:12:55.648554 TX Vref=22, minBit 3, minWin=25, winSum=416
3612 11:12:55.651855 TX Vref=24, minBit 7, minWin=25, winSum=422
3613 11:12:55.654803 TX Vref=26, minBit 15, minWin=25, winSum=429
3614 11:12:55.658795 TX Vref=28, minBit 2, minWin=26, winSum=433
3615 11:12:55.661831 TX Vref=30, minBit 2, minWin=26, winSum=435
3616 11:12:55.668502 TX Vref=32, minBit 2, minWin=26, winSum=435
3617 11:12:55.671728 [TxChooseVref] Worse bit 2, Min win 26, Win sum 435, Final Vref 30
3618 11:12:55.671814
3619 11:12:55.675174 Final TX Range 1 Vref 30
3620 11:12:55.675258
3621 11:12:55.675324 ==
3622 11:12:55.678378 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 11:12:55.682097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 11:12:55.682192 ==
3625 11:12:55.684889
3626 11:12:55.684972
3627 11:12:55.685076 TX Vref Scan disable
3628 11:12:55.688809 == TX Byte 0 ==
3629 11:12:55.691985 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3630 11:12:55.694948 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3631 11:12:55.698737 == TX Byte 1 ==
3632 11:12:55.701396 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3633 11:12:55.705236 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3634 11:12:55.708417
3635 11:12:55.708492 [DATLAT]
3636 11:12:55.708563 Freq=1200, CH1 RK1
3637 11:12:55.708625
3638 11:12:55.711591 DATLAT Default: 0xd
3639 11:12:55.711684 0, 0xFFFF, sum = 0
3640 11:12:55.714775 1, 0xFFFF, sum = 0
3641 11:12:55.714850 2, 0xFFFF, sum = 0
3642 11:12:55.718761 3, 0xFFFF, sum = 0
3643 11:12:55.718839 4, 0xFFFF, sum = 0
3644 11:12:55.721942 5, 0xFFFF, sum = 0
3645 11:12:55.725395 6, 0xFFFF, sum = 0
3646 11:12:55.725480 7, 0xFFFF, sum = 0
3647 11:12:55.728494 8, 0xFFFF, sum = 0
3648 11:12:55.728623 9, 0xFFFF, sum = 0
3649 11:12:55.731864 10, 0xFFFF, sum = 0
3650 11:12:55.731940 11, 0xFFFF, sum = 0
3651 11:12:55.735090 12, 0x0, sum = 1
3652 11:12:55.735173 13, 0x0, sum = 2
3653 11:12:55.738219 14, 0x0, sum = 3
3654 11:12:55.738293 15, 0x0, sum = 4
3655 11:12:55.738363 best_step = 13
3656 11:12:55.741513
3657 11:12:55.741593 ==
3658 11:12:55.744703 Dram Type= 6, Freq= 0, CH_1, rank 1
3659 11:12:55.748488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3660 11:12:55.748562 ==
3661 11:12:55.748633 RX Vref Scan: 0
3662 11:12:55.748700
3663 11:12:55.751878 RX Vref 0 -> 0, step: 1
3664 11:12:55.751995
3665 11:12:55.755142 RX Delay -21 -> 252, step: 4
3666 11:12:55.758415 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3667 11:12:55.764681 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3668 11:12:55.768518 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3669 11:12:55.771691 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3670 11:12:55.775087 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3671 11:12:55.778079 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3672 11:12:55.785009 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3673 11:12:55.787950 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3674 11:12:55.791667 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3675 11:12:55.794662 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3676 11:12:55.798140 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3677 11:12:55.804658 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3678 11:12:55.808272 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3679 11:12:55.811303 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3680 11:12:55.814459 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3681 11:12:55.817770 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3682 11:12:55.821531 ==
3683 11:12:55.821608 Dram Type= 6, Freq= 0, CH_1, rank 1
3684 11:12:55.828146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3685 11:12:55.828234 ==
3686 11:12:55.828310 DQS Delay:
3687 11:12:55.831388 DQS0 = 0, DQS1 = 0
3688 11:12:55.831464 DQM Delay:
3689 11:12:55.834753 DQM0 = 113, DQM1 = 109
3690 11:12:55.834841 DQ Delay:
3691 11:12:55.837962 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =112
3692 11:12:55.841348 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =110
3693 11:12:55.844656 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3694 11:12:55.847926 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3695 11:12:55.848012
3696 11:12:55.848093
3697 11:12:55.857585 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb03, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 412 ps
3698 11:12:55.857668 CH1 RK1: MR19=304, MR18=FB03
3699 11:12:55.864097 CH1_RK1: MR19=0x304, MR18=0xFB03, DQSOSC=408, MR23=63, INC=39, DEC=26
3700 11:12:55.867352 [RxdqsGatingPostProcess] freq 1200
3701 11:12:55.874147 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3702 11:12:55.877504 best DQS0 dly(2T, 0.5T) = (0, 11)
3703 11:12:55.880777 best DQS1 dly(2T, 0.5T) = (0, 11)
3704 11:12:55.883936 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3705 11:12:55.887512 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3706 11:12:55.890887 best DQS0 dly(2T, 0.5T) = (0, 11)
3707 11:12:55.893928 best DQS1 dly(2T, 0.5T) = (0, 11)
3708 11:12:55.897456 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3709 11:12:55.900542 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3710 11:12:55.900626 Pre-setting of DQS Precalculation
3711 11:12:55.907599 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3712 11:12:55.914143 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3713 11:12:55.920803 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3714 11:12:55.920884
3715 11:12:55.920957
3716 11:12:55.923676 [Calibration Summary] 2400 Mbps
3717 11:12:55.927355 CH 0, Rank 0
3718 11:12:55.927469 SW Impedance : PASS
3719 11:12:55.930705 DUTY Scan : NO K
3720 11:12:55.933866 ZQ Calibration : PASS
3721 11:12:55.933943 Jitter Meter : NO K
3722 11:12:55.937160 CBT Training : PASS
3723 11:12:55.940563 Write leveling : PASS
3724 11:12:55.940643 RX DQS gating : PASS
3725 11:12:55.943906 RX DQ/DQS(RDDQC) : PASS
3726 11:12:55.947281 TX DQ/DQS : PASS
3727 11:12:55.947424 RX DATLAT : PASS
3728 11:12:55.950594 RX DQ/DQS(Engine): PASS
3729 11:12:55.950671 TX OE : NO K
3730 11:12:55.953781 All Pass.
3731 11:12:55.953869
3732 11:12:55.953934 CH 0, Rank 1
3733 11:12:55.957071 SW Impedance : PASS
3734 11:12:55.957146 DUTY Scan : NO K
3735 11:12:55.960184 ZQ Calibration : PASS
3736 11:12:55.963574 Jitter Meter : NO K
3737 11:12:55.963679 CBT Training : PASS
3738 11:12:55.966877 Write leveling : PASS
3739 11:12:55.970074 RX DQS gating : PASS
3740 11:12:55.970151 RX DQ/DQS(RDDQC) : PASS
3741 11:12:55.973309 TX DQ/DQS : PASS
3742 11:12:55.977125 RX DATLAT : PASS
3743 11:12:55.977209 RX DQ/DQS(Engine): PASS
3744 11:12:55.980273 TX OE : NO K
3745 11:12:55.980381 All Pass.
3746 11:12:55.980474
3747 11:12:55.983543 CH 1, Rank 0
3748 11:12:55.983627 SW Impedance : PASS
3749 11:12:55.986746 DUTY Scan : NO K
3750 11:12:55.989933 ZQ Calibration : PASS
3751 11:12:55.990019 Jitter Meter : NO K
3752 11:12:55.993697 CBT Training : PASS
3753 11:12:55.996981 Write leveling : PASS
3754 11:12:55.997066 RX DQS gating : PASS
3755 11:12:56.000260 RX DQ/DQS(RDDQC) : PASS
3756 11:12:56.003472 TX DQ/DQS : PASS
3757 11:12:56.003560 RX DATLAT : PASS
3758 11:12:56.007063 RX DQ/DQS(Engine): PASS
3759 11:12:56.007148 TX OE : NO K
3760 11:12:56.010246 All Pass.
3761 11:12:56.010331
3762 11:12:56.010415 CH 1, Rank 1
3763 11:12:56.013063 SW Impedance : PASS
3764 11:12:56.013148 DUTY Scan : NO K
3765 11:12:56.016666 ZQ Calibration : PASS
3766 11:12:56.019755 Jitter Meter : NO K
3767 11:12:56.019839 CBT Training : PASS
3768 11:12:56.023498 Write leveling : PASS
3769 11:12:56.026457 RX DQS gating : PASS
3770 11:12:56.026550 RX DQ/DQS(RDDQC) : PASS
3771 11:12:56.029694 TX DQ/DQS : PASS
3772 11:12:56.033097 RX DATLAT : PASS
3773 11:12:56.033175 RX DQ/DQS(Engine): PASS
3774 11:12:56.036369 TX OE : NO K
3775 11:12:56.036448 All Pass.
3776 11:12:56.036528
3777 11:12:56.039636 DramC Write-DBI off
3778 11:12:56.042910 PER_BANK_REFRESH: Hybrid Mode
3779 11:12:56.042989 TX_TRACKING: ON
3780 11:12:56.052868 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3781 11:12:56.056188 [FAST_K] Save calibration result to emmc
3782 11:12:56.059320 dramc_set_vcore_voltage set vcore to 650000
3783 11:12:56.062654 Read voltage for 600, 5
3784 11:12:56.062756 Vio18 = 0
3785 11:12:56.062857 Vcore = 650000
3786 11:12:56.066517 Vdram = 0
3787 11:12:56.066607 Vddq = 0
3788 11:12:56.066691 Vmddr = 0
3789 11:12:56.073126 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3790 11:12:56.076380 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3791 11:12:56.079524 MEM_TYPE=3, freq_sel=19
3792 11:12:56.082636 sv_algorithm_assistance_LP4_1600
3793 11:12:56.085881 ============ PULL DRAM RESETB DOWN ============
3794 11:12:56.093052 ========== PULL DRAM RESETB DOWN end =========
3795 11:12:56.096121 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3796 11:12:56.099148 ===================================
3797 11:12:56.102395 LPDDR4 DRAM CONFIGURATION
3798 11:12:56.106353 ===================================
3799 11:12:56.106434 EX_ROW_EN[0] = 0x0
3800 11:12:56.109459 EX_ROW_EN[1] = 0x0
3801 11:12:56.109534 LP4Y_EN = 0x0
3802 11:12:56.112538 WORK_FSP = 0x0
3803 11:12:56.112628 WL = 0x2
3804 11:12:56.116183 RL = 0x2
3805 11:12:56.116255 BL = 0x2
3806 11:12:56.119358 RPST = 0x0
3807 11:12:56.119444 RD_PRE = 0x0
3808 11:12:56.122913 WR_PRE = 0x1
3809 11:12:56.122999 WR_PST = 0x0
3810 11:12:56.125981 DBI_WR = 0x0
3811 11:12:56.126066 DBI_RD = 0x0
3812 11:12:56.129660 OTF = 0x1
3813 11:12:56.132499 ===================================
3814 11:12:56.136128 ===================================
3815 11:12:56.136246 ANA top config
3816 11:12:56.139199 ===================================
3817 11:12:56.142590 DLL_ASYNC_EN = 0
3818 11:12:56.145934 ALL_SLAVE_EN = 1
3819 11:12:56.149341 NEW_RANK_MODE = 1
3820 11:12:56.149428 DLL_IDLE_MODE = 1
3821 11:12:56.153160 LP45_APHY_COMB_EN = 1
3822 11:12:56.156576 TX_ODT_DIS = 1
3823 11:12:56.159580 NEW_8X_MODE = 1
3824 11:12:56.162815 ===================================
3825 11:12:56.165954 ===================================
3826 11:12:56.169179 data_rate = 1200
3827 11:12:56.169264 CKR = 1
3828 11:12:56.172453 DQ_P2S_RATIO = 8
3829 11:12:56.176326 ===================================
3830 11:12:56.179580 CA_P2S_RATIO = 8
3831 11:12:56.182856 DQ_CA_OPEN = 0
3832 11:12:56.185941 DQ_SEMI_OPEN = 0
3833 11:12:56.189197 CA_SEMI_OPEN = 0
3834 11:12:56.189283 CA_FULL_RATE = 0
3835 11:12:56.192486 DQ_CKDIV4_EN = 1
3836 11:12:56.195665 CA_CKDIV4_EN = 1
3837 11:12:56.198896 CA_PREDIV_EN = 0
3838 11:12:56.202641 PH8_DLY = 0
3839 11:12:56.205793 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3840 11:12:56.205890 DQ_AAMCK_DIV = 4
3841 11:12:56.208985 CA_AAMCK_DIV = 4
3842 11:12:56.212208 CA_ADMCK_DIV = 4
3843 11:12:56.215592 DQ_TRACK_CA_EN = 0
3844 11:12:56.218935 CA_PICK = 600
3845 11:12:56.222655 CA_MCKIO = 600
3846 11:12:56.225660 MCKIO_SEMI = 0
3847 11:12:56.225744 PLL_FREQ = 2288
3848 11:12:56.229175 DQ_UI_PI_RATIO = 32
3849 11:12:56.232274 CA_UI_PI_RATIO = 0
3850 11:12:56.235527 ===================================
3851 11:12:56.239147 ===================================
3852 11:12:56.242236 memory_type:LPDDR4
3853 11:12:56.242319 GP_NUM : 10
3854 11:12:56.245932 SRAM_EN : 1
3855 11:12:56.249276 MD32_EN : 0
3856 11:12:56.252617 ===================================
3857 11:12:56.252702 [ANA_INIT] >>>>>>>>>>>>>>
3858 11:12:56.255895 <<<<<< [CONFIGURE PHASE]: ANA_TX
3859 11:12:56.259032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3860 11:12:56.262233 ===================================
3861 11:12:56.265551 data_rate = 1200,PCW = 0X5800
3862 11:12:56.268850 ===================================
3863 11:12:56.272011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3864 11:12:56.279058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3865 11:12:56.282278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3866 11:12:56.288714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3867 11:12:56.291918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3868 11:12:56.295739 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3869 11:12:56.295832 [ANA_INIT] flow start
3870 11:12:56.298967 [ANA_INIT] PLL >>>>>>>>
3871 11:12:56.302189 [ANA_INIT] PLL <<<<<<<<
3872 11:12:56.305347 [ANA_INIT] MIDPI >>>>>>>>
3873 11:12:56.305433 [ANA_INIT] MIDPI <<<<<<<<
3874 11:12:56.308922 [ANA_INIT] DLL >>>>>>>>
3875 11:12:56.311983 [ANA_INIT] flow end
3876 11:12:56.315192 ============ LP4 DIFF to SE enter ============
3877 11:12:56.318674 ============ LP4 DIFF to SE exit ============
3878 11:12:56.321792 [ANA_INIT] <<<<<<<<<<<<<
3879 11:12:56.325708 [Flow] Enable top DCM control >>>>>
3880 11:12:56.328819 [Flow] Enable top DCM control <<<<<
3881 11:12:56.331857 Enable DLL master slave shuffle
3882 11:12:56.335542 ==============================================================
3883 11:12:56.338422 Gating Mode config
3884 11:12:56.342237 ==============================================================
3885 11:12:56.345130 Config description:
3886 11:12:56.355381 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3887 11:12:56.361930 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3888 11:12:56.365215 SELPH_MODE 0: By rank 1: By Phase
3889 11:12:56.371816 ==============================================================
3890 11:12:56.375172 GAT_TRACK_EN = 1
3891 11:12:56.378387 RX_GATING_MODE = 2
3892 11:12:56.381606 RX_GATING_TRACK_MODE = 2
3893 11:12:56.384794 SELPH_MODE = 1
3894 11:12:56.388027 PICG_EARLY_EN = 1
3895 11:12:56.391950 VALID_LAT_VALUE = 1
3896 11:12:56.395189 ==============================================================
3897 11:12:56.398424 Enter into Gating configuration >>>>
3898 11:12:56.401653 Exit from Gating configuration <<<<
3899 11:12:56.404907 Enter into DVFS_PRE_config >>>>>
3900 11:12:56.414859 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3901 11:12:56.417961 Exit from DVFS_PRE_config <<<<<
3902 11:12:56.421817 Enter into PICG configuration >>>>
3903 11:12:56.424942 Exit from PICG configuration <<<<
3904 11:12:56.428135 [RX_INPUT] configuration >>>>>
3905 11:12:56.431433 [RX_INPUT] configuration <<<<<
3906 11:12:56.438325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3907 11:12:56.441212 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3908 11:12:56.447998 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3909 11:12:56.454561 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3910 11:12:56.461540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3911 11:12:56.468207 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3912 11:12:56.471583 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3913 11:12:56.474928 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3914 11:12:56.478052 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3915 11:12:56.484661 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3916 11:12:56.487580 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3917 11:12:56.491086 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3918 11:12:56.494471 ===================================
3919 11:12:56.497541 LPDDR4 DRAM CONFIGURATION
3920 11:12:56.500626 ===================================
3921 11:12:56.500712 EX_ROW_EN[0] = 0x0
3922 11:12:56.504482 EX_ROW_EN[1] = 0x0
3923 11:12:56.507551 LP4Y_EN = 0x0
3924 11:12:56.507663 WORK_FSP = 0x0
3925 11:12:56.510912 WL = 0x2
3926 11:12:56.510998 RL = 0x2
3927 11:12:56.514441 BL = 0x2
3928 11:12:56.514526 RPST = 0x0
3929 11:12:56.517574 RD_PRE = 0x0
3930 11:12:56.517665 WR_PRE = 0x1
3931 11:12:56.521090 WR_PST = 0x0
3932 11:12:56.521175 DBI_WR = 0x0
3933 11:12:56.524014 DBI_RD = 0x0
3934 11:12:56.524132 OTF = 0x1
3935 11:12:56.527800 ===================================
3936 11:12:56.531030 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3937 11:12:56.537621 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3938 11:12:56.540906 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3939 11:12:56.544405 ===================================
3940 11:12:56.547369 LPDDR4 DRAM CONFIGURATION
3941 11:12:56.551008 ===================================
3942 11:12:56.551106 EX_ROW_EN[0] = 0x10
3943 11:12:56.554006 EX_ROW_EN[1] = 0x0
3944 11:12:56.554086 LP4Y_EN = 0x0
3945 11:12:56.557712 WORK_FSP = 0x0
3946 11:12:56.560906 WL = 0x2
3947 11:12:56.561031 RL = 0x2
3948 11:12:56.563980 BL = 0x2
3949 11:12:56.564062 RPST = 0x0
3950 11:12:56.567161 RD_PRE = 0x0
3951 11:12:56.567249 WR_PRE = 0x1
3952 11:12:56.570416 WR_PST = 0x0
3953 11:12:56.570507 DBI_WR = 0x0
3954 11:12:56.574336 DBI_RD = 0x0
3955 11:12:56.574411 OTF = 0x1
3956 11:12:56.577524 ===================================
3957 11:12:56.583940 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3958 11:12:56.587851 nWR fixed to 30
3959 11:12:56.591138 [ModeRegInit_LP4] CH0 RK0
3960 11:12:56.591217 [ModeRegInit_LP4] CH0 RK1
3961 11:12:56.594409 [ModeRegInit_LP4] CH1 RK0
3962 11:12:56.598237 [ModeRegInit_LP4] CH1 RK1
3963 11:12:56.598348 match AC timing 17
3964 11:12:56.604280 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3965 11:12:56.607599 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3966 11:12:56.610770 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3967 11:12:56.617995 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3968 11:12:56.621465 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3969 11:12:56.621546 ==
3970 11:12:56.624564 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 11:12:56.627391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 11:12:56.627485 ==
3973 11:12:56.634547 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3974 11:12:56.641087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3975 11:12:56.644241 [CA 0] Center 36 (6~66) winsize 61
3976 11:12:56.647729 [CA 1] Center 36 (6~66) winsize 61
3977 11:12:56.650681 [CA 2] Center 34 (4~65) winsize 62
3978 11:12:56.653914 [CA 3] Center 34 (4~65) winsize 62
3979 11:12:56.657739 [CA 4] Center 34 (4~64) winsize 61
3980 11:12:56.660645 [CA 5] Center 33 (3~64) winsize 62
3981 11:12:56.660722
3982 11:12:56.664303 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3983 11:12:56.664383
3984 11:12:56.667376 [CATrainingPosCal] consider 1 rank data
3985 11:12:56.670676 u2DelayCellTimex100 = 270/100 ps
3986 11:12:56.673840 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3987 11:12:56.677050 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3988 11:12:56.680381 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3989 11:12:56.684269 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3990 11:12:56.690712 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3991 11:12:56.694022 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3992 11:12:56.694130
3993 11:12:56.697321 CA PerBit enable=1, Macro0, CA PI delay=33
3994 11:12:56.697400
3995 11:12:56.700599 [CBTSetCACLKResult] CA Dly = 33
3996 11:12:56.700677 CS Dly: 4 (0~35)
3997 11:12:56.700753 ==
3998 11:12:56.703953 Dram Type= 6, Freq= 0, CH_0, rank 1
3999 11:12:56.710518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 11:12:56.710612 ==
4001 11:12:56.713568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4002 11:12:56.720071 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4003 11:12:56.723845 [CA 0] Center 36 (6~66) winsize 61
4004 11:12:56.727153 [CA 1] Center 36 (6~66) winsize 61
4005 11:12:56.730424 [CA 2] Center 34 (4~65) winsize 62
4006 11:12:56.733520 [CA 3] Center 34 (4~65) winsize 62
4007 11:12:56.736728 [CA 4] Center 33 (3~64) winsize 62
4008 11:12:56.739779 [CA 5] Center 33 (3~64) winsize 62
4009 11:12:56.739862
4010 11:12:56.743149 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4011 11:12:56.743224
4012 11:12:56.746956 [CATrainingPosCal] consider 2 rank data
4013 11:12:56.750172 u2DelayCellTimex100 = 270/100 ps
4014 11:12:56.753425 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4015 11:12:56.756649 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4016 11:12:56.763297 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4017 11:12:56.766162 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4018 11:12:56.769831 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4019 11:12:56.773521 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4020 11:12:56.773602
4021 11:12:56.776215 CA PerBit enable=1, Macro0, CA PI delay=33
4022 11:12:56.776293
4023 11:12:56.779344 [CBTSetCACLKResult] CA Dly = 33
4024 11:12:56.779449 CS Dly: 5 (0~37)
4025 11:12:56.783240
4026 11:12:56.786493 ----->DramcWriteLeveling(PI) begin...
4027 11:12:56.786573 ==
4028 11:12:56.789731 Dram Type= 6, Freq= 0, CH_0, rank 0
4029 11:12:56.792984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4030 11:12:56.793072 ==
4031 11:12:56.796235 Write leveling (Byte 0): 31 => 31
4032 11:12:56.799567 Write leveling (Byte 1): 30 => 30
4033 11:12:56.802801 DramcWriteLeveling(PI) end<-----
4034 11:12:56.802880
4035 11:12:56.802954 ==
4036 11:12:56.806070 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 11:12:56.809297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 11:12:56.809378 ==
4039 11:12:56.812924 [Gating] SW mode calibration
4040 11:12:56.819666 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4041 11:12:56.826154 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4042 11:12:56.829511 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 11:12:56.833119 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 11:12:56.836380 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4045 11:12:56.842776 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4046 11:12:56.846112 0 9 16 | B1->B0 | 3030 2c2c | 1 1 | (1 0) (1 0)
4047 11:12:56.849701 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4048 11:12:56.856094 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 11:12:56.859336 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 11:12:56.862641 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 11:12:56.869258 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 11:12:56.873032 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 11:12:56.876254 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 11:12:56.882630 0 10 16 | B1->B0 | 2f2f 3a3a | 0 0 | (0 0) (0 0)
4055 11:12:56.886097 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4056 11:12:56.889297 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 11:12:56.895987 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 11:12:56.899307 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 11:12:56.902569 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 11:12:56.908966 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 11:12:56.912280 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 11:12:56.915961 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4063 11:12:56.922018 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:12:56.925951 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 11:12:56.929093 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 11:12:56.935607 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 11:12:56.938920 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 11:12:56.942106 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 11:12:56.948566 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 11:12:56.951929 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 11:12:56.955814 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 11:12:56.962421 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 11:12:56.965607 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:12:56.968898 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:12:56.975664 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:12:56.978676 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:12:56.981809 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:12:56.988842 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4079 11:12:56.992363 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 11:12:56.995306 Total UI for P1: 0, mck2ui 16
4081 11:12:56.998474 best dqsien dly found for B0: ( 0, 13, 16)
4082 11:12:57.001996 Total UI for P1: 0, mck2ui 16
4083 11:12:57.005276 best dqsien dly found for B1: ( 0, 13, 16)
4084 11:12:57.008609 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4085 11:12:57.011863 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4086 11:12:57.011941
4087 11:12:57.015114 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4088 11:12:57.018910 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4089 11:12:57.022097 [Gating] SW calibration Done
4090 11:12:57.022178 ==
4091 11:12:57.025212 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 11:12:57.028794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 11:12:57.028876 ==
4094 11:12:57.031958 RX Vref Scan: 0
4095 11:12:57.032034
4096 11:12:57.035236 RX Vref 0 -> 0, step: 1
4097 11:12:57.035363
4098 11:12:57.035449 RX Delay -230 -> 252, step: 16
4099 11:12:57.042246 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4100 11:12:57.045435 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4101 11:12:57.048494 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4102 11:12:57.052321 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4103 11:12:57.058818 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4104 11:12:57.062009 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4105 11:12:57.065250 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4106 11:12:57.068683 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4107 11:12:57.071994 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4108 11:12:57.078441 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4109 11:12:57.082114 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4110 11:12:57.085415 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4111 11:12:57.088886 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4112 11:12:57.094902 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4113 11:12:57.098716 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4114 11:12:57.101771 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4115 11:12:57.101850 ==
4116 11:12:57.105490 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 11:12:57.108544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 11:12:57.111825 ==
4119 11:12:57.111913 DQS Delay:
4120 11:12:57.112036 DQS0 = 0, DQS1 = 0
4121 11:12:57.114991 DQM Delay:
4122 11:12:57.115107 DQM0 = 41, DQM1 = 32
4123 11:12:57.118285 DQ Delay:
4124 11:12:57.121802 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4125 11:12:57.121877 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4126 11:12:57.124957 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4127 11:12:57.131644 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4128 11:12:57.131743
4129 11:12:57.131823
4130 11:12:57.131915 ==
4131 11:12:57.134803 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 11:12:57.137848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 11:12:57.137933 ==
4134 11:12:57.138018
4135 11:12:57.138097
4136 11:12:57.141756 TX Vref Scan disable
4137 11:12:57.141857 == TX Byte 0 ==
4138 11:12:57.148263 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4139 11:12:57.151320 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4140 11:12:57.151413 == TX Byte 1 ==
4141 11:12:57.158247 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4142 11:12:57.161432 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4143 11:12:57.161517 ==
4144 11:12:57.164686 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 11:12:57.167905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 11:12:57.168003 ==
4147 11:12:57.168082
4148 11:12:57.168140
4149 11:12:57.171305 TX Vref Scan disable
4150 11:12:57.174507 == TX Byte 0 ==
4151 11:12:57.177758 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4152 11:12:57.181703 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4153 11:12:57.184732 == TX Byte 1 ==
4154 11:12:57.187841 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4155 11:12:57.194427 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4156 11:12:57.194516
4157 11:12:57.194601 [DATLAT]
4158 11:12:57.194700 Freq=600, CH0 RK0
4159 11:12:57.194798
4160 11:12:57.198356 DATLAT Default: 0x9
4161 11:12:57.198465 0, 0xFFFF, sum = 0
4162 11:12:57.201363 1, 0xFFFF, sum = 0
4163 11:12:57.201449 2, 0xFFFF, sum = 0
4164 11:12:57.204462 3, 0xFFFF, sum = 0
4165 11:12:57.204549 4, 0xFFFF, sum = 0
4166 11:12:57.208131 5, 0xFFFF, sum = 0
4167 11:12:57.211257 6, 0xFFFF, sum = 0
4168 11:12:57.211343 7, 0xFFFF, sum = 0
4169 11:12:57.211466 8, 0x0, sum = 1
4170 11:12:57.214344 9, 0x0, sum = 2
4171 11:12:57.214430 10, 0x0, sum = 3
4172 11:12:57.217563 11, 0x0, sum = 4
4173 11:12:57.217649 best_step = 9
4174 11:12:57.217732
4175 11:12:57.217811 ==
4176 11:12:57.221413 Dram Type= 6, Freq= 0, CH_0, rank 0
4177 11:12:57.227870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 11:12:57.227954 ==
4179 11:12:57.228054 RX Vref Scan: 1
4180 11:12:57.228147
4181 11:12:57.231294 RX Vref 0 -> 0, step: 1
4182 11:12:57.231419
4183 11:12:57.234289 RX Delay -195 -> 252, step: 8
4184 11:12:57.234390
4185 11:12:57.238054 Set Vref, RX VrefLevel [Byte0]: 55
4186 11:12:57.241120 [Byte1]: 50
4187 11:12:57.241204
4188 11:12:57.244542 Final RX Vref Byte 0 = 55 to rank0
4189 11:12:57.248020 Final RX Vref Byte 1 = 50 to rank0
4190 11:12:57.251049 Final RX Vref Byte 0 = 55 to rank1
4191 11:12:57.254797 Final RX Vref Byte 1 = 50 to rank1==
4192 11:12:57.257748 Dram Type= 6, Freq= 0, CH_0, rank 0
4193 11:12:57.261439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 11:12:57.261537 ==
4195 11:12:57.264471 DQS Delay:
4196 11:12:57.264555 DQS0 = 0, DQS1 = 0
4197 11:12:57.264638 DQM Delay:
4198 11:12:57.267833 DQM0 = 42, DQM1 = 33
4199 11:12:57.267918 DQ Delay:
4200 11:12:57.271168 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4201 11:12:57.274395 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4202 11:12:57.277692 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4203 11:12:57.280949 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4204 11:12:57.281042
4205 11:12:57.281143
4206 11:12:57.291119 [DQSOSCAuto] RK0, (LSB)MR18= 0x4120, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4207 11:12:57.294378 CH0 RK0: MR19=808, MR18=4120
4208 11:12:57.297471 CH0_RK0: MR19=0x808, MR18=0x4120, DQSOSC=397, MR23=63, INC=166, DEC=110
4209 11:12:57.297549
4210 11:12:57.304146 ----->DramcWriteLeveling(PI) begin...
4211 11:12:57.304233 ==
4212 11:12:57.308006 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 11:12:57.310917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 11:12:57.311027 ==
4215 11:12:57.314562 Write leveling (Byte 0): 33 => 33
4216 11:12:57.317387 Write leveling (Byte 1): 30 => 30
4217 11:12:57.320798 DramcWriteLeveling(PI) end<-----
4218 11:12:57.320882
4219 11:12:57.320948 ==
4220 11:12:57.324317 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 11:12:57.327547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 11:12:57.327632 ==
4223 11:12:57.330842 [Gating] SW mode calibration
4224 11:12:57.337548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4225 11:12:57.344222 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4226 11:12:57.347315 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 11:12:57.350569 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4228 11:12:57.357054 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4229 11:12:57.360435 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
4230 11:12:57.364244 0 9 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 1) (0 0)
4231 11:12:57.370399 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4232 11:12:57.373666 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 11:12:57.376784 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 11:12:57.384036 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 11:12:57.387346 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 11:12:57.390611 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 11:12:57.393715 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
4238 11:12:57.400067 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4239 11:12:57.403373 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 11:12:57.407308 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 11:12:57.413869 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 11:12:57.416871 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 11:12:57.420405 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 11:12:57.427108 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 11:12:57.429936 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4246 11:12:57.433606 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4247 11:12:57.440669 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4248 11:12:57.443761 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:12:57.446829 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:12:57.453945 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:12:57.457058 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:12:57.460237 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:12:57.466730 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:12:57.469881 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 11:12:57.473662 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 11:12:57.480050 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:12:57.483480 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:12:57.486783 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:12:57.493324 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:12:57.496722 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:12:57.499775 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4262 11:12:57.506798 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4263 11:12:57.506878 Total UI for P1: 0, mck2ui 16
4264 11:12:57.513413 best dqsien dly found for B0: ( 0, 13, 12)
4265 11:12:57.516642 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 11:12:57.519774 Total UI for P1: 0, mck2ui 16
4267 11:12:57.523191 best dqsien dly found for B1: ( 0, 13, 16)
4268 11:12:57.526228 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4269 11:12:57.529761 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4270 11:12:57.529836
4271 11:12:57.533091 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4272 11:12:57.536684 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4273 11:12:57.539648 [Gating] SW calibration Done
4274 11:12:57.539724 ==
4275 11:12:57.543263 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 11:12:57.546877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 11:12:57.546977 ==
4278 11:12:57.549756 RX Vref Scan: 0
4279 11:12:57.549829
4280 11:12:57.552870 RX Vref 0 -> 0, step: 1
4281 11:12:57.552947
4282 11:12:57.556539 RX Delay -230 -> 252, step: 16
4283 11:12:57.559681 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4284 11:12:57.562869 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4285 11:12:57.566115 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4286 11:12:57.570031 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4287 11:12:57.576139 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4288 11:12:57.579522 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4289 11:12:57.582725 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4290 11:12:57.585999 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4291 11:12:57.593202 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4292 11:12:57.596615 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4293 11:12:57.599727 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4294 11:12:57.602949 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4295 11:12:57.609337 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4296 11:12:57.612588 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4297 11:12:57.616444 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4298 11:12:57.619190 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4299 11:12:57.619289 ==
4300 11:12:57.623116 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 11:12:57.629030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 11:12:57.629109 ==
4303 11:12:57.629178 DQS Delay:
4304 11:12:57.632931 DQS0 = 0, DQS1 = 0
4305 11:12:57.633010 DQM Delay:
4306 11:12:57.633078 DQM0 = 39, DQM1 = 31
4307 11:12:57.636297 DQ Delay:
4308 11:12:57.639104 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4309 11:12:57.642670 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4310 11:12:57.646002 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4311 11:12:57.649667 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4312 11:12:57.649754
4313 11:12:57.649818
4314 11:12:57.649878 ==
4315 11:12:57.652513 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 11:12:57.655642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 11:12:57.655717 ==
4318 11:12:57.655779
4319 11:12:57.655850
4320 11:12:57.659234 TX Vref Scan disable
4321 11:12:57.659341 == TX Byte 0 ==
4322 11:12:57.665670 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4323 11:12:57.669357 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4324 11:12:57.669437 == TX Byte 1 ==
4325 11:12:57.675765 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4326 11:12:57.678864 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4327 11:12:57.678938 ==
4328 11:12:57.682723 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 11:12:57.686025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 11:12:57.686099 ==
4331 11:12:57.686164
4332 11:12:57.688713
4333 11:12:57.688827 TX Vref Scan disable
4334 11:12:57.692454 == TX Byte 0 ==
4335 11:12:57.695683 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4336 11:12:57.702660 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4337 11:12:57.702768 == TX Byte 1 ==
4338 11:12:57.705926 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4339 11:12:57.712270 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4340 11:12:57.712348
4341 11:12:57.712412 [DATLAT]
4342 11:12:57.712471 Freq=600, CH0 RK1
4343 11:12:57.712532
4344 11:12:57.716109 DATLAT Default: 0x9
4345 11:12:57.716184 0, 0xFFFF, sum = 0
4346 11:12:57.719458 1, 0xFFFF, sum = 0
4347 11:12:57.719543 2, 0xFFFF, sum = 0
4348 11:12:57.722665 3, 0xFFFF, sum = 0
4349 11:12:57.725895 4, 0xFFFF, sum = 0
4350 11:12:57.725978 5, 0xFFFF, sum = 0
4351 11:12:57.729106 6, 0xFFFF, sum = 0
4352 11:12:57.729189 7, 0xFFFF, sum = 0
4353 11:12:57.732266 8, 0x0, sum = 1
4354 11:12:57.732349 9, 0x0, sum = 2
4355 11:12:57.732415 10, 0x0, sum = 3
4356 11:12:57.735553 11, 0x0, sum = 4
4357 11:12:57.735636 best_step = 9
4358 11:12:57.735700
4359 11:12:57.735760 ==
4360 11:12:57.738910 Dram Type= 6, Freq= 0, CH_0, rank 1
4361 11:12:57.746003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 11:12:57.746086 ==
4363 11:12:57.746150 RX Vref Scan: 0
4364 11:12:57.746209
4365 11:12:57.749088 RX Vref 0 -> 0, step: 1
4366 11:12:57.749170
4367 11:12:57.752276 RX Delay -195 -> 252, step: 8
4368 11:12:57.755821 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4369 11:12:57.762406 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4370 11:12:57.765458 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4371 11:12:57.768665 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4372 11:12:57.772454 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4373 11:12:57.778816 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4374 11:12:57.782421 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4375 11:12:57.785475 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4376 11:12:57.788777 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4377 11:12:57.791997 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4378 11:12:57.798461 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4379 11:12:57.801655 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4380 11:12:57.805634 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4381 11:12:57.808307 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4382 11:12:57.815361 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4383 11:12:57.818685 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4384 11:12:57.818765 ==
4385 11:12:57.821874 Dram Type= 6, Freq= 0, CH_0, rank 1
4386 11:12:57.825198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 11:12:57.825279 ==
4388 11:12:57.828454 DQS Delay:
4389 11:12:57.828534 DQS0 = 0, DQS1 = 0
4390 11:12:57.831709 DQM Delay:
4391 11:12:57.831788 DQM0 = 40, DQM1 = 33
4392 11:12:57.831851 DQ Delay:
4393 11:12:57.835337 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4394 11:12:57.838580 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4395 11:12:57.841951 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =20
4396 11:12:57.845200 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4397 11:12:57.845284
4398 11:12:57.845350
4399 11:12:57.854619 [DQSOSCAuto] RK1, (LSB)MR18= 0x5031, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4400 11:12:57.858404 CH0 RK1: MR19=808, MR18=5031
4401 11:12:57.864746 CH0_RK1: MR19=0x808, MR18=0x5031, DQSOSC=394, MR23=63, INC=168, DEC=112
4402 11:12:57.864847 [RxdqsGatingPostProcess] freq 600
4403 11:12:57.871337 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4404 11:12:57.874595 Pre-setting of DQS Precalculation
4405 11:12:57.878260 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4406 11:12:57.881171 ==
4407 11:12:57.884311 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 11:12:57.888020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 11:12:57.888104 ==
4410 11:12:57.890983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4411 11:12:57.898073 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4412 11:12:57.901466 [CA 0] Center 35 (5~65) winsize 61
4413 11:12:57.905343 [CA 1] Center 35 (5~66) winsize 62
4414 11:12:57.908715 [CA 2] Center 34 (4~65) winsize 62
4415 11:12:57.911444 [CA 3] Center 34 (3~65) winsize 63
4416 11:12:57.915386 [CA 4] Center 34 (3~65) winsize 63
4417 11:12:57.918645 [CA 5] Center 33 (3~64) winsize 62
4418 11:12:57.918728
4419 11:12:57.921616 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4420 11:12:57.921699
4421 11:12:57.924801 [CATrainingPosCal] consider 1 rank data
4422 11:12:57.928630 u2DelayCellTimex100 = 270/100 ps
4423 11:12:57.931902 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4424 11:12:57.935161 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4425 11:12:57.941521 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4426 11:12:57.944852 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4427 11:12:57.948032 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4428 11:12:57.951892 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4429 11:12:57.951976
4430 11:12:57.955117 CA PerBit enable=1, Macro0, CA PI delay=33
4431 11:12:57.955200
4432 11:12:57.958082 [CBTSetCACLKResult] CA Dly = 33
4433 11:12:57.958165 CS Dly: 4 (0~35)
4434 11:12:57.961692 ==
4435 11:12:57.961775 Dram Type= 6, Freq= 0, CH_1, rank 1
4436 11:12:57.968081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 11:12:57.968165 ==
4438 11:12:57.971308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4439 11:12:57.978076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4440 11:12:57.981904 [CA 0] Center 35 (5~66) winsize 62
4441 11:12:57.984918 [CA 1] Center 35 (5~66) winsize 62
4442 11:12:57.988621 [CA 2] Center 34 (4~65) winsize 62
4443 11:12:57.991764 [CA 3] Center 34 (3~65) winsize 63
4444 11:12:57.995282 [CA 4] Center 34 (4~65) winsize 62
4445 11:12:57.998388 [CA 5] Center 33 (3~64) winsize 62
4446 11:12:57.998497
4447 11:12:58.001702 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4448 11:12:58.001785
4449 11:12:58.005057 [CATrainingPosCal] consider 2 rank data
4450 11:12:58.008350 u2DelayCellTimex100 = 270/100 ps
4451 11:12:58.011678 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4452 11:12:58.018616 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4453 11:12:58.021687 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4454 11:12:58.024780 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4455 11:12:58.028506 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4456 11:12:58.031733 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4457 11:12:58.031815
4458 11:12:58.034936 CA PerBit enable=1, Macro0, CA PI delay=33
4459 11:12:58.035019
4460 11:12:58.038131 [CBTSetCACLKResult] CA Dly = 33
4461 11:12:58.038214 CS Dly: 4 (0~36)
4462 11:12:58.041518
4463 11:12:58.044541 ----->DramcWriteLeveling(PI) begin...
4464 11:12:58.044625 ==
4465 11:12:58.047846 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 11:12:58.051149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 11:12:58.051259 ==
4468 11:12:58.054318 Write leveling (Byte 0): 29 => 29
4469 11:12:58.058175 Write leveling (Byte 1): 32 => 32
4470 11:12:58.061432 DramcWriteLeveling(PI) end<-----
4471 11:12:58.061515
4472 11:12:58.061580 ==
4473 11:12:58.064664 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 11:12:58.068216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 11:12:58.068300 ==
4476 11:12:58.071471 [Gating] SW mode calibration
4477 11:12:58.077815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4478 11:12:58.084548 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4479 11:12:58.087737 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4480 11:12:58.091219 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4481 11:12:58.097364 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 11:12:58.100992 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 1)
4483 11:12:58.104060 0 9 16 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (0 0)
4484 11:12:58.110929 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 11:12:58.114255 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 11:12:58.117460 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 11:12:58.124511 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 11:12:58.127610 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 11:12:58.130786 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 11:12:58.137481 0 10 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
4491 11:12:58.140999 0 10 16 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
4492 11:12:58.144139 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 11:12:58.150800 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 11:12:58.154034 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 11:12:58.157387 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 11:12:58.160663 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 11:12:58.167253 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 11:12:58.170314 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4499 11:12:58.173822 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4500 11:12:58.180432 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 11:12:58.183699 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:12:58.186957 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 11:12:58.193836 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 11:12:58.196912 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 11:12:58.200760 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 11:12:58.207422 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 11:12:58.210519 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 11:12:58.213602 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:12:58.220270 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:12:58.223545 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:12:58.227328 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:12:58.233614 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:12:58.236761 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:12:58.240070 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:12:58.246528 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 11:12:58.246634 Total UI for P1: 0, mck2ui 16
4517 11:12:58.253508 best dqsien dly found for B0: ( 0, 13, 14)
4518 11:12:58.253592 Total UI for P1: 0, mck2ui 16
4519 11:12:58.260460 best dqsien dly found for B1: ( 0, 13, 14)
4520 11:12:58.262950 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4521 11:12:58.266908 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4522 11:12:58.267018
4523 11:12:58.269639 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4524 11:12:58.273461 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4525 11:12:58.276518 [Gating] SW calibration Done
4526 11:12:58.276628 ==
4527 11:12:58.279795 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 11:12:58.282986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 11:12:58.283090 ==
4530 11:12:58.286798 RX Vref Scan: 0
4531 11:12:58.286907
4532 11:12:58.287001 RX Vref 0 -> 0, step: 1
4533 11:12:58.289967
4534 11:12:58.290076 RX Delay -230 -> 252, step: 16
4535 11:12:58.296662 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4536 11:12:58.299779 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4537 11:12:58.302792 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4538 11:12:58.306512 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4539 11:12:58.313113 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4540 11:12:58.316102 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4541 11:12:58.320063 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4542 11:12:58.323224 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4543 11:12:58.326307 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4544 11:12:58.332863 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4545 11:12:58.335760 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4546 11:12:58.339509 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4547 11:12:58.342910 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4548 11:12:58.349315 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4549 11:12:58.352611 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4550 11:12:58.356454 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4551 11:12:58.356554 ==
4552 11:12:58.359617 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 11:12:58.362699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 11:12:58.365826 ==
4555 11:12:58.365943 DQS Delay:
4556 11:12:58.366050 DQS0 = 0, DQS1 = 0
4557 11:12:58.369799 DQM Delay:
4558 11:12:58.369929 DQM0 = 43, DQM1 = 36
4559 11:12:58.370017 DQ Delay:
4560 11:12:58.372450 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4561 11:12:58.376110 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4562 11:12:58.379285 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4563 11:12:58.382403 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4564 11:12:58.382545
4565 11:12:58.385644
4566 11:12:58.385744 ==
4567 11:12:58.389516 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 11:12:58.392798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 11:12:58.392904 ==
4570 11:12:58.392985
4571 11:12:58.393048
4572 11:12:58.396086 TX Vref Scan disable
4573 11:12:58.396162 == TX Byte 0 ==
4574 11:12:58.402631 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4575 11:12:58.405907 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4576 11:12:58.406012 == TX Byte 1 ==
4577 11:12:58.412733 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4578 11:12:58.415719 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4579 11:12:58.415824 ==
4580 11:12:58.418745 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 11:12:58.422392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 11:12:58.422469 ==
4583 11:12:58.422550
4584 11:12:58.422645
4585 11:12:58.425522 TX Vref Scan disable
4586 11:12:58.429004 == TX Byte 0 ==
4587 11:12:58.432047 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4588 11:12:58.435393 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4589 11:12:58.438542 == TX Byte 1 ==
4590 11:12:58.442236 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4591 11:12:58.448672 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4592 11:12:58.448790
4593 11:12:58.448883 [DATLAT]
4594 11:12:58.448984 Freq=600, CH1 RK0
4595 11:12:58.449074
4596 11:12:58.451911 DATLAT Default: 0x9
4597 11:12:58.452015 0, 0xFFFF, sum = 0
4598 11:12:58.455131 1, 0xFFFF, sum = 0
4599 11:12:58.455249 2, 0xFFFF, sum = 0
4600 11:12:58.458494 3, 0xFFFF, sum = 0
4601 11:12:58.458607 4, 0xFFFF, sum = 0
4602 11:12:58.461699 5, 0xFFFF, sum = 0
4603 11:12:58.465035 6, 0xFFFF, sum = 0
4604 11:12:58.465139 7, 0xFFFF, sum = 0
4605 11:12:58.468339 8, 0x0, sum = 1
4606 11:12:58.468440 9, 0x0, sum = 2
4607 11:12:58.468542 10, 0x0, sum = 3
4608 11:12:58.472090 11, 0x0, sum = 4
4609 11:12:58.472174 best_step = 9
4610 11:12:58.472241
4611 11:12:58.472300 ==
4612 11:12:58.475416 Dram Type= 6, Freq= 0, CH_1, rank 0
4613 11:12:58.481829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 11:12:58.481931 ==
4615 11:12:58.482034 RX Vref Scan: 1
4616 11:12:58.482124
4617 11:12:58.484933 RX Vref 0 -> 0, step: 1
4618 11:12:58.485040
4619 11:12:58.488587 RX Delay -179 -> 252, step: 8
4620 11:12:58.488659
4621 11:12:58.491899 Set Vref, RX VrefLevel [Byte0]: 59
4622 11:12:58.495069 [Byte1]: 52
4623 11:12:58.495177
4624 11:12:58.498156 Final RX Vref Byte 0 = 59 to rank0
4625 11:12:58.501475 Final RX Vref Byte 1 = 52 to rank0
4626 11:12:58.504721 Final RX Vref Byte 0 = 59 to rank1
4627 11:12:58.507941 Final RX Vref Byte 1 = 52 to rank1==
4628 11:12:58.511764 Dram Type= 6, Freq= 0, CH_1, rank 0
4629 11:12:58.514981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 11:12:58.515084 ==
4631 11:12:58.518140 DQS Delay:
4632 11:12:58.518238 DQS0 = 0, DQS1 = 0
4633 11:12:58.521965 DQM Delay:
4634 11:12:58.522068 DQM0 = 40, DQM1 = 33
4635 11:12:58.522162 DQ Delay:
4636 11:12:58.524945 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4637 11:12:58.527927 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4638 11:12:58.531490 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4639 11:12:58.534649 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4640 11:12:58.534722
4641 11:12:58.534813
4642 11:12:58.544525 [DQSOSCAuto] RK0, (LSB)MR18= 0x490f, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4643 11:12:58.548229 CH1 RK0: MR19=808, MR18=490F
4644 11:12:58.554892 CH1_RK0: MR19=0x808, MR18=0x490F, DQSOSC=396, MR23=63, INC=167, DEC=111
4645 11:12:58.555005
4646 11:12:58.558074 ----->DramcWriteLeveling(PI) begin...
4647 11:12:58.558183 ==
4648 11:12:58.561336 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 11:12:58.564538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 11:12:58.564650 ==
4651 11:12:58.567855 Write leveling (Byte 0): 28 => 28
4652 11:12:58.571101 Write leveling (Byte 1): 31 => 31
4653 11:12:58.574390 DramcWriteLeveling(PI) end<-----
4654 11:12:58.574479
4655 11:12:58.574545 ==
4656 11:12:58.577691 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 11:12:58.581011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 11:12:58.581161 ==
4659 11:12:58.584191 [Gating] SW mode calibration
4660 11:12:58.591344 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4661 11:12:58.597576 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4662 11:12:58.600892 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4663 11:12:58.604155 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4664 11:12:58.611247 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4665 11:12:58.614586 0 9 12 | B1->B0 | 3030 2b2b | 1 1 | (1 1) (1 0)
4666 11:12:58.617828 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4667 11:12:58.623920 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 11:12:58.627618 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4669 11:12:58.630595 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 11:12:58.637169 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 11:12:58.640761 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 11:12:58.643955 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4673 11:12:58.651079 0 10 12 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
4674 11:12:58.654016 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
4675 11:12:58.657361 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 11:12:58.663780 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 11:12:58.666940 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 11:12:58.670726 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 11:12:58.677139 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 11:12:58.680492 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 11:12:58.683919 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4682 11:12:58.690336 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 11:12:58.693582 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 11:12:58.697166 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 11:12:58.703914 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 11:12:58.707304 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 11:12:58.710493 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 11:12:58.713654 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 11:12:58.720280 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 11:12:58.723519 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 11:12:58.726686 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:12:58.733822 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 11:12:58.736687 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 11:12:58.740267 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:12:58.746655 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 11:12:58.750298 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4697 11:12:58.753558 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 11:12:58.756509 Total UI for P1: 0, mck2ui 16
4699 11:12:58.759879 best dqsien dly found for B0: ( 0, 13, 8)
4700 11:12:58.763380 Total UI for P1: 0, mck2ui 16
4701 11:12:58.766426 best dqsien dly found for B1: ( 0, 13, 10)
4702 11:12:58.770271 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4703 11:12:58.773771 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4704 11:12:58.776709
4705 11:12:58.779994 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4706 11:12:58.783224 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4707 11:12:58.786446 [Gating] SW calibration Done
4708 11:12:58.786534 ==
4709 11:12:58.790265 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 11:12:58.793521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 11:12:58.793630 ==
4712 11:12:58.793725 RX Vref Scan: 0
4713 11:12:58.793825
4714 11:12:58.796792 RX Vref 0 -> 0, step: 1
4715 11:12:58.796866
4716 11:12:58.799999 RX Delay -230 -> 252, step: 16
4717 11:12:58.802995 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4718 11:12:58.806631 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4719 11:12:58.813105 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4720 11:12:58.816429 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4721 11:12:58.819672 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4722 11:12:58.822914 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4723 11:12:58.829966 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4724 11:12:58.833221 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4725 11:12:58.836557 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4726 11:12:58.839530 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4727 11:12:58.842993 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4728 11:12:58.849510 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4729 11:12:58.853036 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4730 11:12:58.856501 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4731 11:12:58.859426 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4732 11:12:58.866150 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4733 11:12:58.866303 ==
4734 11:12:58.869545 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 11:12:58.872802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 11:12:58.872916 ==
4737 11:12:58.873033 DQS Delay:
4738 11:12:58.876062 DQS0 = 0, DQS1 = 0
4739 11:12:58.876164 DQM Delay:
4740 11:12:58.879342 DQM0 = 42, DQM1 = 38
4741 11:12:58.879426 DQ Delay:
4742 11:12:58.882567 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4743 11:12:58.885845 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4744 11:12:58.889690 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4745 11:12:58.892935 DQ12 =41, DQ13 =57, DQ14 =41, DQ15 =49
4746 11:12:58.893042
4747 11:12:58.893136
4748 11:12:58.893225 ==
4749 11:12:58.896267 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 11:12:58.899470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 11:12:58.902783 ==
4752 11:12:58.902895
4753 11:12:58.902999
4754 11:12:58.903098 TX Vref Scan disable
4755 11:12:58.905899 == TX Byte 0 ==
4756 11:12:58.909539 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4757 11:12:58.915774 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4758 11:12:58.915884 == TX Byte 1 ==
4759 11:12:58.919021 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4760 11:12:58.925566 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4761 11:12:58.925673 ==
4762 11:12:58.928841 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 11:12:58.932355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 11:12:58.932461 ==
4765 11:12:58.932556
4766 11:12:58.932646
4767 11:12:58.935401 TX Vref Scan disable
4768 11:12:58.938801 == TX Byte 0 ==
4769 11:12:58.942103 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4770 11:12:58.945411 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4771 11:12:58.948954 == TX Byte 1 ==
4772 11:12:58.952711 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4773 11:12:58.955585 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4774 11:12:58.955671
4775 11:12:58.955739 [DATLAT]
4776 11:12:58.959181 Freq=600, CH1 RK1
4777 11:12:58.959267
4778 11:12:58.962197 DATLAT Default: 0x9
4779 11:12:58.962284 0, 0xFFFF, sum = 0
4780 11:12:58.965878 1, 0xFFFF, sum = 0
4781 11:12:58.965965 2, 0xFFFF, sum = 0
4782 11:12:58.969115 3, 0xFFFF, sum = 0
4783 11:12:58.969202 4, 0xFFFF, sum = 0
4784 11:12:58.972051 5, 0xFFFF, sum = 0
4785 11:12:58.972146 6, 0xFFFF, sum = 0
4786 11:12:58.975776 7, 0xFFFF, sum = 0
4787 11:12:58.975858 8, 0x0, sum = 1
4788 11:12:58.978943 9, 0x0, sum = 2
4789 11:12:58.979029 10, 0x0, sum = 3
4790 11:12:58.979103 11, 0x0, sum = 4
4791 11:12:58.982083 best_step = 9
4792 11:12:58.982163
4793 11:12:58.982237 ==
4794 11:12:58.985391 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 11:12:58.988550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 11:12:58.988635 ==
4797 11:12:58.991858 RX Vref Scan: 0
4798 11:12:58.991945
4799 11:12:58.992013 RX Vref 0 -> 0, step: 1
4800 11:12:58.995346
4801 11:12:58.995428 RX Delay -179 -> 252, step: 8
4802 11:12:59.002850 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4803 11:12:59.006054 iDelay=205, Bit 1, Center 36 (-115 ~ 188) 304
4804 11:12:59.009364 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4805 11:12:59.012827 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4806 11:12:59.019782 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4807 11:12:59.023123 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4808 11:12:59.025797 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4809 11:12:59.029170 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4810 11:12:59.036334 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4811 11:12:59.039593 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4812 11:12:59.042812 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4813 11:12:59.046075 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4814 11:12:59.049168 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4815 11:12:59.056393 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4816 11:12:59.059283 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4817 11:12:59.062579 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4818 11:12:59.062664 ==
4819 11:12:59.065374 Dram Type= 6, Freq= 0, CH_1, rank 1
4820 11:12:59.072506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4821 11:12:59.072592 ==
4822 11:12:59.072658 DQS Delay:
4823 11:12:59.075609 DQS0 = 0, DQS1 = 0
4824 11:12:59.075693 DQM Delay:
4825 11:12:59.075759 DQM0 = 39, DQM1 = 33
4826 11:12:59.079207 DQ Delay:
4827 11:12:59.082304 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =36
4828 11:12:59.085539 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4829 11:12:59.088783 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4830 11:12:59.091931 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4831 11:12:59.092041
4832 11:12:59.092142
4833 11:12:59.098512 [DQSOSCAuto] RK1, (LSB)MR18= 0x3341, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4834 11:12:59.102442 CH1 RK1: MR19=808, MR18=3341
4835 11:12:59.108811 CH1_RK1: MR19=0x808, MR18=0x3341, DQSOSC=397, MR23=63, INC=166, DEC=110
4836 11:12:59.112090 [RxdqsGatingPostProcess] freq 600
4837 11:12:59.115308 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4838 11:12:59.118875 Pre-setting of DQS Precalculation
4839 11:12:59.125340 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4840 11:12:59.131997 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4841 11:12:59.139093 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4842 11:12:59.139194
4843 11:12:59.139291
4844 11:12:59.142259 [Calibration Summary] 1200 Mbps
4845 11:12:59.142332 CH 0, Rank 0
4846 11:12:59.145583 SW Impedance : PASS
4847 11:12:59.148905 DUTY Scan : NO K
4848 11:12:59.149003 ZQ Calibration : PASS
4849 11:12:59.152314 Jitter Meter : NO K
4850 11:12:59.155214 CBT Training : PASS
4851 11:12:59.155311 Write leveling : PASS
4852 11:12:59.158476 RX DQS gating : PASS
4853 11:12:59.161979 RX DQ/DQS(RDDQC) : PASS
4854 11:12:59.162050 TX DQ/DQS : PASS
4855 11:12:59.164946 RX DATLAT : PASS
4856 11:12:59.168616 RX DQ/DQS(Engine): PASS
4857 11:12:59.168691 TX OE : NO K
4858 11:12:59.168754 All Pass.
4859 11:12:59.171670
4860 11:12:59.171740 CH 0, Rank 1
4861 11:12:59.175326 SW Impedance : PASS
4862 11:12:59.175437 DUTY Scan : NO K
4863 11:12:59.178359 ZQ Calibration : PASS
4864 11:12:59.178429 Jitter Meter : NO K
4865 11:12:59.181531 CBT Training : PASS
4866 11:12:59.185304 Write leveling : PASS
4867 11:12:59.185377 RX DQS gating : PASS
4868 11:12:59.188243 RX DQ/DQS(RDDQC) : PASS
4869 11:12:59.191421 TX DQ/DQS : PASS
4870 11:12:59.191531 RX DATLAT : PASS
4871 11:12:59.194738 RX DQ/DQS(Engine): PASS
4872 11:12:59.198488 TX OE : NO K
4873 11:12:59.198565 All Pass.
4874 11:12:59.198628
4875 11:12:59.198688 CH 1, Rank 0
4876 11:12:59.201714 SW Impedance : PASS
4877 11:12:59.204796 DUTY Scan : NO K
4878 11:12:59.204868 ZQ Calibration : PASS
4879 11:12:59.208061 Jitter Meter : NO K
4880 11:12:59.211247 CBT Training : PASS
4881 11:12:59.211345 Write leveling : PASS
4882 11:12:59.214509 RX DQS gating : PASS
4883 11:12:59.218030 RX DQ/DQS(RDDQC) : PASS
4884 11:12:59.218133 TX DQ/DQS : PASS
4885 11:12:59.221505 RX DATLAT : PASS
4886 11:12:59.224561 RX DQ/DQS(Engine): PASS
4887 11:12:59.224637 TX OE : NO K
4888 11:12:59.224701 All Pass.
4889 11:12:59.227808
4890 11:12:59.227879 CH 1, Rank 1
4891 11:12:59.231189 SW Impedance : PASS
4892 11:12:59.231286 DUTY Scan : NO K
4893 11:12:59.234469 ZQ Calibration : PASS
4894 11:12:59.238128 Jitter Meter : NO K
4895 11:12:59.238201 CBT Training : PASS
4896 11:12:59.241429 Write leveling : PASS
4897 11:12:59.241501 RX DQS gating : PASS
4898 11:12:59.244745 RX DQ/DQS(RDDQC) : PASS
4899 11:12:59.248110 TX DQ/DQS : PASS
4900 11:12:59.248211 RX DATLAT : PASS
4901 11:12:59.250970 RX DQ/DQS(Engine): PASS
4902 11:12:59.254755 TX OE : NO K
4903 11:12:59.254839 All Pass.
4904 11:12:59.254919
4905 11:12:59.257911 DramC Write-DBI off
4906 11:12:59.257995 PER_BANK_REFRESH: Hybrid Mode
4907 11:12:59.261033 TX_TRACKING: ON
4908 11:12:59.267657 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4909 11:12:59.274493 [FAST_K] Save calibration result to emmc
4910 11:12:59.277529 dramc_set_vcore_voltage set vcore to 662500
4911 11:12:59.277614 Read voltage for 933, 3
4912 11:12:59.281357 Vio18 = 0
4913 11:12:59.281433 Vcore = 662500
4914 11:12:59.281512 Vdram = 0
4915 11:12:59.284339 Vddq = 0
4916 11:12:59.284415 Vmddr = 0
4917 11:12:59.287407 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4918 11:12:59.294612 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4919 11:12:59.297537 MEM_TYPE=3, freq_sel=17
4920 11:12:59.300743 sv_algorithm_assistance_LP4_1600
4921 11:12:59.304615 ============ PULL DRAM RESETB DOWN ============
4922 11:12:59.307810 ========== PULL DRAM RESETB DOWN end =========
4923 11:12:59.314172 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4924 11:12:59.317483 ===================================
4925 11:12:59.317564 LPDDR4 DRAM CONFIGURATION
4926 11:12:59.320656 ===================================
4927 11:12:59.324469 EX_ROW_EN[0] = 0x0
4928 11:12:59.324546 EX_ROW_EN[1] = 0x0
4929 11:12:59.327562 LP4Y_EN = 0x0
4930 11:12:59.327661 WORK_FSP = 0x0
4931 11:12:59.330679 WL = 0x3
4932 11:12:59.330750 RL = 0x3
4933 11:12:59.333847 BL = 0x2
4934 11:12:59.337712 RPST = 0x0
4935 11:12:59.337784 RD_PRE = 0x0
4936 11:12:59.340892 WR_PRE = 0x1
4937 11:12:59.340983 WR_PST = 0x0
4938 11:12:59.344266 DBI_WR = 0x0
4939 11:12:59.344339 DBI_RD = 0x0
4940 11:12:59.347576 OTF = 0x1
4941 11:12:59.350853 ===================================
4942 11:12:59.354126 ===================================
4943 11:12:59.354202 ANA top config
4944 11:12:59.357398 ===================================
4945 11:12:59.360553 DLL_ASYNC_EN = 0
4946 11:12:59.363677 ALL_SLAVE_EN = 1
4947 11:12:59.363756 NEW_RANK_MODE = 1
4948 11:12:59.367484 DLL_IDLE_MODE = 1
4949 11:12:59.370762 LP45_APHY_COMB_EN = 1
4950 11:12:59.373913 TX_ODT_DIS = 1
4951 11:12:59.377366 NEW_8X_MODE = 1
4952 11:12:59.377443 ===================================
4953 11:12:59.380318 ===================================
4954 11:12:59.384040 data_rate = 1866
4955 11:12:59.386985 CKR = 1
4956 11:12:59.390601 DQ_P2S_RATIO = 8
4957 11:12:59.393570 ===================================
4958 11:12:59.397204 CA_P2S_RATIO = 8
4959 11:12:59.400337 DQ_CA_OPEN = 0
4960 11:12:59.403646 DQ_SEMI_OPEN = 0
4961 11:12:59.403744 CA_SEMI_OPEN = 0
4962 11:12:59.406972 CA_FULL_RATE = 0
4963 11:12:59.410170 DQ_CKDIV4_EN = 1
4964 11:12:59.413325 CA_CKDIV4_EN = 1
4965 11:12:59.417102 CA_PREDIV_EN = 0
4966 11:12:59.420368 PH8_DLY = 0
4967 11:12:59.420451 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4968 11:12:59.423522 DQ_AAMCK_DIV = 4
4969 11:12:59.426792 CA_AAMCK_DIV = 4
4970 11:12:59.430093 CA_ADMCK_DIV = 4
4971 11:12:59.433243 DQ_TRACK_CA_EN = 0
4972 11:12:59.436472 CA_PICK = 933
4973 11:12:59.436557 CA_MCKIO = 933
4974 11:12:59.440275 MCKIO_SEMI = 0
4975 11:12:59.443532 PLL_FREQ = 3732
4976 11:12:59.446900 DQ_UI_PI_RATIO = 32
4977 11:12:59.449926 CA_UI_PI_RATIO = 0
4978 11:12:59.453264 ===================================
4979 11:12:59.456646 ===================================
4980 11:12:59.459703 memory_type:LPDDR4
4981 11:12:59.459788 GP_NUM : 10
4982 11:12:59.463581 SRAM_EN : 1
4983 11:12:59.463665 MD32_EN : 0
4984 11:12:59.466777 ===================================
4985 11:12:59.469825 [ANA_INIT] >>>>>>>>>>>>>>
4986 11:12:59.473107 <<<<<< [CONFIGURE PHASE]: ANA_TX
4987 11:12:59.476961 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4988 11:12:59.480244 ===================================
4989 11:12:59.483281 data_rate = 1866,PCW = 0X8f00
4990 11:12:59.486544 ===================================
4991 11:12:59.490003 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4992 11:12:59.496813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4993 11:12:59.500176 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4994 11:12:59.506449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4995 11:12:59.510082 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4996 11:12:59.513159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4997 11:12:59.513243 [ANA_INIT] flow start
4998 11:12:59.516965 [ANA_INIT] PLL >>>>>>>>
4999 11:12:59.519919 [ANA_INIT] PLL <<<<<<<<
5000 11:12:59.520002 [ANA_INIT] MIDPI >>>>>>>>
5001 11:12:59.523086 [ANA_INIT] MIDPI <<<<<<<<
5002 11:12:59.526369 [ANA_INIT] DLL >>>>>>>>
5003 11:12:59.526478 [ANA_INIT] flow end
5004 11:12:59.532861 ============ LP4 DIFF to SE enter ============
5005 11:12:59.536742 ============ LP4 DIFF to SE exit ============
5006 11:12:59.536825 [ANA_INIT] <<<<<<<<<<<<<
5007 11:12:59.539916 [Flow] Enable top DCM control >>>>>
5008 11:12:59.543210 [Flow] Enable top DCM control <<<<<
5009 11:12:59.546493 Enable DLL master slave shuffle
5010 11:12:59.553054 ==============================================================
5011 11:12:59.556257 Gating Mode config
5012 11:12:59.559410 ==============================================================
5013 11:12:59.563239 Config description:
5014 11:12:59.572914 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5015 11:12:59.579935 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5016 11:12:59.583206 SELPH_MODE 0: By rank 1: By Phase
5017 11:12:59.590146 ==============================================================
5018 11:12:59.593510 GAT_TRACK_EN = 1
5019 11:12:59.593596 RX_GATING_MODE = 2
5020 11:12:59.596583 RX_GATING_TRACK_MODE = 2
5021 11:12:59.600436 SELPH_MODE = 1
5022 11:12:59.603256 PICG_EARLY_EN = 1
5023 11:12:59.606985 VALID_LAT_VALUE = 1
5024 11:12:59.612958 ==============================================================
5025 11:12:59.616625 Enter into Gating configuration >>>>
5026 11:12:59.619682 Exit from Gating configuration <<<<
5027 11:12:59.622760 Enter into DVFS_PRE_config >>>>>
5028 11:12:59.632886 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5029 11:12:59.636166 Exit from DVFS_PRE_config <<<<<
5030 11:12:59.639331 Enter into PICG configuration >>>>
5031 11:12:59.643088 Exit from PICG configuration <<<<
5032 11:12:59.646431 [RX_INPUT] configuration >>>>>
5033 11:12:59.649591 [RX_INPUT] configuration <<<<<
5034 11:12:59.652872 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5035 11:12:59.659340 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5036 11:12:59.665973 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5037 11:12:59.672923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5038 11:12:59.676085 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5039 11:12:59.682503 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5040 11:12:59.685791 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5041 11:12:59.693028 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5042 11:12:59.696101 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5043 11:12:59.699445 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5044 11:12:59.702815 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5045 11:12:59.709442 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5046 11:12:59.712501 ===================================
5047 11:12:59.712596 LPDDR4 DRAM CONFIGURATION
5048 11:12:59.716109 ===================================
5049 11:12:59.719056 EX_ROW_EN[0] = 0x0
5050 11:12:59.722734 EX_ROW_EN[1] = 0x0
5051 11:12:59.722817 LP4Y_EN = 0x0
5052 11:12:59.725996 WORK_FSP = 0x0
5053 11:12:59.726079 WL = 0x3
5054 11:12:59.729551 RL = 0x3
5055 11:12:59.729648 BL = 0x2
5056 11:12:59.732548 RPST = 0x0
5057 11:12:59.732672 RD_PRE = 0x0
5058 11:12:59.735686 WR_PRE = 0x1
5059 11:12:59.735793 WR_PST = 0x0
5060 11:12:59.738890 DBI_WR = 0x0
5061 11:12:59.738987 DBI_RD = 0x0
5062 11:12:59.742776 OTF = 0x1
5063 11:12:59.745957 ===================================
5064 11:12:59.749123 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5065 11:12:59.752512 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5066 11:12:59.758794 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5067 11:12:59.761997 ===================================
5068 11:12:59.762070 LPDDR4 DRAM CONFIGURATION
5069 11:12:59.765953 ===================================
5070 11:12:59.769201 EX_ROW_EN[0] = 0x10
5071 11:12:59.772445 EX_ROW_EN[1] = 0x0
5072 11:12:59.772544 LP4Y_EN = 0x0
5073 11:12:59.775789 WORK_FSP = 0x0
5074 11:12:59.775860 WL = 0x3
5075 11:12:59.778916 RL = 0x3
5076 11:12:59.779013 BL = 0x2
5077 11:12:59.782020 RPST = 0x0
5078 11:12:59.782120 RD_PRE = 0x0
5079 11:12:59.785268 WR_PRE = 0x1
5080 11:12:59.785342 WR_PST = 0x0
5081 11:12:59.788601 DBI_WR = 0x0
5082 11:12:59.788672 DBI_RD = 0x0
5083 11:12:59.792462 OTF = 0x1
5084 11:12:59.795663 ===================================
5085 11:12:59.802249 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5086 11:12:59.805459 nWR fixed to 30
5087 11:12:59.805544 [ModeRegInit_LP4] CH0 RK0
5088 11:12:59.808711 [ModeRegInit_LP4] CH0 RK1
5089 11:12:59.812416 [ModeRegInit_LP4] CH1 RK0
5090 11:12:59.815529 [ModeRegInit_LP4] CH1 RK1
5091 11:12:59.815612 match AC timing 9
5092 11:12:59.821857 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5093 11:12:59.825399 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5094 11:12:59.828428 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5095 11:12:59.835279 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5096 11:12:59.838786 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5097 11:12:59.838905 ==
5098 11:12:59.841704 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 11:12:59.844938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 11:12:59.845037 ==
5101 11:12:59.851936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5102 11:12:59.858382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5103 11:12:59.861566 [CA 0] Center 38 (8~69) winsize 62
5104 11:12:59.864797 [CA 1] Center 38 (8~69) winsize 62
5105 11:12:59.868782 [CA 2] Center 35 (5~66) winsize 62
5106 11:12:59.871489 [CA 3] Center 34 (4~65) winsize 62
5107 11:12:59.875229 [CA 4] Center 34 (4~64) winsize 61
5108 11:12:59.878591 [CA 5] Center 34 (4~64) winsize 61
5109 11:12:59.878701
5110 11:12:59.881936 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5111 11:12:59.882037
5112 11:12:59.885291 [CATrainingPosCal] consider 1 rank data
5113 11:12:59.888370 u2DelayCellTimex100 = 270/100 ps
5114 11:12:59.891600 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5115 11:12:59.894822 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5116 11:12:59.898654 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5117 11:12:59.901834 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5118 11:12:59.905085 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5119 11:12:59.908360 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5120 11:12:59.908435
5121 11:12:59.914726 CA PerBit enable=1, Macro0, CA PI delay=34
5122 11:12:59.914830
5123 11:12:59.914922 [CBTSetCACLKResult] CA Dly = 34
5124 11:12:59.918061 CS Dly: 6 (0~37)
5125 11:12:59.918133 ==
5126 11:12:59.921266 Dram Type= 6, Freq= 0, CH_0, rank 1
5127 11:12:59.924792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 11:12:59.924865 ==
5129 11:12:59.931640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5130 11:12:59.937843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5131 11:12:59.941640 [CA 0] Center 38 (8~69) winsize 62
5132 11:12:59.944721 [CA 1] Center 38 (7~69) winsize 63
5133 11:12:59.947859 [CA 2] Center 35 (5~66) winsize 62
5134 11:12:59.951069 [CA 3] Center 35 (4~66) winsize 63
5135 11:12:59.954669 [CA 4] Center 34 (3~65) winsize 63
5136 11:12:59.957868 [CA 5] Center 33 (3~64) winsize 62
5137 11:12:59.957953
5138 11:12:59.961090 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5139 11:12:59.961177
5140 11:12:59.964267 [CATrainingPosCal] consider 2 rank data
5141 11:12:59.967540 u2DelayCellTimex100 = 270/100 ps
5142 11:12:59.970807 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5143 11:12:59.974167 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5144 11:12:59.977455 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5145 11:12:59.980798 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5146 11:12:59.984554 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5147 11:12:59.991129 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5148 11:12:59.991212
5149 11:12:59.994268 CA PerBit enable=1, Macro0, CA PI delay=34
5150 11:12:59.994352
5151 11:12:59.997457 [CBTSetCACLKResult] CA Dly = 34
5152 11:12:59.997540 CS Dly: 7 (0~39)
5153 11:12:59.997644
5154 11:13:00.000674 ----->DramcWriteLeveling(PI) begin...
5155 11:13:00.000759 ==
5156 11:13:00.004448 Dram Type= 6, Freq= 0, CH_0, rank 0
5157 11:13:00.007675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 11:13:00.010935 ==
5159 11:13:00.014412 Write leveling (Byte 0): 34 => 34
5160 11:13:00.014511 Write leveling (Byte 1): 25 => 25
5161 11:13:00.017433 DramcWriteLeveling(PI) end<-----
5162 11:13:00.017517
5163 11:13:00.017582 ==
5164 11:13:00.020664 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 11:13:00.027716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 11:13:00.027800 ==
5167 11:13:00.030534 [Gating] SW mode calibration
5168 11:13:00.037499 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5169 11:13:00.040533 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5170 11:13:00.047102 0 14 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5171 11:13:00.050634 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5172 11:13:00.053773 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 11:13:00.060379 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 11:13:00.063582 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 11:13:00.066982 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 11:13:00.073661 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 11:13:00.076873 0 14 28 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
5178 11:13:00.080733 0 15 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)
5179 11:13:00.087223 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 11:13:00.090483 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 11:13:00.093770 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 11:13:00.096823 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 11:13:00.103964 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 11:13:00.107242 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 11:13:00.110409 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 11:13:00.116884 1 0 0 | B1->B0 | 3434 3f3f | 0 0 | (0 0) (1 1)
5187 11:13:00.120026 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 11:13:00.123257 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 11:13:00.130340 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 11:13:00.133572 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 11:13:00.136612 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 11:13:00.143297 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 11:13:00.146815 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 11:13:00.149759 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5195 11:13:00.156598 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5196 11:13:00.160117 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 11:13:00.163082 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 11:13:00.170105 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 11:13:00.173359 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 11:13:00.176688 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 11:13:00.183116 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 11:13:00.186422 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 11:13:00.189676 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 11:13:00.196266 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:13:00.199915 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:13:00.203089 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:13:00.209439 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:13:00.213308 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:13:00.216545 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5210 11:13:00.222878 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5211 11:13:00.225960 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5212 11:13:00.229771 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 11:13:00.233089 Total UI for P1: 0, mck2ui 16
5214 11:13:00.236377 best dqsien dly found for B0: ( 1, 3, 0)
5215 11:13:00.239583 Total UI for P1: 0, mck2ui 16
5216 11:13:00.242764 best dqsien dly found for B1: ( 1, 3, 2)
5217 11:13:00.246252 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5218 11:13:00.249325 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5219 11:13:00.249428
5220 11:13:00.253072 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5221 11:13:00.256055 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5222 11:13:00.259692 [Gating] SW calibration Done
5223 11:13:00.259764 ==
5224 11:13:00.262826 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 11:13:00.269593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 11:13:00.269698 ==
5227 11:13:00.269790 RX Vref Scan: 0
5228 11:13:00.269879
5229 11:13:00.272699 RX Vref 0 -> 0, step: 1
5230 11:13:00.272793
5231 11:13:00.275904 RX Delay -80 -> 252, step: 8
5232 11:13:00.279819 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5233 11:13:00.283050 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5234 11:13:00.286294 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5235 11:13:00.289599 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5236 11:13:00.292860 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5237 11:13:00.299435 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5238 11:13:00.302556 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5239 11:13:00.306370 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5240 11:13:00.309426 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5241 11:13:00.312595 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5242 11:13:00.319108 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5243 11:13:00.322905 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5244 11:13:00.326264 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5245 11:13:00.329570 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5246 11:13:00.332816 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5247 11:13:00.335978 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5248 11:13:00.339275 ==
5249 11:13:00.339393 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 11:13:00.345842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 11:13:00.345950 ==
5252 11:13:00.346052 DQS Delay:
5253 11:13:00.349748 DQS0 = 0, DQS1 = 0
5254 11:13:00.349850 DQM Delay:
5255 11:13:00.352764 DQM0 = 98, DQM1 = 88
5256 11:13:00.352839 DQ Delay:
5257 11:13:00.356296 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =95
5258 11:13:00.359256 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5259 11:13:00.362338 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5260 11:13:00.366002 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5261 11:13:00.366108
5262 11:13:00.366208
5263 11:13:00.366300 ==
5264 11:13:00.368937 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 11:13:00.372623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 11:13:00.372725 ==
5267 11:13:00.372816
5268 11:13:00.372908
5269 11:13:00.375666 TX Vref Scan disable
5270 11:13:00.379262 == TX Byte 0 ==
5271 11:13:00.382379 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5272 11:13:00.385657 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5273 11:13:00.388826 == TX Byte 1 ==
5274 11:13:00.392165 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5275 11:13:00.396023 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5276 11:13:00.396107 ==
5277 11:13:00.399474 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 11:13:00.405879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 11:13:00.405966 ==
5280 11:13:00.406065
5281 11:13:00.406126
5282 11:13:00.406225 TX Vref Scan disable
5283 11:13:00.410488 == TX Byte 0 ==
5284 11:13:00.412882 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5285 11:13:00.419328 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5286 11:13:00.419449 == TX Byte 1 ==
5287 11:13:00.422614 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5288 11:13:00.429118 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5289 11:13:00.429201
5290 11:13:00.429267 [DATLAT]
5291 11:13:00.429328 Freq=933, CH0 RK0
5292 11:13:00.429388
5293 11:13:00.432398 DATLAT Default: 0xd
5294 11:13:00.435834 0, 0xFFFF, sum = 0
5295 11:13:00.435923 1, 0xFFFF, sum = 0
5296 11:13:00.439600 2, 0xFFFF, sum = 0
5297 11:13:00.439715 3, 0xFFFF, sum = 0
5298 11:13:00.442329 4, 0xFFFF, sum = 0
5299 11:13:00.442440 5, 0xFFFF, sum = 0
5300 11:13:00.446181 6, 0xFFFF, sum = 0
5301 11:13:00.446291 7, 0xFFFF, sum = 0
5302 11:13:00.449348 8, 0xFFFF, sum = 0
5303 11:13:00.449424 9, 0xFFFF, sum = 0
5304 11:13:00.452636 10, 0x0, sum = 1
5305 11:13:00.452725 11, 0x0, sum = 2
5306 11:13:00.455820 12, 0x0, sum = 3
5307 11:13:00.455894 13, 0x0, sum = 4
5308 11:13:00.455966 best_step = 11
5309 11:13:00.459188
5310 11:13:00.459287 ==
5311 11:13:00.462300 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 11:13:00.465874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 11:13:00.465957 ==
5314 11:13:00.466036 RX Vref Scan: 1
5315 11:13:00.466152
5316 11:13:00.468922 RX Vref 0 -> 0, step: 1
5317 11:13:00.468991
5318 11:13:00.472602 RX Delay -61 -> 252, step: 4
5319 11:13:00.472698
5320 11:13:00.475776 Set Vref, RX VrefLevel [Byte0]: 55
5321 11:13:00.479381 [Byte1]: 50
5322 11:13:00.482316
5323 11:13:00.482426 Final RX Vref Byte 0 = 55 to rank0
5324 11:13:00.485397 Final RX Vref Byte 1 = 50 to rank0
5325 11:13:00.488917 Final RX Vref Byte 0 = 55 to rank1
5326 11:13:00.492112 Final RX Vref Byte 1 = 50 to rank1==
5327 11:13:00.495483 Dram Type= 6, Freq= 0, CH_0, rank 0
5328 11:13:00.498747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 11:13:00.502002 ==
5330 11:13:00.502104 DQS Delay:
5331 11:13:00.502195 DQS0 = 0, DQS1 = 0
5332 11:13:00.505908 DQM Delay:
5333 11:13:00.506005 DQM0 = 96, DQM1 = 87
5334 11:13:00.509034 DQ Delay:
5335 11:13:00.512263 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5336 11:13:00.512337 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5337 11:13:00.516129 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =80
5338 11:13:00.522260 DQ12 =92, DQ13 =90, DQ14 =100, DQ15 =96
5339 11:13:00.522344
5340 11:13:00.522409
5341 11:13:00.528734 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5342 11:13:00.532587 CH0 RK0: MR19=504, MR18=10FB
5343 11:13:00.539082 CH0_RK0: MR19=0x504, MR18=0x10FB, DQSOSC=416, MR23=63, INC=62, DEC=41
5344 11:13:00.539168
5345 11:13:00.542557 ----->DramcWriteLeveling(PI) begin...
5346 11:13:00.542674 ==
5347 11:13:00.545832 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 11:13:00.549302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 11:13:00.549405 ==
5350 11:13:00.551768 Write leveling (Byte 0): 31 => 31
5351 11:13:00.555772 Write leveling (Byte 1): 30 => 30
5352 11:13:00.558689 DramcWriteLeveling(PI) end<-----
5353 11:13:00.558788
5354 11:13:00.558884 ==
5355 11:13:00.561959 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 11:13:00.565229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 11:13:00.565302 ==
5358 11:13:00.568499 [Gating] SW mode calibration
5359 11:13:00.575303 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5360 11:13:00.581940 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5361 11:13:00.585138 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5362 11:13:00.591728 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 11:13:00.594778 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 11:13:00.598623 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 11:13:00.605322 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 11:13:00.608418 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 11:13:00.611658 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5368 11:13:00.618722 0 14 28 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)
5369 11:13:00.621795 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5370 11:13:00.624951 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5371 11:13:00.628148 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 11:13:00.634579 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 11:13:00.637968 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 11:13:00.641256 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 11:13:00.648426 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 11:13:00.651706 0 15 28 | B1->B0 | 2424 2f2f | 0 1 | (1 1) (0 0)
5377 11:13:00.654944 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5378 11:13:00.661424 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 11:13:00.664615 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 11:13:00.667898 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 11:13:00.674638 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 11:13:00.677661 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 11:13:00.681495 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 11:13:00.688155 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5385 11:13:00.691084 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5386 11:13:00.694713 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5387 11:13:00.701487 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:13:00.704428 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 11:13:00.707618 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 11:13:00.714118 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 11:13:00.717966 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:13:00.721286 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 11:13:00.727702 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:13:00.730748 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:13:00.734114 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:13:00.741173 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:13:00.744628 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:13:00.747928 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:13:00.754484 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:13:00.757721 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5401 11:13:00.760961 Total UI for P1: 0, mck2ui 16
5402 11:13:00.764337 best dqsien dly found for B0: ( 1, 2, 26)
5403 11:13:00.767480 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5404 11:13:00.770776 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 11:13:00.774021 Total UI for P1: 0, mck2ui 16
5406 11:13:00.777893 best dqsien dly found for B1: ( 1, 3, 0)
5407 11:13:00.781134 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5408 11:13:00.787719 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5409 11:13:00.787804
5410 11:13:00.790834 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5411 11:13:00.793911 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5412 11:13:00.797519 [Gating] SW calibration Done
5413 11:13:00.797606 ==
5414 11:13:00.800675 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 11:13:00.804268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 11:13:00.804385 ==
5417 11:13:00.804482 RX Vref Scan: 0
5418 11:13:00.807341
5419 11:13:00.807464 RX Vref 0 -> 0, step: 1
5420 11:13:00.807582
5421 11:13:00.811001 RX Delay -80 -> 252, step: 8
5422 11:13:00.814295 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5423 11:13:00.817511 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5424 11:13:00.823863 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5425 11:13:00.827089 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5426 11:13:00.830353 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5427 11:13:00.834029 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5428 11:13:00.837245 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5429 11:13:00.840384 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5430 11:13:00.847616 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5431 11:13:00.850973 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5432 11:13:00.854115 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5433 11:13:00.857445 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5434 11:13:00.860675 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5435 11:13:00.863838 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5436 11:13:00.870793 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5437 11:13:00.874124 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5438 11:13:00.874198 ==
5439 11:13:00.877489 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 11:13:00.880773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 11:13:00.880888 ==
5442 11:13:00.884049 DQS Delay:
5443 11:13:00.884176 DQS0 = 0, DQS1 = 0
5444 11:13:00.884269 DQM Delay:
5445 11:13:00.887252 DQM0 = 97, DQM1 = 87
5446 11:13:00.887369 DQ Delay:
5447 11:13:00.890480 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5448 11:13:00.893526 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =107
5449 11:13:00.897157 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5450 11:13:00.900282 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5451 11:13:00.900366
5452 11:13:00.900478
5453 11:13:00.900571 ==
5454 11:13:00.903825 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 11:13:00.910040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 11:13:00.910127 ==
5457 11:13:00.910194
5458 11:13:00.910257
5459 11:13:00.910317 TX Vref Scan disable
5460 11:13:00.913688 == TX Byte 0 ==
5461 11:13:00.917453 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5462 11:13:00.923570 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5463 11:13:00.923656 == TX Byte 1 ==
5464 11:13:00.926806 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5465 11:13:00.933918 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5466 11:13:00.933999 ==
5467 11:13:00.937135 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 11:13:00.940209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 11:13:00.940292 ==
5470 11:13:00.940364
5471 11:13:00.940464
5472 11:13:00.943439 TX Vref Scan disable
5473 11:13:00.943509 == TX Byte 0 ==
5474 11:13:00.950473 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5475 11:13:00.953678 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5476 11:13:00.953757 == TX Byte 1 ==
5477 11:13:00.960210 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5478 11:13:00.963438 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5479 11:13:00.963538
5480 11:13:00.963630 [DATLAT]
5481 11:13:00.966635 Freq=933, CH0 RK1
5482 11:13:00.966710
5483 11:13:00.966772 DATLAT Default: 0xb
5484 11:13:00.969872 0, 0xFFFF, sum = 0
5485 11:13:00.969944 1, 0xFFFF, sum = 0
5486 11:13:00.973717 2, 0xFFFF, sum = 0
5487 11:13:00.973823 3, 0xFFFF, sum = 0
5488 11:13:00.977010 4, 0xFFFF, sum = 0
5489 11:13:00.977083 5, 0xFFFF, sum = 0
5490 11:13:00.980307 6, 0xFFFF, sum = 0
5491 11:13:00.983683 7, 0xFFFF, sum = 0
5492 11:13:00.983756 8, 0xFFFF, sum = 0
5493 11:13:00.986777 9, 0xFFFF, sum = 0
5494 11:13:00.986847 10, 0x0, sum = 1
5495 11:13:00.986908 11, 0x0, sum = 2
5496 11:13:00.990168 12, 0x0, sum = 3
5497 11:13:00.990283 13, 0x0, sum = 4
5498 11:13:00.993345 best_step = 11
5499 11:13:00.993459
5500 11:13:00.993562 ==
5501 11:13:00.996688 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 11:13:01.000348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 11:13:01.000469 ==
5504 11:13:01.003381 RX Vref Scan: 0
5505 11:13:01.003494
5506 11:13:01.003607 RX Vref 0 -> 0, step: 1
5507 11:13:01.003703
5508 11:13:01.006441 RX Delay -61 -> 252, step: 4
5509 11:13:01.014497 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5510 11:13:01.017530 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5511 11:13:01.020548 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5512 11:13:01.024066 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5513 11:13:01.027534 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5514 11:13:01.030665 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5515 11:13:01.037108 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5516 11:13:01.040357 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5517 11:13:01.044129 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5518 11:13:01.047407 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5519 11:13:01.050637 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5520 11:13:01.057306 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5521 11:13:01.060485 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5522 11:13:01.063741 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5523 11:13:01.066968 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5524 11:13:01.070307 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5525 11:13:01.070406 ==
5526 11:13:01.073581 Dram Type= 6, Freq= 0, CH_0, rank 1
5527 11:13:01.080034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 11:13:01.080170 ==
5529 11:13:01.080326 DQS Delay:
5530 11:13:01.083316 DQS0 = 0, DQS1 = 0
5531 11:13:01.083459 DQM Delay:
5532 11:13:01.083566 DQM0 = 95, DQM1 = 87
5533 11:13:01.087205 DQ Delay:
5534 11:13:01.090507 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5535 11:13:01.093696 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =102
5536 11:13:01.096914 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =78
5537 11:13:01.100352 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =96
5538 11:13:01.100463
5539 11:13:01.100565
5540 11:13:01.106511 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5541 11:13:01.110344 CH0 RK1: MR19=505, MR18=1B09
5542 11:13:01.116453 CH0_RK1: MR19=0x505, MR18=0x1B09, DQSOSC=413, MR23=63, INC=63, DEC=42
5543 11:13:01.120115 [RxdqsGatingPostProcess] freq 933
5544 11:13:01.123183 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5545 11:13:01.126736 best DQS0 dly(2T, 0.5T) = (0, 11)
5546 11:13:01.129656 best DQS1 dly(2T, 0.5T) = (0, 11)
5547 11:13:01.133277 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5548 11:13:01.136364 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5549 11:13:01.140217 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 11:13:01.143478 best DQS1 dly(2T, 0.5T) = (0, 11)
5551 11:13:01.146389 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 11:13:01.150237 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5553 11:13:01.152840 Pre-setting of DQS Precalculation
5554 11:13:01.156817 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5555 11:13:01.159969 ==
5556 11:13:01.160049 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 11:13:01.166508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 11:13:01.166615 ==
5559 11:13:01.169601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5560 11:13:01.176041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5561 11:13:01.179914 [CA 0] Center 37 (7~67) winsize 61
5562 11:13:01.183293 [CA 1] Center 36 (6~67) winsize 62
5563 11:13:01.186595 [CA 2] Center 34 (4~64) winsize 61
5564 11:13:01.189762 [CA 3] Center 33 (3~64) winsize 62
5565 11:13:01.193040 [CA 4] Center 34 (3~65) winsize 63
5566 11:13:01.196265 [CA 5] Center 33 (3~63) winsize 61
5567 11:13:01.196374
5568 11:13:01.200210 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5569 11:13:01.200317
5570 11:13:01.203542 [CATrainingPosCal] consider 1 rank data
5571 11:13:01.206709 u2DelayCellTimex100 = 270/100 ps
5572 11:13:01.210060 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5573 11:13:01.213207 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5574 11:13:01.219382 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5575 11:13:01.222996 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5576 11:13:01.226733 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5577 11:13:01.229711 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5578 11:13:01.229816
5579 11:13:01.232990 CA PerBit enable=1, Macro0, CA PI delay=33
5580 11:13:01.233097
5581 11:13:01.236488 [CBTSetCACLKResult] CA Dly = 33
5582 11:13:01.236587 CS Dly: 4 (0~35)
5583 11:13:01.239466 ==
5584 11:13:01.239567 Dram Type= 6, Freq= 0, CH_1, rank 1
5585 11:13:01.246241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 11:13:01.246349 ==
5587 11:13:01.249519 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5588 11:13:01.256439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5589 11:13:01.259746 [CA 0] Center 36 (6~67) winsize 62
5590 11:13:01.263083 [CA 1] Center 37 (7~67) winsize 61
5591 11:13:01.266194 [CA 2] Center 34 (4~64) winsize 61
5592 11:13:01.270079 [CA 3] Center 33 (3~64) winsize 62
5593 11:13:01.273481 [CA 4] Center 34 (4~65) winsize 62
5594 11:13:01.276591 [CA 5] Center 32 (2~63) winsize 62
5595 11:13:01.276669
5596 11:13:01.279601 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5597 11:13:01.279679
5598 11:13:01.282907 [CATrainingPosCal] consider 2 rank data
5599 11:13:01.286134 u2DelayCellTimex100 = 270/100 ps
5600 11:13:01.289581 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5601 11:13:01.296115 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5602 11:13:01.299342 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5603 11:13:01.303533 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5604 11:13:01.306505 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5605 11:13:01.309832 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5606 11:13:01.309935
5607 11:13:01.313132 CA PerBit enable=1, Macro0, CA PI delay=33
5608 11:13:01.313232
5609 11:13:01.316521 [CBTSetCACLKResult] CA Dly = 33
5610 11:13:01.316622 CS Dly: 5 (0~37)
5611 11:13:01.316714
5612 11:13:01.319648 ----->DramcWriteLeveling(PI) begin...
5613 11:13:01.322667 ==
5614 11:13:01.326334 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 11:13:01.329432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 11:13:01.329532 ==
5617 11:13:01.332938 Write leveling (Byte 0): 25 => 25
5618 11:13:01.336058 Write leveling (Byte 1): 28 => 28
5619 11:13:01.339233 DramcWriteLeveling(PI) end<-----
5620 11:13:01.339336
5621 11:13:01.339416 ==
5622 11:13:01.342769 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 11:13:01.346393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 11:13:01.346468 ==
5625 11:13:01.349284 [Gating] SW mode calibration
5626 11:13:01.356325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5627 11:13:01.362958 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5628 11:13:01.366133 0 14 0 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
5629 11:13:01.369275 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 11:13:01.375736 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 11:13:01.379735 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5632 11:13:01.382902 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 11:13:01.386192 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 11:13:01.392713 0 14 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5635 11:13:01.396027 0 14 28 | B1->B0 | 3131 3333 | 1 1 | (1 0) (1 0)
5636 11:13:01.399788 0 15 0 | B1->B0 | 2424 2828 | 0 0 | (1 0) (0 0)
5637 11:13:01.406349 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5638 11:13:01.409548 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 11:13:01.412912 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 11:13:01.419438 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 11:13:01.422777 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 11:13:01.425815 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 11:13:01.432593 0 15 28 | B1->B0 | 3131 2c2c | 1 0 | (0 0) (0 0)
5644 11:13:01.435686 1 0 0 | B1->B0 | 4444 4141 | 0 1 | (0 0) (0 0)
5645 11:13:01.439329 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 11:13:01.445997 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 11:13:01.449400 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 11:13:01.452373 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 11:13:01.459370 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 11:13:01.462546 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 11:13:01.465626 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5652 11:13:01.472080 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:13:01.476061 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 11:13:01.479177 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 11:13:01.485758 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:13:01.488892 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:13:01.492178 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 11:13:01.498716 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:13:01.501995 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:13:01.505826 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:13:01.512371 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 11:13:01.515669 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 11:13:01.518889 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:13:01.525533 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:13:01.528815 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:13:01.532126 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:13:01.535660 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5668 11:13:01.538734 Total UI for P1: 0, mck2ui 16
5669 11:13:01.541916 best dqsien dly found for B1: ( 1, 2, 26)
5670 11:13:01.548702 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 11:13:01.552281 Total UI for P1: 0, mck2ui 16
5672 11:13:01.555489 best dqsien dly found for B0: ( 1, 2, 28)
5673 11:13:01.558368 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5674 11:13:01.561990 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5675 11:13:01.562075
5676 11:13:01.565510 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5677 11:13:01.568654 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5678 11:13:01.571728 [Gating] SW calibration Done
5679 11:13:01.571810 ==
5680 11:13:01.575577 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 11:13:01.578810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 11:13:01.578893 ==
5683 11:13:01.582137 RX Vref Scan: 0
5684 11:13:01.582221
5685 11:13:01.582286 RX Vref 0 -> 0, step: 1
5686 11:13:01.585235
5687 11:13:01.585322 RX Delay -80 -> 252, step: 8
5688 11:13:01.591884 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5689 11:13:01.595072 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5690 11:13:01.598341 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5691 11:13:01.602204 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5692 11:13:01.604865 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5693 11:13:01.608780 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5694 11:13:01.615185 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5695 11:13:01.618529 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5696 11:13:01.621838 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5697 11:13:01.625201 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5698 11:13:01.628381 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5699 11:13:01.634945 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5700 11:13:01.638149 iDelay=200, Bit 12, Center 99 (0 ~ 199) 200
5701 11:13:01.641629 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5702 11:13:01.644647 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5703 11:13:01.648222 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5704 11:13:01.648334 ==
5705 11:13:01.651302 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 11:13:01.657900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 11:13:01.658013 ==
5708 11:13:01.658111 DQS Delay:
5709 11:13:01.658206 DQS0 = 0, DQS1 = 0
5710 11:13:01.661645 DQM Delay:
5711 11:13:01.661752 DQM0 = 95, DQM1 = 89
5712 11:13:01.664705 DQ Delay:
5713 11:13:01.667855 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =95
5714 11:13:01.671555 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5715 11:13:01.674627 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5716 11:13:01.677759 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5717 11:13:01.677865
5718 11:13:01.677985
5719 11:13:01.678088 ==
5720 11:13:01.681457 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 11:13:01.684603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 11:13:01.684710 ==
5723 11:13:01.684809
5724 11:13:01.684901
5725 11:13:01.687880 TX Vref Scan disable
5726 11:13:01.687988 == TX Byte 0 ==
5727 11:13:01.694410 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5728 11:13:01.697733 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5729 11:13:01.697842 == TX Byte 1 ==
5730 11:13:01.704292 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5731 11:13:01.707724 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5732 11:13:01.707843 ==
5733 11:13:01.710851 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 11:13:01.714653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 11:13:01.714773 ==
5736 11:13:01.714872
5737 11:13:01.717913
5738 11:13:01.718020 TX Vref Scan disable
5739 11:13:01.721177 == TX Byte 0 ==
5740 11:13:01.724477 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5741 11:13:01.727698 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5742 11:13:01.730957 == TX Byte 1 ==
5743 11:13:01.734240 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5744 11:13:01.737476 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5745 11:13:01.740989
5746 11:13:01.741099 [DATLAT]
5747 11:13:01.741196 Freq=933, CH1 RK0
5748 11:13:01.741288
5749 11:13:01.744663 DATLAT Default: 0xd
5750 11:13:01.744782 0, 0xFFFF, sum = 0
5751 11:13:01.747701 1, 0xFFFF, sum = 0
5752 11:13:01.747827 2, 0xFFFF, sum = 0
5753 11:13:01.751420 3, 0xFFFF, sum = 0
5754 11:13:01.751504 4, 0xFFFF, sum = 0
5755 11:13:01.754400 5, 0xFFFF, sum = 0
5756 11:13:01.754482 6, 0xFFFF, sum = 0
5757 11:13:01.757511 7, 0xFFFF, sum = 0
5758 11:13:01.757599 8, 0xFFFF, sum = 0
5759 11:13:01.761354 9, 0xFFFF, sum = 0
5760 11:13:01.761440 10, 0x0, sum = 1
5761 11:13:01.764180 11, 0x0, sum = 2
5762 11:13:01.764294 12, 0x0, sum = 3
5763 11:13:01.767860 13, 0x0, sum = 4
5764 11:13:01.767946 best_step = 11
5765 11:13:01.768012
5766 11:13:01.768074 ==
5767 11:13:01.771366 Dram Type= 6, Freq= 0, CH_1, rank 0
5768 11:13:01.777961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 11:13:01.778049 ==
5770 11:13:01.778117 RX Vref Scan: 1
5771 11:13:01.778179
5772 11:13:01.780984 RX Vref 0 -> 0, step: 1
5773 11:13:01.781059
5774 11:13:01.784045 RX Delay -61 -> 252, step: 4
5775 11:13:01.784130
5776 11:13:01.787828 Set Vref, RX VrefLevel [Byte0]: 59
5777 11:13:01.791362 [Byte1]: 52
5778 11:13:01.791447
5779 11:13:01.794512 Final RX Vref Byte 0 = 59 to rank0
5780 11:13:01.797883 Final RX Vref Byte 1 = 52 to rank0
5781 11:13:01.801212 Final RX Vref Byte 0 = 59 to rank1
5782 11:13:01.804523 Final RX Vref Byte 1 = 52 to rank1==
5783 11:13:01.807632 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 11:13:01.810906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 11:13:01.811005 ==
5786 11:13:01.814168 DQS Delay:
5787 11:13:01.814266 DQS0 = 0, DQS1 = 0
5788 11:13:01.817285 DQM Delay:
5789 11:13:01.817375 DQM0 = 97, DQM1 = 90
5790 11:13:01.817442 DQ Delay:
5791 11:13:01.821279 DQ0 =100, DQ1 =90, DQ2 =88, DQ3 =96
5792 11:13:01.824598 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =94
5793 11:13:01.827754 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =88
5794 11:13:01.830989 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =96
5795 11:13:01.831063
5796 11:13:01.831128
5797 11:13:01.841422 [DQSOSCAuto] RK0, (LSB)MR18= 0x14f1, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5798 11:13:01.844621 CH1 RK0: MR19=504, MR18=14F1
5799 11:13:01.847855 CH1_RK0: MR19=0x504, MR18=0x14F1, DQSOSC=415, MR23=63, INC=62, DEC=41
5800 11:13:01.847936
5801 11:13:01.851159 ----->DramcWriteLeveling(PI) begin...
5802 11:13:01.854185 ==
5803 11:13:01.857763 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 11:13:01.861434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 11:13:01.861513 ==
5806 11:13:01.864343 Write leveling (Byte 0): 31 => 31
5807 11:13:01.867384 Write leveling (Byte 1): 31 => 31
5808 11:13:01.870955 DramcWriteLeveling(PI) end<-----
5809 11:13:01.871035
5810 11:13:01.871099 ==
5811 11:13:01.874001 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 11:13:01.877766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 11:13:01.877841 ==
5814 11:13:01.880864 [Gating] SW mode calibration
5815 11:13:01.887317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5816 11:13:01.894187 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5817 11:13:01.897267 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 11:13:01.901103 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5819 11:13:01.907662 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 11:13:01.910827 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5821 11:13:01.914122 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 11:13:01.920572 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 11:13:01.923812 0 14 24 | B1->B0 | 3131 2e2e | 1 1 | (1 1) (1 0)
5824 11:13:01.927095 0 14 28 | B1->B0 | 2e2e 2424 | 0 0 | (1 0) (0 0)
5825 11:13:01.933608 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 11:13:01.936942 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 11:13:01.940854 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 11:13:01.947535 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 11:13:01.950841 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 11:13:01.954134 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5831 11:13:01.957388 0 15 24 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
5832 11:13:01.963651 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5833 11:13:01.967393 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 11:13:01.970400 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 11:13:01.977058 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 11:13:01.980587 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 11:13:01.983612 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 11:13:01.990170 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5839 11:13:01.993887 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 11:13:01.996969 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5841 11:13:02.003412 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 11:13:02.006669 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 11:13:02.010692 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 11:13:02.017132 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 11:13:02.020434 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 11:13:02.023651 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 11:13:02.030276 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:13:02.033475 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:13:02.036711 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:13:02.043323 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:13:02.046741 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 11:13:02.050005 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:13:02.057089 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:13:02.060341 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5855 11:13:02.063658 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5856 11:13:02.070196 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 11:13:02.070275 Total UI for P1: 0, mck2ui 16
5858 11:13:02.076891 best dqsien dly found for B0: ( 1, 2, 22)
5859 11:13:02.076970 Total UI for P1: 0, mck2ui 16
5860 11:13:02.079978 best dqsien dly found for B1: ( 1, 2, 24)
5861 11:13:02.086737 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5862 11:13:02.089818 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5863 11:13:02.089902
5864 11:13:02.093557 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5865 11:13:02.096516 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5866 11:13:02.100262 [Gating] SW calibration Done
5867 11:13:02.100347 ==
5868 11:13:02.103233 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 11:13:02.106860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 11:13:02.106945 ==
5871 11:13:02.109896 RX Vref Scan: 0
5872 11:13:02.109979
5873 11:13:02.110044 RX Vref 0 -> 0, step: 1
5874 11:13:02.110107
5875 11:13:02.113038 RX Delay -80 -> 252, step: 8
5876 11:13:02.116331 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5877 11:13:02.120099 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5878 11:13:02.126670 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5879 11:13:02.129998 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5880 11:13:02.133309 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5881 11:13:02.136519 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5882 11:13:02.139678 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5883 11:13:02.142932 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5884 11:13:02.150042 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5885 11:13:02.153345 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5886 11:13:02.156573 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5887 11:13:02.159880 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5888 11:13:02.163061 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5889 11:13:02.170026 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5890 11:13:02.173405 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5891 11:13:02.176463 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5892 11:13:02.176547 ==
5893 11:13:02.179692 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 11:13:02.183304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 11:13:02.183425 ==
5896 11:13:02.186333 DQS Delay:
5897 11:13:02.186416 DQS0 = 0, DQS1 = 0
5898 11:13:02.186481 DQM Delay:
5899 11:13:02.189903 DQM0 = 94, DQM1 = 88
5900 11:13:02.189986 DQ Delay:
5901 11:13:02.193072 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5902 11:13:02.196594 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5903 11:13:02.199581 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5904 11:13:02.203287 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5905 11:13:02.203406
5906 11:13:02.203472
5907 11:13:02.203533 ==
5908 11:13:02.206288 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 11:13:02.212794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 11:13:02.212878 ==
5911 11:13:02.212944
5912 11:13:02.213006
5913 11:13:02.213065 TX Vref Scan disable
5914 11:13:02.216372 == TX Byte 0 ==
5915 11:13:02.219905 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5916 11:13:02.223544 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5917 11:13:02.226376 == TX Byte 1 ==
5918 11:13:02.229745 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5919 11:13:02.236409 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5920 11:13:02.236493 ==
5921 11:13:02.239702 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 11:13:02.243073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 11:13:02.243163 ==
5924 11:13:02.243234
5925 11:13:02.243299
5926 11:13:02.246356 TX Vref Scan disable
5927 11:13:02.246455 == TX Byte 0 ==
5928 11:13:02.252895 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5929 11:13:02.256125 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5930 11:13:02.256245 == TX Byte 1 ==
5931 11:13:02.263155 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5932 11:13:02.266452 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5933 11:13:02.266537
5934 11:13:02.266604 [DATLAT]
5935 11:13:02.269507 Freq=933, CH1 RK1
5936 11:13:02.269591
5937 11:13:02.269664 DATLAT Default: 0xb
5938 11:13:02.272872 0, 0xFFFF, sum = 0
5939 11:13:02.272945 1, 0xFFFF, sum = 0
5940 11:13:02.276344 2, 0xFFFF, sum = 0
5941 11:13:02.276417 3, 0xFFFF, sum = 0
5942 11:13:02.279315 4, 0xFFFF, sum = 0
5943 11:13:02.282649 5, 0xFFFF, sum = 0
5944 11:13:02.282725 6, 0xFFFF, sum = 0
5945 11:13:02.285924 7, 0xFFFF, sum = 0
5946 11:13:02.285999 8, 0xFFFF, sum = 0
5947 11:13:02.289642 9, 0xFFFF, sum = 0
5948 11:13:02.289730 10, 0x0, sum = 1
5949 11:13:02.292682 11, 0x0, sum = 2
5950 11:13:02.292761 12, 0x0, sum = 3
5951 11:13:02.292845 13, 0x0, sum = 4
5952 11:13:02.296247 best_step = 11
5953 11:13:02.296322
5954 11:13:02.296387 ==
5955 11:13:02.299354 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 11:13:02.302527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 11:13:02.302614 ==
5958 11:13:02.306220 RX Vref Scan: 0
5959 11:13:02.306295
5960 11:13:02.306372 RX Vref 0 -> 0, step: 1
5961 11:13:02.309214
5962 11:13:02.309310 RX Delay -61 -> 252, step: 4
5963 11:13:02.317286 iDelay=195, Bit 0, Center 96 (3 ~ 190) 188
5964 11:13:02.320415 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5965 11:13:02.323341 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5966 11:13:02.326587 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5967 11:13:02.330356 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5968 11:13:02.333602 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5969 11:13:02.340120 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5970 11:13:02.343222 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5971 11:13:02.346565 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5972 11:13:02.350018 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
5973 11:13:02.353445 iDelay=195, Bit 10, Center 92 (-1 ~ 186) 188
5974 11:13:02.359881 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5975 11:13:02.363091 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5976 11:13:02.366518 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5977 11:13:02.369629 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5978 11:13:02.372908 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5979 11:13:02.372993 ==
5980 11:13:02.376222 Dram Type= 6, Freq= 0, CH_1, rank 1
5981 11:13:02.382777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5982 11:13:02.382867 ==
5983 11:13:02.382953 DQS Delay:
5984 11:13:02.386019 DQS0 = 0, DQS1 = 0
5985 11:13:02.386104 DQM Delay:
5986 11:13:02.386188 DQM0 = 94, DQM1 = 90
5987 11:13:02.389336 DQ Delay:
5988 11:13:02.392602 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =94
5989 11:13:02.395818 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =90
5990 11:13:02.399583 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5991 11:13:02.402493 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
5992 11:13:02.402609
5993 11:13:02.402691
5994 11:13:02.409231 [DQSOSCAuto] RK1, (LSB)MR18= 0x111a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5995 11:13:02.412477 CH1 RK1: MR19=505, MR18=111A
5996 11:13:02.419648 CH1_RK1: MR19=0x505, MR18=0x111A, DQSOSC=413, MR23=63, INC=63, DEC=42
5997 11:13:02.422767 [RxdqsGatingPostProcess] freq 933
5998 11:13:02.425773 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5999 11:13:02.429431 best DQS0 dly(2T, 0.5T) = (0, 10)
6000 11:13:02.432696 best DQS1 dly(2T, 0.5T) = (0, 10)
6001 11:13:02.435795 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6002 11:13:02.439177 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6003 11:13:02.442389 best DQS0 dly(2T, 0.5T) = (0, 10)
6004 11:13:02.445653 best DQS1 dly(2T, 0.5T) = (0, 10)
6005 11:13:02.448925 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6006 11:13:02.452907 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6007 11:13:02.456172 Pre-setting of DQS Precalculation
6008 11:13:02.459488 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6009 11:13:02.469401 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6010 11:13:02.475823 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6011 11:13:02.475906
6012 11:13:02.475971
6013 11:13:02.479162 [Calibration Summary] 1866 Mbps
6014 11:13:02.479245 CH 0, Rank 0
6015 11:13:02.482519 SW Impedance : PASS
6016 11:13:02.482608 DUTY Scan : NO K
6017 11:13:02.485680 ZQ Calibration : PASS
6018 11:13:02.489220 Jitter Meter : NO K
6019 11:13:02.489300 CBT Training : PASS
6020 11:13:02.492217 Write leveling : PASS
6021 11:13:02.495533 RX DQS gating : PASS
6022 11:13:02.495609 RX DQ/DQS(RDDQC) : PASS
6023 11:13:02.498894 TX DQ/DQS : PASS
6024 11:13:02.502160 RX DATLAT : PASS
6025 11:13:02.502237 RX DQ/DQS(Engine): PASS
6026 11:13:02.505207 TX OE : NO K
6027 11:13:02.505283 All Pass.
6028 11:13:02.505346
6029 11:13:02.508964 CH 0, Rank 1
6030 11:13:02.509038 SW Impedance : PASS
6031 11:13:02.511990 DUTY Scan : NO K
6032 11:13:02.515734 ZQ Calibration : PASS
6033 11:13:02.515809 Jitter Meter : NO K
6034 11:13:02.518730 CBT Training : PASS
6035 11:13:02.521869 Write leveling : PASS
6036 11:13:02.521945 RX DQS gating : PASS
6037 11:13:02.525475 RX DQ/DQS(RDDQC) : PASS
6038 11:13:02.525552 TX DQ/DQS : PASS
6039 11:13:02.528589 RX DATLAT : PASS
6040 11:13:02.532164 RX DQ/DQS(Engine): PASS
6041 11:13:02.532247 TX OE : NO K
6042 11:13:02.535214 All Pass.
6043 11:13:02.535295
6044 11:13:02.535386 CH 1, Rank 0
6045 11:13:02.538972 SW Impedance : PASS
6046 11:13:02.539055 DUTY Scan : NO K
6047 11:13:02.542128 ZQ Calibration : PASS
6048 11:13:02.545426 Jitter Meter : NO K
6049 11:13:02.545504 CBT Training : PASS
6050 11:13:02.548705 Write leveling : PASS
6051 11:13:02.552021 RX DQS gating : PASS
6052 11:13:02.552097 RX DQ/DQS(RDDQC) : PASS
6053 11:13:02.555212 TX DQ/DQS : PASS
6054 11:13:02.558458 RX DATLAT : PASS
6055 11:13:02.558552 RX DQ/DQS(Engine): PASS
6056 11:13:02.561782 TX OE : NO K
6057 11:13:02.561865 All Pass.
6058 11:13:02.561931
6059 11:13:02.565516 CH 1, Rank 1
6060 11:13:02.565599 SW Impedance : PASS
6061 11:13:02.568866 DUTY Scan : NO K
6062 11:13:02.572242 ZQ Calibration : PASS
6063 11:13:02.572325 Jitter Meter : NO K
6064 11:13:02.575356 CBT Training : PASS
6065 11:13:02.578599 Write leveling : PASS
6066 11:13:02.578682 RX DQS gating : PASS
6067 11:13:02.582112 RX DQ/DQS(RDDQC) : PASS
6068 11:13:02.582195 TX DQ/DQS : PASS
6069 11:13:02.585084 RX DATLAT : PASS
6070 11:13:02.588411 RX DQ/DQS(Engine): PASS
6071 11:13:02.588503 TX OE : NO K
6072 11:13:02.591715 All Pass.
6073 11:13:02.591797
6074 11:13:02.591862 DramC Write-DBI off
6075 11:13:02.594983 PER_BANK_REFRESH: Hybrid Mode
6076 11:13:02.598346 TX_TRACKING: ON
6077 11:13:02.604907 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6078 11:13:02.608089 [FAST_K] Save calibration result to emmc
6079 11:13:02.615097 dramc_set_vcore_voltage set vcore to 650000
6080 11:13:02.615181 Read voltage for 400, 6
6081 11:13:02.615246 Vio18 = 0
6082 11:13:02.618097 Vcore = 650000
6083 11:13:02.618179 Vdram = 0
6084 11:13:02.618245 Vddq = 0
6085 11:13:02.621724 Vmddr = 0
6086 11:13:02.624754 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6087 11:13:02.631566 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6088 11:13:02.634526 MEM_TYPE=3, freq_sel=20
6089 11:13:02.634605 sv_algorithm_assistance_LP4_800
6090 11:13:02.641182 ============ PULL DRAM RESETB DOWN ============
6091 11:13:02.644852 ========== PULL DRAM RESETB DOWN end =========
6092 11:13:02.647946 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6093 11:13:02.651440 ===================================
6094 11:13:02.654611 LPDDR4 DRAM CONFIGURATION
6095 11:13:02.657913 ===================================
6096 11:13:02.661033 EX_ROW_EN[0] = 0x0
6097 11:13:02.661105 EX_ROW_EN[1] = 0x0
6098 11:13:02.664290 LP4Y_EN = 0x0
6099 11:13:02.664366 WORK_FSP = 0x0
6100 11:13:02.668124 WL = 0x2
6101 11:13:02.668196 RL = 0x2
6102 11:13:02.671435 BL = 0x2
6103 11:13:02.671509 RPST = 0x0
6104 11:13:02.674591 RD_PRE = 0x0
6105 11:13:02.674664 WR_PRE = 0x1
6106 11:13:02.677853 WR_PST = 0x0
6107 11:13:02.677936 DBI_WR = 0x0
6108 11:13:02.680971 DBI_RD = 0x0
6109 11:13:02.681049 OTF = 0x1
6110 11:13:02.684249 ===================================
6111 11:13:02.688158 ===================================
6112 11:13:02.691387 ANA top config
6113 11:13:02.694593 ===================================
6114 11:13:02.697701 DLL_ASYNC_EN = 0
6115 11:13:02.697830 ALL_SLAVE_EN = 1
6116 11:13:02.701049 NEW_RANK_MODE = 1
6117 11:13:02.704380 DLL_IDLE_MODE = 1
6118 11:13:02.707466 LP45_APHY_COMB_EN = 1
6119 11:13:02.707548 TX_ODT_DIS = 1
6120 11:13:02.711302 NEW_8X_MODE = 1
6121 11:13:02.714672 ===================================
6122 11:13:02.717847 ===================================
6123 11:13:02.721324 data_rate = 800
6124 11:13:02.724435 CKR = 1
6125 11:13:02.727897 DQ_P2S_RATIO = 4
6126 11:13:02.730838 ===================================
6127 11:13:02.734611 CA_P2S_RATIO = 4
6128 11:13:02.734693 DQ_CA_OPEN = 0
6129 11:13:02.737672 DQ_SEMI_OPEN = 1
6130 11:13:02.741465 CA_SEMI_OPEN = 1
6131 11:13:02.744320 CA_FULL_RATE = 0
6132 11:13:02.747196 DQ_CKDIV4_EN = 0
6133 11:13:02.751048 CA_CKDIV4_EN = 1
6134 11:13:02.751181 CA_PREDIV_EN = 0
6135 11:13:02.754128 PH8_DLY = 0
6136 11:13:02.757477 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6137 11:13:02.760635 DQ_AAMCK_DIV = 0
6138 11:13:02.764163 CA_AAMCK_DIV = 0
6139 11:13:02.767086 CA_ADMCK_DIV = 4
6140 11:13:02.767168 DQ_TRACK_CA_EN = 0
6141 11:13:02.771021 CA_PICK = 800
6142 11:13:02.774393 CA_MCKIO = 400
6143 11:13:02.777576 MCKIO_SEMI = 400
6144 11:13:02.780743 PLL_FREQ = 3016
6145 11:13:02.784227 DQ_UI_PI_RATIO = 32
6146 11:13:02.787511 CA_UI_PI_RATIO = 32
6147 11:13:02.790776 ===================================
6148 11:13:02.793937 ===================================
6149 11:13:02.794020 memory_type:LPDDR4
6150 11:13:02.797735 GP_NUM : 10
6151 11:13:02.800973 SRAM_EN : 1
6152 11:13:02.801055 MD32_EN : 0
6153 11:13:02.804102 ===================================
6154 11:13:02.807361 [ANA_INIT] >>>>>>>>>>>>>>
6155 11:13:02.810706 <<<<<< [CONFIGURE PHASE]: ANA_TX
6156 11:13:02.813900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6157 11:13:02.817275 ===================================
6158 11:13:02.820763 data_rate = 800,PCW = 0X7400
6159 11:13:02.823948 ===================================
6160 11:13:02.826993 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6161 11:13:02.830840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6162 11:13:02.843881 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6163 11:13:02.847528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6164 11:13:02.850691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6165 11:13:02.853693 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6166 11:13:02.857399 [ANA_INIT] flow start
6167 11:13:02.857484 [ANA_INIT] PLL >>>>>>>>
6168 11:13:02.860334 [ANA_INIT] PLL <<<<<<<<
6169 11:13:02.863643 [ANA_INIT] MIDPI >>>>>>>>
6170 11:13:02.867659 [ANA_INIT] MIDPI <<<<<<<<
6171 11:13:02.867738 [ANA_INIT] DLL >>>>>>>>
6172 11:13:02.870776 [ANA_INIT] flow end
6173 11:13:02.874013 ============ LP4 DIFF to SE enter ============
6174 11:13:02.877386 ============ LP4 DIFF to SE exit ============
6175 11:13:02.880559 [ANA_INIT] <<<<<<<<<<<<<
6176 11:13:02.884178 [Flow] Enable top DCM control >>>>>
6177 11:13:02.887395 [Flow] Enable top DCM control <<<<<
6178 11:13:02.890467 Enable DLL master slave shuffle
6179 11:13:02.893834 ==============================================================
6180 11:13:02.897011 Gating Mode config
6181 11:13:02.903654 ==============================================================
6182 11:13:02.903741 Config description:
6183 11:13:02.914364 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6184 11:13:02.920640 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6185 11:13:02.927098 SELPH_MODE 0: By rank 1: By Phase
6186 11:13:02.930319 ==============================================================
6187 11:13:02.933628 GAT_TRACK_EN = 0
6188 11:13:02.936818 RX_GATING_MODE = 2
6189 11:13:02.940699 RX_GATING_TRACK_MODE = 2
6190 11:13:02.943768 SELPH_MODE = 1
6191 11:13:02.946804 PICG_EARLY_EN = 1
6192 11:13:02.950370 VALID_LAT_VALUE = 1
6193 11:13:02.954003 ==============================================================
6194 11:13:02.957041 Enter into Gating configuration >>>>
6195 11:13:02.960620 Exit from Gating configuration <<<<
6196 11:13:02.963744 Enter into DVFS_PRE_config >>>>>
6197 11:13:02.977190 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6198 11:13:02.980421 Exit from DVFS_PRE_config <<<<<
6199 11:13:02.983598 Enter into PICG configuration >>>>
6200 11:13:02.983701 Exit from PICG configuration <<<<
6201 11:13:02.987058 [RX_INPUT] configuration >>>>>
6202 11:13:02.990196 [RX_INPUT] configuration <<<<<
6203 11:13:02.996599 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6204 11:13:03.000801 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6205 11:13:03.007190 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6206 11:13:03.013581 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6207 11:13:03.020133 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6208 11:13:03.026572 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6209 11:13:03.029967 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6210 11:13:03.033626 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6211 11:13:03.036894 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6212 11:13:03.043545 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6213 11:13:03.046830 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6214 11:13:03.050358 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6215 11:13:03.053281 ===================================
6216 11:13:03.056814 LPDDR4 DRAM CONFIGURATION
6217 11:13:03.059865 ===================================
6218 11:13:03.063467 EX_ROW_EN[0] = 0x0
6219 11:13:03.063564 EX_ROW_EN[1] = 0x0
6220 11:13:03.066551 LP4Y_EN = 0x0
6221 11:13:03.066633 WORK_FSP = 0x0
6222 11:13:03.070239 WL = 0x2
6223 11:13:03.070323 RL = 0x2
6224 11:13:03.073395 BL = 0x2
6225 11:13:03.073478 RPST = 0x0
6226 11:13:03.076246 RD_PRE = 0x0
6227 11:13:03.076329 WR_PRE = 0x1
6228 11:13:03.080107 WR_PST = 0x0
6229 11:13:03.080190 DBI_WR = 0x0
6230 11:13:03.083354 DBI_RD = 0x0
6231 11:13:03.083451 OTF = 0x1
6232 11:13:03.086565 ===================================
6233 11:13:03.093147 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6234 11:13:03.096487 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6235 11:13:03.099813 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6236 11:13:03.103068 ===================================
6237 11:13:03.106323 LPDDR4 DRAM CONFIGURATION
6238 11:13:03.109586 ===================================
6239 11:13:03.112782 EX_ROW_EN[0] = 0x10
6240 11:13:03.112874 EX_ROW_EN[1] = 0x0
6241 11:13:03.116331 LP4Y_EN = 0x0
6242 11:13:03.116418 WORK_FSP = 0x0
6243 11:13:03.119977 WL = 0x2
6244 11:13:03.120062 RL = 0x2
6245 11:13:03.123237 BL = 0x2
6246 11:13:03.123315 RPST = 0x0
6247 11:13:03.126456 RD_PRE = 0x0
6248 11:13:03.126532 WR_PRE = 0x1
6249 11:13:03.129685 WR_PST = 0x0
6250 11:13:03.129761 DBI_WR = 0x0
6251 11:13:03.132781 DBI_RD = 0x0
6252 11:13:03.132859 OTF = 0x1
6253 11:13:03.136072 ===================================
6254 11:13:03.143128 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6255 11:13:03.147075 nWR fixed to 30
6256 11:13:03.150996 [ModeRegInit_LP4] CH0 RK0
6257 11:13:03.151076 [ModeRegInit_LP4] CH0 RK1
6258 11:13:03.154384 [ModeRegInit_LP4] CH1 RK0
6259 11:13:03.157416 [ModeRegInit_LP4] CH1 RK1
6260 11:13:03.157498 match AC timing 19
6261 11:13:03.163923 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6262 11:13:03.167001 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6263 11:13:03.170529 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6264 11:13:03.177202 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6265 11:13:03.180442 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6266 11:13:03.180521 ==
6267 11:13:03.184074 Dram Type= 6, Freq= 0, CH_0, rank 0
6268 11:13:03.187078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 11:13:03.187162 ==
6270 11:13:03.193750 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6271 11:13:03.200424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6272 11:13:03.203781 [CA 0] Center 36 (8~64) winsize 57
6273 11:13:03.207164 [CA 1] Center 36 (8~64) winsize 57
6274 11:13:03.210667 [CA 2] Center 36 (8~64) winsize 57
6275 11:13:03.210745 [CA 3] Center 36 (8~64) winsize 57
6276 11:13:03.213964 [CA 4] Center 36 (8~64) winsize 57
6277 11:13:03.217393 [CA 5] Center 36 (8~64) winsize 57
6278 11:13:03.217476
6279 11:13:03.223861 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6280 11:13:03.223945
6281 11:13:03.227152 [CATrainingPosCal] consider 1 rank data
6282 11:13:03.230337 u2DelayCellTimex100 = 270/100 ps
6283 11:13:03.233720 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 11:13:03.236990 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 11:13:03.240449 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 11:13:03.243607 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 11:13:03.246996 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 11:13:03.250174 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 11:13:03.250265
6290 11:13:03.253472 CA PerBit enable=1, Macro0, CA PI delay=36
6291 11:13:03.253562
6292 11:13:03.256685 [CBTSetCACLKResult] CA Dly = 36
6293 11:13:03.260101 CS Dly: 1 (0~32)
6294 11:13:03.260181 ==
6295 11:13:03.263731 Dram Type= 6, Freq= 0, CH_0, rank 1
6296 11:13:03.266878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 11:13:03.266959 ==
6298 11:13:03.273799 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6299 11:13:03.276738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6300 11:13:03.280353 [CA 0] Center 36 (8~64) winsize 57
6301 11:13:03.283272 [CA 1] Center 36 (8~64) winsize 57
6302 11:13:03.286665 [CA 2] Center 36 (8~64) winsize 57
6303 11:13:03.290120 [CA 3] Center 36 (8~64) winsize 57
6304 11:13:03.293671 [CA 4] Center 36 (8~64) winsize 57
6305 11:13:03.296539 [CA 5] Center 36 (8~64) winsize 57
6306 11:13:03.296622
6307 11:13:03.299858 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6308 11:13:03.299941
6309 11:13:03.303551 [CATrainingPosCal] consider 2 rank data
6310 11:13:03.306853 u2DelayCellTimex100 = 270/100 ps
6311 11:13:03.310057 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 11:13:03.313282 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 11:13:03.319767 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 11:13:03.323552 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 11:13:03.326818 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 11:13:03.329466 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 11:13:03.329573
6318 11:13:03.333350 CA PerBit enable=1, Macro0, CA PI delay=36
6319 11:13:03.333436
6320 11:13:03.336553 [CBTSetCACLKResult] CA Dly = 36
6321 11:13:03.336631 CS Dly: 1 (0~32)
6322 11:13:03.336696
6323 11:13:03.340015 ----->DramcWriteLeveling(PI) begin...
6324 11:13:03.343248 ==
6325 11:13:03.346497 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 11:13:03.349722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 11:13:03.349796 ==
6328 11:13:03.353010 Write leveling (Byte 0): 40 => 8
6329 11:13:03.356295 Write leveling (Byte 1): 32 => 0
6330 11:13:03.359491 DramcWriteLeveling(PI) end<-----
6331 11:13:03.359568
6332 11:13:03.359637 ==
6333 11:13:03.362656 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 11:13:03.366521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 11:13:03.366597 ==
6336 11:13:03.369419 [Gating] SW mode calibration
6337 11:13:03.375843 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6338 11:13:03.383036 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6339 11:13:03.386117 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6340 11:13:03.389272 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6341 11:13:03.392781 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 11:13:03.399058 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6343 11:13:03.402711 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 11:13:03.406392 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 11:13:03.412661 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 11:13:03.415883 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6347 11:13:03.419316 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6348 11:13:03.422475 Total UI for P1: 0, mck2ui 16
6349 11:13:03.425694 best dqsien dly found for B0: ( 0, 14, 24)
6350 11:13:03.429098 Total UI for P1: 0, mck2ui 16
6351 11:13:03.432195 best dqsien dly found for B1: ( 0, 14, 24)
6352 11:13:03.436127 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6353 11:13:03.442663 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6354 11:13:03.442744
6355 11:13:03.446126 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6356 11:13:03.449336 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6357 11:13:03.452681 [Gating] SW calibration Done
6358 11:13:03.452763 ==
6359 11:13:03.456026 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 11:13:03.459425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 11:13:03.459496 ==
6362 11:13:03.459556 RX Vref Scan: 0
6363 11:13:03.462684
6364 11:13:03.462753 RX Vref 0 -> 0, step: 1
6365 11:13:03.462812
6366 11:13:03.465909 RX Delay -410 -> 252, step: 16
6367 11:13:03.469098 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6368 11:13:03.475959 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6369 11:13:03.479425 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6370 11:13:03.482428 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6371 11:13:03.485449 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6372 11:13:03.492199 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6373 11:13:03.495444 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6374 11:13:03.498794 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6375 11:13:03.502366 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6376 11:13:03.508909 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6377 11:13:03.512050 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6378 11:13:03.515681 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6379 11:13:03.518964 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6380 11:13:03.525497 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6381 11:13:03.528625 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6382 11:13:03.531871 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6383 11:13:03.531951 ==
6384 11:13:03.535398 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 11:13:03.541841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 11:13:03.541924 ==
6387 11:13:03.541990 DQS Delay:
6388 11:13:03.545087 DQS0 = 35, DQS1 = 51
6389 11:13:03.545170 DQM Delay:
6390 11:13:03.545234 DQM0 = 8, DQM1 = 11
6391 11:13:03.548457 DQ Delay:
6392 11:13:03.552367 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6393 11:13:03.552449 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6394 11:13:03.555155 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6395 11:13:03.559016 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6396 11:13:03.559100
6397 11:13:03.562155
6398 11:13:03.562237 ==
6399 11:13:03.565455 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 11:13:03.568709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 11:13:03.568793 ==
6402 11:13:03.568859
6403 11:13:03.568952
6404 11:13:03.571959 TX Vref Scan disable
6405 11:13:03.572045 == TX Byte 0 ==
6406 11:13:03.575136 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 11:13:03.581807 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 11:13:03.581907 == TX Byte 1 ==
6409 11:13:03.585236 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6410 11:13:03.592167 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6411 11:13:03.592276 ==
6412 11:13:03.595190 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 11:13:03.598422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 11:13:03.598533 ==
6415 11:13:03.598601
6416 11:13:03.598662
6417 11:13:03.601487 TX Vref Scan disable
6418 11:13:03.601575 == TX Byte 0 ==
6419 11:13:03.605308 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6420 11:13:03.612096 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6421 11:13:03.612184 == TX Byte 1 ==
6422 11:13:03.615051 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6423 11:13:03.621626 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6424 11:13:03.621730
6425 11:13:03.621826 [DATLAT]
6426 11:13:03.625010 Freq=400, CH0 RK0
6427 11:13:03.625105
6428 11:13:03.625196 DATLAT Default: 0xf
6429 11:13:03.628155 0, 0xFFFF, sum = 0
6430 11:13:03.628232 1, 0xFFFF, sum = 0
6431 11:13:03.631575 2, 0xFFFF, sum = 0
6432 11:13:03.631644 3, 0xFFFF, sum = 0
6433 11:13:03.634781 4, 0xFFFF, sum = 0
6434 11:13:03.634851 5, 0xFFFF, sum = 0
6435 11:13:03.638507 6, 0xFFFF, sum = 0
6436 11:13:03.638578 7, 0xFFFF, sum = 0
6437 11:13:03.641854 8, 0xFFFF, sum = 0
6438 11:13:03.641944 9, 0xFFFF, sum = 0
6439 11:13:03.645155 10, 0xFFFF, sum = 0
6440 11:13:03.645256 11, 0xFFFF, sum = 0
6441 11:13:03.648695 12, 0xFFFF, sum = 0
6442 11:13:03.648779 13, 0x0, sum = 1
6443 11:13:03.651662 14, 0x0, sum = 2
6444 11:13:03.651746 15, 0x0, sum = 3
6445 11:13:03.654960 16, 0x0, sum = 4
6446 11:13:03.655044 best_step = 14
6447 11:13:03.655109
6448 11:13:03.655169 ==
6449 11:13:03.658395 Dram Type= 6, Freq= 0, CH_0, rank 0
6450 11:13:03.665041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 11:13:03.665126 ==
6452 11:13:03.665191 RX Vref Scan: 1
6453 11:13:03.665253
6454 11:13:03.668325 RX Vref 0 -> 0, step: 1
6455 11:13:03.668409
6456 11:13:03.671712 RX Delay -343 -> 252, step: 8
6457 11:13:03.671835
6458 11:13:03.674829 Set Vref, RX VrefLevel [Byte0]: 55
6459 11:13:03.678021 [Byte1]: 50
6460 11:13:03.678122
6461 11:13:03.681255 Final RX Vref Byte 0 = 55 to rank0
6462 11:13:03.684677 Final RX Vref Byte 1 = 50 to rank0
6463 11:13:03.688453 Final RX Vref Byte 0 = 55 to rank1
6464 11:13:03.691744 Final RX Vref Byte 1 = 50 to rank1==
6465 11:13:03.695087 Dram Type= 6, Freq= 0, CH_0, rank 0
6466 11:13:03.698127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 11:13:03.701221 ==
6468 11:13:03.701332 DQS Delay:
6469 11:13:03.701428 DQS0 = 44, DQS1 = 60
6470 11:13:03.704916 DQM Delay:
6471 11:13:03.705038 DQM0 = 11, DQM1 = 16
6472 11:13:03.707948 DQ Delay:
6473 11:13:03.708027 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6474 11:13:03.711715 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6475 11:13:03.714655 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6476 11:13:03.718291 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6477 11:13:03.718392
6478 11:13:03.718489
6479 11:13:03.728251 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6480 11:13:03.731336 CH0 RK0: MR19=C0C, MR18=8B59
6481 11:13:03.738413 CH0_RK0: MR19=0xC0C, MR18=0x8B59, DQSOSC=392, MR23=63, INC=384, DEC=256
6482 11:13:03.738538 ==
6483 11:13:03.741462 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 11:13:03.744801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 11:13:03.744907 ==
6486 11:13:03.747967 [Gating] SW mode calibration
6487 11:13:03.754535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6488 11:13:03.758443 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6489 11:13:03.764936 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6490 11:13:03.767640 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6491 11:13:03.771585 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 11:13:03.777548 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 11:13:03.781325 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 11:13:03.784557 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 11:13:03.791582 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 11:13:03.794231 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6497 11:13:03.798151 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 11:13:03.801498 Total UI for P1: 0, mck2ui 16
6499 11:13:03.804519 best dqsien dly found for B0: ( 0, 14, 24)
6500 11:13:03.807523 Total UI for P1: 0, mck2ui 16
6501 11:13:03.810916 best dqsien dly found for B1: ( 0, 14, 24)
6502 11:13:03.814338 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6503 11:13:03.817553 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6504 11:13:03.817640
6505 11:13:03.824175 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6506 11:13:03.827913 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6507 11:13:03.830914 [Gating] SW calibration Done
6508 11:13:03.830995 ==
6509 11:13:03.834750 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 11:13:03.837687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 11:13:03.837772 ==
6512 11:13:03.837852 RX Vref Scan: 0
6513 11:13:03.837918
6514 11:13:03.841237 RX Vref 0 -> 0, step: 1
6515 11:13:03.841324
6516 11:13:03.844442 RX Delay -410 -> 252, step: 16
6517 11:13:03.847672 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6518 11:13:03.854202 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6519 11:13:03.857574 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6520 11:13:03.860877 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6521 11:13:03.864119 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6522 11:13:03.870826 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6523 11:13:03.873958 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6524 11:13:03.877239 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6525 11:13:03.880530 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6526 11:13:03.887590 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6527 11:13:03.890842 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6528 11:13:03.894017 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6529 11:13:03.897255 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6530 11:13:03.903681 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6531 11:13:03.907057 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6532 11:13:03.910973 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6533 11:13:03.911057 ==
6534 11:13:03.914011 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 11:13:03.920697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 11:13:03.920804 ==
6537 11:13:03.920907 DQS Delay:
6538 11:13:03.923838 DQS0 = 43, DQS1 = 51
6539 11:13:03.923933 DQM Delay:
6540 11:13:03.923997 DQM0 = 11, DQM1 = 9
6541 11:13:03.927514 DQ Delay:
6542 11:13:03.927596 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6543 11:13:03.930483 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6544 11:13:03.933548 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6545 11:13:03.937251 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6546 11:13:03.937334
6547 11:13:03.937397
6548 11:13:03.937457 ==
6549 11:13:03.940601 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 11:13:03.947316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 11:13:03.947446 ==
6552 11:13:03.947525
6553 11:13:03.947616
6554 11:13:03.947692 TX Vref Scan disable
6555 11:13:03.950480 == TX Byte 0 ==
6556 11:13:03.953888 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6557 11:13:03.960322 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6558 11:13:03.960404 == TX Byte 1 ==
6559 11:13:03.963562 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6560 11:13:03.966834 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6561 11:13:03.970055 ==
6562 11:13:03.973456 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 11:13:03.976766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 11:13:03.976848 ==
6565 11:13:03.976913
6566 11:13:03.976972
6567 11:13:03.980045 TX Vref Scan disable
6568 11:13:03.980128 == TX Byte 0 ==
6569 11:13:03.983341 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6570 11:13:03.990638 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6571 11:13:03.990720 == TX Byte 1 ==
6572 11:13:03.993776 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6573 11:13:04.000228 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6574 11:13:04.000329
6575 11:13:04.000426 [DATLAT]
6576 11:13:04.000501 Freq=400, CH0 RK1
6577 11:13:04.000593
6578 11:13:04.003453 DATLAT Default: 0xe
6579 11:13:04.003537 0, 0xFFFF, sum = 0
6580 11:13:04.006848 1, 0xFFFF, sum = 0
6581 11:13:04.010067 2, 0xFFFF, sum = 0
6582 11:13:04.010149 3, 0xFFFF, sum = 0
6583 11:13:04.013325 4, 0xFFFF, sum = 0
6584 11:13:04.013409 5, 0xFFFF, sum = 0
6585 11:13:04.017356 6, 0xFFFF, sum = 0
6586 11:13:04.017440 7, 0xFFFF, sum = 0
6587 11:13:04.020257 8, 0xFFFF, sum = 0
6588 11:13:04.020340 9, 0xFFFF, sum = 0
6589 11:13:04.023276 10, 0xFFFF, sum = 0
6590 11:13:04.023404 11, 0xFFFF, sum = 0
6591 11:13:04.027091 12, 0xFFFF, sum = 0
6592 11:13:04.027174 13, 0x0, sum = 1
6593 11:13:04.030051 14, 0x0, sum = 2
6594 11:13:04.030134 15, 0x0, sum = 3
6595 11:13:04.033185 16, 0x0, sum = 4
6596 11:13:04.033268 best_step = 14
6597 11:13:04.033334
6598 11:13:04.033392 ==
6599 11:13:04.036442 Dram Type= 6, Freq= 0, CH_0, rank 1
6600 11:13:04.040286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 11:13:04.043088 ==
6602 11:13:04.043171 RX Vref Scan: 0
6603 11:13:04.043235
6604 11:13:04.046634 RX Vref 0 -> 0, step: 1
6605 11:13:04.046716
6606 11:13:04.049787 RX Delay -343 -> 252, step: 8
6607 11:13:04.053353 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6608 11:13:04.059728 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6609 11:13:04.063029 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6610 11:13:04.066925 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6611 11:13:04.070328 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6612 11:13:04.076869 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6613 11:13:04.080078 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6614 11:13:04.083394 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6615 11:13:04.086607 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6616 11:13:04.093189 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6617 11:13:04.096511 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6618 11:13:04.099681 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6619 11:13:04.103295 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6620 11:13:04.110054 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6621 11:13:04.113144 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6622 11:13:04.116530 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6623 11:13:04.116617 ==
6624 11:13:04.119740 Dram Type= 6, Freq= 0, CH_0, rank 1
6625 11:13:04.126150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 11:13:04.126237 ==
6627 11:13:04.126306 DQS Delay:
6628 11:13:04.129766 DQS0 = 48, DQS1 = 60
6629 11:13:04.129866 DQM Delay:
6630 11:13:04.132997 DQM0 = 13, DQM1 = 13
6631 11:13:04.133094 DQ Delay:
6632 11:13:04.136277 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6633 11:13:04.139889 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6634 11:13:04.142745 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6635 11:13:04.146038 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6636 11:13:04.146122
6637 11:13:04.146188
6638 11:13:04.152924 [DQSOSCAuto] RK1, (LSB)MR18= 0x9363, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6639 11:13:04.156529 CH0 RK1: MR19=C0C, MR18=9363
6640 11:13:04.162705 CH0_RK1: MR19=0xC0C, MR18=0x9363, DQSOSC=391, MR23=63, INC=386, DEC=257
6641 11:13:04.165895 [RxdqsGatingPostProcess] freq 400
6642 11:13:04.169420 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6643 11:13:04.172705 best DQS0 dly(2T, 0.5T) = (0, 10)
6644 11:13:04.176008 best DQS1 dly(2T, 0.5T) = (0, 10)
6645 11:13:04.179235 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6646 11:13:04.182553 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6647 11:13:04.185672 best DQS0 dly(2T, 0.5T) = (0, 10)
6648 11:13:04.188900 best DQS1 dly(2T, 0.5T) = (0, 10)
6649 11:13:04.192183 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6650 11:13:04.195469 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6651 11:13:04.198767 Pre-setting of DQS Precalculation
6652 11:13:04.202037 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6653 11:13:04.205874 ==
6654 11:13:04.205955 Dram Type= 6, Freq= 0, CH_1, rank 0
6655 11:13:04.212364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 11:13:04.212445 ==
6657 11:13:04.215587 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6658 11:13:04.222554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6659 11:13:04.225857 [CA 0] Center 36 (8~64) winsize 57
6660 11:13:04.228570 [CA 1] Center 36 (8~64) winsize 57
6661 11:13:04.232731 [CA 2] Center 36 (8~64) winsize 57
6662 11:13:04.235691 [CA 3] Center 36 (8~64) winsize 57
6663 11:13:04.238782 [CA 4] Center 36 (8~64) winsize 57
6664 11:13:04.242590 [CA 5] Center 36 (8~64) winsize 57
6665 11:13:04.242690
6666 11:13:04.245771 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6667 11:13:04.245870
6668 11:13:04.248686 [CATrainingPosCal] consider 1 rank data
6669 11:13:04.252578 u2DelayCellTimex100 = 270/100 ps
6670 11:13:04.255359 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 11:13:04.259078 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 11:13:04.261996 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 11:13:04.265507 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 11:13:04.268568 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 11:13:04.275676 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 11:13:04.275786
6677 11:13:04.278987 CA PerBit enable=1, Macro0, CA PI delay=36
6678 11:13:04.279086
6679 11:13:04.282291 [CBTSetCACLKResult] CA Dly = 36
6680 11:13:04.282375 CS Dly: 1 (0~32)
6681 11:13:04.282457 ==
6682 11:13:04.285554 Dram Type= 6, Freq= 0, CH_1, rank 1
6683 11:13:04.288835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 11:13:04.288919 ==
6685 11:13:04.295308 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6686 11:13:04.302388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6687 11:13:04.305683 [CA 0] Center 36 (8~64) winsize 57
6688 11:13:04.308787 [CA 1] Center 36 (8~64) winsize 57
6689 11:13:04.311803 [CA 2] Center 36 (8~64) winsize 57
6690 11:13:04.315099 [CA 3] Center 36 (8~64) winsize 57
6691 11:13:04.319056 [CA 4] Center 36 (8~64) winsize 57
6692 11:13:04.322300 [CA 5] Center 36 (8~64) winsize 57
6693 11:13:04.322402
6694 11:13:04.325556 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6695 11:13:04.325645
6696 11:13:04.328743 [CATrainingPosCal] consider 2 rank data
6697 11:13:04.332044 u2DelayCellTimex100 = 270/100 ps
6698 11:13:04.335201 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 11:13:04.339065 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 11:13:04.342186 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 11:13:04.345888 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 11:13:04.348986 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 11:13:04.352137 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 11:13:04.352247
6705 11:13:04.355330 CA PerBit enable=1, Macro0, CA PI delay=36
6706 11:13:04.355438
6707 11:13:04.358455 [CBTSetCACLKResult] CA Dly = 36
6708 11:13:04.362132 CS Dly: 1 (0~32)
6709 11:13:04.362229
6710 11:13:04.365080 ----->DramcWriteLeveling(PI) begin...
6711 11:13:04.365165 ==
6712 11:13:04.368732 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 11:13:04.371845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 11:13:04.371933 ==
6715 11:13:04.375663 Write leveling (Byte 0): 40 => 8
6716 11:13:04.378706 Write leveling (Byte 1): 40 => 8
6717 11:13:04.381757 DramcWriteLeveling(PI) end<-----
6718 11:13:04.381863
6719 11:13:04.381956 ==
6720 11:13:04.385013 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 11:13:04.388302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 11:13:04.388382 ==
6723 11:13:04.391562 [Gating] SW mode calibration
6724 11:13:04.398563 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6725 11:13:04.405119 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6726 11:13:04.408379 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6727 11:13:04.415298 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6728 11:13:04.418413 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 11:13:04.421649 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6730 11:13:04.424999 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 11:13:04.431560 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 11:13:04.434923 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 11:13:04.438393 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6734 11:13:04.444637 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6735 11:13:04.448302 Total UI for P1: 0, mck2ui 16
6736 11:13:04.451490 best dqsien dly found for B0: ( 0, 14, 24)
6737 11:13:04.455132 Total UI for P1: 0, mck2ui 16
6738 11:13:04.458624 best dqsien dly found for B1: ( 0, 14, 24)
6739 11:13:04.461932 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6740 11:13:04.465252 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6741 11:13:04.465359
6742 11:13:04.468274 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6743 11:13:04.471839 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6744 11:13:04.474969 [Gating] SW calibration Done
6745 11:13:04.475081 ==
6746 11:13:04.478568 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 11:13:04.481564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 11:13:04.481652 ==
6749 11:13:04.485252 RX Vref Scan: 0
6750 11:13:04.485342
6751 11:13:04.485441 RX Vref 0 -> 0, step: 1
6752 11:13:04.488180
6753 11:13:04.488292 RX Delay -410 -> 252, step: 16
6754 11:13:04.494691 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6755 11:13:04.497987 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6756 11:13:04.501207 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6757 11:13:04.505026 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6758 11:13:04.511543 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6759 11:13:04.514802 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6760 11:13:04.517999 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6761 11:13:04.521075 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6762 11:13:04.527596 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6763 11:13:04.530835 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6764 11:13:04.534239 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6765 11:13:04.541389 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6766 11:13:04.544563 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6767 11:13:04.547784 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6768 11:13:04.550883 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6769 11:13:04.557620 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6770 11:13:04.557732 ==
6771 11:13:04.560794 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 11:13:04.564040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 11:13:04.564140 ==
6774 11:13:04.564231 DQS Delay:
6775 11:13:04.567254 DQS0 = 43, DQS1 = 59
6776 11:13:04.567359 DQM Delay:
6777 11:13:04.570960 DQM0 = 12, DQM1 = 16
6778 11:13:04.571059 DQ Delay:
6779 11:13:04.574157 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6780 11:13:04.577252 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6781 11:13:04.581014 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6782 11:13:04.584205 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6783 11:13:04.584288
6784 11:13:04.584354
6785 11:13:04.584414 ==
6786 11:13:04.587748 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 11:13:04.590890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 11:13:04.590992 ==
6789 11:13:04.591082
6790 11:13:04.591222
6791 11:13:04.594362 TX Vref Scan disable
6792 11:13:04.594462 == TX Byte 0 ==
6793 11:13:04.600709 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 11:13:04.603934 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 11:13:04.604035 == TX Byte 1 ==
6796 11:13:04.610570 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6797 11:13:04.613719 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6798 11:13:04.613816 ==
6799 11:13:04.617511 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 11:13:04.620725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 11:13:04.620810 ==
6802 11:13:04.620875
6803 11:13:04.620934
6804 11:13:04.623868 TX Vref Scan disable
6805 11:13:04.627075 == TX Byte 0 ==
6806 11:13:04.630884 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 11:13:04.634280 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 11:13:04.637564 == TX Byte 1 ==
6809 11:13:04.640760 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6810 11:13:04.643918 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6811 11:13:04.644042
6812 11:13:04.644150 [DATLAT]
6813 11:13:04.647253 Freq=400, CH1 RK0
6814 11:13:04.647380
6815 11:13:04.647458 DATLAT Default: 0xf
6816 11:13:04.650549 0, 0xFFFF, sum = 0
6817 11:13:04.650655 1, 0xFFFF, sum = 0
6818 11:13:04.653900 2, 0xFFFF, sum = 0
6819 11:13:04.654015 3, 0xFFFF, sum = 0
6820 11:13:04.657707 4, 0xFFFF, sum = 0
6821 11:13:04.657823 5, 0xFFFF, sum = 0
6822 11:13:04.660853 6, 0xFFFF, sum = 0
6823 11:13:04.660979 7, 0xFFFF, sum = 0
6824 11:13:04.663971 8, 0xFFFF, sum = 0
6825 11:13:04.667799 9, 0xFFFF, sum = 0
6826 11:13:04.667939 10, 0xFFFF, sum = 0
6827 11:13:04.670889 11, 0xFFFF, sum = 0
6828 11:13:04.671047 12, 0xFFFF, sum = 0
6829 11:13:04.674078 13, 0x0, sum = 1
6830 11:13:04.674258 14, 0x0, sum = 2
6831 11:13:04.677667 15, 0x0, sum = 3
6832 11:13:04.677847 16, 0x0, sum = 4
6833 11:13:04.677988 best_step = 14
6834 11:13:04.678118
6835 11:13:04.680635 ==
6836 11:13:04.684455 Dram Type= 6, Freq= 0, CH_1, rank 0
6837 11:13:04.687877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 11:13:04.688130 ==
6839 11:13:04.688326 RX Vref Scan: 1
6840 11:13:04.688507
6841 11:13:04.690875 RX Vref 0 -> 0, step: 1
6842 11:13:04.691217
6843 11:13:04.694219 RX Delay -359 -> 252, step: 8
6844 11:13:04.694757
6845 11:13:04.697933 Set Vref, RX VrefLevel [Byte0]: 59
6846 11:13:04.700908 [Byte1]: 52
6847 11:13:04.705022
6848 11:13:04.705447 Final RX Vref Byte 0 = 59 to rank0
6849 11:13:04.708334 Final RX Vref Byte 1 = 52 to rank0
6850 11:13:04.711565 Final RX Vref Byte 0 = 59 to rank1
6851 11:13:04.714805 Final RX Vref Byte 1 = 52 to rank1==
6852 11:13:04.718187 Dram Type= 6, Freq= 0, CH_1, rank 0
6853 11:13:04.724614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 11:13:04.725044 ==
6855 11:13:04.725381 DQS Delay:
6856 11:13:04.728210 DQS0 = 44, DQS1 = 60
6857 11:13:04.728639 DQM Delay:
6858 11:13:04.728975 DQM0 = 9, DQM1 = 13
6859 11:13:04.731181 DQ Delay:
6860 11:13:04.734994 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6861 11:13:04.735464 DQ4 =4, DQ5 =20, DQ6 =20, DQ7 =8
6862 11:13:04.737709 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6863 11:13:04.741690 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6864 11:13:04.742119
6865 11:13:04.742456
6866 11:13:04.751516 [DQSOSCAuto] RK0, (LSB)MR18= 0x8c33, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6867 11:13:04.754924 CH1 RK0: MR19=C0C, MR18=8C33
6868 11:13:04.761228 CH1_RK0: MR19=0xC0C, MR18=0x8C33, DQSOSC=392, MR23=63, INC=384, DEC=256
6869 11:13:04.761664 ==
6870 11:13:04.765058 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 11:13:04.767918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 11:13:04.768361 ==
6873 11:13:04.770991 [Gating] SW mode calibration
6874 11:13:04.777645 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6875 11:13:04.781053 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6876 11:13:04.787456 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6877 11:13:04.790780 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6878 11:13:04.794404 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 11:13:04.801235 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6880 11:13:04.804299 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 11:13:04.807894 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 11:13:04.814021 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 11:13:04.817312 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6884 11:13:04.820838 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6885 11:13:04.823850 Total UI for P1: 0, mck2ui 16
6886 11:13:04.827197 best dqsien dly found for B0: ( 0, 14, 24)
6887 11:13:04.831036 Total UI for P1: 0, mck2ui 16
6888 11:13:04.834344 best dqsien dly found for B1: ( 0, 14, 24)
6889 11:13:04.837403 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6890 11:13:04.843968 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6891 11:13:04.844497
6892 11:13:04.847391 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6893 11:13:04.850658 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6894 11:13:04.853830 [Gating] SW calibration Done
6895 11:13:04.854268 ==
6896 11:13:04.857773 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 11:13:04.860513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 11:13:04.861053 ==
6899 11:13:04.861418 RX Vref Scan: 0
6900 11:13:04.864340
6901 11:13:04.864850 RX Vref 0 -> 0, step: 1
6902 11:13:04.865262
6903 11:13:04.867251 RX Delay -410 -> 252, step: 16
6904 11:13:04.871042 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6905 11:13:04.877161 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6906 11:13:04.880282 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6907 11:13:04.883666 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6908 11:13:04.887261 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6909 11:13:04.893968 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6910 11:13:04.897130 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6911 11:13:04.900343 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6912 11:13:04.904006 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6913 11:13:04.910623 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6914 11:13:04.913586 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6915 11:13:04.917257 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6916 11:13:04.920255 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6917 11:13:04.927043 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6918 11:13:04.930501 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6919 11:13:04.933826 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6920 11:13:04.934251 ==
6921 11:13:04.936987 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 11:13:04.943843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 11:13:04.944269 ==
6924 11:13:04.944601 DQS Delay:
6925 11:13:04.946684 DQS0 = 43, DQS1 = 59
6926 11:13:04.947153 DQM Delay:
6927 11:13:04.947633 DQM0 = 9, DQM1 = 18
6928 11:13:04.949902 DQ Delay:
6929 11:13:04.953819 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6930 11:13:04.954324 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6931 11:13:04.956658 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6932 11:13:04.959889 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6933 11:13:04.960367
6934 11:13:04.960708
6935 11:13:04.963915 ==
6936 11:13:04.967220 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 11:13:04.970293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 11:13:04.970775 ==
6939 11:13:04.971151
6940 11:13:04.971597
6941 11:13:04.973328 TX Vref Scan disable
6942 11:13:04.973797 == TX Byte 0 ==
6943 11:13:04.977057 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6944 11:13:04.983270 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6945 11:13:04.983797 == TX Byte 1 ==
6946 11:13:04.986573 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6947 11:13:04.993171 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6948 11:13:04.993656 ==
6949 11:13:04.996484 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 11:13:04.999760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 11:13:05.000244 ==
6952 11:13:05.000624
6953 11:13:05.001036
6954 11:13:05.003465 TX Vref Scan disable
6955 11:13:05.003973 == TX Byte 0 ==
6956 11:13:05.010127 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6957 11:13:05.013114 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6958 11:13:05.013634 == TX Byte 1 ==
6959 11:13:05.019839 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6960 11:13:05.023287 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6961 11:13:05.023800
6962 11:13:05.024144 [DATLAT]
6963 11:13:05.026479 Freq=400, CH1 RK1
6964 11:13:05.026910
6965 11:13:05.027298 DATLAT Default: 0xe
6966 11:13:05.029953 0, 0xFFFF, sum = 0
6967 11:13:05.030390 1, 0xFFFF, sum = 0
6968 11:13:05.032901 2, 0xFFFF, sum = 0
6969 11:13:05.033351 3, 0xFFFF, sum = 0
6970 11:13:05.036647 4, 0xFFFF, sum = 0
6971 11:13:05.037145 5, 0xFFFF, sum = 0
6972 11:13:05.039948 6, 0xFFFF, sum = 0
6973 11:13:05.040383 7, 0xFFFF, sum = 0
6974 11:13:05.043066 8, 0xFFFF, sum = 0
6975 11:13:05.043552 9, 0xFFFF, sum = 0
6976 11:13:05.046177 10, 0xFFFF, sum = 0
6977 11:13:05.046619 11, 0xFFFF, sum = 0
6978 11:13:05.049994 12, 0xFFFF, sum = 0
6979 11:13:05.050427 13, 0x0, sum = 1
6980 11:13:05.052670 14, 0x0, sum = 2
6981 11:13:05.053104 15, 0x0, sum = 3
6982 11:13:05.056509 16, 0x0, sum = 4
6983 11:13:05.056943 best_step = 14
6984 11:13:05.057278
6985 11:13:05.057588 ==
6986 11:13:05.059752 Dram Type= 6, Freq= 0, CH_1, rank 1
6987 11:13:05.066408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6988 11:13:05.066836 ==
6989 11:13:05.067176 RX Vref Scan: 0
6990 11:13:05.067529
6991 11:13:05.069384 RX Vref 0 -> 0, step: 1
6992 11:13:05.069811
6993 11:13:05.072631 RX Delay -359 -> 252, step: 8
6994 11:13:05.079588 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6995 11:13:05.082612 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6996 11:13:05.086122 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6997 11:13:05.089554 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6998 11:13:05.096529 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6999 11:13:05.099969 iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480
7000 11:13:05.103011 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7001 11:13:05.106331 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7002 11:13:05.112839 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7003 11:13:05.116085 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7004 11:13:05.119121 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7005 11:13:05.126241 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7006 11:13:05.129287 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7007 11:13:05.132831 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7008 11:13:05.135907 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7009 11:13:05.142367 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7010 11:13:05.142801 ==
7011 11:13:05.145705 Dram Type= 6, Freq= 0, CH_1, rank 1
7012 11:13:05.149347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7013 11:13:05.149773 ==
7014 11:13:05.150160 DQS Delay:
7015 11:13:05.152545 DQS0 = 52, DQS1 = 56
7016 11:13:05.152967 DQM Delay:
7017 11:13:05.155834 DQM0 = 14, DQM1 = 9
7018 11:13:05.156256 DQ Delay:
7019 11:13:05.159002 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7020 11:13:05.161947 DQ4 =16, DQ5 =28, DQ6 =24, DQ7 =8
7021 11:13:05.165216 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7022 11:13:05.168509 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7023 11:13:05.168591
7024 11:13:05.168655
7025 11:13:05.175627 [DQSOSCAuto] RK1, (LSB)MR18= 0x7186, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
7026 11:13:05.178777 CH1 RK1: MR19=C0C, MR18=7186
7027 11:13:05.185340 CH1_RK1: MR19=0xC0C, MR18=0x7186, DQSOSC=393, MR23=63, INC=382, DEC=254
7028 11:13:05.188413 [RxdqsGatingPostProcess] freq 400
7029 11:13:05.195109 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7030 11:13:05.195192 best DQS0 dly(2T, 0.5T) = (0, 10)
7031 11:13:05.198381 best DQS1 dly(2T, 0.5T) = (0, 10)
7032 11:13:05.201605 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7033 11:13:05.205009 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7034 11:13:05.208300 best DQS0 dly(2T, 0.5T) = (0, 10)
7035 11:13:05.212059 best DQS1 dly(2T, 0.5T) = (0, 10)
7036 11:13:05.215261 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7037 11:13:05.218595 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7038 11:13:05.221739 Pre-setting of DQS Precalculation
7039 11:13:05.228140 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7040 11:13:05.235343 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7041 11:13:05.241868 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7042 11:13:05.241950
7043 11:13:05.242015
7044 11:13:05.245063 [Calibration Summary] 800 Mbps
7045 11:13:05.245145 CH 0, Rank 0
7046 11:13:05.248600 SW Impedance : PASS
7047 11:13:05.251628 DUTY Scan : NO K
7048 11:13:05.251710 ZQ Calibration : PASS
7049 11:13:05.254648 Jitter Meter : NO K
7050 11:13:05.254730 CBT Training : PASS
7051 11:13:05.258458 Write leveling : PASS
7052 11:13:05.261765 RX DQS gating : PASS
7053 11:13:05.261847 RX DQ/DQS(RDDQC) : PASS
7054 11:13:05.265074 TX DQ/DQS : PASS
7055 11:13:05.268375 RX DATLAT : PASS
7056 11:13:05.268457 RX DQ/DQS(Engine): PASS
7057 11:13:05.271712 TX OE : NO K
7058 11:13:05.271794 All Pass.
7059 11:13:05.271862
7060 11:13:05.274908 CH 0, Rank 1
7061 11:13:05.274989 SW Impedance : PASS
7062 11:13:05.277997 DUTY Scan : NO K
7063 11:13:05.281969 ZQ Calibration : PASS
7064 11:13:05.282051 Jitter Meter : NO K
7065 11:13:05.285108 CBT Training : PASS
7066 11:13:05.288321 Write leveling : NO K
7067 11:13:05.288403 RX DQS gating : PASS
7068 11:13:05.291518 RX DQ/DQS(RDDQC) : PASS
7069 11:13:05.295101 TX DQ/DQS : PASS
7070 11:13:05.295183 RX DATLAT : PASS
7071 11:13:05.298062 RX DQ/DQS(Engine): PASS
7072 11:13:05.298147 TX OE : NO K
7073 11:13:05.301333 All Pass.
7074 11:13:05.301415
7075 11:13:05.301479 CH 1, Rank 0
7076 11:13:05.304638 SW Impedance : PASS
7077 11:13:05.304720 DUTY Scan : NO K
7078 11:13:05.307869 ZQ Calibration : PASS
7079 11:13:05.311181 Jitter Meter : NO K
7080 11:13:05.311263 CBT Training : PASS
7081 11:13:05.314495 Write leveling : PASS
7082 11:13:05.317738 RX DQS gating : PASS
7083 11:13:05.317848 RX DQ/DQS(RDDQC) : PASS
7084 11:13:05.321007 TX DQ/DQS : PASS
7085 11:13:05.324866 RX DATLAT : PASS
7086 11:13:05.324947 RX DQ/DQS(Engine): PASS
7087 11:13:05.327843 TX OE : NO K
7088 11:13:05.327926 All Pass.
7089 11:13:05.327990
7090 11:13:05.331034 CH 1, Rank 1
7091 11:13:05.331116 SW Impedance : PASS
7092 11:13:05.334315 DUTY Scan : NO K
7093 11:13:05.337640 ZQ Calibration : PASS
7094 11:13:05.337721 Jitter Meter : NO K
7095 11:13:05.341385 CBT Training : PASS
7096 11:13:05.344495 Write leveling : NO K
7097 11:13:05.344577 RX DQS gating : PASS
7098 11:13:05.347670 RX DQ/DQS(RDDQC) : PASS
7099 11:13:05.351423 TX DQ/DQS : PASS
7100 11:13:05.351505 RX DATLAT : PASS
7101 11:13:05.354529 RX DQ/DQS(Engine): PASS
7102 11:13:05.354610 TX OE : NO K
7103 11:13:05.357688 All Pass.
7104 11:13:05.357770
7105 11:13:05.357835 DramC Write-DBI off
7106 11:13:05.360822 PER_BANK_REFRESH: Hybrid Mode
7107 11:13:05.364537 TX_TRACKING: ON
7108 11:13:05.370999 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7109 11:13:05.374268 [FAST_K] Save calibration result to emmc
7110 11:13:05.381331 dramc_set_vcore_voltage set vcore to 725000
7111 11:13:05.381413 Read voltage for 1600, 0
7112 11:13:05.381478 Vio18 = 0
7113 11:13:05.384680 Vcore = 725000
7114 11:13:05.384761 Vdram = 0
7115 11:13:05.384826 Vddq = 0
7116 11:13:05.387893 Vmddr = 0
7117 11:13:05.391167 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7118 11:13:05.397403 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7119 11:13:05.401158 MEM_TYPE=3, freq_sel=13
7120 11:13:05.401240 sv_algorithm_assistance_LP4_3733
7121 11:13:05.407496 ============ PULL DRAM RESETB DOWN ============
7122 11:13:05.410635 ========== PULL DRAM RESETB DOWN end =========
7123 11:13:05.413996 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7124 11:13:05.417287 ===================================
7125 11:13:05.421172 LPDDR4 DRAM CONFIGURATION
7126 11:13:05.424323 ===================================
7127 11:13:05.427609 EX_ROW_EN[0] = 0x0
7128 11:13:05.427692 EX_ROW_EN[1] = 0x0
7129 11:13:05.430626 LP4Y_EN = 0x0
7130 11:13:05.430708 WORK_FSP = 0x1
7131 11:13:05.434363 WL = 0x5
7132 11:13:05.434446 RL = 0x5
7133 11:13:05.437164 BL = 0x2
7134 11:13:05.437245 RPST = 0x0
7135 11:13:05.441037 RD_PRE = 0x0
7136 11:13:05.441119 WR_PRE = 0x1
7137 11:13:05.444336 WR_PST = 0x1
7138 11:13:05.444418 DBI_WR = 0x0
7139 11:13:05.447601 DBI_RD = 0x0
7140 11:13:05.447682 OTF = 0x1
7141 11:13:05.450828 ===================================
7142 11:13:05.454382 ===================================
7143 11:13:05.457346 ANA top config
7144 11:13:05.460479 ===================================
7145 11:13:05.464150 DLL_ASYNC_EN = 0
7146 11:13:05.464232 ALL_SLAVE_EN = 0
7147 11:13:05.467217 NEW_RANK_MODE = 1
7148 11:13:05.470872 DLL_IDLE_MODE = 1
7149 11:13:05.474230 LP45_APHY_COMB_EN = 1
7150 11:13:05.477485 TX_ODT_DIS = 0
7151 11:13:05.477565 NEW_8X_MODE = 1
7152 11:13:05.480667 ===================================
7153 11:13:05.483797 ===================================
7154 11:13:05.487053 data_rate = 3200
7155 11:13:05.490965 CKR = 1
7156 11:13:05.494026 DQ_P2S_RATIO = 8
7157 11:13:05.497391 ===================================
7158 11:13:05.500364 CA_P2S_RATIO = 8
7159 11:13:05.500446 DQ_CA_OPEN = 0
7160 11:13:05.503864 DQ_SEMI_OPEN = 0
7161 11:13:05.506921 CA_SEMI_OPEN = 0
7162 11:13:05.510718 CA_FULL_RATE = 0
7163 11:13:05.513411 DQ_CKDIV4_EN = 0
7164 11:13:05.517213 CA_CKDIV4_EN = 0
7165 11:13:05.517295 CA_PREDIV_EN = 0
7166 11:13:05.520537 PH8_DLY = 12
7167 11:13:05.523726 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7168 11:13:05.526965 DQ_AAMCK_DIV = 4
7169 11:13:05.530199 CA_AAMCK_DIV = 4
7170 11:13:05.533506 CA_ADMCK_DIV = 4
7171 11:13:05.533588 DQ_TRACK_CA_EN = 0
7172 11:13:05.537336 CA_PICK = 1600
7173 11:13:05.540505 CA_MCKIO = 1600
7174 11:13:05.543685 MCKIO_SEMI = 0
7175 11:13:05.546830 PLL_FREQ = 3068
7176 11:13:05.550131 DQ_UI_PI_RATIO = 32
7177 11:13:05.554005 CA_UI_PI_RATIO = 0
7178 11:13:05.557289 ===================================
7179 11:13:05.560277 ===================================
7180 11:13:05.560360 memory_type:LPDDR4
7181 11:13:05.564072 GP_NUM : 10
7182 11:13:05.567004 SRAM_EN : 1
7183 11:13:05.567085 MD32_EN : 0
7184 11:13:05.570179 ===================================
7185 11:13:05.573860 [ANA_INIT] >>>>>>>>>>>>>>
7186 11:13:05.576849 <<<<<< [CONFIGURE PHASE]: ANA_TX
7187 11:13:05.580127 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7188 11:13:05.583273 ===================================
7189 11:13:05.587027 data_rate = 3200,PCW = 0X7600
7190 11:13:05.590284 ===================================
7191 11:13:05.593536 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7192 11:13:05.596598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7193 11:13:05.603795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7194 11:13:05.607001 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7195 11:13:05.610139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7196 11:13:05.613232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7197 11:13:05.617094 [ANA_INIT] flow start
7198 11:13:05.620347 [ANA_INIT] PLL >>>>>>>>
7199 11:13:05.620452 [ANA_INIT] PLL <<<<<<<<
7200 11:13:05.623489 [ANA_INIT] MIDPI >>>>>>>>
7201 11:13:05.626759 [ANA_INIT] MIDPI <<<<<<<<
7202 11:13:05.630011 [ANA_INIT] DLL >>>>>>>>
7203 11:13:05.630117 [ANA_INIT] DLL <<<<<<<<
7204 11:13:05.633296 [ANA_INIT] flow end
7205 11:13:05.636614 ============ LP4 DIFF to SE enter ============
7206 11:13:05.640080 ============ LP4 DIFF to SE exit ============
7207 11:13:05.643337 [ANA_INIT] <<<<<<<<<<<<<
7208 11:13:05.646745 [Flow] Enable top DCM control >>>>>
7209 11:13:05.649745 [Flow] Enable top DCM control <<<<<
7210 11:13:05.653593 Enable DLL master slave shuffle
7211 11:13:05.659969 ==============================================================
7212 11:13:05.660045 Gating Mode config
7213 11:13:05.666580 ==============================================================
7214 11:13:05.666658 Config description:
7215 11:13:05.676363 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7216 11:13:05.683165 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7217 11:13:05.689877 SELPH_MODE 0: By rank 1: By Phase
7218 11:13:05.693168 ==============================================================
7219 11:13:05.696395 GAT_TRACK_EN = 1
7220 11:13:05.699724 RX_GATING_MODE = 2
7221 11:13:05.702970 RX_GATING_TRACK_MODE = 2
7222 11:13:05.706080 SELPH_MODE = 1
7223 11:13:05.709410 PICG_EARLY_EN = 1
7224 11:13:05.713039 VALID_LAT_VALUE = 1
7225 11:13:05.716371 ==============================================================
7226 11:13:05.722641 Enter into Gating configuration >>>>
7227 11:13:05.722729 Exit from Gating configuration <<<<
7228 11:13:05.725955 Enter into DVFS_PRE_config >>>>>
7229 11:13:05.739170 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7230 11:13:05.742631 Exit from DVFS_PRE_config <<<<<
7231 11:13:05.745995 Enter into PICG configuration >>>>
7232 11:13:05.749373 Exit from PICG configuration <<<<
7233 11:13:05.749456 [RX_INPUT] configuration >>>>>
7234 11:13:05.752433 [RX_INPUT] configuration <<<<<
7235 11:13:05.759541 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7236 11:13:05.762854 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7237 11:13:05.769460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7238 11:13:05.775728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7239 11:13:05.782344 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7240 11:13:05.788834 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7241 11:13:05.792410 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7242 11:13:05.796007 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7243 11:13:05.802572 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7244 11:13:05.805893 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7245 11:13:05.809276 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7246 11:13:05.812541 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7247 11:13:05.815681 ===================================
7248 11:13:05.818761 LPDDR4 DRAM CONFIGURATION
7249 11:13:05.822313 ===================================
7250 11:13:05.825792 EX_ROW_EN[0] = 0x0
7251 11:13:05.825887 EX_ROW_EN[1] = 0x0
7252 11:13:05.828790 LP4Y_EN = 0x0
7253 11:13:05.828873 WORK_FSP = 0x1
7254 11:13:05.832127 WL = 0x5
7255 11:13:05.832211 RL = 0x5
7256 11:13:05.835323 BL = 0x2
7257 11:13:05.835427 RPST = 0x0
7258 11:13:05.838607 RD_PRE = 0x0
7259 11:13:05.838724 WR_PRE = 0x1
7260 11:13:05.841785 WR_PST = 0x1
7261 11:13:05.845547 DBI_WR = 0x0
7262 11:13:05.845644 DBI_RD = 0x0
7263 11:13:05.848678 OTF = 0x1
7264 11:13:05.851837 ===================================
7265 11:13:05.855092 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7266 11:13:05.858408 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7267 11:13:05.862233 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7268 11:13:05.865555 ===================================
7269 11:13:05.868535 LPDDR4 DRAM CONFIGURATION
7270 11:13:05.872120 ===================================
7271 11:13:05.875402 EX_ROW_EN[0] = 0x10
7272 11:13:05.875500 EX_ROW_EN[1] = 0x0
7273 11:13:05.878692 LP4Y_EN = 0x0
7274 11:13:05.878775 WORK_FSP = 0x1
7275 11:13:05.881859 WL = 0x5
7276 11:13:05.881941 RL = 0x5
7277 11:13:05.885502 BL = 0x2
7278 11:13:05.885598 RPST = 0x0
7279 11:13:05.888635 RD_PRE = 0x0
7280 11:13:05.888746 WR_PRE = 0x1
7281 11:13:05.891660 WR_PST = 0x1
7282 11:13:05.891744 DBI_WR = 0x0
7283 11:13:05.894935 DBI_RD = 0x0
7284 11:13:05.898465 OTF = 0x1
7285 11:13:05.898549 ===================================
7286 11:13:05.905022 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7287 11:13:05.905111 ==
7288 11:13:05.908617 Dram Type= 6, Freq= 0, CH_0, rank 0
7289 11:13:05.915342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7290 11:13:05.915453 ==
7291 11:13:05.915519 [Duty_Offset_Calibration]
7292 11:13:05.918630 B0:2 B1:-1 CA:1
7293 11:13:05.918713
7294 11:13:05.921822 [DutyScan_Calibration_Flow] k_type=0
7295 11:13:05.930748
7296 11:13:05.930826 ==CLK 0==
7297 11:13:05.933982 Final CLK duty delay cell = -4
7298 11:13:05.937171 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7299 11:13:05.940481 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7300 11:13:05.943719 [-4] AVG Duty = 4922%(X100)
7301 11:13:05.943802
7302 11:13:05.946829 CH0 CLK Duty spec in!! Max-Min= 156%
7303 11:13:05.950083 [DutyScan_Calibration_Flow] ====Done====
7304 11:13:05.950166
7305 11:13:05.953244 [DutyScan_Calibration_Flow] k_type=1
7306 11:13:05.969906
7307 11:13:05.969996 ==DQS 0 ==
7308 11:13:05.973284 Final DQS duty delay cell = 0
7309 11:13:05.976575 [0] MAX Duty = 5125%(X100), DQS PI = 20
7310 11:13:05.979876 [0] MIN Duty = 5000%(X100), DQS PI = 14
7311 11:13:05.983055 [0] AVG Duty = 5062%(X100)
7312 11:13:05.983137
7313 11:13:05.983203 ==DQS 1 ==
7314 11:13:05.986215 Final DQS duty delay cell = -4
7315 11:13:05.989763 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7316 11:13:05.992972 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7317 11:13:05.996412 [-4] AVG Duty = 5046%(X100)
7318 11:13:05.996495
7319 11:13:06.000145 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7320 11:13:06.000228
7321 11:13:06.003181 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7322 11:13:06.006709 [DutyScan_Calibration_Flow] ====Done====
7323 11:13:06.006794
7324 11:13:06.009646 [DutyScan_Calibration_Flow] k_type=3
7325 11:13:06.027020
7326 11:13:06.027112 ==DQM 0 ==
7327 11:13:06.030588 Final DQM duty delay cell = 0
7328 11:13:06.033820 [0] MAX Duty = 5000%(X100), DQS PI = 18
7329 11:13:06.037028 [0] MIN Duty = 4875%(X100), DQS PI = 4
7330 11:13:06.040258 [0] AVG Duty = 4937%(X100)
7331 11:13:06.040362
7332 11:13:06.040452 ==DQM 1 ==
7333 11:13:06.044110 Final DQM duty delay cell = 0
7334 11:13:06.047525 [0] MAX Duty = 5187%(X100), DQS PI = 58
7335 11:13:06.050749 [0] MIN Duty = 4969%(X100), DQS PI = 18
7336 11:13:06.054012 [0] AVG Duty = 5078%(X100)
7337 11:13:06.054115
7338 11:13:06.057359 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7339 11:13:06.057458
7340 11:13:06.060369 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7341 11:13:06.063573 [DutyScan_Calibration_Flow] ====Done====
7342 11:13:06.063643
7343 11:13:06.066853 [DutyScan_Calibration_Flow] k_type=2
7344 11:13:06.083791
7345 11:13:06.083872 ==DQ 0 ==
7346 11:13:06.086995 Final DQ duty delay cell = -4
7347 11:13:06.090245 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7348 11:13:06.093382 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7349 11:13:06.097046 [-4] AVG Duty = 4937%(X100)
7350 11:13:06.097132
7351 11:13:06.097197 ==DQ 1 ==
7352 11:13:06.100222 Final DQ duty delay cell = 0
7353 11:13:06.103459 [0] MAX Duty = 5031%(X100), DQS PI = 32
7354 11:13:06.106818 [0] MIN Duty = 4938%(X100), DQS PI = 4
7355 11:13:06.106895 [0] AVG Duty = 4984%(X100)
7356 11:13:06.110009
7357 11:13:06.113634 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7358 11:13:06.113706
7359 11:13:06.116892 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7360 11:13:06.119934 [DutyScan_Calibration_Flow] ====Done====
7361 11:13:06.120004 ==
7362 11:13:06.123675 Dram Type= 6, Freq= 0, CH_1, rank 0
7363 11:13:06.126638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7364 11:13:06.126721 ==
7365 11:13:06.130364 [Duty_Offset_Calibration]
7366 11:13:06.130434 B0:1 B1:1 CA:2
7367 11:13:06.130492
7368 11:13:06.133104 [DutyScan_Calibration_Flow] k_type=0
7369 11:13:06.143947
7370 11:13:06.144028 ==CLK 0==
7371 11:13:06.147582 Final CLK duty delay cell = 0
7372 11:13:06.150636 [0] MAX Duty = 5125%(X100), DQS PI = 58
7373 11:13:06.153819 [0] MIN Duty = 4969%(X100), DQS PI = 10
7374 11:13:06.153902 [0] AVG Duty = 5047%(X100)
7375 11:13:06.156911
7376 11:13:06.161031 CH1 CLK Duty spec in!! Max-Min= 156%
7377 11:13:06.164037 [DutyScan_Calibration_Flow] ====Done====
7378 11:13:06.164111
7379 11:13:06.167192 [DutyScan_Calibration_Flow] k_type=1
7380 11:13:06.183512
7381 11:13:06.183592 ==DQS 0 ==
7382 11:13:06.186837 Final DQS duty delay cell = 0
7383 11:13:06.190054 [0] MAX Duty = 5031%(X100), DQS PI = 52
7384 11:13:06.193866 [0] MIN Duty = 4875%(X100), DQS PI = 0
7385 11:13:06.193948 [0] AVG Duty = 4953%(X100)
7386 11:13:06.197070
7387 11:13:06.197152 ==DQS 1 ==
7388 11:13:06.200236 Final DQS duty delay cell = 0
7389 11:13:06.203532 [0] MAX Duty = 5062%(X100), DQS PI = 20
7390 11:13:06.206745 [0] MIN Duty = 4907%(X100), DQS PI = 46
7391 11:13:06.206828 [0] AVG Duty = 4984%(X100)
7392 11:13:06.210475
7393 11:13:06.213790 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7394 11:13:06.213873
7395 11:13:06.217121 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7396 11:13:06.220151 [DutyScan_Calibration_Flow] ====Done====
7397 11:13:06.220234
7398 11:13:06.223301 [DutyScan_Calibration_Flow] k_type=3
7399 11:13:06.240161
7400 11:13:06.240248 ==DQM 0 ==
7401 11:13:06.243845 Final DQM duty delay cell = 0
7402 11:13:06.246720 [0] MAX Duty = 5093%(X100), DQS PI = 50
7403 11:13:06.250191 [0] MIN Duty = 4907%(X100), DQS PI = 0
7404 11:13:06.253388 [0] AVG Duty = 5000%(X100)
7405 11:13:06.253471
7406 11:13:06.253537 ==DQM 1 ==
7407 11:13:06.256639 Final DQM duty delay cell = 0
7408 11:13:06.260395 [0] MAX Duty = 5187%(X100), DQS PI = 26
7409 11:13:06.263695 [0] MIN Duty = 4875%(X100), DQS PI = 52
7410 11:13:06.267029 [0] AVG Duty = 5031%(X100)
7411 11:13:06.267112
7412 11:13:06.270047 CH1 DQM 0 Duty spec in!! Max-Min= 186%
7413 11:13:06.270160
7414 11:13:06.273379 CH1 DQM 1 Duty spec in!! Max-Min= 312%
7415 11:13:06.277115 [DutyScan_Calibration_Flow] ====Done====
7416 11:13:06.277199
7417 11:13:06.280414 [DutyScan_Calibration_Flow] k_type=2
7418 11:13:06.296179
7419 11:13:06.296301 ==DQ 0 ==
7420 11:13:06.300012 Final DQ duty delay cell = 0
7421 11:13:06.303288 [0] MAX Duty = 5125%(X100), DQS PI = 52
7422 11:13:06.306406 [0] MIN Duty = 4969%(X100), DQS PI = 0
7423 11:13:06.306496 [0] AVG Duty = 5047%(X100)
7424 11:13:06.306562
7425 11:13:06.309714 ==DQ 1 ==
7426 11:13:06.313228 Final DQ duty delay cell = -4
7427 11:13:06.316304 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7428 11:13:06.319519 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7429 11:13:06.319603 [-4] AVG Duty = 4938%(X100)
7430 11:13:06.322599
7431 11:13:06.326640 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7432 11:13:06.326762
7433 11:13:06.329754 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7434 11:13:06.332829 [DutyScan_Calibration_Flow] ====Done====
7435 11:13:06.335939 nWR fixed to 30
7436 11:13:06.339083 [ModeRegInit_LP4] CH0 RK0
7437 11:13:06.339206 [ModeRegInit_LP4] CH0 RK1
7438 11:13:06.342849 [ModeRegInit_LP4] CH1 RK0
7439 11:13:06.345727 [ModeRegInit_LP4] CH1 RK1
7440 11:13:06.345861 match AC timing 5
7441 11:13:06.352448 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7442 11:13:06.356053 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7443 11:13:06.359184 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7444 11:13:06.365881 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7445 11:13:06.369170 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7446 11:13:06.369282 [MiockJmeterHQA]
7447 11:13:06.369382
7448 11:13:06.372270 [DramcMiockJmeter] u1RxGatingPI = 0
7449 11:13:06.376132 0 : 4253, 4027
7450 11:13:06.376250 4 : 4252, 4027
7451 11:13:06.379249 8 : 4368, 4140
7452 11:13:06.379388 12 : 4258, 4029
7453 11:13:06.379494 16 : 4257, 4029
7454 11:13:06.382628 20 : 4258, 4029
7455 11:13:06.382740 24 : 4258, 4030
7456 11:13:06.385800 28 : 4366, 4138
7457 11:13:06.385914 32 : 4255, 4027
7458 11:13:06.389117 36 : 4368, 4137
7459 11:13:06.389234 40 : 4366, 4138
7460 11:13:06.392389 44 : 4368, 4140
7461 11:13:06.392511 48 : 4255, 4027
7462 11:13:06.395697 52 : 4255, 4030
7463 11:13:06.395814 56 : 4257, 4029
7464 11:13:06.395911 60 : 4363, 4138
7465 11:13:06.399038 64 : 4252, 4027
7466 11:13:06.399165 68 : 4360, 4138
7467 11:13:06.402197 72 : 4258, 4029
7468 11:13:06.402308 76 : 4250, 4027
7469 11:13:06.405340 80 : 4363, 4140
7470 11:13:06.405456 84 : 4252, 4030
7471 11:13:06.405558 88 : 4250, 4027
7472 11:13:06.409081 92 : 4361, 4137
7473 11:13:06.409190 96 : 4250, 3275
7474 11:13:06.412144 100 : 4252, 0
7475 11:13:06.412251 104 : 4253, 0
7476 11:13:06.415264 108 : 4250, 0
7477 11:13:06.415388 112 : 4253, 0
7478 11:13:06.415498 116 : 4361, 0
7479 11:13:06.418605 120 : 4363, 0
7480 11:13:06.418719 124 : 4250, 0
7481 11:13:06.418817 128 : 4252, 0
7482 11:13:06.422450 132 : 4255, 0
7483 11:13:06.422552 136 : 4366, 0
7484 11:13:06.425694 140 : 4250, 0
7485 11:13:06.425810 144 : 4252, 0
7486 11:13:06.425941 148 : 4252, 0
7487 11:13:06.428927 152 : 4249, 0
7488 11:13:06.429046 156 : 4250, 0
7489 11:13:06.432201 160 : 4255, 0
7490 11:13:06.432319 164 : 4362, 0
7491 11:13:06.432415 168 : 4255, 0
7492 11:13:06.435374 172 : 4252, 0
7493 11:13:06.435500 176 : 4250, 0
7494 11:13:06.438272 180 : 4249, 0
7495 11:13:06.438380 184 : 4257, 0
7496 11:13:06.438481 188 : 4361, 0
7497 11:13:06.441710 192 : 4252, 0
7498 11:13:06.441815 196 : 4363, 0
7499 11:13:06.445584 200 : 4250, 0
7500 11:13:06.445708 204 : 4363, 0
7501 11:13:06.445804 208 : 4254, 0
7502 11:13:06.448643 212 : 4252, 133
7503 11:13:06.448746 216 : 4250, 3669
7504 11:13:06.451723 220 : 4361, 4137
7505 11:13:06.451838 224 : 4253, 4029
7506 11:13:06.454865 228 : 4250, 4027
7507 11:13:06.454974 232 : 4255, 4029
7508 11:13:06.458617 236 : 4250, 4027
7509 11:13:06.458702 240 : 4252, 4029
7510 11:13:06.458769 244 : 4252, 4030
7511 11:13:06.461671 248 : 4250, 4027
7512 11:13:06.461761 252 : 4252, 4029
7513 11:13:06.465372 256 : 4253, 4026
7514 11:13:06.465456 260 : 4250, 4027
7515 11:13:06.468492 264 : 4255, 4029
7516 11:13:06.468577 268 : 4252, 4029
7517 11:13:06.471742 272 : 4250, 4027
7518 11:13:06.471827 276 : 4250, 4026
7519 11:13:06.475017 280 : 4257, 4032
7520 11:13:06.475105 284 : 4250, 4027
7521 11:13:06.478367 288 : 4250, 4027
7522 11:13:06.478452 292 : 4253, 4029
7523 11:13:06.481977 296 : 4255, 4029
7524 11:13:06.482062 300 : 4363, 4140
7525 11:13:06.485378 304 : 4255, 4029
7526 11:13:06.485463 308 : 4365, 4140
7527 11:13:06.485529 312 : 4250, 4027
7528 11:13:06.488781 316 : 4252, 4030
7529 11:13:06.488865 320 : 4250, 4026
7530 11:13:06.491997 324 : 4252, 4030
7531 11:13:06.492088 328 : 4253, 4029
7532 11:13:06.495160 332 : 4255, 3015
7533 11:13:06.495271 336 : 4252, 25
7534 11:13:06.495407
7535 11:13:06.498457 MIOCK jitter meter ch=0
7536 11:13:06.498544
7537 11:13:06.501745 1T = (336-100) = 236 dly cells
7538 11:13:06.508326 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7539 11:13:06.508447 ==
7540 11:13:06.511571 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 11:13:06.514763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 11:13:06.514840 ==
7543 11:13:06.521838 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7544 11:13:06.525067 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7545 11:13:06.528365 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7546 11:13:06.534928 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7547 11:13:06.543502 [CA 0] Center 44 (14~75) winsize 62
7548 11:13:06.546455 [CA 1] Center 44 (14~74) winsize 61
7549 11:13:06.550095 [CA 2] Center 39 (10~68) winsize 59
7550 11:13:06.553304 [CA 3] Center 39 (10~68) winsize 59
7551 11:13:06.556232 [CA 4] Center 37 (7~67) winsize 61
7552 11:13:06.559962 [CA 5] Center 37 (7~67) winsize 61
7553 11:13:06.560058
7554 11:13:06.562850 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7555 11:13:06.562946
7556 11:13:06.566433 [CATrainingPosCal] consider 1 rank data
7557 11:13:06.570085 u2DelayCellTimex100 = 275/100 ps
7558 11:13:06.576490 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7559 11:13:06.579584 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7560 11:13:06.583425 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7561 11:13:06.586420 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7562 11:13:06.589720 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7563 11:13:06.593026 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7564 11:13:06.593126
7565 11:13:06.596146 CA PerBit enable=1, Macro0, CA PI delay=37
7566 11:13:06.596246
7567 11:13:06.599463 [CBTSetCACLKResult] CA Dly = 37
7568 11:13:06.603304 CS Dly: 10 (0~41)
7569 11:13:06.606599 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7570 11:13:06.609888 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7571 11:13:06.609967 ==
7572 11:13:06.613367 Dram Type= 6, Freq= 0, CH_0, rank 1
7573 11:13:06.616375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 11:13:06.619948 ==
7575 11:13:06.623056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7576 11:13:06.626373 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7577 11:13:06.632831 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7578 11:13:06.639491 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7579 11:13:06.647374 [CA 0] Center 43 (13~74) winsize 62
7580 11:13:06.650444 [CA 1] Center 43 (13~74) winsize 62
7581 11:13:06.653779 [CA 2] Center 39 (10~69) winsize 60
7582 11:13:06.656804 [CA 3] Center 38 (9~68) winsize 60
7583 11:13:06.660513 [CA 4] Center 37 (7~67) winsize 61
7584 11:13:06.663425 [CA 5] Center 36 (6~67) winsize 62
7585 11:13:06.663528
7586 11:13:06.667105 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7587 11:13:06.667247
7588 11:13:06.670233 [CATrainingPosCal] consider 2 rank data
7589 11:13:06.673329 u2DelayCellTimex100 = 275/100 ps
7590 11:13:06.680249 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7591 11:13:06.683451 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7592 11:13:06.686671 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7593 11:13:06.690200 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7594 11:13:06.693383 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7595 11:13:06.696647 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7596 11:13:06.696757
7597 11:13:06.699943 CA PerBit enable=1, Macro0, CA PI delay=37
7598 11:13:06.700068
7599 11:13:06.703055 [CBTSetCACLKResult] CA Dly = 37
7600 11:13:06.706920 CS Dly: 11 (0~44)
7601 11:13:06.710147 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7602 11:13:06.713683 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7603 11:13:06.713769
7604 11:13:06.716668 ----->DramcWriteLeveling(PI) begin...
7605 11:13:06.716755 ==
7606 11:13:06.719975 Dram Type= 6, Freq= 0, CH_0, rank 0
7607 11:13:06.726701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 11:13:06.726792 ==
7609 11:13:06.730089 Write leveling (Byte 0): 34 => 34
7610 11:13:06.733437 Write leveling (Byte 1): 26 => 26
7611 11:13:06.733521 DramcWriteLeveling(PI) end<-----
7612 11:13:06.733590
7613 11:13:06.736553 ==
7614 11:13:06.739820 Dram Type= 6, Freq= 0, CH_0, rank 0
7615 11:13:06.743035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 11:13:06.743113 ==
7617 11:13:06.746205 [Gating] SW mode calibration
7618 11:13:06.753461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7619 11:13:06.756774 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7620 11:13:06.763015 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 11:13:06.766685 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 11:13:06.769631 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 11:13:06.775981 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 11:13:06.779878 1 4 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7625 11:13:06.782904 1 4 20 | B1->B0 | 2423 3131 | 1 1 | (0 0) (1 1)
7626 11:13:06.789270 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7627 11:13:06.792860 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 11:13:06.796208 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7629 11:13:06.802674 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7630 11:13:06.805875 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7631 11:13:06.809150 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7632 11:13:06.816281 1 5 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7633 11:13:06.819496 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (0 1) (1 0)
7634 11:13:06.822821 1 5 24 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
7635 11:13:06.829301 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 11:13:06.832627 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 11:13:06.835840 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 11:13:06.842610 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 11:13:06.845786 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 11:13:06.848998 1 6 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7641 11:13:06.856092 1 6 20 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
7642 11:13:06.859572 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
7643 11:13:06.862743 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 11:13:06.869270 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 11:13:06.872482 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 11:13:06.875423 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 11:13:06.879076 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 11:13:06.885858 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7649 11:13:06.888938 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7650 11:13:06.892505 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7651 11:13:06.899201 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 11:13:06.902500 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 11:13:06.905724 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 11:13:06.912238 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 11:13:06.915563 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 11:13:06.918857 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 11:13:06.925436 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 11:13:06.928675 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 11:13:06.932442 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 11:13:06.938773 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:13:06.942135 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:13:06.945466 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 11:13:06.951933 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7664 11:13:06.955230 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7665 11:13:06.958399 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7666 11:13:06.962297 Total UI for P1: 0, mck2ui 16
7667 11:13:06.965667 best dqsien dly found for B0: ( 1, 9, 14)
7668 11:13:06.972042 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7669 11:13:06.975439 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 11:13:06.978757 Total UI for P1: 0, mck2ui 16
7671 11:13:06.982089 best dqsien dly found for B1: ( 1, 9, 22)
7672 11:13:06.985083 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7673 11:13:06.988754 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7674 11:13:06.988871
7675 11:13:06.991710 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7676 11:13:06.994866 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7677 11:13:06.998357 [Gating] SW calibration Done
7678 11:13:06.998471 ==
7679 11:13:07.001392 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 11:13:07.005050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 11:13:07.008277 ==
7682 11:13:07.008361 RX Vref Scan: 0
7683 11:13:07.008457
7684 11:13:07.011548 RX Vref 0 -> 0, step: 1
7685 11:13:07.011633
7686 11:13:07.011706 RX Delay 0 -> 252, step: 8
7687 11:13:07.018522 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7688 11:13:07.021785 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7689 11:13:07.025039 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7690 11:13:07.028918 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7691 11:13:07.032161 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7692 11:13:07.038497 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7693 11:13:07.041588 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7694 11:13:07.044923 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7695 11:13:07.048339 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7696 11:13:07.051455 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7697 11:13:07.058566 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7698 11:13:07.061808 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7699 11:13:07.065110 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7700 11:13:07.068367 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7701 11:13:07.074681 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7702 11:13:07.078041 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7703 11:13:07.078150 ==
7704 11:13:07.081535 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 11:13:07.084638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 11:13:07.084745 ==
7707 11:13:07.088011 DQS Delay:
7708 11:13:07.088086 DQS0 = 0, DQS1 = 0
7709 11:13:07.088150 DQM Delay:
7710 11:13:07.091617 DQM0 = 132, DQM1 = 124
7711 11:13:07.091696 DQ Delay:
7712 11:13:07.095221 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7713 11:13:07.098120 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7714 11:13:07.101249 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =119
7715 11:13:07.108349 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7716 11:13:07.108430
7717 11:13:07.108493
7718 11:13:07.108552 ==
7719 11:13:07.111259 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 11:13:07.114779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 11:13:07.114857 ==
7722 11:13:07.114938
7723 11:13:07.115000
7724 11:13:07.117924 TX Vref Scan disable
7725 11:13:07.117996 == TX Byte 0 ==
7726 11:13:07.125089 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7727 11:13:07.127744 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7728 11:13:07.127821 == TX Byte 1 ==
7729 11:13:07.134845 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7730 11:13:07.138241 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7731 11:13:07.138313 ==
7732 11:13:07.141409 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 11:13:07.144437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 11:13:07.144522 ==
7735 11:13:07.160160
7736 11:13:07.164034 TX Vref early break, caculate TX vref
7737 11:13:07.167332 TX Vref=16, minBit 1, minWin=21, winSum=356
7738 11:13:07.170636 TX Vref=18, minBit 12, minWin=21, winSum=361
7739 11:13:07.173876 TX Vref=20, minBit 4, minWin=22, winSum=372
7740 11:13:07.177134 TX Vref=22, minBit 1, minWin=23, winSum=387
7741 11:13:07.180424 TX Vref=24, minBit 6, minWin=23, winSum=395
7742 11:13:07.186852 TX Vref=26, minBit 4, minWin=24, winSum=405
7743 11:13:07.190759 TX Vref=28, minBit 4, minWin=24, winSum=411
7744 11:13:07.194079 TX Vref=30, minBit 4, minWin=24, winSum=417
7745 11:13:07.197261 TX Vref=32, minBit 4, minWin=24, winSum=411
7746 11:13:07.200411 TX Vref=34, minBit 0, minWin=24, winSum=403
7747 11:13:07.203938 TX Vref=36, minBit 4, minWin=23, winSum=388
7748 11:13:07.210552 [TxChooseVref] Worse bit 4, Min win 24, Win sum 417, Final Vref 30
7749 11:13:07.210641
7750 11:13:07.213508 Final TX Range 0 Vref 30
7751 11:13:07.213592
7752 11:13:07.213657 ==
7753 11:13:07.216861 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 11:13:07.220447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 11:13:07.220531 ==
7756 11:13:07.220604
7757 11:13:07.220675
7758 11:13:07.223323 TX Vref Scan disable
7759 11:13:07.230305 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7760 11:13:07.230391 == TX Byte 0 ==
7761 11:13:07.233876 u2DelayCellOfst[0]=10 cells (3 PI)
7762 11:13:07.236993 u2DelayCellOfst[1]=17 cells (5 PI)
7763 11:13:07.240160 u2DelayCellOfst[2]=10 cells (3 PI)
7764 11:13:07.243356 u2DelayCellOfst[3]=10 cells (3 PI)
7765 11:13:07.247051 u2DelayCellOfst[4]=7 cells (2 PI)
7766 11:13:07.250138 u2DelayCellOfst[5]=0 cells (0 PI)
7767 11:13:07.253392 u2DelayCellOfst[6]=17 cells (5 PI)
7768 11:13:07.257177 u2DelayCellOfst[7]=17 cells (5 PI)
7769 11:13:07.260355 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7770 11:13:07.263554 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7771 11:13:07.266742 == TX Byte 1 ==
7772 11:13:07.270121 u2DelayCellOfst[8]=0 cells (0 PI)
7773 11:13:07.273402 u2DelayCellOfst[9]=3 cells (1 PI)
7774 11:13:07.273484 u2DelayCellOfst[10]=7 cells (2 PI)
7775 11:13:07.276719 u2DelayCellOfst[11]=0 cells (0 PI)
7776 11:13:07.279870 u2DelayCellOfst[12]=10 cells (3 PI)
7777 11:13:07.283748 u2DelayCellOfst[13]=10 cells (3 PI)
7778 11:13:07.286952 u2DelayCellOfst[14]=14 cells (4 PI)
7779 11:13:07.290170 u2DelayCellOfst[15]=10 cells (3 PI)
7780 11:13:07.293399 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7781 11:13:07.299908 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7782 11:13:07.299991 DramC Write-DBI on
7783 11:13:07.300056 ==
7784 11:13:07.303293 Dram Type= 6, Freq= 0, CH_0, rank 0
7785 11:13:07.310048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7786 11:13:07.310135 ==
7787 11:13:07.310201
7788 11:13:07.310261
7789 11:13:07.310319 TX Vref Scan disable
7790 11:13:07.314058 == TX Byte 0 ==
7791 11:13:07.317566 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7792 11:13:07.320437 == TX Byte 1 ==
7793 11:13:07.324331 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7794 11:13:07.327051 DramC Write-DBI off
7795 11:13:07.327135
7796 11:13:07.327200 [DATLAT]
7797 11:13:07.327283 Freq=1600, CH0 RK0
7798 11:13:07.327344
7799 11:13:07.330618 DATLAT Default: 0xf
7800 11:13:07.330701 0, 0xFFFF, sum = 0
7801 11:13:07.333661 1, 0xFFFF, sum = 0
7802 11:13:07.337327 2, 0xFFFF, sum = 0
7803 11:13:07.337411 3, 0xFFFF, sum = 0
7804 11:13:07.340654 4, 0xFFFF, sum = 0
7805 11:13:07.340739 5, 0xFFFF, sum = 0
7806 11:13:07.343854 6, 0xFFFF, sum = 0
7807 11:13:07.343939 7, 0xFFFF, sum = 0
7808 11:13:07.347028 8, 0xFFFF, sum = 0
7809 11:13:07.347113 9, 0xFFFF, sum = 0
7810 11:13:07.350176 10, 0xFFFF, sum = 0
7811 11:13:07.350261 11, 0xFFFF, sum = 0
7812 11:13:07.353885 12, 0xFFFF, sum = 0
7813 11:13:07.353969 13, 0xFFFF, sum = 0
7814 11:13:07.357227 14, 0x0, sum = 1
7815 11:13:07.357311 15, 0x0, sum = 2
7816 11:13:07.360452 16, 0x0, sum = 3
7817 11:13:07.360536 17, 0x0, sum = 4
7818 11:13:07.363903 best_step = 15
7819 11:13:07.363985
7820 11:13:07.364050 ==
7821 11:13:07.367223 Dram Type= 6, Freq= 0, CH_0, rank 0
7822 11:13:07.370451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7823 11:13:07.370535 ==
7824 11:13:07.373648 RX Vref Scan: 1
7825 11:13:07.373731
7826 11:13:07.373796 Set Vref Range= 24 -> 127
7827 11:13:07.373857
7828 11:13:07.376917 RX Vref 24 -> 127, step: 1
7829 11:13:07.377000
7830 11:13:07.380200 RX Delay 11 -> 252, step: 4
7831 11:13:07.380283
7832 11:13:07.383516 Set Vref, RX VrefLevel [Byte0]: 24
7833 11:13:07.386866 [Byte1]: 24
7834 11:13:07.386949
7835 11:13:07.390138 Set Vref, RX VrefLevel [Byte0]: 25
7836 11:13:07.393454 [Byte1]: 25
7837 11:13:07.393538
7838 11:13:07.396726 Set Vref, RX VrefLevel [Byte0]: 26
7839 11:13:07.400120 [Byte1]: 26
7840 11:13:07.404080
7841 11:13:07.404162 Set Vref, RX VrefLevel [Byte0]: 27
7842 11:13:07.407379 [Byte1]: 27
7843 11:13:07.411941
7844 11:13:07.412023 Set Vref, RX VrefLevel [Byte0]: 28
7845 11:13:07.415688 [Byte1]: 28
7846 11:13:07.419579
7847 11:13:07.419662 Set Vref, RX VrefLevel [Byte0]: 29
7848 11:13:07.422939 [Byte1]: 29
7849 11:13:07.427197
7850 11:13:07.427294 Set Vref, RX VrefLevel [Byte0]: 30
7851 11:13:07.430749 [Byte1]: 30
7852 11:13:07.434513
7853 11:13:07.434596 Set Vref, RX VrefLevel [Byte0]: 31
7854 11:13:07.438240 [Byte1]: 31
7855 11:13:07.442514
7856 11:13:07.442597 Set Vref, RX VrefLevel [Byte0]: 32
7857 11:13:07.445460 [Byte1]: 32
7858 11:13:07.449819
7859 11:13:07.449902 Set Vref, RX VrefLevel [Byte0]: 33
7860 11:13:07.453032 [Byte1]: 33
7861 11:13:07.457343
7862 11:13:07.457416 Set Vref, RX VrefLevel [Byte0]: 34
7863 11:13:07.461277 [Byte1]: 34
7864 11:13:07.465057
7865 11:13:07.465129 Set Vref, RX VrefLevel [Byte0]: 35
7866 11:13:07.468323 [Byte1]: 35
7867 11:13:07.472677
7868 11:13:07.472760 Set Vref, RX VrefLevel [Byte0]: 36
7869 11:13:07.476164 [Byte1]: 36
7870 11:13:07.480575
7871 11:13:07.480656 Set Vref, RX VrefLevel [Byte0]: 37
7872 11:13:07.486738 [Byte1]: 37
7873 11:13:07.486820
7874 11:13:07.490012 Set Vref, RX VrefLevel [Byte0]: 38
7875 11:13:07.493321 [Byte1]: 38
7876 11:13:07.493405
7877 11:13:07.496594 Set Vref, RX VrefLevel [Byte0]: 39
7878 11:13:07.499910 [Byte1]: 39
7879 11:13:07.499992
7880 11:13:07.503860 Set Vref, RX VrefLevel [Byte0]: 40
7881 11:13:07.506451 [Byte1]: 40
7882 11:13:07.511046
7883 11:13:07.511135 Set Vref, RX VrefLevel [Byte0]: 41
7884 11:13:07.514592 [Byte1]: 41
7885 11:13:07.518895
7886 11:13:07.518974 Set Vref, RX VrefLevel [Byte0]: 42
7887 11:13:07.521973 [Byte1]: 42
7888 11:13:07.525963
7889 11:13:07.526041 Set Vref, RX VrefLevel [Byte0]: 43
7890 11:13:07.529908 [Byte1]: 43
7891 11:13:07.533502
7892 11:13:07.533597 Set Vref, RX VrefLevel [Byte0]: 44
7893 11:13:07.537097 [Byte1]: 44
7894 11:13:07.541631
7895 11:13:07.541768 Set Vref, RX VrefLevel [Byte0]: 45
7896 11:13:07.544515 [Byte1]: 45
7897 11:13:07.548988
7898 11:13:07.549068 Set Vref, RX VrefLevel [Byte0]: 46
7899 11:13:07.552415 [Byte1]: 46
7900 11:13:07.556341
7901 11:13:07.556414 Set Vref, RX VrefLevel [Byte0]: 47
7902 11:13:07.560108 [Byte1]: 47
7903 11:13:07.564350
7904 11:13:07.564450 Set Vref, RX VrefLevel [Byte0]: 48
7905 11:13:07.567534 [Byte1]: 48
7906 11:13:07.571955
7907 11:13:07.572034 Set Vref, RX VrefLevel [Byte0]: 49
7908 11:13:07.575133 [Byte1]: 49
7909 11:13:07.579725
7910 11:13:07.579827 Set Vref, RX VrefLevel [Byte0]: 50
7911 11:13:07.586544 [Byte1]: 50
7912 11:13:07.586623
7913 11:13:07.588943 Set Vref, RX VrefLevel [Byte0]: 51
7914 11:13:07.592675 [Byte1]: 51
7915 11:13:07.592750
7916 11:13:07.595997 Set Vref, RX VrefLevel [Byte0]: 52
7917 11:13:07.599279 [Byte1]: 52
7918 11:13:07.599384
7919 11:13:07.602773 Set Vref, RX VrefLevel [Byte0]: 53
7920 11:13:07.605960 [Byte1]: 53
7921 11:13:07.610094
7922 11:13:07.610179 Set Vref, RX VrefLevel [Byte0]: 54
7923 11:13:07.613121 [Byte1]: 54
7924 11:13:07.617916
7925 11:13:07.617999 Set Vref, RX VrefLevel [Byte0]: 55
7926 11:13:07.620997 [Byte1]: 55
7927 11:13:07.625529
7928 11:13:07.625641 Set Vref, RX VrefLevel [Byte0]: 56
7929 11:13:07.628843 [Byte1]: 56
7930 11:13:07.632774
7931 11:13:07.632856 Set Vref, RX VrefLevel [Byte0]: 57
7932 11:13:07.635907 [Byte1]: 57
7933 11:13:07.640658
7934 11:13:07.640740 Set Vref, RX VrefLevel [Byte0]: 58
7935 11:13:07.643760 [Byte1]: 58
7936 11:13:07.647957
7937 11:13:07.648039 Set Vref, RX VrefLevel [Byte0]: 59
7938 11:13:07.651011 [Byte1]: 59
7939 11:13:07.655925
7940 11:13:07.656007 Set Vref, RX VrefLevel [Byte0]: 60
7941 11:13:07.658983 [Byte1]: 60
7942 11:13:07.663397
7943 11:13:07.663479 Set Vref, RX VrefLevel [Byte0]: 61
7944 11:13:07.666369 [Byte1]: 61
7945 11:13:07.670792
7946 11:13:07.670874 Set Vref, RX VrefLevel [Byte0]: 62
7947 11:13:07.674094 [Byte1]: 62
7948 11:13:07.678663
7949 11:13:07.678747 Set Vref, RX VrefLevel [Byte0]: 63
7950 11:13:07.682006 [Byte1]: 63
7951 11:13:07.685986
7952 11:13:07.686070 Set Vref, RX VrefLevel [Byte0]: 64
7953 11:13:07.689291 [Byte1]: 64
7954 11:13:07.693924
7955 11:13:07.694006 Set Vref, RX VrefLevel [Byte0]: 65
7956 11:13:07.697283 [Byte1]: 65
7957 11:13:07.701244
7958 11:13:07.701342 Set Vref, RX VrefLevel [Byte0]: 66
7959 11:13:07.704460 [Byte1]: 66
7960 11:13:07.709000
7961 11:13:07.709083 Set Vref, RX VrefLevel [Byte0]: 67
7962 11:13:07.712357 [Byte1]: 67
7963 11:13:07.716888
7964 11:13:07.716971 Set Vref, RX VrefLevel [Byte0]: 68
7965 11:13:07.719841 [Byte1]: 68
7966 11:13:07.724128
7967 11:13:07.724211 Set Vref, RX VrefLevel [Byte0]: 69
7968 11:13:07.727261 [Byte1]: 69
7969 11:13:07.731616
7970 11:13:07.731699 Set Vref, RX VrefLevel [Byte0]: 70
7971 11:13:07.735044 [Byte1]: 70
7972 11:13:07.739222
7973 11:13:07.739320 Set Vref, RX VrefLevel [Byte0]: 71
7974 11:13:07.742937 [Byte1]: 71
7975 11:13:07.746777
7976 11:13:07.746860 Set Vref, RX VrefLevel [Byte0]: 72
7977 11:13:07.750595 [Byte1]: 72
7978 11:13:07.754555
7979 11:13:07.754638 Set Vref, RX VrefLevel [Byte0]: 73
7980 11:13:07.757982 [Byte1]: 73
7981 11:13:07.762205
7982 11:13:07.762288 Set Vref, RX VrefLevel [Byte0]: 74
7983 11:13:07.765275 [Byte1]: 74
7984 11:13:07.769956
7985 11:13:07.770039 Set Vref, RX VrefLevel [Byte0]: 75
7986 11:13:07.773092 [Byte1]: 75
7987 11:13:07.777288
7988 11:13:07.777371 Set Vref, RX VrefLevel [Byte0]: 76
7989 11:13:07.780915 [Byte1]: 76
7990 11:13:07.784750
7991 11:13:07.784832 Final RX Vref Byte 0 = 62 to rank0
7992 11:13:07.788502 Final RX Vref Byte 1 = 61 to rank0
7993 11:13:07.791805 Final RX Vref Byte 0 = 62 to rank1
7994 11:13:07.795001 Final RX Vref Byte 1 = 61 to rank1==
7995 11:13:07.798278 Dram Type= 6, Freq= 0, CH_0, rank 0
7996 11:13:07.804982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 11:13:07.805062 ==
7998 11:13:07.805128 DQS Delay:
7999 11:13:07.805188 DQS0 = 0, DQS1 = 0
8000 11:13:07.808174 DQM Delay:
8001 11:13:07.808247 DQM0 = 130, DQM1 = 121
8002 11:13:07.811495 DQ Delay:
8003 11:13:07.814785 DQ0 =132, DQ1 =132, DQ2 =126, DQ3 =126
8004 11:13:07.817903 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8005 11:13:07.821332 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
8006 11:13:07.825150 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8007 11:13:07.825234
8008 11:13:07.825298
8009 11:13:07.825358
8010 11:13:07.827921 [DramC_TX_OE_Calibration] TA2
8011 11:13:07.831523 Original DQ_B0 (3 6) =30, OEN = 27
8012 11:13:07.834585 Original DQ_B1 (3 6) =30, OEN = 27
8013 11:13:07.837874 24, 0x0, End_B0=24 End_B1=24
8014 11:13:07.837959 25, 0x0, End_B0=25 End_B1=25
8015 11:13:07.841174 26, 0x0, End_B0=26 End_B1=26
8016 11:13:07.844331 27, 0x0, End_B0=27 End_B1=27
8017 11:13:07.847574 28, 0x0, End_B0=28 End_B1=28
8018 11:13:07.850886 29, 0x0, End_B0=29 End_B1=29
8019 11:13:07.850971 30, 0x0, End_B0=30 End_B1=30
8020 11:13:07.854110 31, 0x4141, End_B0=30 End_B1=30
8021 11:13:07.857998 Byte0 end_step=30 best_step=27
8022 11:13:07.861048 Byte1 end_step=30 best_step=27
8023 11:13:07.864327 Byte0 TX OE(2T, 0.5T) = (3, 3)
8024 11:13:07.867954 Byte1 TX OE(2T, 0.5T) = (3, 3)
8025 11:13:07.868037
8026 11:13:07.868102
8027 11:13:07.874132 [DQSOSCAuto] RK0, (LSB)MR18= 0x1205, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 400 ps
8028 11:13:07.877697 CH0 RK0: MR19=303, MR18=1205
8029 11:13:07.884538 CH0_RK0: MR19=0x303, MR18=0x1205, DQSOSC=400, MR23=63, INC=23, DEC=15
8030 11:13:07.884626
8031 11:13:07.887435 ----->DramcWriteLeveling(PI) begin...
8032 11:13:07.887524 ==
8033 11:13:07.890905 Dram Type= 6, Freq= 0, CH_0, rank 1
8034 11:13:07.894116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 11:13:07.894236 ==
8036 11:13:07.897808 Write leveling (Byte 0): 34 => 34
8037 11:13:07.900991 Write leveling (Byte 1): 29 => 29
8038 11:13:07.904336 DramcWriteLeveling(PI) end<-----
8039 11:13:07.904421
8040 11:13:07.904505 ==
8041 11:13:07.907893 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 11:13:07.911008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 11:13:07.911094 ==
8044 11:13:07.914271 [Gating] SW mode calibration
8045 11:13:07.920700 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8046 11:13:07.927228 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8047 11:13:07.930436 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 11:13:07.937623 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 11:13:07.940704 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8050 11:13:07.943777 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
8051 11:13:07.950948 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8052 11:13:07.954159 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
8053 11:13:07.957322 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 11:13:07.960622 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 11:13:07.967397 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 11:13:07.970566 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 11:13:07.974305 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8058 11:13:07.980588 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8059 11:13:07.983746 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8060 11:13:07.987240 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
8061 11:13:07.994121 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8062 11:13:07.997196 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 11:13:08.000816 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 11:13:08.007254 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 11:13:08.010529 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8066 11:13:08.013826 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8067 11:13:08.020465 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8068 11:13:08.023654 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8069 11:13:08.026904 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 11:13:08.033543 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 11:13:08.037441 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 11:13:08.040539 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 11:13:08.046926 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8074 11:13:08.050258 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8075 11:13:08.053481 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8076 11:13:08.060057 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8077 11:13:08.063335 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 11:13:08.066976 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 11:13:08.073284 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 11:13:08.076727 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 11:13:08.079879 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 11:13:08.086571 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 11:13:08.090150 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 11:13:08.093308 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 11:13:08.099944 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:13:08.103491 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:13:08.106514 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:13:08.110296 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:13:08.116963 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8090 11:13:08.120279 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8091 11:13:08.123565 Total UI for P1: 0, mck2ui 16
8092 11:13:08.126880 best dqsien dly found for B0: ( 1, 9, 8)
8093 11:13:08.130113 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8094 11:13:08.136643 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8095 11:13:08.139909 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 11:13:08.143280 Total UI for P1: 0, mck2ui 16
8097 11:13:08.146517 best dqsien dly found for B1: ( 1, 9, 20)
8098 11:13:08.149647 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8099 11:13:08.153565 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8100 11:13:08.153700
8101 11:13:08.156759 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8102 11:13:08.160023 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8103 11:13:08.163172 [Gating] SW calibration Done
8104 11:13:08.163282 ==
8105 11:13:08.166325 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 11:13:08.173303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 11:13:08.173414 ==
8108 11:13:08.173511 RX Vref Scan: 0
8109 11:13:08.173577
8110 11:13:08.176356 RX Vref 0 -> 0, step: 1
8111 11:13:08.176439
8112 11:13:08.179636 RX Delay 0 -> 252, step: 8
8113 11:13:08.182788 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8114 11:13:08.186116 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8115 11:13:08.189843 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8116 11:13:08.192879 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8117 11:13:08.199816 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8118 11:13:08.202885 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8119 11:13:08.206141 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8120 11:13:08.209484 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8121 11:13:08.213040 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8122 11:13:08.219199 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8123 11:13:08.223231 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8124 11:13:08.226482 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8125 11:13:08.229792 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8126 11:13:08.233092 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8127 11:13:08.239618 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8128 11:13:08.242856 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8129 11:13:08.242927 ==
8130 11:13:08.246261 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 11:13:08.249462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 11:13:08.249547 ==
8133 11:13:08.252504 DQS Delay:
8134 11:13:08.252587 DQS0 = 0, DQS1 = 0
8135 11:13:08.252652 DQM Delay:
8136 11:13:08.255869 DQM0 = 131, DQM1 = 124
8137 11:13:08.255952 DQ Delay:
8138 11:13:08.259767 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8139 11:13:08.263067 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8140 11:13:08.266314 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8141 11:13:08.272786 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8142 11:13:08.272869
8143 11:13:08.272934
8144 11:13:08.272995 ==
8145 11:13:08.275913 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 11:13:08.279513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 11:13:08.279602 ==
8148 11:13:08.279669
8149 11:13:08.279730
8150 11:13:08.282766 TX Vref Scan disable
8151 11:13:08.282850 == TX Byte 0 ==
8152 11:13:08.289442 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8153 11:13:08.292718 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8154 11:13:08.292802 == TX Byte 1 ==
8155 11:13:08.299331 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8156 11:13:08.302368 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8157 11:13:08.302452 ==
8158 11:13:08.305595 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 11:13:08.309235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 11:13:08.309321 ==
8161 11:13:08.325220
8162 11:13:08.328353 TX Vref early break, caculate TX vref
8163 11:13:08.331676 TX Vref=16, minBit 5, minWin=22, winSum=379
8164 11:13:08.334863 TX Vref=18, minBit 1, minWin=23, winSum=387
8165 11:13:08.338180 TX Vref=20, minBit 1, minWin=23, winSum=395
8166 11:13:08.341534 TX Vref=22, minBit 0, minWin=24, winSum=405
8167 11:13:08.344671 TX Vref=24, minBit 1, minWin=24, winSum=411
8168 11:13:08.351275 TX Vref=26, minBit 4, minWin=24, winSum=419
8169 11:13:08.354967 TX Vref=28, minBit 0, minWin=25, winSum=424
8170 11:13:08.358204 TX Vref=30, minBit 0, minWin=25, winSum=420
8171 11:13:08.361527 TX Vref=32, minBit 2, minWin=25, winSum=417
8172 11:13:08.364644 TX Vref=34, minBit 7, minWin=24, winSum=408
8173 11:13:08.368659 TX Vref=36, minBit 0, minWin=24, winSum=401
8174 11:13:08.375140 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8175 11:13:08.375227
8176 11:13:08.378484 Final TX Range 0 Vref 28
8177 11:13:08.378568
8178 11:13:08.378635 ==
8179 11:13:08.381646 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 11:13:08.384663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 11:13:08.384774 ==
8182 11:13:08.384877
8183 11:13:08.384969
8184 11:13:08.387900 TX Vref Scan disable
8185 11:13:08.394441 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8186 11:13:08.394555 == TX Byte 0 ==
8187 11:13:08.398466 u2DelayCellOfst[0]=14 cells (4 PI)
8188 11:13:08.401747 u2DelayCellOfst[1]=17 cells (5 PI)
8189 11:13:08.404737 u2DelayCellOfst[2]=10 cells (3 PI)
8190 11:13:08.407874 u2DelayCellOfst[3]=10 cells (3 PI)
8191 11:13:08.411161 u2DelayCellOfst[4]=10 cells (3 PI)
8192 11:13:08.414735 u2DelayCellOfst[5]=0 cells (0 PI)
8193 11:13:08.417693 u2DelayCellOfst[6]=17 cells (5 PI)
8194 11:13:08.421536 u2DelayCellOfst[7]=17 cells (5 PI)
8195 11:13:08.424610 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8196 11:13:08.427658 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8197 11:13:08.431469 == TX Byte 1 ==
8198 11:13:08.434775 u2DelayCellOfst[8]=0 cells (0 PI)
8199 11:13:08.437944 u2DelayCellOfst[9]=3 cells (1 PI)
8200 11:13:08.438029 u2DelayCellOfst[10]=7 cells (2 PI)
8201 11:13:08.441129 u2DelayCellOfst[11]=3 cells (1 PI)
8202 11:13:08.444511 u2DelayCellOfst[12]=14 cells (4 PI)
8203 11:13:08.447752 u2DelayCellOfst[13]=14 cells (4 PI)
8204 11:13:08.451080 u2DelayCellOfst[14]=14 cells (4 PI)
8205 11:13:08.454427 u2DelayCellOfst[15]=10 cells (3 PI)
8206 11:13:08.458405 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8207 11:13:08.464706 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8208 11:13:08.464791 DramC Write-DBI on
8209 11:13:08.464857 ==
8210 11:13:08.468096 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 11:13:08.474578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 11:13:08.474675 ==
8213 11:13:08.474751
8214 11:13:08.474821
8215 11:13:08.474894 TX Vref Scan disable
8216 11:13:08.478563 == TX Byte 0 ==
8217 11:13:08.481665 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8218 11:13:08.484936 == TX Byte 1 ==
8219 11:13:08.488568 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8220 11:13:08.491930 DramC Write-DBI off
8221 11:13:08.492054
8222 11:13:08.492152 [DATLAT]
8223 11:13:08.492243 Freq=1600, CH0 RK1
8224 11:13:08.492331
8225 11:13:08.495215 DATLAT Default: 0xf
8226 11:13:08.495360 0, 0xFFFF, sum = 0
8227 11:13:08.498418 1, 0xFFFF, sum = 0
8228 11:13:08.501630 2, 0xFFFF, sum = 0
8229 11:13:08.501787 3, 0xFFFF, sum = 0
8230 11:13:08.504982 4, 0xFFFF, sum = 0
8231 11:13:08.505161 5, 0xFFFF, sum = 0
8232 11:13:08.508320 6, 0xFFFF, sum = 0
8233 11:13:08.508618 7, 0xFFFF, sum = 0
8234 11:13:08.511412 8, 0xFFFF, sum = 0
8235 11:13:08.511683 9, 0xFFFF, sum = 0
8236 11:13:08.515196 10, 0xFFFF, sum = 0
8237 11:13:08.515486 11, 0xFFFF, sum = 0
8238 11:13:08.518936 12, 0xFFFF, sum = 0
8239 11:13:08.519276 13, 0xFFFF, sum = 0
8240 11:13:08.521894 14, 0x0, sum = 1
8241 11:13:08.522206 15, 0x0, sum = 2
8242 11:13:08.525420 16, 0x0, sum = 3
8243 11:13:08.525863 17, 0x0, sum = 4
8244 11:13:08.528675 best_step = 15
8245 11:13:08.529296
8246 11:13:08.529805 ==
8247 11:13:08.531783 Dram Type= 6, Freq= 0, CH_0, rank 1
8248 11:13:08.535478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8249 11:13:08.535915 ==
8250 11:13:08.538610 RX Vref Scan: 0
8251 11:13:08.539058
8252 11:13:08.539443 RX Vref 0 -> 0, step: 1
8253 11:13:08.539769
8254 11:13:08.541941 RX Delay 11 -> 252, step: 4
8255 11:13:08.545275 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8256 11:13:08.551772 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8257 11:13:08.555058 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8258 11:13:08.558352 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8259 11:13:08.561642 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8260 11:13:08.564924 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8261 11:13:08.571856 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8262 11:13:08.575387 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8263 11:13:08.578068 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8264 11:13:08.581483 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8265 11:13:08.584763 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8266 11:13:08.591083 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8267 11:13:08.594741 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8268 11:13:08.597854 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8269 11:13:08.601086 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8270 11:13:08.604818 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8271 11:13:08.608166 ==
8272 11:13:08.611491 Dram Type= 6, Freq= 0, CH_0, rank 1
8273 11:13:08.614572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 11:13:08.614655 ==
8275 11:13:08.614720 DQS Delay:
8276 11:13:08.617807 DQS0 = 0, DQS1 = 0
8277 11:13:08.617889 DQM Delay:
8278 11:13:08.621034 DQM0 = 127, DQM1 = 122
8279 11:13:08.621116 DQ Delay:
8280 11:13:08.624610 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8281 11:13:08.627603 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8282 11:13:08.631253 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8283 11:13:08.634306 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8284 11:13:08.634388
8285 11:13:08.634452
8286 11:13:08.634511
8287 11:13:08.637420 [DramC_TX_OE_Calibration] TA2
8288 11:13:08.641012 Original DQ_B0 (3 6) =30, OEN = 27
8289 11:13:08.644223 Original DQ_B1 (3 6) =30, OEN = 27
8290 11:13:08.647337 24, 0x0, End_B0=24 End_B1=24
8291 11:13:08.651204 25, 0x0, End_B0=25 End_B1=25
8292 11:13:08.651337 26, 0x0, End_B0=26 End_B1=26
8293 11:13:08.654552 27, 0x0, End_B0=27 End_B1=27
8294 11:13:08.657839 28, 0x0, End_B0=28 End_B1=28
8295 11:13:08.661005 29, 0x0, End_B0=29 End_B1=29
8296 11:13:08.664443 30, 0x0, End_B0=30 End_B1=30
8297 11:13:08.664526 31, 0x4141, End_B0=30 End_B1=30
8298 11:13:08.667569 Byte0 end_step=30 best_step=27
8299 11:13:08.670645 Byte1 end_step=30 best_step=27
8300 11:13:08.673936 Byte0 TX OE(2T, 0.5T) = (3, 3)
8301 11:13:08.677171 Byte1 TX OE(2T, 0.5T) = (3, 3)
8302 11:13:08.677254
8303 11:13:08.677318
8304 11:13:08.684297 [DQSOSCAuto] RK1, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8305 11:13:08.687466 CH0 RK1: MR19=303, MR18=180D
8306 11:13:08.694147 CH0_RK1: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8307 11:13:08.697763 [RxdqsGatingPostProcess] freq 1600
8308 11:13:08.704135 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8309 11:13:08.704238 best DQS0 dly(2T, 0.5T) = (1, 1)
8310 11:13:08.707147 best DQS1 dly(2T, 0.5T) = (1, 1)
8311 11:13:08.711022 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8312 11:13:08.714297 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8313 11:13:08.717636 best DQS0 dly(2T, 0.5T) = (1, 1)
8314 11:13:08.721014 best DQS1 dly(2T, 0.5T) = (1, 1)
8315 11:13:08.724257 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8316 11:13:08.727377 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8317 11:13:08.730559 Pre-setting of DQS Precalculation
8318 11:13:08.734044 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8319 11:13:08.734157 ==
8320 11:13:08.737168 Dram Type= 6, Freq= 0, CH_1, rank 0
8321 11:13:08.743982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 11:13:08.744079 ==
8323 11:13:08.747534 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8324 11:13:08.753817 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8325 11:13:08.757214 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8326 11:13:08.763849 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8327 11:13:08.771260 [CA 0] Center 43 (15~72) winsize 58
8328 11:13:08.775033 [CA 1] Center 43 (14~72) winsize 59
8329 11:13:08.778064 [CA 2] Center 38 (10~67) winsize 58
8330 11:13:08.781309 [CA 3] Center 37 (8~66) winsize 59
8331 11:13:08.784690 [CA 4] Center 38 (8~68) winsize 61
8332 11:13:08.787910 [CA 5] Center 37 (8~66) winsize 59
8333 11:13:08.788147
8334 11:13:08.791223 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8335 11:13:08.794397
8336 11:13:08.797678 [CATrainingPosCal] consider 1 rank data
8337 11:13:08.797916 u2DelayCellTimex100 = 275/100 ps
8338 11:13:08.804924 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8339 11:13:08.807421 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8340 11:13:08.810741 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8341 11:13:08.814092 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8342 11:13:08.817260 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8343 11:13:08.820691 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8344 11:13:08.820929
8345 11:13:08.824556 CA PerBit enable=1, Macro0, CA PI delay=37
8346 11:13:08.824792
8347 11:13:08.828067 [CBTSetCACLKResult] CA Dly = 37
8348 11:13:08.831123 CS Dly: 9 (0~40)
8349 11:13:08.834527 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8350 11:13:08.837722 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8351 11:13:08.837811 ==
8352 11:13:08.840563 Dram Type= 6, Freq= 0, CH_1, rank 1
8353 11:13:08.847239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8354 11:13:08.847321 ==
8355 11:13:08.850935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8356 11:13:08.857755 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8357 11:13:08.860734 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8358 11:13:08.867788 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8359 11:13:08.875037 [CA 0] Center 42 (13~72) winsize 60
8360 11:13:08.878038 [CA 1] Center 42 (14~71) winsize 58
8361 11:13:08.881562 [CA 2] Center 37 (8~67) winsize 60
8362 11:13:08.884863 [CA 3] Center 36 (7~66) winsize 60
8363 11:13:08.888023 [CA 4] Center 37 (8~67) winsize 60
8364 11:13:08.892032 [CA 5] Center 36 (7~66) winsize 60
8365 11:13:08.892513
8366 11:13:08.894519 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8367 11:13:08.895010
8368 11:13:08.898555 [CATrainingPosCal] consider 2 rank data
8369 11:13:08.901693 u2DelayCellTimex100 = 275/100 ps
8370 11:13:08.904930 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8371 11:13:08.911773 CA1 delay=42 (14~71),Diff = 5 PI (17 cell)
8372 11:13:08.915004 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8373 11:13:08.918273 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8374 11:13:08.921333 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8375 11:13:08.924677 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8376 11:13:08.925097
8377 11:13:08.927931 CA PerBit enable=1, Macro0, CA PI delay=37
8378 11:13:08.928352
8379 11:13:08.931679 [CBTSetCACLKResult] CA Dly = 37
8380 11:13:08.935018 CS Dly: 11 (0~44)
8381 11:13:08.938370 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8382 11:13:08.941650 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8383 11:13:08.942236
8384 11:13:08.944852 ----->DramcWriteLeveling(PI) begin...
8385 11:13:08.945449 ==
8386 11:13:08.948387 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 11:13:08.951575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 11:13:08.955136 ==
8389 11:13:08.955774 Write leveling (Byte 0): 25 => 25
8390 11:13:08.958108 Write leveling (Byte 1): 28 => 28
8391 11:13:08.961700 DramcWriteLeveling(PI) end<-----
8392 11:13:08.962276
8393 11:13:08.962803 ==
8394 11:13:08.964727 Dram Type= 6, Freq= 0, CH_1, rank 0
8395 11:13:08.970714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8396 11:13:08.970822 ==
8397 11:13:08.974147 [Gating] SW mode calibration
8398 11:13:08.980614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8399 11:13:08.984397 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8400 11:13:08.990800 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 11:13:08.993929 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 11:13:08.997768 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 11:13:09.004331 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 11:13:09.007567 1 4 16 | B1->B0 | 2828 2727 | 1 0 | (1 1) (0 0)
8405 11:13:09.010756 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8406 11:13:09.014482 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 11:13:09.020820 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 11:13:09.024132 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 11:13:09.027324 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 11:13:09.034446 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 11:13:09.037698 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8412 11:13:09.040870 1 5 16 | B1->B0 | 2e2e 3333 | 0 0 | (0 1) (0 1)
8413 11:13:09.047120 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8414 11:13:09.051115 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 11:13:09.054155 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 11:13:09.060411 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 11:13:09.064026 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 11:13:09.067703 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 11:13:09.073719 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 11:13:09.077628 1 6 16 | B1->B0 | 3c3c 3131 | 0 1 | (0 0) (0 0)
8421 11:13:09.080876 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 11:13:09.087321 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 11:13:09.091038 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 11:13:09.094186 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 11:13:09.100910 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 11:13:09.104070 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 11:13:09.107157 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8428 11:13:09.113610 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8429 11:13:09.117530 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8430 11:13:09.120764 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 11:13:09.127171 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 11:13:09.130505 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 11:13:09.133863 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 11:13:09.140323 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 11:13:09.144215 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 11:13:09.147342 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 11:13:09.150703 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 11:13:09.157190 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 11:13:09.160435 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 11:13:09.164201 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 11:13:09.170268 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:13:09.173447 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:13:09.177199 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8444 11:13:09.183561 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8445 11:13:09.187408 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8446 11:13:09.190534 Total UI for P1: 0, mck2ui 16
8447 11:13:09.193707 best dqsien dly found for B0: ( 1, 9, 14)
8448 11:13:09.196845 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 11:13:09.200110 Total UI for P1: 0, mck2ui 16
8450 11:13:09.203357 best dqsien dly found for B1: ( 1, 9, 18)
8451 11:13:09.207238 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8452 11:13:09.210332 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8453 11:13:09.210461
8454 11:13:09.216748 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8455 11:13:09.219982 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8456 11:13:09.223517 [Gating] SW calibration Done
8457 11:13:09.223591 ==
8458 11:13:09.226773 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 11:13:09.230544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 11:13:09.230619 ==
8461 11:13:09.230682 RX Vref Scan: 0
8462 11:13:09.230740
8463 11:13:09.233965 RX Vref 0 -> 0, step: 1
8464 11:13:09.234034
8465 11:13:09.237123 RX Delay 0 -> 252, step: 8
8466 11:13:09.240733 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8467 11:13:09.243752 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8468 11:13:09.247168 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8469 11:13:09.253783 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8470 11:13:09.257047 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8471 11:13:09.260342 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8472 11:13:09.263517 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8473 11:13:09.266923 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8474 11:13:09.273647 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8475 11:13:09.276985 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8476 11:13:09.280677 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8477 11:13:09.283375 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8478 11:13:09.290313 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8479 11:13:09.293558 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8480 11:13:09.296979 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8481 11:13:09.300153 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8482 11:13:09.300586 ==
8483 11:13:09.303860 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 11:13:09.307047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 11:13:09.310351 ==
8486 11:13:09.310964 DQS Delay:
8487 11:13:09.311572 DQS0 = 0, DQS1 = 0
8488 11:13:09.313596 DQM Delay:
8489 11:13:09.314104 DQM0 = 133, DQM1 = 127
8490 11:13:09.316808 DQ Delay:
8491 11:13:09.320795 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8492 11:13:09.323895 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8493 11:13:09.327025 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8494 11:13:09.330107 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8495 11:13:09.330646
8496 11:13:09.331158
8497 11:13:09.331645 ==
8498 11:13:09.333814 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 11:13:09.336633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 11:13:09.337127 ==
8501 11:13:09.337578
8502 11:13:09.340466
8503 11:13:09.340987 TX Vref Scan disable
8504 11:13:09.343710 == TX Byte 0 ==
8505 11:13:09.346945 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8506 11:13:09.350149 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8507 11:13:09.353550 == TX Byte 1 ==
8508 11:13:09.356734 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8509 11:13:09.359955 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8510 11:13:09.360389 ==
8511 11:13:09.363769 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 11:13:09.370237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 11:13:09.370812 ==
8514 11:13:09.382791
8515 11:13:09.386056 TX Vref early break, caculate TX vref
8516 11:13:09.389169 TX Vref=16, minBit 8, minWin=20, winSum=354
8517 11:13:09.393010 TX Vref=18, minBit 8, minWin=21, winSum=364
8518 11:13:09.395897 TX Vref=20, minBit 8, minWin=22, winSum=380
8519 11:13:09.398855 TX Vref=22, minBit 8, minWin=22, winSum=385
8520 11:13:09.402289 TX Vref=24, minBit 8, minWin=23, winSum=400
8521 11:13:09.409022 TX Vref=26, minBit 8, minWin=24, winSum=410
8522 11:13:09.412129 TX Vref=28, minBit 8, minWin=24, winSum=414
8523 11:13:09.415932 TX Vref=30, minBit 8, minWin=24, winSum=411
8524 11:13:09.419192 TX Vref=32, minBit 8, minWin=24, winSum=407
8525 11:13:09.422220 TX Vref=34, minBit 8, minWin=23, winSum=399
8526 11:13:09.425614 TX Vref=36, minBit 8, minWin=22, winSum=392
8527 11:13:09.432106 [TxChooseVref] Worse bit 8, Min win 24, Win sum 414, Final Vref 28
8528 11:13:09.432542
8529 11:13:09.435732 Final TX Range 0 Vref 28
8530 11:13:09.436162
8531 11:13:09.436496 ==
8532 11:13:09.439017 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 11:13:09.442275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 11:13:09.442745 ==
8535 11:13:09.443090
8536 11:13:09.443515
8537 11:13:09.445674 TX Vref Scan disable
8538 11:13:09.452143 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8539 11:13:09.452761 == TX Byte 0 ==
8540 11:13:09.455461 u2DelayCellOfst[0]=17 cells (5 PI)
8541 11:13:09.458841 u2DelayCellOfst[1]=10 cells (3 PI)
8542 11:13:09.462447 u2DelayCellOfst[2]=0 cells (0 PI)
8543 11:13:09.465769 u2DelayCellOfst[3]=7 cells (2 PI)
8544 11:13:09.468437 u2DelayCellOfst[4]=7 cells (2 PI)
8545 11:13:09.472447 u2DelayCellOfst[5]=21 cells (6 PI)
8546 11:13:09.475665 u2DelayCellOfst[6]=17 cells (5 PI)
8547 11:13:09.478829 u2DelayCellOfst[7]=7 cells (2 PI)
8548 11:13:09.482260 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8549 11:13:09.485355 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8550 11:13:09.488527 == TX Byte 1 ==
8551 11:13:09.491608 u2DelayCellOfst[8]=0 cells (0 PI)
8552 11:13:09.495459 u2DelayCellOfst[9]=7 cells (2 PI)
8553 11:13:09.495960 u2DelayCellOfst[10]=14 cells (4 PI)
8554 11:13:09.498419 u2DelayCellOfst[11]=10 cells (3 PI)
8555 11:13:09.502151 u2DelayCellOfst[12]=17 cells (5 PI)
8556 11:13:09.505277 u2DelayCellOfst[13]=21 cells (6 PI)
8557 11:13:09.508826 u2DelayCellOfst[14]=17 cells (5 PI)
8558 11:13:09.512017 u2DelayCellOfst[15]=17 cells (5 PI)
8559 11:13:09.518465 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8560 11:13:09.521674 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8561 11:13:09.522161 DramC Write-DBI on
8562 11:13:09.522667 ==
8563 11:13:09.525132 Dram Type= 6, Freq= 0, CH_1, rank 0
8564 11:13:09.532251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8565 11:13:09.532680 ==
8566 11:13:09.533017
8567 11:13:09.533327
8568 11:13:09.533646 TX Vref Scan disable
8569 11:13:09.535498 == TX Byte 0 ==
8570 11:13:09.539441 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8571 11:13:09.542237 == TX Byte 1 ==
8572 11:13:09.545590 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8573 11:13:09.548921 DramC Write-DBI off
8574 11:13:09.549346
8575 11:13:09.549680 [DATLAT]
8576 11:13:09.549987 Freq=1600, CH1 RK0
8577 11:13:09.550292
8578 11:13:09.552184 DATLAT Default: 0xf
8579 11:13:09.552606 0, 0xFFFF, sum = 0
8580 11:13:09.556051 1, 0xFFFF, sum = 0
8581 11:13:09.559379 2, 0xFFFF, sum = 0
8582 11:13:09.559832 3, 0xFFFF, sum = 0
8583 11:13:09.562581 4, 0xFFFF, sum = 0
8584 11:13:09.563007 5, 0xFFFF, sum = 0
8585 11:13:09.566045 6, 0xFFFF, sum = 0
8586 11:13:09.566473 7, 0xFFFF, sum = 0
8587 11:13:09.569056 8, 0xFFFF, sum = 0
8588 11:13:09.569482 9, 0xFFFF, sum = 0
8589 11:13:09.572291 10, 0xFFFF, sum = 0
8590 11:13:09.572719 11, 0xFFFF, sum = 0
8591 11:13:09.575401 12, 0xFFFF, sum = 0
8592 11:13:09.575831 13, 0xFFFF, sum = 0
8593 11:13:09.578725 14, 0x0, sum = 1
8594 11:13:09.579150 15, 0x0, sum = 2
8595 11:13:09.581959 16, 0x0, sum = 3
8596 11:13:09.582389 17, 0x0, sum = 4
8597 11:13:09.585312 best_step = 15
8598 11:13:09.585775
8599 11:13:09.586111 ==
8600 11:13:09.588787 Dram Type= 6, Freq= 0, CH_1, rank 0
8601 11:13:09.592346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8602 11:13:09.592773 ==
8603 11:13:09.595432 RX Vref Scan: 1
8604 11:13:09.595882
8605 11:13:09.596226 Set Vref Range= 24 -> 127
8606 11:13:09.596547
8607 11:13:09.598430 RX Vref 24 -> 127, step: 1
8608 11:13:09.598858
8609 11:13:09.602167 RX Delay 19 -> 252, step: 4
8610 11:13:09.602603
8611 11:13:09.605605 Set Vref, RX VrefLevel [Byte0]: 24
8612 11:13:09.608566 [Byte1]: 24
8613 11:13:09.608999
8614 11:13:09.612283 Set Vref, RX VrefLevel [Byte0]: 25
8615 11:13:09.615392 [Byte1]: 25
8616 11:13:09.618376
8617 11:13:09.618864 Set Vref, RX VrefLevel [Byte0]: 26
8618 11:13:09.622256 [Byte1]: 26
8619 11:13:09.626113
8620 11:13:09.626501 Set Vref, RX VrefLevel [Byte0]: 27
8621 11:13:09.629403 [Byte1]: 27
8622 11:13:09.633512
8623 11:13:09.633982 Set Vref, RX VrefLevel [Byte0]: 28
8624 11:13:09.636701 [Byte1]: 28
8625 11:13:09.641228
8626 11:13:09.641612 Set Vref, RX VrefLevel [Byte0]: 29
8627 11:13:09.644222 [Byte1]: 29
8628 11:13:09.648457
8629 11:13:09.648879 Set Vref, RX VrefLevel [Byte0]: 30
8630 11:13:09.652319 [Byte1]: 30
8631 11:13:09.655848
8632 11:13:09.655929 Set Vref, RX VrefLevel [Byte0]: 31
8633 11:13:09.659097 [Byte1]: 31
8634 11:13:09.663617
8635 11:13:09.663699 Set Vref, RX VrefLevel [Byte0]: 32
8636 11:13:09.666970 [Byte1]: 32
8637 11:13:09.670908
8638 11:13:09.670990 Set Vref, RX VrefLevel [Byte0]: 33
8639 11:13:09.674805 [Byte1]: 33
8640 11:13:09.678646
8641 11:13:09.678740 Set Vref, RX VrefLevel [Byte0]: 34
8642 11:13:09.681857 [Byte1]: 34
8643 11:13:09.686327
8644 11:13:09.686409 Set Vref, RX VrefLevel [Byte0]: 35
8645 11:13:09.689697 [Byte1]: 35
8646 11:13:09.694307
8647 11:13:09.694389 Set Vref, RX VrefLevel [Byte0]: 36
8648 11:13:09.697563 [Byte1]: 36
8649 11:13:09.701829
8650 11:13:09.701916 Set Vref, RX VrefLevel [Byte0]: 37
8651 11:13:09.705103 [Byte1]: 37
8652 11:13:09.709461
8653 11:13:09.709562 Set Vref, RX VrefLevel [Byte0]: 38
8654 11:13:09.712241 [Byte1]: 38
8655 11:13:09.716533
8656 11:13:09.716646 Set Vref, RX VrefLevel [Byte0]: 39
8657 11:13:09.720308 [Byte1]: 39
8658 11:13:09.724036
8659 11:13:09.724171 Set Vref, RX VrefLevel [Byte0]: 40
8660 11:13:09.727461 [Byte1]: 40
8661 11:13:09.731977
8662 11:13:09.732062 Set Vref, RX VrefLevel [Byte0]: 41
8663 11:13:09.735229 [Byte1]: 41
8664 11:13:09.739306
8665 11:13:09.739403 Set Vref, RX VrefLevel [Byte0]: 42
8666 11:13:09.742600 [Byte1]: 42
8667 11:13:09.746873
8668 11:13:09.746967 Set Vref, RX VrefLevel [Byte0]: 43
8669 11:13:09.750047 [Byte1]: 43
8670 11:13:09.754501
8671 11:13:09.754611 Set Vref, RX VrefLevel [Byte0]: 44
8672 11:13:09.757760 [Byte1]: 44
8673 11:13:09.761838
8674 11:13:09.761998 Set Vref, RX VrefLevel [Byte0]: 45
8675 11:13:09.765798 [Byte1]: 45
8676 11:13:09.769640
8677 11:13:09.769791 Set Vref, RX VrefLevel [Byte0]: 46
8678 11:13:09.776139 [Byte1]: 46
8679 11:13:09.776312
8680 11:13:09.779459 Set Vref, RX VrefLevel [Byte0]: 47
8681 11:13:09.782713 [Byte1]: 47
8682 11:13:09.782914
8683 11:13:09.785955 Set Vref, RX VrefLevel [Byte0]: 48
8684 11:13:09.789394 [Byte1]: 48
8685 11:13:09.789693
8686 11:13:09.792657 Set Vref, RX VrefLevel [Byte0]: 49
8687 11:13:09.796025 [Byte1]: 49
8688 11:13:09.800903
8689 11:13:09.801322 Set Vref, RX VrefLevel [Byte0]: 50
8690 11:13:09.803932 [Byte1]: 50
8691 11:13:09.807652
8692 11:13:09.808069 Set Vref, RX VrefLevel [Byte0]: 51
8693 11:13:09.811339 [Byte1]: 51
8694 11:13:09.815065
8695 11:13:09.815526 Set Vref, RX VrefLevel [Byte0]: 52
8696 11:13:09.818750 [Byte1]: 52
8697 11:13:09.822892
8698 11:13:09.823309 Set Vref, RX VrefLevel [Byte0]: 53
8699 11:13:09.825971 [Byte1]: 53
8700 11:13:09.830798
8701 11:13:09.831213 Set Vref, RX VrefLevel [Byte0]: 54
8702 11:13:09.833816 [Byte1]: 54
8703 11:13:09.838114
8704 11:13:09.838533 Set Vref, RX VrefLevel [Byte0]: 55
8705 11:13:09.841371 [Byte1]: 55
8706 11:13:09.845886
8707 11:13:09.846306 Set Vref, RX VrefLevel [Byte0]: 56
8708 11:13:09.849152 [Byte1]: 56
8709 11:13:09.852954
8710 11:13:09.853373 Set Vref, RX VrefLevel [Byte0]: 57
8711 11:13:09.856295 [Byte1]: 57
8712 11:13:09.860556
8713 11:13:09.860980 Set Vref, RX VrefLevel [Byte0]: 58
8714 11:13:09.864445 [Byte1]: 58
8715 11:13:09.868233
8716 11:13:09.868747 Set Vref, RX VrefLevel [Byte0]: 59
8717 11:13:09.871409 [Byte1]: 59
8718 11:13:09.875997
8719 11:13:09.876416 Set Vref, RX VrefLevel [Byte0]: 60
8720 11:13:09.879401 [Byte1]: 60
8721 11:13:09.883817
8722 11:13:09.884237 Set Vref, RX VrefLevel [Byte0]: 61
8723 11:13:09.886986 [Byte1]: 61
8724 11:13:09.891066
8725 11:13:09.891513 Set Vref, RX VrefLevel [Byte0]: 62
8726 11:13:09.894402 [Byte1]: 62
8727 11:13:09.898930
8728 11:13:09.899456 Set Vref, RX VrefLevel [Byte0]: 63
8729 11:13:09.902209 [Byte1]: 63
8730 11:13:09.906145
8731 11:13:09.906567 Set Vref, RX VrefLevel [Byte0]: 64
8732 11:13:09.909337 [Byte1]: 64
8733 11:13:09.913618
8734 11:13:09.914036 Set Vref, RX VrefLevel [Byte0]: 65
8735 11:13:09.917176 [Byte1]: 65
8736 11:13:09.921441
8737 11:13:09.921903 Set Vref, RX VrefLevel [Byte0]: 66
8738 11:13:09.924536 [Byte1]: 66
8739 11:13:09.928881
8740 11:13:09.929464 Set Vref, RX VrefLevel [Byte0]: 67
8741 11:13:09.932419 [Byte1]: 67
8742 11:13:09.936372
8743 11:13:09.936825 Set Vref, RX VrefLevel [Byte0]: 68
8744 11:13:09.939621 [Byte1]: 68
8745 11:13:09.943867
8746 11:13:09.944347 Set Vref, RX VrefLevel [Byte0]: 69
8747 11:13:09.947680 [Byte1]: 69
8748 11:13:09.951589
8749 11:13:09.952062 Set Vref, RX VrefLevel [Byte0]: 70
8750 11:13:09.954903 [Byte1]: 70
8751 11:13:09.959133
8752 11:13:09.959754 Set Vref, RX VrefLevel [Byte0]: 71
8753 11:13:09.962350 [Byte1]: 71
8754 11:13:09.966694
8755 11:13:09.967155 Set Vref, RX VrefLevel [Byte0]: 72
8756 11:13:09.969883 [Byte1]: 72
8757 11:13:09.974460
8758 11:13:09.975030 Set Vref, RX VrefLevel [Byte0]: 73
8759 11:13:09.977682 [Byte1]: 73
8760 11:13:09.982302
8761 11:13:09.982746 Set Vref, RX VrefLevel [Byte0]: 74
8762 11:13:09.985469 [Byte1]: 74
8763 11:13:09.989907
8764 11:13:09.990326 Final RX Vref Byte 0 = 53 to rank0
8765 11:13:09.993270 Final RX Vref Byte 1 = 57 to rank0
8766 11:13:09.996485 Final RX Vref Byte 0 = 53 to rank1
8767 11:13:09.999914 Final RX Vref Byte 1 = 57 to rank1==
8768 11:13:10.002983 Dram Type= 6, Freq= 0, CH_1, rank 0
8769 11:13:10.009493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 11:13:10.009931 ==
8771 11:13:10.010268 DQS Delay:
8772 11:13:10.010607 DQS0 = 0, DQS1 = 0
8773 11:13:10.012884 DQM Delay:
8774 11:13:10.013327 DQM0 = 131, DQM1 = 124
8775 11:13:10.016019 DQ Delay:
8776 11:13:10.019247 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8777 11:13:10.022573 DQ4 =132, DQ5 =142, DQ6 =142, DQ7 =128
8778 11:13:10.025981 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8779 11:13:10.029110 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8780 11:13:10.029534
8781 11:13:10.029866
8782 11:13:10.030178
8783 11:13:10.032935 [DramC_TX_OE_Calibration] TA2
8784 11:13:10.036194 Original DQ_B0 (3 6) =30, OEN = 27
8785 11:13:10.039170 Original DQ_B1 (3 6) =30, OEN = 27
8786 11:13:10.042788 24, 0x0, End_B0=24 End_B1=24
8787 11:13:10.043246 25, 0x0, End_B0=25 End_B1=25
8788 11:13:10.045868 26, 0x0, End_B0=26 End_B1=26
8789 11:13:10.049087 27, 0x0, End_B0=27 End_B1=27
8790 11:13:10.052794 28, 0x0, End_B0=28 End_B1=28
8791 11:13:10.056035 29, 0x0, End_B0=29 End_B1=29
8792 11:13:10.056598 30, 0x0, End_B0=30 End_B1=30
8793 11:13:10.059403 31, 0x4141, End_B0=30 End_B1=30
8794 11:13:10.062730 Byte0 end_step=30 best_step=27
8795 11:13:10.065845 Byte1 end_step=30 best_step=27
8796 11:13:10.069084 Byte0 TX OE(2T, 0.5T) = (3, 3)
8797 11:13:10.072808 Byte1 TX OE(2T, 0.5T) = (3, 3)
8798 11:13:10.073236
8799 11:13:10.073576
8800 11:13:10.078991 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8801 11:13:10.082294 CH1 RK0: MR19=302, MR18=13FE
8802 11:13:10.088846 CH1_RK0: MR19=0x302, MR18=0x13FE, DQSOSC=400, MR23=63, INC=23, DEC=15
8803 11:13:10.089278
8804 11:13:10.092723 ----->DramcWriteLeveling(PI) begin...
8805 11:13:10.093152 ==
8806 11:13:10.096014 Dram Type= 6, Freq= 0, CH_1, rank 1
8807 11:13:10.099314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8808 11:13:10.099795 ==
8809 11:13:10.102877 Write leveling (Byte 0): 25 => 25
8810 11:13:10.105949 Write leveling (Byte 1): 26 => 26
8811 11:13:10.109158 DramcWriteLeveling(PI) end<-----
8812 11:13:10.109580
8813 11:13:10.110000 ==
8814 11:13:10.112575 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 11:13:10.115783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 11:13:10.116258 ==
8817 11:13:10.119019 [Gating] SW mode calibration
8818 11:13:10.125663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8819 11:13:10.132281 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8820 11:13:10.135475 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 11:13:10.138911 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 11:13:10.145913 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8823 11:13:10.148902 1 4 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8824 11:13:10.152468 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 11:13:10.158576 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 11:13:10.161740 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 11:13:10.165586 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 11:13:10.171967 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 11:13:10.175005 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8830 11:13:10.178349 1 5 8 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
8831 11:13:10.184753 1 5 12 | B1->B0 | 3030 2424 | 0 1 | (0 1) (1 0)
8832 11:13:10.188017 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 11:13:10.191240 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 11:13:10.198012 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 11:13:10.201820 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 11:13:10.205178 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 11:13:10.211609 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 11:13:10.214970 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8839 11:13:10.218241 1 6 12 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8840 11:13:10.224712 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 11:13:10.227834 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 11:13:10.231708 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 11:13:10.238114 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 11:13:10.241074 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 11:13:10.244803 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8846 11:13:10.251582 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8847 11:13:10.254837 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8848 11:13:10.258359 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8849 11:13:10.264837 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 11:13:10.267987 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 11:13:10.271293 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 11:13:10.277811 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 11:13:10.281042 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 11:13:10.284918 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 11:13:10.288288 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 11:13:10.294834 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 11:13:10.298269 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:13:10.301562 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 11:13:10.308113 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 11:13:10.311437 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 11:13:10.314782 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8862 11:13:10.321095 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8863 11:13:10.324392 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8864 11:13:10.327999 Total UI for P1: 0, mck2ui 16
8865 11:13:10.331301 best dqsien dly found for B0: ( 1, 9, 6)
8866 11:13:10.334592 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 11:13:10.337851 Total UI for P1: 0, mck2ui 16
8868 11:13:10.341079 best dqsien dly found for B1: ( 1, 9, 12)
8869 11:13:10.344561 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8870 11:13:10.347730 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8871 11:13:10.348167
8872 11:13:10.354713 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8873 11:13:10.358139 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8874 11:13:10.361079 [Gating] SW calibration Done
8875 11:13:10.361518 ==
8876 11:13:10.364703 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 11:13:10.367634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 11:13:10.368139 ==
8879 11:13:10.368598 RX Vref Scan: 0
8880 11:13:10.368926
8881 11:13:10.371232 RX Vref 0 -> 0, step: 1
8882 11:13:10.371739
8883 11:13:10.374253 RX Delay 0 -> 252, step: 8
8884 11:13:10.377712 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8885 11:13:10.381332 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8886 11:13:10.388100 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8887 11:13:10.391117 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8888 11:13:10.394388 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8889 11:13:10.397505 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8890 11:13:10.400856 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8891 11:13:10.404068 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8892 11:13:10.410596 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8893 11:13:10.414531 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8894 11:13:10.417602 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8895 11:13:10.421071 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8896 11:13:10.427192 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8897 11:13:10.430530 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8898 11:13:10.433741 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8899 11:13:10.437180 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8900 11:13:10.437262 ==
8901 11:13:10.441059 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 11:13:10.444140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 11:13:10.447730 ==
8904 11:13:10.447832 DQS Delay:
8905 11:13:10.447908 DQS0 = 0, DQS1 = 0
8906 11:13:10.450659 DQM Delay:
8907 11:13:10.450762 DQM0 = 131, DQM1 = 127
8908 11:13:10.454202 DQ Delay:
8909 11:13:10.457293 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8910 11:13:10.460480 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8911 11:13:10.463724 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8912 11:13:10.467319 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8913 11:13:10.467511
8914 11:13:10.467670
8915 11:13:10.467812 ==
8916 11:13:10.470116 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 11:13:10.473980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 11:13:10.476951 ==
8919 11:13:10.477129
8920 11:13:10.477268
8921 11:13:10.477399 TX Vref Scan disable
8922 11:13:10.480611 == TX Byte 0 ==
8923 11:13:10.483406 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8924 11:13:10.487517 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8925 11:13:10.490501 == TX Byte 1 ==
8926 11:13:10.493449 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8927 11:13:10.497168 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8928 11:13:10.497565 ==
8929 11:13:10.500309 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 11:13:10.507398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 11:13:10.507842 ==
8932 11:13:10.519730
8933 11:13:10.523058 TX Vref early break, caculate TX vref
8934 11:13:10.526406 TX Vref=16, minBit 8, minWin=22, winSum=383
8935 11:13:10.530417 TX Vref=18, minBit 8, minWin=23, winSum=392
8936 11:13:10.533646 TX Vref=20, minBit 8, minWin=23, winSum=397
8937 11:13:10.536875 TX Vref=22, minBit 5, minWin=24, winSum=407
8938 11:13:10.540206 TX Vref=24, minBit 5, minWin=25, winSum=415
8939 11:13:10.546729 TX Vref=26, minBit 8, minWin=25, winSum=421
8940 11:13:10.550130 TX Vref=28, minBit 5, minWin=25, winSum=422
8941 11:13:10.553327 TX Vref=30, minBit 0, minWin=26, winSum=421
8942 11:13:10.556602 TX Vref=32, minBit 0, minWin=25, winSum=416
8943 11:13:10.559902 TX Vref=34, minBit 0, minWin=25, winSum=409
8944 11:13:10.563201 TX Vref=36, minBit 8, minWin=23, winSum=396
8945 11:13:10.569730 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 30
8946 11:13:10.570279
8947 11:13:10.572785 Final TX Range 0 Vref 30
8948 11:13:10.573285
8949 11:13:10.573644 ==
8950 11:13:10.576220 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 11:13:10.579674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 11:13:10.580126 ==
8953 11:13:10.580470
8954 11:13:10.580786
8955 11:13:10.583028 TX Vref Scan disable
8956 11:13:10.589811 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8957 11:13:10.590245 == TX Byte 0 ==
8958 11:13:10.592859 u2DelayCellOfst[0]=17 cells (5 PI)
8959 11:13:10.596402 u2DelayCellOfst[1]=10 cells (3 PI)
8960 11:13:10.599451 u2DelayCellOfst[2]=0 cells (0 PI)
8961 11:13:10.602576 u2DelayCellOfst[3]=3 cells (1 PI)
8962 11:13:10.606331 u2DelayCellOfst[4]=7 cells (2 PI)
8963 11:13:10.609419 u2DelayCellOfst[5]=21 cells (6 PI)
8964 11:13:10.613110 u2DelayCellOfst[6]=17 cells (5 PI)
8965 11:13:10.616270 u2DelayCellOfst[7]=7 cells (2 PI)
8966 11:13:10.619576 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8967 11:13:10.622770 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8968 11:13:10.626184 == TX Byte 1 ==
8969 11:13:10.629464 u2DelayCellOfst[8]=0 cells (0 PI)
8970 11:13:10.630038 u2DelayCellOfst[9]=3 cells (1 PI)
8971 11:13:10.632576 u2DelayCellOfst[10]=10 cells (3 PI)
8972 11:13:10.635863 u2DelayCellOfst[11]=7 cells (2 PI)
8973 11:13:10.639003 u2DelayCellOfst[12]=14 cells (4 PI)
8974 11:13:10.642869 u2DelayCellOfst[13]=17 cells (5 PI)
8975 11:13:10.646189 u2DelayCellOfst[14]=17 cells (5 PI)
8976 11:13:10.649562 u2DelayCellOfst[15]=17 cells (5 PI)
8977 11:13:10.652929 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8978 11:13:10.659395 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8979 11:13:10.659837 DramC Write-DBI on
8980 11:13:10.660181 ==
8981 11:13:10.662656 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 11:13:10.669038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 11:13:10.669474 ==
8984 11:13:10.669816
8985 11:13:10.670133
8986 11:13:10.670437 TX Vref Scan disable
8987 11:13:10.672871 == TX Byte 0 ==
8988 11:13:10.676119 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8989 11:13:10.679284 == TX Byte 1 ==
8990 11:13:10.683171 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8991 11:13:10.686236 DramC Write-DBI off
8992 11:13:10.686679
8993 11:13:10.687022 [DATLAT]
8994 11:13:10.687386 Freq=1600, CH1 RK1
8995 11:13:10.687713
8996 11:13:10.689766 DATLAT Default: 0xf
8997 11:13:10.690195 0, 0xFFFF, sum = 0
8998 11:13:10.692746 1, 0xFFFF, sum = 0
8999 11:13:10.693182 2, 0xFFFF, sum = 0
9000 11:13:10.696226 3, 0xFFFF, sum = 0
9001 11:13:10.696662 4, 0xFFFF, sum = 0
9002 11:13:10.699443 5, 0xFFFF, sum = 0
9003 11:13:10.703012 6, 0xFFFF, sum = 0
9004 11:13:10.703623 7, 0xFFFF, sum = 0
9005 11:13:10.706039 8, 0xFFFF, sum = 0
9006 11:13:10.706655 9, 0xFFFF, sum = 0
9007 11:13:10.709428 10, 0xFFFF, sum = 0
9008 11:13:10.710029 11, 0xFFFF, sum = 0
9009 11:13:10.713051 12, 0xFFFF, sum = 0
9010 11:13:10.713619 13, 0xFFFF, sum = 0
9011 11:13:10.715931 14, 0x0, sum = 1
9012 11:13:10.716487 15, 0x0, sum = 2
9013 11:13:10.719549 16, 0x0, sum = 3
9014 11:13:10.720085 17, 0x0, sum = 4
9015 11:13:10.722931 best_step = 15
9016 11:13:10.723489
9017 11:13:10.724001 ==
9018 11:13:10.726280 Dram Type= 6, Freq= 0, CH_1, rank 1
9019 11:13:10.729611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9020 11:13:10.730287 ==
9021 11:13:10.730881 RX Vref Scan: 0
9022 11:13:10.732804
9023 11:13:10.733429 RX Vref 0 -> 0, step: 1
9024 11:13:10.734048
9025 11:13:10.736249 RX Delay 11 -> 252, step: 4
9026 11:13:10.739416 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9027 11:13:10.746166 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9028 11:13:10.749327 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9029 11:13:10.752638 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9030 11:13:10.755919 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9031 11:13:10.758750 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9032 11:13:10.766036 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9033 11:13:10.769224 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9034 11:13:10.772453 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9035 11:13:10.775739 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9036 11:13:10.778754 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9037 11:13:10.785678 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9038 11:13:10.788723 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9039 11:13:10.791971 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9040 11:13:10.795889 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9041 11:13:10.798860 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9042 11:13:10.802141 ==
9043 11:13:10.805523 Dram Type= 6, Freq= 0, CH_1, rank 1
9044 11:13:10.808548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9045 11:13:10.808650 ==
9046 11:13:10.808741 DQS Delay:
9047 11:13:10.811984 DQS0 = 0, DQS1 = 0
9048 11:13:10.812083 DQM Delay:
9049 11:13:10.815985 DQM0 = 129, DQM1 = 126
9050 11:13:10.816069 DQ Delay:
9051 11:13:10.818837 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
9052 11:13:10.821948 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9053 11:13:10.825044 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9054 11:13:10.828777 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9055 11:13:10.828891
9056 11:13:10.828985
9057 11:13:10.829073
9058 11:13:10.831943 [DramC_TX_OE_Calibration] TA2
9059 11:13:10.835071 Original DQ_B0 (3 6) =30, OEN = 27
9060 11:13:10.838460 Original DQ_B1 (3 6) =30, OEN = 27
9061 11:13:10.841697 24, 0x0, End_B0=24 End_B1=24
9062 11:13:10.844877 25, 0x0, End_B0=25 End_B1=25
9063 11:13:10.844987 26, 0x0, End_B0=26 End_B1=26
9064 11:13:10.848275 27, 0x0, End_B0=27 End_B1=27
9065 11:13:10.851536 28, 0x0, End_B0=28 End_B1=28
9066 11:13:10.855326 29, 0x0, End_B0=29 End_B1=29
9067 11:13:10.858580 30, 0x0, End_B0=30 End_B1=30
9068 11:13:10.858650 31, 0x4545, End_B0=30 End_B1=30
9069 11:13:10.861877 Byte0 end_step=30 best_step=27
9070 11:13:10.865167 Byte1 end_step=30 best_step=27
9071 11:13:10.868379 Byte0 TX OE(2T, 0.5T) = (3, 3)
9072 11:13:10.871709 Byte1 TX OE(2T, 0.5T) = (3, 3)
9073 11:13:10.871784
9074 11:13:10.871845
9075 11:13:10.878464 [DQSOSCAuto] RK1, (LSB)MR18= 0xd13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9076 11:13:10.881521 CH1 RK1: MR19=303, MR18=D13
9077 11:13:10.888501 CH1_RK1: MR19=0x303, MR18=0xD13, DQSOSC=400, MR23=63, INC=23, DEC=15
9078 11:13:10.891824 [RxdqsGatingPostProcess] freq 1600
9079 11:13:10.898534 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9080 11:13:10.898647 best DQS0 dly(2T, 0.5T) = (1, 1)
9081 11:13:10.902011 best DQS1 dly(2T, 0.5T) = (1, 1)
9082 11:13:10.905323 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9083 11:13:10.908232 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9084 11:13:10.911278 best DQS0 dly(2T, 0.5T) = (1, 1)
9085 11:13:10.915009 best DQS1 dly(2T, 0.5T) = (1, 1)
9086 11:13:10.918064 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9087 11:13:10.921273 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9088 11:13:10.924829 Pre-setting of DQS Precalculation
9089 11:13:10.927913 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9090 11:13:10.937960 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9091 11:13:10.944520 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 11:13:10.944600
9093 11:13:10.944670
9094 11:13:10.947979 [Calibration Summary] 3200 Mbps
9095 11:13:10.948052 CH 0, Rank 0
9096 11:13:10.951333 SW Impedance : PASS
9097 11:13:10.951447 DUTY Scan : NO K
9098 11:13:10.954537 ZQ Calibration : PASS
9099 11:13:10.957833 Jitter Meter : NO K
9100 11:13:10.957916 CBT Training : PASS
9101 11:13:10.961336 Write leveling : PASS
9102 11:13:10.961419 RX DQS gating : PASS
9103 11:13:10.964511 RX DQ/DQS(RDDQC) : PASS
9104 11:13:10.967822 TX DQ/DQS : PASS
9105 11:13:10.967904 RX DATLAT : PASS
9106 11:13:10.971059 RX DQ/DQS(Engine): PASS
9107 11:13:10.974460 TX OE : PASS
9108 11:13:10.974542 All Pass.
9109 11:13:10.974606
9110 11:13:10.974666 CH 0, Rank 1
9111 11:13:10.977777 SW Impedance : PASS
9112 11:13:10.981681 DUTY Scan : NO K
9113 11:13:10.981763 ZQ Calibration : PASS
9114 11:13:10.984881 Jitter Meter : NO K
9115 11:13:10.988180 CBT Training : PASS
9116 11:13:10.988262 Write leveling : PASS
9117 11:13:10.991339 RX DQS gating : PASS
9118 11:13:10.994533 RX DQ/DQS(RDDQC) : PASS
9119 11:13:10.994614 TX DQ/DQS : PASS
9120 11:13:10.998256 RX DATLAT : PASS
9121 11:13:11.001403 RX DQ/DQS(Engine): PASS
9122 11:13:11.001485 TX OE : PASS
9123 11:13:11.001550 All Pass.
9124 11:13:11.004647
9125 11:13:11.004728 CH 1, Rank 0
9126 11:13:11.007736 SW Impedance : PASS
9127 11:13:11.007819 DUTY Scan : NO K
9128 11:13:11.011684 ZQ Calibration : PASS
9129 11:13:11.011767 Jitter Meter : NO K
9130 11:13:11.014353 CBT Training : PASS
9131 11:13:11.018018 Write leveling : PASS
9132 11:13:11.018101 RX DQS gating : PASS
9133 11:13:11.021617 RX DQ/DQS(RDDQC) : PASS
9134 11:13:11.024583 TX DQ/DQS : PASS
9135 11:13:11.024667 RX DATLAT : PASS
9136 11:13:11.028044 RX DQ/DQS(Engine): PASS
9137 11:13:11.030962 TX OE : PASS
9138 11:13:11.031097 All Pass.
9139 11:13:11.031222
9140 11:13:11.031330 CH 1, Rank 1
9141 11:13:11.034725 SW Impedance : PASS
9142 11:13:11.037724 DUTY Scan : NO K
9143 11:13:11.037807 ZQ Calibration : PASS
9144 11:13:11.041398 Jitter Meter : NO K
9145 11:13:11.044419 CBT Training : PASS
9146 11:13:11.044501 Write leveling : PASS
9147 11:13:11.047646 RX DQS gating : PASS
9148 11:13:11.050958 RX DQ/DQS(RDDQC) : PASS
9149 11:13:11.051064 TX DQ/DQS : PASS
9150 11:13:11.054284 RX DATLAT : PASS
9151 11:13:11.057443 RX DQ/DQS(Engine): PASS
9152 11:13:11.057529 TX OE : PASS
9153 11:13:11.060753 All Pass.
9154 11:13:11.060835
9155 11:13:11.060900 DramC Write-DBI on
9156 11:13:11.064045 PER_BANK_REFRESH: Hybrid Mode
9157 11:13:11.064128 TX_TRACKING: ON
9158 11:13:11.073921 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9159 11:13:11.080972 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9160 11:13:11.090879 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9161 11:13:11.094115 [FAST_K] Save calibration result to emmc
9162 11:13:11.097537 sync common calibartion params.
9163 11:13:11.097620 sync cbt_mode0:1, 1:1
9164 11:13:11.100743 dram_init: ddr_geometry: 2
9165 11:13:11.104254 dram_init: ddr_geometry: 2
9166 11:13:11.104336 dram_init: ddr_geometry: 2
9167 11:13:11.107491 0:dram_rank_size:100000000
9168 11:13:11.110661 1:dram_rank_size:100000000
9169 11:13:11.114046 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9170 11:13:11.117345 DFS_SHUFFLE_HW_MODE: ON
9171 11:13:11.120698 dramc_set_vcore_voltage set vcore to 725000
9172 11:13:11.123926 Read voltage for 1600, 0
9173 11:13:11.124008 Vio18 = 0
9174 11:13:11.127637 Vcore = 725000
9175 11:13:11.127721 Vdram = 0
9176 11:13:11.127787 Vddq = 0
9177 11:13:11.130469 Vmddr = 0
9178 11:13:11.130554 switch to 3200 Mbps bootup
9179 11:13:11.134201 [DramcRunTimeConfig]
9180 11:13:11.134278 PHYPLL
9181 11:13:11.137065 DPM_CONTROL_AFTERK: ON
9182 11:13:11.137145 PER_BANK_REFRESH: ON
9183 11:13:11.140812 REFRESH_OVERHEAD_REDUCTION: ON
9184 11:13:11.143864 CMD_PICG_NEW_MODE: OFF
9185 11:13:11.143940 XRTWTW_NEW_MODE: ON
9186 11:13:11.147236 XRTRTR_NEW_MODE: ON
9187 11:13:11.147372 TX_TRACKING: ON
9188 11:13:11.150521 RDSEL_TRACKING: OFF
9189 11:13:11.154006 DQS Precalculation for DVFS: ON
9190 11:13:11.154108 RX_TRACKING: OFF
9191 11:13:11.157125 HW_GATING DBG: ON
9192 11:13:11.157228 ZQCS_ENABLE_LP4: ON
9193 11:13:11.160308 RX_PICG_NEW_MODE: ON
9194 11:13:11.160420 TX_PICG_NEW_MODE: ON
9195 11:13:11.163630 ENABLE_RX_DCM_DPHY: ON
9196 11:13:11.167488 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9197 11:13:11.170902 DUMMY_READ_FOR_TRACKING: OFF
9198 11:13:11.171049 !!! SPM_CONTROL_AFTERK: OFF
9199 11:13:11.173494 !!! SPM could not control APHY
9200 11:13:11.177598 IMPEDANCE_TRACKING: ON
9201 11:13:11.177752 TEMP_SENSOR: ON
9202 11:13:11.180767 HW_SAVE_FOR_SR: OFF
9203 11:13:11.184060 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9204 11:13:11.187223 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9205 11:13:11.187431 Read ODT Tracking: ON
9206 11:13:11.190576 Refresh Rate DeBounce: ON
9207 11:13:11.193929 DFS_NO_QUEUE_FLUSH: ON
9208 11:13:11.197376 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9209 11:13:11.197777 ENABLE_DFS_RUNTIME_MRW: OFF
9210 11:13:11.200615 DDR_RESERVE_NEW_MODE: ON
9211 11:13:11.203817 MR_CBT_SWITCH_FREQ: ON
9212 11:13:11.204238 =========================
9213 11:13:11.223992 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9214 11:13:11.227106 dram_init: ddr_geometry: 2
9215 11:13:11.245842 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9216 11:13:11.248801 dram_init: dram init end (result: 0)
9217 11:13:11.255580 DRAM-K: Full calibration passed in 24594 msecs
9218 11:13:11.259208 MRC: failed to locate region type 0.
9219 11:13:11.259764 DRAM rank0 size:0x100000000,
9220 11:13:11.262056 DRAM rank1 size=0x100000000
9221 11:13:11.272485 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9222 11:13:11.278885 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9223 11:13:11.285954 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9224 11:13:11.292379 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9225 11:13:11.295493 DRAM rank0 size:0x100000000,
9226 11:13:11.298832 DRAM rank1 size=0x100000000
9227 11:13:11.299452 CBMEM:
9228 11:13:11.302138 IMD: root @ 0xfffff000 254 entries.
9229 11:13:11.305362 IMD: root @ 0xffffec00 62 entries.
9230 11:13:11.308706 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9231 11:13:11.311801 WARNING: RO_VPD is uninitialized or empty.
9232 11:13:11.318606 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9233 11:13:11.325850 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9234 11:13:11.338852 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9235 11:13:11.350016 BS: romstage times (exec / console): total (unknown) / 24095 ms
9236 11:13:11.350555
9237 11:13:11.350970
9238 11:13:11.359613 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9239 11:13:11.363320 ARM64: Exception handlers installed.
9240 11:13:11.366153 ARM64: Testing exception
9241 11:13:11.369802 ARM64: Done test exception
9242 11:13:11.370395 Enumerating buses...
9243 11:13:11.373014 Show all devs... Before device enumeration.
9244 11:13:11.376219 Root Device: enabled 1
9245 11:13:11.379486 CPU_CLUSTER: 0: enabled 1
9246 11:13:11.380006 CPU: 00: enabled 1
9247 11:13:11.383391 Compare with tree...
9248 11:13:11.383836 Root Device: enabled 1
9249 11:13:11.386533 CPU_CLUSTER: 0: enabled 1
9250 11:13:11.389757 CPU: 00: enabled 1
9251 11:13:11.390282 Root Device scanning...
9252 11:13:11.392994 scan_static_bus for Root Device
9253 11:13:11.396341 CPU_CLUSTER: 0 enabled
9254 11:13:11.399620 scan_static_bus for Root Device done
9255 11:13:11.402711 scan_bus: bus Root Device finished in 8 msecs
9256 11:13:11.403148 done
9257 11:13:11.409600 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9258 11:13:11.413083 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9259 11:13:11.419437 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9260 11:13:11.422969 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9261 11:13:11.426176 Allocating resources...
9262 11:13:11.429460 Reading resources...
9263 11:13:11.432631 Root Device read_resources bus 0 link: 0
9264 11:13:11.433155 DRAM rank0 size:0x100000000,
9265 11:13:11.435910 DRAM rank1 size=0x100000000
9266 11:13:11.439772 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9267 11:13:11.442958 CPU: 00 missing read_resources
9268 11:13:11.446422 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9269 11:13:11.452938 Root Device read_resources bus 0 link: 0 done
9270 11:13:11.453363 Done reading resources.
9271 11:13:11.459612 Show resources in subtree (Root Device)...After reading.
9272 11:13:11.462593 Root Device child on link 0 CPU_CLUSTER: 0
9273 11:13:11.465984 CPU_CLUSTER: 0 child on link 0 CPU: 00
9274 11:13:11.476316 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9275 11:13:11.476934 CPU: 00
9276 11:13:11.479097 Root Device assign_resources, bus 0 link: 0
9277 11:13:11.482810 CPU_CLUSTER: 0 missing set_resources
9278 11:13:11.489157 Root Device assign_resources, bus 0 link: 0 done
9279 11:13:11.489588 Done setting resources.
9280 11:13:11.495921 Show resources in subtree (Root Device)...After assigning values.
9281 11:13:11.499112 Root Device child on link 0 CPU_CLUSTER: 0
9282 11:13:11.502879 CPU_CLUSTER: 0 child on link 0 CPU: 00
9283 11:13:11.512714 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9284 11:13:11.513407 CPU: 00
9285 11:13:11.515781 Done allocating resources.
9286 11:13:11.519052 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9287 11:13:11.522242 Enabling resources...
9288 11:13:11.522781 done.
9289 11:13:11.528865 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9290 11:13:11.529487 Initializing devices...
9291 11:13:11.532833 Root Device init
9292 11:13:11.533494 init hardware done!
9293 11:13:11.536079 0x00000018: ctrlr->caps
9294 11:13:11.538946 52.000 MHz: ctrlr->f_max
9295 11:13:11.539609 0.400 MHz: ctrlr->f_min
9296 11:13:11.542338 0x40ff8080: ctrlr->voltages
9297 11:13:11.542818 sclk: 390625
9298 11:13:11.545691 Bus Width = 1
9299 11:13:11.546240 sclk: 390625
9300 11:13:11.549005 Bus Width = 1
9301 11:13:11.549615 Early init status = 3
9302 11:13:11.555497 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9303 11:13:11.558906 in-header: 03 fc 00 00 01 00 00 00
9304 11:13:11.559495 in-data: 00
9305 11:13:11.565962 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9306 11:13:11.568764 in-header: 03 fd 00 00 00 00 00 00
9307 11:13:11.572491 in-data:
9308 11:13:11.575332 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9309 11:13:11.579331 in-header: 03 fc 00 00 01 00 00 00
9310 11:13:11.582185 in-data: 00
9311 11:13:11.585878 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9312 11:13:11.590635 in-header: 03 fd 00 00 00 00 00 00
9313 11:13:11.594326 in-data:
9314 11:13:11.597408 [SSUSB] Setting up USB HOST controller...
9315 11:13:11.600706 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9316 11:13:11.603889 [SSUSB] phy power-on done.
9317 11:13:11.607747 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9318 11:13:11.614202 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9319 11:13:11.617468 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9320 11:13:11.623824 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9321 11:13:11.630263 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9322 11:13:11.636938 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9323 11:13:11.643809 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9324 11:13:11.650214 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9325 11:13:11.653456 SPM: binary array size = 0x9dc
9326 11:13:11.656765 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9327 11:13:11.663955 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9328 11:13:11.670194 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9329 11:13:11.676719 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9330 11:13:11.679880 configure_display: Starting display init
9331 11:13:11.713740 anx7625_power_on_init: Init interface.
9332 11:13:11.716975 anx7625_disable_pd_protocol: Disabled PD feature.
9333 11:13:11.720270 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9334 11:13:11.748478 anx7625_start_dp_work: Secure OCM version=00
9335 11:13:11.751721 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9336 11:13:11.765999 sp_tx_get_edid_block: EDID Block = 1
9337 11:13:11.869222 Extracted contents:
9338 11:13:11.872322 header: 00 ff ff ff ff ff ff 00
9339 11:13:11.875643 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9340 11:13:11.878832 version: 01 04
9341 11:13:11.882077 basic params: 95 1f 11 78 0a
9342 11:13:11.885399 chroma info: 76 90 94 55 54 90 27 21 50 54
9343 11:13:11.888718 established: 00 00 00
9344 11:13:11.895299 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9345 11:13:11.898792 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9346 11:13:11.905141 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9347 11:13:11.911806 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9348 11:13:11.918477 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9349 11:13:11.921490 extensions: 00
9350 11:13:11.921581 checksum: fb
9351 11:13:11.921658
9352 11:13:11.925047 Manufacturer: IVO Model 57d Serial Number 0
9353 11:13:11.928601 Made week 0 of 2020
9354 11:13:11.928689 EDID version: 1.4
9355 11:13:11.931829 Digital display
9356 11:13:11.935009 6 bits per primary color channel
9357 11:13:11.935111 DisplayPort interface
9358 11:13:11.938278 Maximum image size: 31 cm x 17 cm
9359 11:13:11.941530 Gamma: 220%
9360 11:13:11.941599 Check DPMS levels
9361 11:13:11.945338 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9362 11:13:11.951636 First detailed timing is preferred timing
9363 11:13:11.951719 Established timings supported:
9364 11:13:11.954901 Standard timings supported:
9365 11:13:11.958414 Detailed timings
9366 11:13:11.961315 Hex of detail: 383680a07038204018303c0035ae10000019
9367 11:13:11.964565 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9368 11:13:11.971412 0780 0798 07c8 0820 hborder 0
9369 11:13:11.974537 0438 043b 0447 0458 vborder 0
9370 11:13:11.978422 -hsync -vsync
9371 11:13:11.978495 Did detailed timing
9372 11:13:11.984928 Hex of detail: 000000000000000000000000000000000000
9373 11:13:11.988340 Manufacturer-specified data, tag 0
9374 11:13:11.991492 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9375 11:13:11.994794 ASCII string: InfoVision
9376 11:13:11.997949 Hex of detail: 000000fe00523134304e574635205248200a
9377 11:13:12.001066 ASCII string: R140NWF5 RH
9378 11:13:12.001139 Checksum
9379 11:13:12.004272 Checksum: 0xfb (valid)
9380 11:13:12.007804 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9381 11:13:12.011311 DSI data_rate: 832800000 bps
9382 11:13:12.017545 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9383 11:13:12.021140 anx7625_parse_edid: pixelclock(138800).
9384 11:13:12.024120 hactive(1920), hsync(48), hfp(24), hbp(88)
9385 11:13:12.027645 vactive(1080), vsync(12), vfp(3), vbp(17)
9386 11:13:12.030776 anx7625_dsi_config: config dsi.
9387 11:13:12.037300 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9388 11:13:12.050766 anx7625_dsi_config: success to config DSI
9389 11:13:12.053888 anx7625_dp_start: MIPI phy setup OK.
9390 11:13:12.057322 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9391 11:13:12.060505 mtk_ddp_mode_set invalid vrefresh 60
9392 11:13:12.064496 main_disp_path_setup
9393 11:13:12.064570 ovl_layer_smi_id_en
9394 11:13:12.067088 ovl_layer_smi_id_en
9395 11:13:12.067183 ccorr_config
9396 11:13:12.067272 aal_config
9397 11:13:12.070392 gamma_config
9398 11:13:12.070466 postmask_config
9399 11:13:12.073769 dither_config
9400 11:13:12.077642 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9401 11:13:12.083626 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9402 11:13:12.087556 Root Device init finished in 552 msecs
9403 11:13:12.090727 CPU_CLUSTER: 0 init
9404 11:13:12.097396 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9405 11:13:12.100502 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9406 11:13:12.103793 APU_MBOX 0x190000b0 = 0x10001
9407 11:13:12.107040 APU_MBOX 0x190001b0 = 0x10001
9408 11:13:12.110219 APU_MBOX 0x190005b0 = 0x10001
9409 11:13:12.113741 APU_MBOX 0x190006b0 = 0x10001
9410 11:13:12.117448 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9411 11:13:12.129651 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9412 11:13:12.142444 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9413 11:13:12.149131 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9414 11:13:12.160414 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9415 11:13:12.169559 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9416 11:13:12.173444 CPU_CLUSTER: 0 init finished in 81 msecs
9417 11:13:12.176722 Devices initialized
9418 11:13:12.179427 Show all devs... After init.
9419 11:13:12.179502 Root Device: enabled 1
9420 11:13:12.182684 CPU_CLUSTER: 0: enabled 1
9421 11:13:12.186675 CPU: 00: enabled 1
9422 11:13:12.189716 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9423 11:13:12.193057 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9424 11:13:12.196389 ELOG: NV offset 0x57f000 size 0x1000
9425 11:13:12.202991 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9426 11:13:12.209367 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9427 11:13:12.212873 ELOG: Event(17) added with size 13 at 2023-06-05 11:13:12 UTC
9428 11:13:12.216329 out: cmd=0x121: 03 db 21 01 00 00 00 00
9429 11:13:12.220801 in-header: 03 c0 00 00 2c 00 00 00
9430 11:13:12.234468 in-data: 9f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9431 11:13:12.240855 ELOG: Event(A1) added with size 10 at 2023-06-05 11:13:12 UTC
9432 11:13:12.247537 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9433 11:13:12.254219 ELOG: Event(A0) added with size 9 at 2023-06-05 11:13:12 UTC
9434 11:13:12.257528 elog_add_boot_reason: Logged dev mode boot
9435 11:13:12.260527 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9436 11:13:12.264476 Finalize devices...
9437 11:13:12.264550 Devices finalized
9438 11:13:12.270774 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9439 11:13:12.274094 Writing coreboot table at 0xffe64000
9440 11:13:12.277460 0. 000000000010a000-0000000000113fff: RAMSTAGE
9441 11:13:12.280796 1. 0000000040000000-00000000400fffff: RAM
9442 11:13:12.287333 2. 0000000040100000-000000004032afff: RAMSTAGE
9443 11:13:12.290571 3. 000000004032b000-00000000545fffff: RAM
9444 11:13:12.293832 4. 0000000054600000-000000005465ffff: BL31
9445 11:13:12.297160 5. 0000000054660000-00000000ffe63fff: RAM
9446 11:13:12.303991 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9447 11:13:12.307246 7. 0000000100000000-000000023fffffff: RAM
9448 11:13:12.307378 Passing 5 GPIOs to payload:
9449 11:13:12.313845 NAME | PORT | POLARITY | VALUE
9450 11:13:12.317095 EC in RW | 0x000000aa | low | undefined
9451 11:13:12.323859 EC interrupt | 0x00000005 | low | undefined
9452 11:13:12.327136 TPM interrupt | 0x000000ab | high | undefined
9453 11:13:12.330393 SD card detect | 0x00000011 | high | undefined
9454 11:13:12.337233 speaker enable | 0x00000093 | high | undefined
9455 11:13:12.340304 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9456 11:13:12.343921 in-header: 03 f9 00 00 02 00 00 00
9457 11:13:12.343991 in-data: 02 00
9458 11:13:12.347024 ADC[4]: Raw value=899852 ID=7
9459 11:13:12.350547 ADC[3]: Raw value=213336 ID=1
9460 11:13:12.350622 RAM Code: 0x71
9461 11:13:12.353624 ADC[6]: Raw value=74557 ID=0
9462 11:13:12.356954 ADC[5]: Raw value=211860 ID=1
9463 11:13:12.357029 SKU Code: 0x1
9464 11:13:12.363401 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9465 11:13:12.367111 coreboot table: 964 bytes.
9466 11:13:12.370498 IMD ROOT 0. 0xfffff000 0x00001000
9467 11:13:12.373703 IMD SMALL 1. 0xffffe000 0x00001000
9468 11:13:12.376770 RO MCACHE 2. 0xffffc000 0x00001104
9469 11:13:12.380772 CONSOLE 3. 0xfff7c000 0x00080000
9470 11:13:12.384014 FMAP 4. 0xfff7b000 0x00000452
9471 11:13:12.387195 TIME STAMP 5. 0xfff7a000 0x00000910
9472 11:13:12.390302 VBOOT WORK 6. 0xfff66000 0x00014000
9473 11:13:12.393552 RAMOOPS 7. 0xffe66000 0x00100000
9474 11:13:12.396966 COREBOOT 8. 0xffe64000 0x00002000
9475 11:13:12.397039 IMD small region:
9476 11:13:12.400245 IMD ROOT 0. 0xffffec00 0x00000400
9477 11:13:12.403573 VPD 1. 0xffffeba0 0x0000004c
9478 11:13:12.406888 MMC STATUS 2. 0xffffeb80 0x00000004
9479 11:13:12.413323 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9480 11:13:12.416669 Probing TPM: done!
9481 11:13:12.420010 Connected to device vid:did:rid of 1ae0:0028:00
9482 11:13:12.430236 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9483 11:13:12.433496 Initialized TPM device CR50 revision 0
9484 11:13:12.436860 Checking cr50 for pending updates
9485 11:13:12.440562 Reading cr50 TPM mode
9486 11:13:12.449025 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9487 11:13:12.455858 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9488 11:13:12.496421 read SPI 0x3990ec 0x4f1b0: 34855 us, 9296 KB/s, 74.368 Mbps
9489 11:13:12.499842 Checking segment from ROM address 0x40100000
9490 11:13:12.503240 Checking segment from ROM address 0x4010001c
9491 11:13:12.509738 Loading segment from ROM address 0x40100000
9492 11:13:12.510168 code (compression=0)
9493 11:13:12.516246 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9494 11:13:12.526228 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9495 11:13:12.526667 it's not compressed!
9496 11:13:12.532631 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9497 11:13:12.536356 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9498 11:13:12.556194 Loading segment from ROM address 0x4010001c
9499 11:13:12.556621 Entry Point 0x80000000
9500 11:13:12.559764 Loaded segments
9501 11:13:12.563261 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9502 11:13:12.569799 Jumping to boot code at 0x80000000(0xffe64000)
9503 11:13:12.576393 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9504 11:13:12.582791 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9505 11:13:12.590738 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9506 11:13:12.593748 Checking segment from ROM address 0x40100000
9507 11:13:12.597013 Checking segment from ROM address 0x4010001c
9508 11:13:12.603769 Loading segment from ROM address 0x40100000
9509 11:13:12.603853 code (compression=1)
9510 11:13:12.610269 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9511 11:13:12.620511 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9512 11:13:12.620595 using LZMA
9513 11:13:12.628818 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9514 11:13:12.635317 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9515 11:13:12.639090 Loading segment from ROM address 0x4010001c
9516 11:13:12.639199 Entry Point 0x54601000
9517 11:13:12.642299 Loaded segments
9518 11:13:12.645629 NOTICE: MT8192 bl31_setup
9519 11:13:12.652747 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9520 11:13:12.655457 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9521 11:13:12.658871 WARNING: region 0:
9522 11:13:12.662499 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 11:13:12.662646 WARNING: region 1:
9524 11:13:12.669249 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9525 11:13:12.672768 WARNING: region 2:
9526 11:13:12.675674 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9527 11:13:12.678870 WARNING: region 3:
9528 11:13:12.682540 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9529 11:13:12.685669 WARNING: region 4:
9530 11:13:12.692330 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9531 11:13:12.692593 WARNING: region 5:
9532 11:13:12.695926 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 11:13:12.699147 WARNING: region 6:
9534 11:13:12.702504 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 11:13:12.705835 WARNING: region 7:
9536 11:13:12.709095 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 11:13:12.716088 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9538 11:13:12.719404 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9539 11:13:12.722749 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9540 11:13:12.729001 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9541 11:13:12.732922 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9542 11:13:12.736209 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9543 11:13:12.742433 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9544 11:13:12.745670 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9545 11:13:12.752868 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9546 11:13:12.756168 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9547 11:13:12.759282 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9548 11:13:12.765771 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9549 11:13:12.769039 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9550 11:13:12.772161 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9551 11:13:12.779201 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9552 11:13:12.782319 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9553 11:13:12.789307 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9554 11:13:12.792311 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9555 11:13:12.795553 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9556 11:13:12.802792 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9557 11:13:12.805698 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9558 11:13:12.809561 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9559 11:13:12.816020 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9560 11:13:12.819279 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9561 11:13:12.825589 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9562 11:13:12.828782 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9563 11:13:12.835960 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9564 11:13:12.839244 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9565 11:13:12.842709 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9566 11:13:12.848978 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9567 11:13:12.852969 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9568 11:13:12.855511 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9569 11:13:12.862524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9570 11:13:12.865790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9571 11:13:12.869101 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9572 11:13:12.872399 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9573 11:13:12.878916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9574 11:13:12.882214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9575 11:13:12.885866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9576 11:13:12.888709 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9577 11:13:12.895894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9578 11:13:12.898852 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9579 11:13:12.902387 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9580 11:13:12.905449 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9581 11:13:12.912585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9582 11:13:12.915425 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9583 11:13:12.918728 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9584 11:13:12.925847 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9585 11:13:12.929222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9586 11:13:12.932275 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9587 11:13:12.938883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9588 11:13:12.942043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9589 11:13:12.948688 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9590 11:13:12.952489 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9591 11:13:12.955573 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9592 11:13:12.962586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9593 11:13:12.965977 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9594 11:13:12.972590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9595 11:13:12.975900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9596 11:13:12.982180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9597 11:13:12.985388 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9598 11:13:12.992384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9599 11:13:12.995931 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9600 11:13:12.998752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9601 11:13:13.005806 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9602 11:13:13.008797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9603 11:13:13.015906 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9604 11:13:13.018983 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9605 11:13:13.025347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9606 11:13:13.029154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9607 11:13:13.032415 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9608 11:13:13.038894 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9609 11:13:13.042131 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9610 11:13:13.048708 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9611 11:13:13.052800 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9612 11:13:13.058913 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9613 11:13:13.062018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9614 11:13:13.065973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9615 11:13:13.072572 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9616 11:13:13.075887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9617 11:13:13.082319 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9618 11:13:13.085462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9619 11:13:13.091944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9620 11:13:13.095877 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9621 11:13:13.099056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9622 11:13:13.105837 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9623 11:13:13.108893 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9624 11:13:13.115683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9625 11:13:13.119051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9626 11:13:13.125595 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9627 11:13:13.128585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9628 11:13:13.132120 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9629 11:13:13.138876 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9630 11:13:13.142212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9631 11:13:13.148622 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9632 11:13:13.152625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9633 11:13:13.158979 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9634 11:13:13.161972 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9635 11:13:13.165081 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9636 11:13:13.168915 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9637 11:13:13.174889 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9638 11:13:13.178176 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9639 11:13:13.181363 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9640 11:13:13.187962 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9641 11:13:13.191736 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9642 11:13:13.198358 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9643 11:13:13.201524 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9644 11:13:13.204874 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9645 11:13:13.211273 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9646 11:13:13.215114 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9647 11:13:13.218518 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9648 11:13:13.225025 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9649 11:13:13.227995 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9650 11:13:13.234751 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9651 11:13:13.238412 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9652 11:13:13.241493 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9653 11:13:13.248388 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9654 11:13:13.251670 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9655 11:13:13.254905 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9656 11:13:13.262044 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9657 11:13:13.265350 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9658 11:13:13.267955 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9659 11:13:13.271915 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9660 11:13:13.278468 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9661 11:13:13.281632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9662 11:13:13.284865 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9663 11:13:13.291250 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9664 11:13:13.294975 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9665 11:13:13.301619 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9666 11:13:13.304761 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9667 11:13:13.308046 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9668 11:13:13.314514 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9669 11:13:13.317875 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9670 11:13:13.324674 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9671 11:13:13.328308 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9672 11:13:13.331346 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9673 11:13:13.337825 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9674 11:13:13.341544 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9675 11:13:13.344709 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9676 11:13:13.351520 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9677 11:13:13.354490 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9678 11:13:13.361233 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9679 11:13:13.364573 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9680 11:13:13.368280 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9681 11:13:13.374790 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9682 11:13:13.377932 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9683 11:13:13.385277 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9684 11:13:13.388723 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9685 11:13:13.391856 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9686 11:13:13.398341 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9687 11:13:13.401626 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9688 11:13:13.404964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9689 11:13:13.411376 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9690 11:13:13.414622 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9691 11:13:13.421929 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9692 11:13:13.424890 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9693 11:13:13.428018 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9694 11:13:13.434556 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9695 11:13:13.438334 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9696 11:13:13.444953 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9697 11:13:13.448063 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9698 11:13:13.451746 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9699 11:13:13.457737 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9700 11:13:13.461278 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9701 11:13:13.468238 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9702 11:13:13.471402 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9703 11:13:13.474495 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9704 11:13:13.481485 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9705 11:13:13.484767 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9706 11:13:13.491120 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9707 11:13:13.494394 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9708 11:13:13.497657 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9709 11:13:13.504777 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9710 11:13:13.507892 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9711 11:13:13.511146 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9712 11:13:13.517738 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9713 11:13:13.520884 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9714 11:13:13.527776 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9715 11:13:13.531197 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9716 11:13:13.534452 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9717 11:13:13.541037 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9718 11:13:13.544391 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9719 11:13:13.550999 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9720 11:13:13.554028 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9721 11:13:13.557742 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9722 11:13:13.563603 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9723 11:13:13.567216 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9724 11:13:13.573348 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9725 11:13:13.577172 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9726 11:13:13.580478 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9727 11:13:13.587176 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9728 11:13:13.590374 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9729 11:13:13.596835 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9730 11:13:13.600303 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9731 11:13:13.606555 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9732 11:13:13.609805 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9733 11:13:13.613822 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9734 11:13:13.620266 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9735 11:13:13.623560 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9736 11:13:13.629949 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9737 11:13:13.633211 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9738 11:13:13.637033 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9739 11:13:13.643682 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9740 11:13:13.646839 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9741 11:13:13.653642 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9742 11:13:13.656729 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9743 11:13:13.663322 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9744 11:13:13.666398 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9745 11:13:13.670128 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9746 11:13:13.676708 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9747 11:13:13.679575 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9748 11:13:13.686524 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9749 11:13:13.689593 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9750 11:13:13.693480 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9751 11:13:13.699886 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9752 11:13:13.703028 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9753 11:13:13.709435 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9754 11:13:13.713208 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9755 11:13:13.719706 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9756 11:13:13.722888 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9757 11:13:13.726272 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9758 11:13:13.732815 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9759 11:13:13.736201 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9760 11:13:13.742667 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9761 11:13:13.746004 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9762 11:13:13.752446 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9763 11:13:13.755795 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9764 11:13:13.759000 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9765 11:13:13.765962 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9766 11:13:13.769065 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9767 11:13:13.772785 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9768 11:13:13.775810 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9769 11:13:13.782545 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9770 11:13:13.786172 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9771 11:13:13.789320 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9772 11:13:13.795953 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9773 11:13:13.799101 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9774 11:13:13.802370 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9775 11:13:13.809442 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9776 11:13:13.812713 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9777 11:13:13.815813 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9778 11:13:13.822450 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9779 11:13:13.825683 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9780 11:13:13.828794 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9781 11:13:13.835951 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9782 11:13:13.839166 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9783 11:13:13.845672 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9784 11:13:13.848916 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9785 11:13:13.852198 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9786 11:13:13.859335 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9787 11:13:13.862625 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9788 11:13:13.869171 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9789 11:13:13.872182 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9790 11:13:13.875873 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9791 11:13:13.882516 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9792 11:13:13.885559 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9793 11:13:13.889134 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9794 11:13:13.895277 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9795 11:13:13.899213 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9796 11:13:13.902165 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9797 11:13:13.908640 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9798 11:13:13.911909 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9799 11:13:13.918546 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9800 11:13:13.921836 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9801 11:13:13.925744 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9802 11:13:13.932547 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9803 11:13:13.935676 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9804 11:13:13.938986 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9805 11:13:13.945467 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9806 11:13:13.948751 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9807 11:13:13.951849 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9808 11:13:13.955122 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9809 11:13:13.958387 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9810 11:13:13.964961 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9811 11:13:13.968390 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9812 11:13:13.972373 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9813 11:13:13.975385 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9814 11:13:13.981990 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9815 11:13:13.984894 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9816 11:13:13.988439 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9817 11:13:13.994986 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9818 11:13:13.998193 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9819 11:13:14.001333 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9820 11:13:14.008443 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9821 11:13:14.011524 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9822 11:13:14.018096 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9823 11:13:14.022005 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9824 11:13:14.025220 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9825 11:13:14.031833 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9826 11:13:14.035110 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9827 11:13:14.041668 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9828 11:13:14.044852 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9829 11:13:14.048098 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9830 11:13:14.054663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9831 11:13:14.057917 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9832 11:13:14.065138 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9833 11:13:14.068384 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9834 11:13:14.071743 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9835 11:13:14.078100 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9836 11:13:14.081470 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9837 11:13:14.088090 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9838 11:13:14.091746 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9839 11:13:14.097931 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9840 11:13:14.101340 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9841 11:13:14.104520 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9842 11:13:14.111132 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9843 11:13:14.114687 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9844 11:13:14.121089 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9845 11:13:14.124195 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9846 11:13:14.127706 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9847 11:13:14.134616 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9848 11:13:14.137962 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9849 11:13:14.144517 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9850 11:13:14.147760 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9851 11:13:14.151105 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9852 11:13:14.157644 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9853 11:13:14.160584 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9854 11:13:14.167789 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9855 11:13:14.170360 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9856 11:13:14.177581 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9857 11:13:14.180882 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9858 11:13:14.184162 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9859 11:13:14.190578 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9860 11:13:14.193913 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9861 11:13:14.200336 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9862 11:13:14.203880 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9863 11:13:14.207164 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9864 11:13:14.213657 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9865 11:13:14.217381 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9866 11:13:14.223452 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9867 11:13:14.226911 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9868 11:13:14.230345 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9869 11:13:14.237015 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9870 11:13:14.240669 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9871 11:13:14.247171 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9872 11:13:14.250419 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9873 11:13:14.256898 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9874 11:13:14.260198 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9875 11:13:14.263398 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9876 11:13:14.270046 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9877 11:13:14.273457 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9878 11:13:14.279942 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9879 11:13:14.283131 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9880 11:13:14.286422 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9881 11:13:14.293472 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9882 11:13:14.296755 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9883 11:13:14.303201 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9884 11:13:14.306275 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9885 11:13:14.309928 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9886 11:13:14.316726 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9887 11:13:14.319657 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9888 11:13:14.337786 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9889 11:13:14.337943 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9890 11:13:14.338042 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9891 11:13:14.339944 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9892 11:13:14.343326 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9893 11:13:14.349457 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9894 11:13:14.353354 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9895 11:13:14.359851 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9896 11:13:14.363148 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9897 11:13:14.369741 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9898 11:13:14.372929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9899 11:13:14.376406 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9900 11:13:14.383344 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9901 11:13:14.386808 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9902 11:13:14.393186 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9903 11:13:14.396401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9904 11:13:14.402661 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9905 11:13:14.406459 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9906 11:13:14.409829 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9907 11:13:14.416348 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9908 11:13:14.419381 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9909 11:13:14.426507 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9910 11:13:14.429492 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9911 11:13:14.436310 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9912 11:13:14.439536 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9913 11:13:14.442594 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9914 11:13:14.449244 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9915 11:13:14.452968 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9916 11:13:14.459233 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9917 11:13:14.463055 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9918 11:13:14.469743 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9919 11:13:14.473034 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9920 11:13:14.476215 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9921 11:13:14.482835 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9922 11:13:14.486211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9923 11:13:14.492588 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9924 11:13:14.496461 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9925 11:13:14.502951 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9926 11:13:14.506226 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9927 11:13:14.512790 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9928 11:13:14.516057 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9929 11:13:14.519785 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9930 11:13:14.526015 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9931 11:13:14.529603 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9932 11:13:14.536699 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9933 11:13:14.539307 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9934 11:13:14.545724 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9935 11:13:14.548668 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9936 11:13:14.552298 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9937 11:13:14.558935 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9938 11:13:14.562558 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9939 11:13:14.565685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9940 11:13:14.572492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9941 11:13:14.575760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9942 11:13:14.582270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9943 11:13:14.585534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9944 11:13:14.592639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9945 11:13:14.595829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9946 11:13:14.602411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9947 11:13:14.605637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9948 11:13:14.612082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9949 11:13:14.615293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9950 11:13:14.621809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9951 11:13:14.625532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9952 11:13:14.631836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9953 11:13:14.635007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9954 11:13:14.641965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9955 11:13:14.645284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9956 11:13:14.651779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9957 11:13:14.655157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9958 11:13:14.661815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9959 11:13:14.665307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9960 11:13:14.672158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9961 11:13:14.675161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9962 11:13:14.681581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9963 11:13:14.685513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9964 11:13:14.691341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9965 11:13:14.695401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9966 11:13:14.701638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9967 11:13:14.704797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9968 11:13:14.711860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9969 11:13:14.715100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9970 11:13:14.721479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9971 11:13:14.724834 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9972 11:13:14.724917 INFO: [APUAPC] vio 0
9973 11:13:14.732300 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9974 11:13:14.736027 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9975 11:13:14.739326 INFO: [APUAPC] D0_APC_0: 0x400510
9976 11:13:14.742601 INFO: [APUAPC] D0_APC_1: 0x0
9977 11:13:14.745967 INFO: [APUAPC] D0_APC_2: 0x1540
9978 11:13:14.749200 INFO: [APUAPC] D0_APC_3: 0x0
9979 11:13:14.752197 INFO: [APUAPC] D1_APC_0: 0xffffffff
9980 11:13:14.755406 INFO: [APUAPC] D1_APC_1: 0xffffffff
9981 11:13:14.758885 INFO: [APUAPC] D1_APC_2: 0x3fffff
9982 11:13:14.762508 INFO: [APUAPC] D1_APC_3: 0x0
9983 11:13:14.765602 INFO: [APUAPC] D2_APC_0: 0xffffffff
9984 11:13:14.768663 INFO: [APUAPC] D2_APC_1: 0xffffffff
9985 11:13:14.772301 INFO: [APUAPC] D2_APC_2: 0x3fffff
9986 11:13:14.775392 INFO: [APUAPC] D2_APC_3: 0x0
9987 11:13:14.778603 INFO: [APUAPC] D3_APC_0: 0xffffffff
9988 11:13:14.782147 INFO: [APUAPC] D3_APC_1: 0xffffffff
9989 11:13:14.785408 INFO: [APUAPC] D3_APC_2: 0x3fffff
9990 11:13:14.788590 INFO: [APUAPC] D3_APC_3: 0x0
9991 11:13:14.791965 INFO: [APUAPC] D4_APC_0: 0xffffffff
9992 11:13:14.795174 INFO: [APUAPC] D4_APC_1: 0xffffffff
9993 11:13:14.798473 INFO: [APUAPC] D4_APC_2: 0x3fffff
9994 11:13:14.801662 INFO: [APUAPC] D4_APC_3: 0x0
9995 11:13:14.804922 INFO: [APUAPC] D5_APC_0: 0xffffffff
9996 11:13:14.808836 INFO: [APUAPC] D5_APC_1: 0xffffffff
9997 11:13:14.812143 INFO: [APUAPC] D5_APC_2: 0x3fffff
9998 11:13:14.812246 INFO: [APUAPC] D5_APC_3: 0x0
9999 11:13:14.817980 INFO: [APUAPC] D6_APC_0: 0xffffffff
10000 11:13:14.821410 INFO: [APUAPC] D6_APC_1: 0xffffffff
10001 11:13:14.824652 INFO: [APUAPC] D6_APC_2: 0x3fffff
10002 11:13:14.824736 INFO: [APUAPC] D6_APC_3: 0x0
10003 11:13:14.831257 INFO: [APUAPC] D7_APC_0: 0xffffffff
10004 11:13:14.835014 INFO: [APUAPC] D7_APC_1: 0xffffffff
10005 11:13:14.838107 INFO: [APUAPC] D7_APC_2: 0x3fffff
10006 11:13:14.838191 INFO: [APUAPC] D7_APC_3: 0x0
10007 11:13:14.841402 INFO: [APUAPC] D8_APC_0: 0xffffffff
10008 11:13:14.844639 INFO: [APUAPC] D8_APC_1: 0xffffffff
10009 11:13:14.847931 INFO: [APUAPC] D8_APC_2: 0x3fffff
10010 11:13:14.851167 INFO: [APUAPC] D8_APC_3: 0x0
10011 11:13:14.854415 INFO: [APUAPC] D9_APC_0: 0xffffffff
10012 11:13:14.858291 INFO: [APUAPC] D9_APC_1: 0xffffffff
10013 11:13:14.861422 INFO: [APUAPC] D9_APC_2: 0x3fffff
10014 11:13:14.864690 INFO: [APUAPC] D9_APC_3: 0x0
10015 11:13:14.868257 INFO: [APUAPC] D10_APC_0: 0xffffffff
10016 11:13:14.871176 INFO: [APUAPC] D10_APC_1: 0xffffffff
10017 11:13:14.874246 INFO: [APUAPC] D10_APC_2: 0x3fffff
10018 11:13:14.877948 INFO: [APUAPC] D10_APC_3: 0x0
10019 11:13:14.881518 INFO: [APUAPC] D11_APC_0: 0xffffffff
10020 11:13:14.884454 INFO: [APUAPC] D11_APC_1: 0xffffffff
10021 11:13:14.887566 INFO: [APUAPC] D11_APC_2: 0x3fffff
10022 11:13:14.890778 INFO: [APUAPC] D11_APC_3: 0x0
10023 11:13:14.894726 INFO: [APUAPC] D12_APC_0: 0xffffffff
10024 11:13:14.898038 INFO: [APUAPC] D12_APC_1: 0xffffffff
10025 11:13:14.901200 INFO: [APUAPC] D12_APC_2: 0x3fffff
10026 11:13:14.904452 INFO: [APUAPC] D12_APC_3: 0x0
10027 11:13:14.907753 INFO: [APUAPC] D13_APC_0: 0xffffffff
10028 11:13:14.910946 INFO: [APUAPC] D13_APC_1: 0xffffffff
10029 11:13:14.914179 INFO: [APUAPC] D13_APC_2: 0x3fffff
10030 11:13:14.917500 INFO: [APUAPC] D13_APC_3: 0x0
10031 11:13:14.920875 INFO: [APUAPC] D14_APC_0: 0xffffffff
10032 11:13:14.927450 INFO: [APUAPC] D14_APC_1: 0xffffffff
10033 11:13:14.930719 INFO: [APUAPC] D14_APC_2: 0x3fffff
10034 11:13:14.930829 INFO: [APUAPC] D14_APC_3: 0x0
10035 11:13:14.933956 INFO: [APUAPC] D15_APC_0: 0xffffffff
10036 11:13:14.940940 INFO: [APUAPC] D15_APC_1: 0xffffffff
10037 11:13:14.944117 INFO: [APUAPC] D15_APC_2: 0x3fffff
10038 11:13:14.944200 INFO: [APUAPC] D15_APC_3: 0x0
10039 11:13:14.947388 INFO: [APUAPC] APC_CON: 0x4
10040 11:13:14.950698 INFO: [NOCDAPC] D0_APC_0: 0x0
10041 11:13:14.954511 INFO: [NOCDAPC] D0_APC_1: 0x0
10042 11:13:14.957760 INFO: [NOCDAPC] D1_APC_0: 0x0
10043 11:13:14.960849 INFO: [NOCDAPC] D1_APC_1: 0xfff
10044 11:13:14.964055 INFO: [NOCDAPC] D2_APC_0: 0x0
10045 11:13:14.968145 INFO: [NOCDAPC] D2_APC_1: 0xfff
10046 11:13:14.968231 INFO: [NOCDAPC] D3_APC_0: 0x0
10047 11:13:14.971056 INFO: [NOCDAPC] D3_APC_1: 0xfff
10048 11:13:14.974006 INFO: [NOCDAPC] D4_APC_0: 0x0
10049 11:13:14.977767 INFO: [NOCDAPC] D4_APC_1: 0xfff
10050 11:13:14.980887 INFO: [NOCDAPC] D5_APC_0: 0x0
10051 11:13:14.984043 INFO: [NOCDAPC] D5_APC_1: 0xfff
10052 11:13:14.987690 INFO: [NOCDAPC] D6_APC_0: 0x0
10053 11:13:14.990878 INFO: [NOCDAPC] D6_APC_1: 0xfff
10054 11:13:14.994321 INFO: [NOCDAPC] D7_APC_0: 0x0
10055 11:13:14.997476 INFO: [NOCDAPC] D7_APC_1: 0xfff
10056 11:13:15.000590 INFO: [NOCDAPC] D8_APC_0: 0x0
10057 11:13:15.003955 INFO: [NOCDAPC] D8_APC_1: 0xfff
10058 11:13:15.004040 INFO: [NOCDAPC] D9_APC_0: 0x0
10059 11:13:15.007768 INFO: [NOCDAPC] D9_APC_1: 0xfff
10060 11:13:15.011002 INFO: [NOCDAPC] D10_APC_0: 0x0
10061 11:13:15.014378 INFO: [NOCDAPC] D10_APC_1: 0xfff
10062 11:13:15.017641 INFO: [NOCDAPC] D11_APC_0: 0x0
10063 11:13:15.020777 INFO: [NOCDAPC] D11_APC_1: 0xfff
10064 11:13:15.024226 INFO: [NOCDAPC] D12_APC_0: 0x0
10065 11:13:15.027289 INFO: [NOCDAPC] D12_APC_1: 0xfff
10066 11:13:15.030561 INFO: [NOCDAPC] D13_APC_0: 0x0
10067 11:13:15.033830 INFO: [NOCDAPC] D13_APC_1: 0xfff
10068 11:13:15.037242 INFO: [NOCDAPC] D14_APC_0: 0x0
10069 11:13:15.040469 INFO: [NOCDAPC] D14_APC_1: 0xfff
10070 11:13:15.044331 INFO: [NOCDAPC] D15_APC_0: 0x0
10071 11:13:15.047337 INFO: [NOCDAPC] D15_APC_1: 0xfff
10072 11:13:15.047441 INFO: [NOCDAPC] APC_CON: 0x4
10073 11:13:15.050489 INFO: [APUAPC] set_apusys_apc done
10074 11:13:15.053766 INFO: [DEVAPC] devapc_init done
10075 11:13:15.060945 INFO: GICv3 without legacy support detected.
10076 11:13:15.064168 INFO: ARM GICv3 driver initialized in EL3
10077 11:13:15.067392 INFO: Maximum SPI INTID supported: 639
10078 11:13:15.070561 INFO: BL31: Initializing runtime services
10079 11:13:15.077127 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10080 11:13:15.080768 INFO: SPM: enable CPC mode
10081 11:13:15.083855 INFO: mcdi ready for mcusys-off-idle and system suspend
10082 11:13:15.090652 INFO: BL31: Preparing for EL3 exit to normal world
10083 11:13:15.093623 INFO: Entry point address = 0x80000000
10084 11:13:15.093706 INFO: SPSR = 0x8
10085 11:13:15.100758
10086 11:13:15.100842
10087 11:13:15.100908
10088 11:13:15.103946 Starting depthcharge on Spherion...
10089 11:13:15.104053
10090 11:13:15.104149 Wipe memory regions:
10091 11:13:15.104239
10092 11:13:15.104932 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10093 11:13:15.105037 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10094 11:13:15.105127 Setting prompt string to ['asurada:']
10095 11:13:15.105241 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10096 11:13:15.107139 [0x00000040000000, 0x00000054600000)
10097 11:13:15.229383
10098 11:13:15.229515 [0x00000054660000, 0x00000080000000)
10099 11:13:15.490106
10100 11:13:15.490271 [0x000000821a7280, 0x000000ffe64000)
10101 11:13:16.235359
10102 11:13:16.235546 [0x00000100000000, 0x00000240000000)
10103 11:13:18.125746
10104 11:13:18.128822 Initializing XHCI USB controller at 0x11200000.
10105 11:13:19.167035
10106 11:13:19.170089 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10107 11:13:19.170526
10108 11:13:19.170867
10109 11:13:19.171185
10110 11:13:19.172059 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10112 11:13:19.273110 asurada: tftpboot 192.168.201.1 10591224/tftp-deploy-8fgb2sfx/kernel/image.itb 10591224/tftp-deploy-8fgb2sfx/kernel/cmdline
10113 11:13:19.273272 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10114 11:13:19.273392 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10115 11:13:19.277194 tftpboot 192.168.201.1 10591224/tftp-deploy-8fgb2sfx/kernel/image.itp-deploy-8fgb2sfx/kernel/cmdline
10116 11:13:19.277280
10117 11:13:19.277345 Waiting for link
10118 11:13:19.437631
10119 11:13:19.437769 R8152: Initializing
10120 11:13:19.437836
10121 11:13:19.440970 Version 6 (ocp_data = 5c30)
10122 11:13:19.441052
10123 11:13:19.444334 R8152: Done initializing
10124 11:13:19.444417
10125 11:13:19.444534 Adding net device
10126 11:13:21.408556
10127 11:13:21.408715 done.
10128 11:13:21.408811
10129 11:13:21.408935 MAC: 00:24:32:30:78:52
10130 11:13:21.409026
10131 11:13:21.411838 Sending DHCP discover... done.
10132 11:13:21.411917
10133 11:13:21.415643 Waiting for reply... done.
10134 11:13:21.415729
10135 11:13:21.418306 Sending DHCP request... done.
10136 11:13:21.418389
10137 11:13:21.422892 Waiting for reply... done.
10138 11:13:21.422974
10139 11:13:21.423040 My ip is 192.168.201.14
10140 11:13:21.423101
10141 11:13:21.426664 The DHCP server ip is 192.168.201.1
10142 11:13:21.426748
10143 11:13:21.433233 TFTP server IP predefined by user: 192.168.201.1
10144 11:13:21.433317
10145 11:13:21.439736 Bootfile predefined by user: 10591224/tftp-deploy-8fgb2sfx/kernel/image.itb
10146 11:13:21.439820
10147 11:13:21.439884 Sending tftp read request... done.
10148 11:13:21.442684
10149 11:13:21.446526 Waiting for the transfer...
10150 11:13:21.446610
10151 11:13:22.000916 00000000 ################################################################
10152 11:13:22.001056
10153 11:13:22.562073 00080000 ################################################################
10154 11:13:22.562233
10155 11:13:23.117004 00100000 ################################################################
10156 11:13:23.117146
10157 11:13:23.656843 00180000 ################################################################
10158 11:13:23.656988
10159 11:13:24.195738 00200000 ################################################################
10160 11:13:24.195873
10161 11:13:24.740872 00280000 ################################################################
10162 11:13:24.741040
10163 11:13:25.334864 00300000 ################################################################
10164 11:13:25.335571
10165 11:13:25.961482 00380000 ################################################################
10166 11:13:25.961676
10167 11:13:26.507733 00400000 ################################################################
10168 11:13:26.507893
10169 11:13:27.067243 00480000 ################################################################
10170 11:13:27.067446
10171 11:13:27.629453 00500000 ################################################################
10172 11:13:27.630001
10173 11:13:28.242797 00580000 ################################################################
10174 11:13:28.242946
10175 11:13:28.804206 00600000 ################################################################
10176 11:13:28.804363
10177 11:13:29.400270 00680000 ################################################################
10178 11:13:29.400790
10179 11:13:29.947775 00700000 ################################################################
10180 11:13:29.947917
10181 11:13:30.583865 00780000 ################################################################
10182 11:13:30.584377
10183 11:13:31.190192 00800000 ################################################################
10184 11:13:31.190327
10185 11:13:31.777396 00880000 ################################################################
10186 11:13:31.777559
10187 11:13:32.324387 00900000 ################################################################
10188 11:13:32.324565
10189 11:13:32.943168 00980000 ################################################################
10190 11:13:32.943753
10191 11:13:33.559094 00a00000 ################################################################
10192 11:13:33.559258
10193 11:13:34.181409 00a80000 ################################################################
10194 11:13:34.181624
10195 11:13:34.727296 00b00000 ################################################################
10196 11:13:34.727465
10197 11:13:35.293150 00b80000 ################################################################
10198 11:13:35.293320
10199 11:13:35.849649 00c00000 ################################################################
10200 11:13:35.849785
10201 11:13:36.422115 00c80000 ################################################################
10202 11:13:36.422276
10203 11:13:37.023915 00d00000 ################################################################
10204 11:13:37.024284
10205 11:13:37.570851 00d80000 ################################################################
10206 11:13:37.571023
10207 11:13:38.160108 00e00000 ################################################################
10208 11:13:38.160685
10209 11:13:38.773810 00e80000 ################################################################
10210 11:13:38.774005
10211 11:13:39.358195 00f00000 ################################################################
10212 11:13:39.358368
10213 11:13:39.918162 00f80000 ################################################################
10214 11:13:39.918302
10215 11:13:40.452839 01000000 ################################################################
10216 11:13:40.452978
10217 11:13:41.046715 01080000 ################################################################
10218 11:13:41.046858
10219 11:13:41.612148 01100000 ################################################################
10220 11:13:41.612310
10221 11:13:42.155807 01180000 ################################################################
10222 11:13:42.155949
10223 11:13:42.701331 01200000 ################################################################
10224 11:13:42.701878
10225 11:13:43.355058 01280000 ################################################################
10226 11:13:43.355200
10227 11:13:43.947824 01300000 ################################################################
10228 11:13:43.947970
10229 11:13:44.532201 01380000 ################################################################
10230 11:13:44.532402
10231 11:13:45.143357 01400000 ################################################################
10232 11:13:45.143511
10233 11:13:45.756248 01480000 ################################################################
10234 11:13:45.756774
10235 11:13:46.368607 01500000 ################################################################
10236 11:13:46.369285
10237 11:13:47.012260 01580000 ################################################################
10238 11:13:47.012445
10239 11:13:47.669117 01600000 ################################################################
10240 11:13:47.669266
10241 11:13:48.264694 01680000 ################################################################
10242 11:13:48.264871
10243 11:13:48.873891 01700000 ################################################################
10244 11:13:48.874416
10245 11:13:49.428359 01780000 ################################################################
10246 11:13:49.428512
10247 11:13:50.042270 01800000 ################################################################
10248 11:13:50.042866
10249 11:13:50.639627 01880000 ################################################################
10250 11:13:50.640290
10251 11:13:51.237217 01900000 ################################################################
10252 11:13:51.237523
10253 11:13:51.820387 01980000 ################################################################
10254 11:13:51.820530
10255 11:13:52.411695 01a00000 ############################################################### done.
10256 11:13:52.411850
10257 11:13:52.415572 The bootfile was 27775502 bytes long.
10258 11:13:52.416174
10259 11:13:52.419011 Sending tftp read request... done.
10260 11:13:52.419673
10261 11:13:52.421892 Waiting for the transfer...
10262 11:13:52.422504
10263 11:13:52.423074 00000000 # done.
10264 11:13:52.423615
10265 11:13:52.429028 Command line loaded dynamically from TFTP file: 10591224/tftp-deploy-8fgb2sfx/kernel/cmdline
10266 11:13:52.429592
10267 11:13:52.448655 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591224/extract-nfsrootfs-h4vi_uqd,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10268 11:13:52.449093
10269 11:13:52.451842 Loading FIT.
10270 11:13:52.452316
10271 11:13:52.455504 Image ramdisk-1 has 17640522 bytes.
10272 11:13:52.455930
10273 11:13:52.456302 Image fdt-1 has 46924 bytes.
10274 11:13:52.458617
10275 11:13:52.459134 Image kernel-1 has 10086024 bytes.
10276 11:13:52.459714
10277 11:13:52.468481 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10278 11:13:52.468913
10279 11:13:52.485567 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10280 11:13:52.486175
10281 11:13:52.491693 Choosing best match conf-1 for compat google,spherion-rev2.
10282 11:13:52.496035
10283 11:13:52.500298 Connected to device vid:did:rid of 1ae0:0028:00
10284 11:13:52.507897
10285 11:13:52.510867 tpm_get_response: command 0x17b, return code 0x0
10286 11:13:52.511333
10287 11:13:52.514180 ec_init: CrosEC protocol v3 supported (256, 248)
10288 11:13:52.518261
10289 11:13:52.521289 tpm_cleanup: add release locality here.
10290 11:13:52.521790
10291 11:13:52.522133 Shutting down all USB controllers.
10292 11:13:52.524811
10293 11:13:52.525248 Removing current net device
10294 11:13:52.525588
10295 11:13:52.531316 Exiting depthcharge with code 4 at timestamp: 66847099
10296 11:13:52.531857
10297 11:13:52.534999 LZMA decompressing kernel-1 to 0x821a6718
10298 11:13:52.535438
10299 11:13:52.538208 LZMA decompressing kernel-1 to 0x40000000
10300 11:13:53.804522
10301 11:13:53.804672 jumping to kernel
10302 11:13:53.805078 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10303 11:13:53.805178 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10304 11:13:53.805259 Setting prompt string to ['Linux version [0-9]']
10305 11:13:53.805330 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10306 11:13:53.805399 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10307 11:13:53.887399
10308 11:13:53.890313 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10309 11:13:53.894422 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10310 11:13:53.894891 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10311 11:13:53.895317 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10312 11:13:53.895747 Using line separator: #'\n'#
10313 11:13:53.896070 No login prompt set.
10314 11:13:53.896382 Parsing kernel messages
10315 11:13:53.896670 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10316 11:13:53.897270 [login-action] Waiting for messages, (timeout 00:03:46)
10317 11:13:53.913587 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10318 11:13:53.917332 [ 0.000000] random: crng init done
10319 11:13:53.920432 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10320 11:13:53.923555 [ 0.000000] efi: UEFI not found.
10321 11:13:53.933379 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10322 11:13:53.940572 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10323 11:13:53.950178 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10324 11:13:53.959776 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10325 11:13:53.966706 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10326 11:13:53.969776 [ 0.000000] printk: bootconsole [mtk8250] enabled
10327 11:13:53.978616 [ 0.000000] NUMA: No NUMA configuration found
10328 11:13:53.985675 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10329 11:13:53.991594 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10330 11:13:53.992041 [ 0.000000] Zone ranges:
10331 11:13:53.998637 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10332 11:13:54.001633 [ 0.000000] DMA32 empty
10333 11:13:54.008611 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10334 11:13:54.011697 [ 0.000000] Movable zone start for each node
10335 11:13:54.014723 [ 0.000000] Early memory node ranges
10336 11:13:54.021616 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10337 11:13:54.028312 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10338 11:13:54.034390 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10339 11:13:54.041498 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10340 11:13:54.047757 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10341 11:13:54.054036 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10342 11:13:54.110197 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10343 11:13:54.116862 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10344 11:13:54.124018 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10345 11:13:54.126962 [ 0.000000] psci: probing for conduit method from DT.
10346 11:13:54.133606 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10347 11:13:54.137125 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10348 11:13:54.143809 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10349 11:13:54.146703 [ 0.000000] psci: SMC Calling Convention v1.2
10350 11:13:54.153395 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10351 11:13:54.156885 [ 0.000000] Detected VIPT I-cache on CPU0
10352 11:13:54.163835 [ 0.000000] CPU features: detected: GIC system register CPU interface
10353 11:13:54.170147 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10354 11:13:54.177316 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10355 11:13:54.184140 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10356 11:13:54.190144 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10357 11:13:54.196796 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10358 11:13:54.203391 [ 0.000000] alternatives: applying boot alternatives
10359 11:13:54.206584 [ 0.000000] Fallback order for Node 0: 0
10360 11:13:54.216917 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10361 11:13:54.217543 [ 0.000000] Policy zone: Normal
10362 11:13:54.240000 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591224/extract-nfsrootfs-h4vi_uqd,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10363 11:13:54.249735 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10364 11:13:54.260875 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10365 11:13:54.270748 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10366 11:13:54.277812 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10367 11:13:54.280810 <6>[ 0.000000] software IO TLB: area num 8.
10368 11:13:54.338349 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10369 11:13:54.487102 <6>[ 0.000000] Memory: 7955720K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397048K reserved, 32768K cma-reserved)
10370 11:13:54.493781 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10371 11:13:54.500290 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10372 11:13:54.503960 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10373 11:13:54.510013 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10374 11:13:54.516984 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10375 11:13:54.520376 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10376 11:13:54.530397 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10377 11:13:54.536535 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10378 11:13:54.543444 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10379 11:13:54.550311 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10380 11:13:54.553350 <6>[ 0.000000] GICv3: 608 SPIs implemented
10381 11:13:54.556521 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10382 11:13:54.562985 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10383 11:13:54.566140 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10384 11:13:54.572377 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10385 11:13:54.585598 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10386 11:13:54.598853 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10387 11:13:54.605676 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10388 11:13:54.613466 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10389 11:13:54.626465 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10390 11:13:54.633217 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10391 11:13:54.640018 <6>[ 0.009177] Console: colour dummy device 80x25
10392 11:13:54.650112 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10393 11:13:54.656745 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10394 11:13:54.660185 <6>[ 0.029250] LSM: Security Framework initializing
10395 11:13:54.666173 <6>[ 0.034222] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10396 11:13:54.676180 <6>[ 0.042084] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10397 11:13:54.682944 <6>[ 0.051515] cblist_init_generic: Setting adjustable number of callback queues.
10398 11:13:54.690006 <6>[ 0.058973] cblist_init_generic: Setting shift to 3 and lim to 1.
10399 11:13:54.696547 <6>[ 0.065309] cblist_init_generic: Setting shift to 3 and lim to 1.
10400 11:13:54.702731 <6>[ 0.071716] rcu: Hierarchical SRCU implementation.
10401 11:13:54.709635 <6>[ 0.076731] rcu: Max phase no-delay instances is 1000.
10402 11:13:54.713046 <6>[ 0.083768] EFI services will not be available.
10403 11:13:54.719684 <6>[ 0.088741] smp: Bringing up secondary CPUs ...
10404 11:13:54.727201 <6>[ 0.093796] Detected VIPT I-cache on CPU1
10405 11:13:54.733148 <6>[ 0.093868] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10406 11:13:54.740286 <6>[ 0.093900] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10407 11:13:54.743246 <6>[ 0.094239] Detected VIPT I-cache on CPU2
10408 11:13:54.753529 <6>[ 0.094290] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10409 11:13:54.760761 <6>[ 0.094308] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10410 11:13:54.763690 <6>[ 0.094568] Detected VIPT I-cache on CPU3
10411 11:13:54.769868 <6>[ 0.094614] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10412 11:13:54.776606 <6>[ 0.094630] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10413 11:13:54.780209 <6>[ 0.094937] CPU features: detected: Spectre-v4
10414 11:13:54.786587 <6>[ 0.094943] CPU features: detected: Spectre-BHB
10415 11:13:54.789648 <6>[ 0.094949] Detected PIPT I-cache on CPU4
10416 11:13:54.796486 <6>[ 0.095005] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10417 11:13:54.803153 <6>[ 0.095021] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10418 11:13:54.809405 <6>[ 0.095316] Detected PIPT I-cache on CPU5
10419 11:13:54.816503 <6>[ 0.095379] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10420 11:13:54.823244 <6>[ 0.095396] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10421 11:13:54.826462 <6>[ 0.095681] Detected PIPT I-cache on CPU6
10422 11:13:54.832614 <6>[ 0.095746] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10423 11:13:54.839493 <6>[ 0.095762] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10424 11:13:54.846060 <6>[ 0.096061] Detected PIPT I-cache on CPU7
10425 11:13:54.852876 <6>[ 0.096125] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10426 11:13:54.859076 <6>[ 0.096142] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10427 11:13:54.862747 <6>[ 0.096189] smp: Brought up 1 node, 8 CPUs
10428 11:13:54.869551 <6>[ 0.237619] SMP: Total of 8 processors activated.
10429 11:13:54.872545 <6>[ 0.242539] CPU features: detected: 32-bit EL0 Support
10430 11:13:54.882663 <6>[ 0.247935] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10431 11:13:54.889075 <6>[ 0.256790] CPU features: detected: Common not Private translations
10432 11:13:54.895867 <6>[ 0.263283] CPU features: detected: CRC32 instructions
10433 11:13:54.898917 <6>[ 0.268634] CPU features: detected: RCpc load-acquire (LDAPR)
10434 11:13:54.905486 <6>[ 0.274593] CPU features: detected: LSE atomic instructions
10435 11:13:54.912198 <6>[ 0.280374] CPU features: detected: Privileged Access Never
10436 11:13:54.918983 <6>[ 0.286154] CPU features: detected: RAS Extension Support
10437 11:13:54.925336 <6>[ 0.291797] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10438 11:13:54.928770 <6>[ 0.299018] CPU: All CPU(s) started at EL2
10439 11:13:54.935520 <6>[ 0.303334] alternatives: applying system-wide alternatives
10440 11:13:54.944504 <6>[ 0.314039] devtmpfs: initialized
10441 11:13:54.960944 <6>[ 0.323212] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10442 11:13:54.967149 <6>[ 0.333176] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10443 11:13:54.974082 <6>[ 0.341420] pinctrl core: initialized pinctrl subsystem
10444 11:13:54.977182 <6>[ 0.348085] DMI not present or invalid.
10445 11:13:54.984014 <6>[ 0.352494] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10446 11:13:54.993662 <6>[ 0.359391] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10447 11:13:55.000267 <6>[ 0.366961] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10448 11:13:55.010832 <6>[ 0.375191] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10449 11:13:55.013933 <6>[ 0.383437] audit: initializing netlink subsys (disabled)
10450 11:13:55.023874 <5>[ 0.389134] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10451 11:13:55.030657 <6>[ 0.389839] thermal_sys: Registered thermal governor 'step_wise'
10452 11:13:55.036709 <6>[ 0.397101] thermal_sys: Registered thermal governor 'power_allocator'
10453 11:13:55.040300 <6>[ 0.403357] cpuidle: using governor menu
10454 11:13:55.046577 <6>[ 0.414317] NET: Registered PF_QIPCRTR protocol family
10455 11:13:55.053139 <6>[ 0.419803] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10456 11:13:55.059386 <6>[ 0.426905] ASID allocator initialised with 32768 entries
10457 11:13:55.063148 <6>[ 0.433485] Serial: AMBA PL011 UART driver
10458 11:13:55.073005 <4>[ 0.442167] Trying to register duplicate clock ID: 134
10459 11:13:55.128752 <6>[ 0.501534] KASLR enabled
10460 11:13:55.143641 <6>[ 0.509499] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10461 11:13:55.150221 <6>[ 0.516510] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10462 11:13:55.156359 <6>[ 0.522998] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10463 11:13:55.163198 <6>[ 0.530003] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10464 11:13:55.169998 <6>[ 0.536492] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10465 11:13:55.176220 <6>[ 0.543497] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10466 11:13:55.183179 <6>[ 0.549984] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10467 11:13:55.189910 <6>[ 0.556988] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10468 11:13:55.193093 <6>[ 0.564504] ACPI: Interpreter disabled.
10469 11:13:55.201130 <6>[ 0.570886] iommu: Default domain type: Translated
10470 11:13:55.208064 <6>[ 0.576002] iommu: DMA domain TLB invalidation policy: strict mode
10471 11:13:55.211107 <5>[ 0.582656] SCSI subsystem initialized
10472 11:13:55.218018 <6>[ 0.586823] usbcore: registered new interface driver usbfs
10473 11:13:55.224281 <6>[ 0.592559] usbcore: registered new interface driver hub
10474 11:13:55.228037 <6>[ 0.598112] usbcore: registered new device driver usb
10475 11:13:55.234933 <6>[ 0.604195] pps_core: LinuxPPS API ver. 1 registered
10476 11:13:55.244918 <6>[ 0.609391] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10477 11:13:55.248023 <6>[ 0.618740] PTP clock support registered
10478 11:13:55.251325 <6>[ 0.622983] EDAC MC: Ver: 3.0.0
10479 11:13:55.258468 <6>[ 0.628127] FPGA manager framework
10480 11:13:55.265423 <6>[ 0.631806] Advanced Linux Sound Architecture Driver Initialized.
10481 11:13:55.268398 <6>[ 0.638586] vgaarb: loaded
10482 11:13:55.275252 <6>[ 0.641769] clocksource: Switched to clocksource arch_sys_counter
10483 11:13:55.278200 <5>[ 0.648210] VFS: Disk quotas dquot_6.6.0
10484 11:13:55.284936 <6>[ 0.652393] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10485 11:13:55.288085 <6>[ 0.659582] pnp: PnP ACPI: disabled
10486 11:13:55.296715 <6>[ 0.666330] NET: Registered PF_INET protocol family
10487 11:13:55.306622 <6>[ 0.671927] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10488 11:13:55.318262 <6>[ 0.684256] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10489 11:13:55.327797 <6>[ 0.693076] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10490 11:13:55.334469 <6>[ 0.701044] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10491 11:13:55.341118 <6>[ 0.709741] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10492 11:13:55.353062 <6>[ 0.719456] TCP: Hash tables configured (established 65536 bind 65536)
10493 11:13:55.360067 <6>[ 0.726316] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10494 11:13:55.366534 <6>[ 0.733518] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10495 11:13:55.373100 <6>[ 0.741222] NET: Registered PF_UNIX/PF_LOCAL protocol family
10496 11:13:55.380037 <6>[ 0.747394] RPC: Registered named UNIX socket transport module.
10497 11:13:55.383206 <6>[ 0.753550] RPC: Registered udp transport module.
10498 11:13:55.389368 <6>[ 0.758483] RPC: Registered tcp transport module.
10499 11:13:55.396132 <6>[ 0.763416] RPC: Registered tcp NFSv4.1 backchannel transport module.
10500 11:13:55.399251 <6>[ 0.770085] PCI: CLS 0 bytes, default 64
10501 11:13:55.403038 <6>[ 0.774441] Unpacking initramfs...
10502 11:13:55.419844 <6>[ 0.786255] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10503 11:13:55.430023 <6>[ 0.794920] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10504 11:13:55.433122 <6>[ 0.803771] kvm [1]: IPA Size Limit: 40 bits
10505 11:13:55.440162 <6>[ 0.808304] kvm [1]: GICv3: no GICV resource entry
10506 11:13:55.443159 <6>[ 0.813327] kvm [1]: disabling GICv2 emulation
10507 11:13:55.449859 <6>[ 0.818014] kvm [1]: GIC system register CPU interface enabled
10508 11:13:55.453322 <6>[ 0.824188] kvm [1]: vgic interrupt IRQ18
10509 11:13:55.459880 <6>[ 0.828569] kvm [1]: VHE mode initialized successfully
10510 11:13:55.466663 <5>[ 0.835006] Initialise system trusted keyrings
10511 11:13:55.473185 <6>[ 0.839863] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10512 11:13:55.480593 <6>[ 0.849935] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10513 11:13:55.487310 <5>[ 0.856333] NFS: Registering the id_resolver key type
10514 11:13:55.490434 <5>[ 0.861658] Key type id_resolver registered
10515 11:13:55.497474 <5>[ 0.866080] Key type id_legacy registered
10516 11:13:55.503798 <6>[ 0.870364] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10517 11:13:55.510528 <6>[ 0.877289] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10518 11:13:55.517564 <6>[ 0.885053] 9p: Installing v9fs 9p2000 file system support
10519 11:13:55.552715 <5>[ 0.922091] Key type asymmetric registered
10520 11:13:55.555813 <5>[ 0.926424] Asymmetric key parser 'x509' registered
10521 11:13:55.565754 <6>[ 0.931582] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10522 11:13:55.569127 <6>[ 0.939213] io scheduler mq-deadline registered
10523 11:13:55.572445 <6>[ 0.943981] io scheduler kyber registered
10524 11:13:55.591335 <6>[ 0.960940] EINJ: ACPI disabled.
10525 11:13:55.624550 <4>[ 0.986736] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10526 11:13:55.634037 <4>[ 0.997365] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10527 11:13:55.648957 <6>[ 1.018334] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10528 11:13:55.657367 <6>[ 1.026388] printk: console [ttyS0] disabled
10529 11:13:55.685002 <6>[ 1.051043] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10530 11:13:55.691793 <6>[ 1.060522] printk: console [ttyS0] enabled
10531 11:13:55.695109 <6>[ 1.060522] printk: console [ttyS0] enabled
10532 11:13:55.701842 <6>[ 1.069418] printk: bootconsole [mtk8250] disabled
10533 11:13:55.705134 <6>[ 1.069418] printk: bootconsole [mtk8250] disabled
10534 11:13:55.712034 <6>[ 1.080639] SuperH (H)SCI(F) driver initialized
10535 11:13:55.715174 <6>[ 1.085922] msm_serial: driver initialized
10536 11:13:55.729254 <6>[ 1.094902] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10537 11:13:55.739081 <6>[ 1.103452] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10538 11:13:55.745422 <6>[ 1.111995] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10539 11:13:55.755472 <6>[ 1.120625] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10540 11:13:55.765421 <6>[ 1.129338] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10541 11:13:55.772511 <6>[ 1.138057] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10542 11:13:55.782189 <6>[ 1.146599] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10543 11:13:55.788680 <6>[ 1.155408] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10544 11:13:55.798693 <6>[ 1.163950] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10545 11:13:55.810193 <6>[ 1.179547] loop: module loaded
10546 11:13:55.817431 <6>[ 1.185644] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10547 11:13:55.840008 <4>[ 1.209125] mtk-pmic-keys: Failed to locate of_node [id: -1]
10548 11:13:55.846476 <6>[ 1.215938] megasas: 07.719.03.00-rc1
10549 11:13:55.856245 <6>[ 1.225518] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10550 11:13:55.864018 <6>[ 1.233154] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10551 11:13:55.880757 <6>[ 1.249728] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10552 11:13:55.941657 <6>[ 1.304003] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10553 11:13:56.130501 <6>[ 1.500184] Freeing initrd memory: 17220K
10554 11:13:56.141280 <6>[ 1.510320] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10555 11:13:56.151991 <6>[ 1.521277] tun: Universal TUN/TAP device driver, 1.6
10556 11:13:56.154997 <6>[ 1.527334] thunder_xcv, ver 1.0
10557 11:13:56.158767 <6>[ 1.530839] thunder_bgx, ver 1.0
10558 11:13:56.161936 <6>[ 1.534333] nicpf, ver 1.0
10559 11:13:56.171963 <6>[ 1.538344] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10560 11:13:56.175669 <6>[ 1.545824] hns3: Copyright (c) 2017 Huawei Corporation.
10561 11:13:56.181903 <6>[ 1.551411] hclge is initializing
10562 11:13:56.185628 <6>[ 1.554990] e1000: Intel(R) PRO/1000 Network Driver
10563 11:13:56.192172 <6>[ 1.560119] e1000: Copyright (c) 1999-2006 Intel Corporation.
10564 11:13:56.195111 <6>[ 1.566135] e1000e: Intel(R) PRO/1000 Network Driver
10565 11:13:56.202009 <6>[ 1.571351] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10566 11:13:56.208821 <6>[ 1.577536] igb: Intel(R) Gigabit Ethernet Network Driver
10567 11:13:56.215142 <6>[ 1.583185] igb: Copyright (c) 2007-2014 Intel Corporation.
10568 11:13:56.222239 <6>[ 1.589022] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10569 11:13:56.228643 <6>[ 1.595540] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10570 11:13:56.232209 <6>[ 1.602023] sky2: driver version 1.30
10571 11:13:56.238541 <6>[ 1.607000] VFIO - User Level meta-driver version: 0.3
10572 11:13:56.245659 <6>[ 1.615141] usbcore: registered new interface driver usb-storage
10573 11:13:56.252174 <6>[ 1.621582] usbcore: registered new device driver onboard-usb-hub
10574 11:13:56.260850 <6>[ 1.630642] mt6397-rtc mt6359-rtc: registered as rtc0
10575 11:13:56.270888 <6>[ 1.636119] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:13:56 UTC (1685963636)
10576 11:13:56.274638 <6>[ 1.645723] i2c_dev: i2c /dev entries driver
10577 11:13:56.291069 <6>[ 1.657379] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10578 11:13:56.298366 <6>[ 1.667609] sdhci: Secure Digital Host Controller Interface driver
10579 11:13:56.304467 <6>[ 1.674046] sdhci: Copyright(c) Pierre Ossman
10580 11:13:56.311278 <6>[ 1.679441] Synopsys Designware Multimedia Card Interface Driver
10581 11:13:56.314497 <6>[ 1.686044] mmc0: CQHCI version 5.10
10582 11:13:56.321564 <6>[ 1.686600] sdhci-pltfm: SDHCI platform and OF driver helper
10583 11:13:56.328577 <6>[ 1.697908] ledtrig-cpu: registered to indicate activity on CPUs
10584 11:13:56.339189 <6>[ 1.705327] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10585 11:13:56.345966 <6>[ 1.712727] usbcore: registered new interface driver usbhid
10586 11:13:56.349445 <6>[ 1.718556] usbhid: USB HID core driver
10587 11:13:56.356040 <6>[ 1.722806] spi_master spi0: will run message pump with realtime priority
10588 11:13:56.404664 <6>[ 1.767220] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10589 11:13:56.423900 <6>[ 1.782763] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10590 11:13:56.427710 <6>[ 1.796332] mmc0: Command Queue Engine enabled
10591 11:13:56.434567 <6>[ 1.797750] cros-ec-spi spi0.0: Chrome EC device registered
10592 11:13:56.438000 <6>[ 1.801066] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10593 11:13:56.444680 <6>[ 1.814173] mmcblk0: mmc0:0001 DA4128 116 GiB
10594 11:13:56.458493 <6>[ 1.824627] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10595 11:13:56.465312 <6>[ 1.828279] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10596 11:13:56.472063 <6>[ 1.836062] NET: Registered PF_PACKET protocol family
10597 11:13:56.474989 <6>[ 1.841245] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10598 11:13:56.482114 <6>[ 1.845290] 9pnet: Installing 9P2000 support
10599 11:13:56.485287 <6>[ 1.851029] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10600 11:13:56.491553 <5>[ 1.854966] Key type dns_resolver registered
10601 11:13:56.498564 <6>[ 1.860786] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10602 11:13:56.501737 <6>[ 1.865282] registered taskstats version 1
10603 11:13:56.505463 <5>[ 1.875620] Loading compiled-in X.509 certificates
10604 11:13:56.540086 <4>[ 1.902481] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10605 11:13:56.550096 <4>[ 1.913167] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10606 11:13:56.560441 <3>[ 1.925991] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10607 11:13:56.572175 <6>[ 1.941392] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10608 11:13:56.579075 <6>[ 1.948287] xhci-mtk 11200000.usb: xHCI Host Controller
10609 11:13:56.585937 <6>[ 1.953792] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10610 11:13:56.595817 <6>[ 1.961646] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10611 11:13:56.602814 <6>[ 1.971082] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10612 11:13:56.609023 <6>[ 1.977179] xhci-mtk 11200000.usb: xHCI Host Controller
10613 11:13:56.615749 <6>[ 1.982660] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10614 11:13:56.622475 <6>[ 1.990311] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10615 11:13:56.629479 <6>[ 1.998028] hub 1-0:1.0: USB hub found
10616 11:13:56.632621 <6>[ 2.002050] hub 1-0:1.0: 1 port detected
10617 11:13:56.639453 <6>[ 2.006382] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10618 11:13:56.646100 <6>[ 2.015101] hub 2-0:1.0: USB hub found
10619 11:13:56.649088 <6>[ 2.019131] hub 2-0:1.0: 1 port detected
10620 11:13:56.656803 <6>[ 2.026275] mtk-msdc 11f70000.mmc: Got CD GPIO
10621 11:13:56.679051 <6>[ 2.044728] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10622 11:13:56.685195 <6>[ 2.052787] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10623 11:13:56.695652 <4>[ 2.060766] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10624 11:13:56.705783 <6>[ 2.070439] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10625 11:13:56.712528 <6>[ 2.078523] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10626 11:13:56.718597 <6>[ 2.086563] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10627 11:13:56.728799 <6>[ 2.094478] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10628 11:13:56.735412 <6>[ 2.102299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10629 11:13:56.745628 <6>[ 2.110121] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10630 11:13:56.755743 <6>[ 2.120931] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10631 11:13:56.762226 <6>[ 2.129314] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10632 11:13:56.771959 <6>[ 2.137667] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10633 11:13:56.779118 <6>[ 2.146014] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10634 11:13:56.788688 <6>[ 2.154359] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10635 11:13:56.795412 <6>[ 2.162702] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10636 11:13:56.805555 <6>[ 2.171044] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10637 11:13:56.812449 <6>[ 2.179387] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10638 11:13:56.822111 <6>[ 2.187730] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10639 11:13:56.828509 <6>[ 2.196073] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10640 11:13:56.838430 <6>[ 2.204417] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10641 11:13:56.845287 <6>[ 2.212760] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10642 11:13:56.855590 <6>[ 2.221106] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10643 11:13:56.862166 <6>[ 2.229449] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10644 11:13:56.871830 <6>[ 2.237794] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10645 11:13:56.879279 <6>[ 2.246711] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10646 11:13:56.885260 <6>[ 2.254180] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10647 11:13:56.891660 <6>[ 2.261195] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10648 11:13:56.902543 <6>[ 2.268283] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10649 11:13:56.908735 <6>[ 2.275550] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10650 11:13:56.919191 <6>[ 2.282545] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10651 11:13:56.925450 <6>[ 2.291685] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10652 11:13:56.935042 <6>[ 2.300812] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10653 11:13:56.945129 <6>[ 2.310114] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10654 11:13:56.954983 <6>[ 2.319588] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10655 11:13:56.965055 <6>[ 2.329062] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10656 11:13:56.974860 <6>[ 2.338190] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10657 11:13:56.981363 <6>[ 2.347663] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10658 11:13:56.991169 <6>[ 2.356789] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10659 11:13:57.001649 <6>[ 2.366092] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10660 11:13:57.010686 <6>[ 2.376258] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10661 11:13:57.021207 <6>[ 2.387685] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10662 11:13:57.028166 <6>[ 2.397610] Trying to probe devices needed for running init ...
10663 11:13:57.039727 <6>[ 2.406251] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10664 11:13:57.068745 <6>[ 2.438189] hub 2-1:1.0: USB hub found
10665 11:13:57.072246 <6>[ 2.442706] hub 2-1:1.0: 3 ports detected
10666 11:13:57.191550 <6>[ 2.558015] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10667 11:13:57.344791 <6>[ 2.714230] hub 1-1:1.0: USB hub found
10668 11:13:57.348734 <6>[ 2.718595] hub 1-1:1.0: 4 ports detected
10669 11:13:57.424505 <6>[ 2.790289] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10670 11:13:57.667678 <6>[ 3.034046] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10671 11:13:57.800874 <6>[ 3.170209] hub 1-1.4:1.0: USB hub found
10672 11:13:57.803885 <6>[ 3.174862] hub 1-1.4:1.0: 2 ports detected
10673 11:13:58.100039 <6>[ 3.466033] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10674 11:13:58.291720 <6>[ 3.658051] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10675 11:14:09.324369 <6>[ 14.698601] ALSA device list:
10676 11:14:09.330382 <6>[ 14.701860] No soundcards found.
10677 11:14:09.343338 <6>[ 14.714255] Freeing unused kernel memory: 8384K
10678 11:14:09.346551 <6>[ 14.719189] Run /init as init process
10679 11:14:09.357664 Loading, please wait...
10680 11:14:09.376184 Starting version 247.3-7+deb11u2
10681 11:14:09.693319 <6>[ 15.061286] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10682 11:14:09.708920 <6>[ 15.080020] remoteproc remoteproc0: scp is available
10683 11:14:09.719072 <4>[ 15.086069] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10684 11:14:09.725343 <6>[ 15.095950] remoteproc remoteproc0: powering up scp
10685 11:14:09.735984 <4>[ 15.101138] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10686 11:14:09.742331 <3>[ 15.110968] remoteproc remoteproc0: request_firmware failed: -2
10687 11:14:09.748627 <3>[ 15.113141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 11:14:09.755200 <6>[ 15.117496] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10689 11:14:09.762333 <6>[ 15.117772] mc: Linux media interface: v0.10
10690 11:14:09.765146 <6>[ 15.119267] usbcore: registered new interface driver r8152
10691 11:14:09.775316 <6>[ 15.121998] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10692 11:14:09.782253 <6>[ 15.122022] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10693 11:14:09.792012 <6>[ 15.122031] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10694 11:14:09.798821 <4>[ 15.149255] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10695 11:14:09.808820 <3>[ 15.153439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 11:14:09.814992 <4>[ 15.161806] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10697 11:14:09.822003 <6>[ 15.165362] videodev: Linux video capture interface: v2.00
10698 11:14:09.824999 <6>[ 15.167762] usbcore: registered new interface driver cdc_ether
10699 11:14:09.835735 <3>[ 15.168232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 11:14:09.841962 <4>[ 15.185810] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10701 11:14:09.848961 <4>[ 15.185810] Fallback method does not support PEC.
10702 11:14:09.855389 <3>[ 15.191256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 11:14:09.865729 <3>[ 15.212221] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10704 11:14:09.872131 <3>[ 15.224560] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 11:14:09.878705 <6>[ 15.247544] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10706 11:14:09.888748 <6>[ 15.249532] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10707 11:14:09.895524 <3>[ 15.249615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 11:14:09.905428 <3>[ 15.249633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 11:14:09.911554 <3>[ 15.249641] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 11:14:09.918494 <3>[ 15.249690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 11:14:09.928415 <3>[ 15.249733] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 11:14:09.934871 <3>[ 15.249739] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 11:14:09.945402 <3>[ 15.249745] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 11:14:09.951666 <3>[ 15.249822] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 11:14:09.961541 <3>[ 15.249829] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 11:14:09.969181 <3>[ 15.249835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 11:14:09.975785 <3>[ 15.249841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 11:14:09.985237 <3>[ 15.249847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 11:14:09.992031 <3>[ 15.249874] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 11:14:09.998278 <6>[ 15.256384] pci_bus 0000:00: root bus resource [bus 00-ff]
10721 11:14:10.008523 <6>[ 15.344884] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10722 11:14:10.015442 <6>[ 15.352822] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10723 11:14:10.024699 <6>[ 15.353521] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10724 11:14:10.035306 <6>[ 15.354004] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10725 11:14:10.041355 <4>[ 15.356195] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10726 11:14:10.051551 <4>[ 15.356206] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10727 11:14:10.058266 <6>[ 15.375065] usbcore: registered new interface driver r8153_ecm
10728 11:14:10.068272 <6>[ 15.383930] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10729 11:14:10.071261 <6>[ 15.401900] Bluetooth: Core ver 2.22
10730 11:14:10.078116 <6>[ 15.410255] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10731 11:14:10.081198 <6>[ 15.413923] r8152 2-1.3:1.0 eth0: v1.12.13
10732 11:14:10.088660 <6>[ 15.419316] NET: Registered PF_BLUETOOTH protocol family
10733 11:14:10.095187 <6>[ 15.420803] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10734 11:14:10.105096 <6>[ 15.422139] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10735 11:14:10.111642 <6>[ 15.422284] usbcore: registered new interface driver uvcvideo
10736 11:14:10.118577 <6>[ 15.426693] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10737 11:14:10.124632 <6>[ 15.427309] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10738 11:14:10.131572 <6>[ 15.433371] Bluetooth: HCI device and connection manager initialized
10739 11:14:10.138381 <6>[ 15.433391] Bluetooth: HCI socket layer initialized
10740 11:14:10.144364 <6>[ 15.434184] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10741 11:14:10.147972 <6>[ 15.443377] pci 0000:00:00.0: supports D1 D2
10742 11:14:10.154137 <6>[ 15.447117] Bluetooth: L2CAP socket layer initialized
10743 11:14:10.161012 <6>[ 15.453383] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10744 11:14:10.167937 <6>[ 15.457734] Bluetooth: SCO socket layer initialized
10745 11:14:10.174137 <6>[ 15.465323] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10746 11:14:10.180964 <6>[ 15.514679] usbcore: registered new interface driver btusb
10747 11:14:10.190615 <4>[ 15.515431] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10748 11:14:10.197215 <3>[ 15.515440] Bluetooth: hci0: Failed to load firmware file (-2)
10749 11:14:10.203841 <3>[ 15.515443] Bluetooth: hci0: Failed to set up firmware (-2)
10750 11:14:10.213797 <4>[ 15.515446] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10751 11:14:10.220767 <6>[ 15.520789] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10752 11:14:10.227011 <6>[ 15.595551] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10753 11:14:10.233991 <6>[ 15.603060] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10754 11:14:10.240584 <6>[ 15.610577] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10755 11:14:10.247060 <6>[ 15.618201] pci 0000:01:00.0: supports D1 D2
10756 11:14:10.254143 <6>[ 15.622748] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10757 11:14:10.263727 <3>[ 15.630790] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10758 11:14:10.278728 <6>[ 15.645950] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10759 11:14:10.285070 <6>[ 15.652866] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10760 11:14:10.291341 <6>[ 15.660954] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10761 11:14:10.301625 <6>[ 15.668958] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10762 11:14:10.308321 <6>[ 15.676964] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10763 11:14:10.318438 <6>[ 15.684971] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10764 11:14:10.321381 <6>[ 15.692977] pci 0000:00:00.0: PCI bridge to [bus 01]
10765 11:14:10.331426 <6>[ 15.698199] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10766 11:14:10.338214 <6>[ 15.706353] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10767 11:14:10.344514 <6>[ 15.713578] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10768 11:14:10.350753 <6>[ 15.720573] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10769 11:14:10.368196 <5>[ 15.735786] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10770 11:14:10.386447 <5>[ 15.753882] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10771 11:14:10.393151 <4>[ 15.760765] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10772 11:14:10.399454 <6>[ 15.769663] cfg80211: failed to load regulatory.db
10773 11:14:10.442626 <6>[ 15.810382] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10774 11:14:10.449401 <6>[ 15.817930] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10775 11:14:10.473695 <6>[ 15.844809] mt7921e 0000:01:00.0: ASIC revision: 79610010
10776 11:14:10.582172 <4>[ 15.946824] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 11:14:10.598656 Begin: Loading essential drivers ... done.
10778 11:14:10.602219 Begin: Running /scripts/init-premount ... done.
10779 11:14:10.608707 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10780 11:14:10.618714 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10781 11:14:10.621894 Device /sys/class/net/enx002432307852 found
10782 11:14:10.621975 done.
10783 11:14:10.678153 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10784 11:14:10.707809 <4>[ 16.072192] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 11:14:10.827107 <4>[ 16.191751] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 11:14:10.943015 <4>[ 16.307585] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 11:14:11.058574 <4>[ 16.423485] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 11:14:11.174984 <4>[ 16.539508] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10789 11:14:11.291131 <4>[ 16.655460] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 11:14:11.406710 <4>[ 16.771528] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 11:14:11.522879 <4>[ 16.887456] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 11:14:11.638404 <4>[ 17.003387] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 11:14:11.733626 <6>[ 17.104769] r8152 2-1.3:1.0 enx002432307852: carrier on
10794 11:14:11.749996 <3>[ 17.121699] mt7921e 0000:01:00.0: hardware init failed
10795 11:14:11.764629 IP-Config: no response after 2 secs - giving up
10796 11:14:11.803028 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10797 11:14:12.912933 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10798 11:14:12.919159 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10799 11:14:12.925565 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10800 11:14:12.932157 host : mt8192-asurada-spherion-r0-cbg-3
10801 11:14:12.938724 domain : lava-rack
10802 11:14:12.945344 rootserver: 192.168.201.1 rootpath:
10803 11:14:12.945443 filename :
10804 11:14:12.969425 done.
10805 11:14:12.977148 Begin: Running /scripts/nfs-bottom ... done.
10806 11:14:12.994421 Begin: Running /scripts/init-bottom ... done.
10807 11:14:14.127421 <6>[ 19.499535] NET: Registered PF_INET6 protocol family
10808 11:14:14.134619 <6>[ 19.506331] Segment Routing with IPv6
10809 11:14:14.138423 <6>[ 19.510345] In-situ OAM (IOAM) with IPv6
10810 11:14:14.253862 <30>[ 19.605639] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10811 11:14:14.256961 <30>[ 19.629570] systemd[1]: Detected architecture arm64.
10812 11:14:14.277750
10813 11:14:14.281284 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10814 11:14:14.281374
10815 11:14:14.296719 <30>[ 19.668710] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10816 11:14:14.925642 <30>[ 20.294237] systemd[1]: Queued start job for default target Graphical Interface.
10817 11:14:14.955675 <30>[ 20.327243] systemd[1]: Created slice system-getty.slice.
10818 11:14:14.962189 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10819 11:14:14.978698 <30>[ 20.350613] systemd[1]: Created slice system-modprobe.slice.
10820 11:14:14.985346 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10821 11:14:15.003967 <30>[ 20.375202] systemd[1]: Created slice system-serial\x2dgetty.slice.
10822 11:14:15.013641 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10823 11:14:15.026846 <30>[ 20.398559] systemd[1]: Created slice User and Session Slice.
10824 11:14:15.033537 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10825 11:14:15.054206 <30>[ 20.422619] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10826 11:14:15.064568 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10827 11:14:15.082217 <30>[ 20.450223] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10828 11:14:15.088422 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10829 11:14:15.109345 <30>[ 20.474158] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10830 11:14:15.116218 <30>[ 20.486188] systemd[1]: Reached target Local Encrypted Volumes.
10831 11:14:15.122098 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10832 11:14:15.138470 <30>[ 20.510173] systemd[1]: Reached target Paths.
10833 11:14:15.141645 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10834 11:14:15.158008 <30>[ 20.530061] systemd[1]: Reached target Remote File Systems.
10835 11:14:15.165143 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10836 11:14:15.178117 <30>[ 20.550065] systemd[1]: Reached target Slices.
10837 11:14:15.181901 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10838 11:14:15.198416 <30>[ 20.570083] systemd[1]: Reached target Swap.
10839 11:14:15.201760 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10840 11:14:15.221560 <30>[ 20.590310] systemd[1]: Listening on initctl Compatibility Named Pipe.
10841 11:14:15.228507 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10842 11:14:15.234838 <30>[ 20.605832] systemd[1]: Listening on Journal Audit Socket.
10843 11:14:15.241334 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10844 11:14:15.255081 <30>[ 20.626979] systemd[1]: Listening on Journal Socket (/dev/log).
10845 11:14:15.261655 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10846 11:14:15.279447 <30>[ 20.650859] systemd[1]: Listening on Journal Socket.
10847 11:14:15.285998 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10848 11:14:15.302835 <30>[ 20.671481] systemd[1]: Listening on Network Service Netlink Socket.
10849 11:14:15.309989 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10850 11:14:15.325310 <30>[ 20.697003] systemd[1]: Listening on udev Control Socket.
10851 11:14:15.331987 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10852 11:14:15.346553 <30>[ 20.718326] systemd[1]: Listening on udev Kernel Socket.
10853 11:14:15.353433 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10854 11:14:15.386933 <30>[ 20.758394] systemd[1]: Mounting Huge Pages File System...
10855 11:14:15.393433 Mounting [0;1;39mHuge Pages File System[0m...
10856 11:14:15.409025 <30>[ 20.780468] systemd[1]: Mounting POSIX Message Queue File System...
10857 11:14:15.415690 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10858 11:14:15.432841 <30>[ 20.804475] systemd[1]: Mounting Kernel Debug File System...
10859 11:14:15.439507 Mounting [0;1;39mKernel Debug File System[0m...
10860 11:14:15.458208 <30>[ 20.826386] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10861 11:14:15.493963 <30>[ 20.862427] systemd[1]: Starting Create list of static device nodes for the current kernel...
10862 11:14:15.500425 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10863 11:14:15.521231 <30>[ 20.892749] systemd[1]: Starting Load Kernel Module configfs...
10864 11:14:15.527213 Starting [0;1;39mLoad Kernel Module configfs[0m...
10865 11:14:15.544948 <30>[ 20.916714] systemd[1]: Starting Load Kernel Module drm...
10866 11:14:15.551181 Starting [0;1;39mLoad Kernel Module drm[0m...
10867 11:14:15.568581 <30>[ 20.940683] systemd[1]: Starting Load Kernel Module fuse...
10868 11:14:15.575649 Starting [0;1;39mLoad Kernel Module fuse[0m...
10869 11:14:15.609221 <6>[ 20.980721] fuse: init (API version 7.37)
10870 11:14:15.619009 <30>[ 20.986162] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10871 11:14:15.647034 <30>[ 21.018576] systemd[1]: Starting Journal Service...
10872 11:14:15.649824 Starting [0;1;39mJournal Service[0m...
10873 11:14:15.674866 <30>[ 21.046963] systemd[1]: Starting Load Kernel Modules...
10874 11:14:15.681710 Starting [0;1;39mLoad Kernel Modules[0m...
10875 11:14:15.700334 <30>[ 21.068713] systemd[1]: Starting Remount Root and Kernel File Systems...
10876 11:14:15.707024 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10877 11:14:15.722289 <30>[ 21.093923] systemd[1]: Starting Coldplug All udev Devices...
10878 11:14:15.728361 Starting [0;1;39mColdplug All udev Devices[0m...
10879 11:14:15.745389 <30>[ 21.117254] systemd[1]: Mounted Huge Pages File System.
10880 11:14:15.752256 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10881 11:14:15.766966 <30>[ 21.138656] systemd[1]: Mounted POSIX Message Queue File System.
10882 11:14:15.773294 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10883 11:14:15.790474 <30>[ 21.162551] systemd[1]: Mounted Kernel Debug File System.
10884 11:14:15.797332 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10885 11:14:15.816021 <3>[ 21.184837] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 11:14:15.826531 <30>[ 21.194894] systemd[1]: Finished Create list of static device nodes for the current kernel.
10887 11:14:15.836363 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10888 11:14:15.853850 <3>[ 21.222189] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 11:14:15.860199 <30>[ 21.223000] systemd[1]: modprobe@configfs.service: Succeeded.
10890 11:14:15.867356 <30>[ 21.238013] systemd[1]: Finished Load Kernel Module configfs.
10891 11:14:15.873859 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10892 11:14:15.893360 <3>[ 21.261530] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 11:14:15.900176 <30>[ 21.271531] systemd[1]: modprobe@drm.service: Succeeded.
10894 11:14:15.906576 <30>[ 21.277867] systemd[1]: Finished Load Kernel Module drm.
10895 11:14:15.913428 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10896 11:14:15.924256 <3>[ 21.292287] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 11:14:15.931654 <30>[ 21.302912] systemd[1]: modprobe@fuse.service: Succeeded.
10898 11:14:15.937677 <30>[ 21.309229] systemd[1]: Finished Load Kernel Module fuse.
10899 11:14:15.944590 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10900 11:14:15.954623 <3>[ 21.323037] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 11:14:15.961642 <30>[ 21.333217] systemd[1]: Finished Load Kernel Modules.
10902 11:14:15.967646 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10903 11:14:15.984605 <3>[ 21.352922] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 11:14:15.994791 <30>[ 21.363328] systemd[1]: Finished Remount Root and Kernel File Systems.
10905 11:14:16.000886 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10906 11:14:16.018228 <3>[ 21.386775] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 11:14:16.051988 <3>[ 21.420506] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 11:14:16.066410 <30>[ 21.438128] systemd[1]: Mounting FUSE Control File System...
10909 11:14:16.073079 Mounting [0;1;39mFUSE Control File System[0m...
10910 11:14:16.083914 <3>[ 21.452566] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 11:14:16.096873 <30>[ 21.464837] systemd[1]: Mounting Kernel Configuration File System...
10912 11:14:16.099654 Mounting [0;1;39mKernel Configuration File System[0m...
10913 11:14:16.116606 <3>[ 21.485459] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 11:14:16.132343 <30>[ 21.500774] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10915 11:14:16.142415 <30>[ 21.509886] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10916 11:14:16.150278 <30>[ 21.522431] systemd[1]: Starting Load/Save Random Seed...
10917 11:14:16.157366 Starting [0;1;39mLoad/Save Random Seed[0m...
10918 11:14:16.172977 <30>[ 21.544692] systemd[1]: Starting Apply Kernel Variables...
10919 11:14:16.179177 Starting [0;1;39mApply Kernel Variables[0m...
10920 11:14:16.198300 <30>[ 21.570018] systemd[1]: Starting Create System Users...
10921 11:14:16.204506 Starting [0;1;39mCreate System Users[0m...
10922 11:14:16.220514 <30>[ 21.591725] systemd[1]: Started Journal Service.
10923 11:14:16.223264 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10924 11:14:16.244463 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10925 11:14:16.258444 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10926 11:14:16.282390 <4>[ 21.644221] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10927 11:14:16.292366 <3>[ 21.659960] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10928 11:14:16.295458 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10929 11:14:16.320029 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10930 11:14:16.334392 See 'systemctl status systemd-udev-trigger.service' for details.
10931 11:14:16.351316 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10932 11:14:16.371467 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10933 11:14:16.435040 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10934 11:14:16.452740 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10935 11:14:16.500128 <46>[ 21.868533] systemd-journald[292]: Received client request to flush runtime journal.
10936 11:14:16.540591 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10937 11:14:16.554951 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10938 11:14:16.570820 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10939 11:14:16.622310 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10940 11:14:17.879860 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10941 11:14:17.918921 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10942 11:14:17.967943 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10943 11:14:18.042685 Starting [0;1;39mNetwork Service[0m...
10944 11:14:18.327857 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10945 11:14:18.348237 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10946 11:14:18.401762 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10947 11:14:18.624389 <6>[ 23.996893] remoteproc remoteproc0: powering up scp
10948 11:14:18.656033 <4>[ 24.024906] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10949 11:14:18.662692 <3>[ 24.034806] remoteproc remoteproc0: request_firmware failed: -2
10950 11:14:18.672654 <3>[ 24.041000] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10951 11:14:18.754438 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10952 11:14:18.774388 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10953 11:14:18.791024 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10954 11:14:18.837036 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10955 11:14:18.857320 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10956 11:14:18.914973 Starting [0;1;39mNetwork Name Resolution[0m...
10957 11:14:18.938860 Starting [0;1;39mNetwork Time Synchronization[0m...
10958 11:14:18.960670 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10959 11:14:18.982293 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10960 11:14:19.012162 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10961 11:14:19.030280 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10962 11:14:19.208115 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10963 11:14:19.226431 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10964 11:14:19.245039 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10965 11:14:19.258212 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10966 11:14:19.274180 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10967 11:14:19.413491 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10968 11:14:19.447497 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10969 11:14:19.480209 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10970 11:14:19.509559 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10971 11:14:19.525987 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10972 11:14:19.551021 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10973 11:14:19.562459 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10974 11:14:19.578108 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10975 11:14:19.614180 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10976 11:14:19.646963 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10977 11:14:19.686597 Starting [0;1;39mUser Login Management[0m...
10978 11:14:19.702596 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10979 11:14:19.718671 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10980 11:14:19.737461 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10981 11:14:19.787257 Starting [0;1;39mPermit User Sessions[0m...
10982 11:14:19.896977 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10983 11:14:19.935801 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10984 11:14:19.955618 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10985 11:14:19.972345 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10986 11:14:19.994162 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10987 11:14:20.018264 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10988 11:14:20.039163 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10989 11:14:20.054474 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10990 11:14:20.091484 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10991 11:14:20.129364 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10992 11:14:20.198382
10993 11:14:20.198525
10994 11:14:20.201993 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10995 11:14:20.202086
10996 11:14:20.243885 debian-bullseye-arm64 login: root (automatic login)
10997 11:14:20.243994
10998 11:14:20.244060
10999 11:14:20.580420 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023 aarch64
11000 11:14:20.580573
11001 11:14:20.586834 The programs included with the Debian GNU/Linux system are free software;
11002 11:14:20.594020 the exact distribution terms for each program are described in the
11003 11:14:20.596800 individual files in /usr/share/doc/*/copyright.
11004 11:14:20.596934
11005 11:14:20.603594 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11006 11:14:20.603697 permitted by applicable law.
11007 11:14:20.684224 Matched prompt #10: / #
11009 11:14:20.684499 Setting prompt string to ['/ #']
11010 11:14:20.684595 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11012 11:14:20.684791 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11013 11:14:20.684879 start: 2.2.6 expect-shell-connection (timeout 00:03:20) [common]
11014 11:14:20.684951 Setting prompt string to ['/ #']
11015 11:14:20.685011 Forcing a shell prompt, looking for ['/ #']
11017 11:14:20.735203 / #
11018 11:14:20.735377 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11019 11:14:20.735474 Waiting using forced prompt support (timeout 00:02:30)
11020 11:14:20.740542
11021 11:14:20.740819 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11022 11:14:20.740916 start: 2.2.7 export-device-env (timeout 00:03:19) [common]
11024 11:14:20.841296 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591224/extract-nfsrootfs-h4vi_uqd'
11025 11:14:20.846152 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591224/extract-nfsrootfs-h4vi_uqd'
11027 11:14:20.946669 / # export NFS_SERVER_IP='192.168.201.1'
11028 11:14:20.951763 export NFS_SERVER_IP='192.168.201.1'
11029 11:14:20.952052 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11030 11:14:20.952149 end: 2.2 depthcharge-retry (duration 00:01:41) [common]
11031 11:14:20.952235 end: 2 depthcharge-action (duration 00:01:41) [common]
11032 11:14:20.952325 start: 3 lava-test-retry (timeout 00:30:00) [common]
11033 11:14:20.952412 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11034 11:14:20.952489 Using namespace: common
11036 11:14:21.052810 / # #
11037 11:14:21.052973 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11038 11:14:21.058300 #
11039 11:14:21.058569 Using /lava-10591224
11041 11:14:21.158910 / # export SHELL=/bin/sh
11042 11:14:21.164092 export SHELL=/bin/sh
11044 11:14:21.264658 / # . /lava-10591224/environment
11045 11:14:21.270420 . /lava-10591224/environment
11047 11:14:21.376449 / # /lava-10591224/bin/lava-test-runner /lava-10591224/0
11048 11:14:21.376611 Test shell timeout: 10s (minimum of the action and connection timeout)
11049 11:14:21.381675 /lava-10591224/bin/lava-test-runner /lava-10591224/0
11050 11:14:21.611384 + export TESTRUN_ID=0_lc-compliance
11051 11:14:21.618384 + cd /lava-10591224/0/tests/0_lc-compliance
11052 11:14:21.618476 + cat uuid
11053 11:14:21.625664 + UUID=10591224_1.6.2.3.1
11054 11:14:21.625749 + set +x
11055 11:14:21.632046 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 10591224_1.6.2.3.1>
11056 11:14:21.632308 Received signal: <STARTRUN> 0_lc-compliance 10591224_1.6.2.3.1
11057 11:14:21.632381 Starting test lava.0_lc-compliance (10591224_1.6.2.3.1)
11058 11:14:21.632468 Skipping test definition patterns.
11059 11:14:21.635020 + /usr/bin/lc-compliance-parser.sh
11060 11:14:22.849675 [0:00:28.022878348] [398] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:298 [0mlibcamera v0.0.0+1-76e1cb9f
11061 11:14:22.852724 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11062 11:14:22.862671 [0:00:28.037761087] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11063 11:14:22.923371 [0:00:28.095311661] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11064 11:14:22.940408 [==========] Running 120 tests from 1 test suite.
11065 11:14:22.980583 [0:00:28.151621908] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11066 11:14:23.016562 [----------] Global test environment set-up.
11067 11:14:23.037143 [0:00:28.206954875] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11068 11:14:23.100549 [----------] 120 tests from CaptureTests/SingleStream
11069 11:14:23.176177 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11070 11:14:23.238286 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11071 11:14:23.238597 Received signal: <TESTSET> START CaptureTests/SingleStream
11072 11:14:23.238699 Starting test_set CaptureTests/SingleStream
11073 11:14:23.241377 Camera needs 4 requests, can't test only 1
11074 11:14:23.314285 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11075 11:14:23.397668
11076 11:14:23.489166 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (59 ms)
11077 11:14:23.503295 [0:00:28.663450113] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11078 11:14:23.590210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11079 11:14:23.590542 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11081 11:14:23.605849 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11082 11:14:23.653137 Camera needs 4 requests, can't test only 2
11083 11:14:23.723864 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11084 11:14:23.813369
11085 11:14:23.906014 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (56 ms)
11086 11:14:23.973413 [0:00:29.124127147] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11087 11:14:24.008883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11088 11:14:24.009180 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11090 11:14:24.023212 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11091 11:14:24.073553 Camera needs 4 requests, can't test only 3
11092 11:14:24.146771 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11093 11:14:24.219376
11094 11:14:24.310278 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (55 ms)
11095 11:14:24.415115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11096 11:14:24.415428 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11098 11:14:24.431817 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11099 11:14:24.487208 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (456 ms)
11100 11:14:24.574965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11101 11:14:24.575270 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11103 11:14:24.593629 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11104 11:14:24.647814 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (462 ms)
11105 11:14:24.704282 [0:00:29.842355535] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11106 11:14:24.744491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11107 11:14:24.744779 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11109 11:14:24.761907 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11110 11:14:24.814975 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (718 ms)
11111 11:14:24.915244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11112 11:14:24.915608 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11114 11:14:24.931572 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11115 11:14:25.903035 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1187 ms)
11116 11:14:25.912996 [0:00:31.031498249] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11117 11:14:25.996839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11118 11:14:25.997137 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11120 11:14:26.011379 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11121 11:14:27.304194 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1383 ms)
11122 11:14:27.313831 [0:00:32.414442715] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11123 11:14:27.403050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11124 11:14:27.403405 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11126 11:14:27.419689 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11127 11:14:29.438358 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2111 ms)
11128 11:14:29.451198 [0:00:34.525319523] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11129 11:14:29.546702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11130 11:14:29.547022 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11132 11:14:29.563863 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11133 11:14:32.669862 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3208 ms)
11134 11:14:32.679732 [0:00:37.731704279] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11135 11:14:32.736783 [0:00:37.790745644] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11136 11:14:32.794317 [0:00:37.847879736] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11137 11:14:32.797743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11138 11:14:32.798022 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11140 11:14:32.812842 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11141 11:14:32.852043 [0:00:37.904935008] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11142 11:14:32.876197 Camera needs 4 requests, can't test only 1
11143 11:14:32.963247 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11144 11:14:33.052435
11145 11:14:33.140269 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (58 ms)
11146 11:14:33.222495 [0:00:38.272860660] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11147 11:14:33.249740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11148 11:14:33.250073 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11150 11:14:33.266462 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11151 11:14:33.323222 Camera needs 4 requests, can't test only 2
11152 11:14:33.412522 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11153 11:14:33.501556
11154 11:14:33.598235 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (57 ms)
11155 11:14:33.691018 [0:00:38.739434729] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11156 11:14:33.701406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11157 11:14:33.701723 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11159 11:14:33.717147 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11160 11:14:33.776668 Camera needs 4 requests, can't test only 3
11161 11:14:33.866099 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11162 11:14:33.951449
11163 11:14:34.039337 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (57 ms)
11164 11:14:34.142618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11165 11:14:34.142944 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11167 11:14:34.158191 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11168 11:14:34.209202 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (367 ms)
11169 11:14:34.305583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11170 11:14:34.305904 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11172 11:14:34.325680 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11173 11:14:34.377650 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (467 ms)
11174 11:14:34.390112 [0:00:39.434918971] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11175 11:14:34.474673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11176 11:14:34.474999 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11178 11:14:34.494298 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11179 11:14:34.553353 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (696 ms)
11180 11:14:34.650965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11181 11:14:34.651301 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11183 11:14:34.670992 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11184 11:14:35.583194 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1196 ms)
11185 11:14:35.596238 [0:00:40.630990329] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11186 11:14:35.705839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11187 11:14:35.706166 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11189 11:14:35.722933 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11190 11:14:36.980907 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1393 ms)
11191 11:14:36.994864 [0:00:42.023748362] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11192 11:14:37.093887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11193 11:14:37.094230 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11195 11:14:37.111780 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11196 11:14:39.114407 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2127 ms)
11197 11:14:39.127994 [0:00:44.150978455] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11198 11:14:39.224294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11199 11:14:39.224620 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11201 11:14:39.244697 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11202 11:14:41.009252 <6>[ 46.387526] vpu: disabling
11203 11:14:41.012576 <6>[ 46.390578] vproc2: disabling
11204 11:14:41.016084 <6>[ 46.393850] vproc1: disabling
11205 11:14:41.019235 <6>[ 46.397112] vaud18: disabling
11206 11:14:41.025473 <6>[ 46.400515] vsram_others: disabling
11207 11:14:41.029082 <6>[ 46.404435] va09: disabling
11208 11:14:41.032577 <6>[ 46.407542] vsram_md: disabling
11209 11:14:41.035228 <6>[ 46.411025] Vgpu: disabling
11210 11:14:42.343436 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3222 ms)
11211 11:14:42.356797 [0:00:47.373889081] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11212 11:14:42.410208 [0:00:47.432159945] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11213 11:14:42.467137 [0:00:47.489037067] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11214 11:14:42.473437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11215 11:14:42.474215 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11217 11:14:42.491457 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11218 11:14:42.523989 [0:00:47.546235132] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11219 11:14:42.563210 Camera needs 4 requests, can't test only 1
11220 11:14:42.665564 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11221 11:14:42.768280
11222 11:14:42.871084 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (59 ms)
11223 11:14:42.956271 [0:00:47.977862409] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11224 11:14:42.986799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11225 11:14:42.987083 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11227 11:14:43.003285 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11228 11:14:43.057502 Camera needs 4 requests, can't test only 2
11229 11:14:43.158112 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11230 11:14:43.240194
11231 11:14:43.328284 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (57 ms)
11232 11:14:43.425163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11233 11:14:43.425482 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11235 11:14:43.441599 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11236 11:14:43.491116 Camera needs 4 requests, can't test only 3
11237 11:14:43.562640 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11238 11:14:43.636951
11239 11:14:43.736992 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (57 ms)
11240 11:14:43.760985 [0:00:48.781805755] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11241 11:14:43.853223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11242 11:14:43.853527 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11244 11:14:43.869250 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11245 11:14:43.923308 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (431 ms)
11246 11:14:44.032240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11247 11:14:44.032542 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11249 11:14:44.051452 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11250 11:14:44.121283 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (804 ms)
11251 11:14:44.212485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11252 11:14:44.212820 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11254 11:14:44.228935 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11255 11:14:44.483856 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (730 ms)
11256 11:14:44.497171 [0:00:49.511262840] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11257 11:14:44.581232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11258 11:14:44.581529 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11260 11:14:44.595441 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11261 11:14:45.384409 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (900 ms)
11262 11:14:45.398121 [0:00:50.412743238] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11263 11:14:45.506046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11264 11:14:45.506437 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11266 11:14:45.521071 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11267 11:14:46.785524 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1399 ms)
11268 11:14:46.798866 [0:00:51.812331493] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11269 11:14:46.894146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11270 11:14:46.894498 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11272 11:14:46.908577 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11273 11:14:48.923272 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2133 ms)
11274 11:14:48.933465 [0:00:53.945276510] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11275 11:14:49.026154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11276 11:14:49.027229 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11278 11:14:49.042813 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11279 11:14:52.124823 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3201 ms)
11280 11:14:52.134726 [0:00:57.145306857] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11281 11:14:52.188865 [0:00:57.203785332] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11282 11:14:52.224974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11283 11:14:52.225256 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11285 11:14:52.244678 [0:00:57.259733622] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11286 11:14:52.248256 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11287 11:14:52.296297 Camera needs 4 requests, can't test only 1
11288 11:14:52.306452 [0:00:57.319190837] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11289 11:14:52.370443 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11290 11:14:52.439789
11291 11:14:52.516489 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (59 ms)
11292 11:14:52.610273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11293 11:14:52.610596 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11295 11:14:52.626236 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11296 11:14:52.676764 Camera needs 4 requests, can't test only 2
11297 11:14:52.754486 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11298 11:14:52.769821 [0:00:57.784482070] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11299 11:14:52.834622
11300 11:14:52.910851 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (56 ms)
11301 11:14:52.993170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11302 11:14:52.993488 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11304 11:14:53.008864 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11305 11:14:53.062347 Camera needs 4 requests, can't test only 3
11306 11:14:53.142987 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11307 11:14:53.214282
11308 11:14:53.240384 [0:00:58.255294745] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11309 11:14:53.305763 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (59 ms)
11310 11:14:53.389980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11311 11:14:53.390311 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11313 11:14:53.404393 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11314 11:14:53.451789 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (466 ms)
11315 11:14:53.532638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11316 11:14:53.532929 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11318 11:14:53.550243 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11319 11:14:53.600054 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (470 ms)
11320 11:14:53.696346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11321 11:14:53.696655 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11323 11:14:53.710210 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11324 11:14:53.965269 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (733 ms)
11325 11:14:53.978498 [0:00:58.989070401] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11326 11:14:54.056507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11327 11:14:54.056798 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11329 11:14:54.070338 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11330 11:14:54.867380 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (903 ms)
11331 11:14:54.880383 [0:00:59.891798552] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11332 11:14:54.956984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11333 11:14:54.957298 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11335 11:14:54.970949 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11336 11:14:56.205059 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1338 ms)
11337 11:14:56.218619 [0:01:01.228709311] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11338 11:14:56.303075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11339 11:14:56.303431 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11341 11:14:56.318748 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11342 11:14:58.337963 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2132 ms)
11343 11:14:58.350648 [0:01:03.360538487] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11344 11:14:58.437629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11345 11:14:58.437970 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11347 11:14:58.456855 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11348 11:15:01.569562 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3232 ms)
11349 11:15:01.582862 [0:01:06.592509319] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11350 11:15:01.636126 [0:01:06.651256887] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11351 11:15:01.681047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11352 11:15:01.681366 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11354 11:15:01.693744 [0:01:06.708859146] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11355 11:15:01.703538 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11356 11:15:01.750285 [0:01:06.765686226] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11357 11:15:01.762907 Camera needs 4 requests, can't test only 1
11358 11:15:01.841484 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11359 11:15:01.921413
11360 11:15:02.002824 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (59 ms)
11361 11:15:02.094389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11362 11:15:02.094703 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11364 11:15:02.115267 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11365 11:15:02.172281 Camera needs 4 requests, can't test only 2
11366 11:15:02.253499 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11367 11:15:02.333180
11368 11:15:02.415433 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (57 ms)
11369 11:15:02.497765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11370 11:15:02.498094 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11372 11:15:02.513579 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11373 11:15:02.563124 Camera needs 4 requests, can't test only 3
11374 11:15:02.634260 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11375 11:15:02.718003
11376 11:15:02.815137 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (57 ms)
11377 11:15:02.915019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11378 11:15:02.915338 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11380 11:15:02.929459 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11381 11:15:03.146866 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1404 ms)
11382 11:15:03.160077 [0:01:08.170545335] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11383 11:15:03.248274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11384 11:15:03.248690 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11386 11:15:03.262808 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11387 11:15:04.542411 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1395 ms)
11388 11:15:04.555987 [0:01:09.567662120] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11389 11:15:04.648296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11390 11:15:04.648599 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11392 11:15:04.662877 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11393 11:15:06.942742 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2400 ms)
11394 11:15:06.955765 [0:01:11.967634110] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11395 11:15:07.037270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11396 11:15:07.037591 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11398 11:15:07.053849 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11399 11:15:09.639946 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2697 ms)
11400 11:15:09.653135 [0:01:14.665089762] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11401 11:15:09.758184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11402 11:15:09.758939 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11404 11:15:09.774490 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11405 11:15:13.831578 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4193 ms)
11406 11:15:13.845049 [0:01:18.856641098] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11407 11:15:13.946523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11408 11:15:13.947293 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11410 11:15:13.966313 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11411 11:15:20.217900 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6387 ms)
11412 11:15:20.230972 [0:01:25.243933666] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11413 11:15:20.323161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11414 11:15:20.323460 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11416 11:15:20.338102 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11417 11:15:29.937660 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9720 ms)
11418 11:15:29.950403 [0:01:34.964667923] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11419 11:15:30.006870 [0:01:35.024482436] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11420 11:15:30.055584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11421 11:15:30.055916 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11423 11:15:30.068323 [0:01:35.084268059] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11424 11:15:30.077968 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11425 11:15:30.125563 [0:01:35.142413947] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11426 11:15:30.141096 Camera needs 4 requests, can't test only 1
11427 11:15:30.219691 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11428 11:15:30.291299
11429 11:15:30.388825 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (62 ms)
11430 11:15:30.503771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11431 11:15:30.504556 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11433 11:15:30.519187 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11434 11:15:30.591945 Camera needs 4 requests, can't test only 2
11435 11:15:30.674224 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11436 11:15:30.755387
11437 11:15:30.861912 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (59 ms)
11438 11:15:30.972999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11439 11:15:30.973764 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11441 11:15:30.986991 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11442 11:15:31.050808 Camera needs 4 requests, can't test only 3
11443 11:15:31.132605 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11444 11:15:31.201042
11445 11:15:31.298790 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (58 ms)
11446 11:15:31.385658 [0:01:36.402706922] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11447 11:15:31.407969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11448 11:15:31.408782 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11450 11:15:31.423765 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11451 11:15:31.486840 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1260 ms)
11452 11:15:31.589167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11453 11:15:31.589479 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11455 11:15:31.603097 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11456 11:15:32.902433 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1523 ms)
11457 11:15:32.912514 [0:01:37.925726716] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11458 11:15:32.999095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11459 11:15:32.999442 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11461 11:15:33.011953 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11462 11:15:35.092051 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2190 ms)
11463 11:15:35.101622 [0:01:40.115910236] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11464 11:15:35.192461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11465 11:15:35.192763 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11467 11:15:35.203148 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11468 11:15:38.696193 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (3604 ms)
11469 11:15:38.705983 [0:01:43.720800296] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11470 11:15:38.804345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11471 11:15:38.804747 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11473 11:15:38.815923 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11474 11:15:42.951148 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4256 ms)
11475 11:15:42.961178 [0:01:47.974120289] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11476 11:15:43.066882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11477 11:15:43.067215 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11479 11:15:43.079259 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11480 11:15:49.337709 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6387 ms)
11481 11:15:49.347573 [0:01:54.361575681] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11482 11:15:49.454518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11483 11:15:49.455271 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11485 11:15:49.471065 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11486 11:15:59.054732 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9717 ms)
11487 11:15:59.064787 [0:02:04.078882642] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11488 11:15:59.117960 [0:02:04.137835667] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11489 11:15:59.175174 [0:02:04.195037478] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11490 11:15:59.181656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11491 11:15:59.181946 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11493 11:15:59.191946 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11494 11:15:59.231987 [0:02:04.251563751] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11495 11:15:59.255746 Camera needs 4 requests, can't test only 1
11496 11:15:59.333866 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11497 11:15:59.410328
11498 11:15:59.509856 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (58 ms)
11499 11:15:59.622525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11500 11:15:59.623305 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11502 11:15:59.640335 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11503 11:15:59.703262 Camera needs 4 requests, can't test only 2
11504 11:15:59.789322 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11505 11:15:59.873482
11506 11:15:59.971645 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (58 ms)
11507 11:16:00.093140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11508 11:16:00.093974 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11510 11:16:00.107279 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11511 11:16:00.163689 Camera needs 4 requests, can't test only 3
11512 11:16:00.243487 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11513 11:16:00.330813
11514 11:16:00.424632 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (57 ms)
11515 11:16:00.461895 [0:02:05.480622998] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11516 11:16:00.543010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11517 11:16:00.543818 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11519 11:16:00.561890 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11520 11:16:00.625018 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1228 ms)
11521 11:16:00.740271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11522 11:16:00.741032 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11524 11:16:00.756291 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11525 11:16:01.851688 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1396 ms)
11526 11:16:01.861424 [0:02:06.876812469] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11527 11:16:01.950021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11528 11:16:01.950367 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11530 11:16:01.960994 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11531 11:16:03.942993 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2090 ms)
11532 11:16:03.952398 [0:02:08.967802318] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11533 11:16:04.040145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11534 11:16:04.040487 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11536 11:16:04.054244 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11537 11:16:06.936751 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2995 ms)
11538 11:16:06.946954 [0:02:11.962311639] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11539 11:16:07.037083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11540 11:16:07.037392 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11542 11:16:07.050634 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11543 11:16:11.129802 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4193 ms)
11544 11:16:11.139830 [0:02:16.155148524] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11545 11:16:11.227733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11546 11:16:11.228062 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11548 11:16:11.240355 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11549 11:16:17.448547 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6318 ms)
11550 11:16:17.458688 [0:02:22.472421482] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11551 11:16:17.533405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11552 11:16:17.533827 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11554 11:16:17.543990 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11555 11:16:27.166753 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9718 ms)
11556 11:16:27.176417 [0:02:32.191625521] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11557 11:16:27.233112 [0:02:32.250978896] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11558 11:16:27.275311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11559 11:16:27.275640 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11561 11:16:27.289652 [0:02:32.308066535] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11562 11:16:27.296171 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11563 11:16:27.347155 [0:02:32.365455986] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11564 11:16:27.350310 Camera needs 4 requests, can't test only 1
11565 11:16:27.430859 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11566 11:16:27.507275
11567 11:16:27.592368 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (61 ms)
11568 11:16:27.690087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11569 11:16:27.690407 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11571 11:16:27.702325 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11572 11:16:27.761734 Camera needs 4 requests, can't test only 2
11573 11:16:27.839749 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11574 11:16:27.909766
11575 11:16:28.007941 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (57 ms)
11576 11:16:28.116117 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11578 11:16:28.119597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11579 11:16:28.133084 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11580 11:16:28.183369 Camera needs 4 requests, can't test only 3
11581 11:16:28.257907 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11582 11:16:28.339752
11583 11:16:28.425574 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (57 ms)
11584 11:16:28.522082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11585 11:16:28.522390 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11587 11:16:28.542754 [0:02:33.560911649] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11588 11:16:28.549110 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11589 11:16:28.606755 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1195 ms)
11590 11:16:28.707191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11591 11:16:28.707509 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11593 11:16:28.720847 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11594 11:16:30.057554 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1520 ms)
11595 11:16:30.067663 [0:02:35.081045952] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11596 11:16:30.170288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11597 11:16:30.170604 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11599 11:16:30.182989 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11600 11:16:32.147466 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2090 ms)
11601 11:16:32.157390 [0:02:37.172166601] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11602 11:16:32.247589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11603 11:16:32.247885 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11605 11:16:32.257634 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11606 11:16:35.451892 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (3304 ms)
11607 11:16:35.461649 [0:02:40.477446517] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11608 11:16:35.560372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11609 11:16:35.560704 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11611 11:16:35.573976 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11612 11:16:39.645667 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4193 ms)
11613 11:16:39.655290 [0:02:44.670131708] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11614 11:16:39.741907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11615 11:16:39.742240 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11617 11:16:39.754498 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11618 11:16:46.032124 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6387 ms)
11619 11:16:46.042168 [0:02:51.056309827] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11620 11:16:46.132847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11621 11:16:46.133201 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11623 11:16:46.143712 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11624 11:16:56.050923 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (10019 ms)
11625 11:16:56.060926 [0:03:01.075693055] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11626 11:16:56.161578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11627 11:16:56.161880 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11629 11:16:56.173066 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11630 11:16:56.349889 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (302 ms)
11631 11:16:56.363263 [0:03:01.377519744] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11632 11:16:56.453413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11633 11:16:56.453716 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11635 11:16:56.469024 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11636 11:16:56.619274 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (269 ms)
11637 11:16:56.632158 [0:03:01.646864540] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11638 11:16:56.726458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11639 11:16:56.726779 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11641 11:16:56.743492 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11642 11:16:57.222549 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (603 ms)
11643 11:16:57.235764 [0:03:02.250872563] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11644 11:16:57.313867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11645 11:16:57.314182 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11647 11:16:57.330263 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11648 11:16:57.591146 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (369 ms)
11649 11:16:57.604277 [0:03:02.618911850] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11650 11:16:57.686502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11651 11:16:57.686804 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11653 11:16:57.702491 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11654 11:16:58.088988 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (497 ms)
11655 11:16:58.101766 [0:03:03.117249357] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11656 11:16:58.188365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11657 11:16:58.188676 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11659 11:16:58.204524 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11660 11:16:58.788001 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (699 ms)
11661 11:16:58.801536 [0:03:03.817658117] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11662 11:16:58.884292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11663 11:16:58.884605 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11665 11:16:58.899739 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11666 11:16:59.726396 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (938 ms)
11667 11:16:59.738861 [0:03:04.753322239] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11668 11:16:59.845858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11669 11:16:59.846208 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11671 11:16:59.860385 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11672 11:17:01.124676 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1399 ms)
11673 11:17:01.137651 [0:03:06.152050596] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11674 11:17:01.218703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11675 11:17:01.219095 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11677 11:17:01.233633 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11678 11:17:03.256060 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2131 ms)
11679 11:17:03.269840 [0:03:08.283229626] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11680 11:17:03.357835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11681 11:17:03.358199 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11683 11:17:03.372981 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11684 11:17:06.487597 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3229 ms)
11685 11:17:06.497764 [0:03:11.511727713] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11686 11:17:06.590849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11687 11:17:06.591254 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11689 11:17:06.606412 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11690 11:17:06.788028 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (300 ms)
11691 11:17:06.797333 [0:03:11.812261662] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11692 11:17:06.889361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11693 11:17:06.889720 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11695 11:17:06.902440 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11696 11:17:07.119790 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (332 ms)
11697 11:17:07.129276 [0:03:12.143963170] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11698 11:17:07.225992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11699 11:17:07.226359 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11701 11:17:07.237935 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11702 11:17:07.726450 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (606 ms)
11703 11:17:07.735852 [0:03:12.750811146] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11704 11:17:07.824611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11705 11:17:07.824925 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11707 11:17:07.837011 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11708 11:17:08.092896 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (367 ms)
11709 11:17:08.102698 [0:03:13.116943021] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11710 11:17:08.204506 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11712 11:17:08.207105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11713 11:17:08.220285 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11714 11:17:08.591798 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (499 ms)
11715 11:17:08.601592 [0:03:13.615842703] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11716 11:17:08.698971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11717 11:17:08.699296 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11719 11:17:08.712910 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11720 11:17:09.286196 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (694 ms)
11721 11:17:09.296051 [0:03:14.311584900] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11722 11:17:09.387861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11723 11:17:09.388182 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11725 11:17:09.400087 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11726 11:17:10.287654 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1001 ms)
11727 11:17:10.297159 [0:03:15.313081049] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11728 11:17:10.388571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11729 11:17:10.388883 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11731 11:17:10.399907 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11732 11:17:11.722174 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1434 ms)
11733 11:17:11.731769 [0:03:16.747471455] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11734 11:17:11.818704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11735 11:17:11.819021 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11737 11:17:11.831539 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11738 11:17:13.853665 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2132 ms)
11739 11:17:13.863643 [0:03:18.879485720] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11740 11:17:13.949596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11741 11:17:13.949941 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11743 11:17:13.961745 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11744 11:17:17.119485 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3266 ms)
11745 11:17:17.129050 [0:03:22.145046855] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11746 11:17:17.219578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11747 11:17:17.219909 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11749 11:17:17.232070 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11750 11:17:17.453423 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (334 ms)
11751 11:17:17.463335 [0:03:22.479097380] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11752 11:17:17.559284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11753 11:17:17.559671 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11755 11:17:17.569860 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11756 11:17:17.752163 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (299 ms)
11757 11:17:17.762004 [0:03:22.778464561] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11758 11:17:17.857596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11759 11:17:17.857921 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11761 11:17:17.871192 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11762 11:17:18.085817 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (334 ms)
11763 11:17:18.095926 [0:03:23.111974079] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11764 11:17:18.192469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11765 11:17:18.192810 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11767 11:17:18.203179 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11768 11:17:18.518880 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (432 ms)
11769 11:17:18.528995 [0:03:23.544874523] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11770 11:17:18.623159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11771 11:17:18.623484 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11773 11:17:18.636712 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11774 11:17:18.989247 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (471 ms)
11775 11:17:18.998767 [0:03:24.015089264] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11776 11:17:19.087338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11777 11:17:19.087693 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11779 11:17:19.099449 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11780 11:17:19.720274 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (731 ms)
11781 11:17:19.730041 [0:03:24.746976406] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11782 11:17:19.819656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11783 11:17:19.819981 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11785 11:17:19.832803 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11786 11:17:20.621614 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (901 ms)
11787 11:17:20.631311 [0:03:25.647775366] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11788 11:17:20.724244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11789 11:17:20.724567 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11791 11:17:20.735446 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11792 11:17:21.959625 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1338 ms)
11793 11:17:21.968791 [0:03:26.985105328] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11794 11:17:22.061712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11795 11:17:22.062046 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11797 11:17:22.073176 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11798 11:17:24.091597 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2132 ms)
11799 11:17:24.101566 [0:03:29.119231157] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11800 11:17:24.200882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11801 11:17:24.201193 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11803 11:17:24.217904 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11804 11:17:27.319521 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3227 ms)
11805 11:17:27.329245 [0:03:32.344667000] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11806 11:17:27.426263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11807 11:17:27.426566 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11809 11:17:27.439921 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11810 11:17:27.649283 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (331 ms)
11811 11:17:27.659301 [0:03:32.674844638] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11812 11:17:27.754783 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11814 11:17:27.757767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11815 11:17:27.771430 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11816 11:17:27.916392 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (266 ms)
11817 11:17:27.926284 [0:03:32.941680214] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11818 11:17:28.020818 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11820 11:17:28.023806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11821 11:17:28.038102 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11822 11:17:28.515130 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (599 ms)
11823 11:17:28.525169 [0:03:33.542937787] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11824 11:17:28.612299 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11826 11:17:28.615074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11827 11:17:28.630268 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11828 11:17:29.185456 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (670 ms)
11829 11:17:29.196036 [0:03:34.213210412] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11830 11:17:29.283767 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11832 11:17:29.286749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11833 11:17:29.300639 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11834 11:17:29.679910 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (494 ms)
11835 11:17:29.689585 [0:03:34.707150214] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11836 11:17:29.790428 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11838 11:17:29.793105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11839 11:17:29.808284 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11840 11:17:30.374629 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (695 ms)
11841 11:17:30.385470 [0:03:35.400294090] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11842 11:17:30.488741 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11844 11:17:30.491928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11845 11:17:30.506606 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11846 11:17:31.575795 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1201 ms)
11847 11:17:31.585969 [0:03:36.602963398] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11848 11:17:31.712853 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11850 11:17:31.715677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11851 11:17:31.735659 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11852 11:17:32.907127 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1331 ms)
11853 11:17:32.917374 [0:03:37.934033578] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11854 11:17:33.040131 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11856 11:17:33.042904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11857 11:17:33.060873 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11858 11:17:35.033992 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2127 ms)
11859 11:17:35.043328 [0:03:40.060309732] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11860 11:17:35.159329 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11862 11:17:35.162601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11863 11:17:35.181256 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11864 11:17:38.259965 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3227 ms)
11865 11:17:38.356871 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11867 11:17:38.360235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11868 11:17:38.374338 [----------] 120 tests from CaptureTests/SingleStream (195250 ms total)
11869 11:17:38.459656
11870 11:17:38.559773 [----------] Global test environment tear-down
11871 11:17:38.642270 [==========] 120 tests from 1 test suite ran. (195250 ms total)
11872 11:17:38.735698 <LAVA_SIGNAL_TESTSET STOP>
11873 11:17:38.736010 Received signal: <TESTSET> STOP
11874 11:17:38.736085 Closing test_set CaptureTests/SingleStream
11875 11:17:38.745874 + set +x
11876 11:17:38.749215 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 10591224_1.6.2.3.1>
11877 11:17:38.749468 Received signal: <ENDRUN> 0_lc-compliance 10591224_1.6.2.3.1
11878 11:17:38.749551 Ending use of test pattern.
11879 11:17:38.749614 Ending test lava.0_lc-compliance (10591224_1.6.2.3.1), duration 197.12
11881 11:17:38.752295 <LAVA_TEST_RUNNER EXIT>
11882 11:17:38.752548 ok: lava_test_shell seems to have completed
11883 11:17:38.754389 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11884 11:17:38.754581 end: 3.1 lava-test-shell (duration 00:03:18) [common]
11885 11:17:38.754671 end: 3 lava-test-retry (duration 00:03:18) [common]
11886 11:17:38.754760 start: 4 finalize (timeout 00:10:00) [common]
11887 11:17:38.754848 start: 4.1 power-off (timeout 00:00:30) [common]
11888 11:17:38.754997 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11889 11:17:38.829910 >> Command sent successfully.
11890 11:17:38.832316 Returned 0 in 0 seconds
11891 11:17:38.932732 end: 4.1 power-off (duration 00:00:00) [common]
11893 11:17:38.933056 start: 4.2 read-feedback (timeout 00:10:00) [common]
11894 11:17:38.933321 Listened to connection for namespace 'common' for up to 1s
11895 11:17:39.934270 Finalising connection for namespace 'common'
11896 11:17:39.934441 Disconnecting from shell: Finalise
11897 11:17:39.934522 / #
11898 11:17:40.034855 end: 4.2 read-feedback (duration 00:00:01) [common]
11899 11:17:40.035026 end: 4 finalize (duration 00:00:01) [common]
11900 11:17:40.035145 Cleaning after the job
11901 11:17:40.035242 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/ramdisk
11902 11:17:40.037327 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/kernel
11903 11:17:40.046009 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/dtb
11904 11:17:40.046193 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/nfsrootfs
11905 11:17:40.089696 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591224/tftp-deploy-8fgb2sfx/modules
11906 11:17:40.095422 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591224
11907 11:17:40.352652 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591224
11908 11:17:40.352854 Job finished correctly