Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 178
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 20
1 11:12:04.929702 lava-dispatcher, installed at version: 2023.05.1
2 11:12:04.929895 start: 0 validate
3 11:12:04.930024 Start time: 2023-06-05 11:12:04.930016+00:00 (UTC)
4 11:12:04.930141 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:12:04.930272 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 11:12:05.226376 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:12:05.226616 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:12:05.511806 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:12:05.511990 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:12:20.431023 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:12:20.431206 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:12:21.005765 validate duration: 16.08
14 11:12:21.006028 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:12:21.006127 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:12:21.006215 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:12:21.006338 Not decompressing ramdisk as can be used compressed.
18 11:12:21.006427 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/rootfs.cpio.gz
19 11:12:21.006492 saving as /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/ramdisk/rootfs.cpio.gz
20 11:12:21.006552 total size: 84903995 (80MB)
21 11:12:25.042059 progress 0% (0MB)
22 11:12:25.101207 progress 5% (4MB)
23 11:12:25.123350 progress 10% (8MB)
24 11:12:25.144579 progress 15% (12MB)
25 11:12:25.166121 progress 20% (16MB)
26 11:12:25.187046 progress 25% (20MB)
27 11:12:25.208097 progress 30% (24MB)
28 11:12:25.229272 progress 35% (28MB)
29 11:12:25.250515 progress 40% (32MB)
30 11:12:25.271445 progress 45% (36MB)
31 11:12:25.292931 progress 50% (40MB)
32 11:12:25.313965 progress 55% (44MB)
33 11:12:25.334916 progress 60% (48MB)
34 11:12:25.355724 progress 65% (52MB)
35 11:12:25.376245 progress 70% (56MB)
36 11:12:25.396917 progress 75% (60MB)
37 11:12:25.418145 progress 80% (64MB)
38 11:12:25.439498 progress 85% (68MB)
39 11:12:25.460406 progress 90% (72MB)
40 11:12:25.482273 progress 95% (76MB)
41 11:12:25.502742 progress 100% (80MB)
42 11:12:25.502872 80MB downloaded in 4.50s (18.01MB/s)
43 11:12:25.503052 end: 1.1.1 http-download (duration 00:00:04) [common]
45 11:12:25.503287 end: 1.1 download-retry (duration 00:00:04) [common]
46 11:12:25.503372 start: 1.2 download-retry (timeout 00:09:56) [common]
47 11:12:25.503454 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 11:12:25.503586 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:12:25.503656 saving as /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/kernel/Image
50 11:12:25.503717 total size: 45746688 (43MB)
51 11:12:25.503776 No compression specified
52 11:12:25.797756 progress 0% (0MB)
53 11:12:25.832071 progress 5% (2MB)
54 11:12:25.843646 progress 10% (4MB)
55 11:12:25.855081 progress 15% (6MB)
56 11:12:25.866623 progress 20% (8MB)
57 11:12:25.878073 progress 25% (10MB)
58 11:12:25.889280 progress 30% (13MB)
59 11:12:25.900610 progress 35% (15MB)
60 11:12:25.911948 progress 40% (17MB)
61 11:12:25.923282 progress 45% (19MB)
62 11:12:25.934704 progress 50% (21MB)
63 11:12:25.945952 progress 55% (24MB)
64 11:12:25.957515 progress 60% (26MB)
65 11:12:25.969104 progress 65% (28MB)
66 11:12:25.980599 progress 70% (30MB)
67 11:12:25.991943 progress 75% (32MB)
68 11:12:26.003210 progress 80% (34MB)
69 11:12:26.015606 progress 85% (37MB)
70 11:12:26.027186 progress 90% (39MB)
71 11:12:26.038432 progress 95% (41MB)
72 11:12:26.049494 progress 100% (43MB)
73 11:12:26.049615 43MB downloaded in 0.55s (79.92MB/s)
74 11:12:26.049759 end: 1.2.1 http-download (duration 00:00:01) [common]
76 11:12:26.049985 end: 1.2 download-retry (duration 00:00:01) [common]
77 11:12:26.050071 start: 1.3 download-retry (timeout 00:09:55) [common]
78 11:12:26.050194 start: 1.3.1 http-download (timeout 00:09:55) [common]
79 11:12:26.050332 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:12:26.050404 saving as /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/dtb/mt8192-asurada-spherion-r0.dtb
81 11:12:26.050466 total size: 46924 (0MB)
82 11:12:26.050524 No compression specified
83 11:12:26.051672 progress 69% (0MB)
84 11:12:26.051935 progress 100% (0MB)
85 11:12:26.052084 0MB downloaded in 0.00s (27.69MB/s)
86 11:12:26.052202 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:12:26.052423 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:12:26.052506 start: 1.4 download-retry (timeout 00:09:55) [common]
90 11:12:26.052587 start: 1.4.1 http-download (timeout 00:09:55) [common]
91 11:12:26.052693 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:12:26.052760 saving as /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/modules/modules.tar
93 11:12:26.052880 total size: 8547328 (8MB)
94 11:12:26.052970 Using unxz to decompress xz
95 11:12:26.056245 progress 0% (0MB)
96 11:12:26.077654 progress 5% (0MB)
97 11:12:26.101960 progress 10% (0MB)
98 11:12:26.127857 progress 15% (1MB)
99 11:12:26.151987 progress 20% (1MB)
100 11:12:26.177311 progress 25% (2MB)
101 11:12:26.201663 progress 30% (2MB)
102 11:12:26.226251 progress 35% (2MB)
103 11:12:26.250638 progress 40% (3MB)
104 11:12:26.275124 progress 45% (3MB)
105 11:12:26.298581 progress 50% (4MB)
106 11:12:26.321587 progress 55% (4MB)
107 11:12:26.347413 progress 60% (4MB)
108 11:12:26.372077 progress 65% (5MB)
109 11:12:26.397378 progress 70% (5MB)
110 11:12:26.424179 progress 75% (6MB)
111 11:12:26.453139 progress 80% (6MB)
112 11:12:26.475362 progress 85% (6MB)
113 11:12:26.499673 progress 90% (7MB)
114 11:12:26.522695 progress 95% (7MB)
115 11:12:26.546339 progress 100% (8MB)
116 11:12:26.552251 8MB downloaded in 0.50s (16.32MB/s)
117 11:12:26.552527 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:12:26.552814 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:12:26.552923 start: 1.5 prepare-tftp-overlay (timeout 00:09:54) [common]
121 11:12:26.553020 start: 1.5.1 extract-nfsrootfs (timeout 00:09:54) [common]
122 11:12:26.553102 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:12:26.553188 start: 1.5.2 lava-overlay (timeout 00:09:54) [common]
124 11:12:26.553408 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro
125 11:12:26.553535 makedir: /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin
126 11:12:26.553639 makedir: /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/tests
127 11:12:26.553734 makedir: /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/results
128 11:12:26.553847 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-add-keys
129 11:12:26.553989 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-add-sources
130 11:12:26.554116 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-background-process-start
131 11:12:26.554244 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-background-process-stop
132 11:12:26.554366 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-common-functions
133 11:12:26.554487 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-echo-ipv4
134 11:12:26.554610 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-install-packages
135 11:12:26.554728 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-installed-packages
136 11:12:26.554848 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-os-build
137 11:12:26.554968 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-probe-channel
138 11:12:26.555087 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-probe-ip
139 11:12:26.555206 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-target-ip
140 11:12:26.555325 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-target-mac
141 11:12:26.555443 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-target-storage
142 11:12:26.555566 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-test-case
143 11:12:26.555689 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-test-event
144 11:12:26.555807 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-test-feedback
145 11:12:26.555926 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-test-raise
146 11:12:26.556050 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-test-reference
147 11:12:26.556170 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-test-runner
148 11:12:26.556289 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-test-set
149 11:12:26.556415 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-test-shell
150 11:12:26.556539 Updating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-install-packages (oe)
151 11:12:26.556687 Updating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/bin/lava-installed-packages (oe)
152 11:12:26.556853 Creating /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/environment
153 11:12:26.556987 LAVA metadata
154 11:12:26.557093 - LAVA_JOB_ID=10591211
155 11:12:26.557168 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:12:26.557274 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:54) [common]
157 11:12:26.557341 skipped lava-vland-overlay
158 11:12:26.557417 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:12:26.557496 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
160 11:12:26.557557 skipped lava-multinode-overlay
161 11:12:26.557632 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:12:26.557715 start: 1.5.2.3 test-definition (timeout 00:09:54) [common]
163 11:12:26.557789 Loading test definitions
164 11:12:26.557882 start: 1.5.2.3.1 git-repo-action (timeout 00:09:54) [common]
165 11:12:26.557955 Using /lava-10591211 at stage 0
166 11:12:26.558050 Fetching tests from https://github.com/kernelci/kernelci-core
167 11:12:26.558131 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/0/tests/0_sleep'
168 11:12:27.343232 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/0/tests/0_sleep
169 11:12:27.344367 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 11:12:27.344753 uuid=10591211_1.5.2.3.1 testdef=None
171 11:12:27.344948 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 11:12:27.345202 start: 1.5.2.3.2 test-overlay (timeout 00:09:54) [common]
174 11:12:27.345757 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 11:12:27.345991 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:54) [common]
177 11:12:27.346661 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 11:12:27.346897 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
180 11:12:27.347560 runner path: /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/0/tests/0_sleep test_uuid 10591211_1.5.2.3.1
181 11:12:27.347646 sleep_params='mem freeze'
182 11:12:27.347784 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 11:12:27.347991 Creating lava-test-runner.conf files
185 11:12:27.348063 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591211/lava-overlay-kexx38ro/lava-10591211/0 for stage 0
186 11:12:27.348155 - 0_sleep
187 11:12:27.348257 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 11:12:27.348345 start: 1.5.2.4 compress-overlay (timeout 00:09:54) [common]
189 11:12:27.466053 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 11:12:27.466196 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
191 11:12:27.466289 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 11:12:27.466384 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 11:12:27.466471 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
194 11:12:29.737873 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 11:12:29.738212 start: 1.5.4 extract-modules (timeout 00:09:51) [common]
196 11:12:29.738336 extracting modules file /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591211/extract-overlay-ramdisk-y5a296b8/ramdisk
197 11:12:29.966278 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 11:12:29.966437 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
199 11:12:29.966537 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591211/compress-overlay-mfcsnqqb/overlay-1.5.2.4.tar.gz to ramdisk
200 11:12:29.966627 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591211/compress-overlay-mfcsnqqb/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591211/extract-overlay-ramdisk-y5a296b8/ramdisk
201 11:12:30.056486 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 11:12:30.056673 start: 1.5.6 configure-preseed-file (timeout 00:09:51) [common]
203 11:12:30.056822 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 11:12:30.056917 start: 1.5.7 compress-ramdisk (timeout 00:09:51) [common]
205 11:12:30.057011 Building ramdisk /var/lib/lava/dispatcher/tmp/10591211/extract-overlay-ramdisk-y5a296b8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591211/extract-overlay-ramdisk-y5a296b8/ramdisk
206 11:12:31.423831 >> 561590 blocks
207 11:12:41.038623 rename /var/lib/lava/dispatcher/tmp/10591211/extract-overlay-ramdisk-y5a296b8/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/ramdisk/ramdisk.cpio.gz
208 11:12:41.039021 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 11:12:41.039151 start: 1.5.8 prepare-kernel (timeout 00:09:40) [common]
210 11:12:41.039252 start: 1.5.8.1 prepare-fit (timeout 00:09:40) [common]
211 11:12:41.039360 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/kernel/Image'
212 11:12:52.603508 Returned 0 in 11 seconds
213 11:12:52.704391 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/kernel/image.itb
214 11:12:53.958169 output: FIT description: Kernel Image image with one or more FDT blobs
215 11:12:53.958558 output: Created: Mon Jun 5 12:12:53 2023
216 11:12:53.958640 output: Image 0 (kernel-1)
217 11:12:53.958708 output: Description:
218 11:12:53.958769 output: Created: Mon Jun 5 12:12:53 2023
219 11:12:53.958831 output: Type: Kernel Image
220 11:12:53.958888 output: Compression: lzma compressed
221 11:12:53.958944 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
222 11:12:53.959000 output: Architecture: AArch64
223 11:12:53.959058 output: OS: Linux
224 11:12:53.959113 output: Load Address: 0x00000000
225 11:12:53.959169 output: Entry Point: 0x00000000
226 11:12:53.959223 output: Hash algo: crc32
227 11:12:53.959275 output: Hash value: eb1cf9b8
228 11:12:53.959327 output: Image 1 (fdt-1)
229 11:12:53.959378 output: Description: mt8192-asurada-spherion-r0
230 11:12:53.959430 output: Created: Mon Jun 5 12:12:53 2023
231 11:12:53.959483 output: Type: Flat Device Tree
232 11:12:53.959534 output: Compression: uncompressed
233 11:12:53.959585 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
234 11:12:53.959637 output: Architecture: AArch64
235 11:12:53.959687 output: Hash algo: crc32
236 11:12:53.959738 output: Hash value: 1df858fa
237 11:12:53.959789 output: Image 2 (ramdisk-1)
238 11:12:53.959839 output: Description: unavailable
239 11:12:53.959891 output: Created: Mon Jun 5 12:12:53 2023
240 11:12:53.959942 output: Type: RAMDisk Image
241 11:12:53.959994 output: Compression: Unknown Compression
242 11:12:53.960045 output: Data Size: 98161597 Bytes = 95860.93 KiB = 93.61 MiB
243 11:12:53.960097 output: Architecture: AArch64
244 11:12:53.960148 output: OS: Linux
245 11:12:53.960199 output: Load Address: unavailable
246 11:12:53.960251 output: Entry Point: unavailable
247 11:12:53.960302 output: Hash algo: crc32
248 11:12:53.960353 output: Hash value: d6d08e23
249 11:12:53.960404 output: Default Configuration: 'conf-1'
250 11:12:53.960455 output: Configuration 0 (conf-1)
251 11:12:53.960507 output: Description: mt8192-asurada-spherion-r0
252 11:12:53.960558 output: Kernel: kernel-1
253 11:12:53.960609 output: Init Ramdisk: ramdisk-1
254 11:12:53.960660 output: FDT: fdt-1
255 11:12:53.960711 output: Loadables: kernel-1
256 11:12:53.960762 output:
257 11:12:53.960994 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
258 11:12:53.961088 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
259 11:12:53.961190 end: 1.5 prepare-tftp-overlay (duration 00:00:27) [common]
260 11:12:53.961281 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:27) [common]
261 11:12:53.961362 No LXC device requested
262 11:12:53.961438 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 11:12:53.961519 start: 1.7 deploy-device-env (timeout 00:09:27) [common]
264 11:12:53.961594 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 11:12:53.961658 Checking files for TFTP limit of 4294967296 bytes.
266 11:12:53.962127 end: 1 tftp-deploy (duration 00:00:33) [common]
267 11:12:53.962260 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 11:12:53.962350 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 11:12:53.962464 substitutions:
270 11:12:53.962532 - {DTB}: 10591211/tftp-deploy-c4dhww01/dtb/mt8192-asurada-spherion-r0.dtb
271 11:12:53.962592 - {INITRD}: 10591211/tftp-deploy-c4dhww01/ramdisk/ramdisk.cpio.gz
272 11:12:53.962649 - {KERNEL}: 10591211/tftp-deploy-c4dhww01/kernel/Image
273 11:12:53.962704 - {LAVA_MAC}: None
274 11:12:53.962758 - {PRESEED_CONFIG}: None
275 11:12:53.962812 - {PRESEED_LOCAL}: None
276 11:12:53.962865 - {RAMDISK}: 10591211/tftp-deploy-c4dhww01/ramdisk/ramdisk.cpio.gz
277 11:12:53.962917 - {ROOT_PART}: None
278 11:12:53.962970 - {ROOT}: None
279 11:12:53.963023 - {SERVER_IP}: 192.168.201.1
280 11:12:53.963075 - {TEE}: None
281 11:12:53.963127 Parsed boot commands:
282 11:12:53.963180 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 11:12:53.963344 Parsed boot commands: tftpboot 192.168.201.1 10591211/tftp-deploy-c4dhww01/kernel/image.itb 10591211/tftp-deploy-c4dhww01/kernel/cmdline
284 11:12:53.963432 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 11:12:53.963516 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 11:12:53.963604 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 11:12:53.963689 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 11:12:53.963759 Not connected, no need to disconnect.
289 11:12:53.963833 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 11:12:53.963908 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 11:12:53.963972 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
292 11:12:53.967099 Setting prompt string to ['lava-test: # ']
293 11:12:53.967447 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 11:12:53.967552 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 11:12:53.967649 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 11:12:53.967766 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 11:12:53.967968 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
298 11:12:59.114356 >> Command sent successfully.
299 11:12:59.126889 Returned 0 in 5 seconds
300 11:12:59.228129 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 11:12:59.229726 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 11:12:59.230272 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 11:12:59.230894 Setting prompt string to 'Starting depthcharge on Spherion...'
305 11:12:59.231271 Changing prompt to 'Starting depthcharge on Spherion...'
306 11:12:59.231639 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 11:12:59.233069 [Enter `^Ec?' for help]
308 11:12:59.390098
309 11:12:59.390692
310 11:12:59.391040 F0: 102B 0000
311 11:12:59.391365
312 11:12:59.393557 F3: 1001 0000 [0200]
313 11:12:59.394231
314 11:12:59.394606 F3: 1001 0000
315 11:12:59.394936
316 11:12:59.395249 F7: 102D 0000
317 11:12:59.395551
318 11:12:59.396570 F1: 0000 0000
319 11:12:59.397022
320 11:12:59.397363 V0: 0000 0000 [0001]
321 11:12:59.397679
322 11:12:59.399869 00: 0007 8000
323 11:12:59.400317
324 11:12:59.400662 01: 0000 0000
325 11:12:59.401022
326 11:12:59.403350 BP: 0C00 0209 [0000]
327 11:12:59.403775
328 11:12:59.404112 G0: 1182 0000
329 11:12:59.404429
330 11:12:59.406618 EC: 0000 0021 [4000]
331 11:12:59.407048
332 11:12:59.407387 S7: 0000 0000 [0000]
333 11:12:59.407705
334 11:12:59.410523 CC: 0000 0000 [0001]
335 11:12:59.411167
336 11:12:59.411520 T0: 0000 0040 [010F]
337 11:12:59.411844
338 11:12:59.413500 Jump to BL
339 11:12:59.414002
340 11:12:59.437135
341 11:12:59.437676
342 11:12:59.438121
343 11:12:59.444512 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 11:12:59.448240 ARM64: Exception handlers installed.
345 11:12:59.451606 ARM64: Testing exception
346 11:12:59.455147 ARM64: Done test exception
347 11:12:59.461774 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 11:12:59.472310 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 11:12:59.479058 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 11:12:59.488518 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 11:12:59.495399 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 11:12:59.502061 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 11:12:59.513807 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 11:12:59.520863 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 11:12:59.540251 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 11:12:59.543349 WDT: Last reset was cold boot
357 11:12:59.547043 SPI1(PAD0) initialized at 2873684 Hz
358 11:12:59.550023 SPI5(PAD0) initialized at 992727 Hz
359 11:12:59.553621 VBOOT: Loading verstage.
360 11:12:59.560263 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 11:12:59.563627 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 11:12:59.566684 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 11:12:59.569905 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 11:12:59.577689 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 11:12:59.584147 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 11:12:59.595137 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
367 11:12:59.595672
368 11:12:59.596020
369 11:12:59.605053 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 11:12:59.608347 ARM64: Exception handlers installed.
371 11:12:59.611594 ARM64: Testing exception
372 11:12:59.612032 ARM64: Done test exception
373 11:12:59.618338 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 11:12:59.621621 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 11:12:59.636368 Probing TPM: . done!
376 11:12:59.636945 TPM ready after 0 ms
377 11:12:59.643229 Connected to device vid:did:rid of 1ae0:0028:00
378 11:12:59.652892 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
379 11:12:59.708148 Initialized TPM device CR50 revision 0
380 11:12:59.718920 tlcl_send_startup: Startup return code is 0
381 11:12:59.719385 TPM: setup succeeded
382 11:12:59.730576 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 11:12:59.739373 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 11:12:59.745936 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 11:12:59.758739 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 11:12:59.762012 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 11:12:59.770130 in-header: 03 07 00 00 08 00 00 00
388 11:12:59.773769 in-data: aa e4 47 04 13 02 00 00
389 11:12:59.777706 Chrome EC: UHEPI supported
390 11:12:59.784475 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 11:12:59.788117 in-header: 03 ad 00 00 08 00 00 00
392 11:12:59.791788 in-data: 00 20 20 08 00 00 00 00
393 11:12:59.792220 Phase 1
394 11:12:59.795591 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 11:12:59.803347 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 11:12:59.806755 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 11:12:59.810255 Recovery requested (1009000e)
398 11:12:59.821349 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 11:12:59.824869 tlcl_extend: response is 0
400 11:12:59.834699 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 11:12:59.840624 tlcl_extend: response is 0
402 11:12:59.847604 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 11:12:59.868248 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 11:12:59.875238 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 11:12:59.875670
406 11:12:59.876011
407 11:12:59.884695 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 11:12:59.888333 ARM64: Exception handlers installed.
409 11:12:59.888762 ARM64: Testing exception
410 11:12:59.892156 ARM64: Done test exception
411 11:12:59.913171 pmic_efuse_setting: Set efuses in 11 msecs
412 11:12:59.916722 pmwrap_interface_init: Select PMIF_VLD_RDY
413 11:12:59.924146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 11:12:59.927010 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 11:12:59.933538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 11:12:59.937170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 11:12:59.940409 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 11:12:59.947302 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 11:12:59.950679 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 11:12:59.958149 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 11:12:59.962178 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 11:12:59.965608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 11:12:59.969298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 11:12:59.976030 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 11:12:59.979545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 11:12:59.986536 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 11:12:59.992812 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 11:12:59.996410 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 11:13:00.003925 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 11:13:00.007531 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 11:13:00.014952 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 11:13:00.017850 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 11:13:00.024976 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 11:13:00.032403 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 11:13:00.035509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 11:13:00.041967 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 11:13:00.045315 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 11:13:00.052229 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 11:13:00.058756 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 11:13:00.061967 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 11:13:00.068913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 11:13:00.072078 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 11:13:00.079105 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 11:13:00.082367 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 11:13:00.088928 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 11:13:00.092338 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 11:13:00.095703 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 11:13:00.102183 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 11:13:00.108709 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 11:13:00.112346 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 11:13:00.115780 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 11:13:00.122585 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 11:13:00.126325 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 11:13:00.129507 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 11:13:00.132817 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 11:13:00.140048 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 11:13:00.143052 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 11:13:00.146744 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 11:13:00.152927 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 11:13:00.156196 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 11:13:00.159565 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 11:13:00.162713 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 11:13:00.169762 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 11:13:00.176075 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 11:13:00.185911 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 11:13:00.189120 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 11:13:00.196005 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 11:13:00.205992 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 11:13:00.209071 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 11:13:00.215730 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 11:13:00.219097 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 11:13:00.225982 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x13
473 11:13:00.232394 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 11:13:00.235650 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 11:13:00.242318 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 11:13:00.250750 [RTC]rtc_get_frequency_meter,154: input=15, output=771
477 11:13:00.260252 [RTC]rtc_get_frequency_meter,154: input=23, output=958
478 11:13:00.269682 [RTC]rtc_get_frequency_meter,154: input=19, output=865
479 11:13:00.278849 [RTC]rtc_get_frequency_meter,154: input=17, output=819
480 11:13:00.288868 [RTC]rtc_get_frequency_meter,154: input=16, output=795
481 11:13:00.292117 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
482 11:13:00.298438 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
483 11:13:00.301784 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
484 11:13:00.304590 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
485 11:13:00.308056 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
486 11:13:00.311546 ADC[4]: Raw value=903245 ID=7
487 11:13:00.315166 ADC[3]: Raw value=213179 ID=1
488 11:13:00.318429 RAM Code: 0x71
489 11:13:00.322211 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
490 11:13:00.325083 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
491 11:13:00.335418 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
492 11:13:00.341874 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 11:13:00.345038 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
494 11:13:00.348619 in-header: 03 07 00 00 08 00 00 00
495 11:13:00.351810 in-data: aa e4 47 04 13 02 00 00
496 11:13:00.355271 Chrome EC: UHEPI supported
497 11:13:00.361771 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
498 11:13:00.365160 in-header: 03 ed 00 00 08 00 00 00
499 11:13:00.368396 in-data: 80 20 60 08 00 00 00 00
500 11:13:00.371929 MRC: failed to locate region type 0.
501 11:13:00.378368 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
502 11:13:00.381525 DRAM-K: Running full calibration
503 11:13:00.388521 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
504 11:13:00.389086 header.status = 0x0
505 11:13:00.391710 header.version = 0x6 (expected: 0x6)
506 11:13:00.395029 header.size = 0xd00 (expected: 0xd00)
507 11:13:00.398892 header.flags = 0x0
508 11:13:00.404918 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
509 11:13:00.421665 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
510 11:13:00.428711 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
511 11:13:00.432081 dram_init: ddr_geometry: 2
512 11:13:00.432517 [EMI] MDL number = 2
513 11:13:00.436178 [EMI] Get MDL freq = 0
514 11:13:00.436612 dram_init: ddr_type: 0
515 11:13:00.439385 is_discrete_lpddr4: 1
516 11:13:00.442976 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
517 11:13:00.443412
518 11:13:00.443757
519 11:13:00.447070 [Bian_co] ETT version 0.0.0.1
520 11:13:00.450800 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
521 11:13:00.451249
522 11:13:00.454427 dramc_set_vcore_voltage set vcore to 650000
523 11:13:00.458128 Read voltage for 800, 4
524 11:13:00.458568 Vio18 = 0
525 11:13:00.458906 Vcore = 650000
526 11:13:00.459222 Vdram = 0
527 11:13:00.461727 Vddq = 0
528 11:13:00.462152 Vmddr = 0
529 11:13:00.465472 dram_init: config_dvfs: 1
530 11:13:00.469161 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
531 11:13:00.472612 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
532 11:13:00.476702 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
533 11:13:00.480059 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
534 11:13:00.486758 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
535 11:13:00.490524 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
536 11:13:00.490983 MEM_TYPE=3, freq_sel=18
537 11:13:00.493536 sv_algorithm_assistance_LP4_1600
538 11:13:00.500289 ============ PULL DRAM RESETB DOWN ============
539 11:13:00.503616 ========== PULL DRAM RESETB DOWN end =========
540 11:13:00.506913 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
541 11:13:00.510184 ===================================
542 11:13:00.513502 LPDDR4 DRAM CONFIGURATION
543 11:13:00.517162 ===================================
544 11:13:00.517597 EX_ROW_EN[0] = 0x0
545 11:13:00.520366 EX_ROW_EN[1] = 0x0
546 11:13:00.523466 LP4Y_EN = 0x0
547 11:13:00.523895 WORK_FSP = 0x0
548 11:13:00.526630 WL = 0x2
549 11:13:00.527059 RL = 0x2
550 11:13:00.530300 BL = 0x2
551 11:13:00.530733 RPST = 0x0
552 11:13:00.533406 RD_PRE = 0x0
553 11:13:00.533835 WR_PRE = 0x1
554 11:13:00.536810 WR_PST = 0x0
555 11:13:00.537242 DBI_WR = 0x0
556 11:13:00.540321 DBI_RD = 0x0
557 11:13:00.540824 OTF = 0x1
558 11:13:00.544119 ===================================
559 11:13:00.547691 ===================================
560 11:13:00.548121 ANA top config
561 11:13:00.551511 ===================================
562 11:13:00.555313 DLL_ASYNC_EN = 0
563 11:13:00.558568 ALL_SLAVE_EN = 1
564 11:13:00.559046 NEW_RANK_MODE = 1
565 11:13:00.562408 DLL_IDLE_MODE = 1
566 11:13:00.566092 LP45_APHY_COMB_EN = 1
567 11:13:00.569226 TX_ODT_DIS = 1
568 11:13:00.569734 NEW_8X_MODE = 1
569 11:13:00.572603 ===================================
570 11:13:00.576043 ===================================
571 11:13:00.579271 data_rate = 1600
572 11:13:00.582405 CKR = 1
573 11:13:00.586254 DQ_P2S_RATIO = 8
574 11:13:00.589526 ===================================
575 11:13:00.592827 CA_P2S_RATIO = 8
576 11:13:00.593254 DQ_CA_OPEN = 0
577 11:13:00.596088 DQ_SEMI_OPEN = 0
578 11:13:00.599529 CA_SEMI_OPEN = 0
579 11:13:00.603048 CA_FULL_RATE = 0
580 11:13:00.605995 DQ_CKDIV4_EN = 1
581 11:13:00.609223 CA_CKDIV4_EN = 1
582 11:13:00.609688 CA_PREDIV_EN = 0
583 11:13:00.612337 PH8_DLY = 0
584 11:13:00.615780 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
585 11:13:00.619644 DQ_AAMCK_DIV = 4
586 11:13:00.623066 CA_AAMCK_DIV = 4
587 11:13:00.626199 CA_ADMCK_DIV = 4
588 11:13:00.626759 DQ_TRACK_CA_EN = 0
589 11:13:00.629244 CA_PICK = 800
590 11:13:00.632367 CA_MCKIO = 800
591 11:13:00.635612 MCKIO_SEMI = 0
592 11:13:00.639160 PLL_FREQ = 3068
593 11:13:00.642668 DQ_UI_PI_RATIO = 32
594 11:13:00.646188 CA_UI_PI_RATIO = 0
595 11:13:00.649167 ===================================
596 11:13:00.652600 ===================================
597 11:13:00.653127 memory_type:LPDDR4
598 11:13:00.655929 GP_NUM : 10
599 11:13:00.659347 SRAM_EN : 1
600 11:13:00.659896 MD32_EN : 0
601 11:13:00.662906 ===================================
602 11:13:00.666677 [ANA_INIT] >>>>>>>>>>>>>>
603 11:13:00.670126 <<<<<< [CONFIGURE PHASE]: ANA_TX
604 11:13:00.670582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
605 11:13:00.673643 ===================================
606 11:13:00.677386 data_rate = 1600,PCW = 0X7600
607 11:13:00.681069 ===================================
608 11:13:00.684881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
609 11:13:00.688628 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
610 11:13:00.696349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
611 11:13:00.699857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
612 11:13:00.703015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
613 11:13:00.706759 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
614 11:13:00.710032 [ANA_INIT] flow start
615 11:13:00.710458 [ANA_INIT] PLL >>>>>>>>
616 11:13:00.713411 [ANA_INIT] PLL <<<<<<<<
617 11:13:00.716585 [ANA_INIT] MIDPI >>>>>>>>
618 11:13:00.720241 [ANA_INIT] MIDPI <<<<<<<<
619 11:13:00.720663 [ANA_INIT] DLL >>>>>>>>
620 11:13:00.723627 [ANA_INIT] flow end
621 11:13:00.727051 ============ LP4 DIFF to SE enter ============
622 11:13:00.729989 ============ LP4 DIFF to SE exit ============
623 11:13:00.733214 [ANA_INIT] <<<<<<<<<<<<<
624 11:13:00.736385 [Flow] Enable top DCM control >>>>>
625 11:13:00.739906 [Flow] Enable top DCM control <<<<<
626 11:13:00.743118 Enable DLL master slave shuffle
627 11:13:00.746659 ==============================================================
628 11:13:00.749765 Gating Mode config
629 11:13:00.756266 ==============================================================
630 11:13:00.756691 Config description:
631 11:13:00.766595 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
632 11:13:00.773737 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
633 11:13:00.779971 SELPH_MODE 0: By rank 1: By Phase
634 11:13:00.783085 ==============================================================
635 11:13:00.787094 GAT_TRACK_EN = 1
636 11:13:00.790390 RX_GATING_MODE = 2
637 11:13:00.793708 RX_GATING_TRACK_MODE = 2
638 11:13:00.796666 SELPH_MODE = 1
639 11:13:00.800204 PICG_EARLY_EN = 1
640 11:13:00.803257 VALID_LAT_VALUE = 1
641 11:13:00.806832 ==============================================================
642 11:13:00.809617 Enter into Gating configuration >>>>
643 11:13:00.812867 Exit from Gating configuration <<<<
644 11:13:00.816295 Enter into DVFS_PRE_config >>>>>
645 11:13:00.829604 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
646 11:13:00.830114 Exit from DVFS_PRE_config <<<<<
647 11:13:00.833226 Enter into PICG configuration >>>>
648 11:13:00.836486 Exit from PICG configuration <<<<
649 11:13:00.839809 [RX_INPUT] configuration >>>>>
650 11:13:00.843102 [RX_INPUT] configuration <<<<<
651 11:13:00.849684 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
652 11:13:00.853031 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
653 11:13:00.859731 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
654 11:13:00.866093 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
655 11:13:00.873152 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
656 11:13:00.879263 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
657 11:13:00.882944 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
658 11:13:00.886172 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
659 11:13:00.889953 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
660 11:13:00.893703 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
661 11:13:00.900123 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
662 11:13:00.903459 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
663 11:13:00.906613 ===================================
664 11:13:00.910225 LPDDR4 DRAM CONFIGURATION
665 11:13:00.913281 ===================================
666 11:13:00.913711 EX_ROW_EN[0] = 0x0
667 11:13:00.917004 EX_ROW_EN[1] = 0x0
668 11:13:00.917435 LP4Y_EN = 0x0
669 11:13:00.920260 WORK_FSP = 0x0
670 11:13:00.920687 WL = 0x2
671 11:13:00.923603 RL = 0x2
672 11:13:00.923906 BL = 0x2
673 11:13:00.926572 RPST = 0x0
674 11:13:00.926802 RD_PRE = 0x0
675 11:13:00.929997 WR_PRE = 0x1
676 11:13:00.930227 WR_PST = 0x0
677 11:13:00.933281 DBI_WR = 0x0
678 11:13:00.933465 DBI_RD = 0x0
679 11:13:00.936640 OTF = 0x1
680 11:13:00.939822 ===================================
681 11:13:00.943031 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
682 11:13:00.946675 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
683 11:13:00.953188 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
684 11:13:00.956484 ===================================
685 11:13:00.956605 LPDDR4 DRAM CONFIGURATION
686 11:13:00.959779 ===================================
687 11:13:00.962954 EX_ROW_EN[0] = 0x10
688 11:13:00.966499 EX_ROW_EN[1] = 0x0
689 11:13:00.966586 LP4Y_EN = 0x0
690 11:13:00.969816 WORK_FSP = 0x0
691 11:13:00.969910 WL = 0x2
692 11:13:00.973008 RL = 0x2
693 11:13:00.973095 BL = 0x2
694 11:13:00.976756 RPST = 0x0
695 11:13:00.976891 RD_PRE = 0x0
696 11:13:00.980324 WR_PRE = 0x1
697 11:13:00.980413 WR_PST = 0x0
698 11:13:00.984117 DBI_WR = 0x0
699 11:13:00.984205 DBI_RD = 0x0
700 11:13:00.987448 OTF = 0x1
701 11:13:00.991521 ===================================
702 11:13:00.994620 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
703 11:13:00.999349 nWR fixed to 40
704 11:13:01.003048 [ModeRegInit_LP4] CH0 RK0
705 11:13:01.003141 [ModeRegInit_LP4] CH0 RK1
706 11:13:01.006742 [ModeRegInit_LP4] CH1 RK0
707 11:13:01.010325 [ModeRegInit_LP4] CH1 RK1
708 11:13:01.010455 match AC timing 13
709 11:13:01.013549 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
710 11:13:01.017108 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
711 11:13:01.024332 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
712 11:13:01.028148 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
713 11:13:01.031837 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
714 11:13:01.035204 [EMI DOE] emi_dcm 0
715 11:13:01.039018 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
716 11:13:01.039102 ==
717 11:13:01.042824 Dram Type= 6, Freq= 0, CH_0, rank 0
718 11:13:01.046559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
719 11:13:01.046645 ==
720 11:13:01.053753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
721 11:13:01.057411 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
722 11:13:01.067444 [CA 0] Center 38 (7~69) winsize 63
723 11:13:01.071670 [CA 1] Center 38 (7~69) winsize 63
724 11:13:01.075106 [CA 2] Center 35 (5~66) winsize 62
725 11:13:01.078571 [CA 3] Center 35 (5~66) winsize 62
726 11:13:01.082137 [CA 4] Center 35 (4~66) winsize 63
727 11:13:01.085840 [CA 5] Center 33 (3~64) winsize 62
728 11:13:01.086412
729 11:13:01.089252 [CmdBusTrainingLP45] Vref(ca) range 1: 32
730 11:13:01.089747
731 11:13:01.092894 [CATrainingPosCal] consider 1 rank data
732 11:13:01.093347 u2DelayCellTimex100 = 270/100 ps
733 11:13:01.096875 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
734 11:13:01.100854 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
735 11:13:01.104454 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
736 11:13:01.111430 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
737 11:13:01.115220 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
738 11:13:01.118883 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
739 11:13:01.119374
740 11:13:01.122400 CA PerBit enable=1, Macro0, CA PI delay=33
741 11:13:01.122942
742 11:13:01.123307 [CBTSetCACLKResult] CA Dly = 33
743 11:13:01.126148 CS Dly: 5 (0~36)
744 11:13:01.126622 ==
745 11:13:01.129852 Dram Type= 6, Freq= 0, CH_0, rank 1
746 11:13:01.133238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
747 11:13:01.133565 ==
748 11:13:01.136750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
749 11:13:01.143584 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
750 11:13:01.153703 [CA 0] Center 38 (7~69) winsize 63
751 11:13:01.157476 [CA 1] Center 38 (7~69) winsize 63
752 11:13:01.161482 [CA 2] Center 36 (5~67) winsize 63
753 11:13:01.165255 [CA 3] Center 35 (5~66) winsize 62
754 11:13:01.169080 [CA 4] Center 35 (4~66) winsize 63
755 11:13:01.169210 [CA 5] Center 34 (4~65) winsize 62
756 11:13:01.169325
757 11:13:01.175968 [CmdBusTrainingLP45] Vref(ca) range 1: 32
758 11:13:01.176089
759 11:13:01.179668 [CATrainingPosCal] consider 2 rank data
760 11:13:01.179779 u2DelayCellTimex100 = 270/100 ps
761 11:13:01.183284 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
762 11:13:01.187023 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
763 11:13:01.190461 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
764 11:13:01.194350 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
765 11:13:01.198182 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
766 11:13:01.201947 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
767 11:13:01.202045
768 11:13:01.205722 CA PerBit enable=1, Macro0, CA PI delay=34
769 11:13:01.205800
770 11:13:01.209160 [CBTSetCACLKResult] CA Dly = 34
771 11:13:01.212636 CS Dly: 6 (0~38)
772 11:13:01.212728
773 11:13:01.216337 ----->DramcWriteLeveling(PI) begin...
774 11:13:01.216426 ==
775 11:13:01.220216 Dram Type= 6, Freq= 0, CH_0, rank 0
776 11:13:01.223805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
777 11:13:01.223891 ==
778 11:13:01.227414 Write leveling (Byte 0): 29 => 29
779 11:13:01.227528 Write leveling (Byte 1): 29 => 29
780 11:13:01.231154 DramcWriteLeveling(PI) end<-----
781 11:13:01.231265
782 11:13:01.231360 ==
783 11:13:01.234748 Dram Type= 6, Freq= 0, CH_0, rank 0
784 11:13:01.238580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
785 11:13:01.238685 ==
786 11:13:01.242148 [Gating] SW mode calibration
787 11:13:01.249165 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
788 11:13:01.256646 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
789 11:13:01.260146 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
790 11:13:01.263744 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
791 11:13:01.267527 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
792 11:13:01.271363 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:13:01.278631 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:13:01.282440 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:13:01.286190 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:13:01.289758 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:13:01.293196 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:13:01.300634 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:13:01.304206 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:13:01.307710 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:13:01.310802 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:13:01.317119 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:13:01.320900 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:13:01.323895 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:13:01.330747 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
806 11:13:01.334023 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
807 11:13:01.337328 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
808 11:13:01.344235 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:13:01.347212 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:13:01.351394 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:13:01.357540 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:13:01.360739 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:13:01.364451 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 11:13:01.371297 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
815 11:13:01.374429 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
816 11:13:01.377668 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
817 11:13:01.384552 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:13:01.387687 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:13:01.391041 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 11:13:01.394057 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 11:13:01.400714 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 11:13:01.404274 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
823 11:13:01.407518 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
824 11:13:01.414256 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
825 11:13:01.417568 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:13:01.420983 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:13:01.427708 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:13:01.431067 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:13:01.434164 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:13:01.441021 0 11 4 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
831 11:13:01.444437 0 11 8 | B1->B0 | 2c2c 4545 | 1 0 | (0 0) (0 0)
832 11:13:01.447690 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
833 11:13:01.454541 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:13:01.457577 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:13:01.460712 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 11:13:01.467473 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 11:13:01.470601 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 11:13:01.474375 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 11:13:01.480836 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
840 11:13:01.484147 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:13:01.487479 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:13:01.494016 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:13:01.497421 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:13:01.500928 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:13:01.503996 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:13:01.510460 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:13:01.513760 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:13:01.517073 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:13:01.523928 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:13:01.527150 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:13:01.530605 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:13:01.537101 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 11:13:01.540276 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 11:13:01.544005 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
855 11:13:01.550612 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 11:13:01.553881 Total UI for P1: 0, mck2ui 16
857 11:13:01.557211 best dqsien dly found for B0: ( 0, 14, 4)
858 11:13:01.560487 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
859 11:13:01.563713 Total UI for P1: 0, mck2ui 16
860 11:13:01.566963 best dqsien dly found for B1: ( 0, 14, 8)
861 11:13:01.570354 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
862 11:13:01.573502 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
863 11:13:01.573954
864 11:13:01.577131 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
865 11:13:01.580587 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
866 11:13:01.583617 [Gating] SW calibration Done
867 11:13:01.584053 ==
868 11:13:01.586920 Dram Type= 6, Freq= 0, CH_0, rank 0
869 11:13:01.590096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
870 11:13:01.593664 ==
871 11:13:01.594094 RX Vref Scan: 0
872 11:13:01.594438
873 11:13:01.596726 RX Vref 0 -> 0, step: 1
874 11:13:01.597317
875 11:13:01.600175 RX Delay -130 -> 252, step: 16
876 11:13:01.603440 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
877 11:13:01.606716 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
878 11:13:01.610165 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
879 11:13:01.613541 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
880 11:13:01.620184 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
881 11:13:01.623760 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
882 11:13:01.626823 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
883 11:13:01.630422 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
884 11:13:01.633449 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
885 11:13:01.640296 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
886 11:13:01.643410 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
887 11:13:01.646826 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
888 11:13:01.650129 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
889 11:13:01.656661 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
890 11:13:01.660255 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
891 11:13:01.663532 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
892 11:13:01.663982 ==
893 11:13:01.666599 Dram Type= 6, Freq= 0, CH_0, rank 0
894 11:13:01.669863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
895 11:13:01.670479 ==
896 11:13:01.673148 DQS Delay:
897 11:13:01.673704 DQS0 = 0, DQS1 = 0
898 11:13:01.674251 DQM Delay:
899 11:13:01.676404 DQM0 = 91, DQM1 = 79
900 11:13:01.676996 DQ Delay:
901 11:13:01.680072 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
902 11:13:01.683213 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
903 11:13:01.686482 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
904 11:13:01.689831 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
905 11:13:01.690431
906 11:13:01.690980
907 11:13:01.691518 ==
908 11:13:01.693196 Dram Type= 6, Freq= 0, CH_0, rank 0
909 11:13:01.699645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
910 11:13:01.700193 ==
911 11:13:01.700750
912 11:13:01.701322
913 11:13:01.702930 TX Vref Scan disable
914 11:13:01.703473 == TX Byte 0 ==
915 11:13:01.706460 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 11:13:01.713104 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 11:13:01.713558 == TX Byte 1 ==
918 11:13:01.716374 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
919 11:13:01.722999 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
920 11:13:01.723433 ==
921 11:13:01.726291 Dram Type= 6, Freq= 0, CH_0, rank 0
922 11:13:01.729578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 11:13:01.730013 ==
924 11:13:01.742529 TX Vref=22, minBit 5, minWin=27, winSum=439
925 11:13:01.745585 TX Vref=24, minBit 8, minWin=26, winSum=441
926 11:13:01.749011 TX Vref=26, minBit 5, minWin=27, winSum=447
927 11:13:01.752474 TX Vref=28, minBit 8, minWin=27, winSum=453
928 11:13:01.755797 TX Vref=30, minBit 8, minWin=27, winSum=453
929 11:13:01.762222 TX Vref=32, minBit 5, minWin=28, winSum=454
930 11:13:01.766066 [TxChooseVref] Worse bit 5, Min win 28, Win sum 454, Final Vref 32
931 11:13:01.766513
932 11:13:01.768900 Final TX Range 1 Vref 32
933 11:13:01.769362
934 11:13:01.769703 ==
935 11:13:01.772200 Dram Type= 6, Freq= 0, CH_0, rank 0
936 11:13:01.775784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 11:13:01.776319 ==
938 11:13:01.779026
939 11:13:01.779547
940 11:13:01.779890 TX Vref Scan disable
941 11:13:01.782831 == TX Byte 0 ==
942 11:13:01.785921 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 11:13:01.789054 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 11:13:01.792276 == TX Byte 1 ==
945 11:13:01.795899 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
946 11:13:01.798958 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
947 11:13:01.802419
948 11:13:01.802926 [DATLAT]
949 11:13:01.803299 Freq=800, CH0 RK0
950 11:13:01.803658
951 11:13:01.805868 DATLAT Default: 0xa
952 11:13:01.806320 0, 0xFFFF, sum = 0
953 11:13:01.809247 1, 0xFFFF, sum = 0
954 11:13:01.809687 2, 0xFFFF, sum = 0
955 11:13:01.812460 3, 0xFFFF, sum = 0
956 11:13:01.812974 4, 0xFFFF, sum = 0
957 11:13:01.815649 5, 0xFFFF, sum = 0
958 11:13:01.818792 6, 0xFFFF, sum = 0
959 11:13:01.819230 7, 0xFFFF, sum = 0
960 11:13:01.822229 8, 0xFFFF, sum = 0
961 11:13:01.822678 9, 0x0, sum = 1
962 11:13:01.823020 10, 0x0, sum = 2
963 11:13:01.825541 11, 0x0, sum = 3
964 11:13:01.826028 12, 0x0, sum = 4
965 11:13:01.828729 best_step = 10
966 11:13:01.829188
967 11:13:01.829522 ==
968 11:13:01.832131 Dram Type= 6, Freq= 0, CH_0, rank 0
969 11:13:01.835680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 11:13:01.836213 ==
971 11:13:01.838925 RX Vref Scan: 1
972 11:13:01.839347
973 11:13:01.842072 Set Vref Range= 32 -> 127
974 11:13:01.842620
975 11:13:01.843051 RX Vref 32 -> 127, step: 1
976 11:13:01.843371
977 11:13:01.845463 RX Delay -95 -> 252, step: 8
978 11:13:01.845887
979 11:13:01.848805 Set Vref, RX VrefLevel [Byte0]: 32
980 11:13:01.852244 [Byte1]: 32
981 11:13:01.852672
982 11:13:01.855536 Set Vref, RX VrefLevel [Byte0]: 33
983 11:13:01.858835 [Byte1]: 33
984 11:13:01.863009
985 11:13:01.863430 Set Vref, RX VrefLevel [Byte0]: 34
986 11:13:01.866323 [Byte1]: 34
987 11:13:01.870443
988 11:13:01.870940 Set Vref, RX VrefLevel [Byte0]: 35
989 11:13:01.873367 [Byte1]: 35
990 11:13:01.878368
991 11:13:01.878897 Set Vref, RX VrefLevel [Byte0]: 36
992 11:13:01.881113 [Byte1]: 36
993 11:13:01.885915
994 11:13:01.886408 Set Vref, RX VrefLevel [Byte0]: 37
995 11:13:01.888904 [Byte1]: 37
996 11:13:01.893538
997 11:13:01.894140 Set Vref, RX VrefLevel [Byte0]: 38
998 11:13:01.896671 [Byte1]: 38
999 11:13:01.900821
1000 11:13:01.901245 Set Vref, RX VrefLevel [Byte0]: 39
1001 11:13:01.904618 [Byte1]: 39
1002 11:13:01.908472
1003 11:13:01.908935 Set Vref, RX VrefLevel [Byte0]: 40
1004 11:13:01.912057 [Byte1]: 40
1005 11:13:01.916199
1006 11:13:01.916626 Set Vref, RX VrefLevel [Byte0]: 41
1007 11:13:01.920135 [Byte1]: 41
1008 11:13:01.923877
1009 11:13:01.924340 Set Vref, RX VrefLevel [Byte0]: 42
1010 11:13:01.927578 [Byte1]: 42
1011 11:13:01.931379
1012 11:13:01.931817 Set Vref, RX VrefLevel [Byte0]: 43
1013 11:13:01.934582 [Byte1]: 43
1014 11:13:01.939024
1015 11:13:01.939446 Set Vref, RX VrefLevel [Byte0]: 44
1016 11:13:01.942581 [Byte1]: 44
1017 11:13:01.946303
1018 11:13:01.946736 Set Vref, RX VrefLevel [Byte0]: 45
1019 11:13:01.949713 [Byte1]: 45
1020 11:13:01.953921
1021 11:13:01.954362 Set Vref, RX VrefLevel [Byte0]: 46
1022 11:13:01.957217 [Byte1]: 46
1023 11:13:01.961399
1024 11:13:01.961832 Set Vref, RX VrefLevel [Byte0]: 47
1025 11:13:01.964821 [Byte1]: 47
1026 11:13:01.969135
1027 11:13:01.969660 Set Vref, RX VrefLevel [Byte0]: 48
1028 11:13:01.975790 [Byte1]: 48
1029 11:13:01.976221
1030 11:13:01.978785 Set Vref, RX VrefLevel [Byte0]: 49
1031 11:13:01.982764 [Byte1]: 49
1032 11:13:01.983348
1033 11:13:01.985812 Set Vref, RX VrefLevel [Byte0]: 50
1034 11:13:01.989156 [Byte1]: 50
1035 11:13:01.989634
1036 11:13:01.992571 Set Vref, RX VrefLevel [Byte0]: 51
1037 11:13:01.995490 [Byte1]: 51
1038 11:13:01.999417
1039 11:13:01.999836 Set Vref, RX VrefLevel [Byte0]: 52
1040 11:13:02.002764 [Byte1]: 52
1041 11:13:02.006993
1042 11:13:02.007413 Set Vref, RX VrefLevel [Byte0]: 53
1043 11:13:02.010352 [Byte1]: 53
1044 11:13:02.014902
1045 11:13:02.015329 Set Vref, RX VrefLevel [Byte0]: 54
1046 11:13:02.018165 [Byte1]: 54
1047 11:13:02.022349
1048 11:13:02.022781 Set Vref, RX VrefLevel [Byte0]: 55
1049 11:13:02.025544 [Byte1]: 55
1050 11:13:02.029920
1051 11:13:02.030343 Set Vref, RX VrefLevel [Byte0]: 56
1052 11:13:02.033122 [Byte1]: 56
1053 11:13:02.037626
1054 11:13:02.038048 Set Vref, RX VrefLevel [Byte0]: 57
1055 11:13:02.041060 [Byte1]: 57
1056 11:13:02.045218
1057 11:13:02.045641 Set Vref, RX VrefLevel [Byte0]: 58
1058 11:13:02.048173 [Byte1]: 58
1059 11:13:02.052565
1060 11:13:02.053013 Set Vref, RX VrefLevel [Byte0]: 59
1061 11:13:02.056021 [Byte1]: 59
1062 11:13:02.060345
1063 11:13:02.060954 Set Vref, RX VrefLevel [Byte0]: 60
1064 11:13:02.063595 [Byte1]: 60
1065 11:13:02.067938
1066 11:13:02.068357 Set Vref, RX VrefLevel [Byte0]: 61
1067 11:13:02.074322 [Byte1]: 61
1068 11:13:02.074747
1069 11:13:02.077354 Set Vref, RX VrefLevel [Byte0]: 62
1070 11:13:02.081091 [Byte1]: 62
1071 11:13:02.081662
1072 11:13:02.084217 Set Vref, RX VrefLevel [Byte0]: 63
1073 11:13:02.087555 [Byte1]: 63
1074 11:13:02.088153
1075 11:13:02.090797 Set Vref, RX VrefLevel [Byte0]: 64
1076 11:13:02.094182 [Byte1]: 64
1077 11:13:02.098203
1078 11:13:02.098625 Set Vref, RX VrefLevel [Byte0]: 65
1079 11:13:02.101302 [Byte1]: 65
1080 11:13:02.106524
1081 11:13:02.107074 Set Vref, RX VrefLevel [Byte0]: 66
1082 11:13:02.109374 [Byte1]: 66
1083 11:13:02.113760
1084 11:13:02.114299 Set Vref, RX VrefLevel [Byte0]: 67
1085 11:13:02.116889 [Byte1]: 67
1086 11:13:02.121111
1087 11:13:02.121563 Set Vref, RX VrefLevel [Byte0]: 68
1088 11:13:02.124511 [Byte1]: 68
1089 11:13:02.128866
1090 11:13:02.129358 Set Vref, RX VrefLevel [Byte0]: 69
1091 11:13:02.132123 [Byte1]: 69
1092 11:13:02.136817
1093 11:13:02.137367 Set Vref, RX VrefLevel [Byte0]: 70
1094 11:13:02.139757 [Byte1]: 70
1095 11:13:02.143812
1096 11:13:02.144237 Set Vref, RX VrefLevel [Byte0]: 71
1097 11:13:02.147205 [Byte1]: 71
1098 11:13:02.151848
1099 11:13:02.152415 Set Vref, RX VrefLevel [Byte0]: 72
1100 11:13:02.154935 [Byte1]: 72
1101 11:13:02.158921
1102 11:13:02.159451 Set Vref, RX VrefLevel [Byte0]: 73
1103 11:13:02.162486 [Byte1]: 73
1104 11:13:02.166526
1105 11:13:02.167181 Set Vref, RX VrefLevel [Byte0]: 74
1106 11:13:02.169923 [Byte1]: 74
1107 11:13:02.174117
1108 11:13:02.174552 Set Vref, RX VrefLevel [Byte0]: 75
1109 11:13:02.177446 [Byte1]: 75
1110 11:13:02.182025
1111 11:13:02.182457 Set Vref, RX VrefLevel [Byte0]: 76
1112 11:13:02.185219 [Byte1]: 76
1113 11:13:02.189794
1114 11:13:02.190230 Set Vref, RX VrefLevel [Byte0]: 77
1115 11:13:02.192545 [Byte1]: 77
1116 11:13:02.197306
1117 11:13:02.197725 Set Vref, RX VrefLevel [Byte0]: 78
1118 11:13:02.200404 [Byte1]: 78
1119 11:13:02.204850
1120 11:13:02.205373 Set Vref, RX VrefLevel [Byte0]: 79
1121 11:13:02.207807 [Byte1]: 79
1122 11:13:02.212152
1123 11:13:02.212575 Final RX Vref Byte 0 = 61 to rank0
1124 11:13:02.215584 Final RX Vref Byte 1 = 63 to rank0
1125 11:13:02.218818 Final RX Vref Byte 0 = 61 to rank1
1126 11:13:02.222207 Final RX Vref Byte 1 = 63 to rank1==
1127 11:13:02.225397 Dram Type= 6, Freq= 0, CH_0, rank 0
1128 11:13:02.231928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1129 11:13:02.232422 ==
1130 11:13:02.232762 DQS Delay:
1131 11:13:02.233112 DQS0 = 0, DQS1 = 0
1132 11:13:02.235412 DQM Delay:
1133 11:13:02.235832 DQM0 = 93, DQM1 = 83
1134 11:13:02.238723 DQ Delay:
1135 11:13:02.242128 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1136 11:13:02.245257 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1137 11:13:02.248702 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1138 11:13:02.251884 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1139 11:13:02.252323
1140 11:13:02.252655
1141 11:13:02.258755 [DQSOSCAuto] RK0, (LSB)MR18= 0x3732, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
1142 11:13:02.261838 CH0 RK0: MR19=606, MR18=3732
1143 11:13:02.268691 CH0_RK0: MR19=0x606, MR18=0x3732, DQSOSC=395, MR23=63, INC=94, DEC=63
1144 11:13:02.269164
1145 11:13:02.271853 ----->DramcWriteLeveling(PI) begin...
1146 11:13:02.272321 ==
1147 11:13:02.275386 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 11:13:02.278334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 11:13:02.278941 ==
1150 11:13:02.281857 Write leveling (Byte 0): 35 => 35
1151 11:13:02.285177 Write leveling (Byte 1): 29 => 29
1152 11:13:02.288641 DramcWriteLeveling(PI) end<-----
1153 11:13:02.289094
1154 11:13:02.289424 ==
1155 11:13:02.291987 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 11:13:02.295287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 11:13:02.295716 ==
1158 11:13:02.298650 [Gating] SW mode calibration
1159 11:13:02.305255 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1160 11:13:02.311799 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1161 11:13:02.315092 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1162 11:13:02.359149 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1163 11:13:02.359958 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1164 11:13:02.360270 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:13:02.360334 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:13:02.360394 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:13:02.360452 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:13:02.360520 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:13:02.360580 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:13:02.360636 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:13:02.360692 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:13:02.403069 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:13:02.403653 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:13:02.404014 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:13:02.404163 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:13:02.404282 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:13:02.404414 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1178 11:13:02.404540 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1179 11:13:02.404683 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1180 11:13:02.404806 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:13:02.404939 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:13:02.407810 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:13:02.411436 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:13:02.417842 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 11:13:02.421482 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:13:02.424892 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1187 11:13:02.431811 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
1188 11:13:02.434968 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 11:13:02.438161 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 11:13:02.444951 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 11:13:02.447916 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 11:13:02.451579 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 11:13:02.458115 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1194 11:13:02.461414 0 10 4 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (1 0)
1195 11:13:02.464586 0 10 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
1196 11:13:02.468027 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 11:13:02.474836 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 11:13:02.477847 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 11:13:02.481020 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 11:13:02.488022 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 11:13:02.490934 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:13:02.494285 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1203 11:13:02.501737 0 11 8 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
1204 11:13:02.505425 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 11:13:02.509414 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 11:13:02.512429 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 11:13:02.519050 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 11:13:02.522854 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 11:13:02.526290 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 11:13:02.529799 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1211 11:13:02.536282 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1212 11:13:02.539544 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:13:02.543232 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:13:02.549402 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:13:02.552618 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:13:02.556214 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:13:02.562773 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:13:02.566361 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:13:02.569391 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:13:02.576254 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:13:02.579495 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 11:13:02.582651 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 11:13:02.589021 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 11:13:02.592547 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 11:13:02.596009 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 11:13:02.602607 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 11:13:02.605915 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1228 11:13:02.609071 Total UI for P1: 0, mck2ui 16
1229 11:13:02.612189 best dqsien dly found for B0: ( 0, 14, 6)
1230 11:13:02.615452 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 11:13:02.618669 Total UI for P1: 0, mck2ui 16
1232 11:13:02.622257 best dqsien dly found for B1: ( 0, 14, 8)
1233 11:13:02.625075 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1234 11:13:02.628885 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1235 11:13:02.628967
1236 11:13:02.635083 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1237 11:13:02.638699 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1238 11:13:02.638793 [Gating] SW calibration Done
1239 11:13:02.641975 ==
1240 11:13:02.645178 Dram Type= 6, Freq= 0, CH_0, rank 1
1241 11:13:02.648600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1242 11:13:02.648711 ==
1243 11:13:02.648811 RX Vref Scan: 0
1244 11:13:02.648896
1245 11:13:02.651519 RX Vref 0 -> 0, step: 1
1246 11:13:02.651640
1247 11:13:02.654884 RX Delay -130 -> 252, step: 16
1248 11:13:02.658367 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1249 11:13:02.661700 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1250 11:13:02.668498 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1251 11:13:02.671335 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1252 11:13:02.674818 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1253 11:13:02.678064 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1254 11:13:02.681466 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1255 11:13:02.688067 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1256 11:13:02.691641 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1257 11:13:02.694910 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1258 11:13:02.698275 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1259 11:13:02.701311 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1260 11:13:02.707740 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1261 11:13:02.711512 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1262 11:13:02.714790 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1263 11:13:02.717770 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1264 11:13:02.717904 ==
1265 11:13:02.721354 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 11:13:02.727695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 11:13:02.727780 ==
1268 11:13:02.727846 DQS Delay:
1269 11:13:02.730965 DQS0 = 0, DQS1 = 0
1270 11:13:02.731064 DQM Delay:
1271 11:13:02.731144 DQM0 = 89, DQM1 = 81
1272 11:13:02.734346 DQ Delay:
1273 11:13:02.737790 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1274 11:13:02.741091 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1275 11:13:02.744534 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1276 11:13:02.747842 DQ12 =77, DQ13 =93, DQ14 =93, DQ15 =93
1277 11:13:02.747950
1278 11:13:02.748042
1279 11:13:02.748131 ==
1280 11:13:02.750858 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 11:13:02.754742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 11:13:02.754822 ==
1283 11:13:02.754887
1284 11:13:02.754948
1285 11:13:02.757709 TX Vref Scan disable
1286 11:13:02.761138 == TX Byte 0 ==
1287 11:13:02.764669 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1288 11:13:02.768087 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1289 11:13:02.771327 == TX Byte 1 ==
1290 11:13:02.774432 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1291 11:13:02.777774 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1292 11:13:02.778329 ==
1293 11:13:02.781172 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 11:13:02.784279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 11:13:02.787659 ==
1296 11:13:02.799565 TX Vref=22, minBit 1, minWin=27, winSum=443
1297 11:13:02.803035 TX Vref=24, minBit 1, minWin=27, winSum=448
1298 11:13:02.806331 TX Vref=26, minBit 8, minWin=27, winSum=452
1299 11:13:02.809764 TX Vref=28, minBit 10, minWin=27, winSum=453
1300 11:13:02.813177 TX Vref=30, minBit 4, minWin=28, winSum=458
1301 11:13:02.816561 TX Vref=32, minBit 8, minWin=27, winSum=457
1302 11:13:02.823107 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 30
1303 11:13:02.823524
1304 11:13:02.826445 Final TX Range 1 Vref 30
1305 11:13:02.826859
1306 11:13:02.827182 ==
1307 11:13:02.829624 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 11:13:02.832739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 11:13:02.833102 ==
1310 11:13:02.835979
1311 11:13:02.836270
1312 11:13:02.836500 TX Vref Scan disable
1313 11:13:02.839772 == TX Byte 0 ==
1314 11:13:02.843293 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1315 11:13:02.849754 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1316 11:13:02.850055 == TX Byte 1 ==
1317 11:13:02.853082 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1318 11:13:02.860155 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1319 11:13:02.860555
1320 11:13:02.860809 [DATLAT]
1321 11:13:02.861032 Freq=800, CH0 RK1
1322 11:13:02.861241
1323 11:13:02.863266 DATLAT Default: 0xa
1324 11:13:02.863557 0, 0xFFFF, sum = 0
1325 11:13:02.866992 1, 0xFFFF, sum = 0
1326 11:13:02.867412 2, 0xFFFF, sum = 0
1327 11:13:02.870046 3, 0xFFFF, sum = 0
1328 11:13:02.870433 4, 0xFFFF, sum = 0
1329 11:13:02.873419 5, 0xFFFF, sum = 0
1330 11:13:02.873805 6, 0xFFFF, sum = 0
1331 11:13:02.876696 7, 0xFFFF, sum = 0
1332 11:13:02.880053 8, 0xFFFF, sum = 0
1333 11:13:02.880472 9, 0x0, sum = 1
1334 11:13:02.880853 10, 0x0, sum = 2
1335 11:13:02.883310 11, 0x0, sum = 3
1336 11:13:02.883725 12, 0x0, sum = 4
1337 11:13:02.886881 best_step = 10
1338 11:13:02.887290
1339 11:13:02.887610 ==
1340 11:13:02.890127 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 11:13:02.893353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 11:13:02.893435 ==
1343 11:13:02.896268 RX Vref Scan: 0
1344 11:13:02.896348
1345 11:13:02.896411 RX Vref 0 -> 0, step: 1
1346 11:13:02.896469
1347 11:13:02.899379 RX Delay -79 -> 252, step: 8
1348 11:13:02.905997 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1349 11:13:02.909566 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1350 11:13:02.912622 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1351 11:13:02.916024 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1352 11:13:02.919571 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1353 11:13:02.926189 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1354 11:13:02.929388 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1355 11:13:02.932589 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1356 11:13:02.935843 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1357 11:13:02.939422 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1358 11:13:02.946087 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1359 11:13:02.949447 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1360 11:13:02.952625 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1361 11:13:02.956390 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1362 11:13:02.962685 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1363 11:13:02.966004 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1364 11:13:02.966293 ==
1365 11:13:02.969750 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 11:13:02.972690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 11:13:02.973149 ==
1368 11:13:02.976405 DQS Delay:
1369 11:13:02.976965 DQS0 = 0, DQS1 = 0
1370 11:13:02.977299 DQM Delay:
1371 11:13:02.979402 DQM0 = 91, DQM1 = 81
1372 11:13:02.979815 DQ Delay:
1373 11:13:02.982731 DQ0 =88, DQ1 =92, DQ2 =92, DQ3 =84
1374 11:13:02.986052 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1375 11:13:02.989177 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1376 11:13:02.992641 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1377 11:13:02.993211
1378 11:13:02.993547
1379 11:13:03.002747 [DQSOSCAuto] RK1, (LSB)MR18= 0x431e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1380 11:13:03.003168 CH0 RK1: MR19=606, MR18=431E
1381 11:13:03.009301 CH0_RK1: MR19=0x606, MR18=0x431E, DQSOSC=393, MR23=63, INC=95, DEC=63
1382 11:13:03.012430 [RxdqsGatingPostProcess] freq 800
1383 11:13:03.019055 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1384 11:13:03.022458 Pre-setting of DQS Precalculation
1385 11:13:03.025729 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1386 11:13:03.026142 ==
1387 11:13:03.029376 Dram Type= 6, Freq= 0, CH_1, rank 0
1388 11:13:03.035856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 11:13:03.036275 ==
1390 11:13:03.038954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1391 11:13:03.045607 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1392 11:13:03.055106 [CA 0] Center 36 (6~67) winsize 62
1393 11:13:03.058524 [CA 1] Center 37 (6~68) winsize 63
1394 11:13:03.061660 [CA 2] Center 35 (5~65) winsize 61
1395 11:13:03.064971 [CA 3] Center 34 (4~65) winsize 62
1396 11:13:03.068338 [CA 4] Center 34 (4~65) winsize 62
1397 11:13:03.071598 [CA 5] Center 34 (3~65) winsize 63
1398 11:13:03.072107
1399 11:13:03.074595 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1400 11:13:03.075032
1401 11:13:03.078418 [CATrainingPosCal] consider 1 rank data
1402 11:13:03.081428 u2DelayCellTimex100 = 270/100 ps
1403 11:13:03.084619 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1404 11:13:03.091197 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1405 11:13:03.094065 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1406 11:13:03.097355 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1407 11:13:03.100628 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1408 11:13:03.103958 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1409 11:13:03.104040
1410 11:13:03.107672 CA PerBit enable=1, Macro0, CA PI delay=34
1411 11:13:03.107757
1412 11:13:03.110947 [CBTSetCACLKResult] CA Dly = 34
1413 11:13:03.111031 CS Dly: 4 (0~35)
1414 11:13:03.113950 ==
1415 11:13:03.117434 Dram Type= 6, Freq= 0, CH_1, rank 1
1416 11:13:03.120611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 11:13:03.120743 ==
1418 11:13:03.124201 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1419 11:13:03.131083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1420 11:13:03.140873 [CA 0] Center 37 (7~67) winsize 61
1421 11:13:03.144401 [CA 1] Center 37 (7~68) winsize 62
1422 11:13:03.147682 [CA 2] Center 35 (5~66) winsize 62
1423 11:13:03.150967 [CA 3] Center 34 (4~65) winsize 62
1424 11:13:03.154271 [CA 4] Center 35 (5~65) winsize 61
1425 11:13:03.157751 [CA 5] Center 34 (4~65) winsize 62
1426 11:13:03.158196
1427 11:13:03.161703 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1428 11:13:03.162248
1429 11:13:03.164473 [CATrainingPosCal] consider 2 rank data
1430 11:13:03.167852 u2DelayCellTimex100 = 270/100 ps
1431 11:13:03.171480 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1432 11:13:03.175179 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
1433 11:13:03.179016 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1434 11:13:03.182645 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 11:13:03.186475 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1436 11:13:03.190259 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1437 11:13:03.190354
1438 11:13:03.194127 CA PerBit enable=1, Macro0, CA PI delay=34
1439 11:13:03.194211
1440 11:13:03.197555 [CBTSetCACLKResult] CA Dly = 34
1441 11:13:03.197638 CS Dly: 5 (0~37)
1442 11:13:03.197731
1443 11:13:03.200986 ----->DramcWriteLeveling(PI) begin...
1444 11:13:03.204216 ==
1445 11:13:03.204299 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 11:13:03.210689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 11:13:03.210773 ==
1448 11:13:03.213896 Write leveling (Byte 0): 27 => 27
1449 11:13:03.217646 Write leveling (Byte 1): 27 => 27
1450 11:13:03.220706 DramcWriteLeveling(PI) end<-----
1451 11:13:03.220849
1452 11:13:03.220944 ==
1453 11:13:03.224243 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 11:13:03.227515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 11:13:03.227599 ==
1456 11:13:03.230945 [Gating] SW mode calibration
1457 11:13:03.237219 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1458 11:13:03.240591 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1459 11:13:03.247290 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1460 11:13:03.250665 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:13:03.253974 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:13:03.260816 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:13:03.264196 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:13:03.267349 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:13:03.273980 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:13:03.277251 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:13:03.280471 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:13:03.287093 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:13:03.290404 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:13:03.293542 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:13:03.300454 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:13:03.303623 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:13:03.306973 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:13:03.313795 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:13:03.317187 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1476 11:13:03.320066 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1477 11:13:03.327039 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:13:03.330673 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:13:03.333848 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 11:13:03.340582 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:13:03.343791 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:13:03.347308 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 11:13:03.353926 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:13:03.357392 0 9 4 | B1->B0 | 2424 2727 | 0 1 | (1 1) (1 1)
1485 11:13:03.360826 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1486 11:13:03.363924 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 11:13:03.370652 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 11:13:03.373935 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 11:13:03.377284 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 11:13:03.383687 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 11:13:03.387122 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1492 11:13:03.390156 0 10 4 | B1->B0 | 3030 2f2f | 0 0 | (1 1) (1 1)
1493 11:13:03.396840 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1494 11:13:03.400218 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 11:13:03.403834 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 11:13:03.410871 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:13:03.413676 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:13:03.416988 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 11:13:03.423409 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 11:13:03.426497 0 11 4 | B1->B0 | 2d2d 3737 | 1 0 | (0 0) (0 0)
1501 11:13:03.430198 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1502 11:13:03.436519 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 11:13:03.439875 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 11:13:03.443249 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 11:13:03.450011 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 11:13:03.453186 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 11:13:03.456401 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1508 11:13:03.463458 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1509 11:13:03.466644 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:13:03.469928 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:13:03.476610 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:13:03.479694 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:13:03.483044 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:13:03.489646 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:13:03.493237 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:13:03.496368 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:13:03.503378 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 11:13:03.506478 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 11:13:03.509830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 11:13:03.516447 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 11:13:03.519763 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 11:13:03.522940 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 11:13:03.529603 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1524 11:13:03.532799 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 11:13:03.536578 Total UI for P1: 0, mck2ui 16
1526 11:13:03.540054 best dqsien dly found for B0: ( 0, 14, 0)
1527 11:13:03.543097 Total UI for P1: 0, mck2ui 16
1528 11:13:03.546907 best dqsien dly found for B1: ( 0, 14, 2)
1529 11:13:03.549610 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1530 11:13:03.553287 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1531 11:13:03.553757
1532 11:13:03.556282 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1533 11:13:03.559605 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1534 11:13:03.563089 [Gating] SW calibration Done
1535 11:13:03.563667 ==
1536 11:13:03.566261 Dram Type= 6, Freq= 0, CH_1, rank 0
1537 11:13:03.569683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1538 11:13:03.570137 ==
1539 11:13:03.573150 RX Vref Scan: 0
1540 11:13:03.573650
1541 11:13:03.573992 RX Vref 0 -> 0, step: 1
1542 11:13:03.576380
1543 11:13:03.576819 RX Delay -130 -> 252, step: 16
1544 11:13:03.582875 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1545 11:13:03.586236 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1546 11:13:03.589439 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1547 11:13:03.592724 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1548 11:13:03.596271 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1549 11:13:03.602571 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1550 11:13:03.605899 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1551 11:13:03.609390 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1552 11:13:03.612651 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1553 11:13:03.616078 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1554 11:13:03.622421 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1555 11:13:03.625833 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1556 11:13:03.629051 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1557 11:13:03.632732 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1558 11:13:03.635657 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1559 11:13:03.642684 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1560 11:13:03.643205 ==
1561 11:13:03.646186 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 11:13:03.649136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 11:13:03.649571 ==
1564 11:13:03.650004 DQS Delay:
1565 11:13:03.652619 DQS0 = 0, DQS1 = 0
1566 11:13:03.653125 DQM Delay:
1567 11:13:03.655935 DQM0 = 92, DQM1 = 85
1568 11:13:03.656469 DQ Delay:
1569 11:13:03.659081 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1570 11:13:03.662433 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =93
1571 11:13:03.665645 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1572 11:13:03.669096 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1573 11:13:03.669522
1574 11:13:03.669894
1575 11:13:03.670210 ==
1576 11:13:03.672202 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 11:13:03.675629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 11:13:03.679357 ==
1579 11:13:03.679876
1580 11:13:03.680209
1581 11:13:03.680517 TX Vref Scan disable
1582 11:13:03.682308 == TX Byte 0 ==
1583 11:13:03.686038 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1584 11:13:03.689208 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1585 11:13:03.692576 == TX Byte 1 ==
1586 11:13:03.695867 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1587 11:13:03.698707 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1588 11:13:03.702401 ==
1589 11:13:03.702821 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 11:13:03.708704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 11:13:03.709164 ==
1592 11:13:03.721130 TX Vref=22, minBit 11, minWin=26, winSum=444
1593 11:13:03.724130 TX Vref=24, minBit 8, minWin=27, winSum=450
1594 11:13:03.727622 TX Vref=26, minBit 8, minWin=27, winSum=455
1595 11:13:03.731247 TX Vref=28, minBit 12, minWin=27, winSum=456
1596 11:13:03.734167 TX Vref=30, minBit 8, minWin=28, winSum=458
1597 11:13:03.741476 TX Vref=32, minBit 8, minWin=27, winSum=453
1598 11:13:03.745144 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
1599 11:13:03.745661
1600 11:13:03.748515 Final TX Range 1 Vref 30
1601 11:13:03.749079
1602 11:13:03.749430 ==
1603 11:13:03.751475 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 11:13:03.755531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 11:13:03.756121 ==
1606 11:13:03.756593
1607 11:13:03.756976
1608 11:13:03.758217 TX Vref Scan disable
1609 11:13:03.761591 == TX Byte 0 ==
1610 11:13:03.764892 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1611 11:13:03.768607 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1612 11:13:03.771536 == TX Byte 1 ==
1613 11:13:03.775127 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1614 11:13:03.778288 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1615 11:13:03.778723
1616 11:13:03.781904 [DATLAT]
1617 11:13:03.782344 Freq=800, CH1 RK0
1618 11:13:03.782688
1619 11:13:03.785013 DATLAT Default: 0xa
1620 11:13:03.785436 0, 0xFFFF, sum = 0
1621 11:13:03.788369 1, 0xFFFF, sum = 0
1622 11:13:03.789019 2, 0xFFFF, sum = 0
1623 11:13:03.791542 3, 0xFFFF, sum = 0
1624 11:13:03.792080 4, 0xFFFF, sum = 0
1625 11:13:03.794976 5, 0xFFFF, sum = 0
1626 11:13:03.795560 6, 0xFFFF, sum = 0
1627 11:13:03.797962 7, 0xFFFF, sum = 0
1628 11:13:03.798555 8, 0xFFFF, sum = 0
1629 11:13:03.801504 9, 0x0, sum = 1
1630 11:13:03.802007 10, 0x0, sum = 2
1631 11:13:03.804921 11, 0x0, sum = 3
1632 11:13:03.805347 12, 0x0, sum = 4
1633 11:13:03.807836 best_step = 10
1634 11:13:03.808345
1635 11:13:03.808861 ==
1636 11:13:03.811219 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 11:13:03.814957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 11:13:03.815385 ==
1639 11:13:03.818275 RX Vref Scan: 1
1640 11:13:03.818733
1641 11:13:03.819251 Set Vref Range= 32 -> 127
1642 11:13:03.819730
1643 11:13:03.821555 RX Vref 32 -> 127, step: 1
1644 11:13:03.822158
1645 11:13:03.824814 RX Delay -95 -> 252, step: 8
1646 11:13:03.825241
1647 11:13:03.827969 Set Vref, RX VrefLevel [Byte0]: 32
1648 11:13:03.831327 [Byte1]: 32
1649 11:13:03.831753
1650 11:13:03.834788 Set Vref, RX VrefLevel [Byte0]: 33
1651 11:13:03.839496 [Byte1]: 33
1652 11:13:03.841396
1653 11:13:03.841821 Set Vref, RX VrefLevel [Byte0]: 34
1654 11:13:03.844685 [Byte1]: 34
1655 11:13:03.848854
1656 11:13:03.849360 Set Vref, RX VrefLevel [Byte0]: 35
1657 11:13:03.852003 [Byte1]: 35
1658 11:13:03.856648
1659 11:13:03.857181 Set Vref, RX VrefLevel [Byte0]: 36
1660 11:13:03.859787 [Byte1]: 36
1661 11:13:03.864290
1662 11:13:03.864875 Set Vref, RX VrefLevel [Byte0]: 37
1663 11:13:03.867104 [Byte1]: 37
1664 11:13:03.871451
1665 11:13:03.871878 Set Vref, RX VrefLevel [Byte0]: 38
1666 11:13:03.875038 [Byte1]: 38
1667 11:13:03.879772
1668 11:13:03.880319 Set Vref, RX VrefLevel [Byte0]: 39
1669 11:13:03.882436 [Byte1]: 39
1670 11:13:03.886848
1671 11:13:03.887271 Set Vref, RX VrefLevel [Byte0]: 40
1672 11:13:03.890144 [Byte1]: 40
1673 11:13:03.894542
1674 11:13:03.894967 Set Vref, RX VrefLevel [Byte0]: 41
1675 11:13:03.900663 [Byte1]: 41
1676 11:13:03.901170
1677 11:13:03.904475 Set Vref, RX VrefLevel [Byte0]: 42
1678 11:13:03.907491 [Byte1]: 42
1679 11:13:03.907949
1680 11:13:03.910698 Set Vref, RX VrefLevel [Byte0]: 43
1681 11:13:03.914062 [Byte1]: 43
1682 11:13:03.914489
1683 11:13:03.917410 Set Vref, RX VrefLevel [Byte0]: 44
1684 11:13:03.920732 [Byte1]: 44
1685 11:13:03.924714
1686 11:13:03.925190 Set Vref, RX VrefLevel [Byte0]: 45
1687 11:13:03.928015 [Byte1]: 45
1688 11:13:03.932356
1689 11:13:03.932801 Set Vref, RX VrefLevel [Byte0]: 46
1690 11:13:03.935660 [Byte1]: 46
1691 11:13:03.940154
1692 11:13:03.940597 Set Vref, RX VrefLevel [Byte0]: 47
1693 11:13:03.943751 [Byte1]: 47
1694 11:13:03.947934
1695 11:13:03.948456 Set Vref, RX VrefLevel [Byte0]: 48
1696 11:13:03.951094 [Byte1]: 48
1697 11:13:03.955045
1698 11:13:03.955553 Set Vref, RX VrefLevel [Byte0]: 49
1699 11:13:03.958643 [Byte1]: 49
1700 11:13:03.962779
1701 11:13:03.963322 Set Vref, RX VrefLevel [Byte0]: 50
1702 11:13:03.966205 [Byte1]: 50
1703 11:13:03.970202
1704 11:13:03.970630 Set Vref, RX VrefLevel [Byte0]: 51
1705 11:13:03.973766 [Byte1]: 51
1706 11:13:03.977825
1707 11:13:03.978242 Set Vref, RX VrefLevel [Byte0]: 52
1708 11:13:03.981265 [Byte1]: 52
1709 11:13:03.985800
1710 11:13:03.986214 Set Vref, RX VrefLevel [Byte0]: 53
1711 11:13:03.988734 [Byte1]: 53
1712 11:13:03.993139
1713 11:13:03.993555 Set Vref, RX VrefLevel [Byte0]: 54
1714 11:13:03.996355 [Byte1]: 54
1715 11:13:04.001043
1716 11:13:04.001456 Set Vref, RX VrefLevel [Byte0]: 55
1717 11:13:04.003811 [Byte1]: 55
1718 11:13:04.008760
1719 11:13:04.009204 Set Vref, RX VrefLevel [Byte0]: 56
1720 11:13:04.011960 [Byte1]: 56
1721 11:13:04.015980
1722 11:13:04.016399 Set Vref, RX VrefLevel [Byte0]: 57
1723 11:13:04.019413 [Byte1]: 57
1724 11:13:04.023549
1725 11:13:04.024083 Set Vref, RX VrefLevel [Byte0]: 58
1726 11:13:04.026968 [Byte1]: 58
1727 11:13:04.030874
1728 11:13:04.031277 Set Vref, RX VrefLevel [Byte0]: 59
1729 11:13:04.034082 [Byte1]: 59
1730 11:13:04.038776
1731 11:13:04.039192 Set Vref, RX VrefLevel [Byte0]: 60
1732 11:13:04.042075 [Byte1]: 60
1733 11:13:04.046187
1734 11:13:04.046732 Set Vref, RX VrefLevel [Byte0]: 61
1735 11:13:04.049680 [Byte1]: 61
1736 11:13:04.053887
1737 11:13:04.054328 Set Vref, RX VrefLevel [Byte0]: 62
1738 11:13:04.057156 [Byte1]: 62
1739 11:13:04.061339
1740 11:13:04.061754 Set Vref, RX VrefLevel [Byte0]: 63
1741 11:13:04.064729 [Byte1]: 63
1742 11:13:04.069245
1743 11:13:04.069730 Set Vref, RX VrefLevel [Byte0]: 64
1744 11:13:04.072636 [Byte1]: 64
1745 11:13:04.076552
1746 11:13:04.077176 Set Vref, RX VrefLevel [Byte0]: 65
1747 11:13:04.079746 [Byte1]: 65
1748 11:13:04.084265
1749 11:13:04.084817 Set Vref, RX VrefLevel [Byte0]: 66
1750 11:13:04.087645 [Byte1]: 66
1751 11:13:04.092156
1752 11:13:04.092574 Set Vref, RX VrefLevel [Byte0]: 67
1753 11:13:04.095247 [Byte1]: 67
1754 11:13:04.099429
1755 11:13:04.100013 Set Vref, RX VrefLevel [Byte0]: 68
1756 11:13:04.103014 [Byte1]: 68
1757 11:13:04.107096
1758 11:13:04.107730 Set Vref, RX VrefLevel [Byte0]: 69
1759 11:13:04.110418 [Byte1]: 69
1760 11:13:04.114576
1761 11:13:04.115007 Set Vref, RX VrefLevel [Byte0]: 70
1762 11:13:04.118345 [Byte1]: 70
1763 11:13:04.122522
1764 11:13:04.123071 Set Vref, RX VrefLevel [Byte0]: 71
1765 11:13:04.125377 [Byte1]: 71
1766 11:13:04.129702
1767 11:13:04.133045 Set Vref, RX VrefLevel [Byte0]: 72
1768 11:13:04.136278 [Byte1]: 72
1769 11:13:04.136880
1770 11:13:04.139663 Set Vref, RX VrefLevel [Byte0]: 73
1771 11:13:04.142707 [Byte1]: 73
1772 11:13:04.143272
1773 11:13:04.146156 Set Vref, RX VrefLevel [Byte0]: 74
1774 11:13:04.149781 [Byte1]: 74
1775 11:13:04.150357
1776 11:13:04.153019 Final RX Vref Byte 0 = 52 to rank0
1777 11:13:04.156442 Final RX Vref Byte 1 = 62 to rank0
1778 11:13:04.160062 Final RX Vref Byte 0 = 52 to rank1
1779 11:13:04.162907 Final RX Vref Byte 1 = 62 to rank1==
1780 11:13:04.166306 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 11:13:04.169219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 11:13:04.173024 ==
1783 11:13:04.173618 DQS Delay:
1784 11:13:04.174132 DQS0 = 0, DQS1 = 0
1785 11:13:04.175946 DQM Delay:
1786 11:13:04.176505 DQM0 = 93, DQM1 = 83
1787 11:13:04.179546 DQ Delay:
1788 11:13:04.182685 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1789 11:13:04.186254 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1790 11:13:04.186795 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1791 11:13:04.192832 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1792 11:13:04.193292
1793 11:13:04.193620
1794 11:13:04.199025 [DQSOSCAuto] RK0, (LSB)MR18= 0x324e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1795 11:13:04.202576 CH1 RK0: MR19=606, MR18=324E
1796 11:13:04.208986 CH1_RK0: MR19=0x606, MR18=0x324E, DQSOSC=390, MR23=63, INC=97, DEC=64
1797 11:13:04.209514
1798 11:13:04.212460 ----->DramcWriteLeveling(PI) begin...
1799 11:13:04.213045 ==
1800 11:13:04.215745 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 11:13:04.218915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 11:13:04.219342 ==
1803 11:13:04.222183 Write leveling (Byte 0): 25 => 25
1804 11:13:04.225564 Write leveling (Byte 1): 30 => 30
1805 11:13:04.228970 DramcWriteLeveling(PI) end<-----
1806 11:13:04.229404
1807 11:13:04.229814 ==
1808 11:13:04.232451 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 11:13:04.235700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 11:13:04.236145 ==
1811 11:13:04.238966 [Gating] SW mode calibration
1812 11:13:04.245278 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 11:13:04.252154 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 11:13:04.255438 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1815 11:13:04.262120 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:13:04.265203 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:13:04.268818 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:13:04.275156 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:13:04.278775 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:13:04.282149 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:13:04.285234 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:13:04.291853 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:13:04.294905 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:13:04.298401 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:13:04.305024 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:13:04.308895 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:13:04.311623 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:13:04.318156 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:13:04.321416 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:13:04.324674 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1831 11:13:04.331361 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1832 11:13:04.334889 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:13:04.338225 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:13:04.344804 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:13:04.348154 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:13:04.351554 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:13:04.358078 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:13:04.361335 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:13:04.364629 0 9 4 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
1840 11:13:04.371185 0 9 8 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
1841 11:13:04.374670 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 11:13:04.377806 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 11:13:04.384739 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 11:13:04.388215 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 11:13:04.391552 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 11:13:04.397973 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 11:13:04.401003 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (0 1)
1848 11:13:04.404541 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:13:04.411482 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:13:04.414574 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:13:04.417557 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:13:04.424677 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:13:04.427476 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:13:04.431005 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 11:13:04.437608 0 11 4 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
1856 11:13:04.440835 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1857 11:13:04.444046 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 11:13:04.451053 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 11:13:04.454296 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 11:13:04.457607 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 11:13:04.464058 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 11:13:04.467260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 11:13:04.471178 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1864 11:13:04.477507 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:13:04.480814 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:13:04.484381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:13:04.487554 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:13:04.494036 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:13:04.497571 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:13:04.500577 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:13:04.506795 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:13:04.510187 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:13:04.513387 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:13:04.520580 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:13:04.523341 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 11:13:04.526537 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 11:13:04.533143 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 11:13:04.536563 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 11:13:04.539966 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1880 11:13:04.547194 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 11:13:04.550497 Total UI for P1: 0, mck2ui 16
1882 11:13:04.553854 best dqsien dly found for B0: ( 0, 14, 6)
1883 11:13:04.557170 Total UI for P1: 0, mck2ui 16
1884 11:13:04.560498 best dqsien dly found for B1: ( 0, 14, 4)
1885 11:13:04.563665 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1886 11:13:04.567055 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1887 11:13:04.567481
1888 11:13:04.570378 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1889 11:13:04.573717 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1890 11:13:04.577058 [Gating] SW calibration Done
1891 11:13:04.577486 ==
1892 11:13:04.580574 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 11:13:04.583947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 11:13:04.584470 ==
1895 11:13:04.587544 RX Vref Scan: 0
1896 11:13:04.588064
1897 11:13:04.588404 RX Vref 0 -> 0, step: 1
1898 11:13:04.588724
1899 11:13:04.590492 RX Delay -130 -> 252, step: 16
1900 11:13:04.593314 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1901 11:13:04.600439 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1902 11:13:04.603362 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1903 11:13:04.606857 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1904 11:13:04.610281 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1905 11:13:04.613277 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1906 11:13:04.619569 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1907 11:13:04.623154 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1908 11:13:04.626393 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1909 11:13:04.629844 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1910 11:13:04.633059 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1911 11:13:04.639616 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1912 11:13:04.643156 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1913 11:13:04.646684 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1914 11:13:04.649949 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1915 11:13:04.653136 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1916 11:13:04.656380 ==
1917 11:13:04.659630 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 11:13:04.662812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 11:13:04.662895 ==
1920 11:13:04.662961 DQS Delay:
1921 11:13:04.666582 DQS0 = 0, DQS1 = 0
1922 11:13:04.666657 DQM Delay:
1923 11:13:04.669915 DQM0 = 92, DQM1 = 86
1924 11:13:04.669990 DQ Delay:
1925 11:13:04.673168 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =93
1926 11:13:04.676479 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1927 11:13:04.679876 DQ8 =69, DQ9 =77, DQ10 =93, DQ11 =77
1928 11:13:04.683073 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1929 11:13:04.683148
1930 11:13:04.683210
1931 11:13:04.683269 ==
1932 11:13:04.686300 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 11:13:04.689807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 11:13:04.689897 ==
1935 11:13:04.689965
1936 11:13:04.690026
1937 11:13:04.693000 TX Vref Scan disable
1938 11:13:04.696033 == TX Byte 0 ==
1939 11:13:04.699498 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1940 11:13:04.703145 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1941 11:13:04.706101 == TX Byte 1 ==
1942 11:13:04.709660 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1943 11:13:04.712963 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1944 11:13:04.713039 ==
1945 11:13:04.716043 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 11:13:04.719561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 11:13:04.723183 ==
1948 11:13:04.735129 TX Vref=22, minBit 10, minWin=27, winSum=449
1949 11:13:04.738415 TX Vref=24, minBit 8, minWin=27, winSum=454
1950 11:13:04.741455 TX Vref=26, minBit 8, minWin=28, winSum=457
1951 11:13:04.744933 TX Vref=28, minBit 13, minWin=27, winSum=458
1952 11:13:04.748462 TX Vref=30, minBit 8, minWin=28, winSum=460
1953 11:13:04.754649 TX Vref=32, minBit 8, minWin=28, winSum=460
1954 11:13:04.758010 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1955 11:13:04.758093
1956 11:13:04.761412 Final TX Range 1 Vref 30
1957 11:13:04.761495
1958 11:13:04.761560 ==
1959 11:13:04.764496 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 11:13:04.767773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 11:13:04.771205 ==
1962 11:13:04.771304
1963 11:13:04.771378
1964 11:13:04.771447 TX Vref Scan disable
1965 11:13:04.774991 == TX Byte 0 ==
1966 11:13:04.778369 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1967 11:13:04.785383 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1968 11:13:04.785586 == TX Byte 1 ==
1969 11:13:04.788686 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1970 11:13:04.794879 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1971 11:13:04.795058
1972 11:13:04.795190 [DATLAT]
1973 11:13:04.795303 Freq=800, CH1 RK1
1974 11:13:04.795412
1975 11:13:04.798290 DATLAT Default: 0xa
1976 11:13:04.798442 0, 0xFFFF, sum = 0
1977 11:13:04.801504 1, 0xFFFF, sum = 0
1978 11:13:04.801681 2, 0xFFFF, sum = 0
1979 11:13:04.805065 3, 0xFFFF, sum = 0
1980 11:13:04.807983 4, 0xFFFF, sum = 0
1981 11:13:04.808097 5, 0xFFFF, sum = 0
1982 11:13:04.811605 6, 0xFFFF, sum = 0
1983 11:13:04.811694 7, 0xFFFF, sum = 0
1984 11:13:04.815233 8, 0xFFFF, sum = 0
1985 11:13:04.815409 9, 0x0, sum = 1
1986 11:13:04.818077 10, 0x0, sum = 2
1987 11:13:04.818232 11, 0x0, sum = 3
1988 11:13:04.818343 12, 0x0, sum = 4
1989 11:13:04.821817 best_step = 10
1990 11:13:04.821997
1991 11:13:04.822087 ==
1992 11:13:04.825103 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 11:13:04.828074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 11:13:04.828265 ==
1995 11:13:04.831795 RX Vref Scan: 0
1996 11:13:04.831998
1997 11:13:04.832110 RX Vref 0 -> 0, step: 1
1998 11:13:04.834942
1999 11:13:04.835140 RX Delay -95 -> 252, step: 8
2000 11:13:04.842274 iDelay=209, Bit 0, Center 96 (1 ~ 192) 192
2001 11:13:04.845447 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2002 11:13:04.849025 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2003 11:13:04.852221 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2004 11:13:04.855102 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2005 11:13:04.862342 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2006 11:13:04.865478 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2007 11:13:04.868634 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2008 11:13:04.871864 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2009 11:13:04.875103 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2010 11:13:04.882155 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2011 11:13:04.885426 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2012 11:13:04.888690 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2013 11:13:04.891947 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2014 11:13:04.895134 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2015 11:13:04.901824 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2016 11:13:04.902248 ==
2017 11:13:04.905408 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 11:13:04.908541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 11:13:04.908983 ==
2020 11:13:04.909318 DQS Delay:
2021 11:13:04.911824 DQS0 = 0, DQS1 = 0
2022 11:13:04.912245 DQM Delay:
2023 11:13:04.915341 DQM0 = 91, DQM1 = 84
2024 11:13:04.915762 DQ Delay:
2025 11:13:04.918266 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2026 11:13:04.921620 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2027 11:13:04.925247 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2028 11:13:04.928173 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =92
2029 11:13:04.928597
2030 11:13:04.929003
2031 11:13:04.935355 [DQSOSCAuto] RK1, (LSB)MR18= 0x350a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
2032 11:13:04.938297 CH1 RK1: MR19=606, MR18=350A
2033 11:13:04.944870 CH1_RK1: MR19=0x606, MR18=0x350A, DQSOSC=396, MR23=63, INC=94, DEC=62
2034 11:13:04.948552 [RxdqsGatingPostProcess] freq 800
2035 11:13:04.954879 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 11:13:04.958353 Pre-setting of DQS Precalculation
2037 11:13:04.961431 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 11:13:04.968022 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 11:13:04.974614 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 11:13:04.974697
2041 11:13:04.977922
2042 11:13:04.978011 [Calibration Summary] 1600 Mbps
2043 11:13:04.981511 CH 0, Rank 0
2044 11:13:04.981678 SW Impedance : PASS
2045 11:13:04.984603 DUTY Scan : NO K
2046 11:13:04.988075 ZQ Calibration : PASS
2047 11:13:04.988255 Jitter Meter : NO K
2048 11:13:04.991228 CBT Training : PASS
2049 11:13:04.994463 Write leveling : PASS
2050 11:13:04.994650 RX DQS gating : PASS
2051 11:13:04.997772 RX DQ/DQS(RDDQC) : PASS
2052 11:13:05.001597 TX DQ/DQS : PASS
2053 11:13:05.001778 RX DATLAT : PASS
2054 11:13:05.004621 RX DQ/DQS(Engine): PASS
2055 11:13:05.007787 TX OE : NO K
2056 11:13:05.007978 All Pass.
2057 11:13:05.008131
2058 11:13:05.008254 CH 0, Rank 1
2059 11:13:05.011382 SW Impedance : PASS
2060 11:13:05.014307 DUTY Scan : NO K
2061 11:13:05.014545 ZQ Calibration : PASS
2062 11:13:05.017848 Jitter Meter : NO K
2063 11:13:05.018052 CBT Training : PASS
2064 11:13:05.021148 Write leveling : PASS
2065 11:13:05.024224 RX DQS gating : PASS
2066 11:13:05.024465 RX DQ/DQS(RDDQC) : PASS
2067 11:13:05.027720 TX DQ/DQS : PASS
2068 11:13:05.031369 RX DATLAT : PASS
2069 11:13:05.031671 RX DQ/DQS(Engine): PASS
2070 11:13:05.034556 TX OE : NO K
2071 11:13:05.034942 All Pass.
2072 11:13:05.035247
2073 11:13:05.038154 CH 1, Rank 0
2074 11:13:05.038573 SW Impedance : PASS
2075 11:13:05.041576 DUTY Scan : NO K
2076 11:13:05.044874 ZQ Calibration : PASS
2077 11:13:05.045296 Jitter Meter : NO K
2078 11:13:05.048382 CBT Training : PASS
2079 11:13:05.051485 Write leveling : PASS
2080 11:13:05.051908 RX DQS gating : PASS
2081 11:13:05.054639 RX DQ/DQS(RDDQC) : PASS
2082 11:13:05.058370 TX DQ/DQS : PASS
2083 11:13:05.058889 RX DATLAT : PASS
2084 11:13:05.061642 RX DQ/DQS(Engine): PASS
2085 11:13:05.062169 TX OE : NO K
2086 11:13:05.064859 All Pass.
2087 11:13:05.065374
2088 11:13:05.065705 CH 1, Rank 1
2089 11:13:05.068329 SW Impedance : PASS
2090 11:13:05.068907 DUTY Scan : NO K
2091 11:13:05.071536 ZQ Calibration : PASS
2092 11:13:05.074804 Jitter Meter : NO K
2093 11:13:05.075332 CBT Training : PASS
2094 11:13:05.077721 Write leveling : PASS
2095 11:13:05.081401 RX DQS gating : PASS
2096 11:13:05.081919 RX DQ/DQS(RDDQC) : PASS
2097 11:13:05.084759 TX DQ/DQS : PASS
2098 11:13:05.088365 RX DATLAT : PASS
2099 11:13:05.088916 RX DQ/DQS(Engine): PASS
2100 11:13:05.091231 TX OE : NO K
2101 11:13:05.091640 All Pass.
2102 11:13:05.091958
2103 11:13:05.094670 DramC Write-DBI off
2104 11:13:05.098223 PER_BANK_REFRESH: Hybrid Mode
2105 11:13:05.098748 TX_TRACKING: ON
2106 11:13:05.101185 [GetDramInforAfterCalByMRR] Vendor 6.
2107 11:13:05.104293 [GetDramInforAfterCalByMRR] Revision 606.
2108 11:13:05.108065 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 11:13:05.111074 MR0 0x3b3b
2110 11:13:05.111498 MR8 0x5151
2111 11:13:05.114674 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 11:13:05.115205
2113 11:13:05.115543 MR0 0x3b3b
2114 11:13:05.117605 MR8 0x5151
2115 11:13:05.120904 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 11:13:05.121329
2117 11:13:05.130525 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 11:13:05.134108 [FAST_K] Save calibration result to emmc
2119 11:13:05.137323 [FAST_K] Save calibration result to emmc
2120 11:13:05.137412 dram_init: config_dvfs: 1
2121 11:13:05.144328 dramc_set_vcore_voltage set vcore to 662500
2122 11:13:05.144423 Read voltage for 1200, 2
2123 11:13:05.147310 Vio18 = 0
2124 11:13:05.147413 Vcore = 662500
2125 11:13:05.147495 Vdram = 0
2126 11:13:05.150726 Vddq = 0
2127 11:13:05.150808 Vmddr = 0
2128 11:13:05.153853 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 11:13:05.160873 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 11:13:05.164202 MEM_TYPE=3, freq_sel=15
2131 11:13:05.164284 sv_algorithm_assistance_LP4_1600
2132 11:13:05.170928 ============ PULL DRAM RESETB DOWN ============
2133 11:13:05.174047 ========== PULL DRAM RESETB DOWN end =========
2134 11:13:05.177229 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 11:13:05.180591 ===================================
2136 11:13:05.184239 LPDDR4 DRAM CONFIGURATION
2137 11:13:05.187408 ===================================
2138 11:13:05.190702 EX_ROW_EN[0] = 0x0
2139 11:13:05.190784 EX_ROW_EN[1] = 0x0
2140 11:13:05.194110 LP4Y_EN = 0x0
2141 11:13:05.194193 WORK_FSP = 0x0
2142 11:13:05.197513 WL = 0x4
2143 11:13:05.197596 RL = 0x4
2144 11:13:05.200828 BL = 0x2
2145 11:13:05.200915 RPST = 0x0
2146 11:13:05.204185 RD_PRE = 0x0
2147 11:13:05.204268 WR_PRE = 0x1
2148 11:13:05.207232 WR_PST = 0x0
2149 11:13:05.207339 DBI_WR = 0x0
2150 11:13:05.210441 DBI_RD = 0x0
2151 11:13:05.210523 OTF = 0x1
2152 11:13:05.213909 ===================================
2153 11:13:05.217057 ===================================
2154 11:13:05.220731 ANA top config
2155 11:13:05.223952 ===================================
2156 11:13:05.227016 DLL_ASYNC_EN = 0
2157 11:13:05.227103 ALL_SLAVE_EN = 0
2158 11:13:05.230467 NEW_RANK_MODE = 1
2159 11:13:05.233594 DLL_IDLE_MODE = 1
2160 11:13:05.237056 LP45_APHY_COMB_EN = 1
2161 11:13:05.240586 TX_ODT_DIS = 1
2162 11:13:05.240695 NEW_8X_MODE = 1
2163 11:13:05.243682 ===================================
2164 11:13:05.247534 ===================================
2165 11:13:05.250734 data_rate = 2400
2166 11:13:05.253828 CKR = 1
2167 11:13:05.257616 DQ_P2S_RATIO = 8
2168 11:13:05.260947 ===================================
2169 11:13:05.264295 CA_P2S_RATIO = 8
2170 11:13:05.267285 DQ_CA_OPEN = 0
2171 11:13:05.267764 DQ_SEMI_OPEN = 0
2172 11:13:05.270467 CA_SEMI_OPEN = 0
2173 11:13:05.274056 CA_FULL_RATE = 0
2174 11:13:05.277354 DQ_CKDIV4_EN = 0
2175 11:13:05.280567 CA_CKDIV4_EN = 0
2176 11:13:05.281103 CA_PREDIV_EN = 0
2177 11:13:05.284000 PH8_DLY = 17
2178 11:13:05.287231 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 11:13:05.290409 DQ_AAMCK_DIV = 4
2180 11:13:05.293623 CA_AAMCK_DIV = 4
2181 11:13:05.297199 CA_ADMCK_DIV = 4
2182 11:13:05.297622 DQ_TRACK_CA_EN = 0
2183 11:13:05.300738 CA_PICK = 1200
2184 11:13:05.304199 CA_MCKIO = 1200
2185 11:13:05.307741 MCKIO_SEMI = 0
2186 11:13:05.310969 PLL_FREQ = 2366
2187 11:13:05.313918 DQ_UI_PI_RATIO = 32
2188 11:13:05.317201 CA_UI_PI_RATIO = 0
2189 11:13:05.320254 ===================================
2190 11:13:05.323930 ===================================
2191 11:13:05.324354 memory_type:LPDDR4
2192 11:13:05.326980 GP_NUM : 10
2193 11:13:05.330355 SRAM_EN : 1
2194 11:13:05.330778 MD32_EN : 0
2195 11:13:05.333841 ===================================
2196 11:13:05.336819 [ANA_INIT] >>>>>>>>>>>>>>
2197 11:13:05.340197 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 11:13:05.343899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 11:13:05.347350 ===================================
2200 11:13:05.350161 data_rate = 2400,PCW = 0X5b00
2201 11:13:05.353609 ===================================
2202 11:13:05.356824 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 11:13:05.359972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 11:13:05.366907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 11:13:05.370165 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 11:13:05.373329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 11:13:05.376908 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 11:13:05.379965 [ANA_INIT] flow start
2209 11:13:05.383662 [ANA_INIT] PLL >>>>>>>>
2210 11:13:05.384090 [ANA_INIT] PLL <<<<<<<<
2211 11:13:05.387056 [ANA_INIT] MIDPI >>>>>>>>
2212 11:13:05.390288 [ANA_INIT] MIDPI <<<<<<<<
2213 11:13:05.393702 [ANA_INIT] DLL >>>>>>>>
2214 11:13:05.394122 [ANA_INIT] DLL <<<<<<<<
2215 11:13:05.396718 [ANA_INIT] flow end
2216 11:13:05.400112 ============ LP4 DIFF to SE enter ============
2217 11:13:05.403344 ============ LP4 DIFF to SE exit ============
2218 11:13:05.406528 [ANA_INIT] <<<<<<<<<<<<<
2219 11:13:05.409872 [Flow] Enable top DCM control >>>>>
2220 11:13:05.413112 [Flow] Enable top DCM control <<<<<
2221 11:13:05.416315 Enable DLL master slave shuffle
2222 11:13:05.423160 ==============================================================
2223 11:13:05.423738 Gating Mode config
2224 11:13:05.429888 ==============================================================
2225 11:13:05.430356 Config description:
2226 11:13:05.439802 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 11:13:05.446003 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 11:13:05.452685 SELPH_MODE 0: By rank 1: By Phase
2229 11:13:05.455926 ==============================================================
2230 11:13:05.459498 GAT_TRACK_EN = 1
2231 11:13:05.462694 RX_GATING_MODE = 2
2232 11:13:05.466006 RX_GATING_TRACK_MODE = 2
2233 11:13:05.469345 SELPH_MODE = 1
2234 11:13:05.472633 PICG_EARLY_EN = 1
2235 11:13:05.476004 VALID_LAT_VALUE = 1
2236 11:13:05.482764 ==============================================================
2237 11:13:05.486053 Enter into Gating configuration >>>>
2238 11:13:05.489593 Exit from Gating configuration <<<<
2239 11:13:05.490016 Enter into DVFS_PRE_config >>>>>
2240 11:13:05.503005 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 11:13:05.506254 Exit from DVFS_PRE_config <<<<<
2242 11:13:05.509571 Enter into PICG configuration >>>>
2243 11:13:05.512936 Exit from PICG configuration <<<<
2244 11:13:05.513518 [RX_INPUT] configuration >>>>>
2245 11:13:05.516532 [RX_INPUT] configuration <<<<<
2246 11:13:05.522568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 11:13:05.526281 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 11:13:05.532820 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 11:13:05.539601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 11:13:05.546408 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 11:13:05.552592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 11:13:05.555955 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 11:13:05.559458 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 11:13:05.566057 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 11:13:05.569560 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 11:13:05.572732 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 11:13:05.576115 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 11:13:05.579475 ===================================
2259 11:13:05.582562 LPDDR4 DRAM CONFIGURATION
2260 11:13:05.585820 ===================================
2261 11:13:05.589388 EX_ROW_EN[0] = 0x0
2262 11:13:05.589810 EX_ROW_EN[1] = 0x0
2263 11:13:05.592688 LP4Y_EN = 0x0
2264 11:13:05.593146 WORK_FSP = 0x0
2265 11:13:05.595986 WL = 0x4
2266 11:13:05.596408 RL = 0x4
2267 11:13:05.599278 BL = 0x2
2268 11:13:05.599693 RPST = 0x0
2269 11:13:05.602574 RD_PRE = 0x0
2270 11:13:05.602994 WR_PRE = 0x1
2271 11:13:05.605733 WR_PST = 0x0
2272 11:13:05.606153 DBI_WR = 0x0
2273 11:13:05.609510 DBI_RD = 0x0
2274 11:13:05.609935 OTF = 0x1
2275 11:13:05.612811 ===================================
2276 11:13:05.619204 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 11:13:05.622656 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 11:13:05.625964 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 11:13:05.629265 ===================================
2280 11:13:05.632722 LPDDR4 DRAM CONFIGURATION
2281 11:13:05.636023 ===================================
2282 11:13:05.639447 EX_ROW_EN[0] = 0x10
2283 11:13:05.639868 EX_ROW_EN[1] = 0x0
2284 11:13:05.642324 LP4Y_EN = 0x0
2285 11:13:05.642747 WORK_FSP = 0x0
2286 11:13:05.645715 WL = 0x4
2287 11:13:05.646195 RL = 0x4
2288 11:13:05.649226 BL = 0x2
2289 11:13:05.649648 RPST = 0x0
2290 11:13:05.652391 RD_PRE = 0x0
2291 11:13:05.652838 WR_PRE = 0x1
2292 11:13:05.655761 WR_PST = 0x0
2293 11:13:05.656185 DBI_WR = 0x0
2294 11:13:05.659127 DBI_RD = 0x0
2295 11:13:05.659548 OTF = 0x1
2296 11:13:05.662248 ===================================
2297 11:13:05.669074 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 11:13:05.669503 ==
2299 11:13:05.672530 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 11:13:05.678822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 11:13:05.679235 ==
2302 11:13:05.679561 [Duty_Offset_Calibration]
2303 11:13:05.682176 B0:2 B1:0 CA:1
2304 11:13:05.682584
2305 11:13:05.685810 [DutyScan_Calibration_Flow] k_type=0
2306 11:13:05.693515
2307 11:13:05.693951 ==CLK 0==
2308 11:13:05.696746 Final CLK duty delay cell = -4
2309 11:13:05.700415 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2310 11:13:05.703714 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2311 11:13:05.706877 [-4] AVG Duty = 4953%(X100)
2312 11:13:05.707287
2313 11:13:05.710133 CH0 CLK Duty spec in!! Max-Min= 156%
2314 11:13:05.713677 [DutyScan_Calibration_Flow] ====Done====
2315 11:13:05.714089
2316 11:13:05.716574 [DutyScan_Calibration_Flow] k_type=1
2317 11:13:05.732573
2318 11:13:05.733040 ==DQS 0 ==
2319 11:13:05.735702 Final DQS duty delay cell = 0
2320 11:13:05.738941 [0] MAX Duty = 5187%(X100), DQS PI = 30
2321 11:13:05.742637 [0] MIN Duty = 4938%(X100), DQS PI = 0
2322 11:13:05.745769 [0] AVG Duty = 5062%(X100)
2323 11:13:05.746220
2324 11:13:05.746575 ==DQS 1 ==
2325 11:13:05.749045 Final DQS duty delay cell = -4
2326 11:13:05.752082 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2327 11:13:05.755604 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2328 11:13:05.758852 [-4] AVG Duty = 5031%(X100)
2329 11:13:05.759264
2330 11:13:05.762295 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2331 11:13:05.762707
2332 11:13:05.765689 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2333 11:13:05.769058 [DutyScan_Calibration_Flow] ====Done====
2334 11:13:05.769469
2335 11:13:05.771653 [DutyScan_Calibration_Flow] k_type=3
2336 11:13:05.788212
2337 11:13:05.788293 ==DQM 0 ==
2338 11:13:05.791532 Final DQM duty delay cell = 0
2339 11:13:05.794561 [0] MAX Duty = 5062%(X100), DQS PI = 24
2340 11:13:05.797836 [0] MIN Duty = 4844%(X100), DQS PI = 0
2341 11:13:05.797917 [0] AVG Duty = 4953%(X100)
2342 11:13:05.801527
2343 11:13:05.801607 ==DQM 1 ==
2344 11:13:05.804946 Final DQM duty delay cell = -4
2345 11:13:05.807798 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2346 11:13:05.811253 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2347 11:13:05.814568 [-4] AVG Duty = 4906%(X100)
2348 11:13:05.814648
2349 11:13:05.817837 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2350 11:13:05.817917
2351 11:13:05.821151 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2352 11:13:05.824255 [DutyScan_Calibration_Flow] ====Done====
2353 11:13:05.824335
2354 11:13:05.827606 [DutyScan_Calibration_Flow] k_type=2
2355 11:13:05.844895
2356 11:13:05.844980 ==DQ 0 ==
2357 11:13:05.848047 Final DQ duty delay cell = -4
2358 11:13:05.851621 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2359 11:13:05.855031 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2360 11:13:05.858053 [-4] AVG Duty = 4953%(X100)
2361 11:13:05.858134
2362 11:13:05.858197 ==DQ 1 ==
2363 11:13:05.861355 Final DQ duty delay cell = 4
2364 11:13:05.864982 [4] MAX Duty = 5093%(X100), DQS PI = 4
2365 11:13:05.867951 [4] MIN Duty = 5031%(X100), DQS PI = 2
2366 11:13:05.868031 [4] AVG Duty = 5062%(X100)
2367 11:13:05.871420
2368 11:13:05.874612 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2369 11:13:05.874693
2370 11:13:05.878045 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2371 11:13:05.881604 [DutyScan_Calibration_Flow] ====Done====
2372 11:13:05.881684 ==
2373 11:13:05.884664 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 11:13:05.888039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 11:13:05.888121 ==
2376 11:13:05.891383 [Duty_Offset_Calibration]
2377 11:13:05.891463 B0:0 B1:-1 CA:2
2378 11:13:05.891527
2379 11:13:05.894732 [DutyScan_Calibration_Flow] k_type=0
2380 11:13:05.904967
2381 11:13:05.905047 ==CLK 0==
2382 11:13:05.908247 Final CLK duty delay cell = 0
2383 11:13:05.911501 [0] MAX Duty = 5156%(X100), DQS PI = 16
2384 11:13:05.914827 [0] MIN Duty = 4938%(X100), DQS PI = 44
2385 11:13:05.914909 [0] AVG Duty = 5047%(X100)
2386 11:13:05.918571
2387 11:13:05.921859 CH1 CLK Duty spec in!! Max-Min= 218%
2388 11:13:05.925120 [DutyScan_Calibration_Flow] ====Done====
2389 11:13:05.925201
2390 11:13:05.928324 [DutyScan_Calibration_Flow] k_type=1
2391 11:13:05.944281
2392 11:13:05.944366 ==DQS 0 ==
2393 11:13:05.947701 Final DQS duty delay cell = 0
2394 11:13:05.951238 [0] MAX Duty = 5093%(X100), DQS PI = 22
2395 11:13:05.954364 [0] MIN Duty = 4969%(X100), DQS PI = 0
2396 11:13:05.954445 [0] AVG Duty = 5031%(X100)
2397 11:13:05.957979
2398 11:13:05.958059 ==DQS 1 ==
2399 11:13:05.961529 Final DQS duty delay cell = 0
2400 11:13:05.964608 [0] MAX Duty = 5156%(X100), DQS PI = 0
2401 11:13:05.967863 [0] MIN Duty = 4844%(X100), DQS PI = 36
2402 11:13:05.967957 [0] AVG Duty = 5000%(X100)
2403 11:13:05.971004
2404 11:13:05.974882 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2405 11:13:05.975069
2406 11:13:05.977739 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2407 11:13:05.981163 [DutyScan_Calibration_Flow] ====Done====
2408 11:13:05.981346
2409 11:13:05.984595 [DutyScan_Calibration_Flow] k_type=3
2410 11:13:06.002059
2411 11:13:06.002548 ==DQM 0 ==
2412 11:13:06.005380 Final DQM duty delay cell = 4
2413 11:13:06.009140 [4] MAX Duty = 5093%(X100), DQS PI = 6
2414 11:13:06.012317 [4] MIN Duty = 4969%(X100), DQS PI = 28
2415 11:13:06.012879 [4] AVG Duty = 5031%(X100)
2416 11:13:06.015619
2417 11:13:06.016144 ==DQM 1 ==
2418 11:13:06.018917 Final DQM duty delay cell = 0
2419 11:13:06.022048 [0] MAX Duty = 5249%(X100), DQS PI = 0
2420 11:13:06.025400 [0] MIN Duty = 4875%(X100), DQS PI = 36
2421 11:13:06.029015 [0] AVG Duty = 5062%(X100)
2422 11:13:06.029541
2423 11:13:06.031950 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2424 11:13:06.032374
2425 11:13:06.035733 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2426 11:13:06.038661 [DutyScan_Calibration_Flow] ====Done====
2427 11:13:06.039142
2428 11:13:06.041781 [DutyScan_Calibration_Flow] k_type=2
2429 11:13:06.058752
2430 11:13:06.059339 ==DQ 0 ==
2431 11:13:06.061927 Final DQ duty delay cell = 0
2432 11:13:06.065132 [0] MAX Duty = 5062%(X100), DQS PI = 18
2433 11:13:06.068593 [0] MIN Duty = 4938%(X100), DQS PI = 0
2434 11:13:06.069056 [0] AVG Duty = 5000%(X100)
2435 11:13:06.069390
2436 11:13:06.071675 ==DQ 1 ==
2437 11:13:06.074873 Final DQ duty delay cell = 0
2438 11:13:06.078358 [0] MAX Duty = 5031%(X100), DQS PI = 0
2439 11:13:06.081567 [0] MIN Duty = 4813%(X100), DQS PI = 36
2440 11:13:06.081993 [0] AVG Duty = 4922%(X100)
2441 11:13:06.082363
2442 11:13:06.085175 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2443 11:13:06.088360
2444 11:13:06.091477 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2445 11:13:06.094403 [DutyScan_Calibration_Flow] ====Done====
2446 11:13:06.098446 nWR fixed to 30
2447 11:13:06.098523 [ModeRegInit_LP4] CH0 RK0
2448 11:13:06.101133 [ModeRegInit_LP4] CH0 RK1
2449 11:13:06.105057 [ModeRegInit_LP4] CH1 RK0
2450 11:13:06.105163 [ModeRegInit_LP4] CH1 RK1
2451 11:13:06.108406 match AC timing 7
2452 11:13:06.111616 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 11:13:06.115377 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 11:13:06.121608 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 11:13:06.124893 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 11:13:06.131435 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 11:13:06.131572 ==
2458 11:13:06.134775 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 11:13:06.138154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 11:13:06.138330 ==
2461 11:13:06.144732 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 11:13:06.151315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2463 11:13:06.158362 [CA 0] Center 38 (8~69) winsize 62
2464 11:13:06.161382 [CA 1] Center 38 (7~69) winsize 63
2465 11:13:06.165386 [CA 2] Center 35 (5~66) winsize 62
2466 11:13:06.168091 [CA 3] Center 35 (5~66) winsize 62
2467 11:13:06.171962 [CA 4] Center 34 (4~65) winsize 62
2468 11:13:06.175106 [CA 5] Center 33 (3~63) winsize 61
2469 11:13:06.175631
2470 11:13:06.178330 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2471 11:13:06.178899
2472 11:13:06.181518 [CATrainingPosCal] consider 1 rank data
2473 11:13:06.184867 u2DelayCellTimex100 = 270/100 ps
2474 11:13:06.188174 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2475 11:13:06.194569 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2476 11:13:06.198243 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 11:13:06.201532 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2478 11:13:06.204718 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2479 11:13:06.208182 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2480 11:13:06.208807
2481 11:13:06.211407 CA PerBit enable=1, Macro0, CA PI delay=33
2482 11:13:06.211952
2483 11:13:06.214908 [CBTSetCACLKResult] CA Dly = 33
2484 11:13:06.215474 CS Dly: 6 (0~37)
2485 11:13:06.218309 ==
2486 11:13:06.220971 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 11:13:06.225055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 11:13:06.225621 ==
2489 11:13:06.227970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 11:13:06.234724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2491 11:13:06.244494 [CA 0] Center 39 (8~70) winsize 63
2492 11:13:06.247783 [CA 1] Center 38 (8~69) winsize 62
2493 11:13:06.250750 [CA 2] Center 35 (5~66) winsize 62
2494 11:13:06.253920 [CA 3] Center 35 (5~66) winsize 62
2495 11:13:06.257394 [CA 4] Center 34 (4~65) winsize 62
2496 11:13:06.260909 [CA 5] Center 34 (4~64) winsize 61
2497 11:13:06.261439
2498 11:13:06.263900 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2499 11:13:06.264417
2500 11:13:06.267488 [CATrainingPosCal] consider 2 rank data
2501 11:13:06.270499 u2DelayCellTimex100 = 270/100 ps
2502 11:13:06.273784 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2503 11:13:06.280370 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2504 11:13:06.283638 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 11:13:06.286882 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 11:13:06.290551 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2507 11:13:06.293723 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2508 11:13:06.294181
2509 11:13:06.297057 CA PerBit enable=1, Macro0, CA PI delay=33
2510 11:13:06.297381
2511 11:13:06.300279 [CBTSetCACLKResult] CA Dly = 33
2512 11:13:06.300583 CS Dly: 7 (0~39)
2513 11:13:06.300928
2514 11:13:06.303357 ----->DramcWriteLeveling(PI) begin...
2515 11:13:06.306937 ==
2516 11:13:06.309958 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 11:13:06.313740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 11:13:06.313896 ==
2519 11:13:06.316883 Write leveling (Byte 0): 35 => 35
2520 11:13:06.320017 Write leveling (Byte 1): 32 => 32
2521 11:13:06.323372 DramcWriteLeveling(PI) end<-----
2522 11:13:06.323488
2523 11:13:06.323581 ==
2524 11:13:06.326811 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 11:13:06.330000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 11:13:06.330162 ==
2527 11:13:06.333390 [Gating] SW mode calibration
2528 11:13:06.339910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 11:13:06.346857 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 11:13:06.350121 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2531 11:13:06.353523 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2532 11:13:06.359885 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 11:13:06.363837 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 11:13:06.366741 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 11:13:06.370381 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 11:13:06.376529 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2537 11:13:06.380330 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
2538 11:13:06.383694 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
2539 11:13:06.390113 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 11:13:06.393449 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 11:13:06.397250 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 11:13:06.403672 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 11:13:06.406945 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 11:13:06.410254 1 0 24 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
2545 11:13:06.417311 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2546 11:13:06.420254 1 1 0 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
2547 11:13:06.423730 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2548 11:13:06.430272 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 11:13:06.433359 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 11:13:06.437140 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 11:13:06.443529 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 11:13:06.446798 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 11:13:06.450169 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2554 11:13:06.456361 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 11:13:06.459695 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:13:06.462931 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:13:06.469882 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:13:06.473219 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:13:06.476161 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:13:06.482761 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:13:06.486292 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:13:06.489822 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:13:06.495885 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:13:06.499507 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:13:06.502713 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 11:13:06.509291 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 11:13:06.512550 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 11:13:06.516247 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 11:13:06.522925 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 11:13:06.526169 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 11:13:06.529620 Total UI for P1: 0, mck2ui 16
2572 11:13:06.532958 best dqsien dly found for B0: ( 1, 3, 26)
2573 11:13:06.536451 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 11:13:06.539493 Total UI for P1: 0, mck2ui 16
2575 11:13:06.542901 best dqsien dly found for B1: ( 1, 4, 0)
2576 11:13:06.546265 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2577 11:13:06.549485 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2578 11:13:06.549911
2579 11:13:06.552742 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2580 11:13:06.556159 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2581 11:13:06.559685 [Gating] SW calibration Done
2582 11:13:06.560278 ==
2583 11:13:06.562596 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 11:13:06.569527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 11:13:06.569981 ==
2586 11:13:06.570324 RX Vref Scan: 0
2587 11:13:06.570641
2588 11:13:06.572808 RX Vref 0 -> 0, step: 1
2589 11:13:06.573245
2590 11:13:06.576139 RX Delay -40 -> 252, step: 8
2591 11:13:06.579215 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2592 11:13:06.582462 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2593 11:13:06.586143 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2594 11:13:06.589122 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2595 11:13:06.595843 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2596 11:13:06.599226 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2597 11:13:06.602321 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2598 11:13:06.605850 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2599 11:13:06.609250 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2600 11:13:06.616360 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2601 11:13:06.619495 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2602 11:13:06.622342 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2603 11:13:06.626099 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2604 11:13:06.629083 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2605 11:13:06.635781 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2606 11:13:06.639608 iDelay=208, Bit 15, Center 119 (56 ~ 183) 128
2607 11:13:06.640031 ==
2608 11:13:06.642371 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 11:13:06.645632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 11:13:06.646058 ==
2611 11:13:06.648880 DQS Delay:
2612 11:13:06.649298 DQS0 = 0, DQS1 = 0
2613 11:13:06.649635 DQM Delay:
2614 11:13:06.652519 DQM0 = 123, DQM1 = 110
2615 11:13:06.653084 DQ Delay:
2616 11:13:06.656262 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2617 11:13:06.659455 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2618 11:13:06.662513 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2619 11:13:06.669081 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =119
2620 11:13:06.669595
2621 11:13:06.669937
2622 11:13:06.670245 ==
2623 11:13:06.672510 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 11:13:06.676053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 11:13:06.676575 ==
2626 11:13:06.676966
2627 11:13:06.677285
2628 11:13:06.678947 TX Vref Scan disable
2629 11:13:06.679371 == TX Byte 0 ==
2630 11:13:06.685607 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2631 11:13:06.689076 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2632 11:13:06.689503 == TX Byte 1 ==
2633 11:13:06.695759 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2634 11:13:06.698815 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2635 11:13:06.699242 ==
2636 11:13:06.702107 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 11:13:06.705555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 11:13:06.705978 ==
2639 11:13:06.718670 TX Vref=22, minBit 5, minWin=23, winSum=401
2640 11:13:06.722185 TX Vref=24, minBit 0, minWin=25, winSum=414
2641 11:13:06.725364 TX Vref=26, minBit 4, minWin=24, winSum=415
2642 11:13:06.728744 TX Vref=28, minBit 7, minWin=24, winSum=414
2643 11:13:06.732319 TX Vref=30, minBit 0, minWin=25, winSum=414
2644 11:13:06.738659 TX Vref=32, minBit 0, minWin=25, winSum=414
2645 11:13:06.741516 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 24
2646 11:13:06.741939
2647 11:13:06.744758 Final TX Range 1 Vref 24
2648 11:13:06.745205
2649 11:13:06.745541 ==
2650 11:13:06.748048 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 11:13:06.751802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 11:13:06.752225 ==
2653 11:13:06.754610
2654 11:13:06.755025
2655 11:13:06.755355 TX Vref Scan disable
2656 11:13:06.758104 == TX Byte 0 ==
2657 11:13:06.761630 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2658 11:13:06.764944 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2659 11:13:06.768185 == TX Byte 1 ==
2660 11:13:06.771549 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2661 11:13:06.775133 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2662 11:13:06.778158
2663 11:13:06.778675 [DATLAT]
2664 11:13:06.779012 Freq=1200, CH0 RK0
2665 11:13:06.779327
2666 11:13:06.781658 DATLAT Default: 0xd
2667 11:13:06.782077 0, 0xFFFF, sum = 0
2668 11:13:06.784725 1, 0xFFFF, sum = 0
2669 11:13:06.785199 2, 0xFFFF, sum = 0
2670 11:13:06.787888 3, 0xFFFF, sum = 0
2671 11:13:06.791326 4, 0xFFFF, sum = 0
2672 11:13:06.791752 5, 0xFFFF, sum = 0
2673 11:13:06.794430 6, 0xFFFF, sum = 0
2674 11:13:06.794857 7, 0xFFFF, sum = 0
2675 11:13:06.797861 8, 0xFFFF, sum = 0
2676 11:13:06.798286 9, 0xFFFF, sum = 0
2677 11:13:06.800869 10, 0xFFFF, sum = 0
2678 11:13:06.801296 11, 0xFFFF, sum = 0
2679 11:13:06.804597 12, 0x0, sum = 1
2680 11:13:06.805067 13, 0x0, sum = 2
2681 11:13:06.807705 14, 0x0, sum = 3
2682 11:13:06.808132 15, 0x0, sum = 4
2683 11:13:06.811069 best_step = 13
2684 11:13:06.811487
2685 11:13:06.811821 ==
2686 11:13:06.814316 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 11:13:06.817494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 11:13:06.817576 ==
2689 11:13:06.817640 RX Vref Scan: 1
2690 11:13:06.817699
2691 11:13:06.820823 Set Vref Range= 32 -> 127
2692 11:13:06.820929
2693 11:13:06.824081 RX Vref 32 -> 127, step: 1
2694 11:13:06.824162
2695 11:13:06.827325 RX Delay -13 -> 252, step: 4
2696 11:13:06.827486
2697 11:13:06.830528 Set Vref, RX VrefLevel [Byte0]: 32
2698 11:13:06.833868 [Byte1]: 32
2699 11:13:06.834040
2700 11:13:06.837424 Set Vref, RX VrefLevel [Byte0]: 33
2701 11:13:06.840472 [Byte1]: 33
2702 11:13:06.844483
2703 11:13:06.844668 Set Vref, RX VrefLevel [Byte0]: 34
2704 11:13:06.847558 [Byte1]: 34
2705 11:13:06.852251
2706 11:13:06.852422 Set Vref, RX VrefLevel [Byte0]: 35
2707 11:13:06.855607 [Byte1]: 35
2708 11:13:06.860188
2709 11:13:06.860363 Set Vref, RX VrefLevel [Byte0]: 36
2710 11:13:06.863390 [Byte1]: 36
2711 11:13:06.868504
2712 11:13:06.868780 Set Vref, RX VrefLevel [Byte0]: 37
2713 11:13:06.871614 [Byte1]: 37
2714 11:13:06.876253
2715 11:13:06.876600 Set Vref, RX VrefLevel [Byte0]: 38
2716 11:13:06.879361 [Byte1]: 38
2717 11:13:06.883808
2718 11:13:06.884185 Set Vref, RX VrefLevel [Byte0]: 39
2719 11:13:06.886669 [Byte1]: 39
2720 11:13:06.891247
2721 11:13:06.891334 Set Vref, RX VrefLevel [Byte0]: 40
2722 11:13:06.894755 [Byte1]: 40
2723 11:13:06.899260
2724 11:13:06.899436 Set Vref, RX VrefLevel [Byte0]: 41
2725 11:13:06.902684 [Byte1]: 41
2726 11:13:06.907215
2727 11:13:06.907376 Set Vref, RX VrefLevel [Byte0]: 42
2728 11:13:06.910321 [Byte1]: 42
2729 11:13:06.915139
2730 11:13:06.915261 Set Vref, RX VrefLevel [Byte0]: 43
2731 11:13:06.918315 [Byte1]: 43
2732 11:13:06.923417
2733 11:13:06.923568 Set Vref, RX VrefLevel [Byte0]: 44
2734 11:13:06.926281 [Byte1]: 44
2735 11:13:06.931142
2736 11:13:06.931446 Set Vref, RX VrefLevel [Byte0]: 45
2737 11:13:06.934244 [Byte1]: 45
2738 11:13:06.939072
2739 11:13:06.939414 Set Vref, RX VrefLevel [Byte0]: 46
2740 11:13:06.942475 [Byte1]: 46
2741 11:13:06.947403
2742 11:13:06.948123 Set Vref, RX VrefLevel [Byte0]: 47
2743 11:13:06.950261 [Byte1]: 47
2744 11:13:06.954855
2745 11:13:06.955300 Set Vref, RX VrefLevel [Byte0]: 48
2746 11:13:06.958156 [Byte1]: 48
2747 11:13:06.963091
2748 11:13:06.963518 Set Vref, RX VrefLevel [Byte0]: 49
2749 11:13:06.966434 [Byte1]: 49
2750 11:13:06.971163
2751 11:13:06.971692 Set Vref, RX VrefLevel [Byte0]: 50
2752 11:13:06.974419 [Byte1]: 50
2753 11:13:06.979006
2754 11:13:06.979545 Set Vref, RX VrefLevel [Byte0]: 51
2755 11:13:06.981993 [Byte1]: 51
2756 11:13:06.986956
2757 11:13:06.987493 Set Vref, RX VrefLevel [Byte0]: 52
2758 11:13:06.989988 [Byte1]: 52
2759 11:13:06.994581
2760 11:13:06.995155 Set Vref, RX VrefLevel [Byte0]: 53
2761 11:13:06.997803 [Byte1]: 53
2762 11:13:07.002894
2763 11:13:07.003515 Set Vref, RX VrefLevel [Byte0]: 54
2764 11:13:07.005522 [Byte1]: 54
2765 11:13:07.010011
2766 11:13:07.010435 Set Vref, RX VrefLevel [Byte0]: 55
2767 11:13:07.013641 [Byte1]: 55
2768 11:13:07.018201
2769 11:13:07.018753 Set Vref, RX VrefLevel [Byte0]: 56
2770 11:13:07.021439 [Byte1]: 56
2771 11:13:07.026337
2772 11:13:07.026957 Set Vref, RX VrefLevel [Byte0]: 57
2773 11:13:07.029182 [Byte1]: 57
2774 11:13:07.034049
2775 11:13:07.034688 Set Vref, RX VrefLevel [Byte0]: 58
2776 11:13:07.037136 [Byte1]: 58
2777 11:13:07.042137
2778 11:13:07.042669 Set Vref, RX VrefLevel [Byte0]: 59
2779 11:13:07.045055 [Byte1]: 59
2780 11:13:07.049795
2781 11:13:07.050374 Set Vref, RX VrefLevel [Byte0]: 60
2782 11:13:07.052739 [Byte1]: 60
2783 11:13:07.057243
2784 11:13:07.057662 Set Vref, RX VrefLevel [Byte0]: 61
2785 11:13:07.060761 [Byte1]: 61
2786 11:13:07.065519
2787 11:13:07.065942 Set Vref, RX VrefLevel [Byte0]: 62
2788 11:13:07.068871 [Byte1]: 62
2789 11:13:07.073437
2790 11:13:07.073963 Set Vref, RX VrefLevel [Byte0]: 63
2791 11:13:07.076681 [Byte1]: 63
2792 11:13:07.081327
2793 11:13:07.081754 Set Vref, RX VrefLevel [Byte0]: 64
2794 11:13:07.084972 [Byte1]: 64
2795 11:13:07.089647
2796 11:13:07.090177 Set Vref, RX VrefLevel [Byte0]: 65
2797 11:13:07.092971 [Byte1]: 65
2798 11:13:07.097133
2799 11:13:07.097560 Set Vref, RX VrefLevel [Byte0]: 66
2800 11:13:07.100537 [Byte1]: 66
2801 11:13:07.104824
2802 11:13:07.105382 Set Vref, RX VrefLevel [Byte0]: 67
2803 11:13:07.108348 [Byte1]: 67
2804 11:13:07.113057
2805 11:13:07.113618 Set Vref, RX VrefLevel [Byte0]: 68
2806 11:13:07.116197 [Byte1]: 68
2807 11:13:07.120538
2808 11:13:07.120985 Set Vref, RX VrefLevel [Byte0]: 69
2809 11:13:07.124016 [Byte1]: 69
2810 11:13:07.128811
2811 11:13:07.129349 Set Vref, RX VrefLevel [Byte0]: 70
2812 11:13:07.132170 [Byte1]: 70
2813 11:13:07.136588
2814 11:13:07.137091 Final RX Vref Byte 0 = 57 to rank0
2815 11:13:07.140005 Final RX Vref Byte 1 = 48 to rank0
2816 11:13:07.143083 Final RX Vref Byte 0 = 57 to rank1
2817 11:13:07.146355 Final RX Vref Byte 1 = 48 to rank1==
2818 11:13:07.149941 Dram Type= 6, Freq= 0, CH_0, rank 0
2819 11:13:07.156339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 11:13:07.156830 ==
2821 11:13:07.157208 DQS Delay:
2822 11:13:07.157527 DQS0 = 0, DQS1 = 0
2823 11:13:07.159947 DQM Delay:
2824 11:13:07.160392 DQM0 = 122, DQM1 = 109
2825 11:13:07.162763 DQ Delay:
2826 11:13:07.166468 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2827 11:13:07.169268 DQ4 =124, DQ5 =116, DQ6 =130, DQ7 =128
2828 11:13:07.173015 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2829 11:13:07.176280 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2830 11:13:07.176852
2831 11:13:07.177226
2832 11:13:07.186438 [DQSOSCAuto] RK0, (LSB)MR18= 0xb07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
2833 11:13:07.186979 CH0 RK0: MR19=404, MR18=B07
2834 11:13:07.192973 CH0_RK0: MR19=0x404, MR18=0xB07, DQSOSC=405, MR23=63, INC=39, DEC=26
2835 11:13:07.193539
2836 11:13:07.196253 ----->DramcWriteLeveling(PI) begin...
2837 11:13:07.196684 ==
2838 11:13:07.199652 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 11:13:07.202901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 11:13:07.206019 ==
2841 11:13:07.206547 Write leveling (Byte 0): 35 => 35
2842 11:13:07.209244 Write leveling (Byte 1): 30 => 30
2843 11:13:07.212974 DramcWriteLeveling(PI) end<-----
2844 11:13:07.213582
2845 11:13:07.214100 ==
2846 11:13:07.215880 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 11:13:07.222479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 11:13:07.223072 ==
2849 11:13:07.226061 [Gating] SW mode calibration
2850 11:13:07.232308 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2851 11:13:07.236025 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2852 11:13:07.242190 0 15 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2853 11:13:07.245555 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 11:13:07.249283 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 11:13:07.255779 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 11:13:07.259199 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 11:13:07.262354 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 11:13:07.265894 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2859 11:13:07.272552 0 15 28 | B1->B0 | 3232 2f2f | 0 0 | (1 0) (0 1)
2860 11:13:07.275537 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 11:13:07.279039 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 11:13:07.285444 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 11:13:07.289662 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 11:13:07.292085 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 11:13:07.298884 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 11:13:07.302113 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2867 11:13:07.305828 1 0 28 | B1->B0 | 3535 3d3d | 0 0 | (1 1) (0 0)
2868 11:13:07.312257 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 11:13:07.315969 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 11:13:07.318701 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 11:13:07.325320 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 11:13:07.328720 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 11:13:07.331810 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 11:13:07.338706 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2875 11:13:07.341817 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2876 11:13:07.344966 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:13:07.352043 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:13:07.354943 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:13:07.358487 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:13:07.364994 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:13:07.368348 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 11:13:07.371824 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 11:13:07.378197 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 11:13:07.381641 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 11:13:07.385026 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 11:13:07.391700 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 11:13:07.394790 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:13:07.398483 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 11:13:07.405298 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 11:13:07.408326 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2891 11:13:07.411588 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2892 11:13:07.418352 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 11:13:07.418899 Total UI for P1: 0, mck2ui 16
2894 11:13:07.424951 best dqsien dly found for B0: ( 1, 3, 26)
2895 11:13:07.425372 Total UI for P1: 0, mck2ui 16
2896 11:13:07.431180 best dqsien dly found for B1: ( 1, 3, 30)
2897 11:13:07.434448 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2898 11:13:07.438377 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2899 11:13:07.438802
2900 11:13:07.441072 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2901 11:13:07.444517 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2902 11:13:07.447794 [Gating] SW calibration Done
2903 11:13:07.448216 ==
2904 11:13:07.451125 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 11:13:07.454667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 11:13:07.455210 ==
2907 11:13:07.458006 RX Vref Scan: 0
2908 11:13:07.458548
2909 11:13:07.458887 RX Vref 0 -> 0, step: 1
2910 11:13:07.459196
2911 11:13:07.461134 RX Delay -40 -> 252, step: 8
2912 11:13:07.464696 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2913 11:13:07.471146 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2914 11:13:07.474250 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2915 11:13:07.478249 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2916 11:13:07.480937 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2917 11:13:07.484193 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2918 11:13:07.491278 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2919 11:13:07.494412 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2920 11:13:07.497646 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2921 11:13:07.501055 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2922 11:13:07.504872 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2923 11:13:07.511492 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2924 11:13:07.514569 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2925 11:13:07.517929 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2926 11:13:07.521376 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2927 11:13:07.524489 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2928 11:13:07.527405 ==
2929 11:13:07.530538 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 11:13:07.533983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 11:13:07.534418 ==
2932 11:13:07.534853 DQS Delay:
2933 11:13:07.537316 DQS0 = 0, DQS1 = 0
2934 11:13:07.537826 DQM Delay:
2935 11:13:07.540594 DQM0 = 120, DQM1 = 108
2936 11:13:07.541060 DQ Delay:
2937 11:13:07.543933 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2938 11:13:07.547767 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2939 11:13:07.550869 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2940 11:13:07.554005 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2941 11:13:07.554432
2942 11:13:07.554793
2943 11:13:07.555104 ==
2944 11:13:07.557178 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 11:13:07.564154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 11:13:07.564584 ==
2947 11:13:07.564977
2948 11:13:07.565295
2949 11:13:07.565599 TX Vref Scan disable
2950 11:13:07.567692 == TX Byte 0 ==
2951 11:13:07.570861 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2952 11:13:07.577425 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2953 11:13:07.577952 == TX Byte 1 ==
2954 11:13:07.580653 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2955 11:13:07.587271 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2956 11:13:07.587720 ==
2957 11:13:07.590702 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 11:13:07.593890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 11:13:07.594358 ==
2960 11:13:07.605447 TX Vref=22, minBit 0, minWin=24, winSum=411
2961 11:13:07.608826 TX Vref=24, minBit 2, minWin=24, winSum=413
2962 11:13:07.612501 TX Vref=26, minBit 7, minWin=24, winSum=418
2963 11:13:07.615807 TX Vref=28, minBit 1, minWin=25, winSum=424
2964 11:13:07.619210 TX Vref=30, minBit 5, minWin=25, winSum=427
2965 11:13:07.625575 TX Vref=32, minBit 2, minWin=25, winSum=421
2966 11:13:07.628658 [TxChooseVref] Worse bit 5, Min win 25, Win sum 427, Final Vref 30
2967 11:13:07.629126
2968 11:13:07.631974 Final TX Range 1 Vref 30
2969 11:13:07.632410
2970 11:13:07.632944 ==
2971 11:13:07.635355 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 11:13:07.638606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 11:13:07.639058 ==
2974 11:13:07.641999
2975 11:13:07.642429
2976 11:13:07.642860 TX Vref Scan disable
2977 11:13:07.645310 == TX Byte 0 ==
2978 11:13:07.648805 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2979 11:13:07.655495 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2980 11:13:07.655928 == TX Byte 1 ==
2981 11:13:07.658740 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2982 11:13:07.665405 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2983 11:13:07.665839
2984 11:13:07.666270 [DATLAT]
2985 11:13:07.666675 Freq=1200, CH0 RK1
2986 11:13:07.667074
2987 11:13:07.668445 DATLAT Default: 0xd
2988 11:13:07.668923 0, 0xFFFF, sum = 0
2989 11:13:07.671738 1, 0xFFFF, sum = 0
2990 11:13:07.675383 2, 0xFFFF, sum = 0
2991 11:13:07.675817 3, 0xFFFF, sum = 0
2992 11:13:07.678736 4, 0xFFFF, sum = 0
2993 11:13:07.679173 5, 0xFFFF, sum = 0
2994 11:13:07.682134 6, 0xFFFF, sum = 0
2995 11:13:07.682569 7, 0xFFFF, sum = 0
2996 11:13:07.685422 8, 0xFFFF, sum = 0
2997 11:13:07.685859 9, 0xFFFF, sum = 0
2998 11:13:07.688756 10, 0xFFFF, sum = 0
2999 11:13:07.689339 11, 0xFFFF, sum = 0
3000 11:13:07.692021 12, 0x0, sum = 1
3001 11:13:07.692459 13, 0x0, sum = 2
3002 11:13:07.695246 14, 0x0, sum = 3
3003 11:13:07.695686 15, 0x0, sum = 4
3004 11:13:07.698372 best_step = 13
3005 11:13:07.698803
3006 11:13:07.699227 ==
3007 11:13:07.702220 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 11:13:07.705113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 11:13:07.705554 ==
3010 11:13:07.705989 RX Vref Scan: 0
3011 11:13:07.706397
3012 11:13:07.708334 RX Vref 0 -> 0, step: 1
3013 11:13:07.708792
3014 11:13:07.711699 RX Delay -21 -> 252, step: 4
3015 11:13:07.715040 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3016 11:13:07.722178 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3017 11:13:07.725466 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3018 11:13:07.728913 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3019 11:13:07.732160 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3020 11:13:07.735110 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3021 11:13:07.741689 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3022 11:13:07.745268 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3023 11:13:07.748210 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3024 11:13:07.751795 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3025 11:13:07.754975 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3026 11:13:07.761538 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3027 11:13:07.764841 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3028 11:13:07.768269 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3029 11:13:07.771752 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3030 11:13:07.775062 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3031 11:13:07.778803 ==
3032 11:13:07.779323 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 11:13:07.785361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 11:13:07.785905 ==
3035 11:13:07.786241 DQS Delay:
3036 11:13:07.788605 DQS0 = 0, DQS1 = 0
3037 11:13:07.789161 DQM Delay:
3038 11:13:07.791827 DQM0 = 119, DQM1 = 107
3039 11:13:07.792351 DQ Delay:
3040 11:13:07.795028 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3041 11:13:07.798535 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3042 11:13:07.801834 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3043 11:13:07.805015 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3044 11:13:07.805431
3045 11:13:07.805763
3046 11:13:07.815209 [DQSOSCAuto] RK1, (LSB)MR18= 0xff6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3047 11:13:07.815741 CH0 RK1: MR19=403, MR18=FF6
3048 11:13:07.821592 CH0_RK1: MR19=0x403, MR18=0xFF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3049 11:13:07.825189 [RxdqsGatingPostProcess] freq 1200
3050 11:13:07.831514 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3051 11:13:07.835294 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 11:13:07.838351 best DQS1 dly(2T, 0.5T) = (0, 12)
3053 11:13:07.841373 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 11:13:07.844926 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3055 11:13:07.848210 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 11:13:07.848743 best DQS1 dly(2T, 0.5T) = (0, 11)
3057 11:13:07.851657 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 11:13:07.854627 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3059 11:13:07.857974 Pre-setting of DQS Precalculation
3060 11:13:07.864792 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3061 11:13:07.865330 ==
3062 11:13:07.867830 Dram Type= 6, Freq= 0, CH_1, rank 0
3063 11:13:07.871056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 11:13:07.871480 ==
3065 11:13:07.877567 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3066 11:13:07.884257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3067 11:13:07.891955 [CA 0] Center 37 (7~68) winsize 62
3068 11:13:07.895175 [CA 1] Center 37 (7~68) winsize 62
3069 11:13:07.898189 [CA 2] Center 35 (5~65) winsize 61
3070 11:13:07.901570 [CA 3] Center 34 (4~65) winsize 62
3071 11:13:07.905045 [CA 4] Center 34 (4~64) winsize 61
3072 11:13:07.908055 [CA 5] Center 33 (3~64) winsize 62
3073 11:13:07.908489
3074 11:13:07.911494 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3075 11:13:07.912009
3076 11:13:07.914666 [CATrainingPosCal] consider 1 rank data
3077 11:13:07.917900 u2DelayCellTimex100 = 270/100 ps
3078 11:13:07.921171 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3079 11:13:07.928199 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3080 11:13:07.931318 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3081 11:13:07.934509 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3082 11:13:07.937634 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3083 11:13:07.941107 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3084 11:13:07.941528
3085 11:13:07.944313 CA PerBit enable=1, Macro0, CA PI delay=33
3086 11:13:07.944736
3087 11:13:07.948002 [CBTSetCACLKResult] CA Dly = 33
3088 11:13:07.951326 CS Dly: 5 (0~36)
3089 11:13:07.951871 ==
3090 11:13:07.954431 Dram Type= 6, Freq= 0, CH_1, rank 1
3091 11:13:07.957625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 11:13:07.958047 ==
3093 11:13:07.964108 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3094 11:13:07.967693 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3095 11:13:07.977085 [CA 0] Center 38 (8~68) winsize 61
3096 11:13:07.980310 [CA 1] Center 38 (8~68) winsize 61
3097 11:13:07.983717 [CA 2] Center 35 (5~66) winsize 62
3098 11:13:07.987099 [CA 3] Center 34 (4~65) winsize 62
3099 11:13:07.990509 [CA 4] Center 35 (5~65) winsize 61
3100 11:13:07.993860 [CA 5] Center 34 (4~64) winsize 61
3101 11:13:07.994292
3102 11:13:07.997087 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3103 11:13:07.997516
3104 11:13:08.000532 [CATrainingPosCal] consider 2 rank data
3105 11:13:08.003983 u2DelayCellTimex100 = 270/100 ps
3106 11:13:08.007172 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3107 11:13:08.013593 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3108 11:13:08.016822 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3109 11:13:08.020431 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3110 11:13:08.023497 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3111 11:13:08.026893 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3112 11:13:08.027319
3113 11:13:08.030323 CA PerBit enable=1, Macro0, CA PI delay=34
3114 11:13:08.030750
3115 11:13:08.033435 [CBTSetCACLKResult] CA Dly = 34
3116 11:13:08.033871 CS Dly: 6 (0~39)
3117 11:13:08.036707
3118 11:13:08.040403 ----->DramcWriteLeveling(PI) begin...
3119 11:13:08.040956 ==
3120 11:13:08.043182 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 11:13:08.046968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 11:13:08.047396 ==
3123 11:13:08.050277 Write leveling (Byte 0): 25 => 25
3124 11:13:08.053551 Write leveling (Byte 1): 27 => 27
3125 11:13:08.056794 DramcWriteLeveling(PI) end<-----
3126 11:13:08.057247
3127 11:13:08.057589 ==
3128 11:13:08.060176 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 11:13:08.063307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 11:13:08.063822 ==
3131 11:13:08.066694 [Gating] SW mode calibration
3132 11:13:08.073607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3133 11:13:08.080118 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3134 11:13:08.083479 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 11:13:08.086838 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 11:13:08.093030 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 11:13:08.096332 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 11:13:08.099699 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 11:13:08.106275 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3140 11:13:08.109593 0 15 24 | B1->B0 | 2828 2525 | 1 0 | (1 1) (1 0)
3141 11:13:08.112827 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3142 11:13:08.119867 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 11:13:08.122875 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 11:13:08.126625 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 11:13:08.129930 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 11:13:08.136441 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 11:13:08.139712 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3148 11:13:08.146833 1 0 24 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
3149 11:13:08.150045 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 11:13:08.153190 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 11:13:08.156118 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 11:13:08.163595 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 11:13:08.166405 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 11:13:08.169705 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 11:13:08.176583 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3156 11:13:08.179589 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3157 11:13:08.183094 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3158 11:13:08.189472 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:13:08.192908 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:13:08.196185 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:13:08.202584 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:13:08.206010 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:13:08.208945 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:13:08.215540 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 11:13:08.219231 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 11:13:08.222148 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 11:13:08.228902 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 11:13:08.232447 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 11:13:08.236096 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 11:13:08.242336 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 11:13:08.245308 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 11:13:08.248813 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3173 11:13:08.255287 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 11:13:08.255908 Total UI for P1: 0, mck2ui 16
3175 11:13:08.262167 best dqsien dly found for B0: ( 1, 3, 24)
3176 11:13:08.262643 Total UI for P1: 0, mck2ui 16
3177 11:13:08.268689 best dqsien dly found for B1: ( 1, 3, 24)
3178 11:13:08.272193 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3179 11:13:08.275569 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3180 11:13:08.276099
3181 11:13:08.278665 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3182 11:13:08.282249 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3183 11:13:08.285543 [Gating] SW calibration Done
3184 11:13:08.285977 ==
3185 11:13:08.288398 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 11:13:08.292042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 11:13:08.292460 ==
3188 11:13:08.295420 RX Vref Scan: 0
3189 11:13:08.295856
3190 11:13:08.296231 RX Vref 0 -> 0, step: 1
3191 11:13:08.296548
3192 11:13:08.298492 RX Delay -40 -> 252, step: 8
3193 11:13:08.301718 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3194 11:13:08.308674 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3195 11:13:08.311981 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3196 11:13:08.315330 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3197 11:13:08.318622 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3198 11:13:08.322128 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3199 11:13:08.328579 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3200 11:13:08.331980 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3201 11:13:08.334986 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3202 11:13:08.338712 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3203 11:13:08.341791 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3204 11:13:08.348404 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3205 11:13:08.351754 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3206 11:13:08.354973 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3207 11:13:08.358239 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3208 11:13:08.361620 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3209 11:13:08.364692 ==
3210 11:13:08.368456 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 11:13:08.371849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 11:13:08.372281 ==
3213 11:13:08.372614 DQS Delay:
3214 11:13:08.375301 DQS0 = 0, DQS1 = 0
3215 11:13:08.375833 DQM Delay:
3216 11:13:08.377969 DQM0 = 119, DQM1 = 112
3217 11:13:08.378386 DQ Delay:
3218 11:13:08.381626 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3219 11:13:08.384715 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3220 11:13:08.388427 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3221 11:13:08.391436 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3222 11:13:08.391941
3223 11:13:08.392272
3224 11:13:08.392576 ==
3225 11:13:08.394873 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 11:13:08.401825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 11:13:08.402360 ==
3228 11:13:08.402699
3229 11:13:08.403013
3230 11:13:08.403312 TX Vref Scan disable
3231 11:13:08.404892 == TX Byte 0 ==
3232 11:13:08.408352 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3233 11:13:08.414915 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3234 11:13:08.415341 == TX Byte 1 ==
3235 11:13:08.418169 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3236 11:13:08.421599 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3237 11:13:08.424429 ==
3238 11:13:08.427882 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 11:13:08.431466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 11:13:08.431544 ==
3241 11:13:08.442205 TX Vref=22, minBit 11, minWin=23, winSum=404
3242 11:13:08.446092 TX Vref=24, minBit 3, minWin=24, winSum=408
3243 11:13:08.449265 TX Vref=26, minBit 8, minWin=25, winSum=414
3244 11:13:08.452776 TX Vref=28, minBit 10, minWin=25, winSum=422
3245 11:13:08.455900 TX Vref=30, minBit 10, minWin=25, winSum=422
3246 11:13:08.462495 TX Vref=32, minBit 9, minWin=25, winSum=419
3247 11:13:08.465565 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 28
3248 11:13:08.465731
3249 11:13:08.468706 Final TX Range 1 Vref 28
3250 11:13:08.468899
3251 11:13:08.469012 ==
3252 11:13:08.472268 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 11:13:08.479159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 11:13:08.479401 ==
3255 11:13:08.479537
3256 11:13:08.479660
3257 11:13:08.479775 TX Vref Scan disable
3258 11:13:08.482905 == TX Byte 0 ==
3259 11:13:08.486142 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3260 11:13:08.489390 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3261 11:13:08.492700 == TX Byte 1 ==
3262 11:13:08.496181 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3263 11:13:08.502587 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3264 11:13:08.503017
3265 11:13:08.503328 [DATLAT]
3266 11:13:08.503568 Freq=1200, CH1 RK0
3267 11:13:08.503794
3268 11:13:08.506193 DATLAT Default: 0xd
3269 11:13:08.506693 0, 0xFFFF, sum = 0
3270 11:13:08.509309 1, 0xFFFF, sum = 0
3271 11:13:08.509854 2, 0xFFFF, sum = 0
3272 11:13:08.512939 3, 0xFFFF, sum = 0
3273 11:13:08.516207 4, 0xFFFF, sum = 0
3274 11:13:08.516797 5, 0xFFFF, sum = 0
3275 11:13:08.519571 6, 0xFFFF, sum = 0
3276 11:13:08.520109 7, 0xFFFF, sum = 0
3277 11:13:08.522496 8, 0xFFFF, sum = 0
3278 11:13:08.522942 9, 0xFFFF, sum = 0
3279 11:13:08.525868 10, 0xFFFF, sum = 0
3280 11:13:08.526300 11, 0xFFFF, sum = 0
3281 11:13:08.529093 12, 0x0, sum = 1
3282 11:13:08.529522 13, 0x0, sum = 2
3283 11:13:08.532843 14, 0x0, sum = 3
3284 11:13:08.533409 15, 0x0, sum = 4
3285 11:13:08.535623 best_step = 13
3286 11:13:08.536331
3287 11:13:08.536692 ==
3288 11:13:08.539138 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 11:13:08.542273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 11:13:08.542930 ==
3291 11:13:08.543334 RX Vref Scan: 1
3292 11:13:08.543674
3293 11:13:08.545511 Set Vref Range= 32 -> 127
3294 11:13:08.545935
3295 11:13:08.548753 RX Vref 32 -> 127, step: 1
3296 11:13:08.549217
3297 11:13:08.552220 RX Delay -13 -> 252, step: 4
3298 11:13:08.552876
3299 11:13:08.555442 Set Vref, RX VrefLevel [Byte0]: 32
3300 11:13:08.558690 [Byte1]: 32
3301 11:13:08.559129
3302 11:13:08.562142 Set Vref, RX VrefLevel [Byte0]: 33
3303 11:13:08.565604 [Byte1]: 33
3304 11:13:08.568926
3305 11:13:08.569338 Set Vref, RX VrefLevel [Byte0]: 34
3306 11:13:08.572243 [Byte1]: 34
3307 11:13:08.576984
3308 11:13:08.577393 Set Vref, RX VrefLevel [Byte0]: 35
3309 11:13:08.580321 [Byte1]: 35
3310 11:13:08.584986
3311 11:13:08.585398 Set Vref, RX VrefLevel [Byte0]: 36
3312 11:13:08.588182 [Byte1]: 36
3313 11:13:08.592569
3314 11:13:08.593110 Set Vref, RX VrefLevel [Byte0]: 37
3315 11:13:08.596208 [Byte1]: 37
3316 11:13:08.600476
3317 11:13:08.600945 Set Vref, RX VrefLevel [Byte0]: 38
3318 11:13:08.603818 [Byte1]: 38
3319 11:13:08.608310
3320 11:13:08.608899 Set Vref, RX VrefLevel [Byte0]: 39
3321 11:13:08.611798 [Byte1]: 39
3322 11:13:08.616563
3323 11:13:08.617237 Set Vref, RX VrefLevel [Byte0]: 40
3324 11:13:08.619579 [Byte1]: 40
3325 11:13:08.623926
3326 11:13:08.624422 Set Vref, RX VrefLevel [Byte0]: 41
3327 11:13:08.627744 [Byte1]: 41
3328 11:13:08.632262
3329 11:13:08.632869 Set Vref, RX VrefLevel [Byte0]: 42
3330 11:13:08.635563 [Byte1]: 42
3331 11:13:08.640134
3332 11:13:08.640551 Set Vref, RX VrefLevel [Byte0]: 43
3333 11:13:08.643420 [Byte1]: 43
3334 11:13:08.647927
3335 11:13:08.648334 Set Vref, RX VrefLevel [Byte0]: 44
3336 11:13:08.651224 [Byte1]: 44
3337 11:13:08.656016
3338 11:13:08.656534 Set Vref, RX VrefLevel [Byte0]: 45
3339 11:13:08.659427 [Byte1]: 45
3340 11:13:08.663985
3341 11:13:08.664582 Set Vref, RX VrefLevel [Byte0]: 46
3342 11:13:08.667232 [Byte1]: 46
3343 11:13:08.671739
3344 11:13:08.672243 Set Vref, RX VrefLevel [Byte0]: 47
3345 11:13:08.674971 [Byte1]: 47
3346 11:13:08.679970
3347 11:13:08.680505 Set Vref, RX VrefLevel [Byte0]: 48
3348 11:13:08.682834 [Byte1]: 48
3349 11:13:08.687698
3350 11:13:08.688249 Set Vref, RX VrefLevel [Byte0]: 49
3351 11:13:08.690962 [Byte1]: 49
3352 11:13:08.695292
3353 11:13:08.695704 Set Vref, RX VrefLevel [Byte0]: 50
3354 11:13:08.699005 [Byte1]: 50
3355 11:13:08.703395
3356 11:13:08.703804 Set Vref, RX VrefLevel [Byte0]: 51
3357 11:13:08.706610 [Byte1]: 51
3358 11:13:08.710856
3359 11:13:08.711259 Set Vref, RX VrefLevel [Byte0]: 52
3360 11:13:08.714693 [Byte1]: 52
3361 11:13:08.718898
3362 11:13:08.719305 Set Vref, RX VrefLevel [Byte0]: 53
3363 11:13:08.722207 [Byte1]: 53
3364 11:13:08.727270
3365 11:13:08.727674 Set Vref, RX VrefLevel [Byte0]: 54
3366 11:13:08.730263 [Byte1]: 54
3367 11:13:08.734948
3368 11:13:08.735352 Set Vref, RX VrefLevel [Byte0]: 55
3369 11:13:08.738054 [Byte1]: 55
3370 11:13:08.742484
3371 11:13:08.742899 Set Vref, RX VrefLevel [Byte0]: 56
3372 11:13:08.745876 [Byte1]: 56
3373 11:13:08.750552
3374 11:13:08.750956 Set Vref, RX VrefLevel [Byte0]: 57
3375 11:13:08.753859 [Byte1]: 57
3376 11:13:08.758209
3377 11:13:08.758616 Set Vref, RX VrefLevel [Byte0]: 58
3378 11:13:08.761934 [Byte1]: 58
3379 11:13:08.766201
3380 11:13:08.766606 Set Vref, RX VrefLevel [Byte0]: 59
3381 11:13:08.769770 [Byte1]: 59
3382 11:13:08.774308
3383 11:13:08.774387 Set Vref, RX VrefLevel [Byte0]: 60
3384 11:13:08.777271 [Byte1]: 60
3385 11:13:08.781861
3386 11:13:08.781940 Set Vref, RX VrefLevel [Byte0]: 61
3387 11:13:08.784759 [Byte1]: 61
3388 11:13:08.790273
3389 11:13:08.790784 Set Vref, RX VrefLevel [Byte0]: 62
3390 11:13:08.793240 [Byte1]: 62
3391 11:13:08.797854
3392 11:13:08.800979 Set Vref, RX VrefLevel [Byte0]: 63
3393 11:13:08.804359 [Byte1]: 63
3394 11:13:08.804903
3395 11:13:08.807655 Set Vref, RX VrefLevel [Byte0]: 64
3396 11:13:08.810831 [Byte1]: 64
3397 11:13:08.811244
3398 11:13:08.814428 Set Vref, RX VrefLevel [Byte0]: 65
3399 11:13:08.817352 [Byte1]: 65
3400 11:13:08.821485
3401 11:13:08.821986 Set Vref, RX VrefLevel [Byte0]: 66
3402 11:13:08.824752 [Byte1]: 66
3403 11:13:08.829401
3404 11:13:08.829806 Set Vref, RX VrefLevel [Byte0]: 67
3405 11:13:08.832690 [Byte1]: 67
3406 11:13:08.837542
3407 11:13:08.838072 Final RX Vref Byte 0 = 51 to rank0
3408 11:13:08.840699 Final RX Vref Byte 1 = 53 to rank0
3409 11:13:08.844001 Final RX Vref Byte 0 = 51 to rank1
3410 11:13:08.847270 Final RX Vref Byte 1 = 53 to rank1==
3411 11:13:08.850496 Dram Type= 6, Freq= 0, CH_1, rank 0
3412 11:13:08.857158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3413 11:13:08.857690 ==
3414 11:13:08.858025 DQS Delay:
3415 11:13:08.860545 DQS0 = 0, DQS1 = 0
3416 11:13:08.861006 DQM Delay:
3417 11:13:08.861342 DQM0 = 119, DQM1 = 112
3418 11:13:08.863547 DQ Delay:
3419 11:13:08.866688 DQ0 =122, DQ1 =112, DQ2 =112, DQ3 =118
3420 11:13:08.870343 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3421 11:13:08.873836 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3422 11:13:08.876822 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3423 11:13:08.877249
3424 11:13:08.877613
3425 11:13:08.886370 [DQSOSCAuto] RK0, (LSB)MR18= 0x14, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3426 11:13:08.886453 CH1 RK0: MR19=404, MR18=14
3427 11:13:08.893234 CH1_RK0: MR19=0x404, MR18=0x14, DQSOSC=402, MR23=63, INC=40, DEC=27
3428 11:13:08.893316
3429 11:13:08.896524 ----->DramcWriteLeveling(PI) begin...
3430 11:13:08.896625 ==
3431 11:13:08.899684 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 11:13:08.902851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 11:13:08.906383 ==
3434 11:13:08.906454 Write leveling (Byte 0): 25 => 25
3435 11:13:08.909883 Write leveling (Byte 1): 29 => 29
3436 11:13:08.913181 DramcWriteLeveling(PI) end<-----
3437 11:13:08.913263
3438 11:13:08.913328 ==
3439 11:13:08.916349 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 11:13:08.922867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 11:13:08.922949 ==
3442 11:13:08.923014 [Gating] SW mode calibration
3443 11:13:08.932704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3444 11:13:08.936208 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3445 11:13:08.943050 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 11:13:08.946117 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 11:13:08.949782 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 11:13:08.952841 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 11:13:08.959801 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 11:13:08.962753 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 11:13:08.966141 0 15 24 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
3452 11:13:08.972569 0 15 28 | B1->B0 | 2323 2d2d | 0 0 | (1 0) (0 0)
3453 11:13:08.975875 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 11:13:08.979420 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 11:13:08.986156 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 11:13:08.989423 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 11:13:08.992643 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 11:13:08.999267 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3459 11:13:09.002751 1 0 24 | B1->B0 | 3a3a 2424 | 0 0 | (0 0) (0 0)
3460 11:13:09.006236 1 0 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
3461 11:13:09.012843 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 11:13:09.016454 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 11:13:09.019262 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 11:13:09.025924 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 11:13:09.029442 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 11:13:09.032656 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 11:13:09.039086 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3468 11:13:09.042695 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3469 11:13:09.045650 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:13:09.052279 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:13:09.055645 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 11:13:09.059172 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:13:09.065502 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:13:09.069170 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:13:09.072502 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 11:13:09.078808 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 11:13:09.082099 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 11:13:09.085440 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 11:13:09.092218 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 11:13:09.095730 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 11:13:09.099201 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 11:13:09.105554 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 11:13:09.108721 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3484 11:13:09.112138 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 11:13:09.115425 Total UI for P1: 0, mck2ui 16
3486 11:13:09.118830 best dqsien dly found for B0: ( 1, 3, 24)
3487 11:13:09.122336 Total UI for P1: 0, mck2ui 16
3488 11:13:09.125390 best dqsien dly found for B1: ( 1, 3, 24)
3489 11:13:09.128718 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3490 11:13:09.132027 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3491 11:13:09.132442
3492 11:13:09.138542 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3493 11:13:09.141955 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3494 11:13:09.145020 [Gating] SW calibration Done
3495 11:13:09.145637 ==
3496 11:13:09.148556 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 11:13:09.151858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 11:13:09.152278 ==
3499 11:13:09.152609 RX Vref Scan: 0
3500 11:13:09.152967
3501 11:13:09.155098 RX Vref 0 -> 0, step: 1
3502 11:13:09.155516
3503 11:13:09.158445 RX Delay -40 -> 252, step: 8
3504 11:13:09.161722 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3505 11:13:09.165051 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3506 11:13:09.171448 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3507 11:13:09.174693 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3508 11:13:09.177943 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3509 11:13:09.181055 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3510 11:13:09.184391 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3511 11:13:09.191374 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3512 11:13:09.194504 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3513 11:13:09.198047 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3514 11:13:09.200953 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3515 11:13:09.204692 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3516 11:13:09.211213 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3517 11:13:09.214358 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3518 11:13:09.217551 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3519 11:13:09.221141 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3520 11:13:09.221223 ==
3521 11:13:09.224270 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 11:13:09.230852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 11:13:09.230939 ==
3524 11:13:09.231008 DQS Delay:
3525 11:13:09.231071 DQS0 = 0, DQS1 = 0
3526 11:13:09.234355 DQM Delay:
3527 11:13:09.234448 DQM0 = 120, DQM1 = 113
3528 11:13:09.237713 DQ Delay:
3529 11:13:09.241040 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =123
3530 11:13:09.243973 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3531 11:13:09.247578 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3532 11:13:09.250959 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3533 11:13:09.251115
3534 11:13:09.251211
3535 11:13:09.251301 ==
3536 11:13:09.254387 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 11:13:09.257424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 11:13:09.257601 ==
3539 11:13:09.260732
3540 11:13:09.260924
3541 11:13:09.261044 TX Vref Scan disable
3542 11:13:09.263868 == TX Byte 0 ==
3543 11:13:09.267568 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3544 11:13:09.270748 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3545 11:13:09.273968 == TX Byte 1 ==
3546 11:13:09.277403 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3547 11:13:09.280729 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3548 11:13:09.284391 ==
3549 11:13:09.284815 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 11:13:09.290733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 11:13:09.291225 ==
3552 11:13:09.301381 TX Vref=22, minBit 1, minWin=25, winSum=419
3553 11:13:09.305315 TX Vref=24, minBit 1, minWin=25, winSum=421
3554 11:13:09.308246 TX Vref=26, minBit 1, minWin=26, winSum=426
3555 11:13:09.311719 TX Vref=28, minBit 1, minWin=26, winSum=428
3556 11:13:09.314767 TX Vref=30, minBit 1, minWin=26, winSum=428
3557 11:13:09.321766 TX Vref=32, minBit 9, minWin=25, winSum=426
3558 11:13:09.325022 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3559 11:13:09.325554
3560 11:13:09.328030 Final TX Range 1 Vref 28
3561 11:13:09.328450
3562 11:13:09.328814 ==
3563 11:13:09.331190 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 11:13:09.334498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 11:13:09.338210 ==
3566 11:13:09.338730
3567 11:13:09.339062
3568 11:13:09.339366 TX Vref Scan disable
3569 11:13:09.341719 == TX Byte 0 ==
3570 11:13:09.344820 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3571 11:13:09.351725 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3572 11:13:09.352250 == TX Byte 1 ==
3573 11:13:09.355055 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3574 11:13:09.361017 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3575 11:13:09.361439
3576 11:13:09.361764 [DATLAT]
3577 11:13:09.362069 Freq=1200, CH1 RK1
3578 11:13:09.362365
3579 11:13:09.364534 DATLAT Default: 0xd
3580 11:13:09.367617 0, 0xFFFF, sum = 0
3581 11:13:09.368045 1, 0xFFFF, sum = 0
3582 11:13:09.371780 2, 0xFFFF, sum = 0
3583 11:13:09.372303 3, 0xFFFF, sum = 0
3584 11:13:09.374198 4, 0xFFFF, sum = 0
3585 11:13:09.374620 5, 0xFFFF, sum = 0
3586 11:13:09.378152 6, 0xFFFF, sum = 0
3587 11:13:09.378696 7, 0xFFFF, sum = 0
3588 11:13:09.381252 8, 0xFFFF, sum = 0
3589 11:13:09.381847 9, 0xFFFF, sum = 0
3590 11:13:09.384480 10, 0xFFFF, sum = 0
3591 11:13:09.385054 11, 0xFFFF, sum = 0
3592 11:13:09.387660 12, 0x0, sum = 1
3593 11:13:09.388189 13, 0x0, sum = 2
3594 11:13:09.390901 14, 0x0, sum = 3
3595 11:13:09.391427 15, 0x0, sum = 4
3596 11:13:09.393957 best_step = 13
3597 11:13:09.394375
3598 11:13:09.394702 ==
3599 11:13:09.397729 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 11:13:09.400911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 11:13:09.401412 ==
3602 11:13:09.404229 RX Vref Scan: 0
3603 11:13:09.404824
3604 11:13:09.405173 RX Vref 0 -> 0, step: 1
3605 11:13:09.405489
3606 11:13:09.407567 RX Delay -13 -> 252, step: 4
3607 11:13:09.414508 iDelay=195, Bit 0, Center 124 (67 ~ 182) 116
3608 11:13:09.417563 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3609 11:13:09.420724 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3610 11:13:09.424204 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3611 11:13:09.427163 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3612 11:13:09.434022 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3613 11:13:09.437101 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3614 11:13:09.440362 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3615 11:13:09.443699 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3616 11:13:09.446895 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3617 11:13:09.453892 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3618 11:13:09.457174 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3619 11:13:09.460338 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3620 11:13:09.463618 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3621 11:13:09.466861 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3622 11:13:09.473402 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3623 11:13:09.473933 ==
3624 11:13:09.477022 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 11:13:09.480048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 11:13:09.480469 ==
3627 11:13:09.480828 DQS Delay:
3628 11:13:09.483690 DQS0 = 0, DQS1 = 0
3629 11:13:09.484107 DQM Delay:
3630 11:13:09.486807 DQM0 = 119, DQM1 = 113
3631 11:13:09.487269 DQ Delay:
3632 11:13:09.490397 DQ0 =124, DQ1 =114, DQ2 =108, DQ3 =118
3633 11:13:09.493413 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3634 11:13:09.497381 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3635 11:13:09.500258 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3636 11:13:09.503660
3637 11:13:09.504189
3638 11:13:09.510220 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 407 ps
3639 11:13:09.513340 CH1 RK1: MR19=403, MR18=6EA
3640 11:13:09.520081 CH1_RK1: MR19=0x403, MR18=0x6EA, DQSOSC=407, MR23=63, INC=39, DEC=26
3641 11:13:09.523057 [RxdqsGatingPostProcess] freq 1200
3642 11:13:09.526550 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3643 11:13:09.529724 best DQS0 dly(2T, 0.5T) = (0, 11)
3644 11:13:09.532639 best DQS1 dly(2T, 0.5T) = (0, 11)
3645 11:13:09.535993 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3646 11:13:09.539273 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3647 11:13:09.542745 best DQS0 dly(2T, 0.5T) = (0, 11)
3648 11:13:09.546067 best DQS1 dly(2T, 0.5T) = (0, 11)
3649 11:13:09.549365 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3650 11:13:09.552525 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3651 11:13:09.555920 Pre-setting of DQS Precalculation
3652 11:13:09.559138 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3653 11:13:09.565900 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3654 11:13:09.576306 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3655 11:13:09.576621
3656 11:13:09.576873
3657 11:13:09.579191 [Calibration Summary] 2400 Mbps
3658 11:13:09.579436 CH 0, Rank 0
3659 11:13:09.582838 SW Impedance : PASS
3660 11:13:09.583168 DUTY Scan : NO K
3661 11:13:09.585965 ZQ Calibration : PASS
3662 11:13:09.589100 Jitter Meter : NO K
3663 11:13:09.589497 CBT Training : PASS
3664 11:13:09.592590 Write leveling : PASS
3665 11:13:09.595886 RX DQS gating : PASS
3666 11:13:09.596302 RX DQ/DQS(RDDQC) : PASS
3667 11:13:09.599086 TX DQ/DQS : PASS
3668 11:13:09.599583 RX DATLAT : PASS
3669 11:13:09.602300 RX DQ/DQS(Engine): PASS
3670 11:13:09.605601 TX OE : NO K
3671 11:13:09.606020 All Pass.
3672 11:13:09.606350
3673 11:13:09.606654 CH 0, Rank 1
3674 11:13:09.609092 SW Impedance : PASS
3675 11:13:09.612213 DUTY Scan : NO K
3676 11:13:09.612630 ZQ Calibration : PASS
3677 11:13:09.615886 Jitter Meter : NO K
3678 11:13:09.618938 CBT Training : PASS
3679 11:13:09.619353 Write leveling : PASS
3680 11:13:09.622153 RX DQS gating : PASS
3681 11:13:09.625571 RX DQ/DQS(RDDQC) : PASS
3682 11:13:09.625989 TX DQ/DQS : PASS
3683 11:13:09.628964 RX DATLAT : PASS
3684 11:13:09.632317 RX DQ/DQS(Engine): PASS
3685 11:13:09.632735 TX OE : NO K
3686 11:13:09.635797 All Pass.
3687 11:13:09.636317
3688 11:13:09.636648 CH 1, Rank 0
3689 11:13:09.638743 SW Impedance : PASS
3690 11:13:09.639163 DUTY Scan : NO K
3691 11:13:09.642468 ZQ Calibration : PASS
3692 11:13:09.645698 Jitter Meter : NO K
3693 11:13:09.646211 CBT Training : PASS
3694 11:13:09.648411 Write leveling : PASS
3695 11:13:09.651871 RX DQS gating : PASS
3696 11:13:09.652305 RX DQ/DQS(RDDQC) : PASS
3697 11:13:09.655608 TX DQ/DQS : PASS
3698 11:13:09.658893 RX DATLAT : PASS
3699 11:13:09.659322 RX DQ/DQS(Engine): PASS
3700 11:13:09.662346 TX OE : NO K
3701 11:13:09.662780 All Pass.
3702 11:13:09.663213
3703 11:13:09.665127 CH 1, Rank 1
3704 11:13:09.665555 SW Impedance : PASS
3705 11:13:09.668861 DUTY Scan : NO K
3706 11:13:09.671939 ZQ Calibration : PASS
3707 11:13:09.672468 Jitter Meter : NO K
3708 11:13:09.675117 CBT Training : PASS
3709 11:13:09.675549 Write leveling : PASS
3710 11:13:09.678678 RX DQS gating : PASS
3711 11:13:09.681671 RX DQ/DQS(RDDQC) : PASS
3712 11:13:09.682204 TX DQ/DQS : PASS
3713 11:13:09.685361 RX DATLAT : PASS
3714 11:13:09.688367 RX DQ/DQS(Engine): PASS
3715 11:13:09.688813 TX OE : NO K
3716 11:13:09.692033 All Pass.
3717 11:13:09.692567
3718 11:13:09.693048 DramC Write-DBI off
3719 11:13:09.695204 PER_BANK_REFRESH: Hybrid Mode
3720 11:13:09.698200 TX_TRACKING: ON
3721 11:13:09.705027 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3722 11:13:09.708328 [FAST_K] Save calibration result to emmc
3723 11:13:09.711356 dramc_set_vcore_voltage set vcore to 650000
3724 11:13:09.715309 Read voltage for 600, 5
3725 11:13:09.715840 Vio18 = 0
3726 11:13:09.718660 Vcore = 650000
3727 11:13:09.719191 Vdram = 0
3728 11:13:09.719631 Vddq = 0
3729 11:13:09.721743 Vmddr = 0
3730 11:13:09.725024 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3731 11:13:09.731743 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3732 11:13:09.732183 MEM_TYPE=3, freq_sel=19
3733 11:13:09.734714 sv_algorithm_assistance_LP4_1600
3734 11:13:09.741206 ============ PULL DRAM RESETB DOWN ============
3735 11:13:09.744669 ========== PULL DRAM RESETB DOWN end =========
3736 11:13:09.748020 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3737 11:13:09.751377 ===================================
3738 11:13:09.754906 LPDDR4 DRAM CONFIGURATION
3739 11:13:09.757536 ===================================
3740 11:13:09.761532 EX_ROW_EN[0] = 0x0
3741 11:13:09.762066 EX_ROW_EN[1] = 0x0
3742 11:13:09.764755 LP4Y_EN = 0x0
3743 11:13:09.765335 WORK_FSP = 0x0
3744 11:13:09.767985 WL = 0x2
3745 11:13:09.768516 RL = 0x2
3746 11:13:09.771116 BL = 0x2
3747 11:13:09.771644 RPST = 0x0
3748 11:13:09.774153 RD_PRE = 0x0
3749 11:13:09.774683 WR_PRE = 0x1
3750 11:13:09.777541 WR_PST = 0x0
3751 11:13:09.777972 DBI_WR = 0x0
3752 11:13:09.781033 DBI_RD = 0x0
3753 11:13:09.781566 OTF = 0x1
3754 11:13:09.784397 ===================================
3755 11:13:09.787486 ===================================
3756 11:13:09.790840 ANA top config
3757 11:13:09.794190 ===================================
3758 11:13:09.797329 DLL_ASYNC_EN = 0
3759 11:13:09.797864 ALL_SLAVE_EN = 1
3760 11:13:09.800627 NEW_RANK_MODE = 1
3761 11:13:09.804163 DLL_IDLE_MODE = 1
3762 11:13:09.807405 LP45_APHY_COMB_EN = 1
3763 11:13:09.810611 TX_ODT_DIS = 1
3764 11:13:09.811050 NEW_8X_MODE = 1
3765 11:13:09.813838 ===================================
3766 11:13:09.817299 ===================================
3767 11:13:09.820526 data_rate = 1200
3768 11:13:09.823895 CKR = 1
3769 11:13:09.827053 DQ_P2S_RATIO = 8
3770 11:13:09.830340 ===================================
3771 11:13:09.833439 CA_P2S_RATIO = 8
3772 11:13:09.836920 DQ_CA_OPEN = 0
3773 11:13:09.837450 DQ_SEMI_OPEN = 0
3774 11:13:09.840501 CA_SEMI_OPEN = 0
3775 11:13:09.843409 CA_FULL_RATE = 0
3776 11:13:09.846647 DQ_CKDIV4_EN = 1
3777 11:13:09.849909 CA_CKDIV4_EN = 1
3778 11:13:09.853284 CA_PREDIV_EN = 0
3779 11:13:09.856381 PH8_DLY = 0
3780 11:13:09.856968 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3781 11:13:09.859805 DQ_AAMCK_DIV = 4
3782 11:13:09.863300 CA_AAMCK_DIV = 4
3783 11:13:09.866920 CA_ADMCK_DIV = 4
3784 11:13:09.869548 DQ_TRACK_CA_EN = 0
3785 11:13:09.873207 CA_PICK = 600
3786 11:13:09.876239 CA_MCKIO = 600
3787 11:13:09.876800 MCKIO_SEMI = 0
3788 11:13:09.879968 PLL_FREQ = 2288
3789 11:13:09.882986 DQ_UI_PI_RATIO = 32
3790 11:13:09.886208 CA_UI_PI_RATIO = 0
3791 11:13:09.889235 ===================================
3792 11:13:09.892597 ===================================
3793 11:13:09.896011 memory_type:LPDDR4
3794 11:13:09.896539 GP_NUM : 10
3795 11:13:09.899111 SRAM_EN : 1
3796 11:13:09.902599 MD32_EN : 0
3797 11:13:09.905943 ===================================
3798 11:13:09.906478 [ANA_INIT] >>>>>>>>>>>>>>
3799 11:13:09.909366 <<<<<< [CONFIGURE PHASE]: ANA_TX
3800 11:13:09.912469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3801 11:13:09.916046 ===================================
3802 11:13:09.919213 data_rate = 1200,PCW = 0X5800
3803 11:13:09.922426 ===================================
3804 11:13:09.925637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3805 11:13:09.932346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3806 11:13:09.935324 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3807 11:13:09.941931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3808 11:13:09.945333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3809 11:13:09.948461 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3810 11:13:09.952259 [ANA_INIT] flow start
3811 11:13:09.952821 [ANA_INIT] PLL >>>>>>>>
3812 11:13:09.955141 [ANA_INIT] PLL <<<<<<<<
3813 11:13:09.958669 [ANA_INIT] MIDPI >>>>>>>>
3814 11:13:09.959202 [ANA_INIT] MIDPI <<<<<<<<
3815 11:13:09.961992 [ANA_INIT] DLL >>>>>>>>
3816 11:13:09.965057 [ANA_INIT] flow end
3817 11:13:09.968788 ============ LP4 DIFF to SE enter ============
3818 11:13:09.972198 ============ LP4 DIFF to SE exit ============
3819 11:13:09.975184 [ANA_INIT] <<<<<<<<<<<<<
3820 11:13:09.978779 [Flow] Enable top DCM control >>>>>
3821 11:13:09.981870 [Flow] Enable top DCM control <<<<<
3822 11:13:09.984893 Enable DLL master slave shuffle
3823 11:13:09.988111 ==============================================================
3824 11:13:09.991460 Gating Mode config
3825 11:13:09.998168 ==============================================================
3826 11:13:09.998606 Config description:
3827 11:13:10.008194 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3828 11:13:10.014570 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3829 11:13:10.017881 SELPH_MODE 0: By rank 1: By Phase
3830 11:13:10.024953 ==============================================================
3831 11:13:10.028146 GAT_TRACK_EN = 1
3832 11:13:10.031312 RX_GATING_MODE = 2
3833 11:13:10.034642 RX_GATING_TRACK_MODE = 2
3834 11:13:10.037906 SELPH_MODE = 1
3835 11:13:10.041020 PICG_EARLY_EN = 1
3836 11:13:10.044382 VALID_LAT_VALUE = 1
3837 11:13:10.047555 ==============================================================
3838 11:13:10.051304 Enter into Gating configuration >>>>
3839 11:13:10.054381 Exit from Gating configuration <<<<
3840 11:13:10.057478 Enter into DVFS_PRE_config >>>>>
3841 11:13:10.070972 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3842 11:13:10.071401 Exit from DVFS_PRE_config <<<<<
3843 11:13:10.073988 Enter into PICG configuration >>>>
3844 11:13:10.077537 Exit from PICG configuration <<<<
3845 11:13:10.080975 [RX_INPUT] configuration >>>>>
3846 11:13:10.084320 [RX_INPUT] configuration <<<<<
3847 11:13:10.090964 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3848 11:13:10.094181 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3849 11:13:10.100408 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 11:13:10.107109 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 11:13:10.113732 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3852 11:13:10.120376 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3853 11:13:10.123413 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3854 11:13:10.126657 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3855 11:13:10.130334 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3856 11:13:10.136927 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3857 11:13:10.140198 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3858 11:13:10.143287 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3859 11:13:10.146580 ===================================
3860 11:13:10.149829 LPDDR4 DRAM CONFIGURATION
3861 11:13:10.153292 ===================================
3862 11:13:10.156469 EX_ROW_EN[0] = 0x0
3863 11:13:10.156843 EX_ROW_EN[1] = 0x0
3864 11:13:10.159648 LP4Y_EN = 0x0
3865 11:13:10.160046 WORK_FSP = 0x0
3866 11:13:10.163206 WL = 0x2
3867 11:13:10.163607 RL = 0x2
3868 11:13:10.166677 BL = 0x2
3869 11:13:10.167089 RPST = 0x0
3870 11:13:10.169907 RD_PRE = 0x0
3871 11:13:10.170210 WR_PRE = 0x1
3872 11:13:10.172928 WR_PST = 0x0
3873 11:13:10.173330 DBI_WR = 0x0
3874 11:13:10.176312 DBI_RD = 0x0
3875 11:13:10.176618 OTF = 0x1
3876 11:13:10.179568 ===================================
3877 11:13:10.186289 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3878 11:13:10.189611 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3879 11:13:10.192978 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3880 11:13:10.196148 ===================================
3881 11:13:10.199462 LPDDR4 DRAM CONFIGURATION
3882 11:13:10.203113 ===================================
3883 11:13:10.206199 EX_ROW_EN[0] = 0x10
3884 11:13:10.206503 EX_ROW_EN[1] = 0x0
3885 11:13:10.209525 LP4Y_EN = 0x0
3886 11:13:10.209827 WORK_FSP = 0x0
3887 11:13:10.212795 WL = 0x2
3888 11:13:10.213103 RL = 0x2
3889 11:13:10.216339 BL = 0x2
3890 11:13:10.216643 RPST = 0x0
3891 11:13:10.219450 RD_PRE = 0x0
3892 11:13:10.219750 WR_PRE = 0x1
3893 11:13:10.222643 WR_PST = 0x0
3894 11:13:10.222944 DBI_WR = 0x0
3895 11:13:10.225908 DBI_RD = 0x0
3896 11:13:10.226211 OTF = 0x1
3897 11:13:10.229220 ===================================
3898 11:13:10.235672 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3899 11:13:10.240868 nWR fixed to 30
3900 11:13:10.244123 [ModeRegInit_LP4] CH0 RK0
3901 11:13:10.244425 [ModeRegInit_LP4] CH0 RK1
3902 11:13:10.247340 [ModeRegInit_LP4] CH1 RK0
3903 11:13:10.250638 [ModeRegInit_LP4] CH1 RK1
3904 11:13:10.250945 match AC timing 17
3905 11:13:10.257482 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3906 11:13:10.260823 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3907 11:13:10.264012 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3908 11:13:10.270351 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3909 11:13:10.273725 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3910 11:13:10.274026 ==
3911 11:13:10.277549 Dram Type= 6, Freq= 0, CH_0, rank 0
3912 11:13:10.280516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3913 11:13:10.280844 ==
3914 11:13:10.287297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3915 11:13:10.294165 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3916 11:13:10.296942 [CA 0] Center 36 (6~67) winsize 62
3917 11:13:10.300290 [CA 1] Center 36 (6~67) winsize 62
3918 11:13:10.303772 [CA 2] Center 34 (4~65) winsize 62
3919 11:13:10.306992 [CA 3] Center 34 (3~65) winsize 63
3920 11:13:10.309973 [CA 4] Center 33 (3~64) winsize 62
3921 11:13:10.313528 [CA 5] Center 33 (3~64) winsize 62
3922 11:13:10.313610
3923 11:13:10.317110 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3924 11:13:10.317193
3925 11:13:10.320184 [CATrainingPosCal] consider 1 rank data
3926 11:13:10.323543 u2DelayCellTimex100 = 270/100 ps
3927 11:13:10.327108 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3928 11:13:10.330419 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3929 11:13:10.333309 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3930 11:13:10.336716 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3931 11:13:10.343395 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3932 11:13:10.346688 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3933 11:13:10.346771
3934 11:13:10.349895 CA PerBit enable=1, Macro0, CA PI delay=33
3935 11:13:10.349978
3936 11:13:10.353483 [CBTSetCACLKResult] CA Dly = 33
3937 11:13:10.353647 CS Dly: 4 (0~35)
3938 11:13:10.353728 ==
3939 11:13:10.356688 Dram Type= 6, Freq= 0, CH_0, rank 1
3940 11:13:10.363161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 11:13:10.363339 ==
3942 11:13:10.366516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3943 11:13:10.373309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3944 11:13:10.376313 [CA 0] Center 36 (6~67) winsize 62
3945 11:13:10.379850 [CA 1] Center 36 (6~67) winsize 62
3946 11:13:10.383104 [CA 2] Center 34 (4~65) winsize 62
3947 11:13:10.386537 [CA 3] Center 34 (4~65) winsize 62
3948 11:13:10.389791 [CA 4] Center 34 (3~65) winsize 63
3949 11:13:10.393313 [CA 5] Center 33 (3~64) winsize 62
3950 11:13:10.393618
3951 11:13:10.396488 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3952 11:13:10.396750
3953 11:13:10.399672 [CATrainingPosCal] consider 2 rank data
3954 11:13:10.403263 u2DelayCellTimex100 = 270/100 ps
3955 11:13:10.406369 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3956 11:13:10.413073 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3957 11:13:10.416650 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3958 11:13:10.419886 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3959 11:13:10.423109 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3960 11:13:10.426097 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 11:13:10.426523
3962 11:13:10.429835 CA PerBit enable=1, Macro0, CA PI delay=33
3963 11:13:10.430254
3964 11:13:10.433052 [CBTSetCACLKResult] CA Dly = 33
3965 11:13:10.433469 CS Dly: 5 (0~37)
3966 11:13:10.436233
3967 11:13:10.439758 ----->DramcWriteLeveling(PI) begin...
3968 11:13:10.440291 ==
3969 11:13:10.443003 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 11:13:10.445860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 11:13:10.445942 ==
3972 11:13:10.449028 Write leveling (Byte 0): 34 => 34
3973 11:13:10.452376 Write leveling (Byte 1): 30 => 30
3974 11:13:10.455607 DramcWriteLeveling(PI) end<-----
3975 11:13:10.455689
3976 11:13:10.455754 ==
3977 11:13:10.458946 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 11:13:10.462235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 11:13:10.462317 ==
3980 11:13:10.465631 [Gating] SW mode calibration
3981 11:13:10.471978 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3982 11:13:10.479071 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3983 11:13:10.482158 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 11:13:10.485469 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 11:13:10.491941 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 11:13:10.495338 0 9 12 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (1 0)
3987 11:13:10.498807 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
3988 11:13:10.505189 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 11:13:10.508458 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 11:13:10.512100 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 11:13:10.518436 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 11:13:10.521726 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 11:13:10.525031 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 11:13:10.531839 0 10 12 | B1->B0 | 2a2a 4242 | 0 0 | (0 0) (1 1)
3995 11:13:10.535342 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3996 11:13:10.538619 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 11:13:10.545268 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 11:13:10.548675 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 11:13:10.551718 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 11:13:10.558384 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 11:13:10.561266 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 11:13:10.565362 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4003 11:13:10.571588 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:13:10.575367 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:13:10.577762 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:13:10.584616 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:13:10.587882 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:13:10.591389 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:13:10.597619 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:13:10.600959 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:13:10.604109 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:13:10.611156 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:13:10.614043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 11:13:10.617347 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 11:13:10.624357 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 11:13:10.627543 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 11:13:10.630809 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 11:13:10.637376 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4019 11:13:10.640702 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 11:13:10.644258 Total UI for P1: 0, mck2ui 16
4021 11:13:10.647226 best dqsien dly found for B0: ( 0, 13, 12)
4022 11:13:10.650485 Total UI for P1: 0, mck2ui 16
4023 11:13:10.653797 best dqsien dly found for B1: ( 0, 13, 12)
4024 11:13:10.657054 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4025 11:13:10.660582 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4026 11:13:10.661155
4027 11:13:10.663795 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4028 11:13:10.667105 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4029 11:13:10.670164 [Gating] SW calibration Done
4030 11:13:10.670594 ==
4031 11:13:10.673483 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 11:13:10.680405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 11:13:10.680974 ==
4034 11:13:10.681323 RX Vref Scan: 0
4035 11:13:10.681641
4036 11:13:10.683439 RX Vref 0 -> 0, step: 1
4037 11:13:10.683960
4038 11:13:10.686774 RX Delay -230 -> 252, step: 16
4039 11:13:10.690011 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4040 11:13:10.693423 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4041 11:13:10.696660 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4042 11:13:10.703458 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4043 11:13:10.706343 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4044 11:13:10.709684 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4045 11:13:10.713345 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4046 11:13:10.719864 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4047 11:13:10.722516 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4048 11:13:10.726094 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4049 11:13:10.729459 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4050 11:13:10.736098 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4051 11:13:10.739613 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4052 11:13:10.742742 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4053 11:13:10.745714 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4054 11:13:10.752325 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4055 11:13:10.752863 ==
4056 11:13:10.755767 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 11:13:10.759281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 11:13:10.759811 ==
4059 11:13:10.760165 DQS Delay:
4060 11:13:10.762153 DQS0 = 0, DQS1 = 0
4061 11:13:10.762595 DQM Delay:
4062 11:13:10.765938 DQM0 = 51, DQM1 = 40
4063 11:13:10.766452 DQ Delay:
4064 11:13:10.769132 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4065 11:13:10.772661 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4066 11:13:10.775838 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4067 11:13:10.779022 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4068 11:13:10.779542
4069 11:13:10.779880
4070 11:13:10.780186 ==
4071 11:13:10.782412 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 11:13:10.785687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 11:13:10.789139 ==
4074 11:13:10.789665
4075 11:13:10.790002
4076 11:13:10.790308 TX Vref Scan disable
4077 11:13:10.792543 == TX Byte 0 ==
4078 11:13:10.795438 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4079 11:13:10.799051 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4080 11:13:10.802095 == TX Byte 1 ==
4081 11:13:10.805219 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4082 11:13:10.809035 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4083 11:13:10.812566 ==
4084 11:13:10.815642 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 11:13:10.818972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 11:13:10.819499 ==
4087 11:13:10.819837
4088 11:13:10.820145
4089 11:13:10.822138 TX Vref Scan disable
4090 11:13:10.825358 == TX Byte 0 ==
4091 11:13:10.828759 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4092 11:13:10.831891 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4093 11:13:10.835156 == TX Byte 1 ==
4094 11:13:10.838434 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4095 11:13:10.841404 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4096 11:13:10.841826
4097 11:13:10.842162 [DATLAT]
4098 11:13:10.844877 Freq=600, CH0 RK0
4099 11:13:10.845440
4100 11:13:10.848177 DATLAT Default: 0x9
4101 11:13:10.848599 0, 0xFFFF, sum = 0
4102 11:13:10.851422 1, 0xFFFF, sum = 0
4103 11:13:10.851883 2, 0xFFFF, sum = 0
4104 11:13:10.854573 3, 0xFFFF, sum = 0
4105 11:13:10.855058 4, 0xFFFF, sum = 0
4106 11:13:10.858496 5, 0xFFFF, sum = 0
4107 11:13:10.859024 6, 0xFFFF, sum = 0
4108 11:13:10.861429 7, 0xFFFF, sum = 0
4109 11:13:10.861948 8, 0x0, sum = 1
4110 11:13:10.864465 9, 0x0, sum = 2
4111 11:13:10.864963 10, 0x0, sum = 3
4112 11:13:10.867826 11, 0x0, sum = 4
4113 11:13:10.868264 best_step = 9
4114 11:13:10.868661
4115 11:13:10.869027 ==
4116 11:13:10.871009 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 11:13:10.874787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 11:13:10.875208 ==
4119 11:13:10.878116 RX Vref Scan: 1
4120 11:13:10.878533
4121 11:13:10.881264 RX Vref 0 -> 0, step: 1
4122 11:13:10.881687
4123 11:13:10.882023 RX Delay -179 -> 252, step: 8
4124 11:13:10.882404
4125 11:13:10.884644 Set Vref, RX VrefLevel [Byte0]: 57
4126 11:13:10.887796 [Byte1]: 48
4127 11:13:10.891777
4128 11:13:10.891883 Final RX Vref Byte 0 = 57 to rank0
4129 11:13:10.895362 Final RX Vref Byte 1 = 48 to rank0
4130 11:13:10.898294 Final RX Vref Byte 0 = 57 to rank1
4131 11:13:10.902111 Final RX Vref Byte 1 = 48 to rank1==
4132 11:13:10.905494 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 11:13:10.911653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 11:13:10.911748 ==
4135 11:13:10.911823 DQS Delay:
4136 11:13:10.915429 DQS0 = 0, DQS1 = 0
4137 11:13:10.915531 DQM Delay:
4138 11:13:10.915613 DQM0 = 51, DQM1 = 37
4139 11:13:10.918772 DQ Delay:
4140 11:13:10.921726 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =48
4141 11:13:10.924949 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =60
4142 11:13:10.928518 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4143 11:13:10.931420 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4144 11:13:10.931514
4145 11:13:10.931589
4146 11:13:10.938282 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f59, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
4147 11:13:10.942131 CH0 RK0: MR19=808, MR18=5F59
4148 11:13:10.948128 CH0_RK0: MR19=0x808, MR18=0x5F59, DQSOSC=391, MR23=63, INC=171, DEC=114
4149 11:13:10.948331
4150 11:13:10.951542 ----->DramcWriteLeveling(PI) begin...
4151 11:13:10.951711 ==
4152 11:13:10.954630 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 11:13:10.958097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 11:13:10.958276 ==
4155 11:13:10.961403 Write leveling (Byte 0): 33 => 33
4156 11:13:10.964730 Write leveling (Byte 1): 32 => 32
4157 11:13:10.967969 DramcWriteLeveling(PI) end<-----
4158 11:13:10.968169
4159 11:13:10.968329 ==
4160 11:13:10.971280 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 11:13:10.974927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 11:13:10.978255 ==
4163 11:13:10.978604 [Gating] SW mode calibration
4164 11:13:10.988398 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4165 11:13:10.991732 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4166 11:13:10.994890 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 11:13:11.001302 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 11:13:11.004390 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 11:13:11.008194 0 9 12 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
4170 11:13:11.014419 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4171 11:13:11.017789 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 11:13:11.021709 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 11:13:11.028060 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 11:13:11.031239 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 11:13:11.034356 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 11:13:11.040958 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 11:13:11.044265 0 10 12 | B1->B0 | 2c2c 3232 | 1 0 | (0 0) (0 0)
4178 11:13:11.047536 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 11:13:11.054060 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 11:13:11.057223 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 11:13:11.060706 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 11:13:11.067311 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 11:13:11.070558 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 11:13:11.074029 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 11:13:11.080256 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 11:13:11.083354 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:13:11.087198 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:13:11.093522 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:13:11.096934 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:13:11.100196 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:13:11.107046 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:13:11.110267 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:13:11.113482 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:13:11.120197 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 11:13:11.123217 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 11:13:11.126543 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 11:13:11.133473 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 11:13:11.136511 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 11:13:11.139656 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 11:13:11.146286 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 11:13:11.149330 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4202 11:13:11.152589 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 11:13:11.155832 Total UI for P1: 0, mck2ui 16
4204 11:13:11.159086 best dqsien dly found for B0: ( 0, 13, 12)
4205 11:13:11.162822 Total UI for P1: 0, mck2ui 16
4206 11:13:11.166135 best dqsien dly found for B1: ( 0, 13, 14)
4207 11:13:11.169270 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4208 11:13:11.176282 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4209 11:13:11.176847
4210 11:13:11.179082 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4211 11:13:11.182785 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4212 11:13:11.186313 [Gating] SW calibration Done
4213 11:13:11.186875 ==
4214 11:13:11.189614 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 11:13:11.192497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 11:13:11.193067 ==
4217 11:13:11.196001 RX Vref Scan: 0
4218 11:13:11.196519
4219 11:13:11.196902 RX Vref 0 -> 0, step: 1
4220 11:13:11.197224
4221 11:13:11.199402 RX Delay -230 -> 252, step: 16
4222 11:13:11.202416 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4223 11:13:11.209005 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4224 11:13:11.212111 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4225 11:13:11.215079 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4226 11:13:11.218893 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4227 11:13:11.224933 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4228 11:13:11.228899 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4229 11:13:11.232005 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4230 11:13:11.235450 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4231 11:13:11.241787 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4232 11:13:11.245184 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4233 11:13:11.248515 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4234 11:13:11.251946 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4235 11:13:11.258154 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4236 11:13:11.261492 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4237 11:13:11.264949 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4238 11:13:11.265450 ==
4239 11:13:11.268362 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 11:13:11.271745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 11:13:11.272268 ==
4242 11:13:11.274850 DQS Delay:
4243 11:13:11.275393 DQS0 = 0, DQS1 = 0
4244 11:13:11.278133 DQM Delay:
4245 11:13:11.278552 DQM0 = 48, DQM1 = 40
4246 11:13:11.278884 DQ Delay:
4247 11:13:11.281431 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =49
4248 11:13:11.284888 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4249 11:13:11.288355 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4250 11:13:11.291074 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4251 11:13:11.291498
4252 11:13:11.291828
4253 11:13:11.294890 ==
4254 11:13:11.298022 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 11:13:11.301590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 11:13:11.302121 ==
4257 11:13:11.302459
4258 11:13:11.302770
4259 11:13:11.304833 TX Vref Scan disable
4260 11:13:11.305353 == TX Byte 0 ==
4261 11:13:11.311347 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4262 11:13:11.314288 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4263 11:13:11.314717 == TX Byte 1 ==
4264 11:13:11.321345 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4265 11:13:11.324413 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4266 11:13:11.324996 ==
4267 11:13:11.327685 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 11:13:11.330521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 11:13:11.330953 ==
4270 11:13:11.331283
4271 11:13:11.331586
4272 11:13:11.334224 TX Vref Scan disable
4273 11:13:11.337690 == TX Byte 0 ==
4274 11:13:11.340655 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4275 11:13:11.344283 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4276 11:13:11.347443 == TX Byte 1 ==
4277 11:13:11.350737 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4278 11:13:11.353786 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4279 11:13:11.357090
4280 11:13:11.357604 [DATLAT]
4281 11:13:11.357936 Freq=600, CH0 RK1
4282 11:13:11.358248
4283 11:13:11.360560 DATLAT Default: 0x9
4284 11:13:11.361126 0, 0xFFFF, sum = 0
4285 11:13:11.363774 1, 0xFFFF, sum = 0
4286 11:13:11.364299 2, 0xFFFF, sum = 0
4287 11:13:11.367068 3, 0xFFFF, sum = 0
4288 11:13:11.370257 4, 0xFFFF, sum = 0
4289 11:13:11.370795 5, 0xFFFF, sum = 0
4290 11:13:11.373351 6, 0xFFFF, sum = 0
4291 11:13:11.373793 7, 0xFFFF, sum = 0
4292 11:13:11.376979 8, 0x0, sum = 1
4293 11:13:11.377482 9, 0x0, sum = 2
4294 11:13:11.377827 10, 0x0, sum = 3
4295 11:13:11.380040 11, 0x0, sum = 4
4296 11:13:11.380291 best_step = 9
4297 11:13:11.380412
4298 11:13:11.380484 ==
4299 11:13:11.383013 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 11:13:11.389443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 11:13:11.389553 ==
4302 11:13:11.389645 RX Vref Scan: 0
4303 11:13:11.389734
4304 11:13:11.392724 RX Vref 0 -> 0, step: 1
4305 11:13:11.392815
4306 11:13:11.396076 RX Delay -179 -> 252, step: 8
4307 11:13:11.399698 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4308 11:13:11.406365 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4309 11:13:11.409556 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4310 11:13:11.413152 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4311 11:13:11.416159 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4312 11:13:11.422801 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4313 11:13:11.426034 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4314 11:13:11.429383 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4315 11:13:11.432527 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4316 11:13:11.435637 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4317 11:13:11.442610 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4318 11:13:11.446113 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4319 11:13:11.448975 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4320 11:13:11.452644 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4321 11:13:11.459315 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4322 11:13:11.462249 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4323 11:13:11.462591 ==
4324 11:13:11.465525 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 11:13:11.469189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 11:13:11.469697 ==
4327 11:13:11.472514 DQS Delay:
4328 11:13:11.473069 DQS0 = 0, DQS1 = 0
4329 11:13:11.473397 DQM Delay:
4330 11:13:11.475407 DQM0 = 48, DQM1 = 42
4331 11:13:11.475923 DQ Delay:
4332 11:13:11.478857 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4333 11:13:11.482321 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =52
4334 11:13:11.485365 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4335 11:13:11.488534 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =48
4336 11:13:11.489042
4337 11:13:11.489370
4338 11:13:11.498983 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4339 11:13:11.501942 CH0 RK1: MR19=808, MR18=5F2D
4340 11:13:11.505257 CH0_RK1: MR19=0x808, MR18=0x5F2D, DQSOSC=391, MR23=63, INC=171, DEC=114
4341 11:13:11.508370 [RxdqsGatingPostProcess] freq 600
4342 11:13:11.515274 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4343 11:13:11.518401 Pre-setting of DQS Precalculation
4344 11:13:11.521873 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4345 11:13:11.522402 ==
4346 11:13:11.524929 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 11:13:11.531710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 11:13:11.532120 ==
4349 11:13:11.534856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 11:13:11.541681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4351 11:13:11.545298 [CA 0] Center 35 (5~66) winsize 62
4352 11:13:11.548440 [CA 1] Center 35 (5~66) winsize 62
4353 11:13:11.551928 [CA 2] Center 34 (4~65) winsize 62
4354 11:13:11.555215 [CA 3] Center 34 (3~65) winsize 63
4355 11:13:11.558097 [CA 4] Center 34 (4~65) winsize 62
4356 11:13:11.561567 [CA 5] Center 34 (3~65) winsize 63
4357 11:13:11.561975
4358 11:13:11.565031 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4359 11:13:11.565597
4360 11:13:11.568341 [CATrainingPosCal] consider 1 rank data
4361 11:13:11.571292 u2DelayCellTimex100 = 270/100 ps
4362 11:13:11.574872 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4363 11:13:11.578083 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4364 11:13:11.584875 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4365 11:13:11.588327 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4366 11:13:11.591369 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4367 11:13:11.594649 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4368 11:13:11.595086
4369 11:13:11.597709 CA PerBit enable=1, Macro0, CA PI delay=34
4370 11:13:11.598133
4371 11:13:11.601405 [CBTSetCACLKResult] CA Dly = 34
4372 11:13:11.601922 CS Dly: 4 (0~35)
4373 11:13:11.604910 ==
4374 11:13:11.607861 Dram Type= 6, Freq= 0, CH_1, rank 1
4375 11:13:11.611373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 11:13:11.611899 ==
4377 11:13:11.614702 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4378 11:13:11.621180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4379 11:13:11.625176 [CA 0] Center 36 (6~66) winsize 61
4380 11:13:11.628585 [CA 1] Center 36 (5~67) winsize 63
4381 11:13:11.631601 [CA 2] Center 34 (4~65) winsize 62
4382 11:13:11.634837 [CA 3] Center 34 (4~65) winsize 62
4383 11:13:11.638189 [CA 4] Center 34 (4~65) winsize 62
4384 11:13:11.641302 [CA 5] Center 34 (4~65) winsize 62
4385 11:13:11.641710
4386 11:13:11.645145 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4387 11:13:11.645654
4388 11:13:11.648652 [CATrainingPosCal] consider 2 rank data
4389 11:13:11.651550 u2DelayCellTimex100 = 270/100 ps
4390 11:13:11.654723 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4391 11:13:11.661195 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4392 11:13:11.664405 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4393 11:13:11.667612 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4394 11:13:11.671509 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4395 11:13:11.674542 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4396 11:13:11.674965
4397 11:13:11.678026 CA PerBit enable=1, Macro0, CA PI delay=34
4398 11:13:11.678448
4399 11:13:11.681275 [CBTSetCACLKResult] CA Dly = 34
4400 11:13:11.684477 CS Dly: 4 (0~36)
4401 11:13:11.684927
4402 11:13:11.687741 ----->DramcWriteLeveling(PI) begin...
4403 11:13:11.688167 ==
4404 11:13:11.691054 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 11:13:11.694045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 11:13:11.694466 ==
4407 11:13:11.697568 Write leveling (Byte 0): 29 => 29
4408 11:13:11.700863 Write leveling (Byte 1): 29 => 29
4409 11:13:11.704144 DramcWriteLeveling(PI) end<-----
4410 11:13:11.704566
4411 11:13:11.704928 ==
4412 11:13:11.707602 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 11:13:11.710592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 11:13:11.711017 ==
4415 11:13:11.714217 [Gating] SW mode calibration
4416 11:13:11.720832 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4417 11:13:11.727148 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4418 11:13:11.730746 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 11:13:11.733919 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 11:13:11.740491 0 9 8 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
4421 11:13:11.743760 0 9 12 | B1->B0 | 2f2f 2727 | 1 1 | (1 1) (1 0)
4422 11:13:11.747231 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 11:13:11.753525 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 11:13:11.756818 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 11:13:11.760449 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 11:13:11.767124 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 11:13:11.770224 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 11:13:11.773560 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4429 11:13:11.780172 0 10 12 | B1->B0 | 3d3d 3d3d | 0 0 | (0 0) (0 0)
4430 11:13:11.783409 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 11:13:11.787540 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 11:13:11.793686 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 11:13:11.796883 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 11:13:11.800140 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 11:13:11.806541 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 11:13:11.810184 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 11:13:11.813439 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4438 11:13:11.819787 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:13:11.822962 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:13:11.826378 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:13:11.832919 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:13:11.836508 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:13:11.839876 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:13:11.846296 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:13:11.849382 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:13:11.852872 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:13:11.859357 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 11:13:11.862801 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 11:13:11.866075 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 11:13:11.872725 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 11:13:11.876166 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 11:13:11.879353 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 11:13:11.886096 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4454 11:13:11.889314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 11:13:11.892627 Total UI for P1: 0, mck2ui 16
4456 11:13:11.895815 best dqsien dly found for B0: ( 0, 13, 12)
4457 11:13:11.899170 Total UI for P1: 0, mck2ui 16
4458 11:13:11.902474 best dqsien dly found for B1: ( 0, 13, 14)
4459 11:13:11.905710 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4460 11:13:11.909317 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4461 11:13:11.909851
4462 11:13:11.912296 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4463 11:13:11.915823 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4464 11:13:11.919092 [Gating] SW calibration Done
4465 11:13:11.919546 ==
4466 11:13:11.922346 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 11:13:11.925511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 11:13:11.929167 ==
4469 11:13:11.929711 RX Vref Scan: 0
4470 11:13:11.930056
4471 11:13:11.932185 RX Vref 0 -> 0, step: 1
4472 11:13:11.932636
4473 11:13:11.935736 RX Delay -230 -> 252, step: 16
4474 11:13:11.939210 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4475 11:13:11.942185 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4476 11:13:11.945433 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4477 11:13:11.951935 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4478 11:13:11.955080 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4479 11:13:11.958818 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4480 11:13:11.961944 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4481 11:13:11.965167 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4482 11:13:11.972055 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4483 11:13:11.975131 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4484 11:13:11.978575 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4485 11:13:11.981753 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4486 11:13:11.988375 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4487 11:13:11.991564 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4488 11:13:11.994830 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4489 11:13:11.998286 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4490 11:13:11.998877 ==
4491 11:13:12.001563 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 11:13:12.008346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 11:13:12.009027 ==
4494 11:13:12.009379 DQS Delay:
4495 11:13:12.011588 DQS0 = 0, DQS1 = 0
4496 11:13:12.012264 DQM Delay:
4497 11:13:12.012834 DQM0 = 53, DQM1 = 42
4498 11:13:12.014631 DQ Delay:
4499 11:13:12.018083 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4500 11:13:12.021364 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49
4501 11:13:12.024492 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4502 11:13:12.027963 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4503 11:13:12.028503
4504 11:13:12.028888
4505 11:13:12.029208 ==
4506 11:13:12.031045 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 11:13:12.034898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 11:13:12.035314 ==
4509 11:13:12.035682
4510 11:13:12.036004
4511 11:13:12.038227 TX Vref Scan disable
4512 11:13:12.041076 == TX Byte 0 ==
4513 11:13:12.044691 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4514 11:13:12.048207 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4515 11:13:12.051336 == TX Byte 1 ==
4516 11:13:12.054520 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4517 11:13:12.057667 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4518 11:13:12.058110 ==
4519 11:13:12.061099 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 11:13:12.064738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 11:13:12.067832 ==
4522 11:13:12.068358
4523 11:13:12.068858
4524 11:13:12.069183 TX Vref Scan disable
4525 11:13:12.071516 == TX Byte 0 ==
4526 11:13:12.074934 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4527 11:13:12.081313 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4528 11:13:12.081814 == TX Byte 1 ==
4529 11:13:12.084691 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4530 11:13:12.091532 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4531 11:13:12.092033
4532 11:13:12.092466 [DATLAT]
4533 11:13:12.092993 Freq=600, CH1 RK0
4534 11:13:12.093394
4535 11:13:12.094536 DATLAT Default: 0x9
4536 11:13:12.095039 0, 0xFFFF, sum = 0
4537 11:13:12.097882 1, 0xFFFF, sum = 0
4538 11:13:12.101159 2, 0xFFFF, sum = 0
4539 11:13:12.101593 3, 0xFFFF, sum = 0
4540 11:13:12.104451 4, 0xFFFF, sum = 0
4541 11:13:12.104936 5, 0xFFFF, sum = 0
4542 11:13:12.107815 6, 0xFFFF, sum = 0
4543 11:13:12.108249 7, 0xFFFF, sum = 0
4544 11:13:12.110665 8, 0x0, sum = 1
4545 11:13:12.111139 9, 0x0, sum = 2
4546 11:13:12.114207 10, 0x0, sum = 3
4547 11:13:12.114641 11, 0x0, sum = 4
4548 11:13:12.115079 best_step = 9
4549 11:13:12.115481
4550 11:13:12.117666 ==
4551 11:13:12.118093 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 11:13:12.123942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 11:13:12.124374 ==
4554 11:13:12.124852 RX Vref Scan: 1
4555 11:13:12.125263
4556 11:13:12.127277 RX Vref 0 -> 0, step: 1
4557 11:13:12.127705
4558 11:13:12.130730 RX Delay -179 -> 252, step: 8
4559 11:13:12.131157
4560 11:13:12.134126 Set Vref, RX VrefLevel [Byte0]: 51
4561 11:13:12.137126 [Byte1]: 53
4562 11:13:12.137597
4563 11:13:12.140674 Final RX Vref Byte 0 = 51 to rank0
4564 11:13:12.143656 Final RX Vref Byte 1 = 53 to rank0
4565 11:13:12.147189 Final RX Vref Byte 0 = 51 to rank1
4566 11:13:12.150538 Final RX Vref Byte 1 = 53 to rank1==
4567 11:13:12.153642 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 11:13:12.157011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 11:13:12.160183 ==
4570 11:13:12.160293 DQS Delay:
4571 11:13:12.160393 DQS0 = 0, DQS1 = 0
4572 11:13:12.163428 DQM Delay:
4573 11:13:12.163511 DQM0 = 48, DQM1 = 40
4574 11:13:12.166678 DQ Delay:
4575 11:13:12.166761 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4576 11:13:12.169915 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4577 11:13:12.173095 DQ8 =28, DQ9 =24, DQ10 =48, DQ11 =32
4578 11:13:12.176483 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =44
4579 11:13:12.180220
4580 11:13:12.180323
4581 11:13:12.186515 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d74, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4582 11:13:12.189964 CH1 RK0: MR19=808, MR18=4D74
4583 11:13:12.196510 CH1_RK0: MR19=0x808, MR18=0x4D74, DQSOSC=388, MR23=63, INC=174, DEC=116
4584 11:13:12.196671
4585 11:13:12.199811 ----->DramcWriteLeveling(PI) begin...
4586 11:13:12.200033 ==
4587 11:13:12.203118 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 11:13:12.206441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 11:13:12.206702 ==
4590 11:13:12.209499 Write leveling (Byte 0): 29 => 29
4591 11:13:12.212970 Write leveling (Byte 1): 29 => 29
4592 11:13:12.216676 DramcWriteLeveling(PI) end<-----
4593 11:13:12.217015
4594 11:13:12.217215 ==
4595 11:13:12.220204 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 11:13:12.223499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 11:13:12.223911 ==
4598 11:13:12.226753 [Gating] SW mode calibration
4599 11:13:12.233508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4600 11:13:12.240052 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4601 11:13:12.243273 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 11:13:12.246297 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 11:13:12.253085 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
4604 11:13:12.256570 0 9 12 | B1->B0 | 2c2c 3131 | 0 0 | (0 0) (0 0)
4605 11:13:12.259631 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 11:13:12.266388 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 11:13:12.269740 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 11:13:12.272997 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 11:13:12.279756 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 11:13:12.283356 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 11:13:12.286789 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 11:13:12.293158 0 10 12 | B1->B0 | 3939 2f2f | 0 0 | (0 0) (0 0)
4613 11:13:12.295835 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 11:13:12.299805 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 11:13:12.306231 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 11:13:12.309027 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 11:13:12.312691 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 11:13:12.319159 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 11:13:12.322489 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 11:13:12.325784 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4621 11:13:12.332280 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:13:12.335561 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:13:12.338951 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:13:12.345672 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:13:12.348573 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:13:12.352203 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:13:12.358725 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:13:12.361969 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:13:12.365284 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 11:13:12.372151 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 11:13:12.375074 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 11:13:12.378275 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 11:13:12.385116 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 11:13:12.388360 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 11:13:12.391674 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 11:13:12.398256 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4637 11:13:12.401554 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 11:13:12.404962 Total UI for P1: 0, mck2ui 16
4639 11:13:12.408170 best dqsien dly found for B0: ( 0, 13, 12)
4640 11:13:12.411522 Total UI for P1: 0, mck2ui 16
4641 11:13:12.414985 best dqsien dly found for B1: ( 0, 13, 12)
4642 11:13:12.418191 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4643 11:13:12.421137 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4644 11:13:12.421564
4645 11:13:12.424890 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4646 11:13:12.431113 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4647 11:13:12.431542 [Gating] SW calibration Done
4648 11:13:12.431877 ==
4649 11:13:12.434311 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 11:13:12.441125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 11:13:12.441553 ==
4652 11:13:12.441939 RX Vref Scan: 0
4653 11:13:12.442282
4654 11:13:12.444079 RX Vref 0 -> 0, step: 1
4655 11:13:12.444551
4656 11:13:12.447738 RX Delay -230 -> 252, step: 16
4657 11:13:12.451116 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4658 11:13:12.454498 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4659 11:13:12.457317 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4660 11:13:12.464369 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4661 11:13:12.467340 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4662 11:13:12.470923 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4663 11:13:12.474226 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4664 11:13:12.480820 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4665 11:13:12.483836 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4666 11:13:12.486985 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4667 11:13:12.490327 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4668 11:13:12.496979 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4669 11:13:12.500338 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4670 11:13:12.503546 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4671 11:13:12.507062 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4672 11:13:12.513311 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4673 11:13:12.513921 ==
4674 11:13:12.517071 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 11:13:12.520290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 11:13:12.520958 ==
4677 11:13:12.521505 DQS Delay:
4678 11:13:12.523369 DQS0 = 0, DQS1 = 0
4679 11:13:12.523957 DQM Delay:
4680 11:13:12.526712 DQM0 = 50, DQM1 = 45
4681 11:13:12.527323 DQ Delay:
4682 11:13:12.530023 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4683 11:13:12.533436 DQ4 =49, DQ5 =65, DQ6 =49, DQ7 =49
4684 11:13:12.536665 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4685 11:13:12.539746 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4686 11:13:12.540319
4687 11:13:12.540926
4688 11:13:12.541447 ==
4689 11:13:12.542943 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 11:13:12.546748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 11:13:12.547362 ==
4692 11:13:12.549938
4693 11:13:12.550568
4694 11:13:12.551080 TX Vref Scan disable
4695 11:13:12.553308 == TX Byte 0 ==
4696 11:13:12.556285 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4697 11:13:12.559523 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4698 11:13:12.562869 == TX Byte 1 ==
4699 11:13:12.566215 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4700 11:13:12.569305 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4701 11:13:12.572709 ==
4702 11:13:12.572838 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 11:13:12.579505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 11:13:12.579617 ==
4705 11:13:12.579711
4706 11:13:12.579802
4707 11:13:12.582611 TX Vref Scan disable
4708 11:13:12.582718 == TX Byte 0 ==
4709 11:13:12.589329 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4710 11:13:12.592155 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4711 11:13:12.592266 == TX Byte 1 ==
4712 11:13:12.598846 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4713 11:13:12.602624 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4714 11:13:12.602708
4715 11:13:12.602773 [DATLAT]
4716 11:13:12.605713 Freq=600, CH1 RK1
4717 11:13:12.605802
4718 11:13:12.605872 DATLAT Default: 0x9
4719 11:13:12.609091 0, 0xFFFF, sum = 0
4720 11:13:12.609189 1, 0xFFFF, sum = 0
4721 11:13:12.612254 2, 0xFFFF, sum = 0
4722 11:13:12.615704 3, 0xFFFF, sum = 0
4723 11:13:12.615874 4, 0xFFFF, sum = 0
4724 11:13:12.619093 5, 0xFFFF, sum = 0
4725 11:13:12.619294 6, 0xFFFF, sum = 0
4726 11:13:12.622154 7, 0xFFFF, sum = 0
4727 11:13:12.622311 8, 0x0, sum = 1
4728 11:13:12.625428 9, 0x0, sum = 2
4729 11:13:12.625561 10, 0x0, sum = 3
4730 11:13:12.625661 11, 0x0, sum = 4
4731 11:13:12.628631 best_step = 9
4732 11:13:12.628822
4733 11:13:12.628939 ==
4734 11:13:12.632104 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 11:13:12.635431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 11:13:12.635634 ==
4737 11:13:12.638715 RX Vref Scan: 0
4738 11:13:12.638891
4739 11:13:12.639028 RX Vref 0 -> 0, step: 1
4740 11:13:12.639157
4741 11:13:12.642466 RX Delay -179 -> 252, step: 8
4742 11:13:12.649619 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4743 11:13:12.652784 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4744 11:13:12.656326 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4745 11:13:12.659557 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4746 11:13:12.666445 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4747 11:13:12.669750 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4748 11:13:12.672879 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4749 11:13:12.676134 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4750 11:13:12.679540 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4751 11:13:12.685871 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4752 11:13:12.689405 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4753 11:13:12.692748 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4754 11:13:12.695977 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4755 11:13:12.702569 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4756 11:13:12.705832 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4757 11:13:12.709192 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4758 11:13:12.709648 ==
4759 11:13:12.712604 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 11:13:12.715989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 11:13:12.716578 ==
4762 11:13:12.718879 DQS Delay:
4763 11:13:12.719299 DQS0 = 0, DQS1 = 0
4764 11:13:12.722526 DQM Delay:
4765 11:13:12.723051 DQM0 = 49, DQM1 = 43
4766 11:13:12.723492 DQ Delay:
4767 11:13:12.725508 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4768 11:13:12.729280 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4769 11:13:12.732495 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4770 11:13:12.735969 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4771 11:13:12.736449
4772 11:13:12.736832
4773 11:13:12.745521 [DQSOSCAuto] RK1, (LSB)MR18= 0x5319, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
4774 11:13:12.749120 CH1 RK1: MR19=808, MR18=5319
4775 11:13:12.755990 CH1_RK1: MR19=0x808, MR18=0x5319, DQSOSC=394, MR23=63, INC=168, DEC=112
4776 11:13:12.756563 [RxdqsGatingPostProcess] freq 600
4777 11:13:12.762414 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4778 11:13:12.765341 Pre-setting of DQS Precalculation
4779 11:13:12.769059 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4780 11:13:12.779007 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4781 11:13:12.785282 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4782 11:13:12.785865
4783 11:13:12.786383
4784 11:13:12.788455 [Calibration Summary] 1200 Mbps
4785 11:13:12.788993 CH 0, Rank 0
4786 11:13:12.791865 SW Impedance : PASS
4787 11:13:12.792293 DUTY Scan : NO K
4788 11:13:12.795002 ZQ Calibration : PASS
4789 11:13:12.798586 Jitter Meter : NO K
4790 11:13:12.799012 CBT Training : PASS
4791 11:13:12.801780 Write leveling : PASS
4792 11:13:12.805218 RX DQS gating : PASS
4793 11:13:12.805680 RX DQ/DQS(RDDQC) : PASS
4794 11:13:12.808228 TX DQ/DQS : PASS
4795 11:13:12.811561 RX DATLAT : PASS
4796 11:13:12.812077 RX DQ/DQS(Engine): PASS
4797 11:13:12.815103 TX OE : NO K
4798 11:13:12.815657 All Pass.
4799 11:13:12.816127
4800 11:13:12.818252 CH 0, Rank 1
4801 11:13:12.818697 SW Impedance : PASS
4802 11:13:12.821467 DUTY Scan : NO K
4803 11:13:12.824828 ZQ Calibration : PASS
4804 11:13:12.825251 Jitter Meter : NO K
4805 11:13:12.828200 CBT Training : PASS
4806 11:13:12.832009 Write leveling : PASS
4807 11:13:12.832535 RX DQS gating : PASS
4808 11:13:12.835162 RX DQ/DQS(RDDQC) : PASS
4809 11:13:12.838525 TX DQ/DQS : PASS
4810 11:13:12.838995 RX DATLAT : PASS
4811 11:13:12.841597 RX DQ/DQS(Engine): PASS
4812 11:13:12.842053 TX OE : NO K
4813 11:13:12.844962 All Pass.
4814 11:13:12.845441
4815 11:13:12.845864 CH 1, Rank 0
4816 11:13:12.848068 SW Impedance : PASS
4817 11:13:12.848492 DUTY Scan : NO K
4818 11:13:12.851406 ZQ Calibration : PASS
4819 11:13:12.854581 Jitter Meter : NO K
4820 11:13:12.855065 CBT Training : PASS
4821 11:13:12.857897 Write leveling : PASS
4822 11:13:12.861161 RX DQS gating : PASS
4823 11:13:12.861586 RX DQ/DQS(RDDQC) : PASS
4824 11:13:12.864903 TX DQ/DQS : PASS
4825 11:13:12.867686 RX DATLAT : PASS
4826 11:13:12.868176 RX DQ/DQS(Engine): PASS
4827 11:13:12.871412 TX OE : NO K
4828 11:13:12.871837 All Pass.
4829 11:13:12.872176
4830 11:13:12.874595 CH 1, Rank 1
4831 11:13:12.875109 SW Impedance : PASS
4832 11:13:12.878058 DUTY Scan : NO K
4833 11:13:12.881233 ZQ Calibration : PASS
4834 11:13:12.881682 Jitter Meter : NO K
4835 11:13:12.884511 CBT Training : PASS
4836 11:13:12.887660 Write leveling : PASS
4837 11:13:12.888219 RX DQS gating : PASS
4838 11:13:12.891254 RX DQ/DQS(RDDQC) : PASS
4839 11:13:12.894378 TX DQ/DQS : PASS
4840 11:13:12.894829 RX DATLAT : PASS
4841 11:13:12.897944 RX DQ/DQS(Engine): PASS
4842 11:13:12.898413 TX OE : NO K
4843 11:13:12.900852 All Pass.
4844 11:13:12.901313
4845 11:13:12.901702 DramC Write-DBI off
4846 11:13:12.904021 PER_BANK_REFRESH: Hybrid Mode
4847 11:13:12.907295 TX_TRACKING: ON
4848 11:13:12.914433 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4849 11:13:12.917664 [FAST_K] Save calibration result to emmc
4850 11:13:12.924058 dramc_set_vcore_voltage set vcore to 662500
4851 11:13:12.924489 Read voltage for 933, 3
4852 11:13:12.925090 Vio18 = 0
4853 11:13:12.927633 Vcore = 662500
4854 11:13:12.928185 Vdram = 0
4855 11:13:12.928702 Vddq = 0
4856 11:13:12.930960 Vmddr = 0
4857 11:13:12.933810 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4858 11:13:12.940521 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4859 11:13:12.944295 MEM_TYPE=3, freq_sel=17
4860 11:13:12.944455 sv_algorithm_assistance_LP4_1600
4861 11:13:12.950493 ============ PULL DRAM RESETB DOWN ============
4862 11:13:12.953929 ========== PULL DRAM RESETB DOWN end =========
4863 11:13:12.957091 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4864 11:13:12.960384 ===================================
4865 11:13:12.963440 LPDDR4 DRAM CONFIGURATION
4866 11:13:12.966555 ===================================
4867 11:13:12.969868 EX_ROW_EN[0] = 0x0
4868 11:13:12.969978 EX_ROW_EN[1] = 0x0
4869 11:13:12.973181 LP4Y_EN = 0x0
4870 11:13:12.973290 WORK_FSP = 0x0
4871 11:13:12.976306 WL = 0x3
4872 11:13:12.976407 RL = 0x3
4873 11:13:12.979786 BL = 0x2
4874 11:13:12.979897 RPST = 0x0
4875 11:13:12.983145 RD_PRE = 0x0
4876 11:13:12.983245 WR_PRE = 0x1
4877 11:13:12.986216 WR_PST = 0x0
4878 11:13:12.989585 DBI_WR = 0x0
4879 11:13:12.989694 DBI_RD = 0x0
4880 11:13:12.993377 OTF = 0x1
4881 11:13:12.996459 ===================================
4882 11:13:12.999746 ===================================
4883 11:13:12.999848 ANA top config
4884 11:13:13.003199 ===================================
4885 11:13:13.006074 DLL_ASYNC_EN = 0
4886 11:13:13.009566 ALL_SLAVE_EN = 1
4887 11:13:13.009672 NEW_RANK_MODE = 1
4888 11:13:13.013005 DLL_IDLE_MODE = 1
4889 11:13:13.016328 LP45_APHY_COMB_EN = 1
4890 11:13:13.019415 TX_ODT_DIS = 1
4891 11:13:13.019527 NEW_8X_MODE = 1
4892 11:13:13.022680 ===================================
4893 11:13:13.026090 ===================================
4894 11:13:13.029382 data_rate = 1866
4895 11:13:13.032948 CKR = 1
4896 11:13:13.036057 DQ_P2S_RATIO = 8
4897 11:13:13.039397 ===================================
4898 11:13:13.042716 CA_P2S_RATIO = 8
4899 11:13:13.045894 DQ_CA_OPEN = 0
4900 11:13:13.045971 DQ_SEMI_OPEN = 0
4901 11:13:13.049224 CA_SEMI_OPEN = 0
4902 11:13:13.052481 CA_FULL_RATE = 0
4903 11:13:13.055807 DQ_CKDIV4_EN = 1
4904 11:13:13.059113 CA_CKDIV4_EN = 1
4905 11:13:13.062376 CA_PREDIV_EN = 0
4906 11:13:13.062478 PH8_DLY = 0
4907 11:13:13.065713 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4908 11:13:13.069041 DQ_AAMCK_DIV = 4
4909 11:13:13.072225 CA_AAMCK_DIV = 4
4910 11:13:13.075470 CA_ADMCK_DIV = 4
4911 11:13:13.079100 DQ_TRACK_CA_EN = 0
4912 11:13:13.082326 CA_PICK = 933
4913 11:13:13.082425 CA_MCKIO = 933
4914 11:13:13.085675 MCKIO_SEMI = 0
4915 11:13:13.088973 PLL_FREQ = 3732
4916 11:13:13.092447 DQ_UI_PI_RATIO = 32
4917 11:13:13.095651 CA_UI_PI_RATIO = 0
4918 11:13:13.099212 ===================================
4919 11:13:13.102230 ===================================
4920 11:13:13.105600 memory_type:LPDDR4
4921 11:13:13.105746 GP_NUM : 10
4922 11:13:13.108707 SRAM_EN : 1
4923 11:13:13.108843 MD32_EN : 0
4924 11:13:13.111977 ===================================
4925 11:13:13.115514 [ANA_INIT] >>>>>>>>>>>>>>
4926 11:13:13.118881 <<<<<< [CONFIGURE PHASE]: ANA_TX
4927 11:13:13.122281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4928 11:13:13.125208 ===================================
4929 11:13:13.128497 data_rate = 1866,PCW = 0X8f00
4930 11:13:13.131846 ===================================
4931 11:13:13.135135 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4932 11:13:13.141839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 11:13:13.145328 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4934 11:13:13.151817 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4935 11:13:13.155275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4936 11:13:13.158596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4937 11:13:13.158692 [ANA_INIT] flow start
4938 11:13:13.161776 [ANA_INIT] PLL >>>>>>>>
4939 11:13:13.165168 [ANA_INIT] PLL <<<<<<<<
4940 11:13:13.165280 [ANA_INIT] MIDPI >>>>>>>>
4941 11:13:13.168365 [ANA_INIT] MIDPI <<<<<<<<
4942 11:13:13.171657 [ANA_INIT] DLL >>>>>>>>
4943 11:13:13.171809 [ANA_INIT] flow end
4944 11:13:13.178165 ============ LP4 DIFF to SE enter ============
4945 11:13:13.181545 ============ LP4 DIFF to SE exit ============
4946 11:13:13.185043 [ANA_INIT] <<<<<<<<<<<<<
4947 11:13:13.188299 [Flow] Enable top DCM control >>>>>
4948 11:13:13.191609 [Flow] Enable top DCM control <<<<<
4949 11:13:13.191688 Enable DLL master slave shuffle
4950 11:13:13.198041 ==============================================================
4951 11:13:13.201537 Gating Mode config
4952 11:13:13.204780 ==============================================================
4953 11:13:13.208274 Config description:
4954 11:13:13.217959 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4955 11:13:13.224721 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4956 11:13:13.228080 SELPH_MODE 0: By rank 1: By Phase
4957 11:13:13.234634 ==============================================================
4958 11:13:13.237908 GAT_TRACK_EN = 1
4959 11:13:13.241198 RX_GATING_MODE = 2
4960 11:13:13.244556 RX_GATING_TRACK_MODE = 2
4961 11:13:13.247758 SELPH_MODE = 1
4962 11:13:13.251186 PICG_EARLY_EN = 1
4963 11:13:13.251329 VALID_LAT_VALUE = 1
4964 11:13:13.257896 ==============================================================
4965 11:13:13.261118 Enter into Gating configuration >>>>
4966 11:13:13.264315 Exit from Gating configuration <<<<
4967 11:13:13.268209 Enter into DVFS_PRE_config >>>>>
4968 11:13:13.278093 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4969 11:13:13.281108 Exit from DVFS_PRE_config <<<<<
4970 11:13:13.284379 Enter into PICG configuration >>>>
4971 11:13:13.288033 Exit from PICG configuration <<<<
4972 11:13:13.291227 [RX_INPUT] configuration >>>>>
4973 11:13:13.294649 [RX_INPUT] configuration <<<<<
4974 11:13:13.301229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4975 11:13:13.304499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4976 11:13:13.311284 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 11:13:13.317686 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 11:13:13.324389 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4979 11:13:13.330894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4980 11:13:13.334180 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4981 11:13:13.337485 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4982 11:13:13.340480 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4983 11:13:13.347142 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4984 11:13:13.350654 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4985 11:13:13.353799 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4986 11:13:13.356968 ===================================
4987 11:13:13.360744 LPDDR4 DRAM CONFIGURATION
4988 11:13:13.363990 ===================================
4989 11:13:13.364419 EX_ROW_EN[0] = 0x0
4990 11:13:13.367234 EX_ROW_EN[1] = 0x0
4991 11:13:13.370556 LP4Y_EN = 0x0
4992 11:13:13.370974 WORK_FSP = 0x0
4993 11:13:13.373713 WL = 0x3
4994 11:13:13.374134 RL = 0x3
4995 11:13:13.377406 BL = 0x2
4996 11:13:13.377826 RPST = 0x0
4997 11:13:13.380811 RD_PRE = 0x0
4998 11:13:13.381232 WR_PRE = 0x1
4999 11:13:13.384168 WR_PST = 0x0
5000 11:13:13.384585 DBI_WR = 0x0
5001 11:13:13.387474 DBI_RD = 0x0
5002 11:13:13.387896 OTF = 0x1
5003 11:13:13.390674 ===================================
5004 11:13:13.394132 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5005 11:13:13.400584 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5006 11:13:13.403740 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5007 11:13:13.407134 ===================================
5008 11:13:13.410765 LPDDR4 DRAM CONFIGURATION
5009 11:13:13.414096 ===================================
5010 11:13:13.414626 EX_ROW_EN[0] = 0x10
5011 11:13:13.417086 EX_ROW_EN[1] = 0x0
5012 11:13:13.417506 LP4Y_EN = 0x0
5013 11:13:13.420287 WORK_FSP = 0x0
5014 11:13:13.423515 WL = 0x3
5015 11:13:13.423937 RL = 0x3
5016 11:13:13.426524 BL = 0x2
5017 11:13:13.427056 RPST = 0x0
5018 11:13:13.430217 RD_PRE = 0x0
5019 11:13:13.430789 WR_PRE = 0x1
5020 11:13:13.433540 WR_PST = 0x0
5021 11:13:13.434175 DBI_WR = 0x0
5022 11:13:13.436505 DBI_RD = 0x0
5023 11:13:13.437133 OTF = 0x1
5024 11:13:13.439916 ===================================
5025 11:13:13.446616 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5026 11:13:13.450777 nWR fixed to 30
5027 11:13:13.453960 [ModeRegInit_LP4] CH0 RK0
5028 11:13:13.454379 [ModeRegInit_LP4] CH0 RK1
5029 11:13:13.457364 [ModeRegInit_LP4] CH1 RK0
5030 11:13:13.460234 [ModeRegInit_LP4] CH1 RK1
5031 11:13:13.460758 match AC timing 9
5032 11:13:13.467282 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5033 11:13:13.470651 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5034 11:13:13.473407 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5035 11:13:13.480476 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5036 11:13:13.483826 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5037 11:13:13.484384 ==
5038 11:13:13.487200 Dram Type= 6, Freq= 0, CH_0, rank 0
5039 11:13:13.489851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5040 11:13:13.490279 ==
5041 11:13:13.496113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5042 11:13:13.502960 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5043 11:13:13.506233 [CA 0] Center 37 (7~68) winsize 62
5044 11:13:13.509528 [CA 1] Center 38 (7~69) winsize 63
5045 11:13:13.512731 [CA 2] Center 35 (5~66) winsize 62
5046 11:13:13.516213 [CA 3] Center 35 (5~65) winsize 61
5047 11:13:13.519721 [CA 4] Center 34 (4~65) winsize 62
5048 11:13:13.523117 [CA 5] Center 33 (3~64) winsize 62
5049 11:13:13.523191
5050 11:13:13.525913 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5051 11:13:13.525991
5052 11:13:13.529510 [CATrainingPosCal] consider 1 rank data
5053 11:13:13.532459 u2DelayCellTimex100 = 270/100 ps
5054 11:13:13.536074 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5055 11:13:13.539381 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5056 11:13:13.542944 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5057 11:13:13.549349 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5058 11:13:13.552373 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5059 11:13:13.555826 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5060 11:13:13.555908
5061 11:13:13.559344 CA PerBit enable=1, Macro0, CA PI delay=33
5062 11:13:13.559428
5063 11:13:13.562346 [CBTSetCACLKResult] CA Dly = 33
5064 11:13:13.562431 CS Dly: 6 (0~37)
5065 11:13:13.562514 ==
5066 11:13:13.565882 Dram Type= 6, Freq= 0, CH_0, rank 1
5067 11:13:13.572891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5068 11:13:13.573326 ==
5069 11:13:13.576184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5070 11:13:13.582732 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5071 11:13:13.585851 [CA 0] Center 38 (8~69) winsize 62
5072 11:13:13.589332 [CA 1] Center 38 (8~69) winsize 62
5073 11:13:13.592870 [CA 2] Center 36 (6~66) winsize 61
5074 11:13:13.596144 [CA 3] Center 35 (5~66) winsize 62
5075 11:13:13.599449 [CA 4] Center 34 (4~65) winsize 62
5076 11:13:13.602672 [CA 5] Center 34 (4~65) winsize 62
5077 11:13:13.603104
5078 11:13:13.605874 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5079 11:13:13.606303
5080 11:13:13.609126 [CATrainingPosCal] consider 2 rank data
5081 11:13:13.612441 u2DelayCellTimex100 = 270/100 ps
5082 11:13:13.615780 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5083 11:13:13.622632 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5084 11:13:13.625777 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5085 11:13:13.628946 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5086 11:13:13.632386 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5087 11:13:13.635741 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5088 11:13:13.636340
5089 11:13:13.638960 CA PerBit enable=1, Macro0, CA PI delay=34
5090 11:13:13.639393
5091 11:13:13.642166 [CBTSetCACLKResult] CA Dly = 34
5092 11:13:13.645469 CS Dly: 7 (0~40)
5093 11:13:13.646032
5094 11:13:13.648670 ----->DramcWriteLeveling(PI) begin...
5095 11:13:13.649144 ==
5096 11:13:13.652176 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 11:13:13.655264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 11:13:13.655695 ==
5099 11:13:13.658712 Write leveling (Byte 0): 31 => 31
5100 11:13:13.662017 Write leveling (Byte 1): 27 => 27
5101 11:13:13.665468 DramcWriteLeveling(PI) end<-----
5102 11:13:13.665909
5103 11:13:13.666388 ==
5104 11:13:13.668672 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 11:13:13.671799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 11:13:13.672326 ==
5107 11:13:13.675004 [Gating] SW mode calibration
5108 11:13:13.681904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5109 11:13:13.688542 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5110 11:13:13.691897 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5111 11:13:13.695037 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 11:13:13.701591 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 11:13:13.705158 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 11:13:13.708261 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 11:13:13.715170 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 11:13:13.718209 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5117 11:13:13.721269 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5118 11:13:13.728265 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5119 11:13:13.731338 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 11:13:13.734815 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 11:13:13.741811 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 11:13:13.744846 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 11:13:13.748250 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 11:13:13.754342 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5125 11:13:13.758014 0 15 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
5126 11:13:13.761310 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5127 11:13:13.767632 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 11:13:13.770856 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 11:13:13.774409 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 11:13:13.780829 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 11:13:13.784233 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 11:13:13.787476 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 11:13:13.794046 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5134 11:13:13.797253 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:13:13.800887 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:13:13.807348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:13:13.810532 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:13:13.813714 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:13:13.820689 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:13:13.823782 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:13:13.827269 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:13:13.833783 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:13:13.836880 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 11:13:13.840500 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 11:13:13.847017 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 11:13:13.850194 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 11:13:13.853442 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 11:13:13.860019 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5149 11:13:13.863015 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5150 11:13:13.866268 Total UI for P1: 0, mck2ui 16
5151 11:13:13.869758 best dqsien dly found for B0: ( 1, 2, 24)
5152 11:13:13.873274 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5153 11:13:13.879914 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 11:13:13.880455 Total UI for P1: 0, mck2ui 16
5155 11:13:13.886004 best dqsien dly found for B1: ( 1, 2, 30)
5156 11:13:13.889559 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5157 11:13:13.893059 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5158 11:13:13.893486
5159 11:13:13.896230 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5160 11:13:13.899421 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5161 11:13:13.902973 [Gating] SW calibration Done
5162 11:13:13.903433 ==
5163 11:13:13.906217 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 11:13:13.909483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 11:13:13.909913 ==
5166 11:13:13.912670 RX Vref Scan: 0
5167 11:13:13.913136
5168 11:13:13.913576 RX Vref 0 -> 0, step: 1
5169 11:13:13.915927
5170 11:13:13.916386 RX Delay -80 -> 252, step: 8
5171 11:13:13.922876 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5172 11:13:13.926406 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5173 11:13:13.928997 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5174 11:13:13.932306 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5175 11:13:13.935659 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5176 11:13:13.939032 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5177 11:13:13.946093 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5178 11:13:13.948813 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5179 11:13:13.952647 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5180 11:13:13.955770 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5181 11:13:13.958879 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5182 11:13:13.965423 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5183 11:13:13.968871 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5184 11:13:13.972072 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5185 11:13:13.975329 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5186 11:13:13.978776 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5187 11:13:13.979235 ==
5188 11:13:13.981965 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 11:13:13.988737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 11:13:13.989196 ==
5191 11:13:13.989534 DQS Delay:
5192 11:13:13.989847 DQS0 = 0, DQS1 = 0
5193 11:13:13.992061 DQM Delay:
5194 11:13:13.992482 DQM0 = 105, DQM1 = 90
5195 11:13:13.995468 DQ Delay:
5196 11:13:13.998772 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5197 11:13:14.001862 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5198 11:13:14.005225 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5199 11:13:14.008464 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5200 11:13:14.009124
5201 11:13:14.009641
5202 11:13:14.010157 ==
5203 11:13:14.011816 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 11:13:14.015161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 11:13:14.015770 ==
5206 11:13:14.016113
5207 11:13:14.016428
5208 11:13:14.018342 TX Vref Scan disable
5209 11:13:14.021614 == TX Byte 0 ==
5210 11:13:14.025097 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5211 11:13:14.028418 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5212 11:13:14.031598 == TX Byte 1 ==
5213 11:13:14.035113 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5214 11:13:14.038206 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5215 11:13:14.038704 ==
5216 11:13:14.041901 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 11:13:14.045221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 11:13:14.048538 ==
5219 11:13:14.049077
5220 11:13:14.049415
5221 11:13:14.049782 TX Vref Scan disable
5222 11:13:14.051735 == TX Byte 0 ==
5223 11:13:14.055118 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5224 11:13:14.058838 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5225 11:13:14.062091 == TX Byte 1 ==
5226 11:13:14.065038 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5227 11:13:14.071799 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5228 11:13:14.072224
5229 11:13:14.072560 [DATLAT]
5230 11:13:14.072953 Freq=933, CH0 RK0
5231 11:13:14.073275
5232 11:13:14.075203 DATLAT Default: 0xd
5233 11:13:14.075624 0, 0xFFFF, sum = 0
5234 11:13:14.078019 1, 0xFFFF, sum = 0
5235 11:13:14.081391 2, 0xFFFF, sum = 0
5236 11:13:14.081817 3, 0xFFFF, sum = 0
5237 11:13:14.084889 4, 0xFFFF, sum = 0
5238 11:13:14.085335 5, 0xFFFF, sum = 0
5239 11:13:14.088056 6, 0xFFFF, sum = 0
5240 11:13:14.088552 7, 0xFFFF, sum = 0
5241 11:13:14.091231 8, 0xFFFF, sum = 0
5242 11:13:14.091711 9, 0xFFFF, sum = 0
5243 11:13:14.094765 10, 0x0, sum = 1
5244 11:13:14.095345 11, 0x0, sum = 2
5245 11:13:14.097643 12, 0x0, sum = 3
5246 11:13:14.098094 13, 0x0, sum = 4
5247 11:13:14.100981 best_step = 11
5248 11:13:14.101433
5249 11:13:14.101787 ==
5250 11:13:14.104188 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 11:13:14.107883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 11:13:14.108207 ==
5253 11:13:14.108310 RX Vref Scan: 1
5254 11:13:14.108408
5255 11:13:14.110630 RX Vref 0 -> 0, step: 1
5256 11:13:14.110713
5257 11:13:14.113995 RX Delay -53 -> 252, step: 4
5258 11:13:14.114078
5259 11:13:14.117235 Set Vref, RX VrefLevel [Byte0]: 57
5260 11:13:14.120758 [Byte1]: 48
5261 11:13:14.124066
5262 11:13:14.124147 Final RX Vref Byte 0 = 57 to rank0
5263 11:13:14.127149 Final RX Vref Byte 1 = 48 to rank0
5264 11:13:14.130455 Final RX Vref Byte 0 = 57 to rank1
5265 11:13:14.133829 Final RX Vref Byte 1 = 48 to rank1==
5266 11:13:14.137069 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 11:13:14.143789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 11:13:14.143872 ==
5269 11:13:14.143938 DQS Delay:
5270 11:13:14.143999 DQS0 = 0, DQS1 = 0
5271 11:13:14.147205 DQM Delay:
5272 11:13:14.147286 DQM0 = 107, DQM1 = 91
5273 11:13:14.150599 DQ Delay:
5274 11:13:14.153841 DQ0 =108, DQ1 =108, DQ2 =102, DQ3 =106
5275 11:13:14.157082 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =114
5276 11:13:14.160198 DQ8 =82, DQ9 =78, DQ10 =92, DQ11 =90
5277 11:13:14.163571 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5278 11:13:14.163653
5279 11:13:14.163718
5280 11:13:14.170590 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
5281 11:13:14.173457 CH0 RK0: MR19=505, MR18=241F
5282 11:13:14.179960 CH0_RK0: MR19=0x505, MR18=0x241F, DQSOSC=410, MR23=63, INC=64, DEC=42
5283 11:13:14.180059
5284 11:13:14.183592 ----->DramcWriteLeveling(PI) begin...
5285 11:13:14.183705 ==
5286 11:13:14.186771 Dram Type= 6, Freq= 0, CH_0, rank 1
5287 11:13:14.190077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 11:13:14.190163 ==
5289 11:13:14.193580 Write leveling (Byte 0): 30 => 30
5290 11:13:14.196746 Write leveling (Byte 1): 30 => 30
5291 11:13:14.200048 DramcWriteLeveling(PI) end<-----
5292 11:13:14.200130
5293 11:13:14.200196 ==
5294 11:13:14.203243 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 11:13:14.209766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 11:13:14.209849 ==
5297 11:13:14.209914 [Gating] SW mode calibration
5298 11:13:14.220060 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5299 11:13:14.223170 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5300 11:13:14.226875 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 11:13:14.233305 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 11:13:14.236294 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 11:13:14.239682 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 11:13:14.246129 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 11:13:14.251392 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 11:13:14.253091 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
5307 11:13:14.259753 0 14 28 | B1->B0 | 2d2d 2727 | 1 0 | (1 0) (0 0)
5308 11:13:14.263077 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 11:13:14.266401 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 11:13:14.272944 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 11:13:14.276444 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 11:13:14.279793 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 11:13:14.286499 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 11:13:14.289444 0 15 24 | B1->B0 | 2626 2d2c | 0 1 | (0 0) (0 0)
5315 11:13:14.292877 0 15 28 | B1->B0 | 3636 4141 | 0 0 | (0 0) (0 0)
5316 11:13:14.299346 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 11:13:14.302774 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 11:13:14.306114 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 11:13:14.312622 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 11:13:14.316046 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 11:13:14.319257 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 11:13:14.325912 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 11:13:14.329188 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5324 11:13:14.332263 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:13:14.338960 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:13:14.342126 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:13:14.345479 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:13:14.352375 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:13:14.355534 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:13:14.358920 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:13:14.365636 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:13:14.368715 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 11:13:14.372088 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 11:13:14.378758 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 11:13:14.381691 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 11:13:14.385072 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 11:13:14.391595 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 11:13:14.395092 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5339 11:13:14.398130 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 11:13:14.401532 Total UI for P1: 0, mck2ui 16
5341 11:13:14.405103 best dqsien dly found for B0: ( 1, 2, 24)
5342 11:13:14.408301 Total UI for P1: 0, mck2ui 16
5343 11:13:14.411330 best dqsien dly found for B1: ( 1, 2, 24)
5344 11:13:14.414653 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5345 11:13:14.418066 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5346 11:13:14.418226
5347 11:13:14.424971 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5348 11:13:14.428255 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5349 11:13:14.431617 [Gating] SW calibration Done
5350 11:13:14.431700 ==
5351 11:13:14.434992 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 11:13:14.438004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 11:13:14.438165 ==
5354 11:13:14.438261 RX Vref Scan: 0
5355 11:13:14.438352
5356 11:13:14.441224 RX Vref 0 -> 0, step: 1
5357 11:13:14.441341
5358 11:13:14.444509 RX Delay -80 -> 252, step: 8
5359 11:13:14.447771 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5360 11:13:14.451181 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5361 11:13:14.454328 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5362 11:13:14.461149 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5363 11:13:14.464720 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5364 11:13:14.468180 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5365 11:13:14.471210 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5366 11:13:14.474258 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5367 11:13:14.480662 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5368 11:13:14.484345 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5369 11:13:14.487461 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5370 11:13:14.490588 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5371 11:13:14.494265 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5372 11:13:14.497248 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5373 11:13:14.504218 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5374 11:13:14.507571 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5375 11:13:14.507699 ==
5376 11:13:14.510775 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 11:13:14.514266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 11:13:14.514501 ==
5379 11:13:14.517210 DQS Delay:
5380 11:13:14.517426 DQS0 = 0, DQS1 = 0
5381 11:13:14.517562 DQM Delay:
5382 11:13:14.520560 DQM0 = 104, DQM1 = 89
5383 11:13:14.520843 DQ Delay:
5384 11:13:14.524150 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5385 11:13:14.527263 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5386 11:13:14.530825 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5387 11:13:14.534185 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5388 11:13:14.534484
5389 11:13:14.534752
5390 11:13:14.537296 ==
5391 11:13:14.540572 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 11:13:14.543782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 11:13:14.544195 ==
5394 11:13:14.544528
5395 11:13:14.544880
5396 11:13:14.547223 TX Vref Scan disable
5397 11:13:14.547643 == TX Byte 0 ==
5398 11:13:14.550411 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5399 11:13:14.557023 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5400 11:13:14.557442 == TX Byte 1 ==
5401 11:13:14.563674 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5402 11:13:14.566967 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5403 11:13:14.567385 ==
5404 11:13:14.570358 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 11:13:14.573937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 11:13:14.574459 ==
5407 11:13:14.574911
5408 11:13:14.575371
5409 11:13:14.577264 TX Vref Scan disable
5410 11:13:14.580264 == TX Byte 0 ==
5411 11:13:14.583827 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5412 11:13:14.587100 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5413 11:13:14.590574 == TX Byte 1 ==
5414 11:13:14.593651 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5415 11:13:14.596917 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5416 11:13:14.597337
5417 11:13:14.600236 [DATLAT]
5418 11:13:14.600719 Freq=933, CH0 RK1
5419 11:13:14.601228
5420 11:13:14.603511 DATLAT Default: 0xb
5421 11:13:14.603930 0, 0xFFFF, sum = 0
5422 11:13:14.606558 1, 0xFFFF, sum = 0
5423 11:13:14.606999 2, 0xFFFF, sum = 0
5424 11:13:14.609903 3, 0xFFFF, sum = 0
5425 11:13:14.610331 4, 0xFFFF, sum = 0
5426 11:13:14.613183 5, 0xFFFF, sum = 0
5427 11:13:14.613641 6, 0xFFFF, sum = 0
5428 11:13:14.616632 7, 0xFFFF, sum = 0
5429 11:13:14.617112 8, 0xFFFF, sum = 0
5430 11:13:14.619803 9, 0xFFFF, sum = 0
5431 11:13:14.620250 10, 0x0, sum = 1
5432 11:13:14.622975 11, 0x0, sum = 2
5433 11:13:14.623409 12, 0x0, sum = 3
5434 11:13:14.626463 13, 0x0, sum = 4
5435 11:13:14.627013 best_step = 11
5436 11:13:14.627444
5437 11:13:14.627770 ==
5438 11:13:14.629908 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 11:13:14.636260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 11:13:14.636905 ==
5441 11:13:14.637428 RX Vref Scan: 0
5442 11:13:14.637929
5443 11:13:14.639525 RX Vref 0 -> 0, step: 1
5444 11:13:14.640053
5445 11:13:14.642826 RX Delay -53 -> 252, step: 4
5446 11:13:14.646119 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5447 11:13:14.652841 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5448 11:13:14.656039 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5449 11:13:14.659254 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5450 11:13:14.662500 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5451 11:13:14.666414 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5452 11:13:14.669142 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5453 11:13:14.676193 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5454 11:13:14.679624 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5455 11:13:14.683126 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5456 11:13:14.686119 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5457 11:13:14.689023 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5458 11:13:14.695958 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5459 11:13:14.699064 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5460 11:13:14.702567 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5461 11:13:14.705549 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5462 11:13:14.705971 ==
5463 11:13:14.708658 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 11:13:14.715747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 11:13:14.716171 ==
5466 11:13:14.716504 DQS Delay:
5467 11:13:14.716877 DQS0 = 0, DQS1 = 0
5468 11:13:14.718883 DQM Delay:
5469 11:13:14.719307 DQM0 = 104, DQM1 = 92
5470 11:13:14.722053 DQ Delay:
5471 11:13:14.725639 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5472 11:13:14.728677 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =110
5473 11:13:14.731927 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90
5474 11:13:14.735445 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =98
5475 11:13:14.735865
5476 11:13:14.736198
5477 11:13:14.741908 [DQSOSCAuto] RK1, (LSB)MR18= 0x2808, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5478 11:13:14.745120 CH0 RK1: MR19=505, MR18=2808
5479 11:13:14.751505 CH0_RK1: MR19=0x505, MR18=0x2808, DQSOSC=409, MR23=63, INC=64, DEC=43
5480 11:13:14.754852 [RxdqsGatingPostProcess] freq 933
5481 11:13:14.761884 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5482 11:13:14.762485 best DQS0 dly(2T, 0.5T) = (0, 10)
5483 11:13:14.764933 best DQS1 dly(2T, 0.5T) = (0, 10)
5484 11:13:14.768357 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5485 11:13:14.771507 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5486 11:13:14.774879 best DQS0 dly(2T, 0.5T) = (0, 10)
5487 11:13:14.778306 best DQS1 dly(2T, 0.5T) = (0, 10)
5488 11:13:14.781417 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5489 11:13:14.784724 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5490 11:13:14.787835 Pre-setting of DQS Precalculation
5491 11:13:14.794486 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5492 11:13:14.794596 ==
5493 11:13:14.797969 Dram Type= 6, Freq= 0, CH_1, rank 0
5494 11:13:14.801077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 11:13:14.801189 ==
5496 11:13:14.807473 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5497 11:13:14.811109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5498 11:13:14.814870 [CA 0] Center 37 (7~68) winsize 62
5499 11:13:14.818530 [CA 1] Center 37 (7~68) winsize 62
5500 11:13:14.821486 [CA 2] Center 36 (6~66) winsize 61
5501 11:13:14.824795 [CA 3] Center 34 (4~65) winsize 62
5502 11:13:14.828317 [CA 4] Center 35 (4~66) winsize 63
5503 11:13:14.831782 [CA 5] Center 34 (4~65) winsize 62
5504 11:13:14.831890
5505 11:13:14.834988 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5506 11:13:14.835096
5507 11:13:14.838068 [CATrainingPosCal] consider 1 rank data
5508 11:13:14.841383 u2DelayCellTimex100 = 270/100 ps
5509 11:13:14.844788 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5510 11:13:14.851047 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5511 11:13:14.854301 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5512 11:13:14.857954 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5513 11:13:14.861236 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
5514 11:13:14.864450 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5515 11:13:14.864532
5516 11:13:14.867875 CA PerBit enable=1, Macro0, CA PI delay=34
5517 11:13:14.867959
5518 11:13:14.871042 [CBTSetCACLKResult] CA Dly = 34
5519 11:13:14.874644 CS Dly: 6 (0~37)
5520 11:13:14.875063 ==
5521 11:13:14.877903 Dram Type= 6, Freq= 0, CH_1, rank 1
5522 11:13:14.881101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 11:13:14.881527 ==
5524 11:13:14.887899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 11:13:14.891030 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5526 11:13:14.895893 [CA 0] Center 38 (8~68) winsize 61
5527 11:13:14.898649 [CA 1] Center 38 (8~69) winsize 62
5528 11:13:14.902105 [CA 2] Center 36 (6~67) winsize 62
5529 11:13:14.905441 [CA 3] Center 35 (6~65) winsize 60
5530 11:13:14.908756 [CA 4] Center 36 (6~66) winsize 61
5531 11:13:14.912041 [CA 5] Center 35 (5~65) winsize 61
5532 11:13:14.912525
5533 11:13:14.915419 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5534 11:13:14.915840
5535 11:13:14.918765 [CATrainingPosCal] consider 2 rank data
5536 11:13:14.922027 u2DelayCellTimex100 = 270/100 ps
5537 11:13:14.925248 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5538 11:13:14.932093 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5539 11:13:14.934905 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5540 11:13:14.938149 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5541 11:13:14.941586 CA4 delay=36 (6~66),Diff = 1 PI (6 cell)
5542 11:13:14.945072 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5543 11:13:14.945493
5544 11:13:14.948262 CA PerBit enable=1, Macro0, CA PI delay=35
5545 11:13:14.948684
5546 11:13:14.951725 [CBTSetCACLKResult] CA Dly = 35
5547 11:13:14.954895 CS Dly: 7 (0~39)
5548 11:13:14.955314
5549 11:13:14.958071 ----->DramcWriteLeveling(PI) begin...
5550 11:13:14.958155 ==
5551 11:13:14.961016 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 11:13:14.964513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 11:13:14.964596 ==
5554 11:13:14.967684 Write leveling (Byte 0): 28 => 28
5555 11:13:14.971023 Write leveling (Byte 1): 30 => 30
5556 11:13:14.974305 DramcWriteLeveling(PI) end<-----
5557 11:13:14.974400
5558 11:13:14.974474 ==
5559 11:13:14.977744 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 11:13:14.980997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 11:13:14.981115 ==
5562 11:13:14.984356 [Gating] SW mode calibration
5563 11:13:14.990796 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5564 11:13:14.997840 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5565 11:13:15.000985 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 11:13:15.004455 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 11:13:15.010797 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 11:13:15.014433 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 11:13:15.017767 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 11:13:15.023996 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 11:13:15.027405 0 14 24 | B1->B0 | 2f2f 2f2f | 1 0 | (1 1) (0 0)
5572 11:13:15.030556 0 14 28 | B1->B0 | 2c2c 2525 | 1 0 | (1 0) (0 0)
5573 11:13:15.037351 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 11:13:15.040555 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 11:13:15.043931 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 11:13:15.050538 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 11:13:15.053874 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 11:13:15.057146 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 11:13:15.063724 0 15 24 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (1 1)
5580 11:13:15.067047 0 15 28 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
5581 11:13:15.070525 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 11:13:15.077235 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 11:13:15.080441 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 11:13:15.083769 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 11:13:15.090211 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 11:13:15.093612 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 11:13:15.096885 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5588 11:13:15.103373 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:13:15.106772 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:13:15.110076 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:13:15.116623 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:13:15.120054 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:13:15.123482 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:13:15.129767 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:13:15.133256 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:13:15.136630 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:13:15.143434 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 11:13:15.146385 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 11:13:15.149774 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 11:13:15.156016 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 11:13:15.159233 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 11:13:15.162604 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 11:13:15.169304 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5604 11:13:15.172866 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 11:13:15.175844 Total UI for P1: 0, mck2ui 16
5606 11:13:15.179054 best dqsien dly found for B0: ( 1, 2, 24)
5607 11:13:15.182897 Total UI for P1: 0, mck2ui 16
5608 11:13:15.186148 best dqsien dly found for B1: ( 1, 2, 26)
5609 11:13:15.189116 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5610 11:13:15.192269 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5611 11:13:15.192796
5612 11:13:15.196022 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5613 11:13:15.199326 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5614 11:13:15.202539 [Gating] SW calibration Done
5615 11:13:15.203118 ==
5616 11:13:15.205909 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 11:13:15.212289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 11:13:15.212994 ==
5619 11:13:15.213626 RX Vref Scan: 0
5620 11:13:15.214179
5621 11:13:15.215560 RX Vref 0 -> 0, step: 1
5622 11:13:15.216186
5623 11:13:15.218833 RX Delay -80 -> 252, step: 8
5624 11:13:15.222006 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5625 11:13:15.225204 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5626 11:13:15.228638 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5627 11:13:15.232258 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5628 11:13:15.235466 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5629 11:13:15.241995 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5630 11:13:15.245411 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5631 11:13:15.248406 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5632 11:13:15.251555 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5633 11:13:15.254656 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5634 11:13:15.261240 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5635 11:13:15.264840 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5636 11:13:15.267775 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5637 11:13:15.271452 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5638 11:13:15.274673 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5639 11:13:15.281317 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5640 11:13:15.281403 ==
5641 11:13:15.284759 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 11:13:15.287968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 11:13:15.288053 ==
5644 11:13:15.288118 DQS Delay:
5645 11:13:15.291277 DQS0 = 0, DQS1 = 0
5646 11:13:15.291359 DQM Delay:
5647 11:13:15.294389 DQM0 = 102, DQM1 = 95
5648 11:13:15.294472 DQ Delay:
5649 11:13:15.297719 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5650 11:13:15.300946 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5651 11:13:15.304289 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5652 11:13:15.307580 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5653 11:13:15.307663
5654 11:13:15.307729
5655 11:13:15.307788 ==
5656 11:13:15.310803 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 11:13:15.317175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 11:13:15.317259 ==
5659 11:13:15.317323
5660 11:13:15.317384
5661 11:13:15.317442 TX Vref Scan disable
5662 11:13:15.320956 == TX Byte 0 ==
5663 11:13:15.324295 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5664 11:13:15.331230 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5665 11:13:15.331659 == TX Byte 1 ==
5666 11:13:15.334725 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5667 11:13:15.340919 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5668 11:13:15.341451 ==
5669 11:13:15.344409 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 11:13:15.347472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 11:13:15.347911 ==
5672 11:13:15.348245
5673 11:13:15.348559
5674 11:13:15.350802 TX Vref Scan disable
5675 11:13:15.353937 == TX Byte 0 ==
5676 11:13:15.357264 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5677 11:13:15.360824 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5678 11:13:15.364000 == TX Byte 1 ==
5679 11:13:15.367242 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5680 11:13:15.370670 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5681 11:13:15.371114
5682 11:13:15.371631 [DATLAT]
5683 11:13:15.373874 Freq=933, CH1 RK0
5684 11:13:15.374346
5685 11:13:15.374679 DATLAT Default: 0xd
5686 11:13:15.377774 0, 0xFFFF, sum = 0
5687 11:13:15.380460 1, 0xFFFF, sum = 0
5688 11:13:15.380930 2, 0xFFFF, sum = 0
5689 11:13:15.383927 3, 0xFFFF, sum = 0
5690 11:13:15.384435 4, 0xFFFF, sum = 0
5691 11:13:15.387057 5, 0xFFFF, sum = 0
5692 11:13:15.387579 6, 0xFFFF, sum = 0
5693 11:13:15.390329 7, 0xFFFF, sum = 0
5694 11:13:15.390846 8, 0xFFFF, sum = 0
5695 11:13:15.394124 9, 0xFFFF, sum = 0
5696 11:13:15.394551 10, 0x0, sum = 1
5697 11:13:15.397143 11, 0x0, sum = 2
5698 11:13:15.397572 12, 0x0, sum = 3
5699 11:13:15.400515 13, 0x0, sum = 4
5700 11:13:15.400986 best_step = 11
5701 11:13:15.401322
5702 11:13:15.401628 ==
5703 11:13:15.403874 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 11:13:15.407128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 11:13:15.407648 ==
5706 11:13:15.410436 RX Vref Scan: 1
5707 11:13:15.410860
5708 11:13:15.413680 RX Vref 0 -> 0, step: 1
5709 11:13:15.414105
5710 11:13:15.414442 RX Delay -53 -> 252, step: 4
5711 11:13:15.417089
5712 11:13:15.417516 Set Vref, RX VrefLevel [Byte0]: 51
5713 11:13:15.420413 [Byte1]: 53
5714 11:13:15.425095
5715 11:13:15.425524 Final RX Vref Byte 0 = 51 to rank0
5716 11:13:15.428305 Final RX Vref Byte 1 = 53 to rank0
5717 11:13:15.431954 Final RX Vref Byte 0 = 51 to rank1
5718 11:13:15.435043 Final RX Vref Byte 1 = 53 to rank1==
5719 11:13:15.438026 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 11:13:15.444588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 11:13:15.445107 ==
5722 11:13:15.445539 DQS Delay:
5723 11:13:15.448183 DQS0 = 0, DQS1 = 0
5724 11:13:15.448674 DQM Delay:
5725 11:13:15.449127 DQM0 = 104, DQM1 = 97
5726 11:13:15.451367 DQ Delay:
5727 11:13:15.454663 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5728 11:13:15.457926 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =100
5729 11:13:15.461144 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =90
5730 11:13:15.464362 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =104
5731 11:13:15.465023
5732 11:13:15.465552
5733 11:13:15.474131 [DQSOSCAuto] RK0, (LSB)MR18= 0x172f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5734 11:13:15.474650 CH1 RK0: MR19=505, MR18=172F
5735 11:13:15.480860 CH1_RK0: MR19=0x505, MR18=0x172F, DQSOSC=407, MR23=63, INC=65, DEC=43
5736 11:13:15.481289
5737 11:13:15.484163 ----->DramcWriteLeveling(PI) begin...
5738 11:13:15.484591 ==
5739 11:13:15.487460 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 11:13:15.493978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 11:13:15.494458 ==
5742 11:13:15.497488 Write leveling (Byte 0): 26 => 26
5743 11:13:15.500882 Write leveling (Byte 1): 28 => 28
5744 11:13:15.501287 DramcWriteLeveling(PI) end<-----
5745 11:13:15.501616
5746 11:13:15.504140 ==
5747 11:13:15.507540 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 11:13:15.510865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 11:13:15.511295 ==
5750 11:13:15.514210 [Gating] SW mode calibration
5751 11:13:15.520748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5752 11:13:15.524012 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5753 11:13:15.530785 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 11:13:15.533845 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 11:13:15.537110 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 11:13:15.543665 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 11:13:15.546963 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 11:13:15.550297 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 11:13:15.557667 0 14 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 0) (1 0)
5760 11:13:15.560302 0 14 28 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (1 0)
5761 11:13:15.563775 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
5762 11:13:15.570297 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 11:13:15.573461 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 11:13:15.576625 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 11:13:15.583114 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 11:13:15.586292 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 11:13:15.589585 0 15 24 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
5768 11:13:15.596022 0 15 28 | B1->B0 | 4141 3535 | 0 0 | (0 0) (1 1)
5769 11:13:15.599692 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 11:13:15.602902 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 11:13:15.609548 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 11:13:15.612637 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 11:13:15.615898 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 11:13:15.622652 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 11:13:15.626018 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 11:13:15.629273 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5777 11:13:15.636124 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:13:15.639453 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:13:15.642666 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:13:15.649186 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:13:15.652214 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:13:15.655616 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:13:15.662325 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:13:15.665593 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:13:15.668737 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 11:13:15.675551 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 11:13:15.678761 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 11:13:15.682198 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 11:13:15.688497 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 11:13:15.691911 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 11:13:15.695230 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5792 11:13:15.701662 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 11:13:15.705136 Total UI for P1: 0, mck2ui 16
5794 11:13:15.708305 best dqsien dly found for B0: ( 1, 2, 24)
5795 11:13:15.711577 Total UI for P1: 0, mck2ui 16
5796 11:13:15.715223 best dqsien dly found for B1: ( 1, 2, 26)
5797 11:13:15.718392 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5798 11:13:15.721325 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5799 11:13:15.721880
5800 11:13:15.724586 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5801 11:13:15.727895 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5802 11:13:15.731191 [Gating] SW calibration Done
5803 11:13:15.731700 ==
5804 11:13:15.734480 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 11:13:15.737639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 11:13:15.738156 ==
5807 11:13:15.740934 RX Vref Scan: 0
5808 11:13:15.741360
5809 11:13:15.744379 RX Vref 0 -> 0, step: 1
5810 11:13:15.744877
5811 11:13:15.745227 RX Delay -80 -> 252, step: 8
5812 11:13:15.751063 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5813 11:13:15.754639 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5814 11:13:15.758044 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5815 11:13:15.761275 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5816 11:13:15.764526 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5817 11:13:15.771191 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5818 11:13:15.773912 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5819 11:13:15.777896 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5820 11:13:15.781012 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5821 11:13:15.784275 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5822 11:13:15.790588 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5823 11:13:15.794080 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5824 11:13:15.797112 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5825 11:13:15.800534 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5826 11:13:15.803716 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5827 11:13:15.810227 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5828 11:13:15.810693 ==
5829 11:13:15.813671 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 11:13:15.817247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 11:13:15.817675 ==
5832 11:13:15.818052 DQS Delay:
5833 11:13:15.820241 DQS0 = 0, DQS1 = 0
5834 11:13:15.820695 DQM Delay:
5835 11:13:15.823640 DQM0 = 103, DQM1 = 96
5836 11:13:15.824201 DQ Delay:
5837 11:13:15.826908 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5838 11:13:15.830332 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =103
5839 11:13:15.833731 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5840 11:13:15.837093 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5841 11:13:15.837515
5842 11:13:15.837893
5843 11:13:15.838211 ==
5844 11:13:15.840396 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 11:13:15.847103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 11:13:15.847560 ==
5847 11:13:15.847939
5848 11:13:15.848313
5849 11:13:15.848629 TX Vref Scan disable
5850 11:13:15.850162 == TX Byte 0 ==
5851 11:13:15.853390 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5852 11:13:15.860159 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5853 11:13:15.860610 == TX Byte 1 ==
5854 11:13:15.863522 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5855 11:13:15.870198 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5856 11:13:15.870717 ==
5857 11:13:15.873437 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 11:13:15.876635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 11:13:15.877126 ==
5860 11:13:15.877587
5861 11:13:15.878097
5862 11:13:15.880151 TX Vref Scan disable
5863 11:13:15.880574 == TX Byte 0 ==
5864 11:13:15.886575 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5865 11:13:15.889693 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5866 11:13:15.892878 == TX Byte 1 ==
5867 11:13:15.896425 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5868 11:13:15.899628 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5869 11:13:15.900080
5870 11:13:15.900438 [DATLAT]
5871 11:13:15.903097 Freq=933, CH1 RK1
5872 11:13:15.903648
5873 11:13:15.904111 DATLAT Default: 0xb
5874 11:13:15.906096 0, 0xFFFF, sum = 0
5875 11:13:15.909695 1, 0xFFFF, sum = 0
5876 11:13:15.910186 2, 0xFFFF, sum = 0
5877 11:13:15.912681 3, 0xFFFF, sum = 0
5878 11:13:15.913215 4, 0xFFFF, sum = 0
5879 11:13:15.916201 5, 0xFFFF, sum = 0
5880 11:13:15.916633 6, 0xFFFF, sum = 0
5881 11:13:15.919357 7, 0xFFFF, sum = 0
5882 11:13:15.919787 8, 0xFFFF, sum = 0
5883 11:13:15.922753 9, 0xFFFF, sum = 0
5884 11:13:15.923268 10, 0x0, sum = 1
5885 11:13:15.926492 11, 0x0, sum = 2
5886 11:13:15.926921 12, 0x0, sum = 3
5887 11:13:15.929512 13, 0x0, sum = 4
5888 11:13:15.930041 best_step = 11
5889 11:13:15.930380
5890 11:13:15.930692 ==
5891 11:13:15.932490 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 11:13:15.936264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 11:13:15.939343 ==
5894 11:13:15.939864 RX Vref Scan: 0
5895 11:13:15.940211
5896 11:13:15.942639 RX Vref 0 -> 0, step: 1
5897 11:13:15.943096
5898 11:13:15.945903 RX Delay -53 -> 252, step: 4
5899 11:13:15.949153 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5900 11:13:15.952269 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5901 11:13:15.959186 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5902 11:13:15.962497 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5903 11:13:15.965721 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5904 11:13:15.968953 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5905 11:13:15.972438 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5906 11:13:15.978584 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5907 11:13:15.982292 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5908 11:13:15.985570 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5909 11:13:15.989014 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5910 11:13:15.992108 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5911 11:13:15.995624 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5912 11:13:16.001687 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5913 11:13:16.005125 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5914 11:13:16.008741 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5915 11:13:16.009303 ==
5916 11:13:16.011729 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 11:13:16.015307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 11:13:16.018654 ==
5919 11:13:16.019174 DQS Delay:
5920 11:13:16.019509 DQS0 = 0, DQS1 = 0
5921 11:13:16.021852 DQM Delay:
5922 11:13:16.022271 DQM0 = 105, DQM1 = 97
5923 11:13:16.024983 DQ Delay:
5924 11:13:16.028497 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =102
5925 11:13:16.031817 DQ4 =106, DQ5 =114, DQ6 =114, DQ7 =102
5926 11:13:16.034918 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
5927 11:13:16.037929 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5928 11:13:16.038350
5929 11:13:16.038682
5930 11:13:16.044570 [DQSOSCAuto] RK1, (LSB)MR18= 0x2300, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5931 11:13:16.048333 CH1 RK1: MR19=505, MR18=2300
5932 11:13:16.054800 CH1_RK1: MR19=0x505, MR18=0x2300, DQSOSC=410, MR23=63, INC=64, DEC=42
5933 11:13:16.057889 [RxdqsGatingPostProcess] freq 933
5934 11:13:16.064342 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5935 11:13:16.067765 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 11:13:16.068186 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 11:13:16.070944 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 11:13:16.074286 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 11:13:16.078132 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 11:13:16.081237 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 11:13:16.084605 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 11:13:16.087585 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 11:13:16.091186 Pre-setting of DQS Precalculation
5944 11:13:16.098002 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5945 11:13:16.104160 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5946 11:13:16.110809 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5947 11:13:16.111229
5948 11:13:16.111560
5949 11:13:16.114004 [Calibration Summary] 1866 Mbps
5950 11:13:16.114474 CH 0, Rank 0
5951 11:13:16.117327 SW Impedance : PASS
5952 11:13:16.120436 DUTY Scan : NO K
5953 11:13:16.120881 ZQ Calibration : PASS
5954 11:13:16.124165 Jitter Meter : NO K
5955 11:13:16.127461 CBT Training : PASS
5956 11:13:16.127880 Write leveling : PASS
5957 11:13:16.130851 RX DQS gating : PASS
5958 11:13:16.134002 RX DQ/DQS(RDDQC) : PASS
5959 11:13:16.134421 TX DQ/DQS : PASS
5960 11:13:16.137214 RX DATLAT : PASS
5961 11:13:16.137634 RX DQ/DQS(Engine): PASS
5962 11:13:16.140439 TX OE : NO K
5963 11:13:16.140889 All Pass.
5964 11:13:16.141227
5965 11:13:16.144194 CH 0, Rank 1
5966 11:13:16.144663 SW Impedance : PASS
5967 11:13:16.147192 DUTY Scan : NO K
5968 11:13:16.150776 ZQ Calibration : PASS
5969 11:13:16.151195 Jitter Meter : NO K
5970 11:13:16.154211 CBT Training : PASS
5971 11:13:16.157363 Write leveling : PASS
5972 11:13:16.157782 RX DQS gating : PASS
5973 11:13:16.160752 RX DQ/DQS(RDDQC) : PASS
5974 11:13:16.164334 TX DQ/DQS : PASS
5975 11:13:16.164901 RX DATLAT : PASS
5976 11:13:16.167358 RX DQ/DQS(Engine): PASS
5977 11:13:16.170329 TX OE : NO K
5978 11:13:16.170754 All Pass.
5979 11:13:16.171096
5980 11:13:16.171408 CH 1, Rank 0
5981 11:13:16.173459 SW Impedance : PASS
5982 11:13:16.177255 DUTY Scan : NO K
5983 11:13:16.177675 ZQ Calibration : PASS
5984 11:13:16.180581 Jitter Meter : NO K
5985 11:13:16.183966 CBT Training : PASS
5986 11:13:16.184384 Write leveling : PASS
5987 11:13:16.187236 RX DQS gating : PASS
5988 11:13:16.190239 RX DQ/DQS(RDDQC) : PASS
5989 11:13:16.190660 TX DQ/DQS : PASS
5990 11:13:16.193454 RX DATLAT : PASS
5991 11:13:16.196671 RX DQ/DQS(Engine): PASS
5992 11:13:16.197118 TX OE : NO K
5993 11:13:16.200161 All Pass.
5994 11:13:16.200580
5995 11:13:16.200950 CH 1, Rank 1
5996 11:13:16.203330 SW Impedance : PASS
5997 11:13:16.203751 DUTY Scan : NO K
5998 11:13:16.207128 ZQ Calibration : PASS
5999 11:13:16.210068 Jitter Meter : NO K
6000 11:13:16.210491 CBT Training : PASS
6001 11:13:16.213519 Write leveling : PASS
6002 11:13:16.214035 RX DQS gating : PASS
6003 11:13:16.216456 RX DQ/DQS(RDDQC) : PASS
6004 11:13:16.220087 TX DQ/DQS : PASS
6005 11:13:16.220607 RX DATLAT : PASS
6006 11:13:16.223038 RX DQ/DQS(Engine): PASS
6007 11:13:16.226669 TX OE : NO K
6008 11:13:16.227193 All Pass.
6009 11:13:16.227530
6010 11:13:16.230066 DramC Write-DBI off
6011 11:13:16.230584 PER_BANK_REFRESH: Hybrid Mode
6012 11:13:16.233444 TX_TRACKING: ON
6013 11:13:16.243156 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6014 11:13:16.246524 [FAST_K] Save calibration result to emmc
6015 11:13:16.249637 dramc_set_vcore_voltage set vcore to 650000
6016 11:13:16.250195 Read voltage for 400, 6
6017 11:13:16.253116 Vio18 = 0
6018 11:13:16.253686 Vcore = 650000
6019 11:13:16.254083 Vdram = 0
6020 11:13:16.256150 Vddq = 0
6021 11:13:16.256569 Vmddr = 0
6022 11:13:16.262803 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6023 11:13:16.265889 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6024 11:13:16.269626 MEM_TYPE=3, freq_sel=20
6025 11:13:16.272969 sv_algorithm_assistance_LP4_800
6026 11:13:16.275963 ============ PULL DRAM RESETB DOWN ============
6027 11:13:16.279101 ========== PULL DRAM RESETB DOWN end =========
6028 11:13:16.286049 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6029 11:13:16.289353 ===================================
6030 11:13:16.289774 LPDDR4 DRAM CONFIGURATION
6031 11:13:16.292535 ===================================
6032 11:13:16.295671 EX_ROW_EN[0] = 0x0
6033 11:13:16.299106 EX_ROW_EN[1] = 0x0
6034 11:13:16.299526 LP4Y_EN = 0x0
6035 11:13:16.302256 WORK_FSP = 0x0
6036 11:13:16.302674 WL = 0x2
6037 11:13:16.305803 RL = 0x2
6038 11:13:16.306221 BL = 0x2
6039 11:13:16.309083 RPST = 0x0
6040 11:13:16.309525 RD_PRE = 0x0
6041 11:13:16.312470 WR_PRE = 0x1
6042 11:13:16.312922 WR_PST = 0x0
6043 11:13:16.316176 DBI_WR = 0x0
6044 11:13:16.316699 DBI_RD = 0x0
6045 11:13:16.319077 OTF = 0x1
6046 11:13:16.322222 ===================================
6047 11:13:16.325330 ===================================
6048 11:13:16.325754 ANA top config
6049 11:13:16.329211 ===================================
6050 11:13:16.332285 DLL_ASYNC_EN = 0
6051 11:13:16.335524 ALL_SLAVE_EN = 1
6052 11:13:16.338912 NEW_RANK_MODE = 1
6053 11:13:16.339439 DLL_IDLE_MODE = 1
6054 11:13:16.342454 LP45_APHY_COMB_EN = 1
6055 11:13:16.346058 TX_ODT_DIS = 1
6056 11:13:16.348872 NEW_8X_MODE = 1
6057 11:13:16.352035 ===================================
6058 11:13:16.356061 ===================================
6059 11:13:16.356589 data_rate = 800
6060 11:13:16.359126 CKR = 1
6061 11:13:16.362404 DQ_P2S_RATIO = 4
6062 11:13:16.365311 ===================================
6063 11:13:16.368858 CA_P2S_RATIO = 4
6064 11:13:16.372335 DQ_CA_OPEN = 0
6065 11:13:16.375572 DQ_SEMI_OPEN = 1
6066 11:13:16.376000 CA_SEMI_OPEN = 1
6067 11:13:16.378823 CA_FULL_RATE = 0
6068 11:13:16.382442 DQ_CKDIV4_EN = 0
6069 11:13:16.385424 CA_CKDIV4_EN = 1
6070 11:13:16.388713 CA_PREDIV_EN = 0
6071 11:13:16.391904 PH8_DLY = 0
6072 11:13:16.392324 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6073 11:13:16.395336 DQ_AAMCK_DIV = 0
6074 11:13:16.398871 CA_AAMCK_DIV = 0
6075 11:13:16.402202 CA_ADMCK_DIV = 4
6076 11:13:16.405243 DQ_TRACK_CA_EN = 0
6077 11:13:16.408592 CA_PICK = 800
6078 11:13:16.411956 CA_MCKIO = 400
6079 11:13:16.412377 MCKIO_SEMI = 400
6080 11:13:16.415202 PLL_FREQ = 3016
6081 11:13:16.418229 DQ_UI_PI_RATIO = 32
6082 11:13:16.421905 CA_UI_PI_RATIO = 32
6083 11:13:16.425014 ===================================
6084 11:13:16.428362 ===================================
6085 11:13:16.431696 memory_type:LPDDR4
6086 11:13:16.432114 GP_NUM : 10
6087 11:13:16.434874 SRAM_EN : 1
6088 11:13:16.438427 MD32_EN : 0
6089 11:13:16.441511 ===================================
6090 11:13:16.441935 [ANA_INIT] >>>>>>>>>>>>>>
6091 11:13:16.444837 <<<<<< [CONFIGURE PHASE]: ANA_TX
6092 11:13:16.448612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6093 11:13:16.451379 ===================================
6094 11:13:16.454669 data_rate = 800,PCW = 0X7400
6095 11:13:16.458320 ===================================
6096 11:13:16.461498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6097 11:13:16.468046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 11:13:16.477731 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 11:13:16.484275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6100 11:13:16.487891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6101 11:13:16.491101 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6102 11:13:16.491525 [ANA_INIT] flow start
6103 11:13:16.494410 [ANA_INIT] PLL >>>>>>>>
6104 11:13:16.497690 [ANA_INIT] PLL <<<<<<<<
6105 11:13:16.500882 [ANA_INIT] MIDPI >>>>>>>>
6106 11:13:16.501299 [ANA_INIT] MIDPI <<<<<<<<
6107 11:13:16.504274 [ANA_INIT] DLL >>>>>>>>
6108 11:13:16.504696 [ANA_INIT] flow end
6109 11:13:16.510582 ============ LP4 DIFF to SE enter ============
6110 11:13:16.513899 ============ LP4 DIFF to SE exit ============
6111 11:13:16.517062 [ANA_INIT] <<<<<<<<<<<<<
6112 11:13:16.520840 [Flow] Enable top DCM control >>>>>
6113 11:13:16.524112 [Flow] Enable top DCM control <<<<<
6114 11:13:16.527454 Enable DLL master slave shuffle
6115 11:13:16.530538 ==============================================================
6116 11:13:16.533891 Gating Mode config
6117 11:13:16.537122 ==============================================================
6118 11:13:16.540295 Config description:
6119 11:13:16.550386 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6120 11:13:16.557087 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6121 11:13:16.560243 SELPH_MODE 0: By rank 1: By Phase
6122 11:13:16.566865 ==============================================================
6123 11:13:16.569947 GAT_TRACK_EN = 0
6124 11:13:16.573290 RX_GATING_MODE = 2
6125 11:13:16.576439 RX_GATING_TRACK_MODE = 2
6126 11:13:16.580200 SELPH_MODE = 1
6127 11:13:16.583474 PICG_EARLY_EN = 1
6128 11:13:16.586797 VALID_LAT_VALUE = 1
6129 11:13:16.589847 ==============================================================
6130 11:13:16.593404 Enter into Gating configuration >>>>
6131 11:13:16.596458 Exit from Gating configuration <<<<
6132 11:13:16.599766 Enter into DVFS_PRE_config >>>>>
6133 11:13:16.613153 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6134 11:13:16.613608 Exit from DVFS_PRE_config <<<<<
6135 11:13:16.616413 Enter into PICG configuration >>>>
6136 11:13:16.619681 Exit from PICG configuration <<<<
6137 11:13:16.622942 [RX_INPUT] configuration >>>>>
6138 11:13:16.625919 [RX_INPUT] configuration <<<<<
6139 11:13:16.632947 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6140 11:13:16.636225 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6141 11:13:16.642779 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 11:13:16.649333 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 11:13:16.656146 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 11:13:16.662756 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 11:13:16.666339 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6146 11:13:16.669293 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6147 11:13:16.672750 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6148 11:13:16.679368 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6149 11:13:16.682693 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6150 11:13:16.685748 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6151 11:13:16.689434 ===================================
6152 11:13:16.692266 LPDDR4 DRAM CONFIGURATION
6153 11:13:16.695462 ===================================
6154 11:13:16.699612 EX_ROW_EN[0] = 0x0
6155 11:13:16.700137 EX_ROW_EN[1] = 0x0
6156 11:13:16.702402 LP4Y_EN = 0x0
6157 11:13:16.702824 WORK_FSP = 0x0
6158 11:13:16.705542 WL = 0x2
6159 11:13:16.705969 RL = 0x2
6160 11:13:16.709300 BL = 0x2
6161 11:13:16.709815 RPST = 0x0
6162 11:13:16.712420 RD_PRE = 0x0
6163 11:13:16.712983 WR_PRE = 0x1
6164 11:13:16.715909 WR_PST = 0x0
6165 11:13:16.716429 DBI_WR = 0x0
6166 11:13:16.719212 DBI_RD = 0x0
6167 11:13:16.719740 OTF = 0x1
6168 11:13:16.722398 ===================================
6169 11:13:16.728990 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6170 11:13:16.732489 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6171 11:13:16.735679 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 11:13:16.738759 ===================================
6173 11:13:16.742223 LPDDR4 DRAM CONFIGURATION
6174 11:13:16.745018 ===================================
6175 11:13:16.748446 EX_ROW_EN[0] = 0x10
6176 11:13:16.748887 EX_ROW_EN[1] = 0x0
6177 11:13:16.752064 LP4Y_EN = 0x0
6178 11:13:16.752483 WORK_FSP = 0x0
6179 11:13:16.755134 WL = 0x2
6180 11:13:16.755553 RL = 0x2
6181 11:13:16.758447 BL = 0x2
6182 11:13:16.758867 RPST = 0x0
6183 11:13:16.761627 RD_PRE = 0x0
6184 11:13:16.762045 WR_PRE = 0x1
6185 11:13:16.764915 WR_PST = 0x0
6186 11:13:16.765336 DBI_WR = 0x0
6187 11:13:16.768373 DBI_RD = 0x0
6188 11:13:16.768816 OTF = 0x1
6189 11:13:16.771649 ===================================
6190 11:13:16.778367 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6191 11:13:16.783359 nWR fixed to 30
6192 11:13:16.786838 [ModeRegInit_LP4] CH0 RK0
6193 11:13:16.787287 [ModeRegInit_LP4] CH0 RK1
6194 11:13:16.789916 [ModeRegInit_LP4] CH1 RK0
6195 11:13:16.793306 [ModeRegInit_LP4] CH1 RK1
6196 11:13:16.793723 match AC timing 19
6197 11:13:16.799958 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6198 11:13:16.802939 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6199 11:13:16.806469 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6200 11:13:16.812728 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6201 11:13:16.816022 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6202 11:13:16.816567 ==
6203 11:13:16.819123 Dram Type= 6, Freq= 0, CH_0, rank 0
6204 11:13:16.822844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6205 11:13:16.823450 ==
6206 11:13:16.829213 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6207 11:13:16.835701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6208 11:13:16.838620 [CA 0] Center 36 (8~64) winsize 57
6209 11:13:16.841863 [CA 1] Center 36 (8~64) winsize 57
6210 11:13:16.845362 [CA 2] Center 36 (8~64) winsize 57
6211 11:13:16.848627 [CA 3] Center 36 (8~64) winsize 57
6212 11:13:16.852298 [CA 4] Center 36 (8~64) winsize 57
6213 11:13:16.852410 [CA 5] Center 36 (8~64) winsize 57
6214 11:13:16.855415
6215 11:13:16.858476 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6216 11:13:16.858577
6217 11:13:16.861968 [CATrainingPosCal] consider 1 rank data
6218 11:13:16.865100 u2DelayCellTimex100 = 270/100 ps
6219 11:13:16.868245 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 11:13:16.871594 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 11:13:16.874751 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 11:13:16.878108 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 11:13:16.881765 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 11:13:16.884680 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 11:13:16.884818
6226 11:13:16.888189 CA PerBit enable=1, Macro0, CA PI delay=36
6227 11:13:16.891645
6228 11:13:16.891762 [CBTSetCACLKResult] CA Dly = 36
6229 11:13:16.894893 CS Dly: 1 (0~32)
6230 11:13:16.895006 ==
6231 11:13:16.898027 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 11:13:16.901436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 11:13:16.901537 ==
6234 11:13:16.907611 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 11:13:16.914586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 11:13:16.917914 [CA 0] Center 36 (8~64) winsize 57
6237 11:13:16.921201 [CA 1] Center 36 (8~64) winsize 57
6238 11:13:16.924641 [CA 2] Center 36 (8~64) winsize 57
6239 11:13:16.927996 [CA 3] Center 36 (8~64) winsize 57
6240 11:13:16.928067 [CA 4] Center 36 (8~64) winsize 57
6241 11:13:16.931305 [CA 5] Center 36 (8~64) winsize 57
6242 11:13:16.931377
6243 11:13:16.937712 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 11:13:16.937791
6245 11:13:16.941162 [CATrainingPosCal] consider 2 rank data
6246 11:13:16.944065 u2DelayCellTimex100 = 270/100 ps
6247 11:13:16.947889 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 11:13:16.951093 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 11:13:16.954367 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 11:13:16.957515 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 11:13:16.960986 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 11:13:16.964211 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 11:13:16.964320
6254 11:13:16.967585 CA PerBit enable=1, Macro0, CA PI delay=36
6255 11:13:16.967786
6256 11:13:16.971009 [CBTSetCACLKResult] CA Dly = 36
6257 11:13:16.974714 CS Dly: 1 (0~32)
6258 11:13:16.974933
6259 11:13:16.977818 ----->DramcWriteLeveling(PI) begin...
6260 11:13:16.978062 ==
6261 11:13:16.981127 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 11:13:16.984445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 11:13:16.984702 ==
6264 11:13:16.987647 Write leveling (Byte 0): 40 => 8
6265 11:13:16.990989 Write leveling (Byte 1): 32 => 0
6266 11:13:16.994588 DramcWriteLeveling(PI) end<-----
6267 11:13:16.994916
6268 11:13:16.995118 ==
6269 11:13:16.997410 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 11:13:17.000671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 11:13:17.001086 ==
6272 11:13:17.004025 [Gating] SW mode calibration
6273 11:13:17.011057 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6274 11:13:17.017664 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6275 11:13:17.021100 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 11:13:17.027456 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 11:13:17.030879 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 11:13:17.034476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 11:13:17.040759 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 11:13:17.043991 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 11:13:17.047566 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 11:13:17.050815 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 11:13:17.057458 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 11:13:17.060517 Total UI for P1: 0, mck2ui 16
6285 11:13:17.064057 best dqsien dly found for B0: ( 0, 14, 24)
6286 11:13:17.067252 Total UI for P1: 0, mck2ui 16
6287 11:13:17.070349 best dqsien dly found for B1: ( 0, 14, 24)
6288 11:13:17.073645 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6289 11:13:17.077321 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6290 11:13:17.077812
6291 11:13:17.080107 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 11:13:17.083827 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 11:13:17.087051 [Gating] SW calibration Done
6294 11:13:17.087618 ==
6295 11:13:17.089975 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 11:13:17.093678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 11:13:17.096602 ==
6298 11:13:17.097115 RX Vref Scan: 0
6299 11:13:17.097499
6300 11:13:17.099689 RX Vref 0 -> 0, step: 1
6301 11:13:17.100101
6302 11:13:17.102858 RX Delay -410 -> 252, step: 16
6303 11:13:17.106220 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6304 11:13:17.109620 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6305 11:13:17.113068 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6306 11:13:17.119808 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6307 11:13:17.122971 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6308 11:13:17.126395 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6309 11:13:17.129697 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6310 11:13:17.136424 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6311 11:13:17.139355 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6312 11:13:17.142893 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6313 11:13:17.146187 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6314 11:13:17.152990 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6315 11:13:17.156276 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6316 11:13:17.159022 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6317 11:13:17.165961 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6318 11:13:17.169295 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6319 11:13:17.169716 ==
6320 11:13:17.172419 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 11:13:17.175879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 11:13:17.176297 ==
6323 11:13:17.179050 DQS Delay:
6324 11:13:17.179512 DQS0 = 27, DQS1 = 43
6325 11:13:17.179846 DQM Delay:
6326 11:13:17.182400 DQM0 = 12, DQM1 = 13
6327 11:13:17.182815 DQ Delay:
6328 11:13:17.185652 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6329 11:13:17.189015 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6330 11:13:17.192246 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6331 11:13:17.195493 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6332 11:13:17.195986
6333 11:13:17.196325
6334 11:13:17.196707 ==
6335 11:13:17.198708 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 11:13:17.205259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 11:13:17.205675 ==
6338 11:13:17.206000
6339 11:13:17.206308
6340 11:13:17.206599 TX Vref Scan disable
6341 11:13:17.208877 == TX Byte 0 ==
6342 11:13:17.212302 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 11:13:17.215515 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 11:13:17.218977 == TX Byte 1 ==
6345 11:13:17.222214 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6346 11:13:17.225469 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6347 11:13:17.225884 ==
6348 11:13:17.228361 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 11:13:17.235592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 11:13:17.236172 ==
6351 11:13:17.236507
6352 11:13:17.236942
6353 11:13:17.237256 TX Vref Scan disable
6354 11:13:17.238376 == TX Byte 0 ==
6355 11:13:17.241757 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 11:13:17.245297 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 11:13:17.248733 == TX Byte 1 ==
6358 11:13:17.251762 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6359 11:13:17.254956 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6360 11:13:17.258186
6361 11:13:17.258592 [DATLAT]
6362 11:13:17.258914 Freq=400, CH0 RK0
6363 11:13:17.259217
6364 11:13:17.261999 DATLAT Default: 0xf
6365 11:13:17.262407 0, 0xFFFF, sum = 0
6366 11:13:17.264836 1, 0xFFFF, sum = 0
6367 11:13:17.265257 2, 0xFFFF, sum = 0
6368 11:13:17.268498 3, 0xFFFF, sum = 0
6369 11:13:17.272074 4, 0xFFFF, sum = 0
6370 11:13:17.272589 5, 0xFFFF, sum = 0
6371 11:13:17.275259 6, 0xFFFF, sum = 0
6372 11:13:17.275782 7, 0xFFFF, sum = 0
6373 11:13:17.278360 8, 0xFFFF, sum = 0
6374 11:13:17.278782 9, 0xFFFF, sum = 0
6375 11:13:17.281405 10, 0xFFFF, sum = 0
6376 11:13:17.281824 11, 0xFFFF, sum = 0
6377 11:13:17.284716 12, 0xFFFF, sum = 0
6378 11:13:17.285277 13, 0x0, sum = 1
6379 11:13:17.287968 14, 0x0, sum = 2
6380 11:13:17.288380 15, 0x0, sum = 3
6381 11:13:17.291681 16, 0x0, sum = 4
6382 11:13:17.292096 best_step = 14
6383 11:13:17.292424
6384 11:13:17.292720 ==
6385 11:13:17.294876 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 11:13:17.298182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 11:13:17.301459 ==
6388 11:13:17.301867 RX Vref Scan: 1
6389 11:13:17.302191
6390 11:13:17.304686 RX Vref 0 -> 0, step: 1
6391 11:13:17.305133
6392 11:13:17.307883 RX Delay -327 -> 252, step: 8
6393 11:13:17.308291
6394 11:13:17.308610 Set Vref, RX VrefLevel [Byte0]: 57
6395 11:13:17.311156 [Byte1]: 48
6396 11:13:17.317113
6397 11:13:17.317556 Final RX Vref Byte 0 = 57 to rank0
6398 11:13:17.320180 Final RX Vref Byte 1 = 48 to rank0
6399 11:13:17.323648 Final RX Vref Byte 0 = 57 to rank1
6400 11:13:17.326835 Final RX Vref Byte 1 = 48 to rank1==
6401 11:13:17.329955 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 11:13:17.336940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 11:13:17.337356 ==
6404 11:13:17.337680 DQS Delay:
6405 11:13:17.340134 DQS0 = 24, DQS1 = 48
6406 11:13:17.340542 DQM Delay:
6407 11:13:17.340896 DQM0 = 8, DQM1 = 15
6408 11:13:17.343873 DQ Delay:
6409 11:13:17.347076 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6410 11:13:17.347509 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6411 11:13:17.350117 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6412 11:13:17.353077 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6413 11:13:17.353668
6414 11:13:17.354025
6415 11:13:17.363290 [DQSOSCAuto] RK0, (LSB)MR18= 0xafa7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6416 11:13:17.367455 CH0 RK0: MR19=C0C, MR18=AFA7
6417 11:13:17.373675 CH0_RK0: MR19=0xC0C, MR18=0xAFA7, DQSOSC=388, MR23=63, INC=392, DEC=261
6418 11:13:17.374218 ==
6419 11:13:17.377018 Dram Type= 6, Freq= 0, CH_0, rank 1
6420 11:13:17.380191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 11:13:17.380635 ==
6422 11:13:17.383432 [Gating] SW mode calibration
6423 11:13:17.389838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6424 11:13:17.393716 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6425 11:13:17.400538 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 11:13:17.403706 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 11:13:17.407110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 11:13:17.413423 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 11:13:17.416913 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 11:13:17.420340 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 11:13:17.426911 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 11:13:17.429905 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 11:13:17.432945 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 11:13:17.436145 Total UI for P1: 0, mck2ui 16
6435 11:13:17.439959 best dqsien dly found for B0: ( 0, 14, 24)
6436 11:13:17.443195 Total UI for P1: 0, mck2ui 16
6437 11:13:17.446205 best dqsien dly found for B1: ( 0, 14, 24)
6438 11:13:17.449371 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6439 11:13:17.456238 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6440 11:13:17.456796
6441 11:13:17.459323 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 11:13:17.462736 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 11:13:17.465964 [Gating] SW calibration Done
6444 11:13:17.466385 ==
6445 11:13:17.469329 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 11:13:17.472680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 11:13:17.473260 ==
6448 11:13:17.475979 RX Vref Scan: 0
6449 11:13:17.476509
6450 11:13:17.476890 RX Vref 0 -> 0, step: 1
6451 11:13:17.477214
6452 11:13:17.479272 RX Delay -410 -> 252, step: 16
6453 11:13:17.485513 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6454 11:13:17.488844 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6455 11:13:17.492076 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6456 11:13:17.495411 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6457 11:13:17.502119 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6458 11:13:17.505117 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6459 11:13:17.508816 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6460 11:13:17.512148 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6461 11:13:17.518404 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6462 11:13:17.521817 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6463 11:13:17.524713 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6464 11:13:17.527830 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6465 11:13:17.534914 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6466 11:13:17.537975 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6467 11:13:17.541417 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6468 11:13:17.548116 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6469 11:13:17.548540 ==
6470 11:13:17.551538 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 11:13:17.554604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 11:13:17.555045 ==
6473 11:13:17.555379 DQS Delay:
6474 11:13:17.558152 DQS0 = 27, DQS1 = 43
6475 11:13:17.558569 DQM Delay:
6476 11:13:17.561629 DQM0 = 9, DQM1 = 16
6477 11:13:17.562046 DQ Delay:
6478 11:13:17.564483 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6479 11:13:17.567810 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6480 11:13:17.571220 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6481 11:13:17.574605 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6482 11:13:17.575028
6483 11:13:17.575356
6484 11:13:17.575665 ==
6485 11:13:17.577545 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 11:13:17.581123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 11:13:17.581549 ==
6488 11:13:17.582110
6489 11:13:17.582454
6490 11:13:17.584449 TX Vref Scan disable
6491 11:13:17.584904 == TX Byte 0 ==
6492 11:13:17.590768 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6493 11:13:17.594110 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6494 11:13:17.594532 == TX Byte 1 ==
6495 11:13:17.600720 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6496 11:13:17.603944 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6497 11:13:17.604364 ==
6498 11:13:17.607286 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 11:13:17.610386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 11:13:17.610809 ==
6501 11:13:17.611145
6502 11:13:17.611244
6503 11:13:17.613561 TX Vref Scan disable
6504 11:13:17.616825 == TX Byte 0 ==
6505 11:13:17.620417 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6506 11:13:17.623786 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6507 11:13:17.627318 == TX Byte 1 ==
6508 11:13:17.630573 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6509 11:13:17.633577 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6510 11:13:17.634000
6511 11:13:17.634332 [DATLAT]
6512 11:13:17.637292 Freq=400, CH0 RK1
6513 11:13:17.637713
6514 11:13:17.638046 DATLAT Default: 0xe
6515 11:13:17.640625 0, 0xFFFF, sum = 0
6516 11:13:17.641196 1, 0xFFFF, sum = 0
6517 11:13:17.643664 2, 0xFFFF, sum = 0
6518 11:13:17.644097 3, 0xFFFF, sum = 0
6519 11:13:17.647369 4, 0xFFFF, sum = 0
6520 11:13:17.650421 5, 0xFFFF, sum = 0
6521 11:13:17.650847 6, 0xFFFF, sum = 0
6522 11:13:17.653809 7, 0xFFFF, sum = 0
6523 11:13:17.654235 8, 0xFFFF, sum = 0
6524 11:13:17.657351 9, 0xFFFF, sum = 0
6525 11:13:17.657802 10, 0xFFFF, sum = 0
6526 11:13:17.660362 11, 0xFFFF, sum = 0
6527 11:13:17.660815 12, 0xFFFF, sum = 0
6528 11:13:17.663614 13, 0x0, sum = 1
6529 11:13:17.664040 14, 0x0, sum = 2
6530 11:13:17.666794 15, 0x0, sum = 3
6531 11:13:17.667216 16, 0x0, sum = 4
6532 11:13:17.670352 best_step = 14
6533 11:13:17.670773
6534 11:13:17.671102 ==
6535 11:13:17.673514 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 11:13:17.676880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 11:13:17.677305 ==
6538 11:13:17.677638 RX Vref Scan: 0
6539 11:13:17.680202
6540 11:13:17.680623 RX Vref 0 -> 0, step: 1
6541 11:13:17.681000
6542 11:13:17.683212 RX Delay -327 -> 252, step: 8
6543 11:13:17.690863 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6544 11:13:17.694304 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6545 11:13:17.697467 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6546 11:13:17.701391 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6547 11:13:17.707972 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6548 11:13:17.711251 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6549 11:13:17.714375 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6550 11:13:17.717381 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6551 11:13:17.724478 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6552 11:13:17.727669 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6553 11:13:17.731014 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6554 11:13:17.734272 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6555 11:13:17.740349 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6556 11:13:17.744018 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6557 11:13:17.746957 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6558 11:13:17.754021 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6559 11:13:17.754553 ==
6560 11:13:17.757193 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 11:13:17.760604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 11:13:17.761176 ==
6563 11:13:17.761515 DQS Delay:
6564 11:13:17.763961 DQS0 = 28, DQS1 = 40
6565 11:13:17.764499 DQM Delay:
6566 11:13:17.766840 DQM0 = 11, DQM1 = 12
6567 11:13:17.767359 DQ Delay:
6568 11:13:17.770483 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6569 11:13:17.773444 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6570 11:13:17.777241 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6571 11:13:17.780422 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6572 11:13:17.781174
6573 11:13:17.781604
6574 11:13:17.787082 [DQSOSCAuto] RK1, (LSB)MR18= 0xb76b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6575 11:13:17.790284 CH0 RK1: MR19=C0C, MR18=B76B
6576 11:13:17.796927 CH0_RK1: MR19=0xC0C, MR18=0xB76B, DQSOSC=387, MR23=63, INC=394, DEC=262
6577 11:13:17.800436 [RxdqsGatingPostProcess] freq 400
6578 11:13:17.806916 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6579 11:13:17.807446 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 11:13:17.810381 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 11:13:17.813316 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 11:13:17.816895 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 11:13:17.820510 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 11:13:17.823939 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 11:13:17.827278 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 11:13:17.829982 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 11:13:17.833420 Pre-setting of DQS Precalculation
6588 11:13:17.840121 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6589 11:13:17.840745 ==
6590 11:13:17.843431 Dram Type= 6, Freq= 0, CH_1, rank 0
6591 11:13:17.846932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 11:13:17.847512 ==
6593 11:13:17.853158 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6594 11:13:17.856433 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6595 11:13:17.860287 [CA 0] Center 36 (8~64) winsize 57
6596 11:13:17.863132 [CA 1] Center 36 (8~64) winsize 57
6597 11:13:17.866827 [CA 2] Center 36 (8~64) winsize 57
6598 11:13:17.869903 [CA 3] Center 36 (8~64) winsize 57
6599 11:13:17.872937 [CA 4] Center 36 (8~64) winsize 57
6600 11:13:17.876578 [CA 5] Center 36 (8~64) winsize 57
6601 11:13:17.877155
6602 11:13:17.879905 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6603 11:13:17.880501
6604 11:13:17.882654 [CATrainingPosCal] consider 1 rank data
6605 11:13:17.885818 u2DelayCellTimex100 = 270/100 ps
6606 11:13:17.889445 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 11:13:17.892621 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 11:13:17.899498 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 11:13:17.902763 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 11:13:17.905848 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 11:13:17.909487 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 11:13:17.909909
6613 11:13:17.912791 CA PerBit enable=1, Macro0, CA PI delay=36
6614 11:13:17.913157
6615 11:13:17.915681 [CBTSetCACLKResult] CA Dly = 36
6616 11:13:17.915763 CS Dly: 1 (0~32)
6617 11:13:17.918862 ==
6618 11:13:17.918950 Dram Type= 6, Freq= 0, CH_1, rank 1
6619 11:13:17.925337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 11:13:17.925420 ==
6621 11:13:17.928524 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 11:13:17.935189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6623 11:13:17.938895 [CA 0] Center 36 (8~64) winsize 57
6624 11:13:17.942209 [CA 1] Center 36 (8~64) winsize 57
6625 11:13:17.945260 [CA 2] Center 36 (8~64) winsize 57
6626 11:13:17.948687 [CA 3] Center 36 (8~64) winsize 57
6627 11:13:17.952117 [CA 4] Center 36 (8~64) winsize 57
6628 11:13:17.955232 [CA 5] Center 36 (8~64) winsize 57
6629 11:13:17.955402
6630 11:13:17.958419 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6631 11:13:17.958520
6632 11:13:17.961769 [CATrainingPosCal] consider 2 rank data
6633 11:13:17.965174 u2DelayCellTimex100 = 270/100 ps
6634 11:13:17.968451 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 11:13:17.971755 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 11:13:17.974982 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 11:13:17.981411 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 11:13:17.984689 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 11:13:17.988143 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 11:13:17.988316
6641 11:13:17.991367 CA PerBit enable=1, Macro0, CA PI delay=36
6642 11:13:17.991541
6643 11:13:17.994839 [CBTSetCACLKResult] CA Dly = 36
6644 11:13:17.995041 CS Dly: 1 (0~32)
6645 11:13:17.995200
6646 11:13:17.998108 ----->DramcWriteLeveling(PI) begin...
6647 11:13:17.998403 ==
6648 11:13:18.001291 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 11:13:18.008278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 11:13:18.008580 ==
6651 11:13:18.011266 Write leveling (Byte 0): 40 => 8
6652 11:13:18.014699 Write leveling (Byte 1): 32 => 0
6653 11:13:18.015234 DramcWriteLeveling(PI) end<-----
6654 11:13:18.017785
6655 11:13:18.018204 ==
6656 11:13:18.021483 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 11:13:18.024865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 11:13:18.025290 ==
6659 11:13:18.028010 [Gating] SW mode calibration
6660 11:13:18.035123 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6661 11:13:18.038269 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6662 11:13:18.044476 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 11:13:18.048050 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 11:13:18.050964 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 11:13:18.057562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 11:13:18.061081 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 11:13:18.064152 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 11:13:18.071072 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 11:13:18.074331 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 11:13:18.077657 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 11:13:18.080891 Total UI for P1: 0, mck2ui 16
6672 11:13:18.084261 best dqsien dly found for B0: ( 0, 14, 24)
6673 11:13:18.087415 Total UI for P1: 0, mck2ui 16
6674 11:13:18.090512 best dqsien dly found for B1: ( 0, 14, 24)
6675 11:13:18.097006 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6676 11:13:18.100549 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6677 11:13:18.101120
6678 11:13:18.103905 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 11:13:18.107104 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 11:13:18.110450 [Gating] SW calibration Done
6681 11:13:18.111111 ==
6682 11:13:18.113549 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 11:13:18.116998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 11:13:18.117419 ==
6685 11:13:18.120231 RX Vref Scan: 0
6686 11:13:18.120649
6687 11:13:18.121015 RX Vref 0 -> 0, step: 1
6688 11:13:18.121328
6689 11:13:18.123749 RX Delay -410 -> 252, step: 16
6690 11:13:18.130274 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6691 11:13:18.133650 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6692 11:13:18.136949 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6693 11:13:18.140407 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6694 11:13:18.146702 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6695 11:13:18.149798 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6696 11:13:18.153112 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6697 11:13:18.156849 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6698 11:13:18.163171 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6699 11:13:18.166427 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6700 11:13:18.169763 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6701 11:13:18.173247 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6702 11:13:18.179384 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6703 11:13:18.182685 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6704 11:13:18.185868 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6705 11:13:18.192677 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6706 11:13:18.193276 ==
6707 11:13:18.196101 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 11:13:18.199736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 11:13:18.200264 ==
6710 11:13:18.200600 DQS Delay:
6711 11:13:18.202674 DQS0 = 27, DQS1 = 43
6712 11:13:18.203209 DQM Delay:
6713 11:13:18.206034 DQM0 = 5, DQM1 = 15
6714 11:13:18.206453 DQ Delay:
6715 11:13:18.209306 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6716 11:13:18.212620 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6717 11:13:18.215870 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6718 11:13:18.219215 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6719 11:13:18.219758
6720 11:13:18.220098
6721 11:13:18.220404 ==
6722 11:13:18.222628 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 11:13:18.225604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 11:13:18.226037 ==
6725 11:13:18.226375
6726 11:13:18.226685
6727 11:13:18.229135 TX Vref Scan disable
6728 11:13:18.229570 == TX Byte 0 ==
6729 11:13:18.235950 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 11:13:18.239300 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 11:13:18.239831 == TX Byte 1 ==
6732 11:13:18.245695 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6733 11:13:18.248866 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6734 11:13:18.249296 ==
6735 11:13:18.252207 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 11:13:18.255400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 11:13:18.255932 ==
6738 11:13:18.256336
6739 11:13:18.256962
6740 11:13:18.258371 TX Vref Scan disable
6741 11:13:18.261910 == TX Byte 0 ==
6742 11:13:18.265131 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 11:13:18.268170 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 11:13:18.271406 == TX Byte 1 ==
6745 11:13:18.274956 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6746 11:13:18.277971 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6747 11:13:18.278058
6748 11:13:18.278153 [DATLAT]
6749 11:13:18.281245 Freq=400, CH1 RK0
6750 11:13:18.281372
6751 11:13:18.284425 DATLAT Default: 0xf
6752 11:13:18.284508 0, 0xFFFF, sum = 0
6753 11:13:18.287989 1, 0xFFFF, sum = 0
6754 11:13:18.288089 2, 0xFFFF, sum = 0
6755 11:13:18.291489 3, 0xFFFF, sum = 0
6756 11:13:18.291601 4, 0xFFFF, sum = 0
6757 11:13:18.294363 5, 0xFFFF, sum = 0
6758 11:13:18.294438 6, 0xFFFF, sum = 0
6759 11:13:18.298226 7, 0xFFFF, sum = 0
6760 11:13:18.298303 8, 0xFFFF, sum = 0
6761 11:13:18.301445 9, 0xFFFF, sum = 0
6762 11:13:18.301523 10, 0xFFFF, sum = 0
6763 11:13:18.304704 11, 0xFFFF, sum = 0
6764 11:13:18.304842 12, 0xFFFF, sum = 0
6765 11:13:18.307698 13, 0x0, sum = 1
6766 11:13:18.307774 14, 0x0, sum = 2
6767 11:13:18.311237 15, 0x0, sum = 3
6768 11:13:18.311323 16, 0x0, sum = 4
6769 11:13:18.314215 best_step = 14
6770 11:13:18.314305
6771 11:13:18.314372 ==
6772 11:13:18.317558 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 11:13:18.321049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 11:13:18.321127 ==
6775 11:13:18.324407 RX Vref Scan: 1
6776 11:13:18.324482
6777 11:13:18.324544 RX Vref 0 -> 0, step: 1
6778 11:13:18.324602
6779 11:13:18.327559 RX Delay -327 -> 252, step: 8
6780 11:13:18.327638
6781 11:13:18.331061 Set Vref, RX VrefLevel [Byte0]: 51
6782 11:13:18.334484 [Byte1]: 53
6783 11:13:18.338893
6784 11:13:18.338981 Final RX Vref Byte 0 = 51 to rank0
6785 11:13:18.342643 Final RX Vref Byte 1 = 53 to rank0
6786 11:13:18.345877 Final RX Vref Byte 0 = 51 to rank1
6787 11:13:18.349187 Final RX Vref Byte 1 = 53 to rank1==
6788 11:13:18.352504 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 11:13:18.358771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 11:13:18.358896 ==
6791 11:13:18.358994 DQS Delay:
6792 11:13:18.362215 DQS0 = 32, DQS1 = 40
6793 11:13:18.362351 DQM Delay:
6794 11:13:18.362458 DQM0 = 12, DQM1 = 13
6795 11:13:18.365129 DQ Delay:
6796 11:13:18.368329 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6797 11:13:18.368413 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6798 11:13:18.372136 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6799 11:13:18.375529 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6800 11:13:18.378778
6801 11:13:18.379197
6802 11:13:18.385242 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6803 11:13:18.388991 CH1 RK0: MR19=C0C, MR18=8EC7
6804 11:13:18.395389 CH1_RK0: MR19=0xC0C, MR18=0x8EC7, DQSOSC=385, MR23=63, INC=398, DEC=265
6805 11:13:18.395813 ==
6806 11:13:18.398720 Dram Type= 6, Freq= 0, CH_1, rank 1
6807 11:13:18.401956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 11:13:18.402419 ==
6809 11:13:18.405221 [Gating] SW mode calibration
6810 11:13:18.411860 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6811 11:13:18.418449 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6812 11:13:18.421755 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 11:13:18.425231 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 11:13:18.431922 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 11:13:18.435161 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 11:13:18.438371 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 11:13:18.444809 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 11:13:18.448218 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 11:13:18.451694 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 11:13:18.458344 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 11:13:18.458782 Total UI for P1: 0, mck2ui 16
6822 11:13:18.464841 best dqsien dly found for B0: ( 0, 14, 24)
6823 11:13:18.465466 Total UI for P1: 0, mck2ui 16
6824 11:13:18.468097 best dqsien dly found for B1: ( 0, 14, 24)
6825 11:13:18.474888 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6826 11:13:18.478201 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6827 11:13:18.478862
6828 11:13:18.481398 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 11:13:18.484290 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 11:13:18.487678 [Gating] SW calibration Done
6831 11:13:18.488244 ==
6832 11:13:18.490761 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 11:13:18.494222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 11:13:18.494812 ==
6835 11:13:18.497862 RX Vref Scan: 0
6836 11:13:18.498445
6837 11:13:18.498984 RX Vref 0 -> 0, step: 1
6838 11:13:18.499502
6839 11:13:18.501151 RX Delay -410 -> 252, step: 16
6840 11:13:18.507546 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6841 11:13:18.510946 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6842 11:13:18.514120 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6843 11:13:18.517417 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6844 11:13:18.524028 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6845 11:13:18.526958 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6846 11:13:18.530344 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6847 11:13:18.533509 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6848 11:13:18.540390 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6849 11:13:18.543316 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6850 11:13:18.546890 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6851 11:13:18.550272 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6852 11:13:18.556744 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6853 11:13:18.560113 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6854 11:13:18.563351 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6855 11:13:18.569942 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6856 11:13:18.570050 ==
6857 11:13:18.573351 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 11:13:18.576584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 11:13:18.576685 ==
6860 11:13:18.576818 DQS Delay:
6861 11:13:18.579856 DQS0 = 35, DQS1 = 43
6862 11:13:18.579933 DQM Delay:
6863 11:13:18.583026 DQM0 = 18, DQM1 = 18
6864 11:13:18.583131 DQ Delay:
6865 11:13:18.586607 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6866 11:13:18.589899 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6867 11:13:18.593193 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6868 11:13:18.596389 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6869 11:13:18.596490
6870 11:13:18.596580
6871 11:13:18.596669 ==
6872 11:13:18.599588 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 11:13:18.602956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 11:13:18.603056 ==
6875 11:13:18.603146
6876 11:13:18.606296
6877 11:13:18.606391 TX Vref Scan disable
6878 11:13:18.609946 == TX Byte 0 ==
6879 11:13:18.613330 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6880 11:13:18.616505 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6881 11:13:18.619808 == TX Byte 1 ==
6882 11:13:18.622931 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6883 11:13:18.626205 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6884 11:13:18.626275 ==
6885 11:13:18.629364 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 11:13:18.632778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 11:13:18.635872 ==
6888 11:13:18.635960
6889 11:13:18.636023
6890 11:13:18.636081 TX Vref Scan disable
6891 11:13:18.639035 == TX Byte 0 ==
6892 11:13:18.642570 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6893 11:13:18.646053 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6894 11:13:18.649415 == TX Byte 1 ==
6895 11:13:18.652746 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6896 11:13:18.655662 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6897 11:13:18.655761
6898 11:13:18.655850 [DATLAT]
6899 11:13:18.659239 Freq=400, CH1 RK1
6900 11:13:18.659312
6901 11:13:18.662485 DATLAT Default: 0xe
6902 11:13:18.662557 0, 0xFFFF, sum = 0
6903 11:13:18.665827 1, 0xFFFF, sum = 0
6904 11:13:18.665924 2, 0xFFFF, sum = 0
6905 11:13:18.669121 3, 0xFFFF, sum = 0
6906 11:13:18.669193 4, 0xFFFF, sum = 0
6907 11:13:18.672402 5, 0xFFFF, sum = 0
6908 11:13:18.672499 6, 0xFFFF, sum = 0
6909 11:13:18.675651 7, 0xFFFF, sum = 0
6910 11:13:18.675720 8, 0xFFFF, sum = 0
6911 11:13:18.678798 9, 0xFFFF, sum = 0
6912 11:13:18.678872 10, 0xFFFF, sum = 0
6913 11:13:18.682526 11, 0xFFFF, sum = 0
6914 11:13:18.682599 12, 0xFFFF, sum = 0
6915 11:13:18.685807 13, 0x0, sum = 1
6916 11:13:18.685912 14, 0x0, sum = 2
6917 11:13:18.689028 15, 0x0, sum = 3
6918 11:13:18.689139 16, 0x0, sum = 4
6919 11:13:18.692240 best_step = 14
6920 11:13:18.692342
6921 11:13:18.692437 ==
6922 11:13:18.695331 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 11:13:18.698683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 11:13:18.698797 ==
6925 11:13:18.702239 RX Vref Scan: 0
6926 11:13:18.702341
6927 11:13:18.702445 RX Vref 0 -> 0, step: 1
6928 11:13:18.702533
6929 11:13:18.705440 RX Delay -327 -> 252, step: 8
6930 11:13:18.713446 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6931 11:13:18.716500 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6932 11:13:18.719854 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6933 11:13:18.726456 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6934 11:13:18.729828 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6935 11:13:18.733117 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6936 11:13:18.736236 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6937 11:13:18.742880 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6938 11:13:18.746083 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6939 11:13:18.749386 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6940 11:13:18.752832 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6941 11:13:18.759385 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6942 11:13:18.762414 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6943 11:13:18.765841 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6944 11:13:18.769199 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6945 11:13:18.775522 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6946 11:13:18.775635 ==
6947 11:13:18.778902 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 11:13:18.782395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 11:13:18.782512 ==
6950 11:13:18.785647 DQS Delay:
6951 11:13:18.785735 DQS0 = 28, DQS1 = 36
6952 11:13:18.785800 DQM Delay:
6953 11:13:18.789036 DQM0 = 9, DQM1 = 11
6954 11:13:18.789118 DQ Delay:
6955 11:13:18.792222 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
6956 11:13:18.795810 DQ4 =12, DQ5 =16, DQ6 =16, DQ7 =8
6957 11:13:18.799026 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6958 11:13:18.802320 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6959 11:13:18.802402
6960 11:13:18.802466
6961 11:13:18.808986 [DQSOSCAuto] RK1, (LSB)MR18= 0xa64e, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
6962 11:13:18.812456 CH1 RK1: MR19=C0C, MR18=A64E
6963 11:13:18.818952 CH1_RK1: MR19=0xC0C, MR18=0xA64E, DQSOSC=389, MR23=63, INC=390, DEC=260
6964 11:13:18.822322 [RxdqsGatingPostProcess] freq 400
6965 11:13:18.829128 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6966 11:13:18.832041 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 11:13:18.835503 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 11:13:18.838802 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 11:13:18.841993 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 11:13:18.845073 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 11:13:18.845254 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 11:13:18.851754 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 11:13:18.854898 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 11:13:18.855164 Pre-setting of DQS Precalculation
6975 11:13:18.861489 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6976 11:13:18.868224 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6977 11:13:18.875139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6978 11:13:18.875566
6979 11:13:18.875897
6980 11:13:18.878343 [Calibration Summary] 800 Mbps
6981 11:13:18.881487 CH 0, Rank 0
6982 11:13:18.881956 SW Impedance : PASS
6983 11:13:18.884730 DUTY Scan : NO K
6984 11:13:18.888088 ZQ Calibration : PASS
6985 11:13:18.888505 Jitter Meter : NO K
6986 11:13:18.891783 CBT Training : PASS
6987 11:13:18.894802 Write leveling : PASS
6988 11:13:18.895835 RX DQS gating : PASS
6989 11:13:18.897876 RX DQ/DQS(RDDQC) : PASS
6990 11:13:18.898456 TX DQ/DQS : PASS
6991 11:13:18.901489 RX DATLAT : PASS
6992 11:13:18.904695 RX DQ/DQS(Engine): PASS
6993 11:13:18.905330 TX OE : NO K
6994 11:13:18.908005 All Pass.
6995 11:13:18.908430
6996 11:13:18.908815 CH 0, Rank 1
6997 11:13:18.911494 SW Impedance : PASS
6998 11:13:18.911918 DUTY Scan : NO K
6999 11:13:18.914562 ZQ Calibration : PASS
7000 11:13:18.917825 Jitter Meter : NO K
7001 11:13:18.918341 CBT Training : PASS
7002 11:13:18.921115 Write leveling : NO K
7003 11:13:18.924504 RX DQS gating : PASS
7004 11:13:18.925141 RX DQ/DQS(RDDQC) : PASS
7005 11:13:18.927577 TX DQ/DQS : PASS
7006 11:13:18.931055 RX DATLAT : PASS
7007 11:13:18.931733 RX DQ/DQS(Engine): PASS
7008 11:13:18.934183 TX OE : NO K
7009 11:13:18.934891 All Pass.
7010 11:13:18.935382
7011 11:13:18.937316 CH 1, Rank 0
7012 11:13:18.937778 SW Impedance : PASS
7013 11:13:18.940689 DUTY Scan : NO K
7014 11:13:18.943985 ZQ Calibration : PASS
7015 11:13:18.944708 Jitter Meter : NO K
7016 11:13:18.947319 CBT Training : PASS
7017 11:13:18.950909 Write leveling : PASS
7018 11:13:18.951356 RX DQS gating : PASS
7019 11:13:18.954203 RX DQ/DQS(RDDQC) : PASS
7020 11:13:18.957221 TX DQ/DQS : PASS
7021 11:13:18.957673 RX DATLAT : PASS
7022 11:13:18.960741 RX DQ/DQS(Engine): PASS
7023 11:13:18.964027 TX OE : NO K
7024 11:13:18.964452 All Pass.
7025 11:13:18.964835
7026 11:13:18.965186 CH 1, Rank 1
7027 11:13:18.967519 SW Impedance : PASS
7028 11:13:18.970661 DUTY Scan : NO K
7029 11:13:18.971104 ZQ Calibration : PASS
7030 11:13:18.973758 Jitter Meter : NO K
7031 11:13:18.976911 CBT Training : PASS
7032 11:13:18.977389 Write leveling : NO K
7033 11:13:18.980251 RX DQS gating : PASS
7034 11:13:18.983459 RX DQ/DQS(RDDQC) : PASS
7035 11:13:18.983919 TX DQ/DQS : PASS
7036 11:13:18.987248 RX DATLAT : PASS
7037 11:13:18.987668 RX DQ/DQS(Engine): PASS
7038 11:13:18.990300 TX OE : NO K
7039 11:13:18.990663 All Pass.
7040 11:13:18.990973
7041 11:13:18.993701 DramC Write-DBI off
7042 11:13:18.997120 PER_BANK_REFRESH: Hybrid Mode
7043 11:13:18.997536 TX_TRACKING: ON
7044 11:13:19.006504 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7045 11:13:19.009802 [FAST_K] Save calibration result to emmc
7046 11:13:19.013014 dramc_set_vcore_voltage set vcore to 725000
7047 11:13:19.016423 Read voltage for 1600, 0
7048 11:13:19.016505 Vio18 = 0
7049 11:13:19.019663 Vcore = 725000
7050 11:13:19.019745 Vdram = 0
7051 11:13:19.019809 Vddq = 0
7052 11:13:19.019868 Vmddr = 0
7053 11:13:19.026157 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7054 11:13:19.033070 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7055 11:13:19.033158 MEM_TYPE=3, freq_sel=13
7056 11:13:19.036676 sv_algorithm_assistance_LP4_3733
7057 11:13:19.039685 ============ PULL DRAM RESETB DOWN ============
7058 11:13:19.046143 ========== PULL DRAM RESETB DOWN end =========
7059 11:13:19.049869 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7060 11:13:19.053161 ===================================
7061 11:13:19.056473 LPDDR4 DRAM CONFIGURATION
7062 11:13:19.059897 ===================================
7063 11:13:19.060315 EX_ROW_EN[0] = 0x0
7064 11:13:19.063171 EX_ROW_EN[1] = 0x0
7065 11:13:19.063626 LP4Y_EN = 0x0
7066 11:13:19.066325 WORK_FSP = 0x1
7067 11:13:19.069844 WL = 0x5
7068 11:13:19.070259 RL = 0x5
7069 11:13:19.073308 BL = 0x2
7070 11:13:19.073722 RPST = 0x0
7071 11:13:19.076419 RD_PRE = 0x0
7072 11:13:19.076891 WR_PRE = 0x1
7073 11:13:19.080136 WR_PST = 0x1
7074 11:13:19.080559 DBI_WR = 0x0
7075 11:13:19.082936 DBI_RD = 0x0
7076 11:13:19.083357 OTF = 0x1
7077 11:13:19.086288 ===================================
7078 11:13:19.089863 ===================================
7079 11:13:19.092913 ANA top config
7080 11:13:19.096521 ===================================
7081 11:13:19.097244 DLL_ASYNC_EN = 0
7082 11:13:19.099587 ALL_SLAVE_EN = 0
7083 11:13:19.102815 NEW_RANK_MODE = 1
7084 11:13:19.106093 DLL_IDLE_MODE = 1
7085 11:13:19.106538 LP45_APHY_COMB_EN = 1
7086 11:13:19.109603 TX_ODT_DIS = 0
7087 11:13:19.113008 NEW_8X_MODE = 1
7088 11:13:19.116608 ===================================
7089 11:13:19.119519 ===================================
7090 11:13:19.123137 data_rate = 3200
7091 11:13:19.126107 CKR = 1
7092 11:13:19.129556 DQ_P2S_RATIO = 8
7093 11:13:19.132594 ===================================
7094 11:13:19.133072 CA_P2S_RATIO = 8
7095 11:13:19.136111 DQ_CA_OPEN = 0
7096 11:13:19.139392 DQ_SEMI_OPEN = 0
7097 11:13:19.142298 CA_SEMI_OPEN = 0
7098 11:13:19.145684 CA_FULL_RATE = 0
7099 11:13:19.148916 DQ_CKDIV4_EN = 0
7100 11:13:19.149412 CA_CKDIV4_EN = 0
7101 11:13:19.152221 CA_PREDIV_EN = 0
7102 11:13:19.155803 PH8_DLY = 12
7103 11:13:19.158724 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7104 11:13:19.162414 DQ_AAMCK_DIV = 4
7105 11:13:19.165482 CA_AAMCK_DIV = 4
7106 11:13:19.168890 CA_ADMCK_DIV = 4
7107 11:13:19.169405 DQ_TRACK_CA_EN = 0
7108 11:13:19.172582 CA_PICK = 1600
7109 11:13:19.175966 CA_MCKIO = 1600
7110 11:13:19.179013 MCKIO_SEMI = 0
7111 11:13:19.182277 PLL_FREQ = 3068
7112 11:13:19.185655 DQ_UI_PI_RATIO = 32
7113 11:13:19.188733 CA_UI_PI_RATIO = 0
7114 11:13:19.191999 ===================================
7115 11:13:19.195225 ===================================
7116 11:13:19.195748 memory_type:LPDDR4
7117 11:13:19.198663 GP_NUM : 10
7118 11:13:19.202094 SRAM_EN : 1
7119 11:13:19.202677 MD32_EN : 0
7120 11:13:19.205219 ===================================
7121 11:13:19.208311 [ANA_INIT] >>>>>>>>>>>>>>
7122 11:13:19.212282 <<<<<< [CONFIGURE PHASE]: ANA_TX
7123 11:13:19.215409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7124 11:13:19.218336 ===================================
7125 11:13:19.221506 data_rate = 3200,PCW = 0X7600
7126 11:13:19.225584 ===================================
7127 11:13:19.228691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7128 11:13:19.231594 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 11:13:19.238148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 11:13:19.241407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7131 11:13:19.244541 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7132 11:13:19.247867 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7133 11:13:19.251025 [ANA_INIT] flow start
7134 11:13:19.254169 [ANA_INIT] PLL >>>>>>>>
7135 11:13:19.254592 [ANA_INIT] PLL <<<<<<<<
7136 11:13:19.257868 [ANA_INIT] MIDPI >>>>>>>>
7137 11:13:19.260809 [ANA_INIT] MIDPI <<<<<<<<
7138 11:13:19.264310 [ANA_INIT] DLL >>>>>>>>
7139 11:13:19.264731 [ANA_INIT] DLL <<<<<<<<
7140 11:13:19.267640 [ANA_INIT] flow end
7141 11:13:19.271021 ============ LP4 DIFF to SE enter ============
7142 11:13:19.274438 ============ LP4 DIFF to SE exit ============
7143 11:13:19.277687 [ANA_INIT] <<<<<<<<<<<<<
7144 11:13:19.280911 [Flow] Enable top DCM control >>>>>
7145 11:13:19.284129 [Flow] Enable top DCM control <<<<<
7146 11:13:19.287373 Enable DLL master slave shuffle
7147 11:13:19.294258 ==============================================================
7148 11:13:19.294679 Gating Mode config
7149 11:13:19.300858 ==============================================================
7150 11:13:19.301283 Config description:
7151 11:13:19.310729 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7152 11:13:19.317339 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7153 11:13:19.323847 SELPH_MODE 0: By rank 1: By Phase
7154 11:13:19.327043 ==============================================================
7155 11:13:19.330696 GAT_TRACK_EN = 1
7156 11:13:19.334259 RX_GATING_MODE = 2
7157 11:13:19.337337 RX_GATING_TRACK_MODE = 2
7158 11:13:19.340506 SELPH_MODE = 1
7159 11:13:19.343755 PICG_EARLY_EN = 1
7160 11:13:19.347365 VALID_LAT_VALUE = 1
7161 11:13:19.353728 ==============================================================
7162 11:13:19.357114 Enter into Gating configuration >>>>
7163 11:13:19.359971 Exit from Gating configuration <<<<
7164 11:13:19.363212 Enter into DVFS_PRE_config >>>>>
7165 11:13:19.373477 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7166 11:13:19.376671 Exit from DVFS_PRE_config <<<<<
7167 11:13:19.379760 Enter into PICG configuration >>>>
7168 11:13:19.383011 Exit from PICG configuration <<<<
7169 11:13:19.386427 [RX_INPUT] configuration >>>>>
7170 11:13:19.387086 [RX_INPUT] configuration <<<<<
7171 11:13:19.393037 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7172 11:13:19.400235 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7173 11:13:19.403232 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 11:13:19.409898 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 11:13:19.416272 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 11:13:19.422975 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 11:13:19.426897 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7178 11:13:19.429813 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7179 11:13:19.436249 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7180 11:13:19.439873 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7181 11:13:19.442930 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7182 11:13:19.449249 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7183 11:13:19.452474 ===================================
7184 11:13:19.452953 LPDDR4 DRAM CONFIGURATION
7185 11:13:19.456263 ===================================
7186 11:13:19.459332 EX_ROW_EN[0] = 0x0
7187 11:13:19.462599 EX_ROW_EN[1] = 0x0
7188 11:13:19.463018 LP4Y_EN = 0x0
7189 11:13:19.465970 WORK_FSP = 0x1
7190 11:13:19.466389 WL = 0x5
7191 11:13:19.469210 RL = 0x5
7192 11:13:19.469631 BL = 0x2
7193 11:13:19.472493 RPST = 0x0
7194 11:13:19.473074 RD_PRE = 0x0
7195 11:13:19.475964 WR_PRE = 0x1
7196 11:13:19.476382 WR_PST = 0x1
7197 11:13:19.479671 DBI_WR = 0x0
7198 11:13:19.480202 DBI_RD = 0x0
7199 11:13:19.482419 OTF = 0x1
7200 11:13:19.486180 ===================================
7201 11:13:19.489288 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7202 11:13:19.492815 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7203 11:13:19.498979 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 11:13:19.502033 ===================================
7205 11:13:19.502457 LPDDR4 DRAM CONFIGURATION
7206 11:13:19.505284 ===================================
7207 11:13:19.509015 EX_ROW_EN[0] = 0x10
7208 11:13:19.512134 EX_ROW_EN[1] = 0x0
7209 11:13:19.512644 LP4Y_EN = 0x0
7210 11:13:19.515738 WORK_FSP = 0x1
7211 11:13:19.516272 WL = 0x5
7212 11:13:19.518536 RL = 0x5
7213 11:13:19.519046 BL = 0x2
7214 11:13:19.521995 RPST = 0x0
7215 11:13:19.522417 RD_PRE = 0x0
7216 11:13:19.525467 WR_PRE = 0x1
7217 11:13:19.525888 WR_PST = 0x1
7218 11:13:19.528666 DBI_WR = 0x0
7219 11:13:19.529126 DBI_RD = 0x0
7220 11:13:19.531964 OTF = 0x1
7221 11:13:19.535778 ===================================
7222 11:13:19.541699 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7223 11:13:19.542235 ==
7224 11:13:19.545227 Dram Type= 6, Freq= 0, CH_0, rank 0
7225 11:13:19.548552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7226 11:13:19.549148 ==
7227 11:13:19.552379 [Duty_Offset_Calibration]
7228 11:13:19.552959 B0:2 B1:0 CA:1
7229 11:13:19.553299
7230 11:13:19.555509 [DutyScan_Calibration_Flow] k_type=0
7231 11:13:19.565202
7232 11:13:19.565728 ==CLK 0==
7233 11:13:19.568587 Final CLK duty delay cell = -4
7234 11:13:19.572102 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7235 11:13:19.575215 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7236 11:13:19.578579 [-4] AVG Duty = 4906%(X100)
7237 11:13:19.579180
7238 11:13:19.581495 CH0 CLK Duty spec in!! Max-Min= 187%
7239 11:13:19.585307 [DutyScan_Calibration_Flow] ====Done====
7240 11:13:19.585835
7241 11:13:19.587859 [DutyScan_Calibration_Flow] k_type=1
7242 11:13:19.604941
7243 11:13:19.605499 ==DQS 0 ==
7244 11:13:19.607907 Final DQS duty delay cell = 0
7245 11:13:19.611285 [0] MAX Duty = 5249%(X100), DQS PI = 32
7246 11:13:19.614680 [0] MIN Duty = 4938%(X100), DQS PI = 62
7247 11:13:19.617584 [0] AVG Duty = 5093%(X100)
7248 11:13:19.618047
7249 11:13:19.618415 ==DQS 1 ==
7250 11:13:19.621097 Final DQS duty delay cell = -4
7251 11:13:19.624160 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7252 11:13:19.627392 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7253 11:13:19.630831 [-4] AVG Duty = 5000%(X100)
7254 11:13:19.631262
7255 11:13:19.633973 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7256 11:13:19.634392
7257 11:13:19.637230 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7258 11:13:19.640932 [DutyScan_Calibration_Flow] ====Done====
7259 11:13:19.641447
7260 11:13:19.644272 [DutyScan_Calibration_Flow] k_type=3
7261 11:13:19.661155
7262 11:13:19.661675 ==DQM 0 ==
7263 11:13:19.664470 Final DQM duty delay cell = 0
7264 11:13:19.667767 [0] MAX Duty = 5093%(X100), DQS PI = 26
7265 11:13:19.671109 [0] MIN Duty = 4813%(X100), DQS PI = 50
7266 11:13:19.674638 [0] AVG Duty = 4953%(X100)
7267 11:13:19.675152
7268 11:13:19.675491 ==DQM 1 ==
7269 11:13:19.677523 Final DQM duty delay cell = -4
7270 11:13:19.681040 [-4] MAX Duty = 5031%(X100), DQS PI = 46
7271 11:13:19.684329 [-4] MIN Duty = 4751%(X100), DQS PI = 10
7272 11:13:19.687549 [-4] AVG Duty = 4891%(X100)
7273 11:13:19.687972
7274 11:13:19.690697 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7275 11:13:19.691118
7276 11:13:19.694207 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7277 11:13:19.697570 [DutyScan_Calibration_Flow] ====Done====
7278 11:13:19.697994
7279 11:13:19.700947 [DutyScan_Calibration_Flow] k_type=2
7280 11:13:19.718572
7281 11:13:19.718991 ==DQ 0 ==
7282 11:13:19.722250 Final DQ duty delay cell = 0
7283 11:13:19.725236 [0] MAX Duty = 5156%(X100), DQS PI = 38
7284 11:13:19.728623 [0] MIN Duty = 5000%(X100), DQS PI = 16
7285 11:13:19.729083 [0] AVG Duty = 5078%(X100)
7286 11:13:19.732016
7287 11:13:19.732477 ==DQ 1 ==
7288 11:13:19.735223 Final DQ duty delay cell = 0
7289 11:13:19.738567 [0] MAX Duty = 4969%(X100), DQS PI = 44
7290 11:13:19.741745 [0] MIN Duty = 4875%(X100), DQS PI = 12
7291 11:13:19.742163 [0] AVG Duty = 4922%(X100)
7292 11:13:19.745031
7293 11:13:19.745449 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7294 11:13:19.748673
7295 11:13:19.751833 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7296 11:13:19.755415 [DutyScan_Calibration_Flow] ====Done====
7297 11:13:19.755953 ==
7298 11:13:19.758548 Dram Type= 6, Freq= 0, CH_1, rank 0
7299 11:13:19.761936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 11:13:19.762349 ==
7301 11:13:19.765070 [Duty_Offset_Calibration]
7302 11:13:19.765479 B0:0 B1:-1 CA:2
7303 11:13:19.765804
7304 11:13:19.768383 [DutyScan_Calibration_Flow] k_type=0
7305 11:13:19.778796
7306 11:13:19.779205 ==CLK 0==
7307 11:13:19.782164 Final CLK duty delay cell = 0
7308 11:13:19.785239 [0] MAX Duty = 5156%(X100), DQS PI = 10
7309 11:13:19.788525 [0] MIN Duty = 4938%(X100), DQS PI = 44
7310 11:13:19.791956 [0] AVG Duty = 5047%(X100)
7311 11:13:19.792366
7312 11:13:19.795503 CH1 CLK Duty spec in!! Max-Min= 218%
7313 11:13:19.798586 [DutyScan_Calibration_Flow] ====Done====
7314 11:13:19.798995
7315 11:13:19.802120 [DutyScan_Calibration_Flow] k_type=1
7316 11:13:19.818653
7317 11:13:19.819062 ==DQS 0 ==
7318 11:13:19.822028 Final DQS duty delay cell = 0
7319 11:13:19.825213 [0] MAX Duty = 5124%(X100), DQS PI = 26
7320 11:13:19.828278 [0] MIN Duty = 4969%(X100), DQS PI = 2
7321 11:13:19.832046 [0] AVG Duty = 5046%(X100)
7322 11:13:19.832461
7323 11:13:19.832827 ==DQS 1 ==
7324 11:13:19.835167 Final DQS duty delay cell = 0
7325 11:13:19.838481 [0] MAX Duty = 5187%(X100), DQS PI = 0
7326 11:13:19.842120 [0] MIN Duty = 4844%(X100), DQS PI = 32
7327 11:13:19.844873 [0] AVG Duty = 5015%(X100)
7328 11:13:19.845284
7329 11:13:19.848659 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7330 11:13:19.849093
7331 11:13:19.851669 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7332 11:13:19.855018 [DutyScan_Calibration_Flow] ====Done====
7333 11:13:19.855434
7334 11:13:19.858266 [DutyScan_Calibration_Flow] k_type=3
7335 11:13:19.876581
7336 11:13:19.877140 ==DQM 0 ==
7337 11:13:19.879961 Final DQM duty delay cell = 4
7338 11:13:19.883337 [4] MAX Duty = 5125%(X100), DQS PI = 8
7339 11:13:19.886750 [4] MIN Duty = 5000%(X100), DQS PI = 34
7340 11:13:19.889285 [4] AVG Duty = 5062%(X100)
7341 11:13:19.889894
7342 11:13:19.890240 ==DQM 1 ==
7343 11:13:19.892579 Final DQM duty delay cell = 0
7344 11:13:19.896151 [0] MAX Duty = 5281%(X100), DQS PI = 58
7345 11:13:19.899390 [0] MIN Duty = 4844%(X100), DQS PI = 34
7346 11:13:19.902392 [0] AVG Duty = 5062%(X100)
7347 11:13:19.902807
7348 11:13:19.905540 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7349 11:13:19.905952
7350 11:13:19.909041 CH1 DQM 1 Duty spec in!! Max-Min= 437%
7351 11:13:19.912462 [DutyScan_Calibration_Flow] ====Done====
7352 11:13:19.913011
7353 11:13:19.915753 [DutyScan_Calibration_Flow] k_type=2
7354 11:13:19.933393
7355 11:13:19.934018 ==DQ 0 ==
7356 11:13:19.936706 Final DQ duty delay cell = 0
7357 11:13:19.940002 [0] MAX Duty = 5093%(X100), DQS PI = 20
7358 11:13:19.943242 [0] MIN Duty = 4969%(X100), DQS PI = 46
7359 11:13:19.943786 [0] AVG Duty = 5031%(X100)
7360 11:13:19.946809
7361 11:13:19.947345 ==DQ 1 ==
7362 11:13:19.949723 Final DQ duty delay cell = 0
7363 11:13:19.952839 [0] MAX Duty = 5062%(X100), DQS PI = 2
7364 11:13:19.956140 [0] MIN Duty = 4844%(X100), DQS PI = 32
7365 11:13:19.956572 [0] AVG Duty = 4953%(X100)
7366 11:13:19.956985
7367 11:13:19.959428 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7368 11:13:19.962772
7369 11:13:19.966371 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7370 11:13:19.969702 [DutyScan_Calibration_Flow] ====Done====
7371 11:13:19.973021 nWR fixed to 30
7372 11:13:19.973544 [ModeRegInit_LP4] CH0 RK0
7373 11:13:19.976109 [ModeRegInit_LP4] CH0 RK1
7374 11:13:19.979676 [ModeRegInit_LP4] CH1 RK0
7375 11:13:19.983189 [ModeRegInit_LP4] CH1 RK1
7376 11:13:19.983704 match AC timing 5
7377 11:13:19.989392 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7378 11:13:19.992658 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7379 11:13:19.995823 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7380 11:13:20.002587 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7381 11:13:20.005744 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7382 11:13:20.006156 [MiockJmeterHQA]
7383 11:13:20.006489
7384 11:13:20.009368 [DramcMiockJmeter] u1RxGatingPI = 0
7385 11:13:20.012504 0 : 4254, 4027
7386 11:13:20.013070 4 : 4252, 4027
7387 11:13:20.015880 8 : 4252, 4027
7388 11:13:20.016401 12 : 4363, 4139
7389 11:13:20.016738 16 : 4252, 4027
7390 11:13:20.018876 20 : 4253, 4026
7391 11:13:20.019293 24 : 4363, 4138
7392 11:13:20.022414 28 : 4253, 4026
7393 11:13:20.022945 32 : 4253, 4026
7394 11:13:20.025625 36 : 4255, 4029
7395 11:13:20.026044 40 : 4250, 4026
7396 11:13:20.028706 44 : 4252, 4030
7397 11:13:20.029147 48 : 4252, 4027
7398 11:13:20.029474 52 : 4252, 4027
7399 11:13:20.032525 56 : 4255, 4030
7400 11:13:20.033075 60 : 4253, 4027
7401 11:13:20.035510 64 : 4252, 4030
7402 11:13:20.035927 68 : 4249, 4027
7403 11:13:20.038779 72 : 4363, 4137
7404 11:13:20.039309 76 : 4363, 4137
7405 11:13:20.042281 80 : 4250, 4026
7406 11:13:20.042832 84 : 4250, 4027
7407 11:13:20.043179 88 : 4250, 3285
7408 11:13:20.045705 92 : 4253, 0
7409 11:13:20.046125 96 : 4363, 0
7410 11:13:20.048867 100 : 4253, 0
7411 11:13:20.049292 104 : 4253, 0
7412 11:13:20.049639 108 : 4255, 0
7413 11:13:20.052003 112 : 4252, 0
7414 11:13:20.052430 116 : 4250, 0
7415 11:13:20.055293 120 : 4250, 0
7416 11:13:20.055740 124 : 4252, 0
7417 11:13:20.056087 128 : 4250, 0
7418 11:13:20.058483 132 : 4253, 0
7419 11:13:20.058910 136 : 4258, 0
7420 11:13:20.061811 140 : 4361, 0
7421 11:13:20.062239 144 : 4360, 0
7422 11:13:20.062578 148 : 4258, 0
7423 11:13:20.065067 152 : 4361, 0
7424 11:13:20.065515 156 : 4250, 0
7425 11:13:20.065916 160 : 4250, 0
7426 11:13:20.068375 164 : 4249, 0
7427 11:13:20.068828 168 : 4250, 0
7428 11:13:20.071685 172 : 4250, 0
7429 11:13:20.072113 176 : 4250, 0
7430 11:13:20.072450 180 : 4250, 0
7431 11:13:20.074911 184 : 4253, 0
7432 11:13:20.075339 188 : 4255, 0
7433 11:13:20.078536 192 : 4361, 0
7434 11:13:20.078961 196 : 4250, 0
7435 11:13:20.079300 200 : 4253, 8
7436 11:13:20.081863 204 : 4252, 2641
7437 11:13:20.082290 208 : 4363, 4137
7438 11:13:20.085011 212 : 4250, 4026
7439 11:13:20.085435 216 : 4250, 4027
7440 11:13:20.087989 220 : 4255, 4029
7441 11:13:20.088418 224 : 4360, 4137
7442 11:13:20.091332 228 : 4250, 4026
7443 11:13:20.091759 232 : 4361, 4137
7444 11:13:20.095100 236 : 4255, 4029
7445 11:13:20.095526 240 : 4249, 4027
7446 11:13:20.098340 244 : 4250, 4026
7447 11:13:20.098767 248 : 4250, 4027
7448 11:13:20.099108 252 : 4250, 4027
7449 11:13:20.101281 256 : 4250, 4027
7450 11:13:20.101706 260 : 4250, 4026
7451 11:13:20.104963 264 : 4253, 4029
7452 11:13:20.105389 268 : 4250, 4027
7453 11:13:20.108250 272 : 4250, 4027
7454 11:13:20.108677 276 : 4360, 4137
7455 11:13:20.111382 280 : 4250, 4026
7456 11:13:20.111806 284 : 4361, 4137
7457 11:13:20.114648 288 : 4250, 4027
7458 11:13:20.115174 292 : 4250, 4027
7459 11:13:20.118115 296 : 4250, 4026
7460 11:13:20.118540 300 : 4250, 4027
7461 11:13:20.121424 304 : 4250, 4027
7462 11:13:20.121852 308 : 4255, 4029
7463 11:13:20.122194 312 : 4250, 3933
7464 11:13:20.125001 316 : 4253, 1912
7465 11:13:20.125529
7466 11:13:20.128081 MIOCK jitter meter ch=0
7467 11:13:20.128615
7468 11:13:20.129005 1T = (316-92) = 224 dly cells
7469 11:13:20.134584 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7470 11:13:20.135009 ==
7471 11:13:20.137789 Dram Type= 6, Freq= 0, CH_0, rank 0
7472 11:13:20.144885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7473 11:13:20.145417 ==
7474 11:13:20.148158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7475 11:13:20.154791 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7476 11:13:20.157799 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7477 11:13:20.164298 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7478 11:13:20.171771 [CA 0] Center 42 (12~73) winsize 62
7479 11:13:20.174919 [CA 1] Center 43 (13~73) winsize 61
7480 11:13:20.178568 [CA 2] Center 38 (8~68) winsize 61
7481 11:13:20.181733 [CA 3] Center 37 (8~67) winsize 60
7482 11:13:20.184944 [CA 4] Center 36 (7~66) winsize 60
7483 11:13:20.188407 [CA 5] Center 35 (5~65) winsize 61
7484 11:13:20.189023
7485 11:13:20.191871 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7486 11:13:20.192452
7487 11:13:20.195327 [CATrainingPosCal] consider 1 rank data
7488 11:13:20.199025 u2DelayCellTimex100 = 290/100 ps
7489 11:13:20.201968 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7490 11:13:20.208734 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7491 11:13:20.212000 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7492 11:13:20.215380 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7493 11:13:20.218352 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7494 11:13:20.221575 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7495 11:13:20.222016
7496 11:13:20.224969 CA PerBit enable=1, Macro0, CA PI delay=35
7497 11:13:20.225420
7498 11:13:20.228127 [CBTSetCACLKResult] CA Dly = 35
7499 11:13:20.231435 CS Dly: 10 (0~41)
7500 11:13:20.234662 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7501 11:13:20.237992 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7502 11:13:20.238419 ==
7503 11:13:20.241656 Dram Type= 6, Freq= 0, CH_0, rank 1
7504 11:13:20.248057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 11:13:20.248595 ==
7506 11:13:20.251154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 11:13:20.255135 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 11:13:20.261458 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 11:13:20.267932 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 11:13:20.275399 [CA 0] Center 43 (13~73) winsize 61
7511 11:13:20.278644 [CA 1] Center 43 (13~73) winsize 61
7512 11:13:20.281595 [CA 2] Center 37 (8~67) winsize 60
7513 11:13:20.285401 [CA 3] Center 38 (9~68) winsize 60
7514 11:13:20.288355 [CA 4] Center 37 (7~67) winsize 61
7515 11:13:20.291800 [CA 5] Center 36 (6~66) winsize 61
7516 11:13:20.292400
7517 11:13:20.295325 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7518 11:13:20.295751
7519 11:13:20.298352 [CATrainingPosCal] consider 2 rank data
7520 11:13:20.301663 u2DelayCellTimex100 = 290/100 ps
7521 11:13:20.308437 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7522 11:13:20.311305 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7523 11:13:20.314603 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7524 11:13:20.317994 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7525 11:13:20.321726 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7526 11:13:20.324947 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7527 11:13:20.325469
7528 11:13:20.328321 CA PerBit enable=1, Macro0, CA PI delay=35
7529 11:13:20.328876
7530 11:13:20.331756 [CBTSetCACLKResult] CA Dly = 35
7531 11:13:20.334510 CS Dly: 10 (0~42)
7532 11:13:20.338157 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 11:13:20.341655 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 11:13:20.342172
7535 11:13:20.344494 ----->DramcWriteLeveling(PI) begin...
7536 11:13:20.344964 ==
7537 11:13:20.348005 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 11:13:20.354695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 11:13:20.355128 ==
7540 11:13:20.357633 Write leveling (Byte 0): 38 => 38
7541 11:13:20.361424 Write leveling (Byte 1): 30 => 30
7542 11:13:20.361940 DramcWriteLeveling(PI) end<-----
7543 11:13:20.364484
7544 11:13:20.364998 ==
7545 11:13:20.367848 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 11:13:20.371194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 11:13:20.371710 ==
7548 11:13:20.374642 [Gating] SW mode calibration
7549 11:13:20.380510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7550 11:13:20.386993 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7551 11:13:20.390224 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 11:13:20.393726 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 11:13:20.400372 1 4 8 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
7554 11:13:20.403872 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7555 11:13:20.407077 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7556 11:13:20.413634 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7557 11:13:20.416858 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 11:13:20.420204 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 11:13:20.426781 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 11:13:20.430565 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 11:13:20.433492 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7562 11:13:20.439879 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7563 11:13:20.442886 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7564 11:13:20.446099 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
7565 11:13:20.453102 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 11:13:20.456014 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 11:13:20.459383 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 11:13:20.465871 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 11:13:20.469101 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7570 11:13:20.473145 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7571 11:13:20.480098 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7572 11:13:20.483230 1 6 20 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
7573 11:13:20.486371 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 11:13:20.492684 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 11:13:20.496162 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 11:13:20.499557 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 11:13:20.506095 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 11:13:20.509454 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7579 11:13:20.512647 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7580 11:13:20.516369 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7581 11:13:20.522755 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7582 11:13:20.525708 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 11:13:20.529283 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 11:13:20.535647 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 11:13:20.538888 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 11:13:20.542649 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 11:13:20.549444 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 11:13:20.552703 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 11:13:20.555548 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 11:13:20.562245 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 11:13:20.565412 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 11:13:20.568744 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 11:13:20.575175 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 11:13:20.578952 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7595 11:13:20.582305 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 11:13:20.585575 Total UI for P1: 0, mck2ui 16
7597 11:13:20.588394 best dqsien dly found for B0: ( 1, 9, 10)
7598 11:13:20.595121 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7599 11:13:20.598624 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 11:13:20.601866 Total UI for P1: 0, mck2ui 16
7601 11:13:20.605265 best dqsien dly found for B1: ( 1, 9, 18)
7602 11:13:20.608232 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7603 11:13:20.611937 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7604 11:13:20.612385
7605 11:13:20.614922 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7606 11:13:20.621761 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7607 11:13:20.622211 [Gating] SW calibration Done
7608 11:13:20.622547 ==
7609 11:13:20.624811 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 11:13:20.631747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 11:13:20.632275 ==
7612 11:13:20.632615 RX Vref Scan: 0
7613 11:13:20.633007
7614 11:13:20.635349 RX Vref 0 -> 0, step: 1
7615 11:13:20.635883
7616 11:13:20.638499 RX Delay 0 -> 252, step: 8
7617 11:13:20.642159 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7618 11:13:20.644759 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7619 11:13:20.648708 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7620 11:13:20.651774 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7621 11:13:20.658574 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7622 11:13:20.661590 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7623 11:13:20.664900 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7624 11:13:20.668369 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7625 11:13:20.671576 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7626 11:13:20.678033 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7627 11:13:20.681526 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7628 11:13:20.684640 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7629 11:13:20.688369 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7630 11:13:20.691016 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7631 11:13:20.698195 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7632 11:13:20.701207 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7633 11:13:20.701634 ==
7634 11:13:20.704503 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 11:13:20.707967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 11:13:20.708491 ==
7637 11:13:20.711229 DQS Delay:
7638 11:13:20.711652 DQS0 = 0, DQS1 = 0
7639 11:13:20.711989 DQM Delay:
7640 11:13:20.714425 DQM0 = 137, DQM1 = 127
7641 11:13:20.714846 DQ Delay:
7642 11:13:20.717402 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7643 11:13:20.720748 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7644 11:13:20.727445 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7645 11:13:20.730655 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7646 11:13:20.731079
7647 11:13:20.731411
7648 11:13:20.731722 ==
7649 11:13:20.733901 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 11:13:20.737344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 11:13:20.737789 ==
7652 11:13:20.738132
7653 11:13:20.738441
7654 11:13:20.740988 TX Vref Scan disable
7655 11:13:20.744027 == TX Byte 0 ==
7656 11:13:20.747620 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7657 11:13:20.751264 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7658 11:13:20.754449 == TX Byte 1 ==
7659 11:13:20.757449 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7660 11:13:20.760860 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7661 11:13:20.761383 ==
7662 11:13:20.764018 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 11:13:20.767229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 11:13:20.770469 ==
7665 11:13:20.782362
7666 11:13:20.785648 TX Vref early break, caculate TX vref
7667 11:13:20.788905 TX Vref=16, minBit 7, minWin=22, winSum=378
7668 11:13:20.792154 TX Vref=18, minBit 0, minWin=23, winSum=385
7669 11:13:20.795370 TX Vref=20, minBit 12, minWin=23, winSum=402
7670 11:13:20.798752 TX Vref=22, minBit 0, minWin=25, winSum=412
7671 11:13:20.802321 TX Vref=24, minBit 0, minWin=25, winSum=418
7672 11:13:20.808865 TX Vref=26, minBit 7, minWin=25, winSum=426
7673 11:13:20.812129 TX Vref=28, minBit 0, minWin=26, winSum=432
7674 11:13:20.815485 TX Vref=30, minBit 0, minWin=26, winSum=427
7675 11:13:20.819050 TX Vref=32, minBit 6, minWin=25, winSum=417
7676 11:13:20.822055 TX Vref=34, minBit 11, minWin=24, winSum=402
7677 11:13:20.828591 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
7678 11:13:20.829065
7679 11:13:20.832206 Final TX Range 0 Vref 28
7680 11:13:20.832627
7681 11:13:20.833006 ==
7682 11:13:20.835510 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 11:13:20.838654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 11:13:20.839110 ==
7685 11:13:20.839450
7686 11:13:20.839757
7687 11:13:20.841831 TX Vref Scan disable
7688 11:13:20.848529 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7689 11:13:20.849124 == TX Byte 0 ==
7690 11:13:20.851946 u2DelayCellOfst[0]=13 cells (4 PI)
7691 11:13:20.855080 u2DelayCellOfst[1]=20 cells (6 PI)
7692 11:13:20.858281 u2DelayCellOfst[2]=10 cells (3 PI)
7693 11:13:20.862078 u2DelayCellOfst[3]=13 cells (4 PI)
7694 11:13:20.864786 u2DelayCellOfst[4]=10 cells (3 PI)
7695 11:13:20.868457 u2DelayCellOfst[5]=0 cells (0 PI)
7696 11:13:20.871675 u2DelayCellOfst[6]=20 cells (6 PI)
7697 11:13:20.875190 u2DelayCellOfst[7]=16 cells (5 PI)
7698 11:13:20.878447 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7699 11:13:20.881650 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7700 11:13:20.884940 == TX Byte 1 ==
7701 11:13:20.888285 u2DelayCellOfst[8]=0 cells (0 PI)
7702 11:13:20.891528 u2DelayCellOfst[9]=3 cells (1 PI)
7703 11:13:20.891948 u2DelayCellOfst[10]=10 cells (3 PI)
7704 11:13:20.894792 u2DelayCellOfst[11]=3 cells (1 PI)
7705 11:13:20.898385 u2DelayCellOfst[12]=13 cells (4 PI)
7706 11:13:20.901351 u2DelayCellOfst[13]=10 cells (3 PI)
7707 11:13:20.904654 u2DelayCellOfst[14]=13 cells (4 PI)
7708 11:13:20.908835 u2DelayCellOfst[15]=10 cells (3 PI)
7709 11:13:20.914611 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7710 11:13:20.918062 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7711 11:13:20.918583 DramC Write-DBI on
7712 11:13:20.918921 ==
7713 11:13:20.921135 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 11:13:20.927901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 11:13:20.928447 ==
7716 11:13:20.928834
7717 11:13:20.929209
7718 11:13:20.929563 TX Vref Scan disable
7719 11:13:20.932068 == TX Byte 0 ==
7720 11:13:20.935287 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7721 11:13:20.938543 == TX Byte 1 ==
7722 11:13:20.942272 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7723 11:13:20.945317 DramC Write-DBI off
7724 11:13:20.945736
7725 11:13:20.946069 [DATLAT]
7726 11:13:20.946377 Freq=1600, CH0 RK0
7727 11:13:20.946677
7728 11:13:20.948454 DATLAT Default: 0xf
7729 11:13:20.951761 0, 0xFFFF, sum = 0
7730 11:13:20.952186 1, 0xFFFF, sum = 0
7731 11:13:20.955142 2, 0xFFFF, sum = 0
7732 11:13:20.955736 3, 0xFFFF, sum = 0
7733 11:13:20.958178 4, 0xFFFF, sum = 0
7734 11:13:20.958602 5, 0xFFFF, sum = 0
7735 11:13:20.961860 6, 0xFFFF, sum = 0
7736 11:13:20.962337 7, 0xFFFF, sum = 0
7737 11:13:20.965247 8, 0xFFFF, sum = 0
7738 11:13:20.965670 9, 0xFFFF, sum = 0
7739 11:13:20.968522 10, 0xFFFF, sum = 0
7740 11:13:20.968968 11, 0xFFFF, sum = 0
7741 11:13:20.971682 12, 0xFFFF, sum = 0
7742 11:13:20.972124 13, 0xFFFF, sum = 0
7743 11:13:20.975116 14, 0x0, sum = 1
7744 11:13:20.975651 15, 0x0, sum = 2
7745 11:13:20.978081 16, 0x0, sum = 3
7746 11:13:20.978630 17, 0x0, sum = 4
7747 11:13:20.981460 best_step = 15
7748 11:13:20.981876
7749 11:13:20.982208 ==
7750 11:13:20.984588 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 11:13:20.987891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 11:13:20.988311 ==
7753 11:13:20.991580 RX Vref Scan: 1
7754 11:13:20.992101
7755 11:13:20.992436 Set Vref Range= 24 -> 127
7756 11:13:20.992744
7757 11:13:20.994543 RX Vref 24 -> 127, step: 1
7758 11:13:20.994963
7759 11:13:20.997732 RX Delay 19 -> 252, step: 4
7760 11:13:20.998156
7761 11:13:21.001433 Set Vref, RX VrefLevel [Byte0]: 24
7762 11:13:21.004475 [Byte1]: 24
7763 11:13:21.005033
7764 11:13:21.007725 Set Vref, RX VrefLevel [Byte0]: 25
7765 11:13:21.010899 [Byte1]: 25
7766 11:13:21.014530
7767 11:13:21.014960 Set Vref, RX VrefLevel [Byte0]: 26
7768 11:13:21.018031 [Byte1]: 26
7769 11:13:21.022495
7770 11:13:21.022913 Set Vref, RX VrefLevel [Byte0]: 27
7771 11:13:21.025703 [Byte1]: 27
7772 11:13:21.030002
7773 11:13:21.030419 Set Vref, RX VrefLevel [Byte0]: 28
7774 11:13:21.033504 [Byte1]: 28
7775 11:13:21.037451
7776 11:13:21.037866 Set Vref, RX VrefLevel [Byte0]: 29
7777 11:13:21.040615 [Byte1]: 29
7778 11:13:21.045037
7779 11:13:21.045463 Set Vref, RX VrefLevel [Byte0]: 30
7780 11:13:21.048392 [Byte1]: 30
7781 11:13:21.052453
7782 11:13:21.052909 Set Vref, RX VrefLevel [Byte0]: 31
7783 11:13:21.055742 [Byte1]: 31
7784 11:13:21.060329
7785 11:13:21.060754 Set Vref, RX VrefLevel [Byte0]: 32
7786 11:13:21.063412 [Byte1]: 32
7787 11:13:21.067670
7788 11:13:21.068088 Set Vref, RX VrefLevel [Byte0]: 33
7789 11:13:21.071344 [Byte1]: 33
7790 11:13:21.075486
7791 11:13:21.075904 Set Vref, RX VrefLevel [Byte0]: 34
7792 11:13:21.078686 [Byte1]: 34
7793 11:13:21.083194
7794 11:13:21.083614 Set Vref, RX VrefLevel [Byte0]: 35
7795 11:13:21.086420 [Byte1]: 35
7796 11:13:21.090707
7797 11:13:21.091263 Set Vref, RX VrefLevel [Byte0]: 36
7798 11:13:21.093952 [Byte1]: 36
7799 11:13:21.098191
7800 11:13:21.098611 Set Vref, RX VrefLevel [Byte0]: 37
7801 11:13:21.101356 [Byte1]: 37
7802 11:13:21.105287
7803 11:13:21.105368 Set Vref, RX VrefLevel [Byte0]: 38
7804 11:13:21.109091 [Byte1]: 38
7805 11:13:21.113075
7806 11:13:21.113489 Set Vref, RX VrefLevel [Byte0]: 39
7807 11:13:21.116332 [Byte1]: 39
7808 11:13:21.121187
7809 11:13:21.121620 Set Vref, RX VrefLevel [Byte0]: 40
7810 11:13:21.124252 [Byte1]: 40
7811 11:13:21.128300
7812 11:13:21.128757 Set Vref, RX VrefLevel [Byte0]: 41
7813 11:13:21.131754 [Byte1]: 41
7814 11:13:21.135847
7815 11:13:21.136399 Set Vref, RX VrefLevel [Byte0]: 42
7816 11:13:21.139105 [Byte1]: 42
7817 11:13:21.143398
7818 11:13:21.143813 Set Vref, RX VrefLevel [Byte0]: 43
7819 11:13:21.146805 [Byte1]: 43
7820 11:13:21.150914
7821 11:13:21.151329 Set Vref, RX VrefLevel [Byte0]: 44
7822 11:13:21.154312 [Byte1]: 44
7823 11:13:21.158462
7824 11:13:21.158957 Set Vref, RX VrefLevel [Byte0]: 45
7825 11:13:21.161731 [Byte1]: 45
7826 11:13:21.166269
7827 11:13:21.166686 Set Vref, RX VrefLevel [Byte0]: 46
7828 11:13:21.169468 [Byte1]: 46
7829 11:13:21.174360
7830 11:13:21.174907 Set Vref, RX VrefLevel [Byte0]: 47
7831 11:13:21.176872 [Byte1]: 47
7832 11:13:21.181349
7833 11:13:21.181764 Set Vref, RX VrefLevel [Byte0]: 48
7834 11:13:21.184442 [Byte1]: 48
7835 11:13:21.189219
7836 11:13:21.189636 Set Vref, RX VrefLevel [Byte0]: 49
7837 11:13:21.192254 [Byte1]: 49
7838 11:13:21.196478
7839 11:13:21.197041 Set Vref, RX VrefLevel [Byte0]: 50
7840 11:13:21.200100 [Byte1]: 50
7841 11:13:21.204060
7842 11:13:21.204589 Set Vref, RX VrefLevel [Byte0]: 51
7843 11:13:21.207514 [Byte1]: 51
7844 11:13:21.211788
7845 11:13:21.212328 Set Vref, RX VrefLevel [Byte0]: 52
7846 11:13:21.214840 [Byte1]: 52
7847 11:13:21.219635
7848 11:13:21.220181 Set Vref, RX VrefLevel [Byte0]: 53
7849 11:13:21.222807 [Byte1]: 53
7850 11:13:21.227092
7851 11:13:21.230280 Set Vref, RX VrefLevel [Byte0]: 54
7852 11:13:21.233417 [Byte1]: 54
7853 11:13:21.233842
7854 11:13:21.237056 Set Vref, RX VrefLevel [Byte0]: 55
7855 11:13:21.240215 [Byte1]: 55
7856 11:13:21.240747
7857 11:13:21.243588 Set Vref, RX VrefLevel [Byte0]: 56
7858 11:13:21.246486 [Byte1]: 56
7859 11:13:21.249700
7860 11:13:21.250228 Set Vref, RX VrefLevel [Byte0]: 57
7861 11:13:21.253069 [Byte1]: 57
7862 11:13:21.257422
7863 11:13:21.258114 Set Vref, RX VrefLevel [Byte0]: 58
7864 11:13:21.260613 [Byte1]: 58
7865 11:13:21.264824
7866 11:13:21.265252 Set Vref, RX VrefLevel [Byte0]: 59
7867 11:13:21.268183 [Byte1]: 59
7868 11:13:21.272640
7869 11:13:21.273202 Set Vref, RX VrefLevel [Byte0]: 60
7870 11:13:21.275629 [Byte1]: 60
7871 11:13:21.279927
7872 11:13:21.280455 Set Vref, RX VrefLevel [Byte0]: 61
7873 11:13:21.283311 [Byte1]: 61
7874 11:13:21.287858
7875 11:13:21.288405 Set Vref, RX VrefLevel [Byte0]: 62
7876 11:13:21.290911 [Byte1]: 62
7877 11:13:21.295176
7878 11:13:21.295600 Set Vref, RX VrefLevel [Byte0]: 63
7879 11:13:21.298377 [Byte1]: 63
7880 11:13:21.302788
7881 11:13:21.303326 Set Vref, RX VrefLevel [Byte0]: 64
7882 11:13:21.306157 [Byte1]: 64
7883 11:13:21.310091
7884 11:13:21.310538 Set Vref, RX VrefLevel [Byte0]: 65
7885 11:13:21.313339 [Byte1]: 65
7886 11:13:21.317533
7887 11:13:21.317958 Set Vref, RX VrefLevel [Byte0]: 66
7888 11:13:21.320807 [Byte1]: 66
7889 11:13:21.324972
7890 11:13:21.325401 Set Vref, RX VrefLevel [Byte0]: 67
7891 11:13:21.328626 [Byte1]: 67
7892 11:13:21.332875
7893 11:13:21.333300 Set Vref, RX VrefLevel [Byte0]: 68
7894 11:13:21.336206 [Byte1]: 68
7895 11:13:21.340672
7896 11:13:21.341240 Set Vref, RX VrefLevel [Byte0]: 69
7897 11:13:21.344024 [Byte1]: 69
7898 11:13:21.347888
7899 11:13:21.348315 Set Vref, RX VrefLevel [Byte0]: 70
7900 11:13:21.351240 [Byte1]: 70
7901 11:13:21.355398
7902 11:13:21.355839 Set Vref, RX VrefLevel [Byte0]: 71
7903 11:13:21.361793 [Byte1]: 71
7904 11:13:21.362454
7905 11:13:21.365230 Set Vref, RX VrefLevel [Byte0]: 72
7906 11:13:21.368419 [Byte1]: 72
7907 11:13:21.368999
7908 11:13:21.371824 Set Vref, RX VrefLevel [Byte0]: 73
7909 11:13:21.375066 [Byte1]: 73
7910 11:13:21.375591
7911 11:13:21.378352 Set Vref, RX VrefLevel [Byte0]: 74
7912 11:13:21.381741 [Byte1]: 74
7913 11:13:21.385998
7914 11:13:21.386535 Set Vref, RX VrefLevel [Byte0]: 75
7915 11:13:21.388998 [Byte1]: 75
7916 11:13:21.393502
7917 11:13:21.393946 Set Vref, RX VrefLevel [Byte0]: 76
7918 11:13:21.396362 [Byte1]: 76
7919 11:13:21.400877
7920 11:13:21.401300 Set Vref, RX VrefLevel [Byte0]: 77
7921 11:13:21.404480 [Byte1]: 77
7922 11:13:21.408675
7923 11:13:21.409243 Set Vref, RX VrefLevel [Byte0]: 78
7924 11:13:21.412121 [Byte1]: 78
7925 11:13:21.416427
7926 11:13:21.416988 Set Vref, RX VrefLevel [Byte0]: 79
7927 11:13:21.419463 [Byte1]: 79
7928 11:13:21.423667
7929 11:13:21.424197 Set Vref, RX VrefLevel [Byte0]: 80
7930 11:13:21.426897 [Byte1]: 80
7931 11:13:21.431323
7932 11:13:21.431776 Set Vref, RX VrefLevel [Byte0]: 81
7933 11:13:21.434407 [Byte1]: 81
7934 11:13:21.438917
7935 11:13:21.439476 Final RX Vref Byte 0 = 61 to rank0
7936 11:13:21.442155 Final RX Vref Byte 1 = 60 to rank0
7937 11:13:21.445255 Final RX Vref Byte 0 = 61 to rank1
7938 11:13:21.448592 Final RX Vref Byte 1 = 60 to rank1==
7939 11:13:21.452134 Dram Type= 6, Freq= 0, CH_0, rank 0
7940 11:13:21.458921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 11:13:21.459454 ==
7942 11:13:21.459799 DQS Delay:
7943 11:13:21.461992 DQS0 = 0, DQS1 = 0
7944 11:13:21.462419 DQM Delay:
7945 11:13:21.462758 DQM0 = 136, DQM1 = 124
7946 11:13:21.465021 DQ Delay:
7947 11:13:21.468533 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7948 11:13:21.471774 DQ4 =140, DQ5 =126, DQ6 =142, DQ7 =144
7949 11:13:21.474804 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7950 11:13:21.478214 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =132
7951 11:13:21.478768
7952 11:13:21.479268
7953 11:13:21.479738
7954 11:13:21.481547 [DramC_TX_OE_Calibration] TA2
7955 11:13:21.484839 Original DQ_B0 (3 6) =30, OEN = 27
7956 11:13:21.488165 Original DQ_B1 (3 6) =30, OEN = 27
7957 11:13:21.491517 24, 0x0, End_B0=24 End_B1=24
7958 11:13:21.494869 25, 0x0, End_B0=25 End_B1=25
7959 11:13:21.495298 26, 0x0, End_B0=26 End_B1=26
7960 11:13:21.498246 27, 0x0, End_B0=27 End_B1=27
7961 11:13:21.501390 28, 0x0, End_B0=28 End_B1=28
7962 11:13:21.504637 29, 0x0, End_B0=29 End_B1=29
7963 11:13:21.505155 30, 0x0, End_B0=30 End_B1=30
7964 11:13:21.508055 31, 0x4141, End_B0=30 End_B1=30
7965 11:13:21.511737 Byte0 end_step=30 best_step=27
7966 11:13:21.514895 Byte1 end_step=30 best_step=27
7967 11:13:21.518582 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 11:13:21.521437 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 11:13:21.521955
7970 11:13:21.522297
7971 11:13:21.527824 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7972 11:13:21.530908 CH0 RK0: MR19=303, MR18=1E1C
7973 11:13:21.537671 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7974 11:13:21.538200
7975 11:13:21.541120 ----->DramcWriteLeveling(PI) begin...
7976 11:13:21.541649 ==
7977 11:13:21.544242 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 11:13:21.547438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 11:13:21.548029 ==
7980 11:13:21.550947 Write leveling (Byte 0): 39 => 39
7981 11:13:21.554024 Write leveling (Byte 1): 29 => 29
7982 11:13:21.557813 DramcWriteLeveling(PI) end<-----
7983 11:13:21.558335
7984 11:13:21.558670 ==
7985 11:13:21.560913 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 11:13:21.567572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 11:13:21.568107 ==
7988 11:13:21.568448 [Gating] SW mode calibration
7989 11:13:21.577037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7990 11:13:21.580707 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7991 11:13:21.583771 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 11:13:21.590318 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 11:13:21.593521 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 11:13:21.596719 1 4 12 | B1->B0 | 2424 3030 | 0 1 | (0 0) (0 0)
7995 11:13:21.603367 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 11:13:21.606898 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 11:13:21.610442 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 11:13:21.616665 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 11:13:21.620403 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 11:13:21.623143 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 11:13:21.630467 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8002 11:13:21.633126 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
8003 11:13:21.636699 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8004 11:13:21.643661 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 11:13:21.647079 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 11:13:21.650123 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 11:13:21.656188 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 11:13:21.659788 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 11:13:21.663183 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
8010 11:13:21.670202 1 6 12 | B1->B0 | 2f2f 4343 | 0 1 | (1 1) (0 0)
8011 11:13:21.673518 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8012 11:13:21.676921 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 11:13:21.683142 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 11:13:21.686679 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 11:13:21.689433 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 11:13:21.696402 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 11:13:21.699484 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8018 11:13:21.702644 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8019 11:13:21.709217 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8020 11:13:21.712683 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 11:13:21.715978 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 11:13:21.722632 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 11:13:21.726180 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 11:13:21.729229 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 11:13:21.735768 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 11:13:21.739391 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 11:13:21.742633 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 11:13:21.749212 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 11:13:21.752483 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 11:13:21.755875 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 11:13:21.762205 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 11:13:21.765409 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 11:13:21.768918 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 11:13:21.775987 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8035 11:13:21.778572 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8036 11:13:21.782228 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 11:13:21.785407 Total UI for P1: 0, mck2ui 16
8038 11:13:21.788697 best dqsien dly found for B0: ( 1, 9, 12)
8039 11:13:21.791892 Total UI for P1: 0, mck2ui 16
8040 11:13:21.795264 best dqsien dly found for B1: ( 1, 9, 16)
8041 11:13:21.798424 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8042 11:13:21.801751 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8043 11:13:21.802340
8044 11:13:21.808251 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8045 11:13:21.811555 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8046 11:13:21.814843 [Gating] SW calibration Done
8047 11:13:21.815265 ==
8048 11:13:21.818196 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 11:13:21.821353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 11:13:21.821781 ==
8051 11:13:21.822114 RX Vref Scan: 0
8052 11:13:21.824563
8053 11:13:21.825008 RX Vref 0 -> 0, step: 1
8054 11:13:21.825341
8055 11:13:21.827892 RX Delay 0 -> 252, step: 8
8056 11:13:21.831813 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8057 11:13:21.834686 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8058 11:13:21.841370 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8059 11:13:21.844844 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8060 11:13:21.848165 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8061 11:13:21.851405 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8062 11:13:21.854743 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8063 11:13:21.861435 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8064 11:13:21.864786 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8065 11:13:21.868053 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8066 11:13:21.871372 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8067 11:13:21.874578 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8068 11:13:21.881287 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8069 11:13:21.884539 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8070 11:13:21.887792 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8071 11:13:21.890975 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8072 11:13:21.891498 ==
8073 11:13:21.894187 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 11:13:21.900638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 11:13:21.901179 ==
8076 11:13:21.901519 DQS Delay:
8077 11:13:21.904224 DQS0 = 0, DQS1 = 0
8078 11:13:21.904664 DQM Delay:
8079 11:13:21.907358 DQM0 = 136, DQM1 = 125
8080 11:13:21.907782 DQ Delay:
8081 11:13:21.910765 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8082 11:13:21.914029 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8083 11:13:21.917213 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8084 11:13:21.920522 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8085 11:13:21.921044
8086 11:13:21.921393
8087 11:13:21.921706 ==
8088 11:13:21.923612 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 11:13:21.930142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 11:13:21.930671 ==
8091 11:13:21.931092
8092 11:13:21.931560
8093 11:13:21.932017 TX Vref Scan disable
8094 11:13:21.933706 == TX Byte 0 ==
8095 11:13:21.936932 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8096 11:13:21.943864 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8097 11:13:21.944421 == TX Byte 1 ==
8098 11:13:21.947043 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8099 11:13:21.953740 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8100 11:13:21.954245 ==
8101 11:13:21.957105 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 11:13:21.960495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 11:13:21.961042 ==
8104 11:13:21.975248
8105 11:13:21.978581 TX Vref early break, caculate TX vref
8106 11:13:21.981771 TX Vref=16, minBit 2, minWin=23, winSum=389
8107 11:13:21.985333 TX Vref=18, minBit 12, minWin=23, winSum=397
8108 11:13:21.988834 TX Vref=20, minBit 8, minWin=24, winSum=407
8109 11:13:21.991897 TX Vref=22, minBit 0, minWin=25, winSum=416
8110 11:13:21.995324 TX Vref=24, minBit 0, minWin=26, winSum=426
8111 11:13:22.001703 TX Vref=26, minBit 0, minWin=26, winSum=430
8112 11:13:22.005051 TX Vref=28, minBit 0, minWin=26, winSum=433
8113 11:13:22.008242 TX Vref=30, minBit 0, minWin=26, winSum=430
8114 11:13:22.011883 TX Vref=32, minBit 13, minWin=25, winSum=421
8115 11:13:22.015119 TX Vref=34, minBit 2, minWin=25, winSum=414
8116 11:13:22.018593 TX Vref=36, minBit 2, minWin=24, winSum=401
8117 11:13:22.024976 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
8118 11:13:22.025404
8119 11:13:22.028489 Final TX Range 0 Vref 28
8120 11:13:22.029048
8121 11:13:22.029541 ==
8122 11:13:22.031784 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 11:13:22.034893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 11:13:22.035314 ==
8125 11:13:22.035661
8126 11:13:22.037981
8127 11:13:22.038395 TX Vref Scan disable
8128 11:13:22.044627 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8129 11:13:22.045162 == TX Byte 0 ==
8130 11:13:22.047894 u2DelayCellOfst[0]=10 cells (3 PI)
8131 11:13:22.051300 u2DelayCellOfst[1]=16 cells (5 PI)
8132 11:13:22.054754 u2DelayCellOfst[2]=10 cells (3 PI)
8133 11:13:22.058194 u2DelayCellOfst[3]=10 cells (3 PI)
8134 11:13:22.061393 u2DelayCellOfst[4]=6 cells (2 PI)
8135 11:13:22.064559 u2DelayCellOfst[5]=0 cells (0 PI)
8136 11:13:22.067903 u2DelayCellOfst[6]=16 cells (5 PI)
8137 11:13:22.071191 u2DelayCellOfst[7]=13 cells (4 PI)
8138 11:13:22.074421 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8139 11:13:22.077970 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8140 11:13:22.081252 == TX Byte 1 ==
8141 11:13:22.084559 u2DelayCellOfst[8]=0 cells (0 PI)
8142 11:13:22.087594 u2DelayCellOfst[9]=0 cells (0 PI)
8143 11:13:22.090786 u2DelayCellOfst[10]=3 cells (1 PI)
8144 11:13:22.094022 u2DelayCellOfst[11]=0 cells (0 PI)
8145 11:13:22.097719 u2DelayCellOfst[12]=10 cells (3 PI)
8146 11:13:22.100928 u2DelayCellOfst[13]=6 cells (2 PI)
8147 11:13:22.101371 u2DelayCellOfst[14]=13 cells (4 PI)
8148 11:13:22.104189 u2DelayCellOfst[15]=6 cells (2 PI)
8149 11:13:22.111184 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8150 11:13:22.114218 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8151 11:13:22.117324 DramC Write-DBI on
8152 11:13:22.117745 ==
8153 11:13:22.121004 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 11:13:22.124271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 11:13:22.124859 ==
8156 11:13:22.125208
8157 11:13:22.125521
8158 11:13:22.127450 TX Vref Scan disable
8159 11:13:22.127871 == TX Byte 0 ==
8160 11:13:22.134320 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8161 11:13:22.134848 == TX Byte 1 ==
8162 11:13:22.137273 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8163 11:13:22.140642 DramC Write-DBI off
8164 11:13:22.141105
8165 11:13:22.141443 [DATLAT]
8166 11:13:22.144053 Freq=1600, CH0 RK1
8167 11:13:22.144584
8168 11:13:22.144962 DATLAT Default: 0xf
8169 11:13:22.147241 0, 0xFFFF, sum = 0
8170 11:13:22.147669 1, 0xFFFF, sum = 0
8171 11:13:22.150421 2, 0xFFFF, sum = 0
8172 11:13:22.150847 3, 0xFFFF, sum = 0
8173 11:13:22.153914 4, 0xFFFF, sum = 0
8174 11:13:22.157271 5, 0xFFFF, sum = 0
8175 11:13:22.157817 6, 0xFFFF, sum = 0
8176 11:13:22.160335 7, 0xFFFF, sum = 0
8177 11:13:22.160808 8, 0xFFFF, sum = 0
8178 11:13:22.164009 9, 0xFFFF, sum = 0
8179 11:13:22.164545 10, 0xFFFF, sum = 0
8180 11:13:22.167270 11, 0xFFFF, sum = 0
8181 11:13:22.167807 12, 0xFFFF, sum = 0
8182 11:13:22.170749 13, 0xFFFF, sum = 0
8183 11:13:22.171305 14, 0x0, sum = 1
8184 11:13:22.174038 15, 0x0, sum = 2
8185 11:13:22.174586 16, 0x0, sum = 3
8186 11:13:22.177371 17, 0x0, sum = 4
8187 11:13:22.177909 best_step = 15
8188 11:13:22.178251
8189 11:13:22.178565 ==
8190 11:13:22.180327 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 11:13:22.183907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 11:13:22.187114 ==
8193 11:13:22.187657 RX Vref Scan: 0
8194 11:13:22.188003
8195 11:13:22.190179 RX Vref 0 -> 0, step: 1
8196 11:13:22.190549
8197 11:13:22.193464 RX Delay 11 -> 252, step: 4
8198 11:13:22.196837 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8199 11:13:22.200086 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8200 11:13:22.203387 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8201 11:13:22.210259 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8202 11:13:22.213435 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8203 11:13:22.216545 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8204 11:13:22.220093 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8205 11:13:22.223372 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8206 11:13:22.226688 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8207 11:13:22.233195 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8208 11:13:22.236283 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8209 11:13:22.239882 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8210 11:13:22.242753 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8211 11:13:22.249589 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8212 11:13:22.252816 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8213 11:13:22.256483 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8214 11:13:22.257053 ==
8215 11:13:22.259732 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 11:13:22.263070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 11:13:22.263504 ==
8218 11:13:22.266204 DQS Delay:
8219 11:13:22.266623 DQS0 = 0, DQS1 = 0
8220 11:13:22.269270 DQM Delay:
8221 11:13:22.269694 DQM0 = 133, DQM1 = 123
8222 11:13:22.272565 DQ Delay:
8223 11:13:22.275878 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8224 11:13:22.279709 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8225 11:13:22.282807 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8226 11:13:22.286180 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8227 11:13:22.286600
8228 11:13:22.286930
8229 11:13:22.287240
8230 11:13:22.289462 [DramC_TX_OE_Calibration] TA2
8231 11:13:22.292644 Original DQ_B0 (3 6) =30, OEN = 27
8232 11:13:22.296128 Original DQ_B1 (3 6) =30, OEN = 27
8233 11:13:22.296553 24, 0x0, End_B0=24 End_B1=24
8234 11:13:22.299270 25, 0x0, End_B0=25 End_B1=25
8235 11:13:22.302495 26, 0x0, End_B0=26 End_B1=26
8236 11:13:22.305833 27, 0x0, End_B0=27 End_B1=27
8237 11:13:22.309157 28, 0x0, End_B0=28 End_B1=28
8238 11:13:22.309579 29, 0x0, End_B0=29 End_B1=29
8239 11:13:22.312358 30, 0x0, End_B0=30 End_B1=30
8240 11:13:22.315571 31, 0x4141, End_B0=30 End_B1=30
8241 11:13:22.318852 Byte0 end_step=30 best_step=27
8242 11:13:22.322274 Byte1 end_step=30 best_step=27
8243 11:13:22.325486 Byte0 TX OE(2T, 0.5T) = (3, 3)
8244 11:13:22.325908 Byte1 TX OE(2T, 0.5T) = (3, 3)
8245 11:13:22.328846
8246 11:13:22.329264
8247 11:13:22.335585 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
8248 11:13:22.338672 CH0 RK1: MR19=303, MR18=1F0B
8249 11:13:22.345306 CH0_RK1: MR19=0x303, MR18=0x1F0B, DQSOSC=394, MR23=63, INC=23, DEC=15
8250 11:13:22.348321 [RxdqsGatingPostProcess] freq 1600
8251 11:13:22.351692 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8252 11:13:22.355017 best DQS0 dly(2T, 0.5T) = (1, 1)
8253 11:13:22.358189 best DQS1 dly(2T, 0.5T) = (1, 1)
8254 11:13:22.361549 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8255 11:13:22.364951 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8256 11:13:22.368194 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 11:13:22.371581 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 11:13:22.374638 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 11:13:22.378017 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 11:13:22.381404 Pre-setting of DQS Precalculation
8261 11:13:22.384929 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8262 11:13:22.385457 ==
8263 11:13:22.388114 Dram Type= 6, Freq= 0, CH_1, rank 0
8264 11:13:22.391658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 11:13:22.394262 ==
8266 11:13:22.397929 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8267 11:13:22.401346 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8268 11:13:22.407791 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8269 11:13:22.414270 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8270 11:13:22.421819 [CA 0] Center 41 (12~71) winsize 60
8271 11:13:22.425110 [CA 1] Center 42 (12~72) winsize 61
8272 11:13:22.428448 [CA 2] Center 38 (9~67) winsize 59
8273 11:13:22.431477 [CA 3] Center 36 (7~66) winsize 60
8274 11:13:22.434666 [CA 4] Center 37 (7~68) winsize 62
8275 11:13:22.438031 [CA 5] Center 36 (7~66) winsize 60
8276 11:13:22.438453
8277 11:13:22.441277 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8278 11:13:22.441699
8279 11:13:22.447620 [CATrainingPosCal] consider 1 rank data
8280 11:13:22.448112 u2DelayCellTimex100 = 290/100 ps
8281 11:13:22.454631 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8282 11:13:22.457957 CA1 delay=42 (12~72),Diff = 6 PI (20 cell)
8283 11:13:22.461239 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8284 11:13:22.464402 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8285 11:13:22.467795 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8286 11:13:22.471032 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8287 11:13:22.471462
8288 11:13:22.474731 CA PerBit enable=1, Macro0, CA PI delay=36
8289 11:13:22.475275
8290 11:13:22.477954 [CBTSetCACLKResult] CA Dly = 36
8291 11:13:22.481333 CS Dly: 9 (0~40)
8292 11:13:22.484552 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8293 11:13:22.487614 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8294 11:13:22.488042 ==
8295 11:13:22.490897 Dram Type= 6, Freq= 0, CH_1, rank 1
8296 11:13:22.497524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 11:13:22.498077 ==
8298 11:13:22.500608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8299 11:13:22.504350 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8300 11:13:22.510767 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8301 11:13:22.517082 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8302 11:13:22.524895 [CA 0] Center 41 (12~71) winsize 60
8303 11:13:22.528125 [CA 1] Center 41 (12~71) winsize 60
8304 11:13:22.531439 [CA 2] Center 38 (9~67) winsize 59
8305 11:13:22.535036 [CA 3] Center 37 (8~67) winsize 60
8306 11:13:22.538378 [CA 4] Center 37 (8~67) winsize 60
8307 11:13:22.541387 [CA 5] Center 37 (7~67) winsize 61
8308 11:13:22.541804
8309 11:13:22.544864 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8310 11:13:22.545380
8311 11:13:22.548209 [CATrainingPosCal] consider 2 rank data
8312 11:13:22.551470 u2DelayCellTimex100 = 290/100 ps
8313 11:13:22.557709 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8314 11:13:22.561331 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8315 11:13:22.564320 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8316 11:13:22.567319 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8317 11:13:22.570841 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8318 11:13:22.574151 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8319 11:13:22.574636
8320 11:13:22.577561 CA PerBit enable=1, Macro0, CA PI delay=36
8321 11:13:22.578076
8322 11:13:22.580904 [CBTSetCACLKResult] CA Dly = 36
8323 11:13:22.583883 CS Dly: 10 (0~43)
8324 11:13:22.587224 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8325 11:13:22.590488 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8326 11:13:22.590896
8327 11:13:22.593841 ----->DramcWriteLeveling(PI) begin...
8328 11:13:22.594257 ==
8329 11:13:22.597282 Dram Type= 6, Freq= 0, CH_1, rank 0
8330 11:13:22.603631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 11:13:22.604136 ==
8332 11:13:22.607649 Write leveling (Byte 0): 24 => 24
8333 11:13:22.611045 Write leveling (Byte 1): 28 => 28
8334 11:13:22.611552 DramcWriteLeveling(PI) end<-----
8335 11:13:22.611882
8336 11:13:22.614384 ==
8337 11:13:22.616858 Dram Type= 6, Freq= 0, CH_1, rank 0
8338 11:13:22.620281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 11:13:22.620864 ==
8340 11:13:22.624228 [Gating] SW mode calibration
8341 11:13:22.630777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8342 11:13:22.633943 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8343 11:13:22.640489 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 11:13:22.643753 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 11:13:22.647055 1 4 8 | B1->B0 | 2f2f 3434 | 1 0 | (0 0) (0 0)
8346 11:13:22.653391 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 11:13:22.656757 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 11:13:22.660174 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 11:13:22.666806 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 11:13:22.669981 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 11:13:22.673274 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 11:13:22.679952 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8353 11:13:22.683286 1 5 8 | B1->B0 | 2b2b 2626 | 0 0 | (1 0) (1 0)
8354 11:13:22.686074 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8355 11:13:22.693161 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 11:13:22.696486 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 11:13:22.699736 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 11:13:22.706127 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 11:13:22.710019 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 11:13:22.712829 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8361 11:13:22.719324 1 6 8 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
8362 11:13:22.723121 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 11:13:22.726130 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 11:13:22.732484 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 11:13:22.735911 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 11:13:22.739612 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 11:13:22.746063 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 11:13:22.749359 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8369 11:13:22.752410 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8370 11:13:22.759628 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8371 11:13:22.762300 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 11:13:22.765982 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 11:13:22.772199 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 11:13:22.775591 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 11:13:22.779091 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 11:13:22.785584 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 11:13:22.789106 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 11:13:22.792163 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 11:13:22.798897 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 11:13:22.802024 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 11:13:22.805199 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 11:13:22.812288 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 11:13:22.815568 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 11:13:22.818907 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8385 11:13:22.825462 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8386 11:13:22.828602 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8387 11:13:22.831853 Total UI for P1: 0, mck2ui 16
8388 11:13:22.835193 best dqsien dly found for B0: ( 1, 9, 6)
8389 11:13:22.838391 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 11:13:22.841666 Total UI for P1: 0, mck2ui 16
8391 11:13:22.844896 best dqsien dly found for B1: ( 1, 9, 10)
8392 11:13:22.847989 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8393 11:13:22.851301 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8394 11:13:22.851713
8395 11:13:22.857995 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8396 11:13:22.861245 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8397 11:13:22.864577 [Gating] SW calibration Done
8398 11:13:22.865043 ==
8399 11:13:22.868090 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 11:13:22.871377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 11:13:22.871786 ==
8402 11:13:22.872213 RX Vref Scan: 0
8403 11:13:22.872618
8404 11:13:22.874859 RX Vref 0 -> 0, step: 1
8405 11:13:22.875243
8406 11:13:22.878107 RX Delay 0 -> 252, step: 8
8407 11:13:22.881435 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8408 11:13:22.884428 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8409 11:13:22.887752 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8410 11:13:22.894484 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8411 11:13:22.897985 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8412 11:13:22.901043 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8413 11:13:22.904393 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8414 11:13:22.907698 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8415 11:13:22.914353 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8416 11:13:22.917443 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8417 11:13:22.920624 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8418 11:13:22.924424 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8419 11:13:22.927757 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8420 11:13:22.934178 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8421 11:13:22.937505 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8422 11:13:22.940833 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8423 11:13:22.941257 ==
8424 11:13:22.943973 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 11:13:22.947704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 11:13:22.950725 ==
8427 11:13:22.951181 DQS Delay:
8428 11:13:22.951517 DQS0 = 0, DQS1 = 0
8429 11:13:22.954339 DQM Delay:
8430 11:13:22.954870 DQM0 = 138, DQM1 = 130
8431 11:13:22.957381 DQ Delay:
8432 11:13:22.960791 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8433 11:13:22.964497 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8434 11:13:22.967547 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8435 11:13:22.970890 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8436 11:13:22.971411
8437 11:13:22.971756
8438 11:13:22.972062 ==
8439 11:13:22.974255 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 11:13:22.977217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 11:13:22.977648 ==
8442 11:13:22.978072
8443 11:13:22.980488
8444 11:13:22.980970 TX Vref Scan disable
8445 11:13:22.984281 == TX Byte 0 ==
8446 11:13:22.987749 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8447 11:13:22.990647 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8448 11:13:22.994000 == TX Byte 1 ==
8449 11:13:22.997205 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8450 11:13:23.000553 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8451 11:13:23.001096 ==
8452 11:13:23.003998 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 11:13:23.010260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 11:13:23.010760 ==
8455 11:13:23.021579
8456 11:13:23.024925 TX Vref early break, caculate TX vref
8457 11:13:23.028221 TX Vref=16, minBit 10, minWin=21, winSum=371
8458 11:13:23.031590 TX Vref=18, minBit 10, minWin=22, winSum=382
8459 11:13:23.035278 TX Vref=20, minBit 10, minWin=23, winSum=389
8460 11:13:23.038339 TX Vref=22, minBit 3, minWin=24, winSum=394
8461 11:13:23.044800 TX Vref=24, minBit 10, minWin=24, winSum=404
8462 11:13:23.048205 TX Vref=26, minBit 9, minWin=25, winSum=413
8463 11:13:23.051378 TX Vref=28, minBit 10, minWin=25, winSum=419
8464 11:13:23.054828 TX Vref=30, minBit 10, minWin=25, winSum=420
8465 11:13:23.058142 TX Vref=32, minBit 9, minWin=24, winSum=407
8466 11:13:23.061340 TX Vref=34, minBit 8, minWin=23, winSum=395
8467 11:13:23.067948 [TxChooseVref] Worse bit 10, Min win 25, Win sum 420, Final Vref 30
8468 11:13:23.068460
8469 11:13:23.071148 Final TX Range 0 Vref 30
8470 11:13:23.071573
8471 11:13:23.071927 ==
8472 11:13:23.074530 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 11:13:23.077994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 11:13:23.078431 ==
8475 11:13:23.081334
8476 11:13:23.081753
8477 11:13:23.082083 TX Vref Scan disable
8478 11:13:23.087850 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8479 11:13:23.088273 == TX Byte 0 ==
8480 11:13:23.091123 u2DelayCellOfst[0]=16 cells (5 PI)
8481 11:13:23.094475 u2DelayCellOfst[1]=10 cells (3 PI)
8482 11:13:23.097636 u2DelayCellOfst[2]=0 cells (0 PI)
8483 11:13:23.100744 u2DelayCellOfst[3]=3 cells (1 PI)
8484 11:13:23.104391 u2DelayCellOfst[4]=6 cells (2 PI)
8485 11:13:23.107648 u2DelayCellOfst[5]=16 cells (5 PI)
8486 11:13:23.110755 u2DelayCellOfst[6]=16 cells (5 PI)
8487 11:13:23.114119 u2DelayCellOfst[7]=3 cells (1 PI)
8488 11:13:23.117412 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8489 11:13:23.120810 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8490 11:13:23.124034 == TX Byte 1 ==
8491 11:13:23.127274 u2DelayCellOfst[8]=0 cells (0 PI)
8492 11:13:23.130529 u2DelayCellOfst[9]=3 cells (1 PI)
8493 11:13:23.134062 u2DelayCellOfst[10]=13 cells (4 PI)
8494 11:13:23.137253 u2DelayCellOfst[11]=6 cells (2 PI)
8495 11:13:23.140868 u2DelayCellOfst[12]=16 cells (5 PI)
8496 11:13:23.141349 u2DelayCellOfst[13]=20 cells (6 PI)
8497 11:13:23.144007 u2DelayCellOfst[14]=20 cells (6 PI)
8498 11:13:23.147139 u2DelayCellOfst[15]=16 cells (5 PI)
8499 11:13:23.153707 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8500 11:13:23.157520 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8501 11:13:23.157946 DramC Write-DBI on
8502 11:13:23.160850 ==
8503 11:13:23.164022 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 11:13:23.167382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 11:13:23.167887 ==
8506 11:13:23.168230
8507 11:13:23.168669
8508 11:13:23.170597 TX Vref Scan disable
8509 11:13:23.171064 == TX Byte 0 ==
8510 11:13:23.177243 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8511 11:13:23.177711 == TX Byte 1 ==
8512 11:13:23.180402 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8513 11:13:23.183670 DramC Write-DBI off
8514 11:13:23.184095
8515 11:13:23.184549 [DATLAT]
8516 11:13:23.187064 Freq=1600, CH1 RK0
8517 11:13:23.187503
8518 11:13:23.187980 DATLAT Default: 0xf
8519 11:13:23.190332 0, 0xFFFF, sum = 0
8520 11:13:23.190765 1, 0xFFFF, sum = 0
8521 11:13:23.193534 2, 0xFFFF, sum = 0
8522 11:13:23.194001 3, 0xFFFF, sum = 0
8523 11:13:23.196847 4, 0xFFFF, sum = 0
8524 11:13:23.197288 5, 0xFFFF, sum = 0
8525 11:13:23.200169 6, 0xFFFF, sum = 0
8526 11:13:23.200596 7, 0xFFFF, sum = 0
8527 11:13:23.203439 8, 0xFFFF, sum = 0
8528 11:13:23.206932 9, 0xFFFF, sum = 0
8529 11:13:23.207579 10, 0xFFFF, sum = 0
8530 11:13:23.210004 11, 0xFFFF, sum = 0
8531 11:13:23.210445 12, 0xFFFF, sum = 0
8532 11:13:23.213643 13, 0xFFFF, sum = 0
8533 11:13:23.214093 14, 0x0, sum = 1
8534 11:13:23.216843 15, 0x0, sum = 2
8535 11:13:23.217271 16, 0x0, sum = 3
8536 11:13:23.220153 17, 0x0, sum = 4
8537 11:13:23.220575 best_step = 15
8538 11:13:23.220953
8539 11:13:23.221266 ==
8540 11:13:23.223533 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 11:13:23.226390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 11:13:23.226809 ==
8543 11:13:23.229846 RX Vref Scan: 1
8544 11:13:23.230263
8545 11:13:23.233299 Set Vref Range= 24 -> 127
8546 11:13:23.233735
8547 11:13:23.234065 RX Vref 24 -> 127, step: 1
8548 11:13:23.236466
8549 11:13:23.236932 RX Delay 19 -> 252, step: 4
8550 11:13:23.237368
8551 11:13:23.239940 Set Vref, RX VrefLevel [Byte0]: 24
8552 11:13:23.243247 [Byte1]: 24
8553 11:13:23.246733
8554 11:13:23.247171 Set Vref, RX VrefLevel [Byte0]: 25
8555 11:13:23.250064 [Byte1]: 25
8556 11:13:23.254274
8557 11:13:23.254716 Set Vref, RX VrefLevel [Byte0]: 26
8558 11:13:23.257494 [Byte1]: 26
8559 11:13:23.261845
8560 11:13:23.262272 Set Vref, RX VrefLevel [Byte0]: 27
8561 11:13:23.265159 [Byte1]: 27
8562 11:13:23.269278
8563 11:13:23.269788 Set Vref, RX VrefLevel [Byte0]: 28
8564 11:13:23.272613 [Byte1]: 28
8565 11:13:23.277395
8566 11:13:23.277947 Set Vref, RX VrefLevel [Byte0]: 29
8567 11:13:23.280548 [Byte1]: 29
8568 11:13:23.284399
8569 11:13:23.284872 Set Vref, RX VrefLevel [Byte0]: 30
8570 11:13:23.288262 [Byte1]: 30
8571 11:13:23.292419
8572 11:13:23.292901 Set Vref, RX VrefLevel [Byte0]: 31
8573 11:13:23.295400 [Byte1]: 31
8574 11:13:23.299655
8575 11:13:23.300075 Set Vref, RX VrefLevel [Byte0]: 32
8576 11:13:23.303337 [Byte1]: 32
8577 11:13:23.307241
8578 11:13:23.307686 Set Vref, RX VrefLevel [Byte0]: 33
8579 11:13:23.310678 [Byte1]: 33
8580 11:13:23.314915
8581 11:13:23.315411 Set Vref, RX VrefLevel [Byte0]: 34
8582 11:13:23.318479 [Byte1]: 34
8583 11:13:23.322333
8584 11:13:23.322881 Set Vref, RX VrefLevel [Byte0]: 35
8585 11:13:23.325674 [Byte1]: 35
8586 11:13:23.330062
8587 11:13:23.330493 Set Vref, RX VrefLevel [Byte0]: 36
8588 11:13:23.333362 [Byte1]: 36
8589 11:13:23.337909
8590 11:13:23.338383 Set Vref, RX VrefLevel [Byte0]: 37
8591 11:13:23.340983 [Byte1]: 37
8592 11:13:23.345282
8593 11:13:23.345711 Set Vref, RX VrefLevel [Byte0]: 38
8594 11:13:23.348537 [Byte1]: 38
8595 11:13:23.353002
8596 11:13:23.353573 Set Vref, RX VrefLevel [Byte0]: 39
8597 11:13:23.355904 [Byte1]: 39
8598 11:13:23.360449
8599 11:13:23.360908 Set Vref, RX VrefLevel [Byte0]: 40
8600 11:13:23.363711 [Byte1]: 40
8601 11:13:23.368098
8602 11:13:23.368619 Set Vref, RX VrefLevel [Byte0]: 41
8603 11:13:23.371242 [Byte1]: 41
8604 11:13:23.375621
8605 11:13:23.376121 Set Vref, RX VrefLevel [Byte0]: 42
8606 11:13:23.378680 [Byte1]: 42
8607 11:13:23.383014
8608 11:13:23.383443 Set Vref, RX VrefLevel [Byte0]: 43
8609 11:13:23.386551 [Byte1]: 43
8610 11:13:23.390500
8611 11:13:23.390936 Set Vref, RX VrefLevel [Byte0]: 44
8612 11:13:23.393793 [Byte1]: 44
8613 11:13:23.398036
8614 11:13:23.398539 Set Vref, RX VrefLevel [Byte0]: 45
8615 11:13:23.401738 [Byte1]: 45
8616 11:13:23.406072
8617 11:13:23.406576 Set Vref, RX VrefLevel [Byte0]: 46
8618 11:13:23.408931 [Byte1]: 46
8619 11:13:23.413696
8620 11:13:23.414236 Set Vref, RX VrefLevel [Byte0]: 47
8621 11:13:23.416802 [Byte1]: 47
8622 11:13:23.420744
8623 11:13:23.421219 Set Vref, RX VrefLevel [Byte0]: 48
8624 11:13:23.424032 [Byte1]: 48
8625 11:13:23.428304
8626 11:13:23.428737 Set Vref, RX VrefLevel [Byte0]: 49
8627 11:13:23.431624 [Byte1]: 49
8628 11:13:23.436247
8629 11:13:23.436801 Set Vref, RX VrefLevel [Byte0]: 50
8630 11:13:23.439465 [Byte1]: 50
8631 11:13:23.443966
8632 11:13:23.444500 Set Vref, RX VrefLevel [Byte0]: 51
8633 11:13:23.446930 [Byte1]: 51
8634 11:13:23.451031
8635 11:13:23.451462 Set Vref, RX VrefLevel [Byte0]: 52
8636 11:13:23.454346 [Byte1]: 52
8637 11:13:23.459047
8638 11:13:23.459591 Set Vref, RX VrefLevel [Byte0]: 53
8639 11:13:23.462706 [Byte1]: 53
8640 11:13:23.466369
8641 11:13:23.466892 Set Vref, RX VrefLevel [Byte0]: 54
8642 11:13:23.469925 [Byte1]: 54
8643 11:13:23.473712
8644 11:13:23.474126 Set Vref, RX VrefLevel [Byte0]: 55
8645 11:13:23.477044 [Byte1]: 55
8646 11:13:23.481257
8647 11:13:23.481671 Set Vref, RX VrefLevel [Byte0]: 56
8648 11:13:23.485092 [Byte1]: 56
8649 11:13:23.489297
8650 11:13:23.489715 Set Vref, RX VrefLevel [Byte0]: 57
8651 11:13:23.492561 [Byte1]: 57
8652 11:13:23.496832
8653 11:13:23.497259 Set Vref, RX VrefLevel [Byte0]: 58
8654 11:13:23.499945 [Byte1]: 58
8655 11:13:23.504258
8656 11:13:23.504679 Set Vref, RX VrefLevel [Byte0]: 59
8657 11:13:23.507679 [Byte1]: 59
8658 11:13:23.511709
8659 11:13:23.512124 Set Vref, RX VrefLevel [Byte0]: 60
8660 11:13:23.515011 [Byte1]: 60
8661 11:13:23.519349
8662 11:13:23.519767 Set Vref, RX VrefLevel [Byte0]: 61
8663 11:13:23.522655 [Byte1]: 61
8664 11:13:23.526999
8665 11:13:23.527531 Set Vref, RX VrefLevel [Byte0]: 62
8666 11:13:23.530065 [Byte1]: 62
8667 11:13:23.534852
8668 11:13:23.535266 Set Vref, RX VrefLevel [Byte0]: 63
8669 11:13:23.537748 [Byte1]: 63
8670 11:13:23.542244
8671 11:13:23.542665 Set Vref, RX VrefLevel [Byte0]: 64
8672 11:13:23.545240 [Byte1]: 64
8673 11:13:23.549507
8674 11:13:23.549934 Set Vref, RX VrefLevel [Byte0]: 65
8675 11:13:23.552711 [Byte1]: 65
8676 11:13:23.556877
8677 11:13:23.556959 Set Vref, RX VrefLevel [Byte0]: 66
8678 11:13:23.560135 [Byte1]: 66
8679 11:13:23.564528
8680 11:13:23.564610 Set Vref, RX VrefLevel [Byte0]: 67
8681 11:13:23.567924 [Byte1]: 67
8682 11:13:23.571980
8683 11:13:23.572066 Set Vref, RX VrefLevel [Byte0]: 68
8684 11:13:23.575309 [Byte1]: 68
8685 11:13:23.579623
8686 11:13:23.579705 Set Vref, RX VrefLevel [Byte0]: 69
8687 11:13:23.583136 [Byte1]: 69
8688 11:13:23.587121
8689 11:13:23.587281 Set Vref, RX VrefLevel [Byte0]: 70
8690 11:13:23.590412 [Byte1]: 70
8691 11:13:23.594601
8692 11:13:23.594703 Set Vref, RX VrefLevel [Byte0]: 71
8693 11:13:23.598269 [Byte1]: 71
8694 11:13:23.602533
8695 11:13:23.602725 Set Vref, RX VrefLevel [Byte0]: 72
8696 11:13:23.605709 [Byte1]: 72
8697 11:13:23.609785
8698 11:13:23.609922 Set Vref, RX VrefLevel [Byte0]: 73
8699 11:13:23.613411 [Byte1]: 73
8700 11:13:23.617231
8701 11:13:23.617313 Set Vref, RX VrefLevel [Byte0]: 74
8702 11:13:23.620544 [Byte1]: 74
8703 11:13:23.625159
8704 11:13:23.625241 Set Vref, RX VrefLevel [Byte0]: 75
8705 11:13:23.628352 [Byte1]: 75
8706 11:13:23.632711
8707 11:13:23.632844 Final RX Vref Byte 0 = 59 to rank0
8708 11:13:23.636393 Final RX Vref Byte 1 = 61 to rank0
8709 11:13:23.639603 Final RX Vref Byte 0 = 59 to rank1
8710 11:13:23.642956 Final RX Vref Byte 1 = 61 to rank1==
8711 11:13:23.645941 Dram Type= 6, Freq= 0, CH_1, rank 0
8712 11:13:23.652974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8713 11:13:23.653406 ==
8714 11:13:23.653806 DQS Delay:
8715 11:13:23.656203 DQS0 = 0, DQS1 = 0
8716 11:13:23.656626 DQM Delay:
8717 11:13:23.657146 DQM0 = 134, DQM1 = 129
8718 11:13:23.659149 DQ Delay:
8719 11:13:23.662578 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8720 11:13:23.666036 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =132
8721 11:13:23.669403 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8722 11:13:23.672410 DQ12 =138, DQ13 =134, DQ14 =138, DQ15 =136
8723 11:13:23.672869
8724 11:13:23.673212
8725 11:13:23.673525
8726 11:13:23.676020 [DramC_TX_OE_Calibration] TA2
8727 11:13:23.678738 Original DQ_B0 (3 6) =30, OEN = 27
8728 11:13:23.682304 Original DQ_B1 (3 6) =30, OEN = 27
8729 11:13:23.685713 24, 0x0, End_B0=24 End_B1=24
8730 11:13:23.686215 25, 0x0, End_B0=25 End_B1=25
8731 11:13:23.689074 26, 0x0, End_B0=26 End_B1=26
8732 11:13:23.692375 27, 0x0, End_B0=27 End_B1=27
8733 11:13:23.695998 28, 0x0, End_B0=28 End_B1=28
8734 11:13:23.699302 29, 0x0, End_B0=29 End_B1=29
8735 11:13:23.699855 30, 0x0, End_B0=30 End_B1=30
8736 11:13:23.702522 31, 0x4141, End_B0=30 End_B1=30
8737 11:13:23.705609 Byte0 end_step=30 best_step=27
8738 11:13:23.708981 Byte1 end_step=30 best_step=27
8739 11:13:23.712130 Byte0 TX OE(2T, 0.5T) = (3, 3)
8740 11:13:23.715890 Byte1 TX OE(2T, 0.5T) = (3, 3)
8741 11:13:23.716430
8742 11:13:23.716808
8743 11:13:23.722226 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8744 11:13:23.725414 CH1 RK0: MR19=303, MR18=1826
8745 11:13:23.732095 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8746 11:13:23.732521
8747 11:13:23.735788 ----->DramcWriteLeveling(PI) begin...
8748 11:13:23.736331 ==
8749 11:13:23.738674 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 11:13:23.741939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 11:13:23.742370 ==
8752 11:13:23.745437 Write leveling (Byte 0): 24 => 24
8753 11:13:23.748504 Write leveling (Byte 1): 29 => 29
8754 11:13:23.751806 DramcWriteLeveling(PI) end<-----
8755 11:13:23.752230
8756 11:13:23.752563 ==
8757 11:13:23.754972 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 11:13:23.758909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 11:13:23.761810 ==
8760 11:13:23.762244 [Gating] SW mode calibration
8761 11:13:23.771703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8762 11:13:23.774938 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8763 11:13:23.778165 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 11:13:23.784849 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 11:13:23.787948 1 4 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8766 11:13:23.791371 1 4 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8767 11:13:23.798239 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 11:13:23.801392 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 11:13:23.804664 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 11:13:23.811027 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 11:13:23.814693 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 11:13:23.817520 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 11:13:23.824145 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 0)
8774 11:13:23.827615 1 5 12 | B1->B0 | 2323 3131 | 0 0 | (1 0) (0 1)
8775 11:13:23.830590 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 11:13:23.837347 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 11:13:23.840719 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 11:13:23.843997 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 11:13:23.850479 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 11:13:23.853945 1 6 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8781 11:13:23.857278 1 6 8 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8782 11:13:23.863759 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8783 11:13:23.867141 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 11:13:23.870157 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 11:13:23.877386 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 11:13:23.880403 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 11:13:23.883790 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 11:13:23.890062 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 11:13:23.893672 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8790 11:13:23.896997 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8791 11:13:23.903471 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 11:13:23.906871 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 11:13:23.909962 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 11:13:23.916679 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 11:13:23.919842 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 11:13:23.923154 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 11:13:23.929680 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 11:13:23.933468 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 11:13:23.936872 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 11:13:23.942954 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 11:13:23.946626 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 11:13:23.949773 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 11:13:23.956473 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 11:13:23.959778 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 11:13:23.963062 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8806 11:13:23.969613 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8807 11:13:23.970037 Total UI for P1: 0, mck2ui 16
8808 11:13:23.976098 best dqsien dly found for B0: ( 1, 9, 8)
8809 11:13:23.979408 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 11:13:23.982864 Total UI for P1: 0, mck2ui 16
8811 11:13:23.986321 best dqsien dly found for B1: ( 1, 9, 10)
8812 11:13:23.989116 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8813 11:13:23.992849 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8814 11:13:23.993315
8815 11:13:23.995658 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8816 11:13:23.999049 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8817 11:13:24.002300 [Gating] SW calibration Done
8818 11:13:24.002718 ==
8819 11:13:24.005739 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 11:13:24.012719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 11:13:24.013184 ==
8822 11:13:24.013521 RX Vref Scan: 0
8823 11:13:24.013831
8824 11:13:24.016030 RX Vref 0 -> 0, step: 1
8825 11:13:24.016451
8826 11:13:24.019258 RX Delay 0 -> 252, step: 8
8827 11:13:24.022513 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8828 11:13:24.025597 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8829 11:13:24.029085 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8830 11:13:24.032223 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8831 11:13:24.039072 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8832 11:13:24.042373 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8833 11:13:24.045720 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8834 11:13:24.049165 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8835 11:13:24.052185 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8836 11:13:24.058591 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8837 11:13:24.061888 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8838 11:13:24.065167 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8839 11:13:24.068567 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8840 11:13:24.071903 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8841 11:13:24.078374 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8842 11:13:24.081722 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8843 11:13:24.082233 ==
8844 11:13:24.085094 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 11:13:24.088456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 11:13:24.088944 ==
8847 11:13:24.092016 DQS Delay:
8848 11:13:24.092431 DQS0 = 0, DQS1 = 0
8849 11:13:24.092857 DQM Delay:
8850 11:13:24.094841 DQM0 = 136, DQM1 = 132
8851 11:13:24.095260 DQ Delay:
8852 11:13:24.098616 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8853 11:13:24.101319 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8854 11:13:24.108241 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8855 11:13:24.111355 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8856 11:13:24.111800
8857 11:13:24.112131
8858 11:13:24.112441 ==
8859 11:13:24.114675 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 11:13:24.118216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 11:13:24.118667 ==
8862 11:13:24.119025
8863 11:13:24.119339
8864 11:13:24.121506 TX Vref Scan disable
8865 11:13:24.124621 == TX Byte 0 ==
8866 11:13:24.128086 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8867 11:13:24.131360 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8868 11:13:24.134548 == TX Byte 1 ==
8869 11:13:24.137975 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8870 11:13:24.141237 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8871 11:13:24.141665 ==
8872 11:13:24.144317 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 11:13:24.147654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 11:13:24.150937 ==
8875 11:13:24.162663
8876 11:13:24.165587 TX Vref early break, caculate TX vref
8877 11:13:24.169503 TX Vref=16, minBit 9, minWin=21, winSum=376
8878 11:13:24.172521 TX Vref=18, minBit 8, minWin=23, winSum=390
8879 11:13:24.175656 TX Vref=20, minBit 8, minWin=23, winSum=397
8880 11:13:24.179127 TX Vref=22, minBit 9, minWin=23, winSum=404
8881 11:13:24.182746 TX Vref=24, minBit 8, minWin=24, winSum=411
8882 11:13:24.188884 TX Vref=26, minBit 9, minWin=24, winSum=419
8883 11:13:24.192304 TX Vref=28, minBit 8, minWin=24, winSum=419
8884 11:13:24.195272 TX Vref=30, minBit 15, minWin=24, winSum=413
8885 11:13:24.198680 TX Vref=32, minBit 8, minWin=24, winSum=407
8886 11:13:24.202055 TX Vref=34, minBit 0, minWin=24, winSum=397
8887 11:13:24.208561 [TxChooseVref] Worse bit 9, Min win 24, Win sum 419, Final Vref 26
8888 11:13:24.209064
8889 11:13:24.211964 Final TX Range 0 Vref 26
8890 11:13:24.212392
8891 11:13:24.212729 ==
8892 11:13:24.215139 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 11:13:24.218455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 11:13:24.218882 ==
8895 11:13:24.219241
8896 11:13:24.219556
8897 11:13:24.222180 TX Vref Scan disable
8898 11:13:24.228597 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8899 11:13:24.229170 == TX Byte 0 ==
8900 11:13:24.231916 u2DelayCellOfst[0]=16 cells (5 PI)
8901 11:13:24.235415 u2DelayCellOfst[1]=13 cells (4 PI)
8902 11:13:24.238703 u2DelayCellOfst[2]=0 cells (0 PI)
8903 11:13:24.242072 u2DelayCellOfst[3]=6 cells (2 PI)
8904 11:13:24.245066 u2DelayCellOfst[4]=10 cells (3 PI)
8905 11:13:24.248815 u2DelayCellOfst[5]=20 cells (6 PI)
8906 11:13:24.252093 u2DelayCellOfst[6]=20 cells (6 PI)
8907 11:13:24.255446 u2DelayCellOfst[7]=6 cells (2 PI)
8908 11:13:24.258227 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8909 11:13:24.261498 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8910 11:13:24.264810 == TX Byte 1 ==
8911 11:13:24.268179 u2DelayCellOfst[8]=0 cells (0 PI)
8912 11:13:24.268636 u2DelayCellOfst[9]=3 cells (1 PI)
8913 11:13:24.271393 u2DelayCellOfst[10]=6 cells (2 PI)
8914 11:13:24.275066 u2DelayCellOfst[11]=3 cells (1 PI)
8915 11:13:24.278218 u2DelayCellOfst[12]=10 cells (3 PI)
8916 11:13:24.281353 u2DelayCellOfst[13]=16 cells (5 PI)
8917 11:13:24.284609 u2DelayCellOfst[14]=16 cells (5 PI)
8918 11:13:24.288017 u2DelayCellOfst[15]=16 cells (5 PI)
8919 11:13:24.294663 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8920 11:13:24.297952 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8921 11:13:24.298452 DramC Write-DBI on
8922 11:13:24.298797 ==
8923 11:13:24.301267 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 11:13:24.307558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 11:13:24.308228 ==
8926 11:13:24.308695
8927 11:13:24.309130
8928 11:13:24.309443 TX Vref Scan disable
8929 11:13:24.311844 == TX Byte 0 ==
8930 11:13:24.314933 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8931 11:13:24.318521 == TX Byte 1 ==
8932 11:13:24.321858 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8933 11:13:24.324940 DramC Write-DBI off
8934 11:13:24.325378
8935 11:13:24.325713 [DATLAT]
8936 11:13:24.326025 Freq=1600, CH1 RK1
8937 11:13:24.326325
8938 11:13:24.328116 DATLAT Default: 0xf
8939 11:13:24.328548 0, 0xFFFF, sum = 0
8940 11:13:24.331615 1, 0xFFFF, sum = 0
8941 11:13:24.335151 2, 0xFFFF, sum = 0
8942 11:13:24.335598 3, 0xFFFF, sum = 0
8943 11:13:24.338265 4, 0xFFFF, sum = 0
8944 11:13:24.338693 5, 0xFFFF, sum = 0
8945 11:13:24.341487 6, 0xFFFF, sum = 0
8946 11:13:24.341971 7, 0xFFFF, sum = 0
8947 11:13:24.344814 8, 0xFFFF, sum = 0
8948 11:13:24.345275 9, 0xFFFF, sum = 0
8949 11:13:24.348218 10, 0xFFFF, sum = 0
8950 11:13:24.348701 11, 0xFFFF, sum = 0
8951 11:13:24.351582 12, 0xFFFF, sum = 0
8952 11:13:24.352047 13, 0xFFFF, sum = 0
8953 11:13:24.354892 14, 0x0, sum = 1
8954 11:13:24.355336 15, 0x0, sum = 2
8955 11:13:24.358211 16, 0x0, sum = 3
8956 11:13:24.358640 17, 0x0, sum = 4
8957 11:13:24.361385 best_step = 15
8958 11:13:24.361866
8959 11:13:24.362200 ==
8960 11:13:24.364562 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 11:13:24.367775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 11:13:24.368204 ==
8963 11:13:24.371096 RX Vref Scan: 0
8964 11:13:24.371515
8965 11:13:24.371865 RX Vref 0 -> 0, step: 1
8966 11:13:24.372177
8967 11:13:24.374447 RX Delay 19 -> 252, step: 4
8968 11:13:24.380889 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8969 11:13:24.384417 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
8970 11:13:24.387602 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8971 11:13:24.390838 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8972 11:13:24.393836 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8973 11:13:24.397208 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8974 11:13:24.403933 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8975 11:13:24.407224 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8976 11:13:24.410211 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8977 11:13:24.413967 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8978 11:13:24.420273 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8979 11:13:24.423703 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8980 11:13:24.426978 iDelay=195, Bit 12, Center 140 (91 ~ 190) 100
8981 11:13:24.429906 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8982 11:13:24.433158 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8983 11:13:24.440171 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8984 11:13:24.440285 ==
8985 11:13:24.443195 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 11:13:24.446628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 11:13:24.446722 ==
8988 11:13:24.446797 DQS Delay:
8989 11:13:24.450193 DQS0 = 0, DQS1 = 0
8990 11:13:24.450294 DQM Delay:
8991 11:13:24.453055 DQM0 = 134, DQM1 = 130
8992 11:13:24.453165 DQ Delay:
8993 11:13:24.456610 DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =132
8994 11:13:24.459699 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8995 11:13:24.462878 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
8996 11:13:24.466318 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
8997 11:13:24.466394
8998 11:13:24.469444
8999 11:13:24.469515
9000 11:13:24.469575 [DramC_TX_OE_Calibration] TA2
9001 11:13:24.473052 Original DQ_B0 (3 6) =30, OEN = 27
9002 11:13:24.476270 Original DQ_B1 (3 6) =30, OEN = 27
9003 11:13:24.479486 24, 0x0, End_B0=24 End_B1=24
9004 11:13:24.482881 25, 0x0, End_B0=25 End_B1=25
9005 11:13:24.486033 26, 0x0, End_B0=26 End_B1=26
9006 11:13:24.486117 27, 0x0, End_B0=27 End_B1=27
9007 11:13:24.489664 28, 0x0, End_B0=28 End_B1=28
9008 11:13:24.492966 29, 0x0, End_B0=29 End_B1=29
9009 11:13:24.496152 30, 0x0, End_B0=30 End_B1=30
9010 11:13:24.499428 31, 0x4545, End_B0=30 End_B1=30
9011 11:13:24.499511 Byte0 end_step=30 best_step=27
9012 11:13:24.502612 Byte1 end_step=30 best_step=27
9013 11:13:24.505959 Byte0 TX OE(2T, 0.5T) = (3, 3)
9014 11:13:24.509517 Byte1 TX OE(2T, 0.5T) = (3, 3)
9015 11:13:24.509599
9016 11:13:24.509669
9017 11:13:24.518970 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
9018 11:13:24.519057 CH1 RK1: MR19=303, MR18=1A05
9019 11:13:24.525790 CH1_RK1: MR19=0x303, MR18=0x1A05, DQSOSC=396, MR23=63, INC=23, DEC=15
9020 11:13:24.528784 [RxdqsGatingPostProcess] freq 1600
9021 11:13:24.535406 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9022 11:13:24.538837 best DQS0 dly(2T, 0.5T) = (1, 1)
9023 11:13:24.542326 best DQS1 dly(2T, 0.5T) = (1, 1)
9024 11:13:24.545639 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9025 11:13:24.549080 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9026 11:13:24.549520 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 11:13:24.552441 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 11:13:24.556170 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 11:13:24.559322 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 11:13:24.562765 Pre-setting of DQS Precalculation
9031 11:13:24.569226 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9032 11:13:24.575945 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9033 11:13:24.582470 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9034 11:13:24.582912
9035 11:13:24.583349
9036 11:13:24.585765 [Calibration Summary] 3200 Mbps
9037 11:13:24.586204 CH 0, Rank 0
9038 11:13:24.588905 SW Impedance : PASS
9039 11:13:24.592215 DUTY Scan : NO K
9040 11:13:24.592656 ZQ Calibration : PASS
9041 11:13:24.595310 Jitter Meter : NO K
9042 11:13:24.598916 CBT Training : PASS
9043 11:13:24.599351 Write leveling : PASS
9044 11:13:24.602215 RX DQS gating : PASS
9045 11:13:24.605337 RX DQ/DQS(RDDQC) : PASS
9046 11:13:24.605771 TX DQ/DQS : PASS
9047 11:13:24.608477 RX DATLAT : PASS
9048 11:13:24.611997 RX DQ/DQS(Engine): PASS
9049 11:13:24.612653 TX OE : PASS
9050 11:13:24.615224 All Pass.
9051 11:13:24.615667
9052 11:13:24.616022 CH 0, Rank 1
9053 11:13:24.618495 SW Impedance : PASS
9054 11:13:24.618932 DUTY Scan : NO K
9055 11:13:24.622068 ZQ Calibration : PASS
9056 11:13:24.625227 Jitter Meter : NO K
9057 11:13:24.625679 CBT Training : PASS
9058 11:13:24.628332 Write leveling : PASS
9059 11:13:24.628697 RX DQS gating : PASS
9060 11:13:24.631892 RX DQ/DQS(RDDQC) : PASS
9061 11:13:24.635359 TX DQ/DQS : PASS
9062 11:13:24.635757 RX DATLAT : PASS
9063 11:13:24.638318 RX DQ/DQS(Engine): PASS
9064 11:13:24.641769 TX OE : PASS
9065 11:13:24.642189 All Pass.
9066 11:13:24.642516
9067 11:13:24.642818 CH 1, Rank 0
9068 11:13:24.645208 SW Impedance : PASS
9069 11:13:24.648371 DUTY Scan : NO K
9070 11:13:24.648871 ZQ Calibration : PASS
9071 11:13:24.651504 Jitter Meter : NO K
9072 11:13:24.654890 CBT Training : PASS
9073 11:13:24.655306 Write leveling : PASS
9074 11:13:24.658228 RX DQS gating : PASS
9075 11:13:24.661448 RX DQ/DQS(RDDQC) : PASS
9076 11:13:24.661875 TX DQ/DQS : PASS
9077 11:13:24.664990 RX DATLAT : PASS
9078 11:13:24.668247 RX DQ/DQS(Engine): PASS
9079 11:13:24.668672 TX OE : PASS
9080 11:13:24.671585 All Pass.
9081 11:13:24.672040
9082 11:13:24.672390 CH 1, Rank 1
9083 11:13:24.674795 SW Impedance : PASS
9084 11:13:24.675221 DUTY Scan : NO K
9085 11:13:24.677794 ZQ Calibration : PASS
9086 11:13:24.681486 Jitter Meter : NO K
9087 11:13:24.681913 CBT Training : PASS
9088 11:13:24.684646 Write leveling : PASS
9089 11:13:24.687884 RX DQS gating : PASS
9090 11:13:24.688313 RX DQ/DQS(RDDQC) : PASS
9091 11:13:24.691243 TX DQ/DQS : PASS
9092 11:13:24.694500 RX DATLAT : PASS
9093 11:13:24.694973 RX DQ/DQS(Engine): PASS
9094 11:13:24.697870 TX OE : PASS
9095 11:13:24.698306 All Pass.
9096 11:13:24.698645
9097 11:13:24.701420 DramC Write-DBI on
9098 11:13:24.704644 PER_BANK_REFRESH: Hybrid Mode
9099 11:13:24.705134 TX_TRACKING: ON
9100 11:13:24.714313 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9101 11:13:24.721017 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9102 11:13:24.727435 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9103 11:13:24.730621 [FAST_K] Save calibration result to emmc
9104 11:13:24.734043 sync common calibartion params.
9105 11:13:24.737755 sync cbt_mode0:1, 1:1
9106 11:13:24.740589 dram_init: ddr_geometry: 2
9107 11:13:24.741350 dram_init: ddr_geometry: 2
9108 11:13:24.743851 dram_init: ddr_geometry: 2
9109 11:13:24.747009 0:dram_rank_size:100000000
9110 11:13:24.750796 1:dram_rank_size:100000000
9111 11:13:24.753662 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9112 11:13:24.756956 DFS_SHUFFLE_HW_MODE: ON
9113 11:13:24.760460 dramc_set_vcore_voltage set vcore to 725000
9114 11:13:24.763578 Read voltage for 1600, 0
9115 11:13:24.764281 Vio18 = 0
9116 11:13:24.764889 Vcore = 725000
9117 11:13:24.766811 Vdram = 0
9118 11:13:24.767180 Vddq = 0
9119 11:13:24.767501 Vmddr = 0
9120 11:13:24.770221 switch to 3200 Mbps bootup
9121 11:13:24.773243 [DramcRunTimeConfig]
9122 11:13:24.773936 PHYPLL
9123 11:13:24.774464 DPM_CONTROL_AFTERK: ON
9124 11:13:24.776639 PER_BANK_REFRESH: ON
9125 11:13:24.780032 REFRESH_OVERHEAD_REDUCTION: ON
9126 11:13:24.780456 CMD_PICG_NEW_MODE: OFF
9127 11:13:24.783754 XRTWTW_NEW_MODE: ON
9128 11:13:24.787041 XRTRTR_NEW_MODE: ON
9129 11:13:24.787576 TX_TRACKING: ON
9130 11:13:24.790331 RDSEL_TRACKING: OFF
9131 11:13:24.790752 DQS Precalculation for DVFS: ON
9132 11:13:24.793740 RX_TRACKING: OFF
9133 11:13:24.794165 HW_GATING DBG: ON
9134 11:13:24.796725 ZQCS_ENABLE_LP4: ON
9135 11:13:24.796944 RX_PICG_NEW_MODE: ON
9136 11:13:24.799817 TX_PICG_NEW_MODE: ON
9137 11:13:24.803311 ENABLE_RX_DCM_DPHY: ON
9138 11:13:24.806556 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9139 11:13:24.806641 DUMMY_READ_FOR_TRACKING: OFF
9140 11:13:24.809881 !!! SPM_CONTROL_AFTERK: OFF
9141 11:13:24.813095 !!! SPM could not control APHY
9142 11:13:24.816384 IMPEDANCE_TRACKING: ON
9143 11:13:24.816462 TEMP_SENSOR: ON
9144 11:13:24.819628 HW_SAVE_FOR_SR: OFF
9145 11:13:24.822736 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9146 11:13:24.825969 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9147 11:13:24.826070 Read ODT Tracking: ON
9148 11:13:24.829225 Refresh Rate DeBounce: ON
9149 11:13:24.832625 DFS_NO_QUEUE_FLUSH: ON
9150 11:13:24.836055 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9151 11:13:24.836130 ENABLE_DFS_RUNTIME_MRW: OFF
9152 11:13:24.839722 DDR_RESERVE_NEW_MODE: ON
9153 11:13:24.842824 MR_CBT_SWITCH_FREQ: ON
9154 11:13:24.843242 =========================
9155 11:13:24.862586 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9156 11:13:24.866094 dram_init: ddr_geometry: 2
9157 11:13:24.884348 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9158 11:13:24.887682 dram_init: dram init end (result: 0)
9159 11:13:24.894131 DRAM-K: Full calibration passed in 24501 msecs
9160 11:13:24.897581 MRC: failed to locate region type 0.
9161 11:13:24.898091 DRAM rank0 size:0x100000000,
9162 11:13:24.900601 DRAM rank1 size=0x100000000
9163 11:13:24.910475 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9164 11:13:24.917047 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9165 11:13:24.923465 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9166 11:13:24.933094 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9167 11:13:24.933179 DRAM rank0 size:0x100000000,
9168 11:13:24.936831 DRAM rank1 size=0x100000000
9169 11:13:24.936915 CBMEM:
9170 11:13:24.939933 IMD: root @ 0xfffff000 254 entries.
9171 11:13:24.942981 IMD: root @ 0xffffec00 62 entries.
9172 11:13:24.946505 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9173 11:13:24.952983 WARNING: RO_VPD is uninitialized or empty.
9174 11:13:24.956431 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9175 11:13:24.963718 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9176 11:13:24.976512 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9177 11:13:24.988196 BS: romstage times (exec / console): total (unknown) / 23997 ms
9178 11:13:24.988280
9179 11:13:24.988345
9180 11:13:24.998538 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9181 11:13:25.001646 ARM64: Exception handlers installed.
9182 11:13:25.005035 ARM64: Testing exception
9183 11:13:25.008069 ARM64: Done test exception
9184 11:13:25.008529 Enumerating buses...
9185 11:13:25.011572 Show all devs... Before device enumeration.
9186 11:13:25.015067 Root Device: enabled 1
9187 11:13:25.018201 CPU_CLUSTER: 0: enabled 1
9188 11:13:25.018648 CPU: 00: enabled 1
9189 11:13:25.021365 Compare with tree...
9190 11:13:25.021790 Root Device: enabled 1
9191 11:13:25.024824 CPU_CLUSTER: 0: enabled 1
9192 11:13:25.027843 CPU: 00: enabled 1
9193 11:13:25.028300 Root Device scanning...
9194 11:13:25.031355 scan_static_bus for Root Device
9195 11:13:25.034539 CPU_CLUSTER: 0 enabled
9196 11:13:25.037832 scan_static_bus for Root Device done
9197 11:13:25.041113 scan_bus: bus Root Device finished in 8 msecs
9198 11:13:25.041563 done
9199 11:13:25.048030 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9200 11:13:25.051108 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9201 11:13:25.057755 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9202 11:13:25.060717 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9203 11:13:25.063969 Allocating resources...
9204 11:13:25.067134 Reading resources...
9205 11:13:25.070769 Root Device read_resources bus 0 link: 0
9206 11:13:25.073829 DRAM rank0 size:0x100000000,
9207 11:13:25.073906 DRAM rank1 size=0x100000000
9208 11:13:25.080224 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9209 11:13:25.080303 CPU: 00 missing read_resources
9210 11:13:25.086670 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9211 11:13:25.090164 Root Device read_resources bus 0 link: 0 done
9212 11:13:25.093437 Done reading resources.
9213 11:13:25.096707 Show resources in subtree (Root Device)...After reading.
9214 11:13:25.099907 Root Device child on link 0 CPU_CLUSTER: 0
9215 11:13:25.103421 CPU_CLUSTER: 0 child on link 0 CPU: 00
9216 11:13:25.113199 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9217 11:13:25.113385 CPU: 00
9218 11:13:25.119770 Root Device assign_resources, bus 0 link: 0
9219 11:13:25.123080 CPU_CLUSTER: 0 missing set_resources
9220 11:13:25.126366 Root Device assign_resources, bus 0 link: 0 done
9221 11:13:25.129476 Done setting resources.
9222 11:13:25.132685 Show resources in subtree (Root Device)...After assigning values.
9223 11:13:25.136344 Root Device child on link 0 CPU_CLUSTER: 0
9224 11:13:25.143095 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 11:13:25.149470 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 11:13:25.152688 CPU: 00
9227 11:13:25.152831 Done allocating resources.
9228 11:13:25.159499 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9229 11:13:25.159643 Enabling resources...
9230 11:13:25.162731 done.
9231 11:13:25.166067 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9232 11:13:25.169326 Initializing devices...
9233 11:13:25.169488 Root Device init
9234 11:13:25.172619 init hardware done!
9235 11:13:25.172830 0x00000018: ctrlr->caps
9236 11:13:25.175906 52.000 MHz: ctrlr->f_max
9237 11:13:25.179307 0.400 MHz: ctrlr->f_min
9238 11:13:25.182508 0x40ff8080: ctrlr->voltages
9239 11:13:25.183014 sclk: 390625
9240 11:13:25.183412 Bus Width = 1
9241 11:13:25.185887 sclk: 390625
9242 11:13:25.186262 Bus Width = 1
9243 11:13:25.189408 Early init status = 3
9244 11:13:25.192458 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9245 11:13:25.195863 in-header: 03 fc 00 00 01 00 00 00
9246 11:13:25.199546 in-data: 00
9247 11:13:25.202815 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9248 11:13:25.206975 in-header: 03 fd 00 00 00 00 00 00
9249 11:13:25.210217 in-data:
9250 11:13:25.213554 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9251 11:13:25.217438 in-header: 03 fc 00 00 01 00 00 00
9252 11:13:25.220821 in-data: 00
9253 11:13:25.223992 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9254 11:13:25.228336 in-header: 03 fd 00 00 00 00 00 00
9255 11:13:25.231998 in-data:
9256 11:13:25.234931 [SSUSB] Setting up USB HOST controller...
9257 11:13:25.238485 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9258 11:13:25.241781 [SSUSB] phy power-on done.
9259 11:13:25.244932 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9260 11:13:25.251808 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9261 11:13:25.254798 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9262 11:13:25.261194 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9263 11:13:25.267616 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9264 11:13:25.274350 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9265 11:13:25.281103 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9266 11:13:25.287577 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9267 11:13:25.290699 SPM: binary array size = 0x9dc
9268 11:13:25.294193 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9269 11:13:25.300992 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9270 11:13:25.307594 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9271 11:13:25.313937 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9272 11:13:25.317133 configure_display: Starting display init
9273 11:13:25.351541 anx7625_power_on_init: Init interface.
9274 11:13:25.354860 anx7625_disable_pd_protocol: Disabled PD feature.
9275 11:13:25.358117 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9276 11:13:25.385925 anx7625_start_dp_work: Secure OCM version=00
9277 11:13:25.389261 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9278 11:13:25.404038 sp_tx_get_edid_block: EDID Block = 1
9279 11:13:25.506371 Extracted contents:
9280 11:13:25.509718 header: 00 ff ff ff ff ff ff 00
9281 11:13:25.513057 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9282 11:13:25.516467 version: 01 04
9283 11:13:25.519531 basic params: 95 1f 11 78 0a
9284 11:13:25.523019 chroma info: 76 90 94 55 54 90 27 21 50 54
9285 11:13:25.526151 established: 00 00 00
9286 11:13:25.532601 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9287 11:13:25.535991 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9288 11:13:25.542491 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9289 11:13:25.549039 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9290 11:13:25.556069 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9291 11:13:25.559090 extensions: 00
9292 11:13:25.559185 checksum: fb
9293 11:13:25.559260
9294 11:13:25.562305 Manufacturer: IVO Model 57d Serial Number 0
9295 11:13:25.565704 Made week 0 of 2020
9296 11:13:25.569089 EDID version: 1.4
9297 11:13:25.569200 Digital display
9298 11:13:25.572310 6 bits per primary color channel
9299 11:13:25.572421 DisplayPort interface
9300 11:13:25.576067 Maximum image size: 31 cm x 17 cm
9301 11:13:25.579401 Gamma: 220%
9302 11:13:25.579534 Check DPMS levels
9303 11:13:25.582518 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9304 11:13:25.588966 First detailed timing is preferred timing
9305 11:13:25.589138 Established timings supported:
9306 11:13:25.592275 Standard timings supported:
9307 11:13:25.595496 Detailed timings
9308 11:13:25.598745 Hex of detail: 383680a07038204018303c0035ae10000019
9309 11:13:25.605508 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9310 11:13:25.609088 0780 0798 07c8 0820 hborder 0
9311 11:13:25.612497 0438 043b 0447 0458 vborder 0
9312 11:13:25.615607 -hsync -vsync
9313 11:13:25.616026 Did detailed timing
9314 11:13:25.622000 Hex of detail: 000000000000000000000000000000000000
9315 11:13:25.625215 Manufacturer-specified data, tag 0
9316 11:13:25.628891 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9317 11:13:25.632096 ASCII string: InfoVision
9318 11:13:25.635367 Hex of detail: 000000fe00523134304e574635205248200a
9319 11:13:25.638781 ASCII string: R140NWF5 RH
9320 11:13:25.638881 Checksum
9321 11:13:25.642012 Checksum: 0xfb (valid)
9322 11:13:25.644967 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9323 11:13:25.648686 DSI data_rate: 832800000 bps
9324 11:13:25.655120 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9325 11:13:25.658190 anx7625_parse_edid: pixelclock(138800).
9326 11:13:25.661619 hactive(1920), hsync(48), hfp(24), hbp(88)
9327 11:13:25.664700 vactive(1080), vsync(12), vfp(3), vbp(17)
9328 11:13:25.668356 anx7625_dsi_config: config dsi.
9329 11:13:25.674972 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9330 11:13:25.688604 anx7625_dsi_config: success to config DSI
9331 11:13:25.691966 anx7625_dp_start: MIPI phy setup OK.
9332 11:13:25.695172 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9333 11:13:25.698632 mtk_ddp_mode_set invalid vrefresh 60
9334 11:13:25.701888 main_disp_path_setup
9335 11:13:25.701989 ovl_layer_smi_id_en
9336 11:13:25.704776 ovl_layer_smi_id_en
9337 11:13:25.704888 ccorr_config
9338 11:13:25.704975 aal_config
9339 11:13:25.708083 gamma_config
9340 11:13:25.708213 postmask_config
9341 11:13:25.711667 dither_config
9342 11:13:25.714914 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9343 11:13:25.721591 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9344 11:13:25.724931 Root Device init finished in 551 msecs
9345 11:13:25.728439 CPU_CLUSTER: 0 init
9346 11:13:25.734943 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9347 11:13:25.741645 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9348 11:13:25.741951 APU_MBOX 0x190000b0 = 0x10001
9349 11:13:25.744993 APU_MBOX 0x190001b0 = 0x10001
9350 11:13:25.747991 APU_MBOX 0x190005b0 = 0x10001
9351 11:13:25.751495 APU_MBOX 0x190006b0 = 0x10001
9352 11:13:25.757872 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9353 11:13:25.767955 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9354 11:13:25.780154 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9355 11:13:25.786668 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9356 11:13:25.798202 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9357 11:13:25.807330 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9358 11:13:25.810908 CPU_CLUSTER: 0 init finished in 81 msecs
9359 11:13:25.814109 Devices initialized
9360 11:13:25.817380 Show all devs... After init.
9361 11:13:25.817930 Root Device: enabled 1
9362 11:13:25.820691 CPU_CLUSTER: 0: enabled 1
9363 11:13:25.823846 CPU: 00: enabled 1
9364 11:13:25.827221 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9365 11:13:25.830630 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9366 11:13:25.834029 ELOG: NV offset 0x57f000 size 0x1000
9367 11:13:25.840806 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9368 11:13:25.847459 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9369 11:13:25.850696 ELOG: Event(17) added with size 13 at 2023-06-05 11:13:23 UTC
9370 11:13:25.857365 out: cmd=0x121: 03 db 21 01 00 00 00 00
9371 11:13:25.860632 in-header: 03 30 00 00 2c 00 00 00
9372 11:13:25.873969 in-data: 2f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9373 11:13:25.877050 ELOG: Event(A1) added with size 10 at 2023-06-05 11:13:23 UTC
9374 11:13:25.883706 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9375 11:13:25.890524 ELOG: Event(A0) added with size 9 at 2023-06-05 11:13:23 UTC
9376 11:13:25.893677 elog_add_boot_reason: Logged dev mode boot
9377 11:13:25.900135 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9378 11:13:25.900573 Finalize devices...
9379 11:13:25.903158 Devices finalized
9380 11:13:25.906994 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9381 11:13:25.910137 Writing coreboot table at 0xffe64000
9382 11:13:25.916829 0. 000000000010a000-0000000000113fff: RAMSTAGE
9383 11:13:25.920051 1. 0000000040000000-00000000400fffff: RAM
9384 11:13:25.923338 2. 0000000040100000-000000004032afff: RAMSTAGE
9385 11:13:25.926250 3. 000000004032b000-00000000545fffff: RAM
9386 11:13:25.929842 4. 0000000054600000-000000005465ffff: BL31
9387 11:13:25.933011 5. 0000000054660000-00000000ffe63fff: RAM
9388 11:13:25.939717 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9389 11:13:25.942809 7. 0000000100000000-000000023fffffff: RAM
9390 11:13:25.946202 Passing 5 GPIOs to payload:
9391 11:13:25.949674 NAME | PORT | POLARITY | VALUE
9392 11:13:25.956343 EC in RW | 0x000000aa | low | undefined
9393 11:13:25.959579 EC interrupt | 0x00000005 | low | undefined
9394 11:13:25.966526 TPM interrupt | 0x000000ab | high | undefined
9395 11:13:25.969559 SD card detect | 0x00000011 | high | undefined
9396 11:13:25.972879 speaker enable | 0x00000093 | high | undefined
9397 11:13:25.976112 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9398 11:13:25.979395 in-header: 03 f9 00 00 02 00 00 00
9399 11:13:25.982770 in-data: 02 00
9400 11:13:25.986100 ADC[4]: Raw value=901032 ID=7
9401 11:13:25.989396 ADC[3]: Raw value=213179 ID=1
9402 11:13:25.989832 RAM Code: 0x71
9403 11:13:25.992800 ADC[6]: Raw value=74502 ID=0
9404 11:13:25.996065 ADC[5]: Raw value=212441 ID=1
9405 11:13:25.996626 SKU Code: 0x1
9406 11:13:26.002729 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4ba3
9407 11:13:26.003296 coreboot table: 964 bytes.
9408 11:13:26.005867 IMD ROOT 0. 0xfffff000 0x00001000
9409 11:13:26.009346 IMD SMALL 1. 0xffffe000 0x00001000
9410 11:13:26.012734 RO MCACHE 2. 0xffffc000 0x00001104
9411 11:13:26.016020 CONSOLE 3. 0xfff7c000 0x00080000
9412 11:13:26.019022 FMAP 4. 0xfff7b000 0x00000452
9413 11:13:26.022341 TIME STAMP 5. 0xfff7a000 0x00000910
9414 11:13:26.025563 VBOOT WORK 6. 0xfff66000 0x00014000
9415 11:13:26.028751 RAMOOPS 7. 0xffe66000 0x00100000
9416 11:13:26.032474 COREBOOT 8. 0xffe64000 0x00002000
9417 11:13:26.035670 IMD small region:
9418 11:13:26.038862 IMD ROOT 0. 0xffffec00 0x00000400
9419 11:13:26.042326 VPD 1. 0xffffeba0 0x0000004c
9420 11:13:26.045505 MMC STATUS 2. 0xffffeb80 0x00000004
9421 11:13:26.051948 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9422 11:13:26.052494 Probing TPM: done!
9423 11:13:26.058897 Connected to device vid:did:rid of 1ae0:0028:00
9424 11:13:26.065817 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9425 11:13:26.069203 Initialized TPM device CR50 revision 0
9426 11:13:26.072431 Checking cr50 for pending updates
9427 11:13:26.077551 Reading cr50 TPM mode
9428 11:13:26.086143 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9429 11:13:26.093052 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9430 11:13:26.132924 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9431 11:13:26.136268 Checking segment from ROM address 0x40100000
9432 11:13:26.139667 Checking segment from ROM address 0x4010001c
9433 11:13:26.146622 Loading segment from ROM address 0x40100000
9434 11:13:26.147059 code (compression=0)
9435 11:13:26.156190 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9436 11:13:26.162622 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9437 11:13:26.163052 it's not compressed!
9438 11:13:26.169199 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9439 11:13:26.175928 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9440 11:13:26.193075 Loading segment from ROM address 0x4010001c
9441 11:13:26.193578 Entry Point 0x80000000
9442 11:13:26.196502 Loaded segments
9443 11:13:26.199805 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9444 11:13:26.206550 Jumping to boot code at 0x80000000(0xffe64000)
9445 11:13:26.213471 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9446 11:13:26.219843 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9447 11:13:26.227719 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9448 11:13:26.231320 Checking segment from ROM address 0x40100000
9449 11:13:26.234530 Checking segment from ROM address 0x4010001c
9450 11:13:26.241054 Loading segment from ROM address 0x40100000
9451 11:13:26.241475 code (compression=1)
9452 11:13:26.247732 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9453 11:13:26.257552 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9454 11:13:26.257978 using LZMA
9455 11:13:26.266100 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9456 11:13:26.272762 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9457 11:13:26.275996 Loading segment from ROM address 0x4010001c
9458 11:13:26.276539 Entry Point 0x54601000
9459 11:13:26.279419 Loaded segments
9460 11:13:26.282470 NOTICE: MT8192 bl31_setup
9461 11:13:26.289742 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9462 11:13:26.292866 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9463 11:13:26.296320 WARNING: region 0:
9464 11:13:26.299524 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 11:13:26.299754 WARNING: region 1:
9466 11:13:26.306153 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9467 11:13:26.309592 WARNING: region 2:
9468 11:13:26.312914 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9469 11:13:26.316399 WARNING: region 3:
9470 11:13:26.319373 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9471 11:13:26.322959 WARNING: region 4:
9472 11:13:26.329286 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9473 11:13:26.329712 WARNING: region 5:
9474 11:13:26.332842 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 11:13:26.336502 WARNING: region 6:
9476 11:13:26.339269 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 11:13:26.343212 WARNING: region 7:
9478 11:13:26.346502 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 11:13:26.353003 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9480 11:13:26.356006 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9481 11:13:26.359633 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9482 11:13:26.366175 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9483 11:13:26.369547 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9484 11:13:26.372838 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9485 11:13:26.379137 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9486 11:13:26.382449 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9487 11:13:26.389146 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9488 11:13:26.392955 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9489 11:13:26.396383 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9490 11:13:26.402427 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9491 11:13:26.405817 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9492 11:13:26.409448 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9493 11:13:26.416092 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9494 11:13:26.419245 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9495 11:13:26.425655 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9496 11:13:26.429207 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9497 11:13:26.432376 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9498 11:13:26.439190 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9499 11:13:26.442448 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9500 11:13:26.448758 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9501 11:13:26.452207 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9502 11:13:26.455846 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9503 11:13:26.462783 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9504 11:13:26.465752 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9505 11:13:26.472304 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9506 11:13:26.475659 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9507 11:13:26.478975 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9508 11:13:26.486026 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9509 11:13:26.489353 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9510 11:13:26.492556 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9511 11:13:26.499411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9512 11:13:26.502692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9513 11:13:26.505616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9514 11:13:26.508943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9515 11:13:26.515563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9516 11:13:26.518883 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9517 11:13:26.522678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9518 11:13:26.525810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9519 11:13:26.532264 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9520 11:13:26.536019 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9521 11:13:26.539266 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9522 11:13:26.542414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9523 11:13:26.549246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9524 11:13:26.552691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9525 11:13:26.556069 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9526 11:13:26.562175 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9527 11:13:26.565457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9528 11:13:26.569282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9529 11:13:26.575713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9530 11:13:26.579054 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9531 11:13:26.585617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9532 11:13:26.588955 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9533 11:13:26.595399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9534 11:13:26.598648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9535 11:13:26.602403 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9536 11:13:26.608859 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9537 11:13:26.612385 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9538 11:13:26.618908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9539 11:13:26.622091 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9540 11:13:26.628543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9541 11:13:26.631754 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9542 11:13:26.638820 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9543 11:13:26.641917 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9544 11:13:26.645308 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9545 11:13:26.652227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9546 11:13:26.655228 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9547 11:13:26.661936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9548 11:13:26.665226 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9549 11:13:26.672012 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9550 11:13:26.675167 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9551 11:13:26.678479 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9552 11:13:26.685532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9553 11:13:26.688516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9554 11:13:26.694945 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9555 11:13:26.698232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9556 11:13:26.704874 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9557 11:13:26.708576 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9558 11:13:26.715509 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9559 11:13:26.719104 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9560 11:13:26.721926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9561 11:13:26.728568 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9562 11:13:26.731849 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9563 11:13:26.738518 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9564 11:13:26.741351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9565 11:13:26.748299 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9566 11:13:26.751449 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9567 11:13:26.755005 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9568 11:13:26.761612 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9569 11:13:26.764757 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9570 11:13:26.771252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9571 11:13:26.774585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9572 11:13:26.781157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9573 11:13:26.784457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9574 11:13:26.791218 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9575 11:13:26.794588 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9576 11:13:26.798001 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9577 11:13:26.801203 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9578 11:13:26.807805 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9579 11:13:26.811187 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9580 11:13:26.814544 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9581 11:13:26.821290 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9582 11:13:26.824498 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9583 11:13:26.827721 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9584 11:13:26.834532 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9585 11:13:26.838309 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9586 11:13:26.844299 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9587 11:13:26.847859 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9588 11:13:26.854316 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9589 11:13:26.857539 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9590 11:13:26.860867 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9591 11:13:26.867827 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9592 11:13:26.871388 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9593 11:13:26.878088 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9594 11:13:26.881365 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9595 11:13:26.884840 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9596 11:13:26.887634 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9597 11:13:26.894240 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9598 11:13:26.897350 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9599 11:13:26.900683 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9600 11:13:26.904198 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9601 11:13:26.910870 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9602 11:13:26.913930 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9603 11:13:26.917439 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9604 11:13:26.924007 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9605 11:13:26.927289 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9606 11:13:26.934372 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9607 11:13:26.937424 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9608 11:13:26.941003 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9609 11:13:26.947632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9610 11:13:26.950795 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9611 11:13:26.957357 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9612 11:13:26.960912 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9613 11:13:26.964513 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9614 11:13:26.970928 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9615 11:13:26.974202 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9616 11:13:26.977215 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9617 11:13:26.984159 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9618 11:13:26.986972 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9619 11:13:26.993905 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9620 11:13:26.997028 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9621 11:13:27.000410 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9622 11:13:27.006994 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9623 11:13:27.010149 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9624 11:13:27.016752 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9625 11:13:27.020718 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9626 11:13:27.024094 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9627 11:13:27.030038 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9628 11:13:27.033482 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9629 11:13:27.040525 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9630 11:13:27.044175 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9631 11:13:27.047004 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9632 11:13:27.053661 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9633 11:13:27.056719 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9634 11:13:27.063507 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9635 11:13:27.066897 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9636 11:13:27.070171 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9637 11:13:27.076759 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9638 11:13:27.080115 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9639 11:13:27.083451 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9640 11:13:27.090260 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9641 11:13:27.093524 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9642 11:13:27.100230 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9643 11:13:27.103752 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9644 11:13:27.106571 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9645 11:13:27.112970 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9646 11:13:27.116559 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9647 11:13:27.122863 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9648 11:13:27.126195 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9649 11:13:27.129672 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9650 11:13:27.136368 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9651 11:13:27.139620 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9652 11:13:27.145792 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9653 11:13:27.149161 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9654 11:13:27.152425 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9655 11:13:27.159208 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9656 11:13:27.162485 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9657 11:13:27.169025 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9658 11:13:27.172819 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9659 11:13:27.175981 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9660 11:13:27.182315 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9661 11:13:27.186139 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9662 11:13:27.192043 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9663 11:13:27.195502 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9664 11:13:27.198669 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9665 11:13:27.205106 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9666 11:13:27.208660 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9667 11:13:27.214961 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9668 11:13:27.218680 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9669 11:13:27.225130 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9670 11:13:27.228062 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9671 11:13:27.231431 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9672 11:13:27.237856 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9673 11:13:27.241425 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9674 11:13:27.247936 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9675 11:13:27.251163 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9676 11:13:27.257993 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9677 11:13:27.261737 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9678 11:13:27.264723 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9679 11:13:27.271310 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9680 11:13:27.275160 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9681 11:13:27.281662 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9682 11:13:27.284589 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9683 11:13:27.288290 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9684 11:13:27.295144 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9685 11:13:27.298225 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9686 11:13:27.304640 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9687 11:13:27.307971 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9688 11:13:27.314726 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9689 11:13:27.317690 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9690 11:13:27.320984 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9691 11:13:27.327351 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9692 11:13:27.330587 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9693 11:13:27.337489 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9694 11:13:27.340530 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9695 11:13:27.347155 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9696 11:13:27.350942 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9697 11:13:27.353989 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9698 11:13:27.360532 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9699 11:13:27.363895 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9700 11:13:27.370521 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9701 11:13:27.373544 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9702 11:13:27.380057 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9703 11:13:27.383465 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9704 11:13:27.386798 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9705 11:13:27.393874 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9706 11:13:27.396756 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9707 11:13:27.403988 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9708 11:13:27.406994 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9709 11:13:27.410252 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9710 11:13:27.413396 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9711 11:13:27.420018 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9712 11:13:27.423185 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9713 11:13:27.426703 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9714 11:13:27.433336 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9715 11:13:27.436430 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9716 11:13:27.439804 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9717 11:13:27.446468 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9718 11:13:27.449990 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9719 11:13:27.453222 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9720 11:13:27.460182 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9721 11:13:27.463108 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9722 11:13:27.466441 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9723 11:13:27.472876 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9724 11:13:27.476240 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9725 11:13:27.482805 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9726 11:13:27.486236 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9727 11:13:27.489458 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9728 11:13:27.496150 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9729 11:13:27.499397 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9730 11:13:27.502768 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9731 11:13:27.509818 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9732 11:13:27.513084 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9733 11:13:27.519710 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9734 11:13:27.522933 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9735 11:13:27.526188 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9736 11:13:27.532901 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9737 11:13:27.536086 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9738 11:13:27.539457 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9739 11:13:27.545994 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9740 11:13:27.549271 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9741 11:13:27.555382 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9742 11:13:27.558831 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9743 11:13:27.562104 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9744 11:13:27.568515 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9745 11:13:27.571904 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9746 11:13:27.575187 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9747 11:13:27.582247 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9748 11:13:27.585546 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9749 11:13:27.588656 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9750 11:13:27.592029 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9751 11:13:27.598626 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9752 11:13:27.601619 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9753 11:13:27.604807 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9754 11:13:27.608237 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9755 11:13:27.614885 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9756 11:13:27.618422 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9757 11:13:27.621842 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9758 11:13:27.625059 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9759 11:13:27.631555 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9760 11:13:27.634993 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9761 11:13:27.638071 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9762 11:13:27.645078 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9763 11:13:27.648220 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9764 11:13:27.654762 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9765 11:13:27.658233 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9766 11:13:27.664899 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9767 11:13:27.667944 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9768 11:13:27.671283 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9769 11:13:27.678132 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9770 11:13:27.681418 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9771 11:13:27.688015 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9772 11:13:27.691234 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9773 11:13:27.697921 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9774 11:13:27.701141 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9775 11:13:27.704582 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9776 11:13:27.711577 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9777 11:13:27.714875 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9778 11:13:27.721367 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9779 11:13:27.724529 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9780 11:13:27.727722 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9781 11:13:27.734231 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9782 11:13:27.737640 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9783 11:13:27.743920 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9784 11:13:27.747201 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9785 11:13:27.750581 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9786 11:13:27.756844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9787 11:13:27.760341 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9788 11:13:27.767165 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9789 11:13:27.770143 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9790 11:13:27.777032 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9791 11:13:27.780101 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9792 11:13:27.783282 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9793 11:13:27.790192 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9794 11:13:27.793622 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9795 11:13:27.799967 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9796 11:13:27.803210 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9797 11:13:27.806474 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9798 11:13:27.813399 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9799 11:13:27.816268 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9800 11:13:27.822763 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9801 11:13:27.826128 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9802 11:13:27.829445 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9803 11:13:27.836716 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9804 11:13:27.839992 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9805 11:13:27.846364 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9806 11:13:27.849707 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9807 11:13:27.855962 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9808 11:13:27.859495 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9809 11:13:27.862758 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9810 11:13:27.869741 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9811 11:13:27.872673 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9812 11:13:27.879155 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9813 11:13:27.882889 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9814 11:13:27.889307 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9815 11:13:27.892433 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9816 11:13:27.896063 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9817 11:13:27.902434 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9818 11:13:27.905740 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9819 11:13:27.912425 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9820 11:13:27.915734 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9821 11:13:27.919337 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9822 11:13:27.925654 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9823 11:13:27.928816 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9824 11:13:27.935774 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9825 11:13:27.938924 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9826 11:13:27.942427 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9827 11:13:27.948760 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9828 11:13:27.952578 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9829 11:13:27.959162 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9830 11:13:27.961858 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9831 11:13:27.968874 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9832 11:13:27.972400 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9833 11:13:27.975209 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9834 11:13:27.981834 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9835 11:13:27.985210 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9836 11:13:27.991744 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9837 11:13:27.995211 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9838 11:13:28.001978 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9839 11:13:28.004895 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9840 11:13:28.008119 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9841 11:13:28.015097 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9842 11:13:28.018344 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9843 11:13:28.024921 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9844 11:13:28.028342 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9845 11:13:28.034751 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9846 11:13:28.038001 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9847 11:13:28.044822 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9848 11:13:28.048117 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9849 11:13:28.051487 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9850 11:13:28.057710 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9851 11:13:28.061323 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9852 11:13:28.067965 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9853 11:13:28.071272 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9854 11:13:28.077507 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9855 11:13:28.080956 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9856 11:13:28.084433 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9857 11:13:28.091134 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9858 11:13:28.094406 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9859 11:13:28.100893 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9860 11:13:28.104166 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9861 11:13:28.110740 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9862 11:13:28.114288 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9863 11:13:28.120692 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9864 11:13:28.123980 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9865 11:13:28.127285 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9866 11:13:28.133828 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9867 11:13:28.137076 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9868 11:13:28.144464 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9869 11:13:28.147813 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9870 11:13:28.154344 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9871 11:13:28.157566 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9872 11:13:28.160902 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9873 11:13:28.167192 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9874 11:13:28.170236 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9875 11:13:28.176945 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9876 11:13:28.180088 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9877 11:13:28.186717 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9878 11:13:28.190174 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9879 11:13:28.196868 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9880 11:13:28.200155 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9881 11:13:28.203411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9882 11:13:28.210314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9883 11:13:28.213270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9884 11:13:28.220268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9885 11:13:28.223503 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9886 11:13:28.229712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9887 11:13:28.233309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9888 11:13:28.239968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9889 11:13:28.243114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9890 11:13:28.249810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9891 11:13:28.253148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9892 11:13:28.259655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9893 11:13:28.263235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9894 11:13:28.269571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9895 11:13:28.273271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9896 11:13:28.279175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9897 11:13:28.282581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9898 11:13:28.289565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9899 11:13:28.292996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9900 11:13:28.299599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9901 11:13:28.302358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9902 11:13:28.309026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9903 11:13:28.312033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9904 11:13:28.318895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9905 11:13:28.322284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9906 11:13:28.328727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9907 11:13:28.332003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9908 11:13:28.338464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9909 11:13:28.341888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9910 11:13:28.348424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9911 11:13:28.351993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9912 11:13:28.358327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9913 11:13:28.361707 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9914 11:13:28.365094 INFO: [APUAPC] vio 0
9915 11:13:28.368154 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9916 11:13:28.375023 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9917 11:13:28.378311 INFO: [APUAPC] D0_APC_0: 0x400510
9918 11:13:28.378763 INFO: [APUAPC] D0_APC_1: 0x0
9919 11:13:28.381654 INFO: [APUAPC] D0_APC_2: 0x1540
9920 11:13:28.384887 INFO: [APUAPC] D0_APC_3: 0x0
9921 11:13:28.388031 INFO: [APUAPC] D1_APC_0: 0xffffffff
9922 11:13:28.391623 INFO: [APUAPC] D1_APC_1: 0xffffffff
9923 11:13:28.394533 INFO: [APUAPC] D1_APC_2: 0x3fffff
9924 11:13:28.398137 INFO: [APUAPC] D1_APC_3: 0x0
9925 11:13:28.401383 INFO: [APUAPC] D2_APC_0: 0xffffffff
9926 11:13:28.404614 INFO: [APUAPC] D2_APC_1: 0xffffffff
9927 11:13:28.408234 INFO: [APUAPC] D2_APC_2: 0x3fffff
9928 11:13:28.411232 INFO: [APUAPC] D2_APC_3: 0x0
9929 11:13:28.414617 INFO: [APUAPC] D3_APC_0: 0xffffffff
9930 11:13:28.417903 INFO: [APUAPC] D3_APC_1: 0xffffffff
9931 11:13:28.421034 INFO: [APUAPC] D3_APC_2: 0x3fffff
9932 11:13:28.424511 INFO: [APUAPC] D3_APC_3: 0x0
9933 11:13:28.427724 INFO: [APUAPC] D4_APC_0: 0xffffffff
9934 11:13:28.430823 INFO: [APUAPC] D4_APC_1: 0xffffffff
9935 11:13:28.434124 INFO: [APUAPC] D4_APC_2: 0x3fffff
9936 11:13:28.437554 INFO: [APUAPC] D4_APC_3: 0x0
9937 11:13:28.440854 INFO: [APUAPC] D5_APC_0: 0xffffffff
9938 11:13:28.444066 INFO: [APUAPC] D5_APC_1: 0xffffffff
9939 11:13:28.447583 INFO: [APUAPC] D5_APC_2: 0x3fffff
9940 11:13:28.450760 INFO: [APUAPC] D5_APC_3: 0x0
9941 11:13:28.453691 INFO: [APUAPC] D6_APC_0: 0xffffffff
9942 11:13:28.457354 INFO: [APUAPC] D6_APC_1: 0xffffffff
9943 11:13:28.460734 INFO: [APUAPC] D6_APC_2: 0x3fffff
9944 11:13:28.464389 INFO: [APUAPC] D6_APC_3: 0x0
9945 11:13:28.467515 INFO: [APUAPC] D7_APC_0: 0xffffffff
9946 11:13:28.470565 INFO: [APUAPC] D7_APC_1: 0xffffffff
9947 11:13:28.474172 INFO: [APUAPC] D7_APC_2: 0x3fffff
9948 11:13:28.476964 INFO: [APUAPC] D7_APC_3: 0x0
9949 11:13:28.480499 INFO: [APUAPC] D8_APC_0: 0xffffffff
9950 11:13:28.484301 INFO: [APUAPC] D8_APC_1: 0xffffffff
9951 11:13:28.486770 INFO: [APUAPC] D8_APC_2: 0x3fffff
9952 11:13:28.490684 INFO: [APUAPC] D8_APC_3: 0x0
9953 11:13:28.493584 INFO: [APUAPC] D9_APC_0: 0xffffffff
9954 11:13:28.496962 INFO: [APUAPC] D9_APC_1: 0xffffffff
9955 11:13:28.500210 INFO: [APUAPC] D9_APC_2: 0x3fffff
9956 11:13:28.503469 INFO: [APUAPC] D9_APC_3: 0x0
9957 11:13:28.507010 INFO: [APUAPC] D10_APC_0: 0xffffffff
9958 11:13:28.510273 INFO: [APUAPC] D10_APC_1: 0xffffffff
9959 11:13:28.513315 INFO: [APUAPC] D10_APC_2: 0x3fffff
9960 11:13:28.516668 INFO: [APUAPC] D10_APC_3: 0x0
9961 11:13:28.520239 INFO: [APUAPC] D11_APC_0: 0xffffffff
9962 11:13:28.523164 INFO: [APUAPC] D11_APC_1: 0xffffffff
9963 11:13:28.526315 INFO: [APUAPC] D11_APC_2: 0x3fffff
9964 11:13:28.529713 INFO: [APUAPC] D11_APC_3: 0x0
9965 11:13:28.533213 INFO: [APUAPC] D12_APC_0: 0xffffffff
9966 11:13:28.536353 INFO: [APUAPC] D12_APC_1: 0xffffffff
9967 11:13:28.539765 INFO: [APUAPC] D12_APC_2: 0x3fffff
9968 11:13:28.543165 INFO: [APUAPC] D12_APC_3: 0x0
9969 11:13:28.546286 INFO: [APUAPC] D13_APC_0: 0xffffffff
9970 11:13:28.549515 INFO: [APUAPC] D13_APC_1: 0xffffffff
9971 11:13:28.552840 INFO: [APUAPC] D13_APC_2: 0x3fffff
9972 11:13:28.556064 INFO: [APUAPC] D13_APC_3: 0x0
9973 11:13:28.559389 INFO: [APUAPC] D14_APC_0: 0xffffffff
9974 11:13:28.563042 INFO: [APUAPC] D14_APC_1: 0xffffffff
9975 11:13:28.566181 INFO: [APUAPC] D14_APC_2: 0x3fffff
9976 11:13:28.569598 INFO: [APUAPC] D14_APC_3: 0x0
9977 11:13:28.572862 INFO: [APUAPC] D15_APC_0: 0xffffffff
9978 11:13:28.576015 INFO: [APUAPC] D15_APC_1: 0xffffffff
9979 11:13:28.579283 INFO: [APUAPC] D15_APC_2: 0x3fffff
9980 11:13:28.582938 INFO: [APUAPC] D15_APC_3: 0x0
9981 11:13:28.586361 INFO: [APUAPC] APC_CON: 0x4
9982 11:13:28.589605 INFO: [NOCDAPC] D0_APC_0: 0x0
9983 11:13:28.593161 INFO: [NOCDAPC] D0_APC_1: 0x0
9984 11:13:28.593684 INFO: [NOCDAPC] D1_APC_0: 0x0
9985 11:13:28.596491 INFO: [NOCDAPC] D1_APC_1: 0xfff
9986 11:13:28.599482 INFO: [NOCDAPC] D2_APC_0: 0x0
9987 11:13:28.602690 INFO: [NOCDAPC] D2_APC_1: 0xfff
9988 11:13:28.606045 INFO: [NOCDAPC] D3_APC_0: 0x0
9989 11:13:28.609252 INFO: [NOCDAPC] D3_APC_1: 0xfff
9990 11:13:28.613020 INFO: [NOCDAPC] D4_APC_0: 0x0
9991 11:13:28.616421 INFO: [NOCDAPC] D4_APC_1: 0xfff
9992 11:13:28.619797 INFO: [NOCDAPC] D5_APC_0: 0x0
9993 11:13:28.622927 INFO: [NOCDAPC] D5_APC_1: 0xfff
9994 11:13:28.625788 INFO: [NOCDAPC] D6_APC_0: 0x0
9995 11:13:28.626207 INFO: [NOCDAPC] D6_APC_1: 0xfff
9996 11:13:28.629278 INFO: [NOCDAPC] D7_APC_0: 0x0
9997 11:13:28.632805 INFO: [NOCDAPC] D7_APC_1: 0xfff
9998 11:13:28.635813 INFO: [NOCDAPC] D8_APC_0: 0x0
9999 11:13:28.639295 INFO: [NOCDAPC] D8_APC_1: 0xfff
10000 11:13:28.642514 INFO: [NOCDAPC] D9_APC_0: 0x0
10001 11:13:28.645821 INFO: [NOCDAPC] D9_APC_1: 0xfff
10002 11:13:28.648973 INFO: [NOCDAPC] D10_APC_0: 0x0
10003 11:13:28.652302 INFO: [NOCDAPC] D10_APC_1: 0xfff
10004 11:13:28.655730 INFO: [NOCDAPC] D11_APC_0: 0x0
10005 11:13:28.658962 INFO: [NOCDAPC] D11_APC_1: 0xfff
10006 11:13:28.662393 INFO: [NOCDAPC] D12_APC_0: 0x0
10007 11:13:28.665566 INFO: [NOCDAPC] D12_APC_1: 0xfff
10008 11:13:28.665646 INFO: [NOCDAPC] D13_APC_0: 0x0
10009 11:13:28.668897 INFO: [NOCDAPC] D13_APC_1: 0xfff
10010 11:13:28.672130 INFO: [NOCDAPC] D14_APC_0: 0x0
10011 11:13:28.675302 INFO: [NOCDAPC] D14_APC_1: 0xfff
10012 11:13:28.678759 INFO: [NOCDAPC] D15_APC_0: 0x0
10013 11:13:28.682072 INFO: [NOCDAPC] D15_APC_1: 0xfff
10014 11:13:28.685645 INFO: [NOCDAPC] APC_CON: 0x4
10015 11:13:28.688710 INFO: [APUAPC] set_apusys_apc done
10016 11:13:28.692156 INFO: [DEVAPC] devapc_init done
10017 11:13:28.695414 INFO: GICv3 without legacy support detected.
10018 11:13:28.702048 INFO: ARM GICv3 driver initialized in EL3
10019 11:13:28.705129 INFO: Maximum SPI INTID supported: 639
10020 11:13:28.708437 INFO: BL31: Initializing runtime services
10021 11:13:28.714827 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10022 11:13:28.715366 INFO: SPM: enable CPC mode
10023 11:13:28.721640 INFO: mcdi ready for mcusys-off-idle and system suspend
10024 11:13:28.724847 INFO: BL31: Preparing for EL3 exit to normal world
10025 11:13:28.731253 INFO: Entry point address = 0x80000000
10026 11:13:28.731684 INFO: SPSR = 0x8
10027 11:13:28.737842
10028 11:13:28.738266
10029 11:13:28.738604
10030 11:13:28.741293 Starting depthcharge on Spherion...
10031 11:13:28.741716
10032 11:13:28.742055 Wipe memory regions:
10033 11:13:28.742360
10034 11:13:28.744535 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10035 11:13:28.745082 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10036 11:13:28.745514 Setting prompt string to ['asurada:']
10037 11:13:28.745908 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10038 11:13:28.746567 [0x00000040000000, 0x00000054600000)
10039 11:13:28.866787
10040 11:13:28.867318 [0x00000054660000, 0x00000080000000)
10041 11:13:29.127305
10042 11:13:29.128068 [0x000000821a7280, 0x000000ffe64000)
10043 11:13:29.872444
10044 11:13:29.873049 [0x00000100000000, 0x00000240000000)
10045 11:13:31.762724
10046 11:13:31.766034 Initializing XHCI USB controller at 0x11200000.
10047 11:13:32.803588
10048 11:13:32.806509 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10049 11:13:32.806599
10050 11:13:32.806670
10051 11:13:32.806734
10052 11:13:32.807012 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10054 11:13:32.907395 asurada: tftpboot 192.168.201.1 10591211/tftp-deploy-c4dhww01/kernel/image.itb 10591211/tftp-deploy-c4dhww01/kernel/cmdline
10055 11:13:32.907574 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10056 11:13:32.907715 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10057 11:13:32.911989 tftpboot 192.168.201.1 10591211/tftp-deploy-c4dhww01/kernel/image.itp-deploy-c4dhww01/kernel/cmdline
10058 11:13:32.912076
10059 11:13:32.912141 Waiting for link
10060 11:13:33.072343
10061 11:13:33.072501 R8152: Initializing
10062 11:13:33.072600
10063 11:13:33.075746 Version 9 (ocp_data = 6010)
10064 11:13:33.075829
10065 11:13:33.078988 R8152: Done initializing
10066 11:13:33.079071
10067 11:13:33.079136 Adding net device
10068 11:13:35.025395
10069 11:13:35.025931 done.
10070 11:13:35.026279
10071 11:13:35.026597 MAC: 00:e0:4c:72:2d:d6
10072 11:13:35.026937
10073 11:13:35.028526 Sending DHCP discover... done.
10074 11:13:35.029076
10075 11:13:38.373318 Waiting for reply... done.
10076 11:13:38.373877
10077 11:13:38.374215 Sending DHCP request... done.
10078 11:13:38.376261
10079 11:13:38.381828 Waiting for reply... done.
10080 11:13:38.382245
10081 11:13:38.382571 My ip is 192.168.201.21
10082 11:13:38.382877
10083 11:13:38.385571 The DHCP server ip is 192.168.201.1
10084 11:13:38.385989
10085 11:13:38.392204 TFTP server IP predefined by user: 192.168.201.1
10086 11:13:38.392728
10087 11:13:38.398579 Bootfile predefined by user: 10591211/tftp-deploy-c4dhww01/kernel/image.itb
10088 11:13:38.398999
10089 11:13:38.399327 Sending tftp read request... done.
10090 11:13:38.401653
10091 11:13:38.406522 Waiting for the transfer...
10092 11:13:38.407070
10093 11:13:38.736200 00000000 ################################################################
10094 11:13:38.736337
10095 11:13:39.018258 00080000 ################################################################
10096 11:13:39.018395
10097 11:13:39.265645 00100000 ################################################################
10098 11:13:39.265778
10099 11:13:39.520578 00180000 ################################################################
10100 11:13:39.520713
10101 11:13:39.797422 00200000 ################################################################
10102 11:13:39.797560
10103 11:13:40.070805 00280000 ################################################################
10104 11:13:40.070942
10105 11:13:40.318978 00300000 ################################################################
10106 11:13:40.319127
10107 11:13:40.574603 00380000 ################################################################
10108 11:13:40.574736
10109 11:13:40.848550 00400000 ################################################################
10110 11:13:40.848686
10111 11:13:41.103918 00480000 ################################################################
10112 11:13:41.104052
10113 11:13:41.380744 00500000 ################################################################
10114 11:13:41.380916
10115 11:13:41.629947 00580000 ################################################################
10116 11:13:41.630083
10117 11:13:41.907981 00600000 ################################################################
10118 11:13:41.908124
10119 11:13:42.185921 00680000 ################################################################
10120 11:13:42.186053
10121 11:13:42.462251 00700000 ################################################################
10122 11:13:42.462388
10123 11:13:42.755971 00780000 ################################################################
10124 11:13:42.756110
10125 11:13:43.003189 00800000 ################################################################
10126 11:13:43.003323
10127 11:13:43.278687 00880000 ################################################################
10128 11:13:43.278818
10129 11:13:43.532441 00900000 ################################################################
10130 11:13:43.532586
10131 11:13:43.788383 00980000 ################################################################
10132 11:13:43.788521
10133 11:13:44.053759 00a00000 ################################################################
10134 11:13:44.053890
10135 11:13:44.426911 00a80000 ################################################################
10136 11:13:44.427420
10137 11:13:44.770998 00b00000 ################################################################
10138 11:13:44.771139
10139 11:13:45.021762 00b80000 ################################################################
10140 11:13:45.021898
10141 11:13:45.276481 00c00000 ################################################################
10142 11:13:45.276609
10143 11:13:45.526860 00c80000 ################################################################
10144 11:13:45.526987
10145 11:13:45.790170 00d00000 ################################################################
10146 11:13:45.790303
10147 11:13:46.040411 00d80000 ################################################################
10148 11:13:46.040542
10149 11:13:46.320908 00e00000 ################################################################
10150 11:13:46.321039
10151 11:13:46.584909 00e80000 ################################################################
10152 11:13:46.585036
10153 11:13:46.832285 00f00000 ################################################################
10154 11:13:46.832415
10155 11:13:47.080792 00f80000 ################################################################
10156 11:13:47.080938
10157 11:13:47.347192 01000000 ################################################################
10158 11:13:47.347318
10159 11:13:47.639097 01080000 ################################################################
10160 11:13:47.639231
10161 11:13:47.920197 01100000 ################################################################
10162 11:13:47.920331
10163 11:13:48.201700 01180000 ################################################################
10164 11:13:48.201855
10165 11:13:48.483260 01200000 ################################################################
10166 11:13:48.483398
10167 11:13:48.741023 01280000 ################################################################
10168 11:13:48.741158
10169 11:13:48.988260 01300000 ################################################################
10170 11:13:48.988426
10171 11:13:49.236021 01380000 ################################################################
10172 11:13:49.236180
10173 11:13:49.484422 01400000 ################################################################
10174 11:13:49.484572
10175 11:13:49.732572 01480000 ################################################################
10176 11:13:49.732702
10177 11:13:50.014893 01500000 ################################################################
10178 11:13:50.015068
10179 11:13:50.308996 01580000 ################################################################
10180 11:13:50.309148
10181 11:13:50.569636 01600000 ################################################################
10182 11:13:50.569769
10183 11:13:50.844036 01680000 ################################################################
10184 11:13:50.844169
10185 11:13:51.136103 01700000 ################################################################
10186 11:13:51.136238
10187 11:13:51.425931 01780000 ################################################################
10188 11:13:51.426072
10189 11:13:51.703342 01800000 ################################################################
10190 11:13:51.703478
10191 11:13:51.996102 01880000 ################################################################
10192 11:13:51.996240
10193 11:13:52.255778 01900000 ################################################################
10194 11:13:52.255919
10195 11:13:52.530763 01980000 ################################################################
10196 11:13:52.530900
10197 11:13:52.802368 01a00000 ################################################################
10198 11:13:52.802511
10199 11:13:53.095098 01a80000 ################################################################
10200 11:13:53.095233
10201 11:13:53.389080 01b00000 ################################################################
10202 11:13:53.389214
10203 11:13:53.675112 01b80000 ################################################################
10204 11:13:53.675249
10205 11:13:53.966373 01c00000 ################################################################
10206 11:13:53.966515
10207 11:13:54.257874 01c80000 ################################################################
10208 11:13:54.258018
10209 11:13:54.545762 01d00000 ################################################################
10210 11:13:54.545897
10211 11:13:54.826106 01d80000 ################################################################
10212 11:13:54.826249
10213 11:13:55.120483 01e00000 ################################################################
10214 11:13:55.120622
10215 11:13:55.398965 01e80000 ################################################################
10216 11:13:55.399107
10217 11:13:55.692700 01f00000 ################################################################
10218 11:13:55.692875
10219 11:13:55.979950 01f80000 ################################################################
10220 11:13:55.980091
10221 11:13:56.273373 02000000 ################################################################
10222 11:13:56.273515
10223 11:13:56.567259 02080000 ################################################################
10224 11:13:56.567397
10225 11:13:56.846213 02100000 ################################################################
10226 11:13:56.846347
10227 11:13:57.093564 02180000 ################################################################
10228 11:13:57.093704
10229 11:13:57.341738 02200000 ################################################################
10230 11:13:57.341868
10231 11:13:57.589976 02280000 ################################################################
10232 11:13:57.590110
10233 11:13:57.845981 02300000 ################################################################
10234 11:13:57.846117
10235 11:13:58.138472 02380000 ################################################################
10236 11:13:58.138610
10237 11:13:58.424205 02400000 ################################################################
10238 11:13:58.424348
10239 11:13:58.715374 02480000 ################################################################
10240 11:13:58.715512
10241 11:13:59.009065 02500000 ################################################################
10242 11:13:59.009201
10243 11:13:59.269480 02580000 ################################################################
10244 11:13:59.269617
10245 11:13:59.562733 02600000 ################################################################
10246 11:13:59.562874
10247 11:13:59.856371 02680000 ################################################################
10248 11:13:59.856508
10249 11:14:00.144108 02700000 ################################################################
10250 11:14:00.144243
10251 11:14:00.437612 02780000 ################################################################
10252 11:14:00.437750
10253 11:14:00.728004 02800000 ################################################################
10254 11:14:00.728143
10255 11:14:01.021727 02880000 ################################################################
10256 11:14:01.021906
10257 11:14:01.317365 02900000 ################################################################
10258 11:14:01.317504
10259 11:14:01.612843 02980000 ################################################################
10260 11:14:01.612975
10261 11:14:01.901770 02a00000 ################################################################
10262 11:14:01.901906
10263 11:14:02.195986 02a80000 ################################################################
10264 11:14:02.196119
10265 11:14:02.480028 02b00000 ################################################################
10266 11:14:02.480167
10267 11:14:02.743473 02b80000 ################################################################
10268 11:14:02.743612
10269 11:14:02.991779 02c00000 ################################################################
10270 11:14:02.991944
10271 11:14:03.251553 02c80000 ################################################################
10272 11:14:03.251695
10273 11:14:03.519175 02d00000 ################################################################
10274 11:14:03.519309
10275 11:14:03.786407 02d80000 ################################################################
10276 11:14:03.786543
10277 11:14:04.077431 02e00000 ################################################################
10278 11:14:04.077569
10279 11:14:04.369965 02e80000 ################################################################
10280 11:14:04.370104
10281 11:14:04.664368 02f00000 ################################################################
10282 11:14:04.664511
10283 11:14:04.949240 02f80000 ################################################################
10284 11:14:04.949379
10285 11:14:05.245376 03000000 ################################################################
10286 11:14:05.245510
10287 11:14:05.532654 03080000 ################################################################
10288 11:14:05.532839
10289 11:14:05.828263 03100000 ################################################################
10290 11:14:05.828509
10291 11:14:06.115068 03180000 ################################################################
10292 11:14:06.115349
10293 11:14:06.518155 03200000 ################################################################
10294 11:14:06.518712
10295 11:14:06.919724 03280000 ################################################################
10296 11:14:06.920328
10297 11:14:07.261654 03300000 ################################################################
10298 11:14:07.261804
10299 11:14:07.531590 03380000 ################################################################
10300 11:14:07.531721
10301 11:14:07.828008 03400000 ################################################################
10302 11:14:07.828136
10303 11:14:08.124460 03480000 ################################################################
10304 11:14:08.124589
10305 11:14:08.420855 03500000 ################################################################
10306 11:14:08.420980
10307 11:14:08.709275 03580000 ################################################################
10308 11:14:08.709401
10309 11:14:08.973856 03600000 ################################################################
10310 11:14:08.974010
10311 11:14:09.251982 03680000 ################################################################
10312 11:14:09.252126
10313 11:14:09.510714 03700000 ################################################################
10314 11:14:09.510858
10315 11:14:09.787300 03780000 ################################################################
10316 11:14:09.787453
10317 11:14:10.072898 03800000 ################################################################
10318 11:14:10.073049
10319 11:14:10.364922 03880000 ################################################################
10320 11:14:10.365069
10321 11:14:10.653905 03900000 ################################################################
10322 11:14:10.654053
10323 11:14:10.914490 03980000 ################################################################
10324 11:14:10.914632
10325 11:14:11.175742 03a00000 ################################################################
10326 11:14:11.175889
10327 11:14:11.465551 03a80000 ################################################################
10328 11:14:11.465694
10329 11:14:11.750005 03b00000 ################################################################
10330 11:14:11.750144
10331 11:14:12.045590 03b80000 ################################################################
10332 11:14:12.045729
10333 11:14:12.328224 03c00000 ################################################################
10334 11:14:12.328357
10335 11:14:12.620342 03c80000 ################################################################
10336 11:14:12.620471
10337 11:14:12.903314 03d00000 ################################################################
10338 11:14:12.903491
10339 11:14:13.193245 03d80000 ################################################################
10340 11:14:13.193445
10341 11:14:13.461068 03e00000 ################################################################
10342 11:14:13.461212
10343 11:14:13.715100 03e80000 ################################################################
10344 11:14:13.715243
10345 11:14:13.964327 03f00000 ################################################################
10346 11:14:13.964467
10347 11:14:14.214212 03f80000 ################################################################
10348 11:14:14.214334
10349 11:14:14.464353 04000000 ################################################################
10350 11:14:14.464495
10351 11:14:14.714253 04080000 ################################################################
10352 11:14:14.714387
10353 11:14:14.964419 04100000 ################################################################
10354 11:14:14.964547
10355 11:14:15.214654 04180000 ################################################################
10356 11:14:15.214778
10357 11:14:15.464172 04200000 ################################################################
10358 11:14:15.464307
10359 11:14:15.715424 04280000 ################################################################
10360 11:14:15.715585
10361 11:14:15.977316 04300000 ################################################################
10362 11:14:15.977472
10363 11:14:16.264639 04380000 ################################################################
10364 11:14:16.264821
10365 11:14:16.558209 04400000 ################################################################
10366 11:14:16.558355
10367 11:14:16.848082 04480000 ################################################################
10368 11:14:16.848226
10369 11:14:17.145003 04500000 ################################################################
10370 11:14:17.145150
10371 11:14:17.439571 04580000 ################################################################
10372 11:14:17.439719
10373 11:14:17.729140 04600000 ################################################################
10374 11:14:17.729270
10375 11:14:18.026041 04680000 ################################################################
10376 11:14:18.026172
10377 11:14:18.319472 04700000 ################################################################
10378 11:14:18.319600
10379 11:14:18.612610 04780000 ################################################################
10380 11:14:18.612775
10381 11:14:18.909103 04800000 ################################################################
10382 11:14:18.909231
10383 11:14:19.206399 04880000 ################################################################
10384 11:14:19.206541
10385 11:14:19.492871 04900000 ################################################################
10386 11:14:19.493018
10387 11:14:19.790387 04980000 ################################################################
10388 11:14:19.790541
10389 11:14:20.085513 04a00000 ################################################################
10390 11:14:20.085651
10391 11:14:20.380309 04a80000 ################################################################
10392 11:14:20.380441
10393 11:14:20.639474 04b00000 ################################################################
10394 11:14:20.639599
10395 11:14:20.900706 04b80000 ################################################################
10396 11:14:20.900837
10397 11:14:21.170263 04c00000 ################################################################
10398 11:14:21.170412
10399 11:14:21.439372 04c80000 ################################################################
10400 11:14:21.439525
10401 11:14:21.698448 04d00000 ################################################################
10402 11:14:21.698576
10403 11:14:21.986353 04d80000 ################################################################
10404 11:14:21.986486
10405 11:14:22.282203 04e00000 ################################################################
10406 11:14:22.282336
10407 11:14:22.577028 04e80000 ################################################################
10408 11:14:22.577157
10409 11:14:22.861511 04f00000 ################################################################
10410 11:14:22.861639
10411 11:14:23.157812 04f80000 ################################################################
10412 11:14:23.157960
10413 11:14:23.451408 05000000 ################################################################
10414 11:14:23.451538
10415 11:14:23.747625 05080000 ################################################################
10416 11:14:23.747751
10417 11:14:24.041320 05100000 ################################################################
10418 11:14:24.041452
10419 11:14:24.324192 05180000 ################################################################
10420 11:14:24.324343
10421 11:14:24.599868 05200000 ################################################################
10422 11:14:24.600009
10423 11:14:24.895548 05280000 ################################################################
10424 11:14:24.895689
10425 11:14:25.201529 05300000 ################################################################
10426 11:14:25.201670
10427 11:14:25.495226 05380000 ################################################################
10428 11:14:25.495359
10429 11:14:25.796064 05400000 ################################################################
10430 11:14:25.796191
10431 11:14:26.092883 05480000 ################################################################
10432 11:14:26.093028
10433 11:14:26.371760 05500000 ################################################################
10434 11:14:26.371904
10435 11:14:26.629337 05580000 ################################################################
10436 11:14:26.629462
10437 11:14:26.898773 05600000 ################################################################
10438 11:14:26.898903
10439 11:14:27.192154 05680000 ################################################################
10440 11:14:27.192288
10441 11:14:27.461708 05700000 ################################################################
10442 11:14:27.461838
10443 11:14:27.754268 05780000 ################################################################
10444 11:14:27.754400
10445 11:14:28.041644 05800000 ################################################################
10446 11:14:28.041771
10447 11:14:28.338400 05880000 ################################################################
10448 11:14:28.338528
10449 11:14:28.611217 05900000 ################################################################
10450 11:14:28.611347
10451 11:14:28.893378 05980000 ################################################################
10452 11:14:28.893503
10453 11:14:29.172606 05a00000 ################################################################
10454 11:14:29.172771
10455 11:14:29.468981 05a80000 ################################################################
10456 11:14:29.469107
10457 11:14:29.766285 05b00000 ################################################################
10458 11:14:29.766410
10459 11:14:30.064809 05b80000 ################################################################
10460 11:14:30.064968
10461 11:14:30.361489 05c00000 ################################################################
10462 11:14:30.361644
10463 11:14:30.649024 05c80000 ################################################################
10464 11:14:30.649225
10465 11:14:30.925620 05d00000 ################################################################
10466 11:14:30.925772
10467 11:14:31.199172 05d80000 ################################################################
10468 11:14:31.199313
10469 11:14:31.453015 05e00000 ################################################################
10470 11:14:31.453137
10471 11:14:31.704145 05e80000 ################################################################
10472 11:14:31.704286
10473 11:14:31.961354 05f00000 ################################################################
10474 11:14:31.961492
10475 11:14:32.223319 05f80000 ################################################################
10476 11:14:32.223441
10477 11:14:32.499582 06000000 ################################################################
10478 11:14:32.499727
10479 11:14:32.786697 06080000 ################################################################
10480 11:14:32.786837
10481 11:14:33.061466 06100000 ################################################################
10482 11:14:33.061607
10483 11:14:33.350954 06180000 ################################################################
10484 11:14:33.351091
10485 11:14:33.633381 06200000 ################################################################
10486 11:14:33.633511
10487 11:14:33.927510 06280000 ################################################################
10488 11:14:33.927657
10489 11:14:34.224986 06300000 ################################################################
10490 11:14:34.225154
10491 11:14:34.522561 06380000 ################################################################
10492 11:14:34.522688
10493 11:14:34.820257 06400000 ################################################################
10494 11:14:34.820393
10495 11:14:35.113474 06480000 ################################################################
10496 11:14:35.113608
10497 11:14:35.501909 06500000 ################################################################
10498 11:14:35.502545
10499 11:14:35.902157 06580000 ################################################################
10500 11:14:35.902654
10501 11:14:36.316544 06600000 ################################################################
10502 11:14:36.317134
10503 11:14:36.763283 06680000 ################################################################
10504 11:14:36.763791
10505 11:14:36.988291 06700000 #################################### done.
10506 11:14:36.988810
10507 11:14:36.991692 The bootfile was 108296578 bytes long.
10508 11:14:36.992256
10509 11:14:36.995152 Sending tftp read request... done.
10510 11:14:36.995640
10511 11:14:36.996012 Waiting for the transfer...
10512 11:14:36.996362
10513 11:14:36.998965 00000000 # done.
10514 11:14:36.999540
10515 11:14:37.005330 Command line loaded dynamically from TFTP file: 10591211/tftp-deploy-c4dhww01/kernel/cmdline
10516 11:14:37.005901
10517 11:14:37.018357 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10518 11:14:37.018934
10519 11:14:37.019305 Loading FIT.
10520 11:14:37.019650
10521 11:14:37.021421 Image ramdisk-1 has 98161597 bytes.
10522 11:14:37.021890
10523 11:14:37.025371 Image fdt-1 has 46924 bytes.
10524 11:14:37.025939
10525 11:14:37.028254 Image kernel-1 has 10086024 bytes.
10526 11:14:37.028724
10527 11:14:37.035012 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10528 11:14:37.037851
10529 11:14:37.054607 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10530 11:14:37.055192
10531 11:14:37.057668 Choosing best match conf-1 for compat google,spherion-rev2.
10532 11:14:37.063686
10533 11:14:37.068258 Connected to device vid:did:rid of 1ae0:0028:00
10534 11:14:37.075011
10535 11:14:37.079053 tpm_get_response: command 0x17b, return code 0x0
10536 11:14:37.079625
10537 11:14:37.081390 ec_init: CrosEC protocol v3 supported (256, 248)
10538 11:14:37.085580
10539 11:14:37.088896 tpm_cleanup: add release locality here.
10540 11:14:37.089363
10541 11:14:37.089729 Shutting down all USB controllers.
10542 11:14:37.092231
10543 11:14:37.092831 Removing current net device
10544 11:14:37.093214
10545 11:14:37.099175 Exiting depthcharge with code 4 at timestamp: 97658170
10546 11:14:37.099743
10547 11:14:37.102262 LZMA decompressing kernel-1 to 0x821a6718
10548 11:14:37.102729
10549 11:14:37.105162 LZMA decompressing kernel-1 to 0x40000000
10550 11:14:38.371996
10551 11:14:38.372559 jumping to kernel
10552 11:14:38.374494 end: 2.2.4 bootloader-commands (duration 00:01:10) [common]
10553 11:14:38.375042 start: 2.2.5 auto-login-action (timeout 00:03:16) [common]
10554 11:14:38.375451 Setting prompt string to ['Linux version [0-9]']
10555 11:14:38.375875 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10556 11:14:38.376253 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10557 11:14:38.454655
10558 11:14:38.457773 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10559 11:14:38.461736 start: 2.2.5.1 login-action (timeout 00:03:16) [common]
10560 11:14:38.462358 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10561 11:14:38.462872 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10562 11:14:38.463274 Using line separator: #'\n'#
10563 11:14:38.463617 No login prompt set.
10564 11:14:38.464139 Parsing kernel messages
10565 11:14:38.464525 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10566 11:14:38.465227 [login-action] Waiting for messages, (timeout 00:03:15)
10567 11:14:38.480879 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10568 11:14:38.484109 [ 0.000000] random: crng init done
10569 11:14:38.491227 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10570 11:14:38.493975 [ 0.000000] efi: UEFI not found.
10571 11:14:38.500705 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10572 11:14:38.507152 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10573 11:14:38.517669 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10574 11:14:38.527547 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10575 11:14:38.534245 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10576 11:14:38.540542 [ 0.000000] printk: bootconsole [mtk8250] enabled
10577 11:14:38.546761 [ 0.000000] NUMA: No NUMA configuration found
10578 11:14:38.553362 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10579 11:14:38.556922 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10580 11:14:38.559939 [ 0.000000] Zone ranges:
10581 11:14:38.566823 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10582 11:14:38.569753 [ 0.000000] DMA32 empty
10583 11:14:38.576720 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10584 11:14:38.579821 [ 0.000000] Movable zone start for each node
10585 11:14:38.583359 [ 0.000000] Early memory node ranges
10586 11:14:38.589471 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10587 11:14:38.596248 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10588 11:14:38.602744 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10589 11:14:38.609433 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10590 11:14:38.616287 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10591 11:14:38.622909 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10592 11:14:38.678590 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10593 11:14:38.685080 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10594 11:14:38.692224 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10595 11:14:38.694993 [ 0.000000] psci: probing for conduit method from DT.
10596 11:14:38.701709 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10597 11:14:38.705116 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10598 11:14:38.711701 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10599 11:14:38.714748 [ 0.000000] psci: SMC Calling Convention v1.2
10600 11:14:38.721794 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10601 11:14:38.725673 [ 0.000000] Detected VIPT I-cache on CPU0
10602 11:14:38.731728 [ 0.000000] CPU features: detected: GIC system register CPU interface
10603 11:14:38.738444 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10604 11:14:38.744895 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10605 11:14:38.751840 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10606 11:14:38.757944 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10607 11:14:38.767852 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10608 11:14:38.771430 [ 0.000000] alternatives: applying boot alternatives
10609 11:14:38.777754 [ 0.000000] Fallback order for Node 0: 0
10610 11:14:38.784433 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10611 11:14:38.787451 [ 0.000000] Policy zone: Normal
10612 11:14:38.797490 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10613 11:14:38.810510 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10614 11:14:38.820864 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10615 11:14:38.830631 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10616 11:14:38.837260 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10617 11:14:38.840536 <6>[ 0.000000] software IO TLB: area num 8.
10618 11:14:38.895832 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10619 11:14:39.045204 <6>[ 0.000000] Memory: 7877080K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 475688K reserved, 32768K cma-reserved)
10620 11:14:39.051613 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10621 11:14:39.058273 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10622 11:14:39.061538 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10623 11:14:39.067958 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10624 11:14:39.074799 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10625 11:14:39.077875 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10626 11:14:39.088220 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10627 11:14:39.094935 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10628 11:14:39.101196 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10629 11:14:39.108594 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10630 11:14:39.111166 <6>[ 0.000000] GICv3: 608 SPIs implemented
10631 11:14:39.114280 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10632 11:14:39.120849 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10633 11:14:39.124840 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10634 11:14:39.131149 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10635 11:14:39.144287 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10636 11:14:39.157415 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10637 11:14:39.164659 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10638 11:14:39.171946 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10639 11:14:39.184707 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10640 11:14:39.191527 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10641 11:14:39.197935 <6>[ 0.009182] Console: colour dummy device 80x25
10642 11:14:39.208212 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10643 11:14:39.214668 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10644 11:14:39.217994 <6>[ 0.029225] LSM: Security Framework initializing
10645 11:14:39.224568 <6>[ 0.034194] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10646 11:14:39.234290 <6>[ 0.042053] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10647 11:14:39.244507 <6>[ 0.051481] cblist_init_generic: Setting adjustable number of callback queues.
10648 11:14:39.247458 <6>[ 0.058935] cblist_init_generic: Setting shift to 3 and lim to 1.
10649 11:14:39.254031 <6>[ 0.065273] cblist_init_generic: Setting shift to 3 and lim to 1.
10650 11:14:39.260993 <6>[ 0.071719] rcu: Hierarchical SRCU implementation.
10651 11:14:39.267634 <6>[ 0.076763] rcu: Max phase no-delay instances is 1000.
10652 11:14:39.274362 <6>[ 0.083786] EFI services will not be available.
10653 11:14:39.277068 <6>[ 0.088759] smp: Bringing up secondary CPUs ...
10654 11:14:39.284860 <6>[ 0.093844] Detected VIPT I-cache on CPU1
10655 11:14:39.291413 <6>[ 0.093916] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10656 11:14:39.298427 <6>[ 0.093947] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10657 11:14:39.301561 <6>[ 0.094283] Detected VIPT I-cache on CPU2
10658 11:14:39.311507 <6>[ 0.094334] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10659 11:14:39.318067 <6>[ 0.094350] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10660 11:14:39.321510 <6>[ 0.094609] Detected VIPT I-cache on CPU3
10661 11:14:39.327974 <6>[ 0.094656] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10662 11:14:39.335128 <6>[ 0.094669] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10663 11:14:39.340874 <6>[ 0.094959] CPU features: detected: Spectre-v4
10664 11:14:39.344046 <6>[ 0.094964] CPU features: detected: Spectre-BHB
10665 11:14:39.347301 <6>[ 0.094969] Detected PIPT I-cache on CPU4
10666 11:14:39.354245 <6>[ 0.095020] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10667 11:14:39.364438 <6>[ 0.095035] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10668 11:14:39.367261 <6>[ 0.095325] Detected PIPT I-cache on CPU5
10669 11:14:39.373648 <6>[ 0.095388] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10670 11:14:39.380318 <6>[ 0.095404] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10671 11:14:39.383668 <6>[ 0.095687] Detected PIPT I-cache on CPU6
10672 11:14:39.393981 <6>[ 0.095752] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10673 11:14:39.400393 <6>[ 0.095768] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10674 11:14:39.403682 <6>[ 0.096070] Detected PIPT I-cache on CPU7
10675 11:14:39.410501 <6>[ 0.096133] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10676 11:14:39.416580 <6>[ 0.096150] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10677 11:14:39.420419 <6>[ 0.096196] smp: Brought up 1 node, 8 CPUs
10678 11:14:39.426363 <6>[ 0.237553] SMP: Total of 8 processors activated.
10679 11:14:39.433245 <6>[ 0.242505] CPU features: detected: 32-bit EL0 Support
10680 11:14:39.439398 <6>[ 0.247901] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10681 11:14:39.446293 <6>[ 0.256701] CPU features: detected: Common not Private translations
10682 11:14:39.452973 <6>[ 0.263217] CPU features: detected: CRC32 instructions
10683 11:14:39.459680 <6>[ 0.268568] CPU features: detected: RCpc load-acquire (LDAPR)
10684 11:14:39.462707 <6>[ 0.274528] CPU features: detected: LSE atomic instructions
10685 11:14:39.470033 <6>[ 0.280309] CPU features: detected: Privileged Access Never
10686 11:14:39.475807 <6>[ 0.286088] CPU features: detected: RAS Extension Support
10687 11:14:39.482808 <6>[ 0.291732] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10688 11:14:39.486263 <6>[ 0.298950] CPU: All CPU(s) started at EL2
10689 11:14:39.492679 <6>[ 0.303292] alternatives: applying system-wide alternatives
10690 11:14:39.502504 <6>[ 0.313994] devtmpfs: initialized
10691 11:14:39.518477 <6>[ 0.322768] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10692 11:14:39.525234 <6>[ 0.332727] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10693 11:14:39.531862 <6>[ 0.340947] pinctrl core: initialized pinctrl subsystem
10694 11:14:39.534690 <6>[ 0.347592] DMI not present or invalid.
10695 11:14:39.541204 <6>[ 0.351998] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10696 11:14:39.551367 <6>[ 0.358865] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10697 11:14:39.557932 <6>[ 0.366439] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10698 11:14:39.567811 <6>[ 0.374663] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10699 11:14:39.571033 <6>[ 0.382899] audit: initializing netlink subsys (disabled)
10700 11:14:39.580870 <5>[ 0.388593] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10701 11:14:39.587875 <6>[ 0.389295] thermal_sys: Registered thermal governor 'step_wise'
10702 11:14:39.594238 <6>[ 0.396559] thermal_sys: Registered thermal governor 'power_allocator'
10703 11:14:39.597402 <6>[ 0.402814] cpuidle: using governor menu
10704 11:14:39.604134 <6>[ 0.413772] NET: Registered PF_QIPCRTR protocol family
10705 11:14:39.611114 <6>[ 0.419249] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10706 11:14:39.617632 <6>[ 0.426349] ASID allocator initialised with 32768 entries
10707 11:14:39.620439 <6>[ 0.432912] Serial: AMBA PL011 UART driver
10708 11:14:39.630262 <4>[ 0.441591] Trying to register duplicate clock ID: 134
10709 11:14:39.684501 <6>[ 0.498809] KASLR enabled
10710 11:14:39.698270 <6>[ 0.506502] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10711 11:14:39.705516 <6>[ 0.513517] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10712 11:14:39.712309 <6>[ 0.520004] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10713 11:14:39.718671 <6>[ 0.527009] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10714 11:14:39.725150 <6>[ 0.533496] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10715 11:14:39.731470 <6>[ 0.540500] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10716 11:14:39.738471 <6>[ 0.546987] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10717 11:14:39.744558 <6>[ 0.553991] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10718 11:14:39.747952 <6>[ 0.561461] ACPI: Interpreter disabled.
10719 11:14:39.756615 <6>[ 0.567881] iommu: Default domain type: Translated
10720 11:14:39.763112 <6>[ 0.572993] iommu: DMA domain TLB invalidation policy: strict mode
10721 11:14:39.766988 <5>[ 0.579651] SCSI subsystem initialized
10722 11:14:39.773097 <6>[ 0.583887] usbcore: registered new interface driver usbfs
10723 11:14:39.779932 <6>[ 0.589620] usbcore: registered new interface driver hub
10724 11:14:39.782765 <6>[ 0.595173] usbcore: registered new device driver usb
10725 11:14:39.790107 <6>[ 0.601273] pps_core: LinuxPPS API ver. 1 registered
10726 11:14:39.800052 <6>[ 0.606466] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10727 11:14:39.803160 <6>[ 0.615807] PTP clock support registered
10728 11:14:39.806892 <6>[ 0.620043] EDAC MC: Ver: 3.0.0
10729 11:14:39.814316 <6>[ 0.625221] FPGA manager framework
10730 11:14:39.821088 <6>[ 0.628898] Advanced Linux Sound Architecture Driver Initialized.
10731 11:14:39.824278 <6>[ 0.635662] vgaarb: loaded
10732 11:14:39.830468 <6>[ 0.638816] clocksource: Switched to clocksource arch_sys_counter
10733 11:14:39.833771 <5>[ 0.645264] VFS: Disk quotas dquot_6.6.0
10734 11:14:39.840570 <6>[ 0.649447] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10735 11:14:39.843648 <6>[ 0.656640] pnp: PnP ACPI: disabled
10736 11:14:39.852123 <6>[ 0.663294] NET: Registered PF_INET protocol family
10737 11:14:39.862073 <6>[ 0.668879] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10738 11:14:39.873727 <6>[ 0.681195] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10739 11:14:39.883126 <6>[ 0.690012] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10740 11:14:39.889578 <6>[ 0.697979] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10741 11:14:39.899362 <6>[ 0.706677] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10742 11:14:39.906295 <6>[ 0.716385] TCP: Hash tables configured (established 65536 bind 65536)
10743 11:14:39.912540 <6>[ 0.723245] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10744 11:14:39.922538 <6>[ 0.730439] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10745 11:14:39.929121 <6>[ 0.738142] NET: Registered PF_UNIX/PF_LOCAL protocol family
10746 11:14:39.935885 <6>[ 0.744304] RPC: Registered named UNIX socket transport module.
10747 11:14:39.939183 <6>[ 0.750456] RPC: Registered udp transport module.
10748 11:14:39.945630 <6>[ 0.755389] RPC: Registered tcp transport module.
10749 11:14:39.952201 <6>[ 0.760321] RPC: Registered tcp NFSv4.1 backchannel transport module.
10750 11:14:39.955581 <6>[ 0.766989] PCI: CLS 0 bytes, default 64
10751 11:14:39.958876 <6>[ 0.771369] Unpacking initramfs...
10752 11:14:39.975545 <6>[ 0.783387] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10753 11:14:39.985301 <6>[ 0.792041] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10754 11:14:39.988501 <6>[ 0.800880] kvm [1]: IPA Size Limit: 40 bits
10755 11:14:39.995413 <6>[ 0.805411] kvm [1]: GICv3: no GICV resource entry
10756 11:14:39.998867 <6>[ 0.810432] kvm [1]: disabling GICv2 emulation
10757 11:14:40.005140 <6>[ 0.815116] kvm [1]: GIC system register CPU interface enabled
10758 11:14:40.008733 <6>[ 0.821281] kvm [1]: vgic interrupt IRQ18
10759 11:14:40.015745 <6>[ 0.826999] kvm [1]: VHE mode initialized successfully
10760 11:14:40.022381 <5>[ 0.833346] Initialise system trusted keyrings
10761 11:14:40.028879 <6>[ 0.838178] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10762 11:14:40.037319 <6>[ 0.848176] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10763 11:14:40.044098 <5>[ 0.854567] NFS: Registering the id_resolver key type
10764 11:14:40.047050 <5>[ 0.859868] Key type id_resolver registered
10765 11:14:40.053913 <5>[ 0.864282] Key type id_legacy registered
10766 11:14:40.060291 <6>[ 0.868575] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10767 11:14:40.066928 <6>[ 0.875498] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10768 11:14:40.073339 <6>[ 0.883238] 9p: Installing v9fs 9p2000 file system support
10769 11:14:40.110376 <5>[ 0.921792] Key type asymmetric registered
10770 11:14:40.113739 <5>[ 0.926134] Asymmetric key parser 'x509' registered
10771 11:14:40.123866 <6>[ 0.931282] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10772 11:14:40.126929 <6>[ 0.938899] io scheduler mq-deadline registered
10773 11:14:40.130649 <6>[ 0.943675] io scheduler kyber registered
10774 11:14:40.149197 <6>[ 0.960627] EINJ: ACPI disabled.
10775 11:14:40.181546 <4>[ 0.986356] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10776 11:14:40.191722 <4>[ 0.996994] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10777 11:14:40.206040 <6>[ 1.017637] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10778 11:14:40.214576 <6>[ 1.025724] printk: console [ttyS0] disabled
10779 11:14:40.242587 <6>[ 1.050386] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10780 11:14:40.249609 <6>[ 1.059862] printk: console [ttyS0] enabled
10781 11:14:40.252429 <6>[ 1.059862] printk: console [ttyS0] enabled
10782 11:14:40.259145 <6>[ 1.068757] printk: bootconsole [mtk8250] disabled
10783 11:14:40.262008 <6>[ 1.068757] printk: bootconsole [mtk8250] disabled
10784 11:14:40.268881 <6>[ 1.080017] SuperH (H)SCI(F) driver initialized
10785 11:14:40.272174 <6>[ 1.085276] msm_serial: driver initialized
10786 11:14:40.286105 <6>[ 1.094181] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10787 11:14:40.296147 <6>[ 1.102729] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10788 11:14:40.302570 <6>[ 1.111270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10789 11:14:40.312425 <6>[ 1.119899] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10790 11:14:40.323444 <6>[ 1.128605] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10791 11:14:40.329449 <6>[ 1.137316] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10792 11:14:40.339255 <6>[ 1.145858] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10793 11:14:40.345900 <6>[ 1.154664] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10794 11:14:40.356170 <6>[ 1.163207] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10795 11:14:40.367926 <6>[ 1.178664] loop: module loaded
10796 11:14:40.374161 <6>[ 1.184651] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10797 11:14:40.397276 <4>[ 1.207933] mtk-pmic-keys: Failed to locate of_node [id: -1]
10798 11:14:40.403877 <6>[ 1.214659] megasas: 07.719.03.00-rc1
10799 11:14:40.413547 <6>[ 1.224147] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10800 11:14:40.423044 <6>[ 1.234200] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10801 11:14:40.439570 <6>[ 1.250857] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10802 11:14:40.500672 <6>[ 1.304827] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10803 11:14:43.960924 <6>[ 4.772607] Freeing initrd memory: 95856K
10804 11:14:43.971046 <6>[ 4.782960] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10805 11:14:43.982155 <6>[ 4.793822] tun: Universal TUN/TAP device driver, 1.6
10806 11:14:43.985358 <6>[ 4.799878] thunder_xcv, ver 1.0
10807 11:14:43.988630 <6>[ 4.803383] thunder_bgx, ver 1.0
10808 11:14:43.992278 <6>[ 4.806876] nicpf, ver 1.0
10809 11:14:44.002191 <6>[ 4.810879] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10810 11:14:44.005445 <6>[ 4.818353] hns3: Copyright (c) 2017 Huawei Corporation.
10811 11:14:44.012440 <6>[ 4.823940] hclge is initializing
10812 11:14:44.015926 <6>[ 4.827520] e1000: Intel(R) PRO/1000 Network Driver
10813 11:14:44.022511 <6>[ 4.832649] e1000: Copyright (c) 1999-2006 Intel Corporation.
10814 11:14:44.025488 <6>[ 4.838660] e1000e: Intel(R) PRO/1000 Network Driver
10815 11:14:44.032546 <6>[ 4.843876] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10816 11:14:44.039220 <6>[ 4.850062] igb: Intel(R) Gigabit Ethernet Network Driver
10817 11:14:44.045652 <6>[ 4.855712] igb: Copyright (c) 2007-2014 Intel Corporation.
10818 11:14:44.052365 <6>[ 4.861548] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10819 11:14:44.059048 <6>[ 4.868066] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10820 11:14:44.061823 <6>[ 4.874524] sky2: driver version 1.30
10821 11:14:44.068493 <6>[ 4.879510] VFIO - User Level meta-driver version: 0.3
10822 11:14:44.076142 <6>[ 4.887655] usbcore: registered new interface driver usb-storage
10823 11:14:44.082768 <6>[ 4.894093] usbcore: registered new device driver onboard-usb-hub
10824 11:14:44.091431 <6>[ 4.903119] mt6397-rtc mt6359-rtc: registered as rtc0
10825 11:14:44.101458 <6>[ 4.908583] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:14:41 UTC (1685963681)
10826 11:14:44.104516 <6>[ 4.918139] i2c_dev: i2c /dev entries driver
10827 11:14:44.121129 <6>[ 4.929798] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10828 11:14:44.128056 <6>[ 4.939967] sdhci: Secure Digital Host Controller Interface driver
10829 11:14:44.134845 <6>[ 4.946405] sdhci: Copyright(c) Pierre Ossman
10830 11:14:44.141392 <6>[ 4.951799] Synopsys Designware Multimedia Card Interface Driver
10831 11:14:44.145009 <6>[ 4.958369] mmc0: CQHCI version 5.10
10832 11:14:44.151664 <6>[ 4.958950] sdhci-pltfm: SDHCI platform and OF driver helper
10833 11:14:44.158734 <6>[ 4.970217] ledtrig-cpu: registered to indicate activity on CPUs
10834 11:14:44.169358 <6>[ 4.977524] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10835 11:14:44.175807 <6>[ 4.984903] usbcore: registered new interface driver usbhid
10836 11:14:44.178951 <6>[ 4.990729] usbhid: USB HID core driver
10837 11:14:44.186183 <6>[ 4.994974] spi_master spi0: will run message pump with realtime priority
10838 11:14:44.230891 <6>[ 5.036251] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10839 11:14:44.250695 <6>[ 5.051950] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10840 11:14:44.254239 <6>[ 5.065518] mmc0: Command Queue Engine enabled
10841 11:14:44.260554 <6>[ 5.067020] cros-ec-spi spi0.0: Chrome EC device registered
10842 11:14:44.267058 <6>[ 5.070271] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10843 11:14:44.270200 <6>[ 5.083419] mmcblk0: mmc0:0001 DA4128 116 GiB
10844 11:14:44.285366 <6>[ 5.093448] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10845 11:14:44.291735 <6>[ 5.095580] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10846 11:14:44.298669 <6>[ 5.104901] NET: Registered PF_PACKET protocol family
10847 11:14:44.301483 <6>[ 5.110070] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10848 11:14:44.308122 <6>[ 5.114129] 9pnet: Installing 9P2000 support
10849 11:14:44.311486 <6>[ 5.119875] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10850 11:14:44.318156 <5>[ 5.123792] Key type dns_resolver registered
10851 11:14:44.324844 <6>[ 5.129564] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10852 11:14:44.328050 <6>[ 5.134112] registered taskstats version 1
10853 11:14:44.331231 <5>[ 5.144411] Loading compiled-in X.509 certificates
10854 11:14:44.367751 <4>[ 5.172724] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10855 11:14:44.377361 <4>[ 5.183407] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10856 11:14:44.387914 <3>[ 5.196191] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10857 11:14:44.399906 <6>[ 5.211538] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10858 11:14:44.406503 <6>[ 5.218345] xhci-mtk 11200000.usb: xHCI Host Controller
10859 11:14:44.413305 <6>[ 5.223884] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10860 11:14:44.423292 <6>[ 5.231750] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10861 11:14:44.429931 <6>[ 5.241193] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10862 11:14:44.436600 <6>[ 5.247291] xhci-mtk 11200000.usb: xHCI Host Controller
10863 11:14:44.443175 <6>[ 5.252921] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10864 11:14:44.449502 <6>[ 5.260590] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10865 11:14:44.456652 <6>[ 5.268488] hub 1-0:1.0: USB hub found
10866 11:14:44.459902 <6>[ 5.272522] hub 1-0:1.0: 1 port detected
10867 11:14:44.469742 <6>[ 5.276867] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10868 11:14:44.473101 <6>[ 5.285667] hub 2-0:1.0: USB hub found
10869 11:14:44.476455 <6>[ 5.289701] hub 2-0:1.0: 1 port detected
10870 11:14:44.485200 <6>[ 5.296915] mtk-msdc 11f70000.mmc: Got CD GPIO
10871 11:14:44.503359 <6>[ 5.311527] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10872 11:14:44.509614 <6>[ 5.319567] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10873 11:14:44.519864 <4>[ 5.327530] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10874 11:14:44.529378 <6>[ 5.337185] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10875 11:14:44.536247 <6>[ 5.345265] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10876 11:14:44.546320 <6>[ 5.353291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10877 11:14:44.552643 <6>[ 5.361209] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10878 11:14:44.559642 <6>[ 5.369030] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10879 11:14:44.569174 <6>[ 5.376859] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10880 11:14:44.579121 <6>[ 5.387643] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10881 11:14:44.588991 <6>[ 5.396016] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10882 11:14:44.595674 <6>[ 5.404361] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10883 11:14:44.605661 <6>[ 5.412704] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10884 11:14:44.611979 <6>[ 5.421047] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10885 11:14:44.622216 <6>[ 5.429390] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10886 11:14:44.628628 <6>[ 5.437733] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10887 11:14:44.638756 <6>[ 5.446077] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10888 11:14:44.645535 <6>[ 5.454423] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10889 11:14:44.655061 <6>[ 5.462767] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10890 11:14:44.661974 <6>[ 5.471114] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10891 11:14:44.671792 <6>[ 5.479458] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10892 11:14:44.678350 <6>[ 5.487801] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10893 11:14:44.688420 <6>[ 5.496148] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10894 11:14:44.694949 <6>[ 5.504495] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10895 11:14:44.701552 <6>[ 5.513494] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10896 11:14:44.709103 <6>[ 5.521025] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10897 11:14:44.716445 <6>[ 5.528185] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10898 11:14:44.726970 <6>[ 5.535378] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10899 11:14:44.733602 <6>[ 5.542730] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10900 11:14:44.743560 <6>[ 5.549684] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10901 11:14:44.750480 <6>[ 5.558838] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10902 11:14:44.760023 <6>[ 5.567966] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10903 11:14:44.769758 <6>[ 5.577267] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10904 11:14:44.779488 <6>[ 5.586742] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10905 11:14:44.789591 <6>[ 5.596215] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10906 11:14:44.799618 <6>[ 5.605345] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10907 11:14:44.806106 <6>[ 5.614821] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10908 11:14:44.816509 <6>[ 5.623948] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10909 11:14:44.825900 <6>[ 5.633265] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10910 11:14:44.836121 <6>[ 5.643430] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10911 11:14:44.846767 <6>[ 5.655185] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10912 11:14:44.866594 <6>[ 5.675252] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10913 11:14:44.895872 <6>[ 5.707294] hub 2-1:1.0: USB hub found
10914 11:14:44.898746 <6>[ 5.711789] hub 2-1:1.0: 3 ports detected
10915 11:14:45.018447 <6>[ 5.827062] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10916 11:14:45.171723 <6>[ 5.983409] hub 1-1:1.0: USB hub found
10917 11:14:45.174588 <6>[ 5.987762] hub 1-1:1.0: 4 ports detected
10918 11:14:45.250818 <6>[ 6.059334] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10919 11:14:45.494624 <6>[ 6.303090] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10920 11:14:45.626876 <6>[ 6.438648] hub 1-1.4:1.0: USB hub found
10921 11:14:45.630598 <6>[ 6.443307] hub 1-1.4:1.0: 2 ports detected
10922 11:14:45.926324 <6>[ 6.735090] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10923 11:14:46.118237 <6>[ 6.927088] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10924 11:14:57.146969 <6>[ 17.963636] ALSA device list:
10925 11:14:57.153471 <6>[ 17.966892] No soundcards found.
10926 11:14:57.166151 <6>[ 17.979326] Freeing unused kernel memory: 8384K
10927 11:14:57.169308 <6>[ 17.984256] Run /init as init process
10928 11:14:57.199897 <6>[ 18.012896] NET: Registered PF_INET6 protocol family
10929 11:14:57.206333 <6>[ 18.019266] Segment Routing with IPv6
10930 11:14:57.209422 <6>[ 18.023213] In-situ OAM (IOAM) with IPv6
10931 11:14:57.244256 <30>[ 18.037735] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10932 11:14:57.247708 <30>[ 18.061553] systemd[1]: Detected architecture arm64.
10933 11:14:57.251633
10934 11:14:57.254343 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10935 11:14:57.254854
10936 11:14:57.269794 <30>[ 18.083167] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10937 11:14:57.415047 <30>[ 18.224774] systemd[1]: Queued start job for default target Graphical Interface.
10938 11:14:57.455342 <30>[ 18.268539] systemd[1]: Created slice system-getty.slice.
10939 11:14:57.461673 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10940 11:14:57.478959 <30>[ 18.291805] systemd[1]: Created slice system-modprobe.slice.
10941 11:14:57.484981 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10942 11:14:57.502872 <30>[ 18.316206] systemd[1]: Created slice system-serial\x2dgetty.slice.
10943 11:14:57.512643 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10944 11:14:57.526183 <30>[ 18.339572] systemd[1]: Created slice User and Session Slice.
10945 11:14:57.532832 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10946 11:14:57.553568 <30>[ 18.363646] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10947 11:14:57.563871 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10948 11:14:57.581228 <30>[ 18.391252] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10949 11:14:57.587779 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10950 11:14:57.608597 <30>[ 18.415173] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10951 11:14:57.615184 <30>[ 18.427202] systemd[1]: Reached target Local Encrypted Volumes.
10952 11:14:57.621357 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10953 11:14:57.638118 <30>[ 18.451203] systemd[1]: Reached target Paths.
10954 11:14:57.641491 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10955 11:14:57.657894 <30>[ 18.471132] systemd[1]: Reached target Remote File Systems.
10956 11:14:57.664762 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10957 11:14:57.682169 <30>[ 18.495370] systemd[1]: Reached target Slices.
10958 11:14:57.688465 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10959 11:14:57.701743 <30>[ 18.515167] systemd[1]: Reached target Swap.
10960 11:14:57.705288 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10961 11:14:57.725726 <30>[ 18.535706] systemd[1]: Listening on initctl Compatibility Named Pipe.
10962 11:14:57.732247 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10963 11:14:57.739067 <30>[ 18.550597] systemd[1]: Listening on Journal Audit Socket.
10964 11:14:57.745302 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10965 11:14:57.758364 <30>[ 18.571423] systemd[1]: Listening on Journal Socket (/dev/log).
10966 11:14:57.764819 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10967 11:14:57.782211 <30>[ 18.595415] systemd[1]: Listening on Journal Socket.
10968 11:14:57.788824 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10969 11:14:57.801962 <30>[ 18.615413] systemd[1]: Listening on udev Control Socket.
10970 11:14:57.808614 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10971 11:14:57.826464 <30>[ 18.639758] systemd[1]: Listening on udev Kernel Socket.
10972 11:14:57.833128 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10973 11:14:57.862348 <30>[ 18.675385] systemd[1]: Mounting Huge Pages File System...
10974 11:14:57.868586 Mounting [0;1;39mHuge Pages File System[0m...
10975 11:14:57.884121 <30>[ 18.697149] systemd[1]: Mounting POSIX Message Queue File System...
10976 11:14:57.890495 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10977 11:14:57.907777 <30>[ 18.721159] systemd[1]: Mounting Kernel Debug File System...
10978 11:14:57.914288 Mounting [0;1;39mKernel Debug File System[0m...
10979 11:14:57.933627 <30>[ 18.743355] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10980 11:14:57.969595 <30>[ 18.779512] systemd[1]: Starting Create list of static device nodes for the current kernel...
10981 11:14:57.976244 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10982 11:14:57.995696 <30>[ 18.809325] systemd[1]: Starting Load Kernel Module configfs...
10983 11:14:58.002260 Starting [0;1;39mLoad Kernel Module configfs[0m...
10984 11:14:58.054108 <30>[ 18.867603] systemd[1]: Starting Load Kernel Module drm...
10985 11:14:58.061247 Starting [0;1;39mLoad Kernel Module drm[0m...
10986 11:14:58.077124 <30>[ 18.887365] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10987 11:14:58.087799 <30>[ 18.900938] systemd[1]: Starting Journal Service...
10988 11:14:58.090834 Starting [0;1;39mJournal Service[0m...
10989 11:14:58.108521 <30>[ 18.921889] systemd[1]: Starting Load Kernel Modules...
10990 11:14:58.115135 Starting [0;1;39mLoad Kernel Modules[0m...
10991 11:14:58.135510 <30>[ 18.945675] systemd[1]: Starting Remount Root and Kernel File Systems...
10992 11:14:58.142261 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10993 11:14:58.156560 <30>[ 18.969768] systemd[1]: Starting Coldplug All udev Devices...
10994 11:14:58.163087 Starting [0;1;39mColdplug All udev Devices[0m...
10995 11:14:58.180632 <30>[ 18.993929] systemd[1]: Mounted Huge Pages File System.
10996 11:14:58.187076 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10997 11:14:58.203098 <30>[ 19.016092] systemd[1]: Started Journal Service.
10998 11:14:58.209179 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10999 11:14:58.223689 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11000 11:14:58.239022 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11001 11:14:58.259073 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11002 11:14:58.276058 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11003 11:14:58.295922 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11004 11:14:58.311086 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11005 11:14:58.331407 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11006 11:14:58.345949 See 'systemctl status systemd-remount-fs.service' for details.
11007 11:14:58.379878 Mounting [0;1;39mKernel Configuration File System[0m...
11008 11:14:58.400447 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11009 11:14:58.418183 <46>[ 19.228075] systemd-journald[177]: Received client request to flush runtime journal.
11010 11:14:58.426820 Starting [0;1;39mLoad/Save Random Seed[0m...
11011 11:14:58.448849 Starting [0;1;39mApply Kernel Variables[0m...
11012 11:14:58.465059 Starting [0;1;39mCreate System Users[0m...
11013 11:14:58.486971 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11014 11:14:58.510431 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11015 11:14:58.523175 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11016 11:14:58.539203 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11017 11:14:58.555089 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11018 11:14:58.570581 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11019 11:14:58.603202 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11020 11:14:58.627186 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11021 11:14:58.642229 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11022 11:14:58.661581 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11023 11:14:58.714571 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11024 11:14:58.737779 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11025 11:14:58.762964 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11026 11:14:58.781848 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11027 11:14:58.831898 Starting [0;1;39mNetwork Time Synchronization[0m...
11028 11:14:58.851750 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11029 11:14:58.891052 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11030 11:14:58.939576 [[0;32m OK [0m] Created slic<6>[ 19.748571] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11031 11:14:58.943160 e [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11032 11:14:58.962707 <3>[ 19.772396] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11033 11:14:58.969126 <3>[ 19.780655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11034 11:14:58.979731 <3>[ 19.789510] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11035 11:14:58.986124 <6>[ 19.794146] remoteproc remoteproc0: scp is available
11036 11:14:58.995978 <4>[ 19.803513] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11037 11:14:58.999383 <6>[ 19.813442] remoteproc remoteproc0: powering up scp
11038 11:14:59.008824 <4>[ 19.818667] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11039 11:14:59.015552 <3>[ 19.828502] remoteproc remoteproc0: request_firmware failed: -2
11040 11:14:59.026753 <3>[ 19.836497] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11041 11:14:59.033533 <6>[ 19.839801] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11042 11:14:59.042866 <3>[ 19.844846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11043 11:14:59.046420 <6>[ 19.849025] usbcore: registered new interface driver r8152
11044 11:14:59.056035 <6>[ 19.852205] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11045 11:14:59.066095 <6>[ 19.852220] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11046 11:14:59.072923 <3>[ 19.883634] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11047 11:14:59.079005 <6>[ 19.883934] usbcore: registered new interface driver cdc_ether
11048 11:14:59.088835 <3>[ 19.892043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11049 11:14:59.095493 Startin<6>[ 19.892172] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11050 11:14:59.105141 g [0;1;39mLoad/<4>[ 19.895956] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11051 11:14:59.115311 Save Screen …o<4>[ 19.901947] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11052 11:14:59.121867 f leds:white:kbd<3>[ 19.906111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11053 11:14:59.128511 _backlight[0m..<6>[ 19.924288] mc: Linux media interface: v0.10
11054 11:14:59.129102 .
11055 11:14:59.138128 <3>[ 19.936722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11056 11:14:59.145110 <3>[ 19.956560] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11057 11:14:59.154936 <4>[ 19.962196] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11058 11:14:59.161871 <4>[ 19.962196] Fallback method does not support PEC.
11059 11:14:59.168742 <3>[ 19.965534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11060 11:14:59.175350 <6>[ 19.979136] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11061 11:14:59.182298 <6>[ 19.980232] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11062 11:14:59.188900 <6>[ 19.980245] pci_bus 0000:00: root bus resource [bus 00-ff]
11063 11:14:59.196374 <6>[ 19.980252] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11064 11:14:59.205118 <6>[ 19.980258] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11065 11:14:59.212097 <6>[ 19.980375] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11066 11:14:59.219212 <6>[ 19.980416] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11067 11:14:59.222185 <6>[ 19.980558] pci 0000:00:00.0: supports D1 D2
11068 11:14:59.229510 <6>[ 19.980563] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11069 11:14:59.239675 <6>[ 19.982535] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11070 11:14:59.246034 <6>[ 19.983213] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11071 11:14:59.252826 <6>[ 19.983255] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11072 11:14:59.260492 <6>[ 19.983281] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11073 11:14:59.267103 <6>[ 19.983300] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11074 11:14:59.273198 <6>[ 19.983434] pci 0000:01:00.0: supports D1 D2
11075 11:14:59.280026 <6>[ 19.983438] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11076 11:14:59.286756 <3>[ 19.986775] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11077 11:14:59.296915 <3>[ 19.986949] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11078 11:14:59.300374 <6>[ 19.987001] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11079 11:14:59.310402 <6>[ 19.987072] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11080 11:14:59.317249 <6>[ 19.987080] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11081 11:14:59.326891 <6>[ 19.987097] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11082 11:14:59.333859 <6>[ 19.987114] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11083 11:14:59.343396 <6>[ 19.987130] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11084 11:14:59.346298 <6>[ 19.987147] pci 0000:00:00.0: PCI bridge to [bus 01]
11085 11:14:59.356597 <6>[ 19.987157] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11086 11:14:59.362908 <6>[ 19.987795] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11087 11:14:59.367009 <6>[ 19.990230] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11088 11:14:59.373200 <6>[ 19.990758] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11089 11:14:59.383379 <3>[ 19.997317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11090 11:14:59.389571 <3>[ 20.000978] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11091 11:14:59.399427 <4>[ 20.018267] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11092 11:14:59.409674 <3>[ 20.023716] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11093 11:14:59.412619 <3>[ 20.023881] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
11094 11:14:59.422199 <4>[ 20.029953] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11095 11:14:59.432254 <6>[ 20.035344] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11096 11:14:59.442848 <6>[ 20.035798] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11097 11:14:59.449375 <3>[ 20.037446] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11098 11:14:59.459330 <3>[ 20.044342] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11099 11:14:59.465348 <3>[ 20.044999] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11100 11:14:59.475378 <3>[ 20.048883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11101 11:14:59.482449 <3>[ 20.049022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11102 11:14:59.491872 <3>[ 20.079746] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11103 11:14:59.495396 <6>[ 20.095034] r8152 2-1.3:1.0 eth0: v1.12.13
11104 11:14:59.505112 <3>[ 20.119408] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11105 11:14:59.511914 <3>[ 20.128865] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
11106 11:14:59.518974 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11107 11:14:59.537419 <3>[ 20.347318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11108 11:14:59.546848 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11109 11:14:59.564693 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11110 11:14:59.574866 <3>[ 20.384005] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11111 11:14:59.606907 <3>[ 20.417024] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11112 11:14:59.613575 <3>[ 20.427159] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
11113 11:14:59.624374 <3>[ 20.433930] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
11114 11:14:59.630274 <6>[ 20.440871] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11115 11:14:59.642207 <3>[ 20.452516] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11116 11:14:59.649755 <6>[ 20.463154] videodev: Linux video capture interface: v2.00
11117 11:14:59.656077 <6>[ 20.465650] usbcore: registered new interface driver r8153_ecm
11118 11:14:59.670311 <5>[ 20.480323] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11119 11:14:59.673409 <6>[ 20.489706] Bluetooth: Core ver 2.22
11120 11:14:59.680276 <6>[ 20.493709] NET: Registered PF_BLUETOOTH protocol family
11121 11:14:59.686885 <6>[ 20.495991] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
11122 11:14:59.693238 <6>[ 20.499519] Bluetooth: HCI device and connection manager initialized
11123 11:14:59.699735 <5>[ 20.501159] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11124 11:14:59.706547 <6>[ 20.518955] Bluetooth: HCI socket layer initialized
11125 11:14:59.713187 <6>[ 20.520786] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11126 11:14:59.716626 <6>[ 20.524102] Bluetooth: L2CAP socket layer initialized
11127 11:14:59.729511 <6>[ 20.532402] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11128 11:14:59.736498 <6>[ 20.536595] Bluetooth: SCO socket layer initialized
11129 11:14:59.742712 <6>[ 20.549117] usbcore: registered new interface driver uvcvideo
11130 11:14:59.749962 <4>[ 20.559340] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11131 11:14:59.756533 <6>[ 20.564772] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11132 11:14:59.763922 <6>[ 20.569035] cfg80211: failed to load regulatory.db
11133 11:14:59.766745 <6>[ 20.580234] remoteproc remoteproc0: powering up scp
11134 11:14:59.777150 <4>[ 20.585828] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11135 11:14:59.784513 <3>[ 20.585853] remoteproc remoteproc0: request_firmware failed: -2
11136 11:14:59.791027 <3>[ 20.585861] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11137 11:14:59.800684 <3>[ 20.589380] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11138 11:14:59.807423 [[0;32m OK [0m] Reached targ<6>[ 20.619967] usbcore: registered new interface driver btusb
11139 11:14:59.821110 et [0;1;39mSyst<4>[ 20.621381] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11140 11:14:59.827924 em Initializatio<6>[ 20.630816] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11141 11:14:59.831591 n[0m.
11142 11:14:59.834876 <3>[ 20.638739] Bluetooth: hci0: Failed to load firmware file (-2)
11143 11:14:59.841204 <6>[ 20.647612] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11144 11:14:59.848414 <3>[ 20.654290] Bluetooth: hci0: Failed to set up firmware (-2)
11145 11:14:59.858597 <4>[ 20.666399] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11146 11:14:59.868111 [[0;32m OK [0m] Started [0;<6>[ 20.678882] mt7921e 0000:01:00.0: ASIC revision: 79610010
11147 11:14:59.871579 1;39mDaily Cleanup of Temporary Directories[0m.
11148 11:14:59.886067 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11149 11:14:59.905669 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11150 11:14:59.929438 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11151 11:14:59.941541 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11152 11:14:59.964247 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11153 11:14:59.977337 <4>[ 20.783661] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11154 11:14:59.983807 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11155 11:14:59.997918 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11156 11:15:00.017597 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11157 11:15:00.062909 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11158 11:15:00.094814 <4>[ 20.902195] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11159 11:15:00.107971 Starting [0;1;39mUser Login Management[0m...
11160 11:15:00.124616 Starting [0;1;39mPermit User Sessions[0m...
11161 11:15:00.140479 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11162 11:15:00.171703 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11163 11:15:00.215596 <4>[ 21.022205] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11164 11:15:00.228678 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11165 11:15:00.245101 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11166 11:15:00.262159 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11167 11:15:00.280095 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11168 11:15:00.302121 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11169 11:15:00.334571 [[0;32m OK [0m] Started [0;1;39mUser Login <4>[ 21.141972] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11170 11:15:00.337442 Management[0m.
11171 11:15:00.356049 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11172 11:15:00.374044 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11173 11:15:00.417107 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11174 11:15:00.457205 [[0;32m OK [0m] Finished [0<4>[ 21.262874] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11175 11:15:00.460375 ;1;39mUpdate UTMP about System Runlevel Changes[0m.
11176 11:15:00.502437
11177 11:15:00.503031
11178 11:15:00.505603 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11179 11:15:00.506087
11180 11:15:00.508685 debian-bullseye-arm64 login: root (automatic login)
11181 11:15:00.509220
11182 11:15:00.509697
11183 11:15:00.525258 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023 aarch64
11184 11:15:00.525789
11185 11:15:00.532234 The programs included with the Debian GNU/Linux system are free software;
11186 11:15:00.538780 the exact distribution terms for each program are described in the
11187 11:15:00.541629 individual files in /usr/share/doc/*/copyright.
11188 11:15:00.542142
11189 11:15:00.548811 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11190 11:15:00.551959 permitted by applicable law.
11191 11:15:00.553294 Matched prompt #10: / #
11193 11:15:00.554321 Setting prompt string to ['/ #']
11194 11:15:00.554753 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11196 11:15:00.555724 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11197 11:15:00.556247 start: 2.2.6 expect-shell-connection (timeout 00:02:53) [common]
11198 11:15:00.556615 Setting prompt string to ['/ #']
11199 11:15:00.556954 Forcing a shell prompt, looking for ['/ #']
11201 11:15:00.607809 / #
11202 11:15:00.608489 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11203 11:15:00.609009 Waiting using forced prompt support (timeout 00:02:30)
11204 11:15:00.609534 <4>[ 21.381276] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11205 11:15:00.614051
11206 11:15:00.614993 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11207 11:15:00.615522 start: 2.2.7 export-device-env (timeout 00:02:53) [common]
11208 11:15:00.616049 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11209 11:15:00.616537 end: 2.2 depthcharge-retry (duration 00:02:07) [common]
11210 11:15:00.617049 end: 2 depthcharge-action (duration 00:02:07) [common]
11211 11:15:00.617528 start: 3 lava-test-retry (timeout 00:05:00) [common]
11212 11:15:00.618036 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11213 11:15:00.618431 Using namespace: common
11215 11:15:00.719615 / # #
11216 11:15:00.720270 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11217 11:15:00.720853 #<4>[ 21.501169] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11218 11:15:00.726167
11219 11:15:00.727061 Using /lava-10591211
11221 11:15:00.828506 / # export SHELL=/bin/sh
11222 11:15:00.829357 export SHELL=/bin/sh<4>[ 21.621345] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11223 11:15:00.834783
11225 11:15:00.936852 / # . /lava-10591211/environment
11226 11:15:00.937656 . /lava-10591211/environment<4>[ 21.741713] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11227 11:15:00.943771
11229 11:15:01.087005 / # /lava-10591211/bin/lava-test-runner /lava-10591211/0
11230 11:15:01.087654 Test shell timeout: 10s (minimum of the action and connection timeout)
11231 11:15:01.089360 /lava-10591211/bin/lava-<4>[ 21.861347] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11232 11:15:01.093553 test-runner /lava-10591211/0
11233 11:15:01.137340 + export TESTRUN_ID=0_sleep
11234 11:15:01.137920 + cd /lava-10591211/0/tests/0_sleep
11235 11:15:01.138305 + cat uuid
11236 11:15:01.138699 + UUID=10591211_1.5.2.3.1
11237 11:15:01.139065 + set +x
11238 11:15:01.139402 <LAVA_SIGNAL_STARTRUN 0_sleep 10591211_1.5.2.3.1>
11239 11:15:01.139728 + ./config/lava/sleep/sleep.sh mem freeze
11240 11:15:01.140050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11241 11:15:01.140652 Received signal: <STARTRUN> 0_sleep 10591211_1.5.2.3.1
11242 11:15:01.141065 Starting test lava.0_sleep (10591211_1.5.2.3.1)
11243 11:15:01.141489 Skipping test definition patterns.
11244 11:15:01.142035 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11246 11:15:01.143193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11247 11:15:01.143558 rtcwake: assuming RTC uses UTC ...
11248 11:15:01.144151 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11250 11:15:01.152386 rtcwake: wakeup from "mem" using rtc0 at Mon<6>[ 21.965225] PM: suspend entry (deep)
11251 11:15:01.155301 Jun 5 11:15:04<6>[ 21.969899] Filesystems sync: 0.000 seconds
11252 11:15:01.158370 2023
11253 11:15:01.166786 <3>[ 21.980587] mt7921e 0000:01:00.0: hardware init failed
11254 11:15:01.170029 <6>[ 21.981211] Freezing user space processes
11255 11:15:01.181623 <6>[ 21.992002] Freezing user space processes completed (elapsed 0.001 seconds)
11256 11:15:01.185203 <6>[ 21.999235] OOM killer disabled.
11257 11:15:01.188628 <6>[ 22.002712] Freezing remaining freezable tasks
11258 11:15:01.198750 <6>[ 22.008644] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11259 11:15:01.204696 <6>[ 22.016306] printk: Suspending console(s) (use no_console_suspend to debug)
11260 11:15:04.359100 <3>[ 22.024961] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11261 11:15:04.365019 <3>[ 22.024993] elants_i2c 4-0010: PM: failed to suspend async: error -16
11262 11:15:04.371951 <3>[ 25.163137] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11263 11:15:04.381556 <3>[ 25.163171] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11264 11:15:04.388358 <3>[ 25.163208] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11265 11:15:04.395268 <3>[ 25.163231] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11266 11:15:04.404681 <3>[ 25.163518] PM: Some devices failed to suspend, or early wake event detected
11267 11:15:04.408015 <6>[ 25.222965] OOM killer enabled.
11268 11:15:04.411641 <6>[ 25.226359] Restarting tasks ... done.
11269 11:15:04.417851 <5>[ 25.231731] random: crng reseeded on system resumption
11270 11:15:04.421363 <6>[ 25.238996] PM: suspend exit
11271 11:15:04.424740 rtcwake: write error
11272 11:15:04.432895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11273 11:15:04.433698 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11275 11:15:04.436334 rtcwake: assuming RTC uses UTC ...
11276 11:15:04.442414 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 11:15:07 2023
11277 11:15:04.455592 <6>[ 25.269688] PM: suspend entry (deep)
11278 11:15:04.458956 <6>[ 25.273601] Filesystems sync: 0.000 seconds
11279 11:15:04.461901 <6>[ 25.278611] Freezing user space processes
11280 11:15:04.473811 <6>[ 25.284524] Freezing user space processes completed (elapsed 0.001 seconds)
11281 11:15:04.477188 <6>[ 25.291808] OOM killer disabled.
11282 11:15:04.480740 <6>[ 25.295296] Freezing remaining freezable tasks
11283 11:15:04.490636 <6>[ 25.301211] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11284 11:15:04.497146 <6>[ 25.308873] printk: Suspending console(s) (use no_console_suspend to debug)
11285 11:15:07.686505 <3>[ 25.317053] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11286 11:15:07.692843 <3>[ 25.317090] elants_i2c 4-0010: PM: failed to suspend async: error -16
11287 11:15:07.699821 <3>[ 28.491174] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11288 11:15:07.709149 <3>[ 28.491239] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11289 11:15:07.716043 <3>[ 28.491290] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11290 11:15:07.722458 <3>[ 28.491311] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11291 11:15:07.732541 <3>[ 28.491579] PM: Some devices failed to suspend, or early wake event detected
11292 11:15:07.735963 <6>[ 28.551246] OOM killer enabled.
11293 11:15:07.739083 <6>[ 28.554637] Restarting tasks ... done.
11294 11:15:07.745651 <5>[ 28.559876] random: crng reseeded on system resumption
11295 11:15:07.748981 <6>[ 28.566162] PM: suspend exit
11296 11:15:07.752110 rtcwake: write error
11297 11:15:07.759559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11298 11:15:07.759916 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11300 11:15:07.762538 rtcwake: assuming RTC uses UTC ...
11301 11:15:07.768956 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 11:15:11 2023
11302 11:15:07.781687 <6>[ 28.596741] PM: suspend entry (deep)
11303 11:15:07.785084 <6>[ 28.600644] Filesystems sync: 0.000 seconds
11304 11:15:07.788650 <6>[ 28.605714] Freezing user space processes
11305 11:15:07.799678 <6>[ 28.611651] Freezing user space processes completed (elapsed 0.001 seconds)
11306 11:15:07.803187 <6>[ 28.618930] OOM killer disabled.
11307 11:15:07.806400 <6>[ 28.622408] Freezing remaining freezable tasks
11308 11:15:07.816572 <6>[ 28.628308] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11309 11:15:07.822968 <6>[ 28.635976] printk: Suspending console(s) (use no_console_suspend to debug)
11310 11:15:11.014457 <3>[ 28.644258] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11311 11:15:11.021086 <3>[ 28.644299] elants_i2c 4-0010: PM: failed to suspend async: error -16
11312 11:15:11.027474 <3>[ 31.819063] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11313 11:15:11.037177 <3>[ 31.819087] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11314 11:15:11.043797 <3>[ 31.819112] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11315 11:15:11.050573 <3>[ 31.819134] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11316 11:15:11.060722 <3>[ 31.819410] PM: Some devices failed to suspend, or early wake event detected
11317 11:15:11.063735 <6>[ 31.879778] OOM killer enabled.
11318 11:15:11.067118 <6>[ 31.883214] Restarting tasks ... done.
11319 11:15:11.073783 <5>[ 31.888552] random: crng reseeded on system resumption
11320 11:15:11.076903 <6>[ 31.894762] PM: suspend exit
11321 11:15:11.080586 rtcwake: write error
11322 11:15:11.087268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11323 11:15:11.087533 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11325 11:15:11.090670 rtcwake: assuming RTC uses UTC ...
11326 11:15:11.097054 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 11:15:14 2023
11327 11:15:11.109957 <6>[ 31.925307] PM: suspend entry (deep)
11328 11:15:11.113384 <6>[ 31.929209] Filesystems sync: 0.000 seconds
11329 11:15:11.116551 <6>[ 31.934254] Freezing user space processes
11330 11:15:11.128564 <6>[ 31.940213] Freezing user space processes completed (elapsed 0.001 seconds)
11331 11:15:11.131775 <6>[ 31.947524] OOM killer disabled.
11332 11:15:11.134882 <6>[ 31.951016] Freezing remaining freezable tasks
11333 11:15:11.144661 <6>[ 31.956958] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11334 11:15:11.151367 <6>[ 31.964630] printk: Suspending console(s) (use no_console_suspend to debug)
11335 11:15:14.341263 <3>[ 31.972882] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11336 11:15:14.347814 <3>[ 31.972915] elants_i2c 4-0010: PM: failed to suspend async: error -16
11337 11:15:14.354755 <3>[ 35.147107] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11338 11:15:14.364467 <3>[ 35.147131] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11339 11:15:14.371538 <3>[ 35.147165] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11340 11:15:14.377705 <3>[ 35.147186] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11341 11:15:14.387669 <3>[ 35.147407] PM: Some devices failed to suspend, or early wake event detected
11342 11:15:14.391101 <6>[ 35.207395] OOM killer enabled.
11343 11:15:14.394079 <6>[ 35.210789] Restarting tasks ... done.
11344 11:15:14.401009 <5>[ 35.215946] random: crng reseeded on system resumption
11345 11:15:14.404738 <6>[ 35.223618] PM: suspend exit
11346 11:15:14.407751 rtcwake: write error
11347 11:15:14.415602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11348 11:15:14.415864 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11350 11:15:14.419437 rtcwake: assuming RTC uses UTC ...
11351 11:15:14.425545 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 11:15:17 2023
11352 11:15:14.438390 <6>[ 35.254243] PM: suspend entry (deep)
11353 11:15:14.441736 <6>[ 35.258136] Filesystems sync: 0.000 seconds
11354 11:15:14.448579 <6>[ 35.263265] Freezing user space processes
11355 11:15:14.454692 <6>[ 35.269276] Freezing user space processes completed (elapsed 0.001 seconds)
11356 11:15:14.458233 <6>[ 35.276608] OOM killer disabled.
11357 11:15:14.464993 <6>[ 35.280094] Freezing remaining freezable tasks
11358 11:15:14.471285 <6>[ 35.286052] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11359 11:15:14.481056 <6>[ 35.293723] printk: Suspending console(s) (use no_console_suspend to debug)
11360 11:15:17.669921 <3>[ 35.301979] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11361 11:15:17.676335 <3>[ 35.302015] elants_i2c 4-0010: PM: failed to suspend async: error -16
11362 11:15:17.682700 <3>[ 38.475196] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11363 11:15:17.692739 <3>[ 38.475281] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11364 11:15:17.699328 <3>[ 38.475379] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11365 11:15:17.705724 <3>[ 38.475472] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11366 11:15:17.716068 <3>[ 38.475734] PM: Some devices failed to suspend, or early wake event detected
11367 11:15:17.718805 <6>[ 38.536084] OOM killer enabled.
11368 11:15:17.722524 <6>[ 38.539495] Restarting tasks ... done.
11369 11:15:17.728967 <5>[ 38.544710] random: crng reseeded on system resumption
11370 11:15:17.732187 <6>[ 38.551068] PM: suspend exit
11371 11:15:17.735576 rtcwake: write error
11372 11:15:17.742248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11373 11:15:17.742511 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11375 11:15:17.745313 rtcwake: assuming RTC uses UTC ...
11376 11:15:17.751861 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 11:15:21 2023
11377 11:15:17.765459 <6>[ 38.581362] PM: suspend entry (deep)
11378 11:15:17.768922 <6>[ 38.585265] Filesystems sync: 0.000 seconds
11379 11:15:17.774767 <6>[ 38.590292] Freezing user space processes
11380 11:15:17.781536 <6>[ 38.596267] Freezing user space processes completed (elapsed 0.001 seconds)
11381 11:15:17.784746 <6>[ 38.603515] OOM killer disabled.
11382 11:15:17.791572 <6>[ 38.607001] Freezing remaining freezable tasks
11383 11:15:17.798077 <6>[ 38.613002] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11384 11:15:17.807691 <6>[ 38.620683] printk: Suspending console(s) (use no_console_suspend to debug)
11385 11:15:20.996872 <3>[ 38.628931] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11386 11:15:21.003366 <3>[ 38.628972] elants_i2c 4-0010: PM: failed to suspend async: error -16
11387 11:15:21.010171 <3>[ 41.803065] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11388 11:15:21.019807 <3>[ 41.803090] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11389 11:15:21.026753 <3>[ 41.803114] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11390 11:15:21.033060 <3>[ 41.803137] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11391 11:15:21.043104 <3>[ 41.803469] PM: Some devices failed to suspend, or early wake event detected
11392 11:15:21.046436 <6>[ 41.863354] OOM killer enabled.
11393 11:15:21.049680 <6>[ 41.866749] Restarting tasks ... done.
11394 11:15:21.056135 <5>[ 41.871944] random: crng reseeded on system resumption
11395 11:15:21.059616 <6>[ 41.878371] PM: suspend exit
11396 11:15:21.062497 rtcwake: write error
11397 11:15:21.069792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11398 11:15:21.070051 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11400 11:15:21.073253 rtcwake: assuming RTC uses UTC ...
11401 11:15:21.079577 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 11:15:24 2023
11402 11:15:21.092640 <6>[ 41.909237] PM: suspend entry (deep)
11403 11:15:21.096139 <6>[ 41.913130] Filesystems sync: 0.000 seconds
11404 11:15:21.102316 <6>[ 41.918204] Freezing user space processes
11405 11:15:21.108749 <6>[ 41.924111] Freezing user space processes completed (elapsed 0.001 seconds)
11406 11:15:21.112348 <6>[ 41.931426] OOM killer disabled.
11407 11:15:21.118905 <6>[ 41.934916] Freezing remaining freezable tasks
11408 11:15:21.128662 <6>[ 41.941021] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11409 11:15:21.135583 <6>[ 41.948712] printk: Suspending console(s) (use no_console_suspend to debug)
11410 11:15:24.324217 <3>[ 41.956896] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11411 11:15:24.331033 <3>[ 41.956926] elants_i2c 4-0010: PM: failed to suspend async: error -16
11412 11:15:24.337453 <3>[ 45.131096] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11413 11:15:24.347647 <3>[ 45.131120] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11414 11:15:24.354101 <3>[ 45.131145] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11415 11:15:24.360442 <3>[ 45.131167] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11416 11:15:24.370523 <3>[ 45.131485] PM: Some devices failed to suspend, or early wake event detected
11417 11:15:24.373710 <6>[ 45.191380] OOM killer enabled.
11418 11:15:24.377705 <6>[ 45.194774] Restarting tasks ... done.
11419 11:15:24.384153 <5>[ 45.199955] random: crng reseeded on system resumption
11420 11:15:24.387044 <6>[ 45.206379] PM: suspend exit
11421 11:15:24.390588 rtcwake: write error
11422 11:15:24.397041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11423 11:15:24.397332 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11425 11:15:24.400538 rtcwake: assuming RTC uses UTC ...
11426 11:15:24.407020 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 11:15:27 2023
11427 11:15:24.419814 <6>[ 45.236983] PM: suspend entry (deep)
11428 11:15:24.423507 <6>[ 45.240944] Filesystems sync: 0.000 seconds
11429 11:15:24.430109 <6>[ 45.245983] Freezing user space processes
11430 11:15:24.436294 <6>[ 45.251796] Freezing user space processes completed (elapsed 0.001 seconds)
11431 11:15:24.439922 <6>[ 45.259080] OOM killer disabled.
11432 11:15:24.446433 <6>[ 45.262559] Freezing remaining freezable tasks
11433 11:15:24.453155 <6>[ 45.268453] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11434 11:15:24.462615 <6>[ 45.276106] printk: Suspending console(s) (use no_console_suspend to debug)
11435 11:15:27.652969 <3>[ 45.284326] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11436 11:15:27.659568 <3>[ 45.284359] elants_i2c 4-0010: PM: failed to suspend async: error -16
11437 11:15:27.659671 <6>[ 48.203170] vpu: disabling
11438 11:15:27.662647 <6>[ 48.203264] vproc2: disabling
11439 11:15:27.665977 <6>[ 48.203301] vproc1: disabling
11440 11:15:27.669094 <6>[ 48.203339] vaud18: disabling
11441 11:15:27.675777 <6>[ 48.203521] vsram_others: disabling
11442 11:15:27.675871 <6>[ 48.203647] va09: disabling
11443 11:15:27.679365 <6>[ 48.203701] vsram_md: disabling
11444 11:15:27.682364 <6>[ 48.203795] Vgpu: disabling
11445 11:15:27.689562 <3>[ 48.459066] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11446 11:15:27.699057 <3>[ 48.459091] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11447 11:15:27.709041 <3>[ 48.459115] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11448 11:15:27.715334 <3>[ 48.459138] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11449 11:15:27.722157 <3>[ 48.459541] PM: Some devices failed to suspend, or early wake event detected
11450 11:15:27.725212 <6>[ 48.545932] OOM killer enabled.
11451 11:15:27.733012 <6>[ 48.549332] Restarting tasks ... done.
11452 11:15:27.736293 <5>[ 48.554554] random: crng reseeded on system resumption
11453 11:15:27.740688 <6>[ 48.561235] PM: suspend exit
11454 11:15:27.743681 rtcwake: write error
11455 11:15:27.752149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11456 11:15:27.752417 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11458 11:15:27.755463 rtcwake: assuming RTC uses UTC ...
11459 11:15:27.761835 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 11:15:31 2023
11460 11:15:27.775084 <6>[ 48.592453] PM: suspend entry (deep)
11461 11:15:27.778522 <6>[ 48.596339] Filesystems sync: 0.000 seconds
11462 11:15:27.781479 <6>[ 48.601360] Freezing user space processes
11463 11:15:27.792705 <6>[ 48.606907] Freezing user space processes completed (elapsed 0.001 seconds)
11464 11:15:27.796226 <6>[ 48.614135] OOM killer disabled.
11465 11:15:27.799252 <6>[ 48.617618] Freezing remaining freezable tasks
11466 11:15:27.809651 <6>[ 48.623498] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11467 11:15:27.816150 <6>[ 48.631153] printk: Suspending console(s) (use no_console_suspend to debug)
11468 11:15:30.980031 <3>[ 48.639446] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11469 11:15:30.987240 <3>[ 48.639475] elants_i2c 4-0010: PM: failed to suspend async: error -16
11470 11:15:30.993328 <3>[ 51.787120] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11471 11:15:31.003496 <3>[ 51.787147] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11472 11:15:31.010067 <3>[ 51.787183] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11473 11:15:31.016603 <3>[ 51.787202] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11474 11:15:31.026564 <3>[ 51.787536] PM: Some devices failed to suspend, or early wake event detected
11475 11:15:31.029828 <6>[ 51.847972] OOM killer enabled.
11476 11:15:31.032991 <6>[ 51.851389] Restarting tasks ... done.
11477 11:15:31.039893 <5>[ 51.856716] random: crng reseeded on system resumption
11478 11:15:31.042924 <6>[ 51.862891] PM: suspend exit
11479 11:15:31.046392 rtcwake: write error
11480 11:15:31.053476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11481 11:15:31.053790 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11483 11:15:31.056506 rtcwake: assuming RTC uses UTC ...
11484 11:15:31.063483 rtcwake: wakeup from "mem" using rtc0 at Mon Jun 5 11:15:34 2023
11485 11:15:31.076220 <6>[ 51.894015] PM: suspend entry (deep)
11486 11:15:31.079539 <6>[ 51.897913] Filesystems sync: 0.000 seconds
11487 11:15:31.086009 <6>[ 51.903218] Freezing user space processes
11488 11:15:31.092715 <6>[ 51.909279] Freezing user space processes completed (elapsed 0.001 seconds)
11489 11:15:31.096181 <6>[ 51.916518] OOM killer disabled.
11490 11:15:31.102414 <6>[ 51.920001] Freezing remaining freezable tasks
11491 11:15:31.112117 <6>[ 51.925932] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11492 11:15:31.119245 <6>[ 51.933602] printk: Suspending console(s) (use no_console_suspend to debug)
11493 11:15:34.308115 <3>[ 51.941988] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11494 11:15:34.314968 <3>[ 51.942027] elants_i2c 4-0010: PM: failed to suspend async: error -16
11495 11:15:34.321366 <3>[ 55.115094] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11496 11:15:34.331416 <3>[ 55.115118] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11497 11:15:34.338029 <3>[ 55.115152] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11498 11:15:34.344652 <3>[ 55.115173] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11499 11:15:34.354630 <3>[ 55.115494] PM: Some devices failed to suspend, or early wake event detected
11500 11:15:34.357848 <6>[ 55.176199] OOM killer enabled.
11501 11:15:34.360983 <6>[ 55.179610] Restarting tasks ... done.
11502 11:15:34.368117 <5>[ 55.184691] random: crng reseeded on system resumption
11503 11:15:34.370992 <6>[ 55.190932] PM: suspend exit
11504 11:15:34.374100 rtcwake: write error
11505 11:15:34.380934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11506 11:15:34.381624 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11508 11:15:34.384151 rtcwake: assuming RTC uses UTC ...
11509 11:15:34.390983 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 11:15:37 2023
11510 11:15:34.405548 <6>[ 55.223156] PM: suspend entry (s2idle)
11511 11:15:34.408877 <6>[ 55.227217] Filesystems sync: 0.000 seconds
11512 11:15:34.415081 <6>[ 55.232271] Freezing user space processes
11513 11:15:34.421555 <6>[ 55.238184] Freezing user space processes completed (elapsed 0.001 seconds)
11514 11:15:34.425129 <6>[ 55.245431] OOM killer disabled.
11515 11:15:34.431817 <6>[ 55.248916] Freezing remaining freezable tasks
11516 11:15:34.438447 <6>[ 55.254989] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11517 11:15:34.448062 <6>[ 55.262663] printk: Suspending console(s) (use no_console_suspend to debug)
11518 11:15:37.634909 <3>[ 55.270791] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11519 11:15:37.641544 <3>[ 55.270863] elants_i2c 4-0010: PM: failed to suspend async: error -16
11520 11:15:37.648192 <3>[ 58.443128] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11521 11:15:37.658367 <3>[ 58.443153] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11522 11:15:37.664867 <3>[ 58.443188] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11523 11:15:37.671143 <3>[ 58.443209] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11524 11:15:37.681348 <3>[ 58.443547] PM: Some devices failed to suspend, or early wake event detected
11525 11:15:37.684804 <6>[ 58.503290] OOM killer enabled.
11526 11:15:37.688083 <6>[ 58.506684] Restarting tasks ... done.
11527 11:15:37.694522 <5>[ 58.511854] random: crng reseeded on system resumption
11528 11:15:37.697621 <6>[ 58.518536] PM: suspend exit
11529 11:15:37.700842 rtcwake: write error
11530 11:15:37.708048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11531 11:15:37.708936 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11533 11:15:37.711184 rtcwake: assuming RTC uses UTC ...
11534 11:15:37.717925 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 11:15:41 2023
11535 11:15:37.731041 <6>[ 58.549202] PM: suspend entry (s2idle)
11536 11:15:37.734208 <6>[ 58.553276] Filesystems sync: 0.000 seconds
11537 11:15:37.740704 <6>[ 58.558342] Freezing user space processes
11538 11:15:37.747385 <6>[ 58.564256] Freezing user space processes completed (elapsed 0.001 seconds)
11539 11:15:37.750784 <6>[ 58.571499] OOM killer disabled.
11540 11:15:37.757232 <6>[ 58.574983] Freezing remaining freezable tasks
11541 11:15:37.763776 <6>[ 58.581004] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11542 11:15:37.773507 <6>[ 58.588711] printk: Suspending console(s) (use no_console_suspend to debug)
11543 11:15:40.962796 <3>[ 58.597005] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11544 11:15:40.969573 <3>[ 58.597044] elants_i2c 4-0010: PM: failed to suspend async: error -16
11545 11:15:40.975730 <3>[ 61.771064] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11546 11:15:40.985836 <3>[ 61.771087] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11547 11:15:40.992456 <3>[ 61.771111] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11548 11:15:40.999038 <3>[ 61.771133] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11549 11:15:41.009068 <3>[ 61.771465] PM: Some devices failed to suspend, or early wake event detected
11550 11:15:41.012125 <6>[ 61.831273] OOM killer enabled.
11551 11:15:41.015529 <6>[ 61.834667] Restarting tasks ... done.
11552 11:15:41.023272 <5>[ 61.842042] random: crng reseeded on system resumption
11553 11:15:41.027943 <6>[ 61.849898] PM: suspend exit
11554 11:15:41.031083 rtcwake: write error
11555 11:15:41.039074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11556 11:15:41.039782 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11558 11:15:41.042108 rtcwake: assuming RTC uses UTC ...
11559 11:15:41.048906 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 11:15:44 2023
11560 11:15:41.061958 <6>[ 61.880498] PM: suspend entry (s2idle)
11561 11:15:41.065288 <6>[ 61.884578] Filesystems sync: 0.000 seconds
11562 11:15:41.071952 <6>[ 61.889665] Freezing user space processes
11563 11:15:41.078502 <6>[ 61.894968] Freezing user space processes completed (elapsed 0.001 seconds)
11564 11:15:41.081278 <6>[ 61.902192] OOM killer disabled.
11565 11:15:41.088073 <6>[ 61.905682] Freezing remaining freezable tasks
11566 11:15:41.094975 <6>[ 61.911577] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11567 11:15:41.101181 <6>[ 61.919233] printk: Suspending console(s) (use no_console_suspend to debug)
11568 11:15:44.290115 <3>[ 61.927513] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11569 11:15:44.296867 <3>[ 61.927543] elants_i2c 4-0010: PM: failed to suspend async: error -16
11570 11:15:44.303450 <3>[ 65.099205] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11571 11:15:44.313214 <3>[ 65.099307] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11572 11:15:44.320182 <3>[ 65.099392] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11573 11:15:44.326527 <3>[ 65.099441] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11574 11:15:44.336567 <3>[ 65.099705] PM: Some devices failed to suspend, or early wake event detected
11575 11:15:44.339766 <6>[ 65.159681] OOM killer enabled.
11576 11:15:44.343385 <6>[ 65.163106] Restarting tasks ... done.
11577 11:15:44.349643 <5>[ 65.167785] random: crng reseeded on system resumption
11578 11:15:44.353307 <6>[ 65.174143] PM: suspend exit
11579 11:15:44.356301 rtcwake: write error
11580 11:15:44.363016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11581 11:15:44.363275 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11583 11:15:44.366378 rtcwake: assuming RTC uses UTC ...
11584 11:15:44.372683 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 11:15:47 2023
11585 11:15:44.385922 <6>[ 65.205191] PM: suspend entry (s2idle)
11586 11:15:44.389177 <6>[ 65.209263] Filesystems sync: 0.000 seconds
11587 11:15:44.395784 <6>[ 65.214311] Freezing user space processes
11588 11:15:44.402629 <6>[ 65.219989] Freezing user space processes completed (elapsed 0.001 seconds)
11589 11:15:44.405689 <6>[ 65.227231] OOM killer disabled.
11590 11:15:44.412214 <6>[ 65.230709] Freezing remaining freezable tasks
11591 11:15:44.418517 <6>[ 65.236745] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11592 11:15:44.428418 <6>[ 65.244442] printk: Suspending console(s) (use no_console_suspend to debug)
11593 11:15:47.617956 <3>[ 65.252702] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11594 11:15:47.624183 <3>[ 65.252747] elants_i2c 4-0010: PM: failed to suspend async: error -16
11595 11:15:47.627800 <3>[ 68.427097] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11596 11:15:47.640768 <3>[ 68.427120] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11597 11:15:47.647560 <3>[ 68.427145] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11598 11:15:47.653862 <3>[ 68.427167] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11599 11:15:47.663858 <3>[ 68.427494] PM: Some devices failed to suspend, or early wake event detected
11600 11:15:47.666980 <6>[ 68.487425] OOM killer enabled.
11601 11:15:47.670267 <6>[ 68.490824] Restarting tasks ... done.
11602 11:15:47.676909 <5>[ 68.495566] random: crng reseeded on system resumption
11603 11:15:47.680449 <6>[ 68.503087] PM: suspend exit
11604 11:15:47.683560 rtcwake: write error
11605 11:15:47.690676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11606 11:15:47.690935 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11608 11:15:47.694234 rtcwake: assuming RTC uses UTC ...
11609 11:15:47.700698 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 11:15:51 2023
11610 11:15:47.713657 <6>[ 68.533597] PM: suspend entry (s2idle)
11611 11:15:47.717388 <6>[ 68.537712] Filesystems sync: 0.000 seconds
11612 11:15:47.724073 <6>[ 68.542727] Freezing user space processes
11613 11:15:47.730167 <6>[ 68.548398] Freezing user space processes completed (elapsed 0.001 seconds)
11614 11:15:47.733392 <6>[ 68.555662] OOM killer disabled.
11615 11:15:47.740467 <6>[ 68.559146] Freezing remaining freezable tasks
11616 11:15:47.746984 <6>[ 68.565194] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11617 11:15:47.756553 <6>[ 68.572876] printk: Suspending console(s) (use no_console_suspend to debug)
11618 11:15:50.946027 <3>[ 68.581060] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11619 11:15:50.952564 <3>[ 68.581099] elants_i2c 4-0010: PM: failed to suspend async: error -16
11620 11:15:50.959064 <3>[ 71.755069] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11621 11:15:50.968710 <3>[ 71.755092] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11622 11:15:50.975855 <3>[ 71.755118] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11623 11:15:50.981919 <3>[ 71.755140] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11624 11:15:50.991925 <3>[ 71.755404] PM: Some devices failed to suspend, or early wake event detected
11625 11:15:50.995107 <6>[ 71.815920] OOM killer enabled.
11626 11:15:50.998464 <6>[ 71.819320] Restarting tasks ... done.
11627 11:15:51.005201 <5>[ 71.824116] random: crng reseeded on system resumption
11628 11:15:51.008710 <6>[ 71.831038] PM: suspend exit
11629 11:15:51.011711 rtcwake: write error
11630 11:15:51.018846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11631 11:15:51.019103 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11633 11:15:51.022300 rtcwake: assuming RTC uses UTC ...
11634 11:15:51.029137 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 11:15:54 2023
11635 11:15:51.042221 <6>[ 71.862111] PM: suspend entry (s2idle)
11636 11:15:51.045464 <6>[ 71.866162] Filesystems sync: 0.000 seconds
11637 11:15:51.051698 <6>[ 71.871222] Freezing user space processes
11638 11:15:51.058611 <6>[ 71.876858] Freezing user space processes completed (elapsed 0.001 seconds)
11639 11:15:51.061583 <6>[ 71.884120] OOM killer disabled.
11640 11:15:51.068139 <6>[ 71.887603] Freezing remaining freezable tasks
11641 11:15:51.074939 <6>[ 71.893523] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11642 11:15:51.085003 <6>[ 71.901201] printk: Suspending console(s) (use no_console_suspend to debug)
11643 11:15:54.272867 <3>[ 71.909580] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11644 11:15:54.279564 <3>[ 71.909620] elants_i2c 4-0010: PM: failed to suspend async: error -16
11645 11:15:54.286469 <3>[ 75.083095] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11646 11:15:54.296159 <3>[ 75.083120] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11647 11:15:54.302873 <3>[ 75.083154] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11648 11:15:54.309521 <3>[ 75.083175] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11649 11:15:54.319477 <3>[ 75.083623] PM: Some devices failed to suspend, or early wake event detected
11650 11:15:54.322636 <6>[ 75.143534] OOM killer enabled.
11651 11:15:54.326087 <6>[ 75.146932] Restarting tasks ... done.
11652 11:15:54.332510 <5>[ 75.151844] random: crng reseeded on system resumption
11653 11:15:54.336180 <6>[ 75.158264] PM: suspend exit
11654 11:15:54.339018 rtcwake: write error
11655 11:15:54.346330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11656 11:15:54.347074 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11658 11:15:54.349672 rtcwake: assuming RTC uses UTC ...
11659 11:15:54.356020 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 11:15:57 2023
11660 11:15:54.369002 <6>[ 75.189197] PM: suspend entry (s2idle)
11661 11:15:54.372169 <6>[ 75.193257] Filesystems sync: 0.000 seconds
11662 11:15:54.378703 <6>[ 75.198331] Freezing user space processes
11663 11:15:54.385379 <6>[ 75.203952] Freezing user space processes completed (elapsed 0.001 seconds)
11664 11:15:54.388554 <6>[ 75.211179] OOM killer disabled.
11665 11:15:54.395134 <6>[ 75.214656] Freezing remaining freezable tasks
11666 11:15:54.401851 <6>[ 75.220567] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11667 11:15:54.411537 <6>[ 75.228236] printk: Suspending console(s) (use no_console_suspend to debug)
11668 11:15:57.601324 <3>[ 75.236598] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11669 11:15:57.607977 <3>[ 75.236638] elants_i2c 4-0010: PM: failed to suspend async: error -16
11670 11:15:57.614317 <3>[ 78.411168] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11671 11:15:57.624188 <3>[ 78.411234] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11672 11:15:57.630903 <3>[ 78.411309] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11673 11:15:57.637853 <3>[ 78.411370] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11674 11:15:57.647594 <3>[ 78.411803] PM: Some devices failed to suspend, or early wake event detected
11675 11:15:57.650868 <6>[ 78.472076] OOM killer enabled.
11676 11:15:57.653974 <6>[ 78.475474] Restarting tasks ... done.
11677 11:15:57.660672 <5>[ 78.480280] random: crng reseeded on system resumption
11678 11:15:57.663773 <6>[ 78.486672] PM: suspend exit
11679 11:15:57.666886 rtcwake: write error
11680 11:15:57.673662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11681 11:15:57.673923 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11683 11:15:57.676866 rtcwake: assuming RTC uses UTC ...
11684 11:15:57.683652 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 11:16:01 2023
11685 11:15:57.696545 <6>[ 78.517417] PM: suspend entry (s2idle)
11686 11:15:57.699490 <6>[ 78.521497] Filesystems sync: 0.000 seconds
11687 11:15:57.706464 <6>[ 78.526588] Freezing user space processes
11688 11:15:57.712792 <6>[ 78.532431] Freezing user space processes completed (elapsed 0.001 seconds)
11689 11:15:57.716347 <6>[ 78.539675] OOM killer disabled.
11690 11:15:57.722849 <6>[ 78.543156] Freezing remaining freezable tasks
11691 11:15:57.729563 <6>[ 78.549173] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11692 11:15:57.739170 <6>[ 78.556844] printk: Suspending console(s) (use no_console_suspend to debug)
11693 11:16:00.928109 <3>[ 78.565239] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11694 11:16:00.934947 <3>[ 78.565268] elants_i2c 4-0010: PM: failed to suspend async: error -16
11695 11:16:00.941304 <3>[ 81.739096] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11696 11:16:00.951552 <3>[ 81.739120] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11697 11:16:00.958151 <3>[ 81.739154] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11698 11:16:00.964668 <3>[ 81.739176] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11699 11:16:00.974317 <3>[ 81.739592] PM: Some devices failed to suspend, or early wake event detected
11700 11:16:00.977668 <6>[ 81.799469] OOM killer enabled.
11701 11:16:00.980898 <6>[ 81.802868] Restarting tasks ... done.
11702 11:16:00.987663 <5>[ 81.807684] random: crng reseeded on system resumption
11703 11:16:00.990677 <6>[ 81.814422] PM: suspend exit
11704 11:16:00.994381 rtcwake: write error
11705 11:16:01.001177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11706 11:16:01.001436 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11708 11:16:01.004323 rtcwake: assuming RTC uses UTC ...
11709 11:16:01.010975 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 11:16:04 2023
11710 11:16:01.023724 <6>[ 81.845199] PM: suspend entry (s2idle)
11711 11:16:01.027233 <6>[ 81.849298] Filesystems sync: 0.000 seconds
11712 11:16:01.033553 <6>[ 81.854407] Freezing user space processes
11713 11:16:01.040297 <6>[ 81.860161] Freezing user space processes completed (elapsed 0.001 seconds)
11714 11:16:01.043465 <6>[ 81.867390] OOM killer disabled.
11715 11:16:01.050277 <6>[ 81.870873] Freezing remaining freezable tasks
11716 11:16:01.056659 <6>[ 81.876813] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11717 11:16:01.066553 <6>[ 81.884487] printk: Suspending console(s) (use no_console_suspend to debug)
11718 11:16:04.257161 <3>[ 81.893087] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11719 11:16:04.263577 <3>[ 81.893128] elants_i2c 4-0010: PM: failed to suspend async: error -16
11720 11:16:04.270202 <3>[ 85.067141] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11721 11:16:04.279945 <3>[ 85.067172] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11722 11:16:04.286533 <3>[ 85.067215] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11723 11:16:04.293582 <3>[ 85.067253] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11724 11:16:04.303073 <3>[ 85.067737] PM: Some devices failed to suspend, or early wake event detected
11725 11:16:04.306660 <6>[ 85.128356] OOM killer enabled.
11726 11:16:04.309897 <6>[ 85.131766] Restarting tasks ... done.
11727 11:16:04.316359 <5>[ 85.136456] random: crng reseeded on system resumption
11728 11:16:04.319720 <6>[ 85.142623] PM: suspend exit
11729 11:16:04.322853 rtcwake: write error
11730 11:16:04.329818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11731 11:16:04.330496 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11733 11:16:04.332828 rtcwake: assuming RTC uses UTC ...
11734 11:16:04.339586 rtcwake: wakeup from "freeze" using rtc0 at Mon Jun 5 11:16:07 2023
11735 11:16:04.353268 <6>[ 85.174324] PM: suspend entry (s2idle)
11736 11:16:04.356271 <6>[ 85.178407] Filesystems sync: 0.000 seconds
11737 11:16:04.362900 <6>[ 85.183636] Freezing user space processes
11738 11:16:04.369771 <6>[ 85.189364] Freezing user space processes completed (elapsed 0.001 seconds)
11739 11:16:04.372700 <6>[ 85.196610] OOM killer disabled.
11740 11:16:04.379433 <6>[ 85.200093] Freezing remaining freezable tasks
11741 11:16:04.386063 <6>[ 85.206174] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11742 11:16:04.395892 <6>[ 85.213859] printk: Suspending console(s) (use no_console_suspend to debug)
11743 11:16:07.584083 <3>[ 85.222205] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11744 11:16:07.590736 <3>[ 85.222247] elants_i2c 4-0010: PM: failed to suspend async: error -16
11745 11:16:07.597340 <3>[ 88.395116] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11746 11:16:07.606992 <3>[ 88.395141] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11747 11:16:07.613741 <3>[ 88.395174] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11748 11:16:07.620386 <3>[ 88.395195] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11749 11:16:07.630401 <3>[ 88.395668] PM: Some devices failed to suspend, or early wake event detected
11750 11:16:07.633501 <6>[ 88.456125] OOM killer enabled.
11751 11:16:07.636717 <6>[ 88.459524] Restarting tasks ... done.
11752 11:16:07.643240 <5>[ 88.464310] random: crng reseeded on system resumption
11753 11:16:07.647070 <6>[ 88.472000] PM: suspend exit
11754 11:16:07.650200 rtcwake: write error
11755 11:16:07.657684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11756 11:16:07.657943 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11758 11:16:07.661022 + set +x
11759 11:16:07.664678 <LAVA_SIGNAL_ENDRUN 0_sleep 10591211_1.5.2.3.1>
11760 11:16:07.664780 <LAVA_TEST_RUNNER EXIT>
11761 11:16:07.665029 Received signal: <ENDRUN> 0_sleep 10591211_1.5.2.3.1
11762 11:16:07.665107 Ending use of test pattern.
11763 11:16:07.665167 Ending test lava.0_sleep (10591211_1.5.2.3.1), duration 66.52
11765 11:16:07.665574 ok: lava_test_shell seems to have completed
11766 11:16:07.665760 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11767 11:16:07.665857 end: 3.1 lava-test-shell (duration 00:01:07) [common]
11768 11:16:07.665964 end: 3 lava-test-retry (duration 00:01:07) [common]
11769 11:16:07.666062 start: 4 finalize (timeout 00:06:13) [common]
11770 11:16:07.666150 start: 4.1 power-off (timeout 00:00:30) [common]
11771 11:16:07.666298 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11772 11:16:07.740845 >> Command sent successfully.
11773 11:16:07.743257 Returned 0 in 0 seconds
11774 11:16:07.843651 end: 4.1 power-off (duration 00:00:00) [common]
11776 11:16:07.843966 start: 4.2 read-feedback (timeout 00:06:13) [common]
11777 11:16:07.844221 Listened to connection for namespace 'common' for up to 1s
11778 11:16:07.844501 Listened to connection for namespace 'common' for up to 1s
11779 11:16:08.844876 Finalising connection for namespace 'common'
11780 11:16:08.845060 Disconnecting from shell: Finalise
11781 11:16:08.845155 / #
11782 11:16:08.945472 end: 4.2 read-feedback (duration 00:00:01) [common]
11783 11:16:08.945647 end: 4 finalize (duration 00:00:01) [common]
11784 11:16:08.945794 Cleaning after the job
11785 11:16:08.945927 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/ramdisk
11786 11:16:08.956101 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/kernel
11787 11:16:08.972680 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/dtb
11788 11:16:08.972897 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591211/tftp-deploy-c4dhww01/modules
11789 11:16:08.978154 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591211
11790 11:16:09.118761 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591211
11791 11:16:09.118935 Job finished correctly