Boot log: qemu_arm64-virt-gicv3
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
1 11:29:15.624231 lava-dispatcher, installed at version: 2023.01
2 11:29:15.624408 start: 0 validate
3 11:29:15.624512 Start time: 2023-06-05 11:29:15.624506+00:00 (UTC)
4 11:29:15.625609 Validating that http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig/gcc-10/kernel/Image exists
5 11:29:15.980267 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz exists
6 11:29:16.157872 cmd: ['docker', 'pull', 'kernelci/qemu']
7 11:29:16.158148 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 11:29:16.313836 >> Using default tag: latest
9 11:29:17.418504 >> latest: Pulling from kernelci/qemu
10 11:29:17.450484 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
11 11:29:17.450756 >> Status: Image is up to date for kernelci/qemu:latest
12 11:29:17.483750 >> docker.io/kernelci/qemu:latest
13 11:29:17.487620 Returned 0 in 1 seconds
14 11:29:17.625073 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 11:29:17.625479 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 11:29:20.137643 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 11:29:20.137959 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 11:29:21.706585 Returned 0 in 4 seconds
19 11:29:21.807816 validate duration: 6.18
21 11:29:21.808430 start: 1 deployimages (timeout 00:03:00) [common]
22 11:29:21.808636 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 11:29:21.809124 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8
24 11:29:21.809409 makedir: /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin
25 11:29:21.809643 makedir: /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/tests
26 11:29:21.809888 makedir: /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/results
27 11:29:21.810115 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-add-keys
28 11:29:21.810405 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-add-sources
29 11:29:21.810677 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-background-process-start
30 11:29:21.810953 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-background-process-stop
31 11:29:21.811224 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-common-functions
32 11:29:21.811486 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-echo-ipv4
33 11:29:21.811755 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-install-packages
34 11:29:21.812023 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-installed-packages
35 11:29:21.812288 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-os-build
36 11:29:21.812555 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-probe-channel
37 11:29:21.812818 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-probe-ip
38 11:29:21.813085 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-target-ip
39 11:29:21.813351 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-target-mac
40 11:29:21.813617 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-target-storage
41 11:29:21.813904 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-test-case
42 11:29:21.814176 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-test-event
43 11:29:21.814441 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-test-feedback
44 11:29:21.814709 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-test-raise
45 11:29:21.814980 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-test-reference
46 11:29:21.815248 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-test-runner
47 11:29:21.815512 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-test-set
48 11:29:21.815776 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-test-shell
49 11:29:21.816053 Updating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-install-packages (oe)
50 11:29:21.816384 Updating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/bin/lava-installed-packages (oe)
51 11:29:21.816674 Creating /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/environment
52 11:29:21.816911 LAVA metadata
53 11:29:21.817067 - LAVA_JOB_ID=562716
54 11:29:21.817220 - LAVA_DISPATCHER_IP=172.27.0.2
55 11:29:21.817451 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 11:29:21.817603 skipped lava-vland-overlay
57 11:29:21.817801 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 11:29:21.817986 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 11:29:21.818136 skipped lava-multinode-overlay
60 11:29:21.818320 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 11:29:21.818502 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 11:29:21.818676 Loading test definitions
63 11:29:21.818888 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 11:29:21.819058 Using /lava-562716 at stage 0
65 11:29:21.819700 uuid=562716_1.1.3.1 testdef=None
66 11:29:21.819896 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 11:29:21.820088 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 11:29:21.821028 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 11:29:21.821549 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 11:29:21.822710 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 11:29:21.823238 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 11:29:21.824341 runner path: /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/0/tests/0_timesync-off test_uuid 562716_1.1.3.1
75 11:29:21.824652 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 11:29:21.825178 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 11:29:21.825344 Using /lava-562716 at stage 0
79 11:29:21.825571 Fetching tests from https://github.com/kernelci/test-definitions.git
80 11:29:21.825760 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/0/tests/1_kselftest-arm64_qemu'
81 11:29:30.323318 Running '/usr/bin/git checkout kernelci.org
82 11:29:30.490249 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 11:29:30.491386 uuid=562716_1.1.3.5 testdef=None
84 11:29:30.491621 end: 1.1.3.5 git-repo-action (duration 00:00:09) [common]
86 11:29:30.492088 start: 1.1.3.6 test-overlay (timeout 00:02:51) [common]
87 11:29:30.493633 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 11:29:30.494110 start: 1.1.3.7 test-install-overlay (timeout 00:02:51) [common]
90 11:29:30.496216 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 11:29:30.496708 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:51) [common]
93 11:29:30.498755 runner path: /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/0/tests/1_kselftest-arm64_qemu test_uuid 562716_1.1.3.5
94 11:29:30.498927 BOARD='qemu_arm64-virt-gicv3'
95 11:29:30.499048 BRANCH='cip'
96 11:29:30.499163 SKIPFILE='/dev/null'
97 11:29:30.499279 SKIP_INSTALL='True'
98 11:29:30.499392 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig/gcc-10/kselftest.tar.xz'
99 11:29:30.499511 TST_CASENAME=''
100 11:29:30.499626 TST_CMDFILES='arm64'
101 11:29:30.499885 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 11:29:30.500331 Creating lava-test-runner.conf files
104 11:29:30.500456 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/562716/lava-overlay-7knnoxi8/lava-562716/0 for stage 0
105 11:29:30.500626 - 0_timesync-off
106 11:29:30.500757 - 1_kselftest-arm64_qemu
107 11:29:30.500931 end: 1.1.3 test-definition (duration 00:00:09) [common]
108 11:29:30.501096 start: 1.1.4 compress-overlay (timeout 00:02:51) [common]
109 11:29:39.357170 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 11:29:39.357365 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:42) [common]
111 11:29:39.357455 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 11:29:39.357558 end: 1.1 lava-overlay (duration 00:00:18) [common]
113 11:29:39.357651 start: 1.2 apply-overlay-guest (timeout 00:02:42) [common]
114 11:29:39.357731 Overlay: /var/lib/lava/dispatcher/tmp/562716/compress-overlay-ns7v6ep9/overlay-1.1.4.tar.gz
115 11:29:54.551264 end: 1.2 apply-overlay-guest (duration 00:00:15) [common]
117 11:29:54.551895 start: 1.3 deploy-device-env (timeout 00:02:27) [common]
118 11:29:54.552025 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 11:29:54.552157 start: 1.4 download-retry (timeout 00:02:27) [common]
120 11:29:54.552290 start: 1.4.1 http-download (timeout 00:02:27) [common]
121 11:29:54.552557 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig/gcc-10/kernel/Image
122 11:29:54.552695 saving as /var/lib/lava/dispatcher/tmp/562716/deployimages-kzri8r96/kernel/Image
123 11:29:54.552799 total size: 37356032 (35MB)
124 11:29:54.552903 No compression specified
125 11:29:54.905532 progress 0% (0MB)
126 11:29:55.957827 progress 5% (1MB)
127 11:29:56.133452 progress 10% (3MB)
128 11:29:56.324744 progress 15% (5MB)
129 11:29:56.341672 progress 20% (7MB)
130 11:29:56.701172 progress 25% (8MB)
131 11:29:56.864622 progress 30% (10MB)
132 11:29:57.032063 progress 35% (12MB)
133 11:29:57.238627 progress 40% (14MB)
134 11:29:57.249814 progress 45% (16MB)
135 11:29:57.421519 progress 50% (17MB)
136 11:29:57.782804 progress 55% (19MB)
137 11:29:58.088585 progress 60% (21MB)
138 11:29:58.308324 progress 65% (23MB)
139 11:29:58.613698 progress 70% (24MB)
140 11:29:58.821629 progress 75% (26MB)
141 11:29:59.012702 progress 80% (28MB)
142 11:29:59.318390 progress 85% (30MB)
143 11:29:59.524591 progress 90% (32MB)
144 11:29:59.714965 progress 95% (33MB)
145 11:30:00.020168 progress 100% (35MB)
146 11:30:00.020467 35MB downloaded in 5.47s (6.52MB/s)
147 11:30:00.020750 end: 1.4.1 http-download (duration 00:00:05) [common]
149 11:30:00.021250 end: 1.4 download-retry (duration 00:00:05) [common]
150 11:30:00.021413 start: 1.5 download-retry (timeout 00:02:22) [common]
151 11:30:00.021568 start: 1.5.1 http-download (timeout 00:02:22) [common]
152 11:30:00.021798 Not decompressing ramdisk as can be used compressed.
153 11:30:00.021961 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz
154 11:30:00.022085 saving as /var/lib/lava/dispatcher/tmp/562716/deployimages-kzri8r96/ramdisk/rootfs.cpio.gz
155 11:30:00.022205 total size: 88976554 (84MB)
156 11:30:00.022322 No compression specified
157 11:30:00.199291 progress 0% (0MB)
158 11:30:00.914734 progress 5% (4MB)
159 11:30:01.441034 progress 10% (8MB)
160 11:30:02.150341 progress 15% (12MB)
161 11:30:02.851971 progress 20% (17MB)
162 11:30:03.391019 progress 25% (21MB)
163 11:30:04.099240 progress 30% (25MB)
164 11:30:04.798042 progress 35% (29MB)
165 11:30:05.340297 progress 40% (33MB)
166 11:30:06.040079 progress 45% (38MB)
167 11:30:06.731886 progress 50% (42MB)
168 11:30:07.278390 progress 55% (46MB)
169 11:30:07.975692 progress 60% (50MB)
170 11:30:08.509072 progress 65% (55MB)
171 11:30:09.206145 progress 70% (59MB)
172 11:30:09.895726 progress 75% (63MB)
173 11:30:10.436573 progress 80% (67MB)
174 11:30:11.133139 progress 85% (72MB)
175 11:30:11.673407 progress 90% (76MB)
176 11:30:12.366796 progress 95% (80MB)
177 11:30:12.899939 progress 100% (84MB)
178 11:30:12.900422 84MB downloaded in 12.88s (6.59MB/s)
179 11:30:12.900784 end: 1.5.1 http-download (duration 00:00:13) [common]
181 11:30:12.901517 end: 1.5 download-retry (duration 00:00:13) [common]
182 11:30:12.901767 end: 1 deployimages (duration 00:00:51) [common]
183 11:30:12.902009 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 11:30:12.902247 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 11:30:12.902483 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 11:30:12.902974 Extending command line for qcow2 test overlay
187 11:30:12.903773 Pulling docker image
188 11:30:12.904007 cmd: ['docker', 'pull', 'kernelci/qemu']
189 11:30:12.904208 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 11:30:13.073879 >> Using default tag: latest
191 11:30:14.443365 >> latest: Pulling from kernelci/qemu
192 11:30:14.513119 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
193 11:30:14.513413 >> Status: Image is up to date for kernelci/qemu:latest
194 11:30:14.570807 >> docker.io/kernelci/qemu:latest
195 11:30:14.573493 Returned 0 in 1 seconds
196 11:30:14.712023 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-562716-2.1.1-pxgdojamxi --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/562716/deployimages-kzri8r96/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/562716/deployimages-kzri8r96/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/562716/apply-overlay-guest-q56c4op_/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 11:30:14.856400 started a shell command
198 11:30:14.856935 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 11:30:14.857088 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 11:30:14.857228 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 11:30:14.857367 Setting prompt string to ['Linux version [0-9]']
202 11:30:14.857474 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 11:30:19.464504 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 11:30:19.465094 start: 2.2.1 login-action (timeout 00:04:53) [common]
205 11:30:19.465227 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
206 11:30:19.465358 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
207 11:30:19.465492 Using line separator: #'\n'#
208 11:30:19.465601 No login prompt set.
209 11:30:19.465703 Parsing kernel messages
210 11:30:19.465795 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
211 11:30:19.465933 [login-action] Waiting for messages, (timeout 00:04:53)
212 11:30:19.466756 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609202-arm64-gcc-10-defconfig-vv44j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 11:10:42 UTC 2023
213 11:30:19.466852 [ 0.000000] random: crng init done
214 11:30:19.466951 [ 0.000000] Machine model: linux,dummy-virt
215 11:30:19.467035 [ 0.000000] efi: UEFI not found.
216 11:30:19.467118 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
217 11:30:19.467182 [ 0.000000] printk: bootconsole [pl11] enabled
218 11:30:19.469373 [ 0.000000] NUMA: No NUMA configuration found
219 11:30:19.469602 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 11:30:19.470195 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf2a00-0x7fdf4fff]
221 11:30:19.472411 [ 0.000000] Zone ranges:
222 11:30:19.473160 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 11:30:19.473275 [ 0.000000] DMA32 empty
224 11:30:19.473621 [ 0.000000] Normal empty
225 11:30:19.473831 [ 0.000000] Movable zone start for each node
226 11:30:19.473966 [ 0.000000] Early memory node ranges
227 11:30:19.474164 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 11:30:19.474326 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 11:30:19.488856 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 11:30:19.489775 [ 0.000000] psci: probing for conduit method from DT.
231 11:30:19.490256 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 11:30:19.490704 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 11:30:19.490863 [ 0.000000] psci: Trusted OS migration not required
234 11:30:19.490991 [ 0.000000] psci: SMC Calling Convention v1.0
235 11:30:19.493110 [ 0.000000] percpu: Embedded 20 pages/cpu s44840 r8192 d28888 u81920
236 11:30:19.493756 [ 0.000000] pcpu-alloc: s44840 r8192 d28888 u81920 alloc=20*4096
237 11:30:19.493962 [ 0.000000] pcpu-alloc: [0] 0
238 11:30:19.495413 [ 0.000000] Detected PIPT I-cache on CPU0
239 11:30:19.500717 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 11:30:19.501519 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 11:30:19.501736 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 11:30:19.501939 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 11:30:19.502094 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 11:30:19.502451 [ 0.000000] CPU features: detected: Spectre-v4
245 11:30:19.506369 [ 0.000000] alternatives: applying boot alternatives
246 11:30:19.509320 [ 0.000000] Fallback order for Node 0: 0
247 11:30:19.509788 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 11:30:19.509918 [ 0.000000] Policy zone: DMA
249 11:30:19.510325 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 11:30:19.512867 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 11:30:19.515462 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 11:30:19.516039 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 11:30:19.516559 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 11:30:19.525892 <6>[ 0.000000] Memory: 870672K/1048576K available (16192K kernel code, 3712K rwdata, 8856K rodata, 7552K init, 609K bss, 145136K reserved, 32768K cma-reserved)
255 11:30:19.531796 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 11:30:19.538541 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 11:30:19.538676 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 11:30:19.539035 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 11:30:19.539156 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 11:30:19.539511 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 11:30:19.539869 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 11:30:19.539985 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 11:30:19.541017 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 11:30:19.547811 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 11:30:19.548183 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 11:30:19.549920 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 11:30:19.550095 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 11:30:19.550826 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 11:30:19.555421 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 11:30:19.556266 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @42830000 (indirect, esz 8, psz 64K, shr 1)
271 11:30:19.556627 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @42840000 (flat, esz 8, psz 64K, shr 1)
272 11:30:19.557406 <6>[ 0.000000] GICv3: using LPI property table @0x0000000042850000
273 11:30:19.558167 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000042860000
274 11:30:19.559518 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 11:30:19.567636 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 11:30:19.568146 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 11:30:19.568796 <6>[ 0.000075] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 11:30:19.586024 <6>[ 0.014820] Console: colour dummy device 80x25
279 11:30:19.590373 <6>[ 0.020870] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 11:30:19.590477 <6>[ 0.021829] pid_max: default: 32768 minimum: 301
281 11:30:19.591902 <6>[ 0.023272] LSM: Security Framework initializing
282 11:30:19.596142 <6>[ 0.027507] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 11:30:19.596526 <6>[ 0.027829] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 11:30:19.628707 <4>[ 0.059856] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 11:30:19.634571 <6>[ 0.065803] cblist_init_generic: Setting adjustable number of callback queues.
286 11:30:19.634829 <6>[ 0.066180] cblist_init_generic: Setting shift to 0 and lim to 1.
287 11:30:19.635313 <6>[ 0.066768] cblist_init_generic: Setting shift to 0 and lim to 1.
288 11:30:19.637204 <6>[ 0.068436] rcu: Hierarchical SRCU implementation.
289 11:30:19.637401 <6>[ 0.068715] rcu: Max phase no-delay instances is 1000.
290 11:30:19.642381 <6>[ 0.073606] Platform MSI: its@8080000 domain created
291 11:30:19.643170 <6>[ 0.074225] PCI/MSI: /intc@8000000/its@8080000 domain created
292 11:30:19.643653 <6>[ 0.074882] fsl-mc MSI: its@8080000 domain created
293 11:30:19.646876 <6>[ 0.078340] EFI services will not be available.
294 11:30:19.647996 <6>[ 0.079193] smp: Bringing up secondary CPUs ...
295 11:30:19.648212 <6>[ 0.079421] smp: Brought up 1 node, 1 CPU
296 11:30:19.648408 <6>[ 0.079538] SMP: Total of 1 processors activated.
297 11:30:19.648619 <6>[ 0.079882] CPU features: detected: Branch Target Identification
298 11:30:19.648874 <6>[ 0.080117] CPU features: detected: 32-bit EL0 Support
299 11:30:19.649093 <6>[ 0.080287] CPU features: detected: 32-bit EL1 Support
300 11:30:19.649268 <6>[ 0.080430] CPU features: detected: ARMv8.4 Translation Table Level
301 11:30:19.649422 <6>[ 0.080566] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 11:30:19.649568 <6>[ 0.080870] CPU features: detected: Common not Private translations
303 11:30:19.650000 <6>[ 0.081461] CPU features: detected: CRC32 instructions
304 11:30:19.650176 <6>[ 0.081600] CPU features: detected: E0PD
305 11:30:19.650363 <6>[ 0.081784] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 11:30:19.650554 <6>[ 0.081976] CPU features: detected: RCpc load-acquire (LDAPR)
307 11:30:19.651020 <6>[ 0.082172] CPU features: detected: LSE atomic instructions
308 11:30:19.651213 <6>[ 0.082350] CPU features: detected: Privileged Access Never
309 11:30:19.651374 <6>[ 0.082480] CPU features: detected: RAS Extension Support
310 11:30:19.651548 <6>[ 0.082605] CPU features: detected: Random Number Generator
311 11:30:19.651699 <6>[ 0.082774] CPU features: detected: Speculation barrier (SB)
312 11:30:19.651856 <6>[ 0.082942] CPU features: detected: Stage-2 Force Write-Back
313 11:30:19.652027 <6>[ 0.083080] CPU features: detected: TLB range maintenance instructions
314 11:30:19.652171 <6>[ 0.083285] CPU features: detected: Scalable Matrix Extension
315 11:30:19.652289 <6>[ 0.083420] CPU features: detected: FA64
316 11:30:19.652424 <6>[ 0.083520] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 11:30:19.652544 <6>[ 0.083686] CPU features: detected: Scalable Vector Extension
318 11:30:19.664300 <6>[ 0.093132] SVE: maximum available vector length 256 bytes per vector
319 11:30:19.664748 <6>[ 0.096164] SVE: default vector length 64 bytes per vector
320 11:30:19.666821 <6>[ 0.098085] SME: minimum available vector length 16 bytes per vector
321 11:30:19.666988 <6>[ 0.098244] SME: maximum available vector length 256 bytes per vector
322 11:30:19.667144 <6>[ 0.098421] SME: default vector length 32 bytes per vector
323 11:30:19.667317 <6>[ 0.098844] CPU: All CPU(s) started at EL1
324 11:30:19.667732 <6>[ 0.099173] alternatives: applying system-wide alternatives
325 11:30:19.719669 <6>[ 0.150952] devtmpfs: initialized
326 11:30:19.739821 <6>[ 0.170906] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 11:30:19.740546 <6>[ 0.171832] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 11:30:19.746512 <6>[ 0.177818] pinctrl core: initialized pinctrl subsystem
329 11:30:19.757625 <6>[ 0.189097] DMI not present or invalid.
330 11:30:19.767327 <6>[ 0.198500] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 11:30:19.778971 <6>[ 0.210105] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 11:30:19.779587 <6>[ 0.210941] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 11:30:19.779988 <6>[ 0.211411] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 11:30:19.780411 <6>[ 0.211875] audit: initializing netlink subsys (disabled)
335 11:30:19.786333 <5>[ 0.217582] audit: type=2000 audit(0.176:1): state=initialized audit_enabled=0 res=1
336 11:30:19.788345 <6>[ 0.219600] thermal_sys: Registered thermal governor 'step_wise'
337 11:30:19.788920 <6>[ 0.219669] thermal_sys: Registered thermal governor 'power_allocator'
338 11:30:19.789015 <6>[ 0.220238] cpuidle: using governor menu
339 11:30:19.790578 <6>[ 0.221934] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
340 11:30:19.791253 <6>[ 0.222552] ASID allocator initialised with 65536 entries
341 11:30:19.796697 <6>[ 0.228203] Serial: AMBA PL011 UART driver
342 11:30:19.843649 <6>[ 0.274849] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
343 11:30:19.845010 <6>[ 0.276439] printk: console [ttyAMA0] enabled
344 11:30:19.845523 <6>[ 0.276439] printk: console [ttyAMA0] enabled
345 11:30:19.845714 <6>[ 0.276936] printk: bootconsole [pl11] disabled
346 11:30:19.845885 <6>[ 0.276936] printk: bootconsole [pl11] disabled
347 11:30:19.856028 <6>[ 0.287529] KASLR enabled
348 11:30:19.887533 <6>[ 0.318581] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
349 11:30:19.887715 <6>[ 0.318946] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
350 11:30:19.887823 <6>[ 0.319187] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
351 11:30:19.887960 <6>[ 0.319400] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
352 11:30:19.888336 <6>[ 0.319627] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
353 11:30:19.888552 <6>[ 0.319833] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
354 11:30:19.888698 <6>[ 0.320005] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
355 11:30:19.888847 <6>[ 0.320189] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
356 11:30:19.898167 <6>[ 0.329612] ACPI: Interpreter disabled.
357 11:30:19.906308 <6>[ 0.337586] iommu: Default domain type: Translated
358 11:30:19.906420 <6>[ 0.337745] iommu: DMA domain TLB invalidation policy: strict mode
359 11:30:19.908030 <5>[ 0.339530] SCSI subsystem initialized
360 11:30:19.909094 <7>[ 0.340329] libata version 3.00 loaded.
361 11:30:19.910409 <6>[ 0.341685] usbcore: registered new interface driver usbfs
362 11:30:19.910629 <6>[ 0.342090] usbcore: registered new interface driver hub
363 11:30:19.911044 <6>[ 0.342421] usbcore: registered new device driver usb
364 11:30:19.913962 <6>[ 0.345257] pps_core: LinuxPPS API ver. 1 registered
365 11:30:19.914094 <6>[ 0.345434] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
366 11:30:19.914425 <6>[ 0.345743] PTP clock support registered
367 11:30:19.914750 <6>[ 0.346284] EDAC MC: Ver: 3.0.0
368 11:30:19.919890 <6>[ 0.351426] FPGA manager framework
369 11:30:19.920888 <6>[ 0.352199] Advanced Linux Sound Architecture Driver Initialized.
370 11:30:19.929427 <6>[ 0.360941] vgaarb: loaded
371 11:30:19.933444 <6>[ 0.364664] clocksource: Switched to clocksource arch_sys_counter
372 11:30:19.934371 <5>[ 0.365863] VFS: Disk quotas dquot_6.6.0
373 11:30:19.934801 <6>[ 0.366152] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
374 11:30:19.936431 <6>[ 0.367605] pnp: PnP ACPI: disabled
375 11:30:19.955209 <6>[ 0.386489] NET: Registered PF_INET protocol family
376 11:30:19.957491 <6>[ 0.388747] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
377 11:30:19.964037 <6>[ 0.395271] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
378 11:30:19.964285 <6>[ 0.395642] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
379 11:30:19.964825 <6>[ 0.395962] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
380 11:30:19.965327 <6>[ 0.396578] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
381 11:30:19.966075 <6>[ 0.397276] TCP: Hash tables configured (established 8192 bind 8192)
382 11:30:19.967573 <6>[ 0.398818] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
383 11:30:19.968068 <6>[ 0.399314] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
384 11:30:19.970104 <6>[ 0.401318] NET: Registered PF_UNIX/PF_LOCAL protocol family
385 11:30:19.973043 <6>[ 0.404303] RPC: Registered named UNIX socket transport module.
386 11:30:19.973466 <6>[ 0.404721] RPC: Registered udp transport module.
387 11:30:19.973624 <6>[ 0.404909] RPC: Registered tcp transport module.
388 11:30:19.973807 <6>[ 0.405106] RPC: Registered tcp NFSv4.1 backchannel transport module.
389 11:30:19.973989 <6>[ 0.405473] PCI: CLS 0 bytes, default 64
390 11:30:19.979448 <6>[ 0.410976] Unpacking initramfs...
391 11:30:19.989448 <6>[ 0.420875] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
392 11:30:19.990403 <6>[ 0.421630] kvm [1]: HYP mode not available
393 11:30:19.998010 <5>[ 0.429475] Initialise system trusted keyrings
394 11:30:19.999717 <6>[ 0.430926] workingset: timestamp_bits=42 max_order=18 bucket_order=0
395 11:30:20.035985 <6>[ 0.467213] squashfs: version 4.0 (2009/01/31) Phillip Lougher
396 11:30:20.046384 <5>[ 0.477848] NFS: Registering the id_resolver key type
397 11:30:20.046858 <5>[ 0.478225] Key type id_resolver registered
398 11:30:20.046991 <5>[ 0.478347] Key type id_legacy registered
399 11:30:20.047388 <6>[ 0.478830] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
400 11:30:20.047805 <6>[ 0.479079] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
401 11:30:20.048421 <6>[ 0.479922] 9p: Installing v9fs 9p2000 file system support
402 11:30:20.114051 <5>[ 0.545508] Key type asymmetric registered
403 11:30:20.114626 <5>[ 0.545681] Asymmetric key parser 'x509' registered
404 11:30:20.114780 <6>[ 0.546113] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
405 11:30:20.114952 <6>[ 0.546475] io scheduler mq-deadline registered
406 11:30:20.115352 <6>[ 0.546700] io scheduler kyber registered
407 11:30:20.177612 <6>[ 0.608903] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
408 11:30:20.188224 <6>[ 0.619314] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
409 11:30:20.193278 <6>[ 0.620260] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
410 11:30:20.193992 <6>[ 0.625175] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
411 11:30:20.194345 <6>[ 0.625509] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
412 11:30:20.194919 <4>[ 0.626251] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
413 11:30:20.196117 <6>[ 0.626926] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
414 11:30:20.201350 <6>[ 0.632797] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
415 11:30:20.201806 <6>[ 0.633198] pci_bus 0000:00: root bus resource [bus 00-ff]
416 11:30:20.202057 <6>[ 0.633434] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
417 11:30:20.202263 <6>[ 0.633640] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
418 11:30:20.202432 <6>[ 0.633827] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
419 11:30:20.204098 <6>[ 0.635353] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
420 11:30:20.211825 <6>[ 0.643081] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
421 11:30:20.212238 <6>[ 0.643516] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
422 11:30:20.212416 <6>[ 0.643706] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
423 11:30:20.212653 <6>[ 0.643976] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
424 11:30:20.212877 <6>[ 0.644262] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
425 11:30:20.217604 <6>[ 0.648857] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
426 11:30:20.217798 <6>[ 0.649109] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
427 11:30:20.217950 <6>[ 0.649315] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
428 11:30:20.218385 <6>[ 0.649613] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
429 11:30:20.221068 <6>[ 0.652340] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
430 11:30:20.225466 <6>[ 0.656732] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
431 11:30:20.225676 <6>[ 0.657106] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
432 11:30:20.226154 <6>[ 0.657370] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
433 11:30:20.226341 <6>[ 0.657638] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
434 11:30:20.226498 <6>[ 0.657892] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
435 11:30:20.226671 <6>[ 0.658118] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
436 11:30:20.242346 <6>[ 0.673615] EINJ: ACPI disabled.
437 11:30:20.323258 <6>[ 0.754650] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
438 11:30:20.329970 <6>[ 0.761429] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
439 11:30:20.357687 <6>[ 0.788731] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
440 11:30:20.370094 <6>[ 0.801355] SuperH (H)SCI(F) driver initialized
441 11:30:20.371566 <6>[ 0.802872] msm_serial: driver initialized
442 11:30:20.380610 <4>[ 0.811741] cacheinfo: Unable to detect cache hierarchy for CPU 0
443 11:30:20.413778 <6>[ 0.845234] loop: module loaded
444 11:30:20.414793 <6>[ 0.846275] virtio_blk virtio1: 1/0/0 default/read/poll queues
445 11:30:20.431480 <5>[ 0.862668] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
446 11:30:20.462964 <6>[ 0.894379] megasas: 07.719.03.00-rc1
447 11:30:20.472926 <5>[ 0.904109] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
448 11:30:20.478685 <6>[ 0.909884] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
449 11:30:20.479194 <6>[ 0.910594] Intel/Sharp Extended Query Table at 0x0031
450 11:30:20.480135 <6>[ 0.911392] Using buffer write method
451 11:30:20.480592 <7>[ 0.911860] erase region 0: offset=0x0,size=0x40000,blocks=256
452 11:30:20.481089 <5>[ 0.912264] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
453 11:30:20.485780 <6>[ 0.916911] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
454 11:30:20.486075 <6>[ 0.917216] Intel/Sharp Extended Query Table at 0x0031
455 11:30:20.486282 <6>[ 0.917776] Using buffer write method
456 11:30:20.486516 <7>[ 0.917946] erase region 0: offset=0x0,size=0x40000,blocks=256
457 11:30:20.486741 <5>[ 0.918204] Concatenating MTD devices:
458 11:30:20.486953 <5>[ 0.918363] (0): \"0.flash\"
459 11:30:20.487142 <5>[ 0.918472] (1): \"0.flash\"
460 11:30:20.487313 <5>[ 0.918583] into device \"0.flash\"
461 11:30:25.217566 <6>[ 5.648866] Freeing initrd memory: 86888K
462 11:30:25.336549 <6>[ 5.767884] tun: Universal TUN/TAP device driver, 1.6
463 11:30:25.345910 <6>[ 5.777389] thunder_xcv, ver 1.0
464 11:30:25.346306 <6>[ 5.777625] thunder_bgx, ver 1.0
465 11:30:25.346435 <6>[ 5.777905] nicpf, ver 1.0
466 11:30:25.350118 <6>[ 5.781363] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
467 11:30:25.350247 <6>[ 5.781605] hns3: Copyright (c) 2017 Huawei Corporation.
468 11:30:25.350682 <6>[ 5.782128] hclge is initializing
469 11:30:25.351195 <6>[ 5.782398] e1000: Intel(R) PRO/1000 Network Driver
470 11:30:25.351398 <6>[ 5.782572] e1000: Copyright (c) 1999-2006 Intel Corporation.
471 11:30:25.351953 <6>[ 5.782906] e1000e: Intel(R) PRO/1000 Network Driver
472 11:30:25.352137 <6>[ 5.783050] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
473 11:30:25.352352 <6>[ 5.783329] igb: Intel(R) Gigabit Ethernet Network Driver
474 11:30:25.352609 <6>[ 5.783532] igb: Copyright (c) 2007-2014 Intel Corporation.
475 11:30:25.352783 <6>[ 5.783816] igbvf: Intel(R) Gigabit Virtual Function Network Driver
476 11:30:25.352959 <6>[ 5.784019] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
477 11:30:25.353765 <6>[ 5.785059] sky2: driver version 1.30
478 11:30:25.356612 <6>[ 5.787859] VFIO - User Level meta-driver version: 0.3
479 11:30:25.365359 <6>[ 5.796301] usbcore: registered new interface driver usb-storage
480 11:30:25.375594 <6>[ 5.806812] rtc-pl031 9010000.pl031: registered as rtc0
481 11:30:25.376572 <6>[ 5.807601] rtc-pl031 9010000.pl031: setting system clock to 2023-06-05T11:30:25 UTC (1685964625)
482 11:30:25.378594 <6>[ 5.809807] i2c_dev: i2c /dev entries driver
483 11:30:25.393420 <6>[ 5.824696] sdhci: Secure Digital Host Controller Interface driver
484 11:30:25.393532 <6>[ 5.824873] sdhci: Copyright(c) Pierre Ossman
485 11:30:25.395568 <6>[ 5.826855] Synopsys Designware Multimedia Card Interface Driver
486 11:30:25.398191 <6>[ 5.829437] sdhci-pltfm: SDHCI platform and OF driver helper
487 11:30:25.402874 <6>[ 5.834095] ledtrig-cpu: registered to indicate activity on CPUs
488 11:30:25.408335 <6>[ 5.839471] usbcore: registered new interface driver usbhid
489 11:30:25.408502 <6>[ 5.839721] usbhid: USB HID core driver
490 11:30:25.424142 <6>[ 5.855353] NET: Registered PF_PACKET protocol family
491 11:30:25.425451 <6>[ 5.856662] 9pnet: Installing 9P2000 support
492 11:30:25.425723 <5>[ 5.857085] Key type dns_resolver registered
493 11:30:25.426979 <6>[ 5.858262] registered taskstats version 1
494 11:30:25.427216 <5>[ 5.858685] Loading compiled-in X.509 certificates
495 11:30:25.448150 <6>[ 5.879386] input: gpio-keys as /devices/platform/gpio-keys/input/input0
496 11:30:25.455045 <6>[ 5.886547] ALSA device list:
497 11:30:25.455550 <6>[ 5.886709] No soundcards found.
498 11:30:25.458178 <6>[ 5.889378] uart-pl011 9000000.pl011: no DMA platform data
499 11:30:25.514937 <6>[ 5.946200] Freeing unused kernel memory: 7552K
500 11:30:25.515717 <6>[ 5.947166] Run /init as init process
501 11:30:25.516104 <7>[ 5.947285] with arguments:
502 11:30:25.516214 <7>[ 5.947411] /init
503 11:30:25.516307 <7>[ 5.947544] verbose
504 11:30:25.516411 <7>[ 5.947654] with environment:
505 11:30:25.516497 <7>[ 5.947808] HOME=/
506 11:30:25.516578 <7>[ 5.947929] TERM=linux
507 11:30:25.638554 <30>[ 6.069440] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
508 11:30:25.639445 <31>[ 6.070886] systemd[1]: No virtualization found in DMI
509 11:30:25.640597 <31>[ 6.071859] systemd[1]: UML virtualization not found in /proc/cpuinfo.
510 11:30:25.640839 <31>[ 6.072211] systemd[1]: No virtualization found in CPUID
511 11:30:25.641676 <31>[ 6.072894] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
512 11:30:25.643002 <31>[ 6.074081] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
513 11:30:25.643211 <31>[ 6.074497] systemd[1]: Found VM virtualization qemu
514 11:30:25.643680 <30>[ 6.074821] systemd[1]: Detected virtualization qemu.
515 11:30:25.643876 <30>[ 6.075164] systemd[1]: Detected architecture arm64.
516 11:30:25.644202 <31>[ 6.075541] systemd[1]: Detected initialized system, this is not the first boot.
517 11:30:25.648277
518 11:30:25.648771 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
519 11:30:25.648924
520 11:30:25.650840 <30>[ 6.082013] systemd[1]: Set hostname to <debian-bullseye-arm64>.
521 11:30:25.669749 <31>[ 6.100803] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
522 11:30:25.670998 <31>[ 6.102111] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
523 11:30:25.671239 <31>[ 6.102605] systemd[1]: Successfully brought loopback interface up
524 11:30:25.676029 <31>[ 6.107213] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
525 11:30:25.687726 <31>[ 6.119074] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
526 11:30:25.688255 <31>[ 6.119384] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
527 11:30:25.727359 <31>[ 6.158379] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
528 11:30:25.728273 <31>[ 6.159713] systemd[1]: Controller 'cpu' supported: yes
529 11:30:25.728738 <31>[ 6.159967] systemd[1]: Controller 'cpuacct' supported: no
530 11:30:25.728864 <31>[ 6.160225] systemd[1]: Controller 'cpuset' supported: yes
531 11:30:25.729587 <31>[ 6.160770] systemd[1]: Controller 'io' supported: yes
532 11:30:25.729724 <31>[ 6.161011] systemd[1]: Controller 'blkio' supported: no
533 11:30:25.729850 <31>[ 6.161263] systemd[1]: Controller 'memory' supported: yes
534 11:30:25.730182 <31>[ 6.161512] systemd[1]: Controller 'devices' supported: no
535 11:30:25.730309 <31>[ 6.161750] systemd[1]: Controller 'pids' supported: yes
536 11:30:25.730637 <31>[ 6.161972] systemd[1]: Controller 'bpf-firewall' supported: yes
537 11:30:25.731009 <31>[ 6.162222] systemd[1]: Controller 'bpf-devices' supported: yes
538 11:30:25.731997 <31>[ 6.163478] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
539 11:30:25.732750 <31>[ 6.163845] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
540 11:30:25.733576 <31>[ 6.164826] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
541 11:30:25.740688 <31>[ 6.171881] systemd[1]: Enabling (yes) showing of status (commandline).
542 11:30:25.748280 <31>[ 6.179505] systemd[1]: Successfully forked off '(sd-executor)' as PID 94.
543 11:30:25.757918 <31>[ 6.189166] systemd[94]: Successfully forked off '(direxec)' as PID 95.
544 11:30:25.759988 <31>[ 6.191258] systemd[94]: Successfully forked off '(direxec)' as PID 96.
545 11:30:25.766407 <31>[ 6.197590] systemd[94]: Successfully forked off '(direxec)' as PID 97.
546 11:30:25.768370 <31>[ 6.199604] systemd[94]: Successfully forked off '(direxec)' as PID 98.
547 11:30:25.786818 <31>[ 6.217952] systemd[94]: Successfully forked off '(direxec)' as PID 99.
548 11:30:25.930541 <31>[ 6.361894] systemd-fstab-generator[96]: Parsing /etc/fstab...
549 11:30:25.932908 <31>[ 6.364063] systemd-fstab-generator[96]: Found entry what=/dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76 where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
550 11:30:25.933892 <31>[ 6.365118] systemd-bless-boot-generator[95]: Skipping generator, not an EFI boot.
551 11:30:25.937609 <31>[ 6.368826] systemd-getty-generator[97]: Automatically adding serial getty for /dev/ttyAMA0.
552 11:30:25.939071 <31>[ 6.370288] systemd-getty-generator[97]: SELinux enabled state cached to: disabled
553 11:30:25.951550 <31>[ 6.382752] systemd-fstab-generator[96]: Checking was requested for /dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76, but fsck.ext4 does not exist.
554 11:30:25.961715 <31>[ 6.392990] systemd-fstab-generator[96]: SELinux enabled state cached to: disabled
555 11:30:25.967836 <31>[ 6.399095] systemd[94]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
556 11:30:25.968337 <31>[ 6.399690] systemd[94]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
557 11:30:25.969111 <31>[ 6.400183] systemd[94]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
558 11:30:25.970933 <31>[ 6.401996] systemd[94]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
559 11:30:25.971782 <31>[ 6.402815] systemd[94]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
560 11:30:25.976194 <31>[ 6.407372] systemd[1]: (sd-executor) succeeded.
561 11:30:25.978570 <31>[ 6.409632] systemd[1]: Looking for unit files in (higher priority first):
562 11:30:25.978825 <31>[ 6.409849] systemd[1]: /etc/systemd/system.control
563 11:30:25.979005 <31>[ 6.409971] systemd[1]: /run/systemd/system.control
564 11:30:25.979225 <31>[ 6.410089] systemd[1]: /run/systemd/transient
565 11:30:25.979424 <31>[ 6.410205] systemd[1]: /run/systemd/generator.early
566 11:30:25.979630 <31>[ 6.410330] systemd[1]: /etc/systemd/system
567 11:30:25.979778 <31>[ 6.410455] systemd[1]: /etc/systemd/system.attached
568 11:30:25.979897 <31>[ 6.410571] systemd[1]: /run/systemd/system
569 11:30:25.980009 <31>[ 6.410672] systemd[1]: /run/systemd/system.attached
570 11:30:25.980151 <31>[ 6.410794] systemd[1]: /run/systemd/generator
571 11:30:25.980272 <31>[ 6.410904] systemd[1]: /usr/local/lib/systemd/system
572 11:30:25.980387 <31>[ 6.411035] systemd[1]: /lib/systemd/system
573 11:30:25.980500 <31>[ 6.411139] systemd[1]: /usr/lib/systemd/system
574 11:30:25.980611 <31>[ 6.411258] systemd[1]: /run/systemd/generator.late
575 11:30:26.022153 <31>[ 6.453549] systemd[1]: Modification times have changed, need to update cache.
576 11:30:26.023851 <31>[ 6.455190] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
577 11:30:26.024991 <31>[ 6.456141] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
578 11:30:26.026188 <31>[ 6.457273] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
579 11:30:26.026677 <31>[ 6.458086] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
580 11:30:26.028112 <31>[ 6.458829] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
581 11:30:26.028313 <31>[ 6.459078] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
582 11:30:26.028508 <31>[ 6.459320] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
583 11:30:26.029010 <31>[ 6.459589] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
584 11:30:26.029166 <31>[ 6.459850] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
585 11:30:26.029307 <31>[ 6.460138] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
586 11:30:26.029829 <31>[ 6.460972] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
587 11:30:26.030703 <31>[ 6.461721] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
588 11:30:26.030911 <31>[ 6.461974] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
589 11:30:26.031103 <31>[ 6.462265] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
590 11:30:26.031703 <31>[ 6.462820] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
591 11:30:26.031911 <31>[ 6.463080] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
592 11:30:26.032153 <31>[ 6.463317] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
593 11:30:26.032390 <31>[ 6.463595] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
594 11:30:26.032551 <31>[ 6.463816] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
595 11:30:26.033035 <31>[ 6.464316] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
596 11:30:26.033878 <31>[ 6.465064] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp.service
597 11:30:26.034355 <31>[ 6.465715] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
598 11:30:26.034610 <31>[ 6.465984] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup-pre.target
599 11:30:26.034844 <31>[ 6.466231] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
600 11:30:26.035428 <31>[ 6.466494] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
601 11:30:26.035625 <31>[ 6.466789] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
602 11:30:26.035832 <31>[ 6.467046] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.service
603 11:30:26.036318 <31>[ 6.467586] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
604 11:30:26.037178 <31>[ 6.468200] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
605 11:30:26.037762 <31>[ 6.469003] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
606 11:30:26.037996 <31>[ 6.469273] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
607 11:30:26.038546 <31>[ 6.469682] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
608 11:30:26.038748 <31>[ 6.469952] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
609 11:30:26.038944 <31>[ 6.470181] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
610 11:30:26.039529 <31>[ 6.470411] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
611 11:30:26.039727 <31>[ 6.470661] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
612 11:30:26.039883 <31>[ 6.470900] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-device.target
613 11:30:26.040084 <31>[ 6.471133] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-parse-etc.service
614 11:30:26.040254 <31>[ 6.471380] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
615 11:30:26.040448 <31>[ 6.471607] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
616 11:30:26.040649 <31>[ 6.471835] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
617 11:30:26.040806 <31>[ 6.472061] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
618 11:30:26.041010 <31>[ 6.472294] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
619 11:30:26.041555 <31>[ 6.472798] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
620 11:30:26.041758 <31>[ 6.473050] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
621 11:30:26.042596 <31>[ 6.473754] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
622 11:30:26.042819 <31>[ 6.474087] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
623 11:30:26.043360 <31>[ 6.474664] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel2.target → multi-user.target
624 11:30:26.043588 <31>[ 6.474943] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
625 11:30:26.044155 <31>[ 6.475275] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend.target
626 11:30:26.044347 <31>[ 6.475499] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
627 11:30:26.044550 <31>[ 6.475728] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysusers.service
628 11:30:26.045091 <31>[ 6.476264] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
629 11:30:26.045656 <31>[ 6.476988] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
630 11:30:26.045896 <31>[ 6.477297] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
631 11:30:26.046425 <31>[ 6.477570] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
632 11:30:26.046923 <31>[ 6.478209] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
633 11:30:26.047529 <31>[ 6.478579] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
634 11:30:26.047705 <31>[ 6.478881] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
635 11:30:26.048308 <31>[ 6.479393] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
636 11:30:26.048529 <31>[ 6.479654] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
637 11:30:26.048746 <31>[ 6.479919] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-lookup.target
638 11:30:26.048884 <31>[ 6.480154] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/umount.target
639 11:30:26.049401 <31>[ 6.480745] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
640 11:30:26.049975 <31>[ 6.481099] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-tracing.mount
641 11:30:26.050191 <31>[ 6.481341] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.socket
642 11:30:26.050432 <31>[ 6.481635] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
643 11:30:26.050646 <31>[ 6.481895] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
644 11:30:26.050915 <31>[ 6.482129] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
645 11:30:26.051152 <31>[ 6.482346] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-online.target
646 11:30:26.051382 <31>[ 6.482594] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
647 11:30:26.051612 <31>[ 6.482869] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hybrid-sleep.service
648 11:30:26.051824 <31>[ 6.483121] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
649 11:30:26.052052 <31>[ 6.483358] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
650 11:30:26.052756 <31>[ 6.483893] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
651 11:30:26.052915 <31>[ 6.484135] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
652 11:30:26.053691 <31>[ 6.484394] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
653 11:30:26.054180 <31>[ 6.485529] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
654 11:30:26.054771 <31>[ 6.485855] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
655 11:30:26.055007 <31>[ 6.486154] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
656 11:30:26.055211 <31>[ 6.486516] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
657 11:30:26.055688 <31>[ 6.486934] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
658 11:30:26.056176 <31>[ 6.487515] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.locale1.service → systemd-localed.service
659 11:30:26.056421 <31>[ 6.487844] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
660 11:30:26.056914 <31>[ 6.488121] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
661 11:30:26.057781 <31>[ 6.488807] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
662 11:30:26.057985 <31>[ 6.489193] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
663 11:30:26.058181 <31>[ 6.489479] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
664 11:30:26.058416 <31>[ 6.489768] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
665 11:30:26.058989 <31>[ 6.490049] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsck-root.service
666 11:30:26.059184 <31>[ 6.490348] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-quotacheck.service
667 11:30:26.059427 <31>[ 6.490628] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
668 11:30:26.059676 <31>[ 6.490932] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
669 11:30:26.059930 <31>[ 6.491208] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
670 11:30:26.060163 <31>[ 6.491521] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
671 11:30:26.060363 <31>[ 6.491765] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
672 11:30:26.060857 <31>[ 6.492006] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
673 11:30:26.061381 <31>[ 6.492731] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-varlink@.socket
674 11:30:26.061926 <31>[ 6.493032] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
675 11:30:26.062128 <31>[ 6.493303] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
676 11:30:26.062954 <31>[ 6.494145] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.hostname1.service → systemd-hostnamed.service
677 11:30:26.063180 <31>[ 6.494438] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
678 11:30:26.063387 <31>[ 6.494674] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
679 11:30:26.063580 <31>[ 6.494924] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
680 11:30:26.063803 <31>[ 6.495184] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user-runtime-dir@.service
681 11:30:26.064379 <31>[ 6.495457] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kmod-static-nodes.service
682 11:30:26.064579 <31>[ 6.495704] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-logind.service
683 11:30:26.064772 <31>[ 6.495952] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
684 11:30:26.064928 <31>[ 6.496222] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-bless-boot.service
685 11:30:26.065532 <31>[ 6.496912] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
686 11:30:26.066106 <31>[ 6.497217] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
687 11:30:26.066324 <31>[ 6.497494] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-pre.target
688 11:30:26.066558 <31>[ 6.497724] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
689 11:30:26.066731 <31>[ 6.497965] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
690 11:30:26.066918 <31>[ 6.498222] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
691 11:30:26.067102 <31>[ 6.498463] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
692 11:30:26.067290 <31>[ 6.498700] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
693 11:30:26.067875 <31>[ 6.498945] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.service
694 11:30:26.068114 <31>[ 6.499197] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-cleanup.service
695 11:30:26.068356 <31>[ 6.499462] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/basic.target
696 11:30:26.068592 <31>[ 6.499703] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
697 11:30:26.068850 <31>[ 6.499960] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
698 11:30:26.069030 <31>[ 6.500230] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
699 11:30:26.069289 <31>[ 6.500666] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-kernel.socket
700 11:30:26.069831 <31>[ 6.500974] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
701 11:30:26.070067 <31>[ 6.501243] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
702 11:30:26.070271 <31>[ 6.501507] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/serial-getty@.service
703 11:30:26.070469 <31>[ 6.501757] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
704 11:30:26.070657 <31>[ 6.502002] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
705 11:30:26.070841 <31>[ 6.502241] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sockets.target
706 11:30:26.071366 <31>[ 6.502714] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks.service → /dev/null
707 11:30:26.071585 <31>[ 6.502999] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
708 11:30:26.072442 <31>[ 6.503622] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
709 11:30:26.072669 <31>[ 6.503913] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
710 11:30:26.072856 <31>[ 6.504139] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate.service
711 11:30:26.073369 <31>[ 6.504693] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
712 11:30:26.073859 <31>[ 6.505084] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
713 11:30:26.074104 <31>[ 6.505326] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
714 11:30:26.074329 <31>[ 6.505569] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
715 11:30:26.074543 <31>[ 6.505844] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sound.target
716 11:30:26.074735 <31>[ 6.506080] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
717 11:30:26.074915 <31>[ 6.506310] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
718 11:30:26.075463 <31>[ 6.506562] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
719 11:30:26.075663 <31>[ 6.506985] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
720 11:30:26.076195 <31>[ 6.507387] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
721 11:30:26.076461 <31>[ 6.507646] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
722 11:30:26.076658 <31>[ 6.507866] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
723 11:30:26.076944 <31>[ 6.508108] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
724 11:30:26.077146 <31>[ 6.508340] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/boot-complete.target
725 11:30:26.077742 <31>[ 6.509015] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
726 11:30:26.078274 <31>[ 6.509269] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
727 11:30:26.493347 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
728 11:30:26.498066 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
729 11:30:26.501543 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
730 11:30:26.504621 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
731 11:30:26.508118 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
732 11:30:26.509994 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
733 11:30:26.512151 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
734 11:30:26.513660 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
735 11:30:26.514480 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
736 11:30:26.515002 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
737 11:30:26.516056 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
738 11:30:26.519874 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
739 11:30:26.524149 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
740 11:30:26.527133 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
741 11:30:26.529755 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
742 11:30:26.532037 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
743 11:30:26.534946 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
744 11:30:26.536807 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
745 11:30:26.562959 Mounting [0;1;39mHuge Pages File System[0m...
746 11:30:26.598445 Mounting [0;1;39mPOSIX Message Queue File System[0m...
747 11:30:26.645471 Mounting [0;1;39mKernel Debug File System[0m...
748 11:30:26.683704 Starting [0;1;39mLoad Kernel Module configfs[0m...
749 11:30:26.726887 Starting [0;1;39mLoad Kernel Module drm[0m...
750 11:30:26.790655 Starting [0;1;39mJournal Service[0m...
751 11:30:26.822730 Starting [0;1;39mLoad Kernel Modules[0m...
752 11:30:26.854596 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
753 11:30:26.902708 Starting [0;1;39mColdplug All udev Devices[0m...
754 11:30:27.018019 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
755 11:30:27.024160 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
756 11:30:27.039244 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
757 11:30:27.082560 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
758 11:30:27.135151 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
759 11:30:27.162453 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
760 11:30:27.234807 Mounting [0;1;39mKernel Configuration File System[0m...
761 11:30:27.357576 Starting [0;1;39mApply Kernel Variables[0m...
762 11:30:27.411427 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
763 11:30:27.468355 <47>[ 7.899639] systemd-journald[105]: SELinux enabled state cached to: disabled
764 11:30:27.487201 <47>[ 7.918295] systemd-journald[105]: Auditing in kernel turned off.
765 11:30:27.504052 <47>[ 7.935104] systemd-journald[105]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
766 11:30:27.560386 <47>[ 7.991387] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
767 11:30:27.563609 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
768 11:30:27.564470 See 'systemctl status systemd-remount-fs.service' for details.
769 11:30:27.571320 <47>[ 8.002433] systemd-journald[105]: Fixed min_use=3.8M max_use=19.4M max_size=2.4M min_size=512.0K keep_free=9.7M n_max_files=100
770 11:30:27.572802 <47>[ 8.004037] systemd-journald[105]: Reserving 333 entries in field hash table.
771 11:30:27.579414 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
772 11:30:27.604384 <47>[ 8.035724] systemd-journald[105]: Reserving 4437 entries in data hash table.
773 11:30:27.611110 <47>[ 8.042335] systemd-journald[105]: Vacuuming...
774 11:30:27.611754 <47>[ 8.042978] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
775 11:30:27.612358 <47>[ 8.043651] systemd-journald[105]: Flushing /dev/kmsg...
776 11:30:27.615291 Starting [0;1;39mLoad/Save Random Seed[0m...
777 11:30:27.678741 Starting [0;1;39mCreate System Users[0m...
778 11:30:27.822133 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
779 11:30:27.986998 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
780 11:30:28.026758 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
781 11:30:28.149770 <47>[ 8.580826] systemd-journald[105]: systemd-journald running as PID 105 for the system.
782 11:30:28.163655 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
783 11:30:28.173459 <47>[ 8.604821] systemd-journald[105]: Sent READY=1 notification.
784 11:30:28.174001 <47>[ 8.605287] systemd-journald[105]: Sent WATCHDOG=1 notification.
785 11:30:28.204310 <47>[ 8.635403] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
786 11:30:28.222985 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
787 11:30:28.234754 <47>[ 8.665976] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
788 11:30:28.236963 <47>[ 8.668245] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
789 11:30:28.265595 <47>[ 8.696700] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
790 11:30:28.281625 <47>[ 8.712769] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
791 11:30:28.286337 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
792 11:30:28.290568 <47>[ 8.721699] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
793 11:30:28.292803 <47>[ 8.724034] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
794 11:30:28.296280 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
795 11:30:28.306185 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
796 11:30:28.325014 <47>[ 8.756091] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
797 11:30:28.339828 <47>[ 8.770941] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
798 11:30:28.354004 <47>[ 8.785167] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
799 11:30:28.355873 <47>[ 8.787132] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
800 11:30:28.370056 <47>[ 8.801222] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
801 11:30:28.372270 <47>[ 8.803544] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
802 11:30:28.386441 <47>[ 8.817587] systemd-journald[105]: n/a: New incoming connection.
803 11:30:28.387040 <47>[ 8.818228] systemd-journald[105]: varlink-21: varlink: setting state idle-server
804 11:30:28.398841 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
805 11:30:28.411610 <47>[ 8.842774] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
806 11:30:28.412349 <47>[ 8.843412] systemd-journald[105]: varlink-21: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
807 11:30:28.423194 <47>[ 8.854279] systemd-journald[105]: varlink-21: varlink: changing state idle-server → processing-method
808 11:30:28.423441 <46>[ 8.854626] systemd-journald[105]: Received client request to flush runtime journal.
809 11:30:28.423963 <47>[ 8.855061] systemd-journald[105]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
810 11:30:28.424504 <47>[ 8.855938] systemd-journald[105]: Vacuuming...
811 11:30:28.429474 <47>[ 8.860630] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
812 11:30:28.430731 <47>[ 8.861993] systemd-journald[105]: varlink-21: Sending message: {\"parameters\":{}}
813 11:30:28.430885 <47>[ 8.862258] systemd-journald[105]: varlink-21: varlink: changing state processing-method → processed-method
814 11:30:28.431487 <47>[ 8.862699] systemd-journald[105]: varlink-21: varlink: changing state processed-method → idle-server
815 11:30:28.447813 <47>[ 8.878925] systemd-journald[105]: varlink-21: varlink: changing state idle-server → pending-disconnect
816 11:30:28.448062 <47>[ 8.879332] systemd-journald[105]: varlink-21: varlink: changing state pending-disconnect → processing-disconnect
817 11:30:28.448287 <47>[ 8.879658] systemd-journald[105]: varlink-21: varlink: changing state processing-disconnect → disconnected
818 11:30:28.464561 <47>[ 8.895783] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
819 11:30:28.466336 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
820 11:30:28.522981 Starting [0;1;39mCreate Volatile Files and Directories[0m...
821 11:30:28.540630 <47>[ 8.971714] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
822 11:30:28.937785 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
823 11:30:29.019180 Starting [0;1;39mNetwork Service[0m...
824 11:30:29.053634 <47>[ 9.484756] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
825 11:30:29.062364 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
826 11:30:29.147030 Starting [0;1;39mNetwork Time Synchronization[0m...
827 11:30:29.167449 <47>[ 9.598585] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
828 11:30:29.199076 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
829 11:30:29.215504 <47>[ 9.646661] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
830 11:30:29.662770 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
831 11:30:30.744102 <47>[ 11.174990] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3328 of 4437 items, 2555904 file size, 768 bytes per hash table item), suggesting rotation.
832 11:30:30.744425 <47>[ 11.175574] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
833 11:30:30.744563 <47>[ 11.175945] systemd-journald[105]: Rotating...
834 11:30:30.760735 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
835 11:30:30.763821 <47>[ 11.194998] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
836 11:30:30.765110 <47>[ 11.196348] systemd-journald[105]: Reserving 333 entries in field hash table.
837 11:30:30.808273 <47>[ 11.239423] systemd-journald[105]: Reserving 4437 entries in data hash table.
838 11:30:30.827280 <47>[ 11.258689] systemd-journald[105]: Vacuuming...
839 11:30:30.859967 <47>[ 11.260381] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
840 11:30:30.883456 Starting [0;1;39mNetwork Name Resolution[0m...
841 11:30:30.905485 <47>[ 11.336640] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
842 11:30:31.067604 <47>[ 11.498702] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
843 11:30:31.254568 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
844 11:30:31.256661 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
845 11:30:31.259028 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
846 11:30:32.376162 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
847 11:30:32.380307 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
848 11:30:32.409050 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
849 11:30:32.430682 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
850 11:30:32.441524 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
851 11:30:32.447677 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
852 11:30:32.478397 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
853 11:30:32.478940 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
854 11:30:32.479757 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
855 11:30:32.546676 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
856 11:30:32.563410 <47>[ 12.994518] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
857 11:30:32.702642 <47>[ 13.133665] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
858 11:30:32.703272 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
859 11:30:32.915597 Starting [0;1;39mUser Login Management[0m...
860 11:30:32.925060 <47>[ 13.356230] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
861 11:30:33.452731 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
862 11:30:33.454602 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
863 11:30:33.456520 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
864 11:30:33.516699 Starting [0;1;39mPermit User Sessions[0m...
865 11:30:33.561955 <47>[ 13.993099] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
866 11:30:33.771512 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
867 11:30:33.868236 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
868 11:30:33.972175 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
869 11:30:34.284914 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
870 11:30:36.290524 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
871 11:30:36.380374 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
872 11:30:36.404063 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
873 11:30:36.415521 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
874 11:30:36.428705 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
875 11:30:36.466324 <47>[ 16.897462] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
876 11:30:36.484172 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
877 11:30:36.689791 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
878 11:30:36.734644 <47>[ 17.165766] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
879 11:30:36.735452 <47>[ 17.166653] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
880 11:30:36.770450 <6>[ 17.201866] virtio_net virtio0 enp0s1: renamed from eth0
881 11:30:36.816631
882 11:30:36.817081 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
883 11:30:36.817267
884 11:30:36.817431 debian-bullseye-arm64 login: root (automatic login)
885 11:30:36.817589
886 11:30:37.094139 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 11:10:42 UTC 2023 aarch64
887 11:30:37.094771
888 11:30:37.095023 The programs included with the Debian GNU/Linux system are free software;
889 11:30:37.095232 the exact distribution terms for each program are described in the
890 11:30:37.095414 individual files in /usr/share/doc/*/copyright.
891 11:30:37.095545
892 11:30:37.095666 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
893 11:30:37.095786 permitted by applicable law.
894 11:30:37.614770 <47>[ 18.046069] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
895 11:30:37.727117 <47>[ 18.158098] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3328 of 4437 items, 2555904 file size, 768 bytes per hash table item), suggesting rotation.
896 11:30:37.727458 <47>[ 18.158701] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
897 11:30:37.727654 <47>[ 18.159132] systemd-journald[105]: Rotating...
898 11:30:37.741296 <47>[ 18.172670] systemd-journald[105]: Reserving 333 entries in field hash table.
899 11:30:37.787800 <47>[ 18.219187] systemd-journald[105]: Reserving 4437 entries in data hash table.
900 11:30:37.795333 <47>[ 18.226784] systemd-journald[105]: Vacuuming...
901 11:30:37.796733 <47>[ 18.227931] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
902 11:30:37.879812 <47>[ 18.310850] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
903 11:30:39.693771 <47>[ 20.124754] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
904 11:30:40.073296 Matched prompt #10: / #
906 11:30:40.073925 Setting prompt string to ['/ #']
907 11:30:40.074125 end: 2.2.1 login-action (duration 00:00:21) [common]
909 11:30:40.074581 end: 2.2 auto-login-action (duration 00:00:25) [common]
910 11:30:40.074772 start: 2.3 expect-shell-connection (timeout 00:04:33) [common]
911 11:30:40.074926 Setting prompt string to ['/ #']
912 11:30:40.075061 Forcing a shell prompt, looking for ['/ #']
914 11:30:40.125627 / #
915 11:30:40.125888 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
916 11:30:40.126074 Waiting using forced prompt support (timeout 00:02:30)
917 11:30:40.128245
918 11:30:40.136583 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
919 11:30:40.136779 start: 2.4 export-device-env (timeout 00:04:33) [common]
920 11:30:40.136953 end: 2.4 export-device-env (duration 00:00:00) [common]
921 11:30:40.137113 end: 2 boot-image-retry (duration 00:00:27) [common]
922 11:30:40.137273 start: 3 lava-test-retry (timeout 00:08:42) [common]
923 11:30:40.137431 start: 3.1 lava-test-shell (timeout 00:08:42) [common]
924 11:30:40.137571 Using namespace: common
926 11:30:40.238431 / # #
927 11:30:40.238711 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
928 11:30:40.239455 #
930 11:30:40.348038 / # mkdir /lava-562716
931 11:30:40.348927 mkdir /lava-562716
933 11:30:40.464416 / # mount /dev/disk/by-uuid/8b51171b-9133-410c-aea3-800901777e99 -t ext2 /lava-562716
934 11:30:40.465192 mount /dev/disk/by-uuid/8b51171b-9133-410c-aea3-800901777e99 -t ext2 /lava-562716
935 11:30:40.509263 <4>[ 20.940179] ext2 filesystem being mounted at /lava-562716 supports timestamps until 2038 (0x7fffffff)
937 11:30:40.649256 / # ls -la /lava-562716/bin/lava-test-runner
938 11:30:40.650144 ls -la /lava-562716/bin/lava-test-runner
939 11:30:40.687941 -rwxr-xr-x 1 root root 1039 Jun 5 11:29 /lava-562716/bin/lava-test-runner
940 11:30:40.698962 Using /lava-562716
942 11:30:40.799899 / # export SHELL=/bin/sh
943 11:30:40.800834 export SHELL=/bin/sh
945 11:30:40.909116 / # . /lava-562716/environment
946 11:30:40.909909 . /lava-562716/environment
948 11:30:41.020734 / # /lava-562716/bin/lava-test-runner /lava-562716/0
949 11:30:41.021038 Test shell timeout: 10s (minimum of the action and connection timeout)
950 11:30:41.021908 /lava-562716/bin/lava-test-runner /lava-562716/0
951 11:30:41.165965 + export TESTRUN_ID=0_timesync-off
952 11:30:41.166272 + cd /lava-562716/0/tests/0_timesync-off
953 11:30:41.167949 + cat uuid
954 11:30:41.176226 + UUID=562716_1.1.3.1
955 11:30:41.176475 + set +x
956 11:30:41.176993 <LAVA_SIGNAL_STARTRUN 0_timesync-off 562716_1.1.3.1>
957 11:30:41.177114 + systemctl stop systemd-timesyncd
958 11:30:41.177399 Received signal: <STARTRUN> 0_timesync-off 562716_1.1.3.1
959 11:30:41.177513 Starting test lava.0_timesync-off (562716_1.1.3.1)
960 11:30:41.177643 Skipping test definition patterns.
961 11:30:41.420835 + set +x
962 11:30:41.421241 <LAVA_SIGNAL_ENDRUN 0_timesync-off 562716_1.1.3.1>
963 11:30:41.421493 Received signal: <ENDRUN> 0_timesync-off 562716_1.1.3.1
964 11:30:41.421578 Ending use of test pattern.
965 11:30:41.421642 Ending test lava.0_timesync-off (562716_1.1.3.1), duration 0.24
967 11:30:41.468231 + export TESTRUN_ID=1_kselftest-arm64_qemu
968 11:30:41.468514 + cd /lava-562716/0/tests/1_kselftest-arm64_qemu
969 11:30:41.470464 + cat uuid
970 11:30:41.478209 + UUID=562716_1.1.3.5
971 11:30:41.478406 + set +x
972 11:30:41.478590 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 562716_1.1.3.5>
973 11:30:41.478716 + cd ./automated/linux/kselftest/
974 11:30:41.479039 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 562716_1.1.3.5
975 11:30:41.479206 Starting test lava.1_kselftest-arm64_qemu (562716_1.1.3.5)
976 11:30:41.479421 Skipping test definition patterns.
977 11:30:41.482697 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip -e -p /opt/kselftests/mainline/ -n 1 -i 1
978 11:30:41.572905 INFO: install_deps skipped
979 11:30:41.605288 --2023-06-05 11:30:41-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig/gcc-10/kselftest.tar.xz
980 11:30:41.653034 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
981 11:30:41.851521 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
982 11:30:42.044007 HTTP request sent, awaiting response... 200 OK
983 11:30:42.047118 Length: 2711004 (2.6M) [application/octet-stream]
984 11:30:42.048566 Saving to: 'kselftest.tar.xz'
985 11:30:42.049768
986 11:30:43.336723 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 148KB/s kselftest.tar.xz 8%[> ] 219.84K 318KB/s kselftest.tar.xz 33%[=====> ] 898.59K 862KB/s kselftest.tar.xz 73%[=============> ] 1.90M 1.53MB/s kselftest.tar.xz 100%[===================>] 2.58M 2.04MB/s in 1.3s
987 11:30:43.337040
988 11:30:43.341660 2023-06-05 11:30:43 (2.04 MB/s) - 'kselftest.tar.xz' saved [2711004/2711004]
989 11:30:43.341919
990 11:30:46.855731 skiplist:
991 11:30:46.856154 ========================================
992 11:30:46.856880 ========================================
993 11:30:46.912347 arm64:tags_test
994 11:30:46.912580 arm64:run_tags_test.sh
995 11:30:46.912677 arm64:fake_sigreturn_bad_magic
996 11:30:46.912971 arm64:fake_sigreturn_bad_size
997 11:30:46.913082 arm64:fake_sigreturn_bad_size_for_magic0
998 11:30:46.913176 arm64:fake_sigreturn_duplicated_fpsimd
999 11:30:46.913259 arm64:fake_sigreturn_misaligned_sp
1000 11:30:46.913342 arm64:fake_sigreturn_missing_fpsimd
1001 11:30:46.913420 arm64:fake_sigreturn_sme_change_vl
1002 11:30:46.913500 arm64:fake_sigreturn_sve_change_vl
1003 11:30:46.913577 arm64:mangle_pstate_invalid_compat_toggle
1004 11:30:46.913688 arm64:mangle_pstate_invalid_daif_bits
1005 11:30:46.913783 arm64:mangle_pstate_invalid_mode_el1h
1006 11:30:46.913875 arm64:mangle_pstate_invalid_mode_el1t
1007 11:30:46.913963 arm64:mangle_pstate_invalid_mode_el2h
1008 11:30:46.914051 arm64:mangle_pstate_invalid_mode_el2t
1009 11:30:46.914159 arm64:mangle_pstate_invalid_mode_el3h
1010 11:30:46.914251 arm64:mangle_pstate_invalid_mode_el3t
1011 11:30:46.914336 arm64:sme_trap_no_sm
1012 11:30:46.914413 arm64:sme_trap_non_streaming
1013 11:30:46.914490 arm64:sme_trap_za
1014 11:30:46.914565 arm64:sme_vl
1015 11:30:46.914640 arm64:ssve_regs
1016 11:30:46.914720 arm64:sve_regs
1017 11:30:46.914806 arm64:sve_vl
1018 11:30:46.914893 arm64:za_no_regs
1019 11:30:46.914981 arm64:za_regs
1020 11:30:46.915067 arm64:pac
1021 11:30:46.915175 arm64:fp-stress
1022 11:30:46.915266 arm64:sve-ptrace
1023 11:30:46.915355 arm64:sve-probe-vls
1024 11:30:46.915443 arm64:vec-syscfg
1025 11:30:46.915530 arm64:za-fork
1026 11:30:46.915608 arm64:za-ptrace
1027 11:30:46.915683 arm64:check_buffer_fill
1028 11:30:46.915758 arm64:check_child_memory
1029 11:30:46.915834 arm64:check_gcr_el1_cswitch
1030 11:30:46.915918 arm64:check_ksm_options
1031 11:30:46.915997 arm64:check_mmap_options
1032 11:30:46.916080 arm64:check_prctl
1033 11:30:46.916165 arm64:check_tags_inclusion
1034 11:30:46.916251 arm64:check_user_mem
1035 11:30:46.916337 arm64:btitest
1036 11:30:46.916423 arm64:nobtitest
1037 11:30:46.916516 arm64:hwcap
1038 11:30:46.916603 arm64:ptrace
1039 11:30:46.916691 arm64:syscall-abi
1040 11:30:46.916778 arm64:tpidr2
1041 11:30:46.927394 ============== Tests to run ===============
1042 11:30:46.932161 arm64:tags_test
1043 11:30:46.932381 arm64:run_tags_test.sh
1044 11:30:46.932568 arm64:fake_sigreturn_bad_magic
1045 11:30:46.932934 arm64:fake_sigreturn_bad_size
1046 11:30:46.933047 arm64:fake_sigreturn_bad_size_for_magic0
1047 11:30:46.933139 arm64:fake_sigreturn_duplicated_fpsimd
1048 11:30:46.933227 arm64:fake_sigreturn_misaligned_sp
1049 11:30:46.933313 arm64:fake_sigreturn_missing_fpsimd
1050 11:30:46.933401 arm64:fake_sigreturn_sme_change_vl
1051 11:30:46.933488 arm64:fake_sigreturn_sve_change_vl
1052 11:30:46.933570 arm64:mangle_pstate_invalid_compat_toggle
1053 11:30:46.933653 arm64:mangle_pstate_invalid_daif_bits
1054 11:30:46.933730 arm64:mangle_pstate_invalid_mode_el1h
1055 11:30:46.933806 arm64:mangle_pstate_invalid_mode_el1t
1056 11:30:46.933901 arm64:mangle_pstate_invalid_mode_el2h
1057 11:30:46.933989 arm64:mangle_pstate_invalid_mode_el2t
1058 11:30:46.934076 arm64:mangle_pstate_invalid_mode_el3h
1059 11:30:46.934163 arm64:mangle_pstate_invalid_mode_el3t
1060 11:30:46.934251 arm64:sme_trap_no_sm
1061 11:30:46.934356 arm64:sme_trap_non_streaming
1062 11:30:46.934449 arm64:sme_trap_za
1063 11:30:46.934538 arm64:sme_vl
1064 11:30:46.934624 arm64:ssve_regs
1065 11:30:46.934711 arm64:sve_regs
1066 11:30:46.934797 arm64:sve_vl
1067 11:30:46.934882 arm64:za_no_regs
1068 11:30:46.934969 arm64:za_regs
1069 11:30:46.935055 arm64:pac
1070 11:30:46.935143 arm64:fp-stress
1071 11:30:46.935229 arm64:sve-ptrace
1072 11:30:46.935336 arm64:sve-probe-vls
1073 11:30:46.935421 arm64:vec-syscfg
1074 11:30:46.935501 arm64:za-fork
1075 11:30:46.935576 arm64:za-ptrace
1076 11:30:46.935656 arm64:check_buffer_fill
1077 11:30:46.935741 arm64:check_child_memory
1078 11:30:46.935827 arm64:check_gcr_el1_cswitch
1079 11:30:46.935912 arm64:check_ksm_options
1080 11:30:46.935999 arm64:check_mmap_options
1081 11:30:46.936083 arm64:check_prctl
1082 11:30:46.936167 arm64:check_tags_inclusion
1083 11:30:46.936254 arm64:check_user_mem
1084 11:30:46.936340 arm64:btitest
1085 11:30:46.936425 arm64:nobtitest
1086 11:30:46.936516 arm64:hwcap
1087 11:30:46.936605 arm64:ptrace
1088 11:30:46.936692 arm64:syscall-abi
1089 11:30:46.936779 arm64:tpidr2
1090 11:30:46.936885 ===========End Tests to run ===============
1091 11:30:47.966113 <12>[ 28.397432] kselftest: Running tests in arm64
1092 11:30:48.001393 TAP version 13
1093 11:30:48.024369 1..48
1094 11:30:48.080461 # selftests: arm64: tags_test
1095 11:30:48.138023 ok 1 selftests: arm64: tags_test
1096 11:30:48.193484 # selftests: arm64: run_tags_test.sh
1097 11:30:48.252118 # --------------------
1098 11:30:48.252391 # running tags test
1099 11:30:48.252532 # --------------------
1100 11:30:48.252659 # [PASS]
1101 11:30:48.257711 ok 2 selftests: arm64: run_tags_test.sh
1102 11:30:48.313100 # selftests: arm64: fake_sigreturn_bad_magic
1103 11:30:48.371349 # Registered handlers for all signals.
1104 11:30:48.371942 # Detected MINSTKSIGSZ:10000
1105 11:30:48.372157 # Testcase initialized.
1106 11:30:48.372337 # uc context validated.
1107 11:30:48.372505 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1108 11:30:48.372668 # Handled SIG_COPYCTX
1109 11:30:48.372832 # Available space:3536
1110 11:30:48.372995 # Using badly built context - ERR: BAD MAGIC !
1111 11:30:48.373195 # SIG_OK -- SP:0xFFFFEECEC230 si_addr@:0xffffeecec230 si_code:2 token@:0xffffeeceafd0 offset:-4704
1112 11:30:48.373368 # ==>> completed. PASS(1)
1113 11:30:48.373532 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1114 11:30:48.373711 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEECEAFD0
1115 11:30:48.381723 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1116 11:30:48.458213 # selftests: arm64: fake_sigreturn_bad_size
1117 11:30:48.518843 # Registered handlers for all signals.
1118 11:30:48.519065 # Detected MINSTKSIGSZ:10000
1119 11:30:48.519175 # Testcase initialized.
1120 11:30:48.519498 # uc context validated.
1121 11:30:48.519610 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1122 11:30:48.519701 # Handled SIG_COPYCTX
1123 11:30:48.519787 # Available space:3536
1124 11:30:48.519870 # uc context validated.
1125 11:30:48.519953 # Using badly built context - ERR: Bad size for esr_context
1126 11:30:48.520053 # SIG_OK -- SP:0xFFFFCAAE3AD0 si_addr@:0xffffcaae3ad0 si_code:2 token@:0xffffcaae2870 offset:-4704
1127 11:30:48.520142 # ==>> completed. PASS(1)
1128 11:30:48.520227 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1129 11:30:48.520311 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCAAE2870
1130 11:30:48.530183 ok 4 selftests: arm64: fake_sigreturn_bad_size
1131 11:30:48.595556 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1132 11:30:48.659624 # Registered handlers for all signals.
1133 11:30:48.659885 # Detected MINSTKSIGSZ:10000
1134 11:30:48.660328 # Testcase initialized.
1135 11:30:48.660440 # uc context validated.
1136 11:30:48.660535 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1137 11:30:48.660625 # Handled SIG_COPYCTX
1138 11:30:48.660715 # Available space:3536
1139 11:30:48.660805 # Using badly built context - ERR: Bad size for terminator
1140 11:30:48.661142 # SIG_OK -- SP:0xFFFFF1A20CE0 si_addr@:0xfffff1a20ce0 si_code:2 token@:0xfffff1a1fa80 offset:-4704
1141 11:30:48.661246 # ==>> completed. PASS(1)
1142 11:30:48.661332 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1143 11:30:48.661417 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF1A1FA80
1144 11:30:48.670577 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1145 11:30:48.720320 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1146 11:30:48.778528 # Registered handlers for all signals.
1147 11:30:48.779042 # Detected MINSTKSIGSZ:10000
1148 11:30:48.779269 # Testcase initialized.
1149 11:30:48.779485 # uc context validated.
1150 11:30:48.779700 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1151 11:30:48.779915 # Handled SIG_COPYCTX
1152 11:30:48.780129 # Available space:3536
1153 11:30:48.780384 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1154 11:30:48.780592 # SIG_OK -- SP:0xFFFFC8940D60 si_addr@:0xffffc8940d60 si_code:2 token@:0xffffc893fb00 offset:-4704
1155 11:30:48.780811 # ==>> completed. PASS(1)
1156 11:30:48.781024 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1157 11:30:48.789725 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC893FB00
1158 11:30:48.790231 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1159 11:30:48.854280 # selftests: arm64: fake_sigreturn_misaligned_sp
1160 11:30:48.911364 # Registered handlers for all signals.
1161 11:30:48.911628 # Detected MINSTKSIGSZ:10000
1162 11:30:48.911956 # Testcase initialized.
1163 11:30:48.912071 # uc context validated.
1164 11:30:48.912171 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1165 11:30:48.912259 # Handled SIG_COPYCTX
1166 11:30:48.912334 # SIG_OK -- SP:0xFFFFE44DA5D3 si_addr@:0xffffe44da5d3 si_code:2 token@:0xffffe44da5d3 offset:0
1167 11:30:48.912402 # ==>> completed. PASS(1)
1168 11:30:48.912492 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1169 11:30:48.912569 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE44DA5D3
1170 11:30:48.921484 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1171 11:30:48.970925 # selftests: arm64: fake_sigreturn_missing_fpsimd
1172 11:30:49.033584 # Registered handlers for all signals.
1173 11:30:49.033919 # Detected MINSTKSIGSZ:10000
1174 11:30:49.034108 # Testcase initialized.
1175 11:30:49.034532 # uc context validated.
1176 11:30:49.034670 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1177 11:30:49.034800 # Handled SIG_COPYCTX
1178 11:30:49.034909 # Mangling template header. Spare space:4096
1179 11:30:49.035007 # Using badly built context - ERR: Missing FPSIMD
1180 11:30:49.035101 # SIG_OK -- SP:0xFFFFD18112C0 si_addr@:0xffffd18112c0 si_code:2 token@:0xffffd1810060 offset:-4704
1181 11:30:49.035198 # ==>> completed. PASS(1)
1182 11:30:49.035332 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1183 11:30:49.035491 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD1810060
1184 11:30:49.044873 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1185 11:30:49.096652 # selftests: arm64: fake_sigreturn_sme_change_vl
1186 11:30:49.150214 # Registered handlers for all signals.
1187 11:30:49.150806 # Detected MINSTKSIGSZ:10000
1188 11:30:49.150977 # Required Features: [ SME ] supported
1189 11:30:49.151177 # Incompatible Features: [] absent
1190 11:30:49.151368 # Testcase initialized.
1191 11:30:49.151556 # uc context validated.
1192 11:30:49.151746 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1193 11:30:49.151949 # Handled SIG_COPYCTX
1194 11:30:49.152135 # Attempting to change VL from 16 to 256
1195 11:30:49.152322 # SIG_OK -- SP:0xFFFFD58A1630 si_addr@:0xffffd58a1630 si_code:2 token@:0xffffd58a03d0 offset:-4704
1196 11:30:49.152551 # ==>> completed. PASS(1)
1197 11:30:49.152728 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1198 11:30:49.152919 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD58A03D0
1199 11:30:49.162538 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1200 11:30:49.224995 # selftests: arm64: fake_sigreturn_sve_change_vl
1201 11:30:49.278599 # Registered handlers for all signals.
1202 11:30:49.279108 # Detected MINSTKSIGSZ:10000
1203 11:30:49.279219 # Required Features: [ SVE ] supported
1204 11:30:49.279312 # Incompatible Features: [] absent
1205 11:30:49.279402 # Testcase initialized.
1206 11:30:49.279490 # uc context validated.
1207 11:30:49.279575 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1208 11:30:49.279663 # Handled SIG_COPYCTX
1209 11:30:49.279955 # Attempting to change VL from 16 to 256
1210 11:30:49.280060 # SIG_OK -- SP:0xFFFFD725BDD0 si_addr@:0xffffd725bdd0 si_code:2 token@:0xffffd725ab70 offset:-4704
1211 11:30:49.280151 # ==>> completed. PASS(1)
1212 11:30:49.280237 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1213 11:30:49.280324 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD725AB70
1214 11:30:49.288737 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1215 11:30:49.337917 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1216 11:30:49.390341 # Registered handlers for all signals.
1217 11:30:49.390771 # Detected MINSTKSIGSZ:10000
1218 11:30:49.390848 # Testcase initialized.
1219 11:30:49.390915 # uc context validated.
1220 11:30:49.390979 # Handled SIG_TRIG
1221 11:30:49.393625 # SIG_OK -- SP:0xFFFFCC8B3B60 si_addr@:0xffffcc8b3b60 si_code:2 token@:(nil) offset:-281474113420128
1222 11:30:49.393796 # ==>> completed. PASS(1)
1223 11:30:49.394096 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1224 11:30:49.404419 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1225 11:30:49.475706 # selftests: arm64: mangle_pstate_invalid_daif_bits
1226 11:30:49.556395 # Registered handlers for all signals.
1227 11:30:49.556636 # Detected MINSTKSIGSZ:10000
1228 11:30:49.556735 # Testcase initialized.
1229 11:30:49.556825 # uc context validated.
1230 11:30:49.556912 # Handled SIG_TRIG
1231 11:30:49.557019 # SIG_OK -- SP:0xFFFFE7A8E760 si_addr@:0xffffe7a8e760 si_code:2 token@:(nil) offset:-281474568349536
1232 11:30:49.557111 # ==>> completed. PASS(1)
1233 11:30:49.557198 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1234 11:30:49.569440 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1235 11:30:49.620669 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1236 11:30:49.682085 # Registered handlers for all signals.
1237 11:30:49.682683 # Detected MINSTKSIGSZ:10000
1238 11:30:49.682886 # Testcase initialized.
1239 11:30:49.683058 # uc context validated.
1240 11:30:49.683223 # Handled SIG_TRIG
1241 11:30:49.683407 # SIG_OK -- SP:0xFFFFCBFA6490 si_addr@:0xffffcbfa6490 si_code:2 token@:(nil) offset:-281474103927952
1242 11:30:49.683636 # ==>> completed. PASS(1)
1243 11:30:49.683866 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1244 11:30:49.690033 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1245 11:30:49.741300 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1246 11:30:49.796224 # Registered handlers for all signals.
1247 11:30:49.796472 # Detected MINSTKSIGSZ:10000
1248 11:30:49.796568 # Testcase initialized.
1249 11:30:49.796659 # uc context validated.
1250 11:30:49.796954 # Handled SIG_TRIG
1251 11:30:49.797052 # SIG_OK -- SP:0xFFFFFDE7A5F0 si_addr@:0xfffffde7a5f0 si_code:2 token@:(nil) offset:-281474941560304
1252 11:30:49.798776 # ==>> completed. PASS(1)
1253 11:30:49.799085 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1254 11:30:49.806671 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1255 11:30:49.859209 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1256 11:30:49.929410 # Registered handlers for all signals.
1257 11:30:49.929709 # Detected MINSTKSIGSZ:10000
1258 11:30:49.929898 # Testcase initialized.
1259 11:30:49.930052 # uc context validated.
1260 11:30:49.933032 # Handled SIG_TRIG
1261 11:30:49.933479 # SIG_OK -- SP:0xFFFFE10E8860 si_addr@:0xffffe10e8860 si_code:2 token@:(nil) offset:-281474457569376
1262 11:30:49.933703 # ==>> completed. PASS(1)
1263 11:30:49.934188 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1264 11:30:49.943282 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1265 11:30:49.999800 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1266 11:30:50.052168 # Registered handlers for all signals.
1267 11:30:50.052626 # Detected MINSTKSIGSZ:10000
1268 11:30:50.052936 # Testcase initialized.
1269 11:30:50.053044 # uc context validated.
1270 11:30:50.053129 # Handled SIG_TRIG
1271 11:30:50.053209 # SIG_OK -- SP:0xFFFFED60A540 si_addr@:0xffffed60a540 si_code:2 token@:(nil) offset:-281474664277312
1272 11:30:50.053290 # ==>> completed. PASS(1)
1273 11:30:50.053369 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1274 11:30:50.061423 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1275 11:30:50.110852 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1276 11:30:50.166306 # Registered handlers for all signals.
1277 11:30:50.166541 # Detected MINSTKSIGSZ:10000
1278 11:30:50.166626 # Testcase initialized.
1279 11:30:50.166706 # uc context validated.
1280 11:30:50.166786 # Handled SIG_TRIG
1281 11:30:50.166866 # SIG_OK -- SP:0xFFFFE51DD680 si_addr@:0xffffe51dd680 si_code:2 token@:(nil) offset:-281474525681280
1282 11:30:50.167138 # ==>> completed. PASS(1)
1283 11:30:50.167244 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1284 11:30:50.175219 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1285 11:30:50.231462 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1286 11:30:50.287487 # Registered handlers for all signals.
1287 11:30:50.287976 # Detected MINSTKSIGSZ:10000
1288 11:30:50.288180 # Testcase initialized.
1289 11:30:50.288351 # uc context validated.
1290 11:30:50.288472 # Handled SIG_TRIG
1291 11:30:50.288599 # SIG_OK -- SP:0xFFFFE224E760 si_addr@:0xffffe224e760 si_code:2 token@:(nil) offset:-281474475812704
1292 11:30:50.288700 # ==>> completed. PASS(1)
1293 11:30:50.288792 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1294 11:30:50.298317 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1295 11:30:50.354582 # selftests: arm64: sme_trap_no_sm
1296 11:30:50.506046 # Registered handlers for all signals.
1297 11:30:50.506617 # Detected MINSTKSIGSZ:10000
1298 11:30:50.506827 # Required Features: [ SME ] supported
1299 11:30:50.506997 # Incompatible Features: [] absent
1300 11:30:50.507162 # Testcase initialized.
1301 11:30:50.507328 # SIG_OK -- SP:0xFFFFD1AE41B0 si_addr@:0xaaaae23d2514 si_code:1 token@:(nil) offset:-187650916820244
1302 11:30:50.507459 # ==>> completed. PASS(1)
1303 11:30:50.507634 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1304 11:30:50.530288 ok 19 selftests: arm64: sme_trap_no_sm
1305 11:30:50.639837 # selftests: arm64: sme_trap_non_streaming
1306 11:30:50.704098 # Registered handlers for all signals.
1307 11:30:50.704334 # Detected MINSTKSIGSZ:10000
1308 11:30:50.704428 # Required Features: [] NOT supported
1309 11:30:50.704515 # Incompatible Features: [] supported
1310 11:30:50.704602 # ==>> completed. SKIP.
1311 11:30:50.704705 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1312 11:30:50.714597 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1313 11:30:50.768750 # selftests: arm64: sme_trap_za
1314 11:30:50.823352 # Registered handlers for all signals.
1315 11:30:50.823576 # Detected MINSTKSIGSZ:10000
1316 11:30:50.823673 # Testcase initialized.
1317 11:30:50.823782 # SIG_OK -- SP:0xFFFFDB792330 si_addr@:0xaaaaad942510 si_code:1 token@:(nil) offset:-187650033329424
1318 11:30:50.823883 # ==>> completed. PASS(1)
1319 11:30:50.823972 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1320 11:30:50.831739 ok 21 selftests: arm64: sme_trap_za
1321 11:30:50.883446 # selftests: arm64: sme_vl
1322 11:30:50.936793 # Registered handlers for all signals.
1323 11:30:50.937392 # Detected MINSTKSIGSZ:10000
1324 11:30:50.937565 # Required Features: [ SME ] supported
1325 11:30:50.937719 # Incompatible Features: [] absent
1326 11:30:50.937859 # Testcase initialized.
1327 11:30:50.938017 # uc context validated.
1328 11:30:50.939044 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1329 11:30:50.939364 # Handled SIG_COPYCTX
1330 11:30:50.939451 # got expected VL 32
1331 11:30:50.939519 # ==>> completed. PASS(1)
1332 11:30:50.939594 # # SME VL :: Check that we get the right SME VL reported
1333 11:30:50.946577 ok 22 selftests: arm64: sme_vl
1334 11:30:50.998500 # selftests: arm64: ssve_regs
1335 11:30:51.292187 # Registered handlers for all signals.
1336 11:30:51.292561 # Detected MINSTKSIGSZ:10000
1337 11:30:51.293081 # Required Features: [ SME FA64 ] supported
1338 11:30:51.293310 # Incompatible Features: [] absent
1339 11:30:51.293529 # Testcase initialized.
1340 11:30:51.293770 # Testing VL 256
1341 11:30:51.293975 # Validating EXTRA...
1342 11:30:51.294198 # uc context validated.
1343 11:30:51.294413 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1344 11:30:51.294644 # Handled SIG_COPYCTX
1345 11:30:51.294860 # Got expected size 8752 and VL 256
1346 11:30:51.295037 # Testing VL 128
1347 11:30:51.295175 # Validating EXTRA...
1348 11:30:51.295298 # uc context validated.
1349 11:30:51.295415 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1350 11:30:51.295568 # Handled SIG_COPYCTX
1351 11:30:51.295693 # Got expected size 4384 and VL 128
1352 11:30:51.295836 # Testing VL 64
1353 11:30:51.296004 # uc context validated.
1354 11:30:51.296173 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1355 11:30:51.296342 # Handled SIG_COPYCTX
1356 11:30:51.296511 # Got expected size 2208 and VL 64
1357 11:30:51.296647 # Testing VL 32
1358 11:30:51.296764 # uc context validated.
1359 11:30:51.296884 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1360 11:30:51.297000 # Handled SIG_COPYCTX
1361 11:30:51.297115 # Got expected size 1120 and VL 32
1362 11:30:51.297232 # Testing VL 16
1363 11:30:51.297348 # uc context validated.
1364 11:30:51.297463 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1365 11:30:51.297581 # Handled SIG_COPYCTX
1366 11:30:51.297735 # Got expected size 576 and VL 16
1367 11:30:51.297877 # ==>> completed. PASS(1)
1368 11:30:51.297995 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1369 11:30:51.314184 ok 23 selftests: arm64: ssve_regs
1370 11:30:51.383623 # selftests: arm64: sve_regs
1371 11:30:51.860076 # Registered handlers for all signals.
1372 11:30:51.860418 # Detected MINSTKSIGSZ:10000
1373 11:30:51.860798 # Required Features: [ SVE ] supported
1374 11:30:51.861726 # Incompatible Features: [] absent
1375 11:30:51.861904 # Testcase initialized.
1376 11:30:51.862037 # Testing VL 256
1377 11:30:51.862165 # Validating EXTRA...
1378 11:30:51.862290 # uc context validated.
1379 11:30:51.862422 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1380 11:30:51.862849 # Handled SIG_COPYCTX
1381 11:30:51.863050 # Got expected size 8752 and VL 256
1382 11:30:51.863220 # Testing VL 240
1383 11:30:51.863380 # Validating EXTRA...
1384 11:30:51.863571 # uc context validated.
1385 11:30:51.863737 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1386 11:30:51.863904 # Handled SIG_COPYCTX
1387 11:30:51.864103 # Got expected size 8208 and VL 240
1388 11:30:51.864272 # Testing VL 224
1389 11:30:51.864436 # Validating EXTRA...
1390 11:30:51.864597 # uc context validated.
1391 11:30:51.864757 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1392 11:30:51.864890 # Handled SIG_COPYCTX
1393 11:30:51.865008 # Got expected size 7664 and VL 224
1394 11:30:51.865128 # Testing VL 208
1395 11:30:51.865244 # Validating EXTRA...
1396 11:30:51.865357 # uc context validated.
1397 11:30:51.865479 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1398 11:30:51.865629 # Handled SIG_COPYCTX
1399 11:30:51.865767 # Got expected size 7120 and VL 208
1400 11:30:51.865888 # Testing VL 192
1401 11:30:51.866004 # Validating EXTRA...
1402 11:30:51.866122 # uc context validated.
1403 11:30:51.866239 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1404 11:30:51.871955 # Handled SIG_COPYCTX
1405 11:30:51.872511 # Got expected size 6576 and VL 192
1406 11:30:51.872622 # Testing VL 176
1407 11:30:51.872713 # Validating EXTRA...
1408 11:30:51.872803 # uc context validated.
1409 11:30:51.872889 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1410 11:30:51.872974 # Handled SIG_COPYCTX
1411 11:30:51.873057 # Got expected size 6032 and VL 176
1412 11:30:51.873449 # Testing VL 160
1413 11:30:51.873643 # Validating EXTRA...
1414 11:30:51.873820 # uc context validated.
1415 11:30:51.873952 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1416 11:30:51.874068 # Handled SIG_COPYCTX
1417 11:30:51.874460 # Got expected size 5488 and VL 160
1418 11:30:51.874612 # Testing VL 144
1419 11:30:51.874731 # Validating EXTRA...
1420 11:30:51.874848 # uc context validated.
1421 11:30:51.874962 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1422 11:30:51.875077 # Handled SIG_COPYCTX
1423 11:30:51.875191 # Got expected size 4944 and VL 144
1424 11:30:51.875343 # Testing VL 128
1425 11:30:51.875476 # Validating EXTRA...
1426 11:30:51.875590 # uc context validated.
1427 11:30:51.875704 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1428 11:30:51.875817 # Handled SIG_COPYCTX
1429 11:30:51.875929 # Got expected size 4384 and VL 128
1430 11:30:51.876042 # Testing VL 112
1431 11:30:51.876154 # Validating EXTRA...
1432 11:30:51.876267 # uc context validated.
1433 11:30:51.876631 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1434 11:30:51.876815 # Handled SIG_COPYCTX
1435 11:30:51.876934 # Got expected size 3840 and VL 112
1436 11:30:51.877049 # Testing VL 96
1437 11:30:51.877160 # uc context validated.
1438 11:30:51.877272 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1439 11:30:51.877385 # Handled SIG_COPYCTX
1440 11:30:51.877497 # Got expected size 3296 and VL 96
1441 11:30:51.877608 # Testing VL 80
1442 11:30:51.877737 # uc context validated.
1443 11:30:51.877852 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1444 11:30:51.877965 # Handled SIG_COPYCTX
1445 11:30:51.878078 # Got expected size 2752 and VL 80
1446 11:30:51.878190 # Testing VL 64
1447 11:30:51.878302 # uc context validated.
1448 11:30:51.878414 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1449 11:30:51.878527 # Handled SIG_COPYCTX
1450 11:30:51.878638 # Got expected size 2208 and VL 64
1451 11:30:51.878751 # Testing VL 48
1452 11:30:51.878862 # uc context validated.
1453 11:30:51.878973 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1454 11:30:51.879085 # Handled SIG_COPYCTX
1455 11:30:51.879197 # Got expected size 1664 and VL 48
1456 11:30:51.879311 # Testing VL 32
1457 11:30:51.879423 # uc context validated.
1458 11:30:51.879534 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1459 11:30:51.879645 # Handled SIG_COPYCTX
1460 11:30:51.879757 # Got expected size 1120 and VL 32
1461 11:30:51.879869 # Testing VL 16
1462 11:30:51.880015 # uc context validated.
1463 11:30:51.883894 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1464 11:30:51.884129 # Handled SIG_COPYCTX
1465 11:30:51.884296 # Got expected size 576 and VL 16
1466 11:30:51.884701 # ==>> completed. PASS(1)
1467 11:30:51.884843 # # SVE registers :: Check that we get the right SVE registers reported
1468 11:30:51.884962 ok 24 selftests: arm64: sve_regs
1469 11:30:51.931228 # selftests: arm64: sve_vl
1470 11:30:51.989689 # Registered handlers for all signals.
1471 11:30:51.989938 # Detected MINSTKSIGSZ:10000
1472 11:30:51.990319 # Required Features: [ SVE ] supported
1473 11:30:51.990427 # Incompatible Features: [] absent
1474 11:30:51.990519 # Testcase initialized.
1475 11:30:51.990610 # uc context validated.
1476 11:30:51.990696 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1477 11:30:51.990775 # Handled SIG_COPYCTX
1478 11:30:51.990853 # got expected VL 64
1479 11:30:51.990946 # ==>> completed. PASS(1)
1480 11:30:51.991027 # # SVE VL :: Check that we get the right SVE VL reported
1481 11:30:51.999764 ok 25 selftests: arm64: sve_vl
1482 11:30:52.062106 # selftests: arm64: za_no_regs
1483 11:30:52.153092 # Registered handlers for all signals.
1484 11:30:52.153335 # Detected MINSTKSIGSZ:10000
1485 11:30:52.153645 # Required Features: [ SME ] supported
1486 11:30:52.153765 # Incompatible Features: [] absent
1487 11:30:52.153861 # Testcase initialized.
1488 11:30:52.153954 # Testing VL 256
1489 11:30:52.154043 # uc context validated.
1490 11:30:52.154133 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1491 11:30:52.154223 # Handled SIG_COPYCTX
1492 11:30:52.155599 # Got expected size 16 and VL 256
1493 11:30:52.155915 # Testing VL 128
1494 11:30:52.156021 # uc context validated.
1495 11:30:52.156113 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1496 11:30:52.156200 # Handled SIG_COPYCTX
1497 11:30:52.156306 # Got expected size 16 and VL 128
1498 11:30:52.156400 # Testing VL 64
1499 11:30:52.156493 # uc context validated.
1500 11:30:52.156595 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1501 11:30:52.156684 # Handled SIG_COPYCTX
1502 11:30:52.156772 # Got expected size 16 and VL 64
1503 11:30:52.156876 # Testing VL 32
1504 11:30:52.156966 # uc context validated.
1505 11:30:52.157052 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1506 11:30:52.157141 # Handled SIG_COPYCTX
1507 11:30:52.157242 # Got expected size 16 and VL 32
1508 11:30:52.157333 # Testing VL 16
1509 11:30:52.157421 # uc context validated.
1510 11:30:52.157523 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1511 11:30:52.157612 # Handled SIG_COPYCTX
1512 11:30:52.157706 # Got expected size 16 and VL 16
1513 11:30:52.157811 # ==>> completed. PASS(1)
1514 11:30:52.165245 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1515 11:30:52.165701 ok 26 selftests: arm64: za_no_regs
1516 11:30:52.213292 # selftests: arm64: za_regs
1517 11:30:52.415157 # Registered handlers for all signals.
1518 11:30:52.415411 # Detected MINSTKSIGSZ:10000
1519 11:30:52.415509 # Required Features: [ SME ] supported
1520 11:30:52.415602 # Incompatible Features: [] absent
1521 11:30:52.415910 # Testcase initialized.
1522 11:30:52.416025 # Testing VL 256
1523 11:30:52.416113 # Validating EXTRA...
1524 11:30:52.416198 # uc context validated.
1525 11:30:52.416288 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1526 11:30:52.416375 # Handled SIG_COPYCTX
1527 11:30:52.416460 # Got expected size 65552 and VL 256
1528 11:30:52.416546 # Testing VL 128
1529 11:30:52.416632 # Validating EXTRA...
1530 11:30:52.416719 # uc context validated.
1531 11:30:52.416825 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1532 11:30:52.416914 # Handled SIG_COPYCTX
1533 11:30:52.416998 # Got expected size 16400 and VL 128
1534 11:30:52.417083 # Testing VL 64
1535 11:30:52.417167 # Validating EXTRA...
1536 11:30:52.417250 # uc context validated.
1537 11:30:52.417332 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1538 11:30:52.417415 # Handled SIG_COPYCTX
1539 11:30:52.417500 # Got expected size 4112 and VL 64
1540 11:30:52.417583 # Testing VL 32
1541 11:30:52.417696 # uc context validated.
1542 11:30:52.417787 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1543 11:30:52.417872 # Handled SIG_COPYCTX
1544 11:30:52.417957 # Got expected size 1040 and VL 32
1545 11:30:52.418042 # Testing VL 16
1546 11:30:52.418126 # uc context validated.
1547 11:30:52.418211 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1548 11:30:52.418298 # Handled SIG_COPYCTX
1549 11:30:52.418390 # Got expected size 272 and VL 16
1550 11:30:52.418474 # ==>> completed. PASS(1)
1551 11:30:52.418558 # # ZA register :: Check that we get the right ZA registers reported
1552 11:30:52.427116 ok 27 selftests: arm64: za_regs
1553 11:30:52.482405 # selftests: arm64: pac
1554 11:30:52.676377 # TAP version 13
1555 11:30:52.676729 # 1..7
1556 11:30:52.676904 # # Starting 7 tests from 1 test cases.
1557 11:30:52.677369 # # RUN global.corrupt_pac ...
1558 11:30:52.677537 # # OK global.corrupt_pac
1559 11:30:52.677679 # ok 1 global.corrupt_pac
1560 11:30:52.677809 # # RUN global.pac_instructions_not_nop ...
1561 11:30:52.678077 # # OK global.pac_instructions_not_nop
1562 11:30:52.678234 # ok 2 global.pac_instructions_not_nop
1563 11:30:52.678362 # # RUN global.pac_instructions_not_nop_generic ...
1564 11:30:52.678461 # # OK global.pac_instructions_not_nop_generic
1565 11:30:52.678547 # ok 3 global.pac_instructions_not_nop_generic
1566 11:30:52.678632 # # RUN global.single_thread_different_keys ...
1567 11:30:52.678717 # # OK global.single_thread_different_keys
1568 11:30:52.678826 # ok 4 global.single_thread_different_keys
1569 11:30:52.678917 # # RUN global.exec_changed_keys ...
1570 11:30:52.679003 # # OK global.exec_changed_keys
1571 11:30:52.679088 # ok 5 global.exec_changed_keys
1572 11:30:52.679173 # # RUN global.context_switch_keep_keys ...
1573 11:30:52.679274 # # OK global.context_switch_keep_keys
1574 11:30:52.679377 # ok 6 global.context_switch_keep_keys
1575 11:30:52.679473 # # RUN global.context_switch_keep_keys_generic ...
1576 11:30:52.679550 # # OK global.context_switch_keep_keys_generic
1577 11:30:52.679626 # ok 7 global.context_switch_keep_keys_generic
1578 11:30:52.679701 # # PASSED: 7 / 7 tests passed.
1579 11:30:52.679776 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1580 11:30:52.691017 ok 28 selftests: arm64: pac
1581 11:30:52.742891 # selftests: arm64: fp-stress
1582 11:31:09.789508 # TAP version 13
1583 11:31:09.789883 # 1..27
1584 11:31:09.790346 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1585 11:31:09.790556 # # Will run for 10s
1586 11:31:09.790740 # # Started FPSIMD-0-0
1587 11:31:09.790921 # # Started SVE-VL-256-0
1588 11:31:09.791102 # # Started SVE-VL-240-0
1589 11:31:09.791279 # # Started SVE-VL-224-0
1590 11:31:09.791456 # # Started SVE-VL-208-0
1591 11:31:09.791622 # # Started SVE-VL-192-0
1592 11:31:09.791807 # # Started SVE-VL-176-0
1593 11:31:09.791978 # # Started SVE-VL-160-0
1594 11:31:09.792139 # # Started SVE-VL-144-0
1595 11:31:09.792302 # # Started SVE-VL-128-0
1596 11:31:09.792495 # # Started SVE-VL-112-0
1597 11:31:09.792662 # # Started SVE-VL-96-0
1598 11:31:09.792793 # # Started SVE-VL-80-0
1599 11:31:09.792909 # # Started SVE-VL-64-0
1600 11:31:09.793039 # # Started SVE-VL-48-0
1601 11:31:09.793206 # # Started SVE-VL-32-0
1602 11:31:09.793388 # # Started SVE-VL-16-0
1603 11:31:09.793555 # # Started SSVE-VL-256-0
1604 11:31:09.793848 # # Started ZA-VL-256-0
1605 11:31:09.794036 # # Started SSVE-VL-128-0
1606 11:31:09.794215 # # Started ZA-VL-128-0
1607 11:31:09.794386 # # Started SSVE-VL-64-0
1608 11:31:09.794554 # # Started ZA-VL-64-0
1609 11:31:09.794725 # # Started SSVE-VL-32-0
1610 11:31:09.794903 # # Started ZA-VL-32-0
1611 11:31:09.795079 # # Started SSVE-VL-16-0
1612 11:31:09.795257 # # Started ZA-VL-16-0
1613 11:31:09.795427 # # FPSIMD-0-0: Vector length: 128 bits
1614 11:31:09.795596 # # FPSIMD-0-0: PID: 908
1615 11:31:09.795758 # # SVE-VL-256-0: Vector length: 2048 bits
1616 11:31:09.795936 # # SVE-VL-256-0: PID: 909
1617 11:31:09.796096 # # SVE-VL-176-0: Vector length: 1408 bits
1618 11:31:09.796259 # # SVE-VL-176-0: PID: 914
1619 11:31:09.796380 # # SVE-VL-208-0: Vector length: 1664 bits
1620 11:31:09.796494 # # SVE-VL-208-0: PID: 912
1621 11:31:09.796607 # # SVE-VL-144-0: Vector length: 1152 bits
1622 11:31:09.796723 # # SVE-VL-144-0: PID: 916
1623 11:31:09.796912 # # SVE-VL-192-0: Vector length: 1536 bits
1624 11:31:09.797071 # # SVE-VL-192-0: PID: 913
1625 11:31:09.797225 # # SVE-VL-224-0: Vector length: 1792 bits
1626 11:31:09.797387 # # SVE-VL-224-0: PID: 911
1627 11:31:09.797521 # # SVE-VL-48-0: Vector length: 384 bits
1628 11:31:09.797727 # # SVE-VL-48-0: PID: 922
1629 11:31:09.797900 # # SVE-VL-112-0: Vector length: 896 bits
1630 11:31:09.798018 # # SVE-VL-112-0: PID: 918
1631 11:31:09.798130 # # SVE-VL-240-0: Vector length: 1920 bits
1632 11:31:09.798244 # # SVE-VL-240-0: PID: 910
1633 11:31:09.798355 # # SVE-VL-128-0: Vector length: 1024 bits
1634 11:31:09.798466 # # SVE-VL-128-0: PID: 917
1635 11:31:09.798578 # # SVE-VL-160-0: Vector length: 1280 bits
1636 11:31:09.798690 # # SVE-VL-160-0: PID: 915
1637 11:31:09.800728 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1638 11:31:09.801032 # # SSVE-VL-256-0: PID: 925
1639 11:31:09.801570 # # SVE-VL-16-0: Vector length: 128 bits
1640 11:31:09.801765 # # SVE-VL-16-0: PID: 924
1641 11:31:09.801900 # # SVE-VL-80-0: Vector length: 640 bits
1642 11:31:09.802045 # # SVE-VL-80-0: PID: 920
1643 11:31:09.802221 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1644 11:31:09.802357 # # SVE-VL-64-0: Vector length: 512 bits
1645 11:31:09.802475 # # SVE-VL-64-0: PID: 921
1646 11:31:09.802862 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1647 11:31:09.803071 # # ZA-VL-128-0: PID: 928
1648 11:31:09.803253 # # SVE-VL-96-0: Vector length: 768 bits
1649 11:31:09.803421 # # SVE-VL-96-0: PID: 919
1650 11:31:09.803590 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1651 11:31:09.803759 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1652 11:31:09.803909 # # SSVE-VL-64-0: PID: 929
1653 11:31:09.804066 # # ZA-VL-256-0: PID: 926
1654 11:31:09.804205 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1655 11:31:09.804360 # # ZA-VL-64-0: PID: 930
1656 11:31:09.804499 # # SVE-VL-32-0: Vector length: 256 bits
1657 11:31:09.804616 # # SVE-VL-32-0: PID: 923
1658 11:31:09.804730 # # SSVE-VL-32-0: PID: 931
1659 11:31:09.804879 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1660 11:31:09.805002 # # SSVE-VL-128-0: PID: 927
1661 11:31:09.805120 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1662 11:31:09.805240 # # SSVE-VL-16-0: PID: 933
1663 11:31:09.805363 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1664 11:31:09.805488 # # ZA-VL-32-0: PID: 932
1665 11:31:09.805610 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1666 11:31:09.805749 # # ZA-VL-16-0: PID: 934
1667 11:31:09.805907 # # Finishing up...
1668 11:31:09.806067 # ok 1 FPSIMD-0-0
1669 11:31:09.806269 # ok 2 SVE-VL-256-0
1670 11:31:09.806440 # ok 3 SVE-VL-240-0
1671 11:31:09.806655 # ok 4 SVE-VL-224-0
1672 11:31:09.806839 # ok 5 SVE-VL-208-0
1673 11:31:09.807010 # ok 6 SVE-VL-192-0
1674 11:31:09.807220 # ok 7 SVE-VL-176-0
1675 11:31:09.807438 # ok 8 SVE-VL-160-0
1676 11:31:09.807683 # ok 9 SVE-VL-144-0
1677 11:31:09.807871 # ok 10 SVE-VL-128-0
1678 11:31:09.808040 # ok 11 SVE-VL-112-0
1679 11:31:09.808167 # ok 12 SVE-VL-96-0
1680 11:31:09.808281 # ok 13 SVE-VL-80-0
1681 11:31:09.808395 # ok 14 SVE-VL-64-0
1682 11:31:09.808509 # ok 15 SVE-VL-48-0
1683 11:31:09.808623 # ok 16 SVE-VL-32-0
1684 11:31:09.808737 # ok 17 SVE-VL-16-0
1685 11:31:09.808856 # ok 18 SSVE-VL-256-0
1686 11:31:09.808973 # ok 19 ZA-VL-256-0
1687 11:31:09.809088 # ok 20 SSVE-VL-128-0
1688 11:31:09.809204 # ok 21 ZA-VL-128-0
1689 11:31:09.809319 # ok 22 SSVE-VL-64-0
1690 11:31:09.809435 # ok 23 ZA-VL-64-0
1691 11:31:09.809551 # ok 24 SSVE-VL-32-0
1692 11:31:09.809679 # ok 25 ZA-VL-32-0
1693 11:31:09.809797 # ok 26 SSVE-VL-16-0
1694 11:31:09.809914 # ok 27 ZA-VL-16-0
1695 11:31:09.810029 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=3735, signals=9
1696 11:31:09.810176 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=179, signals=9
1697 11:31:09.824756 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=2467, signals=9
1698 11:31:09.825332 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=6016, signals=9
1699 11:31:09.825496 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=2832, signals=9
1700 11:31:09.825715 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=4784, signals=9
1701 11:31:09.825895 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=4496, signals=9
1702 11:31:09.826083 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=1337, signals=9
1703 11:31:09.826223 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=5658, signals=9
1704 11:31:09.826368 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=3602, signals=9
1705 11:31:09.938243 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=681, signals=9
1706 11:31:09.938849 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=12720, signals=9
1707 11:31:09.939065 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=8591, signals=9
1708 11:31:09.939209 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=8175, signals=9
1709 11:31:09.939402 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=2626, signals=9
1710 11:31:09.939570 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=1482, signals=9
1711 11:31:09.939757 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=4127, signals=9
1712 11:31:09.939987 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=3132, signals=9
1713 11:31:09.940139 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=1213, signals=9
1714 11:31:09.940262 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=11849, signals=9
1715 11:31:09.944750 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=7508, signals=9
1716 11:31:09.945150 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=3474, signals=9
1717 11:31:09.945346 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=2436, signals=9
1718 11:31:09.945531 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=3859, signals=9
1719 11:31:09.945728 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2560, signals=9
1720 11:31:09.945958 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=6563, signals=9
1721 11:31:09.946110 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=3168, signals=9
1722 11:31:09.946253 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1723 11:31:09.946376 ok 29 selftests: arm64: fp-stress
1724 11:31:10.079125 # selftests: arm64: sve-ptrace
1725 11:31:10.203056 # TAP version 13
1726 11:31:10.203384 # 1..4104
1727 11:31:10.203556 # # Parent is 951, child is 952
1728 11:31:10.203774 # ok 1 SVE FPSIMD set via SVE: 0
1729 11:31:10.204214 # ok 2 SVE get_fpsimd() gave same state
1730 11:31:10.204409 # ok 3 SVE SVE_PT_VL_INHERIT set
1731 11:31:10.204576 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1732 11:31:10.204721 # ok 5 Set SVE VL 16
1733 11:31:10.204875 # ok 6 Set and get SVE data for VL 16
1734 11:31:10.205055 # ok 7 Set and get FPSIMD data for SVE VL 16
1735 11:31:10.205213 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1736 11:31:10.205367 # ok 9 Set SVE VL 32
1737 11:31:10.205524 # ok 10 Set and get SVE data for VL 32
1738 11:31:10.205732 # ok 11 Set and get FPSIMD data for SVE VL 32
1739 11:31:10.205893 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1740 11:31:10.206047 # ok 13 Set SVE VL 48
1741 11:31:10.206205 # ok 14 Set and get SVE data for VL 48
1742 11:31:10.206378 # ok 15 Set and get FPSIMD data for SVE VL 48
1743 11:31:10.206569 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1744 11:31:10.206740 # ok 17 Set SVE VL 64
1745 11:31:10.206910 # ok 18 Set and get SVE data for VL 64
1746 11:31:10.207070 # ok 19 Set and get FPSIMD data for SVE VL 64
1747 11:31:10.207227 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1748 11:31:10.207400 # ok 21 Set SVE VL 80
1749 11:31:10.207552 # ok 22 Set and get SVE data for VL 80
1750 11:31:10.207713 # ok 23 Set and get FPSIMD data for SVE VL 80
1751 11:31:10.207866 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1752 11:31:10.207993 # ok 25 Set SVE VL 96
1753 11:31:10.208109 # ok 26 Set and get SVE data for VL 96
1754 11:31:10.208267 # ok 27 Set and get FPSIMD data for SVE VL 96
1755 11:31:10.208389 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1756 11:31:10.208506 # ok 29 Set SVE VL 112
1757 11:31:10.208623 # ok 30 Set and get SVE data for VL 112
1758 11:31:10.208737 # ok 31 Set and get FPSIMD data for SVE VL 112
1759 11:31:10.208852 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1760 11:31:10.208967 # ok 33 Set SVE VL 128
1761 11:31:10.209081 # ok 34 Set and get SVE data for VL 128
1762 11:31:10.209196 # ok 35 Set and get FPSIMD data for SVE VL 128
1763 11:31:10.209311 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1764 11:31:10.209427 # ok 37 Set SVE VL 144
1765 11:31:10.209540 # ok 38 Set and get SVE data for VL 144
1766 11:31:10.209698 # ok 39 Set and get FPSIMD data for SVE VL 144
1767 11:31:10.209911 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1768 11:31:10.210101 # ok 41 Set SVE VL 160
1769 11:31:10.210284 # ok 42 Set and get SVE data for VL 160
1770 11:31:10.210468 # ok 43 Set and get FPSIMD data for SVE VL 160
1771 11:31:10.210653 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1772 11:31:10.210835 # ok 45 Set SVE VL 176
1773 11:31:10.211017 # ok 46 Set and get SVE data for VL 176
1774 11:31:10.211193 # ok 47 Set and get FPSIMD data for SVE VL 176
1775 11:31:10.211334 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1776 11:31:10.211474 # ok 49 Set SVE VL 192
1777 11:31:10.212393 # ok 50 Set and get SVE data for VL 192
1778 11:31:10.212840 # ok 51 Set and get FPSIMD data for SVE VL 192
1779 11:31:10.213023 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1780 11:31:10.213235 # ok 53 Set SVE VL 208
1781 11:31:10.213446 # ok 54 Set and get SVE data for VL 208
1782 11:31:10.213620 # ok 55 Set and get FPSIMD data for SVE VL 208
1783 11:31:10.213879 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1784 11:31:10.214101 # ok 57 Set SVE VL 224
1785 11:31:10.214313 # ok 58 Set and get SVE data for VL 224
1786 11:31:10.214503 # ok 59 Set and get FPSIMD data for SVE VL 224
1787 11:31:10.214695 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1788 11:31:10.214876 # ok 61 Set SVE VL 240
1789 11:31:10.215052 # ok 62 Set and get SVE data for VL 240
1790 11:31:10.215257 # ok 63 Set and get FPSIMD data for SVE VL 240
1791 11:31:10.215446 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1792 11:31:10.215650 # ok 65 Set SVE VL 256
1793 11:31:10.215851 # ok 66 Set and get SVE data for VL 256
1794 11:31:10.216065 # ok 67 Set and get FPSIMD data for SVE VL 256
1795 11:31:10.216202 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1796 11:31:10.216322 # ok 69 Set SVE VL 272
1797 11:31:10.216438 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1798 11:31:10.216553 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1799 11:31:10.216671 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1800 11:31:10.216785 # ok 73 Set SVE VL 288
1801 11:31:10.216900 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1802 11:31:10.217015 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1803 11:31:10.217130 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1804 11:31:10.217244 # ok 77 Set SVE VL 304
1805 11:31:10.217358 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1806 11:31:10.217471 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1807 11:31:10.217586 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1808 11:31:10.217720 # ok 81 Set SVE VL 320
1809 11:31:10.217835 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1810 11:31:10.217949 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1811 11:31:10.218062 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1812 11:31:10.218175 # ok 85 Set SVE VL 336
1813 11:31:10.218288 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1814 11:31:10.222164 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1815 11:31:10.222475 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1816 11:31:10.222576 # ok 89 Set SVE VL 352
1817 11:31:10.222667 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1818 11:31:10.222770 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1819 11:31:10.222858 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1820 11:31:10.222944 # ok 93 Set SVE VL 368
1821 11:31:10.223044 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1822 11:31:10.223133 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1823 11:31:10.223232 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1824 11:31:10.223320 # ok 97 Set SVE VL 384
1825 11:31:10.223420 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1826 11:31:10.223521 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1827 11:31:10.223630 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1828 11:31:10.223730 # ok 101 Set SVE VL 400
1829 11:31:10.224902 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1830 11:31:10.225215 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1831 11:31:10.225320 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1832 11:31:10.225424 # ok 105 Set SVE VL 416
1833 11:31:10.225696 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1834 11:31:10.225799 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1835 11:31:10.225887 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1836 11:31:10.225987 # ok 109 Set SVE VL 432
1837 11:31:10.226076 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1838 11:31:10.226177 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1839 11:31:10.226277 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1840 11:31:10.226376 # ok 113 Set SVE VL 448
1841 11:31:10.226475 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1842 11:31:10.226574 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1843 11:31:10.226872 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1844 11:31:10.226975 # ok 117 Set SVE VL 464
1845 11:31:10.227080 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1846 11:31:10.227181 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1847 11:31:10.227287 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1848 11:31:10.227374 # ok 121 Set SVE VL 480
1849 11:31:10.227471 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1850 11:31:10.227766 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1851 11:31:10.227869 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1852 11:31:10.227970 # ok 125 Set SVE VL 496
1853 11:31:10.236308 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1854 11:31:10.236560 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1855 11:31:10.237035 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1856 11:31:10.237240 # ok 129 Set SVE VL 512
1857 11:31:10.237410 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1858 11:31:10.237575 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1859 11:31:10.237758 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1860 11:31:10.237954 # ok 133 Set SVE VL 528
1861 11:31:10.238155 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1862 11:31:10.238310 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1863 11:31:10.238472 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1864 11:31:10.238610 # ok 137 Set SVE VL 544
1865 11:31:10.238739 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1866 11:31:10.238896 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1867 11:31:10.239049 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1868 11:31:10.239215 # ok 141 Set SVE VL 560
1869 11:31:10.239405 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1870 11:31:10.239604 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1871 11:31:10.239841 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1872 11:31:10.240030 # ok 145 Set SVE VL 576
1873 11:31:10.240158 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1874 11:31:10.240275 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1875 11:31:10.240388 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1876 11:31:10.240502 # ok 149 Set SVE VL 592
1877 11:31:10.240616 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1878 11:31:10.240729 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1879 11:31:10.240842 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1880 11:31:10.240957 # ok 153 Set SVE VL 608
1881 11:31:10.241069 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1882 11:31:10.241183 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1883 11:31:10.241296 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1884 11:31:10.241409 # ok 157 Set SVE VL 624
1885 11:31:10.241523 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1886 11:31:10.241636 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1887 11:31:10.241877 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1888 11:31:10.242108 # ok 161 Set SVE VL 640
1889 11:31:10.242298 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1890 11:31:10.246480 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1891 11:31:10.246944 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1892 11:31:10.247168 # ok 165 Set SVE VL 656
1893 11:31:10.247340 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1894 11:31:10.247485 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1895 11:31:10.247708 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1896 11:31:10.247874 # ok 169 Set SVE VL 672
1897 11:31:10.248031 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1898 11:31:10.248157 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1899 11:31:10.248274 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1900 11:31:10.248401 # ok 173 Set SVE VL 688
1901 11:31:10.248576 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1902 11:31:10.248758 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1903 11:31:10.248903 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1904 11:31:10.249078 # ok 177 Set SVE VL 704
1905 11:31:10.249273 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1906 11:31:10.249446 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1907 11:31:10.249599 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1908 11:31:10.249776 # ok 181 Set SVE VL 720
1909 11:31:10.249946 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1910 11:31:10.250088 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1911 11:31:10.250281 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1912 11:31:10.250470 # ok 185 Set SVE VL 736
1913 11:31:10.250658 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1914 11:31:10.250859 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1915 11:31:10.251069 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1916 11:31:10.251256 # ok 189 Set SVE VL 752
1917 11:31:10.251463 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1918 11:31:10.251670 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1919 11:31:10.251871 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1920 11:31:10.252062 # ok 193 Set SVE VL 768
1921 11:31:10.252207 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1922 11:31:10.252325 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1923 11:31:10.252439 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1924 11:31:10.252551 # ok 197 Set SVE VL 784
1925 11:31:10.252695 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1926 11:31:10.252820 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1927 11:31:10.252935 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1928 11:31:10.253049 # ok 201 Set SVE VL 800
1929 11:31:10.253164 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1930 11:31:10.253277 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1931 11:31:10.253389 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1932 11:31:10.253503 # ok 205 Set SVE VL 816
1933 11:31:10.253615 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1934 11:31:10.253848 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1935 11:31:10.254044 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1936 11:31:10.254230 # ok 209 Set SVE VL 832
1937 11:31:10.254660 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1938 11:31:10.254829 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1939 11:31:10.254974 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1940 11:31:10.255118 # ok 213 Set SVE VL 848
1941 11:31:10.255262 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1942 11:31:10.260883 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1943 11:31:10.261145 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1944 11:31:10.261304 # ok 217 Set SVE VL 864
1945 11:31:10.261505 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1946 11:31:10.261708 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1947 11:31:10.261919 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1948 11:31:10.262108 # ok 221 Set SVE VL 880
1949 11:31:10.262309 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1950 11:31:10.262562 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1951 11:31:10.262771 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1952 11:31:10.262959 # ok 225 Set SVE VL 896
1953 11:31:10.263126 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1954 11:31:10.263273 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1955 11:31:10.263461 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1956 11:31:10.263701 # ok 229 Set SVE VL 912
1957 11:31:10.263938 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1958 11:31:10.264129 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1959 11:31:10.264292 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1960 11:31:10.264427 # ok 233 Set SVE VL 928
1961 11:31:10.264544 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1962 11:31:10.264660 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1963 11:31:10.264777 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1964 11:31:10.264892 # ok 237 Set SVE VL 944
1965 11:31:10.265006 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1966 11:31:10.265121 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1967 11:31:10.265235 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1968 11:31:10.265348 # ok 241 Set SVE VL 960
1969 11:31:10.265462 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1970 11:31:10.270658 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1971 11:31:10.271153 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1972 11:31:10.271329 # ok 245 Set SVE VL 976
1973 11:31:10.271500 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1974 11:31:10.271707 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1975 11:31:10.271932 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1976 11:31:10.272089 # ok 249 Set SVE VL 992
1977 11:31:10.272217 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1978 11:31:10.272419 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1979 11:31:10.272644 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1980 11:31:10.272858 # ok 253 Set SVE VL 1008
1981 11:31:10.273076 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1982 11:31:10.273293 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1983 11:31:10.273550 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1984 11:31:10.273764 # ok 257 Set SVE VL 1024
1985 11:31:10.273936 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1986 11:31:10.274092 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1987 11:31:10.274246 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1988 11:31:10.274400 # ok 261 Set SVE VL 1040
1989 11:31:10.274554 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1990 11:31:10.274705 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1991 11:31:10.274858 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1992 11:31:10.275012 # ok 265 Set SVE VL 1056
1993 11:31:10.275166 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1994 11:31:10.275317 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1995 11:31:10.275470 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1996 11:31:10.275644 # ok 269 Set SVE VL 1072
1997 11:31:10.275769 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
1998 11:31:10.275882 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
1999 11:31:10.275995 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2000 11:31:10.276108 # ok 273 Set SVE VL 1088
2001 11:31:10.276220 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2002 11:31:10.276333 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2003 11:31:10.276445 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2004 11:31:10.276558 # ok 277 Set SVE VL 1104
2005 11:31:10.276671 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2006 11:31:10.276785 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2007 11:31:10.276898 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2008 11:31:10.277010 # ok 281 Set SVE VL 1120
2009 11:31:10.277122 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2010 11:31:10.277234 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2011 11:31:10.277350 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2012 11:31:10.277463 # ok 285 Set SVE VL 1136
2013 11:31:10.277576 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2014 11:31:10.277762 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2015 11:31:10.278212 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2016 11:31:10.278407 # ok 289 Set SVE VL 1152
2017 11:31:10.278591 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2018 11:31:10.278775 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2019 11:31:10.278957 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2020 11:31:10.286368 # ok 293 Set SVE VL 1168
2021 11:31:10.286590 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2022 11:31:10.286808 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2023 11:31:10.287066 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2024 11:31:10.287295 # ok 297 Set SVE VL 1184
2025 11:31:10.287478 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2026 11:31:10.287640 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2027 11:31:10.287819 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2028 11:31:10.287980 # ok 301 Set SVE VL 1200
2029 11:31:10.288138 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2030 11:31:10.288265 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2031 11:31:10.288483 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2032 11:31:10.288667 # ok 305 Set SVE VL 1216
2033 11:31:10.288828 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2034 11:31:10.288984 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2035 11:31:10.289151 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2036 11:31:10.289372 # ok 309 Set SVE VL 1232
2037 11:31:10.289593 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2038 11:31:10.290181 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2039 11:31:10.290368 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2040 11:31:10.290543 # ok 313 Set SVE VL 1248
2041 11:31:10.290755 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2042 11:31:10.290923 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2043 11:31:10.291090 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2044 11:31:10.291262 # ok 317 Set SVE VL 1264
2045 11:31:10.291467 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2046 11:31:10.291666 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2047 11:31:10.291842 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2048 11:31:10.292019 # ok 321 Set SVE VL 1280
2049 11:31:10.292193 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2050 11:31:10.292320 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2051 11:31:10.292439 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2052 11:31:10.292557 # ok 325 Set SVE VL 1296
2053 11:31:10.292672 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2054 11:31:10.292791 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2055 11:31:10.292908 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2056 11:31:10.293023 # ok 329 Set SVE VL 1312
2057 11:31:10.293139 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2058 11:31:10.293253 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2059 11:31:10.293370 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2060 11:31:10.293487 # ok 333 Set SVE VL 1328
2061 11:31:10.293602 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2062 11:31:10.293730 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2063 11:31:10.293846 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2064 11:31:10.294171 # ok 337 Set SVE VL 1344
2065 11:31:10.294294 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2066 11:31:10.294409 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2067 11:31:10.294524 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2068 11:31:10.294638 # ok 341 Set SVE VL 1360
2069 11:31:10.294754 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2070 11:31:10.294867 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2071 11:31:10.300202 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2072 11:31:10.300409 # ok 345 Set SVE VL 1376
2073 11:31:10.300771 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2074 11:31:10.300876 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2075 11:31:10.300966 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2076 11:31:10.301053 # ok 349 Set SVE VL 1392
2077 11:31:10.301351 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2078 11:31:10.301544 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2079 11:31:10.301738 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2080 11:31:10.301961 # ok 353 Set SVE VL 1408
2081 11:31:10.302226 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2082 11:31:10.302460 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2083 11:31:10.302659 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2084 11:31:10.302902 # ok 357 Set SVE VL 1424
2085 11:31:10.303096 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2086 11:31:10.303305 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2087 11:31:10.303500 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2088 11:31:10.303693 # ok 361 Set SVE VL 1440
2089 11:31:10.303960 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2090 11:31:10.304143 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2091 11:31:10.304288 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2092 11:31:10.304408 # ok 365 Set SVE VL 1456
2093 11:31:10.304524 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2094 11:31:10.304639 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2095 11:31:10.304753 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2096 11:31:10.304870 # ok 369 Set SVE VL 1472
2097 11:31:10.305013 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2098 11:31:10.305135 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2099 11:31:10.305253 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2100 11:31:10.305367 # ok 373 Set SVE VL 1488
2101 11:31:10.305481 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2102 11:31:10.308349 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2103 11:31:10.308849 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2104 11:31:10.309060 # ok 377 Set SVE VL 1504
2105 11:31:10.309227 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2106 11:31:10.309423 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2107 11:31:10.309596 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2108 11:31:10.309793 # ok 381 Set SVE VL 1520
2109 11:31:10.309962 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2110 11:31:10.310120 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2111 11:31:10.310309 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2112 11:31:10.310476 # ok 385 Set SVE VL 1536
2113 11:31:10.310633 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2114 11:31:10.310768 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2115 11:31:10.310936 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2116 11:31:10.311138 # ok 389 Set SVE VL 1552
2117 11:31:10.311406 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2118 11:31:10.311628 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2119 11:31:10.311835 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2120 11:31:10.312069 # ok 393 Set SVE VL 1568
2121 11:31:10.312218 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2122 11:31:10.312341 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2123 11:31:10.312459 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2124 11:31:10.312574 # ok 397 Set SVE VL 1584
2125 11:31:10.312720 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2126 11:31:10.312842 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2127 11:31:10.312957 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2128 11:31:10.313070 # ok 401 Set SVE VL 1600
2129 11:31:10.313182 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2130 11:31:10.316264 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2131 11:31:10.316616 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2132 11:31:10.316814 # ok 405 Set SVE VL 1616
2133 11:31:10.317002 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2134 11:31:10.317249 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2135 11:31:10.317436 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2136 11:31:10.317590 # ok 409 Set SVE VL 1632
2137 11:31:10.317769 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2138 11:31:10.317931 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2139 11:31:10.318081 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2140 11:31:10.318276 # ok 413 Set SVE VL 1648
2141 11:31:10.318431 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2142 11:31:10.318592 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2143 11:31:10.318734 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2144 11:31:10.318888 # ok 417 Set SVE VL 1664
2145 11:31:10.319047 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2146 11:31:10.319210 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2147 11:31:10.319368 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2148 11:31:10.319530 # ok 421 Set SVE VL 1680
2149 11:31:10.319690 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2150 11:31:10.319908 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2151 11:31:10.320068 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2152 11:31:10.320188 # ok 425 Set SVE VL 1696
2153 11:31:10.320301 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2154 11:31:10.320415 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2155 11:31:10.320531 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2156 11:31:10.320644 # ok 429 Set SVE VL 1712
2157 11:31:10.320758 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2158 11:31:10.320873 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2159 11:31:10.320987 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2160 11:31:10.321100 # ok 433 Set SVE VL 1728
2161 11:31:10.321213 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2162 11:31:10.321325 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2163 11:31:10.321439 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2164 11:31:10.321577 # ok 437 Set SVE VL 1744
2165 11:31:10.324257 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2166 11:31:10.324587 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2167 11:31:10.324691 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2168 11:31:10.324780 # ok 441 Set SVE VL 1760
2169 11:31:10.324880 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2170 11:31:10.324968 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2171 11:31:10.325069 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2172 11:31:10.325158 # ok 445 Set SVE VL 1776
2173 11:31:10.325256 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2174 11:31:10.325357 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2175 11:31:10.325664 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2176 11:31:10.325771 # ok 449 Set SVE VL 1792
2177 11:31:10.325875 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2178 11:31:10.325964 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2179 11:31:10.326062 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2180 11:31:10.326147 # ok 453 Set SVE VL 1808
2181 11:31:10.326241 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2182 11:31:10.326349 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2183 11:31:10.326644 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2184 11:31:10.326746 # ok 457 Set SVE VL 1824
2185 11:31:10.326844 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2186 11:31:10.326945 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2187 11:31:10.327271 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2188 11:31:10.327450 # ok 461 Set SVE VL 1840
2189 11:31:10.327585 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2190 11:31:10.327744 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2191 11:31:10.327910 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2192 11:31:10.328045 # ok 465 Set SVE VL 1856
2193 11:31:10.328162 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2194 11:31:10.328300 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2195 11:31:10.328419 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2196 11:31:10.332300 # ok 469 Set SVE VL 1872
2197 11:31:10.332668 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2198 11:31:10.332808 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2199 11:31:10.332973 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2200 11:31:10.333113 # ok 473 Set SVE VL 1888
2201 11:31:10.333238 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2202 11:31:10.333434 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2203 11:31:10.333571 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2204 11:31:10.333707 # ok 477 Set SVE VL 1904
2205 11:31:10.333824 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2206 11:31:10.333939 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2207 11:31:10.346541 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2208 11:31:10.346703 # ok 481 Set SVE VL 1920
2209 11:31:10.346794 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2210 11:31:10.346902 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2211 11:31:10.346993 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2212 11:31:10.347081 # ok 485 Set SVE VL 1936
2213 11:31:10.347181 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2214 11:31:10.347270 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2215 11:31:10.347371 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2216 11:31:10.347458 # ok 489 Set SVE VL 1952
2217 11:31:10.347556 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2218 11:31:10.347865 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2219 11:31:10.347966 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2220 11:31:10.348065 # ok 493 Set SVE VL 1968
2221 11:31:10.348353 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2222 11:31:10.348680 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2223 11:31:10.348876 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2224 11:31:10.349060 # ok 497 Set SVE VL 1984
2225 11:31:10.349282 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2226 11:31:10.349461 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2227 11:31:10.349709 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2228 11:31:10.349915 # ok 501 Set SVE VL 2000
2229 11:31:10.350136 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2230 11:31:10.350360 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2231 11:31:10.350556 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2232 11:31:10.350786 # ok 505 Set SVE VL 2016
2233 11:31:10.350977 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2234 11:31:10.351171 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2235 11:31:10.351333 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2236 11:31:10.351497 # ok 509 Set SVE VL 2032
2237 11:31:10.351693 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2238 11:31:10.351880 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2239 11:31:10.352033 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2240 11:31:10.352202 # ok 513 Set SVE VL 2048
2241 11:31:10.352335 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2242 11:31:10.352451 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2243 11:31:10.352565 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2244 11:31:10.352677 # ok 517 Set SVE VL 2064
2245 11:31:10.352790 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2246 11:31:10.352905 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2247 11:31:10.353021 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2248 11:31:10.353133 # ok 521 Set SVE VL 2080
2249 11:31:10.353278 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2250 11:31:10.353399 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2251 11:31:10.353513 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2252 11:31:10.353628 # ok 525 Set SVE VL 2096
2253 11:31:10.353764 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2254 11:31:10.353917 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2255 11:31:10.354078 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2256 11:31:10.354243 # ok 529 Set SVE VL 2112
2257 11:31:10.354397 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2258 11:31:10.354517 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2259 11:31:10.354674 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2260 11:31:10.354873 # ok 533 Set SVE VL 2128
2261 11:31:10.355075 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2262 11:31:10.355291 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2263 11:31:10.355504 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2264 11:31:10.355697 # ok 537 Set SVE VL 2144
2265 11:31:10.355912 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2266 11:31:10.356304 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2267 11:31:10.356404 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2268 11:31:10.356496 # ok 541 Set SVE VL 2160
2269 11:31:10.356582 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2270 11:31:10.356665 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2271 11:31:10.356749 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2272 11:31:10.356831 # ok 545 Set SVE VL 2176
2273 11:31:10.356917 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2274 11:31:10.356998 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2275 11:31:10.357082 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2276 11:31:10.357164 # ok 549 Set SVE VL 2192
2277 11:31:10.357247 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2278 11:31:10.357328 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2279 11:31:10.357413 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2280 11:31:10.357495 # ok 553 Set SVE VL 2208
2281 11:31:10.357578 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2282 11:31:10.357689 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2283 11:31:10.357778 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2284 11:31:10.357861 # ok 557 Set SVE VL 2224
2285 11:31:10.357945 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2286 11:31:10.358029 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2287 11:31:10.358114 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2288 11:31:10.358197 # ok 561 Set SVE VL 2240
2289 11:31:10.358276 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2290 11:31:10.358360 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2291 11:31:10.358441 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2292 11:31:10.358541 # ok 565 Set SVE VL 2256
2293 11:31:10.358625 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2294 11:31:10.358708 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2295 11:31:10.358791 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2296 11:31:10.358874 # ok 569 Set SVE VL 2272
2297 11:31:10.358955 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2298 11:31:10.359035 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2299 11:31:10.359133 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2300 11:31:10.359217 # ok 573 Set SVE VL 2288
2301 11:31:10.359300 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2302 11:31:10.359382 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2303 11:31:10.359478 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2304 11:31:10.359564 # ok 577 Set SVE VL 2304
2305 11:31:10.359660 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2306 11:31:10.359757 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2307 11:31:10.359917 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2308 11:31:10.360128 # ok 581 Set SVE VL 2320
2309 11:31:10.360548 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2310 11:31:10.360995 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2311 11:31:10.361144 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2312 11:31:10.361269 # ok 585 Set SVE VL 2336
2313 11:31:10.361424 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2314 11:31:10.361589 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2315 11:31:10.361739 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2316 11:31:10.361857 # ok 589 Set SVE VL 2352
2317 11:31:10.361945 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2318 11:31:10.362019 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2319 11:31:10.362123 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2320 11:31:10.362217 # ok 593 Set SVE VL 2368
2321 11:31:10.362323 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2322 11:31:10.362421 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2323 11:31:10.362519 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2324 11:31:10.362628 # ok 597 Set SVE VL 2384
2325 11:31:10.362716 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2326 11:31:10.362815 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2327 11:31:10.362892 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2328 11:31:10.362961 # ok 601 Set SVE VL 2400
2329 11:31:10.363036 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2330 11:31:10.363101 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2331 11:31:10.363170 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2332 11:31:10.363246 # ok 605 Set SVE VL 2416
2333 11:31:10.363331 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2334 11:31:10.363405 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2335 11:31:10.363499 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2336 11:31:10.363572 # ok 609 Set SVE VL 2432
2337 11:31:10.363660 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2338 11:31:10.363747 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2339 11:31:10.363848 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2340 11:31:10.363967 # ok 613 Set SVE VL 2448
2341 11:31:10.364261 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2342 11:31:10.364347 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2343 11:31:10.364444 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2344 11:31:10.364540 # ok 617 Set SVE VL 2464
2345 11:31:10.364663 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2346 11:31:10.364761 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2347 11:31:10.364853 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2348 11:31:10.365122 # ok 621 Set SVE VL 2480
2349 11:31:10.365201 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2350 11:31:10.365302 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2351 11:31:10.365403 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2352 11:31:10.365492 # ok 625 Set SVE VL 2496
2353 11:31:10.365582 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2354 11:31:10.365698 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2355 11:31:10.365787 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2356 11:31:10.365882 # ok 629 Set SVE VL 2512
2357 11:31:10.365998 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2358 11:31:10.366105 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2359 11:31:10.366196 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2360 11:31:10.366313 # ok 633 Set SVE VL 2528
2361 11:31:10.366406 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2362 11:31:10.366492 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2363 11:31:10.366564 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2364 11:31:10.366674 # ok 637 Set SVE VL 2544
2365 11:31:10.366763 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2366 11:31:10.366862 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2367 11:31:10.366936 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2368 11:31:10.367030 # ok 641 Set SVE VL 2560
2369 11:31:10.367097 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2370 11:31:10.367168 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2371 11:31:10.367266 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2372 11:31:10.367346 # ok 645 Set SVE VL 2576
2373 11:31:10.367446 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2374 11:31:10.367556 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2375 11:31:10.367671 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2376 11:31:10.367807 # ok 649 Set SVE VL 2592
2377 11:31:10.367899 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2378 11:31:10.367979 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2379 11:31:10.368061 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2380 11:31:10.368141 # ok 653 Set SVE VL 2608
2381 11:31:10.368228 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2382 11:31:10.368315 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2383 11:31:10.368417 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2384 11:31:10.368519 # ok 657 Set SVE VL 2624
2385 11:31:10.369062 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2386 11:31:10.369151 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2387 11:31:10.369222 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2388 11:31:10.369307 # ok 661 Set SVE VL 2640
2389 11:31:10.369393 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2390 11:31:10.369465 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2391 11:31:10.369539 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2392 11:31:10.369785 # ok 665 Set SVE VL 2656
2393 11:31:10.369852 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2394 11:31:10.375393 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2395 11:31:10.375740 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2396 11:31:10.375953 # ok 669 Set SVE VL 2672
2397 11:31:10.376101 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2398 11:31:10.376255 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2399 11:31:10.376394 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2400 11:31:10.376540 # ok 673 Set SVE VL 2688
2401 11:31:10.376695 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2402 11:31:10.376838 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2403 11:31:10.377190 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2404 11:31:10.377362 # ok 677 Set SVE VL 2704
2405 11:31:10.377507 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2406 11:31:10.377888 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2407 11:31:10.378033 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2408 11:31:10.378157 # ok 681 Set SVE VL 2720
2409 11:31:10.378285 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2410 11:31:10.378435 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2411 11:31:10.378580 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2412 11:31:10.378742 # ok 685 Set SVE VL 2736
2413 11:31:10.378922 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2414 11:31:10.379052 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2415 11:31:10.379153 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2416 11:31:10.379259 # ok 689 Set SVE VL 2752
2417 11:31:10.379353 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2418 11:31:10.379643 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2419 11:31:10.379730 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2420 11:31:10.379863 # ok 693 Set SVE VL 2768
2421 11:31:10.379954 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2422 11:31:10.380040 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2423 11:31:10.380433 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2424 11:31:10.380548 # ok 697 Set SVE VL 2784
2425 11:31:10.380669 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2426 11:31:10.380789 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2427 11:31:10.381099 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2428 11:31:10.381191 # ok 701 Set SVE VL 2800
2429 11:31:10.381288 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2430 11:31:10.381401 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2431 11:31:10.381498 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2432 11:31:10.381586 # ok 705 Set SVE VL 2816
2433 11:31:10.381689 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2434 11:31:10.381820 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2435 11:31:10.381926 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2436 11:31:10.382067 # ok 709 Set SVE VL 2832
2437 11:31:10.382188 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2438 11:31:10.382284 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2439 11:31:10.382386 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2440 11:31:10.382465 # ok 713 Set SVE VL 2848
2441 11:31:10.382563 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2442 11:31:10.382663 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2443 11:31:10.382749 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2444 11:31:10.382849 # ok 717 Set SVE VL 2864
2445 11:31:10.383129 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2446 11:31:10.383226 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2447 11:31:10.383328 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2448 11:31:10.383429 # ok 721 Set SVE VL 2880
2449 11:31:10.383509 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2450 11:31:10.383600 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2451 11:31:10.383698 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2452 11:31:10.383774 # ok 725 Set SVE VL 2896
2453 11:31:10.383862 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2454 11:31:10.383937 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2455 11:31:10.384206 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2456 11:31:10.384293 # ok 729 Set SVE VL 2912
2457 11:31:10.384367 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2458 11:31:10.384440 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2459 11:31:10.384516 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2460 11:31:10.384593 # ok 733 Set SVE VL 2928
2461 11:31:10.384689 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2462 11:31:10.384963 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2463 11:31:10.385063 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2464 11:31:10.385182 # ok 737 Set SVE VL 2944
2465 11:31:10.385287 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2466 11:31:10.385402 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2467 11:31:10.385491 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2468 11:31:10.385574 # ok 741 Set SVE VL 2960
2469 11:31:10.385670 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2470 11:31:10.385783 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2471 11:31:10.385882 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2472 11:31:10.385967 # ok 745 Set SVE VL 2976
2473 11:31:10.386049 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2474 11:31:10.386129 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2475 11:31:10.386221 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2476 11:31:10.386299 # ok 749 Set SVE VL 2992
2477 11:31:10.386390 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2478 11:31:10.386462 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2479 11:31:10.386550 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2480 11:31:10.386642 # ok 753 Set SVE VL 3008
2481 11:31:10.386742 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2482 11:31:10.386838 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2483 11:31:10.387150 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2484 11:31:10.387307 # ok 757 Set SVE VL 3024
2485 11:31:10.387433 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2486 11:31:10.387603 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2487 11:31:10.387747 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2488 11:31:10.387879 # ok 761 Set SVE VL 3040
2489 11:31:10.387995 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2490 11:31:10.388118 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2491 11:31:10.388236 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2492 11:31:10.388361 # ok 765 Set SVE VL 3056
2493 11:31:10.388484 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2494 11:31:10.388628 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2495 11:31:10.388781 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2496 11:31:10.388925 # ok 769 Set SVE VL 3072
2497 11:31:10.389062 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2498 11:31:10.389206 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2499 11:31:10.389348 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2500 11:31:10.389526 # ok 773 Set SVE VL 3088
2501 11:31:10.389670 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2502 11:31:10.389796 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2503 11:31:10.389910 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2504 11:31:10.389992 # ok 777 Set SVE VL 3104
2505 11:31:10.390074 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2506 11:31:10.390164 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2507 11:31:10.390246 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2508 11:31:10.390322 # ok 781 Set SVE VL 3120
2509 11:31:10.390404 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2510 11:31:10.390491 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2511 11:31:10.390572 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2512 11:31:10.390646 # ok 785 Set SVE VL 3136
2513 11:31:10.390721 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2514 11:31:10.390795 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2515 11:31:10.390876 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2516 11:31:10.390956 # ok 789 Set SVE VL 3152
2517 11:31:10.391030 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2518 11:31:10.391116 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2519 11:31:10.391195 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2520 11:31:10.391266 # ok 793 Set SVE VL 3168
2521 11:31:10.391345 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2522 11:31:10.391423 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2523 11:31:10.391502 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2524 11:31:10.391578 # ok 797 Set SVE VL 3184
2525 11:31:10.391673 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2526 11:31:10.391753 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2527 11:31:10.392048 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2528 11:31:10.392181 # ok 801 Set SVE VL 3200
2529 11:31:10.392299 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2530 11:31:10.392422 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2531 11:31:10.392544 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2532 11:31:10.392669 # ok 805 Set SVE VL 3216
2533 11:31:10.392785 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2534 11:31:10.392928 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2535 11:31:10.393029 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2536 11:31:10.393108 # ok 809 Set SVE VL 3232
2537 11:31:10.393177 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2538 11:31:10.393247 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2539 11:31:10.393328 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2540 11:31:10.393398 # ok 813 Set SVE VL 3248
2541 11:31:10.393470 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2542 11:31:10.393561 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2543 11:31:10.393641 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2544 11:31:10.393729 # ok 817 Set SVE VL 3264
2545 11:31:10.393823 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2546 11:31:10.393948 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2547 11:31:10.394034 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2548 11:31:10.394104 # ok 821 Set SVE VL 3280
2549 11:31:10.394166 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2550 11:31:10.394244 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2551 11:31:10.394312 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2552 11:31:10.394402 # ok 825 Set SVE VL 3296
2553 11:31:10.394483 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2554 11:31:10.394576 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2555 11:31:10.394657 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2556 11:31:10.394734 # ok 829 Set SVE VL 3312
2557 11:31:10.394825 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2558 11:31:10.394904 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2559 11:31:10.394995 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2560 11:31:10.395088 # ok 833 Set SVE VL 3328
2561 11:31:10.395167 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2562 11:31:10.395281 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2563 11:31:10.395383 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2564 11:31:10.395498 # ok 837 Set SVE VL 3344
2565 11:31:10.395584 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2566 11:31:10.395687 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2567 11:31:10.395769 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2568 11:31:10.395859 # ok 841 Set SVE VL 3360
2569 11:31:10.395971 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2570 11:31:10.396065 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2571 11:31:10.396360 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2572 11:31:10.396505 # ok 845 Set SVE VL 3376
2573 11:31:10.396662 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2574 11:31:10.396829 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2575 11:31:10.396946 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2576 11:31:10.397044 # ok 849 Set SVE VL 3392
2577 11:31:10.397157 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2578 11:31:10.397240 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2579 11:31:10.397315 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2580 11:31:10.397389 # ok 853 Set SVE VL 3408
2581 11:31:10.397462 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2582 11:31:10.403168 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2583 11:31:10.403278 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2584 11:31:10.403408 # ok 857 Set SVE VL 3424
2585 11:31:10.403522 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2586 11:31:10.403639 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2587 11:31:10.403730 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2588 11:31:10.403864 # ok 861 Set SVE VL 3440
2589 11:31:10.404010 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2590 11:31:10.404082 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2591 11:31:10.404142 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2592 11:31:10.404479 # ok 865 Set SVE VL 3456
2593 11:31:10.404855 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2594 11:31:10.405051 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2595 11:31:10.405239 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2596 11:31:10.405399 # ok 869 Set SVE VL 3472
2597 11:31:10.405567 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2598 11:31:10.405735 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2599 11:31:10.405902 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2600 11:31:10.406078 # ok 873 Set SVE VL 3488
2601 11:31:10.406242 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2602 11:31:10.406383 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2603 11:31:10.406726 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2604 11:31:10.406860 # ok 877 Set SVE VL 3504
2605 11:31:10.407003 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2606 11:31:10.407075 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2607 11:31:10.407157 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2608 11:31:10.407252 # ok 881 Set SVE VL 3520
2609 11:31:10.407496 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2610 11:31:10.407810 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2611 11:31:10.407909 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2612 11:31:10.407995 # ok 885 Set SVE VL 3536
2613 11:31:10.408486 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2614 11:31:10.408577 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2615 11:31:10.408676 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2616 11:31:10.408768 # ok 889 Set SVE VL 3552
2617 11:31:10.409018 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2618 11:31:10.409126 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2619 11:31:10.409233 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2620 11:31:10.409319 # ok 893 Set SVE VL 3568
2621 11:31:10.409576 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2622 11:31:10.409679 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2623 11:31:10.409773 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2624 11:31:10.409852 # ok 897 Set SVE VL 3584
2625 11:31:10.409939 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2626 11:31:10.410025 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2627 11:31:10.410102 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2628 11:31:10.410194 # ok 901 Set SVE VL 3600
2629 11:31:10.410292 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2630 11:31:10.410384 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2631 11:31:10.410663 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2632 11:31:10.410748 # ok 905 Set SVE VL 3616
2633 11:31:10.410812 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2634 11:31:10.410882 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2635 11:31:10.410957 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2636 11:31:10.411043 # ok 909 Set SVE VL 3632
2637 11:31:10.411134 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2638 11:31:10.411245 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2639 11:31:10.411338 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2640 11:31:10.411629 # ok 913 Set SVE VL 3648
2641 11:31:10.411759 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2642 11:31:10.411878 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2643 11:31:10.411972 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2644 11:31:10.412046 # ok 917 Set SVE VL 3664
2645 11:31:10.412126 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2646 11:31:10.412387 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2647 11:31:10.412485 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2648 11:31:10.412582 # ok 921 Set SVE VL 3680
2649 11:31:10.412685 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2650 11:31:10.412774 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2651 11:31:10.412854 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2652 11:31:10.412948 # ok 925 Set SVE VL 3696
2653 11:31:10.413022 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2654 11:31:10.413109 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2655 11:31:10.413199 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2656 11:31:10.413295 # ok 929 Set SVE VL 3712
2657 11:31:10.413394 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2658 11:31:10.413517 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2659 11:31:10.413628 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2660 11:31:10.413750 # ok 933 Set SVE VL 3728
2661 11:31:10.413848 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2662 11:31:10.413956 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2663 11:31:10.414041 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2664 11:31:10.414136 # ok 937 Set SVE VL 3744
2665 11:31:10.414231 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2666 11:31:10.414331 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2667 11:31:10.414422 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2668 11:31:10.414512 # ok 941 Set SVE VL 3760
2669 11:31:10.414605 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2670 11:31:10.414903 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2671 11:31:10.415002 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2672 11:31:10.415099 # ok 945 Set SVE VL 3776
2673 11:31:10.415201 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2674 11:31:10.415289 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2675 11:31:10.415367 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2676 11:31:10.415472 # ok 949 Set SVE VL 3792
2677 11:31:10.415569 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2678 11:31:10.415686 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2679 11:31:10.415774 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2680 11:31:10.415882 # ok 953 Set SVE VL 3808
2681 11:31:10.415982 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2682 11:31:10.416095 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2683 11:31:10.416189 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2684 11:31:10.416304 # ok 957 Set SVE VL 3824
2685 11:31:10.416400 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2686 11:31:10.416501 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2687 11:31:10.416623 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2688 11:31:10.416723 # ok 961 Set SVE VL 3840
2689 11:31:10.416827 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2690 11:31:10.416919 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2691 11:31:10.417025 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2692 11:31:10.417122 # ok 965 Set SVE VL 3856
2693 11:31:10.417397 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2694 11:31:10.417484 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2695 11:31:10.417571 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2696 11:31:10.417653 # ok 969 Set SVE VL 3872
2697 11:31:10.417742 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2698 11:31:10.417828 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2699 11:31:10.417923 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2700 11:31:10.418017 # ok 973 Set SVE VL 3888
2701 11:31:10.418103 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2702 11:31:10.418196 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2703 11:31:10.418471 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2704 11:31:10.418574 # ok 977 Set SVE VL 3904
2705 11:31:10.418673 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2706 11:31:10.418777 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2707 11:31:10.418865 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2708 11:31:10.418946 # ok 981 Set SVE VL 3920
2709 11:31:10.419046 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2710 11:31:10.419148 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2711 11:31:10.419270 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2712 11:31:10.419367 # ok 985 Set SVE VL 3936
2713 11:31:10.419451 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2714 11:31:10.419547 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2715 11:31:10.419629 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2716 11:31:10.419717 # ok 989 Set SVE VL 3952
2717 11:31:10.419798 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2718 11:31:10.419872 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2719 11:31:10.419970 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2720 11:31:10.420046 # ok 993 Set SVE VL 3968
2721 11:31:10.420142 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2722 11:31:10.420258 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2723 11:31:10.420605 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2724 11:31:10.420827 # ok 997 Set SVE VL 3984
2725 11:31:10.421077 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2726 11:31:10.421234 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2727 11:31:10.421381 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2728 11:31:10.421543 # ok 1001 Set SVE VL 4000
2729 11:31:10.421692 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2730 11:31:10.421854 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2731 11:31:10.421977 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2732 11:31:10.422083 # ok 1005 Set SVE VL 4016
2733 11:31:10.422167 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2734 11:31:10.422267 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2735 11:31:10.422368 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2736 11:31:10.422438 # ok 1009 Set SVE VL 4032
2737 11:31:10.422499 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2738 11:31:10.422558 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2739 11:31:10.422938 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2740 11:31:10.423033 # ok 1013 Set SVE VL 4048
2741 11:31:10.423109 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2742 11:31:10.423187 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2743 11:31:10.423264 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2744 11:31:10.423339 # ok 1017 Set SVE VL 4064
2745 11:31:10.423413 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2746 11:31:10.423657 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2747 11:31:10.423724 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2748 11:31:10.423784 # ok 1021 Set SVE VL 4080
2749 11:31:10.423870 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2750 11:31:10.423965 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2751 11:31:10.424048 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2752 11:31:10.424118 # ok 1025 Set SVE VL 4096
2753 11:31:10.424191 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2754 11:31:10.424259 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2755 11:31:10.424348 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2756 11:31:10.424420 # ok 1029 Set SVE VL 4112
2757 11:31:10.424505 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2758 11:31:10.424594 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2759 11:31:10.424683 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2760 11:31:10.424760 # ok 1033 Set SVE VL 4128
2761 11:31:10.424838 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2762 11:31:10.425110 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2763 11:31:10.425189 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2764 11:31:10.425463 # ok 1037 Set SVE VL 4144
2765 11:31:10.425554 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2766 11:31:10.425643 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2767 11:31:10.425734 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2768 11:31:10.433551 # ok 1041 Set SVE VL 4160
2769 11:31:10.433670 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2770 11:31:10.433967 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2771 11:31:10.434066 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2772 11:31:10.434150 # ok 1045 Set SVE VL 4176
2773 11:31:10.434245 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2774 11:31:10.434338 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2775 11:31:10.434439 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2776 11:31:10.434543 # ok 1049 Set SVE VL 4192
2777 11:31:10.434658 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2778 11:31:10.434769 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2779 11:31:10.435068 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2780 11:31:10.435166 # ok 1053 Set SVE VL 4208
2781 11:31:10.435264 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2782 11:31:10.435343 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2783 11:31:10.435450 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2784 11:31:10.435558 # ok 1057 Set SVE VL 4224
2785 11:31:10.435675 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2786 11:31:10.435777 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2787 11:31:10.436070 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2788 11:31:10.439421 # ok 1061 Set SVE VL 4240
2789 11:31:10.439702 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2790 11:31:10.439821 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2791 11:31:10.440103 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2792 11:31:10.440654 # ok 1065 Set SVE VL 4256
2793 11:31:10.440916 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2794 11:31:10.441030 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2795 11:31:10.441128 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2796 11:31:10.441243 # ok 1069 Set SVE VL 4272
2797 11:31:10.441350 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2798 11:31:10.441701 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2799 11:31:10.441802 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2800 11:31:10.442075 # ok 1073 Set SVE VL 4288
2801 11:31:10.442168 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2802 11:31:10.442258 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2803 11:31:10.442348 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2804 11:31:10.442438 # ok 1077 Set SVE VL 4304
2805 11:31:10.442533 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2806 11:31:10.442629 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2807 11:31:10.442725 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2808 11:31:10.442826 # ok 1081 Set SVE VL 4320
2809 11:31:10.442907 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2810 11:31:10.443173 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2811 11:31:10.443279 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2812 11:31:10.443381 # ok 1085 Set SVE VL 4336
2813 11:31:10.443469 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2814 11:31:10.443754 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2815 11:31:10.443928 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2816 11:31:10.444019 # ok 1089 Set SVE VL 4352
2817 11:31:10.444288 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2818 11:31:10.444398 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2819 11:31:10.444499 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2820 11:31:10.444614 # ok 1093 Set SVE VL 4368
2821 11:31:10.444867 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2822 11:31:10.444980 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2823 11:31:10.445108 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2824 11:31:10.445212 # ok 1097 Set SVE VL 4384
2825 11:31:10.445328 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2826 11:31:10.445452 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2827 11:31:10.445779 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2828 11:31:10.445874 # ok 1101 Set SVE VL 4400
2829 11:31:10.445971 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2830 11:31:10.446062 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2831 11:31:10.446157 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2832 11:31:10.446254 # ok 1105 Set SVE VL 4416
2833 11:31:10.446534 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2834 11:31:10.446627 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2835 11:31:10.446745 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2836 11:31:10.446833 # ok 1109 Set SVE VL 4432
2837 11:31:10.446927 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2838 11:31:10.447215 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2839 11:31:10.447306 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2840 11:31:10.447398 # ok 1113 Set SVE VL 4448
2841 11:31:10.447478 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2842 11:31:10.447570 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2843 11:31:10.447677 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2844 11:31:10.447781 # ok 1117 Set SVE VL 4464
2845 11:31:10.448089 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2846 11:31:10.448415 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2847 11:31:10.448508 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2848 11:31:10.448598 # ok 1121 Set SVE VL 4480
2849 11:31:10.448686 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2850 11:31:10.448792 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2851 11:31:10.449079 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2852 11:31:10.449191 # ok 1125 Set SVE VL 4496
2853 11:31:10.449305 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2854 11:31:10.449393 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2855 11:31:10.449498 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2856 11:31:10.449616 # ok 1129 Set SVE VL 4512
2857 11:31:10.449748 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2858 11:31:10.449871 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2859 11:31:10.450002 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2860 11:31:10.450107 # ok 1133 Set SVE VL 4528
2861 11:31:10.450251 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2862 11:31:10.450369 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2863 11:31:10.450503 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2864 11:31:10.450622 # ok 1137 Set SVE VL 4544
2865 11:31:10.450715 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2866 11:31:10.450795 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2867 11:31:10.450893 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2868 11:31:10.450975 # ok 1141 Set SVE VL 4560
2869 11:31:10.451053 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2870 11:31:10.451176 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2871 11:31:10.451276 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2872 11:31:10.451377 # ok 1145 Set SVE VL 4576
2873 11:31:10.451458 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2874 11:31:10.451553 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2875 11:31:10.451635 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2876 11:31:10.451729 # ok 1149 Set SVE VL 4592
2877 11:31:10.451812 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2878 11:31:10.451936 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2879 11:31:10.452038 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2880 11:31:10.452135 # ok 1153 Set SVE VL 4608
2881 11:31:10.452249 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2882 11:31:10.452360 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2883 11:31:10.452645 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2884 11:31:10.452738 # ok 1157 Set SVE VL 4624
2885 11:31:10.452806 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2886 11:31:10.453129 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2887 11:31:10.453227 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2888 11:31:10.453324 # ok 1161 Set SVE VL 4640
2889 11:31:10.453427 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2890 11:31:10.453526 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2891 11:31:10.453805 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2892 11:31:10.453898 # ok 1165 Set SVE VL 4656
2893 11:31:10.453973 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2894 11:31:10.454047 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2895 11:31:10.454123 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2896 11:31:10.454413 # ok 1169 Set SVE VL 4672
2897 11:31:10.454510 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2898 11:31:10.454590 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2899 11:31:10.454701 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2900 11:31:10.454800 # ok 1173 Set SVE VL 4688
2901 11:31:10.454895 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2902 11:31:10.454986 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2903 11:31:10.455065 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2904 11:31:10.455144 # ok 1177 Set SVE VL 4704
2905 11:31:10.455218 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2906 11:31:10.455293 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2907 11:31:10.455385 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2908 11:31:10.455466 # ok 1181 Set SVE VL 4720
2909 11:31:10.455541 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2910 11:31:10.455647 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2911 11:31:10.455746 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2912 11:31:10.455860 # ok 1185 Set SVE VL 4736
2913 11:31:10.455967 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2914 11:31:10.456038 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2915 11:31:10.456116 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2916 11:31:10.456212 # ok 1189 Set SVE VL 4752
2917 11:31:10.456336 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2918 11:31:10.456444 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2919 11:31:10.456545 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2920 11:31:10.456647 # ok 1193 Set SVE VL 4768
2921 11:31:10.456752 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2922 11:31:10.456856 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2923 11:31:10.456978 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2924 11:31:10.457086 # ok 1197 Set SVE VL 4784
2925 11:31:10.457211 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2926 11:31:10.457319 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2927 11:31:10.457428 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2928 11:31:10.457523 # ok 1201 Set SVE VL 4800
2929 11:31:10.457625 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2930 11:31:10.457723 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2931 11:31:10.457830 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2932 11:31:10.457916 # ok 1205 Set SVE VL 4816
2933 11:31:10.458027 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2934 11:31:10.458117 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2935 11:31:10.458219 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2936 11:31:10.458303 # ok 1209 Set SVE VL 4832
2937 11:31:10.458383 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2938 11:31:10.458472 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2939 11:31:10.458753 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2940 11:31:10.458850 # ok 1213 Set SVE VL 4848
2941 11:31:10.458926 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2942 11:31:10.459024 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2943 11:31:10.459113 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2944 11:31:10.459190 # ok 1217 Set SVE VL 4864
2945 11:31:10.459278 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2946 11:31:10.459356 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2947 11:31:10.459450 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2948 11:31:10.459538 # ok 1221 Set SVE VL 4880
2949 11:31:10.459644 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2950 11:31:10.459720 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2951 11:31:10.469480 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2952 11:31:10.469580 # ok 1225 Set SVE VL 4896
2953 11:31:10.469703 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2954 11:31:10.469804 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2955 11:31:10.469914 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2956 11:31:10.469993 # ok 1229 Set SVE VL 4912
2957 11:31:10.470077 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2958 11:31:10.470174 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2959 11:31:10.470270 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2960 11:31:10.470373 # ok 1233 Set SVE VL 4928
2961 11:31:10.470664 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2962 11:31:10.470757 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2963 11:31:10.470854 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2964 11:31:10.470943 # ok 1237 Set SVE VL 4944
2965 11:31:10.471037 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2966 11:31:10.471122 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2967 11:31:10.471214 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2968 11:31:10.471294 # ok 1241 Set SVE VL 4960
2969 11:31:10.471375 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2970 11:31:10.471464 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2971 11:31:10.471567 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2972 11:31:10.471650 # ok 1245 Set SVE VL 4976
2973 11:31:10.471756 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2974 11:31:10.472050 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2975 11:31:10.472129 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2976 11:31:10.473273 # ok 1249 Set SVE VL 4992
2977 11:31:10.473718 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2978 11:31:10.473882 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2979 11:31:10.474090 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2980 11:31:10.474271 # ok 1253 Set SVE VL 5008
2981 11:31:10.474400 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2982 11:31:10.474524 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2983 11:31:10.474663 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2984 11:31:10.474785 # ok 1257 Set SVE VL 5024
2985 11:31:10.474931 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2986 11:31:10.475097 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2987 11:31:10.475247 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2988 11:31:10.475385 # ok 1261 Set SVE VL 5040
2989 11:31:10.475503 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2990 11:31:10.475626 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2991 11:31:10.475775 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2992 11:31:10.475902 # ok 1265 Set SVE VL 5056
2993 11:31:10.476014 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2994 11:31:10.476128 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2995 11:31:10.476227 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2996 11:31:10.476317 # ok 1269 Set SVE VL 5072
2997 11:31:10.476405 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
2998 11:31:10.476492 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
2999 11:31:10.476598 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3000 11:31:10.476689 # ok 1273 Set SVE VL 5088
3001 11:31:10.476776 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3002 11:31:10.477124 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3003 11:31:10.477223 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3004 11:31:10.477309 # ok 1277 Set SVE VL 5104
3005 11:31:10.477402 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3006 11:31:10.477480 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3007 11:31:10.477582 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3008 11:31:10.477706 # ok 1281 Set SVE VL 5120
3009 11:31:10.477806 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3010 11:31:10.477899 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3011 11:31:10.478015 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3012 11:31:10.478099 # ok 1285 Set SVE VL 5136
3013 11:31:10.478179 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3014 11:31:10.478275 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3015 11:31:10.478361 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3016 11:31:10.478446 # ok 1289 Set SVE VL 5152
3017 11:31:10.478559 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3018 11:31:10.478657 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3019 11:31:10.478774 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3020 11:31:10.478864 # ok 1293 Set SVE VL 5168
3021 11:31:10.478977 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3022 11:31:10.479068 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3023 11:31:10.479172 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3024 11:31:10.479251 # ok 1297 Set SVE VL 5184
3025 11:31:10.479336 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3026 11:31:10.479620 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3027 11:31:10.479728 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3028 11:31:10.479828 # ok 1301 Set SVE VL 5200
3029 11:31:10.479909 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3030 11:31:10.480001 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3031 11:31:10.480076 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3032 11:31:10.480154 # ok 1305 Set SVE VL 5216
3033 11:31:10.480266 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3034 11:31:10.480389 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3035 11:31:10.480482 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3036 11:31:10.480610 # ok 1309 Set SVE VL 5232
3037 11:31:10.480721 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3038 11:31:10.480829 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3039 11:31:10.481206 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3040 11:31:10.481293 # ok 1313 Set SVE VL 5248
3041 11:31:10.481377 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3042 11:31:10.481469 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3043 11:31:10.481596 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3044 11:31:10.481692 # ok 1317 Set SVE VL 5264
3045 11:31:10.481791 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3046 11:31:10.481907 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3047 11:31:10.482005 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3048 11:31:10.482100 # ok 1321 Set SVE VL 5280
3049 11:31:10.482199 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3050 11:31:10.482277 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3051 11:31:10.482341 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3052 11:31:10.482408 # ok 1325 Set SVE VL 5296
3053 11:31:10.482475 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3054 11:31:10.482549 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3055 11:31:10.482634 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3056 11:31:10.482714 # ok 1329 Set SVE VL 5312
3057 11:31:10.482790 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3058 11:31:10.482852 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3059 11:31:10.482933 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3060 11:31:10.483007 # ok 1333 Set SVE VL 5328
3061 11:31:10.483103 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3062 11:31:10.483188 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3063 11:31:10.483282 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3064 11:31:10.483381 # ok 1337 Set SVE VL 5344
3065 11:31:10.483505 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3066 11:31:10.483601 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3067 11:31:10.483678 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3068 11:31:10.483774 # ok 1341 Set SVE VL 5360
3069 11:31:10.483849 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3070 11:31:10.483940 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3071 11:31:10.484024 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3072 11:31:10.484116 # ok 1345 Set SVE VL 5376
3073 11:31:10.484221 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3074 11:31:10.484317 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3075 11:31:10.484664 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3076 11:31:10.484888 # ok 1349 Set SVE VL 5392
3077 11:31:10.485109 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3078 11:31:10.485252 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3079 11:31:10.485397 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3080 11:31:10.485549 # ok 1353 Set SVE VL 5408
3081 11:31:10.485726 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3082 11:31:10.485889 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3083 11:31:10.486087 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3084 11:31:10.486224 # ok 1357 Set SVE VL 5424
3085 11:31:10.486353 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3086 11:31:10.486506 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3087 11:31:10.486669 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3088 11:31:10.486808 # ok 1361 Set SVE VL 5440
3089 11:31:10.486923 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3090 11:31:10.487070 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3091 11:31:10.487214 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3092 11:31:10.487342 # ok 1365 Set SVE VL 5456
3093 11:31:10.487475 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3094 11:31:10.487681 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3095 11:31:10.487805 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3096 11:31:10.487967 # ok 1369 Set SVE VL 5472
3097 11:31:10.488113 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3098 11:31:10.488270 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3099 11:31:10.488424 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3100 11:31:10.488543 # ok 1373 Set SVE VL 5488
3101 11:31:10.488659 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3102 11:31:10.488774 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3103 11:31:10.488895 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3104 11:31:10.489012 # ok 1377 Set SVE VL 5504
3105 11:31:10.489137 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3106 11:31:10.489256 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3107 11:31:10.489353 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3108 11:31:10.489462 # ok 1381 Set SVE VL 5520
3109 11:31:10.489552 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3110 11:31:10.489690 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3111 11:31:10.489852 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3112 11:31:10.489996 # ok 1385 Set SVE VL 5536
3113 11:31:10.490122 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3114 11:31:10.490216 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3115 11:31:10.490309 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3116 11:31:10.490403 # ok 1389 Set SVE VL 5552
3117 11:31:10.490495 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3118 11:31:10.490760 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3119 11:31:10.490831 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3120 11:31:10.490905 # ok 1393 Set SVE VL 5568
3121 11:31:10.490978 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3122 11:31:10.491051 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3123 11:31:10.491124 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3124 11:31:10.491205 # ok 1397 Set SVE VL 5584
3125 11:31:10.491277 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3126 11:31:10.491350 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3127 11:31:10.491424 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3128 11:31:10.491497 # ok 1401 Set SVE VL 5600
3129 11:31:10.491570 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3130 11:31:10.491643 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3131 11:31:10.491716 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3132 11:31:10.491792 # ok 1405 Set SVE VL 5616
3133 11:31:10.491865 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3134 11:31:10.507893 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3135 11:31:10.508023 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3136 11:31:10.508144 # ok 1409 Set SVE VL 5632
3137 11:31:10.518566 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3138 11:31:10.518820 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3139 11:31:10.519259 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3140 11:31:10.519407 # ok 1413 Set SVE VL 5648
3141 11:31:10.519525 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3142 11:31:10.519642 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3143 11:31:10.519753 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3144 11:31:10.519863 # ok 1417 Set SVE VL 5664
3145 11:31:10.519984 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3146 11:31:10.520135 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3147 11:31:10.520264 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3148 11:31:10.520358 # ok 1421 Set SVE VL 5680
3149 11:31:10.520444 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3150 11:31:10.520532 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3151 11:31:10.520616 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3152 11:31:10.520702 # ok 1425 Set SVE VL 5696
3153 11:31:10.520786 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3154 11:31:10.520873 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3155 11:31:10.522214 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3156 11:31:10.522571 # ok 1429 Set SVE VL 5712
3157 11:31:10.522709 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3158 11:31:10.522818 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3159 11:31:10.522958 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3160 11:31:10.523080 # ok 1433 Set SVE VL 5728
3161 11:31:10.523199 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3162 11:31:10.523359 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3163 11:31:10.523551 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3164 11:31:10.523717 # ok 1437 Set SVE VL 5744
3165 11:31:10.523879 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3166 11:31:10.524030 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3167 11:31:10.524196 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3168 11:31:10.524327 # ok 1441 Set SVE VL 5760
3169 11:31:10.524471 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3170 11:31:10.524593 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3171 11:31:10.524709 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3172 11:31:10.524852 # ok 1445 Set SVE VL 5776
3173 11:31:10.525107 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3174 11:31:10.525339 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3175 11:31:10.525607 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3176 11:31:10.525824 # ok 1449 Set SVE VL 5792
3177 11:31:10.525974 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3178 11:31:10.526132 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3179 11:31:10.526345 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3180 11:31:10.526542 # ok 1453 Set SVE VL 5808
3181 11:31:10.526788 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3182 11:31:10.526986 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3183 11:31:10.527167 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3184 11:31:10.527314 # ok 1457 Set SVE VL 5824
3185 11:31:10.527473 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3186 11:31:10.527693 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3187 11:31:10.527877 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3188 11:31:10.528085 # ok 1461 Set SVE VL 5840
3189 11:31:10.528235 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3190 11:31:10.528356 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3191 11:31:10.528503 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3192 11:31:10.528629 # ok 1465 Set SVE VL 5856
3193 11:31:10.528823 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3194 11:31:10.529014 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3195 11:31:10.529232 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3196 11:31:10.529410 # ok 1469 Set SVE VL 5872
3197 11:31:10.529583 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3198 11:31:10.529801 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3199 11:31:10.530237 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3200 11:31:10.530487 # ok 1473 Set SVE VL 5888
3201 11:31:10.530722 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3202 11:31:10.530912 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3203 11:31:10.531147 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3204 11:31:10.531321 # ok 1477 Set SVE VL 5904
3205 11:31:10.531448 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3206 11:31:10.531562 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3207 11:31:10.531671 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3208 11:31:10.531782 # ok 1481 Set SVE VL 5920
3209 11:31:10.531910 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3210 11:31:10.532045 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3211 11:31:10.532149 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3212 11:31:10.532243 # ok 1485 Set SVE VL 5936
3213 11:31:10.532330 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3214 11:31:10.532416 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3215 11:31:10.532521 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3216 11:31:10.532679 # ok 1489 Set SVE VL 5952
3217 11:31:10.532833 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3218 11:31:10.532959 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3219 11:31:10.533104 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3220 11:31:10.533226 # ok 1493 Set SVE VL 5968
3221 11:31:10.533344 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3222 11:31:10.533458 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3223 11:31:10.533580 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3224 11:31:10.534192 # ok 1497 Set SVE VL 5984
3225 11:31:10.534280 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3226 11:31:10.534376 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3227 11:31:10.534470 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3228 11:31:10.534548 # ok 1501 Set SVE VL 6000
3229 11:31:10.534621 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3230 11:31:10.534702 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3231 11:31:10.534791 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3232 11:31:10.534874 # ok 1505 Set SVE VL 6016
3233 11:31:10.534952 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3234 11:31:10.535027 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3235 11:31:10.535103 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3236 11:31:10.535176 # ok 1509 Set SVE VL 6032
3237 11:31:10.535254 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3238 11:31:10.535328 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3239 11:31:10.535404 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3240 11:31:10.535481 # ok 1513 Set SVE VL 6048
3241 11:31:10.535577 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3242 11:31:10.535867 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3243 11:31:10.535983 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3244 11:31:10.536075 # ok 1517 Set SVE VL 6064
3245 11:31:10.536151 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3246 11:31:10.536213 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3247 11:31:10.536330 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3248 11:31:10.536445 # ok 1521 Set SVE VL 6080
3249 11:31:10.536615 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3250 11:31:10.536821 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3251 11:31:10.537003 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3252 11:31:10.537175 # ok 1525 Set SVE VL 6096
3253 11:31:10.537355 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3254 11:31:10.537565 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3255 11:31:10.537806 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3256 11:31:10.537980 # ok 1529 Set SVE VL 6112
3257 11:31:10.538121 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3258 11:31:10.538242 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3259 11:31:10.538334 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3260 11:31:10.538431 # ok 1533 Set SVE VL 6128
3261 11:31:10.538564 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3262 11:31:10.538700 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3263 11:31:10.538809 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3264 11:31:10.538926 # ok 1537 Set SVE VL 6144
3265 11:31:10.539035 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3266 11:31:10.539135 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3267 11:31:10.539243 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3268 11:31:10.539418 # ok 1541 Set SVE VL 6160
3269 11:31:10.539552 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3270 11:31:10.539679 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3271 11:31:10.539807 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3272 11:31:10.539915 # ok 1545 Set SVE VL 6176
3273 11:31:10.540011 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3274 11:31:10.540104 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3275 11:31:10.540191 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3276 11:31:10.540290 # ok 1549 Set SVE VL 6192
3277 11:31:10.540388 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3278 11:31:10.540508 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3279 11:31:10.540624 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3280 11:31:10.540734 # ok 1553 Set SVE VL 6208
3281 11:31:10.540913 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3282 11:31:10.541077 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3283 11:31:10.541236 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3284 11:31:10.541323 # ok 1557 Set SVE VL 6224
3285 11:31:10.541993 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3286 11:31:10.542076 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3287 11:31:10.542140 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3288 11:31:10.542201 # ok 1561 Set SVE VL 6240
3289 11:31:10.542261 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3290 11:31:10.542321 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3291 11:31:10.542382 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3292 11:31:10.542442 # ok 1565 Set SVE VL 6256
3293 11:31:10.542501 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3294 11:31:10.542561 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3295 11:31:10.542621 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3296 11:31:10.542681 # ok 1569 Set SVE VL 6272
3297 11:31:10.542741 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3298 11:31:10.542801 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3299 11:31:10.542861 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3300 11:31:10.542920 # ok 1573 Set SVE VL 6288
3301 11:31:10.542980 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3302 11:31:10.543041 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3303 11:31:10.543101 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3304 11:31:10.543161 # ok 1577 Set SVE VL 6304
3305 11:31:10.543221 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3306 11:31:10.543281 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3307 11:31:10.543340 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3308 11:31:10.543400 # ok 1581 Set SVE VL 6320
3309 11:31:10.543459 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3310 11:31:10.543519 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3311 11:31:10.543584 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3312 11:31:10.543688 # ok 1585 Set SVE VL 6336
3313 11:31:10.543790 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3314 11:31:10.543887 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3315 11:31:10.543956 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3316 11:31:10.544024 # ok 1589 Set SVE VL 6352
3317 11:31:10.544101 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3318 11:31:10.544162 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3319 11:31:10.544221 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3320 11:31:10.544280 # ok 1593 Set SVE VL 6368
3321 11:31:10.544563 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3322 11:31:10.544692 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3323 11:31:10.544801 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3324 11:31:10.545321 # ok 1597 Set SVE VL 6384
3325 11:31:10.545431 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3326 11:31:10.545519 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3327 11:31:10.545605 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3328 11:31:10.545698 # ok 1601 Set SVE VL 6400
3329 11:31:10.545785 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3330 11:31:10.545871 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3331 11:31:10.546187 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3332 11:31:10.546293 # ok 1605 Set SVE VL 6416
3333 11:31:10.546381 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3334 11:31:10.546466 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3335 11:31:10.546550 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3336 11:31:10.546634 # ok 1609 Set SVE VL 6432
3337 11:31:10.546717 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3338 11:31:10.546801 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3339 11:31:10.546907 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3340 11:31:10.546995 # ok 1613 Set SVE VL 6448
3341 11:31:10.547080 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3342 11:31:10.547167 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3343 11:31:10.547252 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3344 11:31:10.547336 # ok 1617 Set SVE VL 6464
3345 11:31:10.547420 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3346 11:31:10.547503 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3347 11:31:10.547604 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3348 11:31:10.547689 # ok 1621 Set SVE VL 6480
3349 11:31:10.547770 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3350 11:31:10.547852 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3351 11:31:10.547938 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3352 11:31:10.548022 # ok 1625 Set SVE VL 6496
3353 11:31:10.548124 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3354 11:31:10.548209 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3355 11:31:10.548292 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3356 11:31:10.548375 # ok 1629 Set SVE VL 6512
3357 11:31:10.548458 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3358 11:31:10.548565 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3359 11:31:10.548649 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3360 11:31:10.548732 # ok 1633 Set SVE VL 6528
3361 11:31:10.548813 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3362 11:31:10.548910 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3363 11:31:10.548993 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3364 11:31:10.549077 # ok 1637 Set SVE VL 6544
3365 11:31:10.549160 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3366 11:31:10.549262 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3367 11:31:10.549348 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3368 11:31:10.549433 # ok 1641 Set SVE VL 6560
3369 11:31:10.549531 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3370 11:31:10.549616 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3371 11:31:10.550190 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3372 11:31:10.550298 # ok 1645 Set SVE VL 6576
3373 11:31:10.550388 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3374 11:31:10.550683 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3375 11:31:10.550793 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3376 11:31:10.550879 # ok 1649 Set SVE VL 6592
3377 11:31:10.550963 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3378 11:31:10.551046 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3379 11:31:10.551130 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3380 11:31:10.551213 # ok 1653 Set SVE VL 6608
3381 11:31:10.551298 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3382 11:31:10.551384 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3383 11:31:10.551469 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3384 11:31:10.551570 # ok 1657 Set SVE VL 6624
3385 11:31:10.551656 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3386 11:31:10.551740 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3387 11:31:10.551824 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3388 11:31:10.551910 # ok 1661 Set SVE VL 6640
3389 11:31:10.551993 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3390 11:31:10.552075 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3391 11:31:10.552176 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3392 11:31:10.552261 # ok 1665 Set SVE VL 6656
3393 11:31:10.552345 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3394 11:31:10.552427 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3395 11:31:10.552509 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3396 11:31:10.552594 # ok 1669 Set SVE VL 6672
3397 11:31:10.552694 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3398 11:31:10.552780 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3399 11:31:10.552863 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3400 11:31:10.552945 # ok 1673 Set SVE VL 6688
3401 11:31:10.553027 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3402 11:31:10.553128 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3403 11:31:10.553215 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3404 11:31:10.553298 # ok 1677 Set SVE VL 6704
3405 11:31:10.553397 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3406 11:31:10.553482 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3407 11:31:10.553580 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3408 11:31:10.554166 # ok 1681 Set SVE VL 6720
3409 11:31:10.554293 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3410 11:31:10.554384 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3411 11:31:10.554472 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3412 11:31:10.554562 # ok 1685 Set SVE VL 6736
3413 11:31:10.554647 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3414 11:31:10.554730 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3415 11:31:10.554814 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3416 11:31:10.555102 # ok 1689 Set SVE VL 6752
3417 11:31:10.555206 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3418 11:31:10.555291 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3419 11:31:10.555374 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3420 11:31:10.555455 # ok 1693 Set SVE VL 6768
3421 11:31:10.555542 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3422 11:31:10.555629 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3423 11:31:10.555714 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3424 11:31:10.555799 # ok 1697 Set SVE VL 6784
3425 11:31:10.555905 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3426 11:31:10.555994 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3427 11:31:10.556081 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3428 11:31:10.556166 # ok 1701 Set SVE VL 6800
3429 11:31:10.556248 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3430 11:31:10.556328 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3431 11:31:10.556409 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3432 11:31:10.556488 # ok 1705 Set SVE VL 6816
3433 11:31:10.556586 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3434 11:31:10.556673 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3435 11:31:10.556754 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3436 11:31:10.556836 # ok 1709 Set SVE VL 6832
3437 11:31:10.556920 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3438 11:31:10.557022 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3439 11:31:10.557105 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3440 11:31:10.557188 # ok 1713 Set SVE VL 6848
3441 11:31:10.557277 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3442 11:31:10.557361 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3443 11:31:10.557463 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3444 11:31:10.557549 # ok 1717 Set SVE VL 6864
3445 11:31:10.557633 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3446 11:31:10.557725 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3447 11:31:10.557810 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3448 11:31:10.557895 # ok 1721 Set SVE VL 6880
3449 11:31:10.557996 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3450 11:31:10.558079 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3451 11:31:10.558160 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3452 11:31:10.558246 # ok 1725 Set SVE VL 6896
3453 11:31:10.558330 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3454 11:31:10.558431 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3455 11:31:10.558518 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3456 11:31:10.558601 # ok 1729 Set SVE VL 6912
3457 11:31:10.558684 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3458 11:31:10.558782 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3459 11:31:10.559124 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3460 11:31:10.559285 # ok 1733 Set SVE VL 6928
3461 11:31:10.559411 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3462 11:31:10.559558 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3463 11:31:10.559699 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3464 11:31:10.559877 # ok 1737 Set SVE VL 6944
3465 11:31:10.560009 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3466 11:31:10.560124 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3467 11:31:10.560230 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3468 11:31:10.560348 # ok 1741 Set SVE VL 6960
3469 11:31:10.560463 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3470 11:31:10.560577 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3471 11:31:10.560694 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3472 11:31:10.560813 # ok 1745 Set SVE VL 6976
3473 11:31:10.560958 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3474 11:31:10.561076 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3475 11:31:10.561195 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3476 11:31:10.561279 # ok 1749 Set SVE VL 6992
3477 11:31:10.561357 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3478 11:31:10.561434 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3479 11:31:10.561511 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3480 11:31:10.561592 # ok 1753 Set SVE VL 7008
3481 11:31:10.561697 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3482 11:31:10.561781 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3483 11:31:10.561866 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3484 11:31:10.561963 # ok 1757 Set SVE VL 7024
3485 11:31:10.562042 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3486 11:31:10.562116 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3487 11:31:10.562215 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3488 11:31:10.562303 # ok 1761 Set SVE VL 7040
3489 11:31:10.562396 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3490 11:31:10.562484 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3491 11:31:10.562576 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3492 11:31:10.562676 # ok 1765 Set SVE VL 7056
3493 11:31:10.562766 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3494 11:31:10.562865 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3495 11:31:10.562951 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3496 11:31:10.563049 # ok 1769 Set SVE VL 7072
3497 11:31:10.563131 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3498 11:31:10.563200 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3499 11:31:10.563278 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3500 11:31:10.565305 # ok 1773 Set SVE VL 7088
3501 11:31:10.565416 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3502 11:31:10.565519 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3503 11:31:10.565610 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3504 11:31:10.565705 # ok 1777 Set SVE VL 7104
3505 11:31:10.565809 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3506 11:31:10.565897 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3507 11:31:10.565982 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3508 11:31:10.566067 # ok 1781 Set SVE VL 7120
3509 11:31:10.566171 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3510 11:31:10.566266 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3511 11:31:10.566353 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3512 11:31:10.566455 # ok 1785 Set SVE VL 7136
3513 11:31:10.566542 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3514 11:31:10.566627 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3515 11:31:10.566731 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3516 11:31:10.566822 # ok 1789 Set SVE VL 7152
3517 11:31:10.566909 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3518 11:31:10.567013 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3519 11:31:10.567099 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3520 11:31:10.567183 # ok 1793 Set SVE VL 7168
3521 11:31:10.567294 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3522 11:31:10.567383 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3523 11:31:10.567469 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3524 11:31:10.567570 # ok 1797 Set SVE VL 7184
3525 11:31:10.567659 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3526 11:31:10.567744 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3527 11:31:10.567849 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3528 11:31:10.567939 # ok 1801 Set SVE VL 7200
3529 11:31:10.568039 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3530 11:31:10.568125 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3531 11:31:10.568526 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3532 11:31:10.568929 # ok 1805 Set SVE VL 7216
3533 11:31:10.569024 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3534 11:31:10.569104 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3535 11:31:10.569198 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3536 11:31:10.569275 # ok 1809 Set SVE VL 7232
3537 11:31:10.569353 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3538 11:31:10.569446 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3539 11:31:10.569527 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3540 11:31:10.569607 # ok 1813 Set SVE VL 7248
3541 11:31:10.569722 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3542 11:31:10.569806 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3543 11:31:10.569896 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3544 11:31:10.569968 # ok 1817 Set SVE VL 7264
3545 11:31:10.570074 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3546 11:31:10.570176 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3547 11:31:10.570269 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3548 11:31:10.570368 # ok 1821 Set SVE VL 7280
3549 11:31:10.570471 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3550 11:31:10.570755 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3551 11:31:10.570864 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3552 11:31:10.570948 # ok 1825 Set SVE VL 7296
3553 11:31:10.571044 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3554 11:31:10.571126 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3555 11:31:10.571206 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3556 11:31:10.571287 # ok 1829 Set SVE VL 7312
3557 11:31:10.571382 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3558 11:31:10.571462 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3559 11:31:10.571552 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3560 11:31:10.571625 # ok 1833 Set SVE VL 7328
3561 11:31:10.571714 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3562 11:31:10.571977 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3563 11:31:10.572108 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3564 11:31:10.572210 # ok 1837 Set SVE VL 7344
3565 11:31:10.572295 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3566 11:31:10.572394 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3567 11:31:10.572473 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3568 11:31:10.572544 # ok 1841 Set SVE VL 7360
3569 11:31:10.572623 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3570 11:31:10.572704 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3571 11:31:10.572795 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3572 11:31:10.572870 # ok 1845 Set SVE VL 7376
3573 11:31:10.572948 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3574 11:31:10.573043 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3575 11:31:10.573132 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3576 11:31:10.573212 # ok 1849 Set SVE VL 7392
3577 11:31:10.573309 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3578 11:31:10.573402 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3579 11:31:10.573776 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3580 11:31:10.573866 # ok 1853 Set SVE VL 7408
3581 11:31:10.573940 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3582 11:31:10.574026 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3583 11:31:10.574105 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3584 11:31:10.574199 # ok 1857 Set SVE VL 7424
3585 11:31:10.574284 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3586 11:31:10.574372 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3587 11:31:10.574462 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3588 11:31:10.574561 # ok 1861 Set SVE VL 7440
3589 11:31:10.574657 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3590 11:31:10.574737 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3591 11:31:10.574821 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3592 11:31:10.574904 # ok 1865 Set SVE VL 7456
3593 11:31:10.575010 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3594 11:31:10.575337 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3595 11:31:10.575440 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3596 11:31:10.575543 # ok 1869 Set SVE VL 7472
3597 11:31:10.575633 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3598 11:31:10.575737 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3599 11:31:10.575872 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3600 11:31:10.575965 # ok 1873 Set SVE VL 7488
3601 11:31:10.576063 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3602 11:31:10.576147 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3603 11:31:10.577554 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3604 11:31:10.577934 # ok 1877 Set SVE VL 7504
3605 11:31:10.578037 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3606 11:31:10.578123 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3607 11:31:10.578223 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3608 11:31:10.578310 # ok 1881 Set SVE VL 7520
3609 11:31:10.578393 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3610 11:31:10.578490 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3611 11:31:10.578576 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3612 11:31:10.578659 # ok 1885 Set SVE VL 7536
3613 11:31:10.578755 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3614 11:31:10.578836 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3615 11:31:10.578933 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3616 11:31:10.579022 # ok 1889 Set SVE VL 7552
3617 11:31:10.579121 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3618 11:31:10.579203 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3619 11:31:10.579304 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3620 11:31:10.579388 # ok 1893 Set SVE VL 7568
3621 11:31:10.579471 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3622 11:31:10.579568 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3623 11:31:10.579652 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3624 11:31:10.579752 # ok 1897 Set SVE VL 7584
3625 11:31:10.579837 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3626 11:31:10.579939 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3627 11:31:10.580041 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3628 11:31:10.580128 # ok 1901 Set SVE VL 7600
3629 11:31:10.580412 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3630 11:31:10.580529 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3631 11:31:10.580826 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3632 11:31:10.580925 # ok 1905 Set SVE VL 7616
3633 11:31:10.581012 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3634 11:31:10.581097 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3635 11:31:10.581198 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3636 11:31:10.581286 # ok 1909 Set SVE VL 7632
3637 11:31:10.581370 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3638 11:31:10.581469 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3639 11:31:10.581556 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3640 11:31:10.581662 # ok 1913 Set SVE VL 7648
3641 11:31:10.581748 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3642 11:31:10.581845 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3643 11:31:10.581943 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3644 11:31:10.582026 # ok 1917 Set SVE VL 7664
3645 11:31:10.582119 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3646 11:31:10.582217 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3647 11:31:10.582328 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3648 11:31:10.582426 # ok 1921 Set SVE VL 7680
3649 11:31:10.582523 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3650 11:31:10.582817 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3651 11:31:10.582919 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3652 11:31:10.583016 # ok 1925 Set SVE VL 7696
3653 11:31:10.583117 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3654 11:31:10.583200 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3655 11:31:10.583297 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3656 11:31:10.583382 # ok 1929 Set SVE VL 7712
3657 11:31:10.583477 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3658 11:31:10.583574 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3659 11:31:10.583672 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3660 11:31:10.583757 # ok 1933 Set SVE VL 7728
3661 11:31:10.583855 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3662 11:31:10.583955 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3663 11:31:10.584055 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3664 11:31:10.584157 # ok 1937 Set SVE VL 7744
3665 11:31:10.584451 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3666 11:31:10.584546 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3667 11:31:10.584647 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3668 11:31:10.584733 # ok 1941 Set SVE VL 7760
3669 11:31:10.584833 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3670 11:31:10.584933 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3671 11:31:10.585033 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3672 11:31:10.585133 # ok 1945 Set SVE VL 7776
3673 11:31:10.585233 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3674 11:31:10.585324 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3675 11:31:10.585423 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3676 11:31:10.585509 # ok 1949 Set SVE VL 7792
3677 11:31:10.585607 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3678 11:31:10.585718 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3679 11:31:10.585819 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3680 11:31:10.585919 # ok 1953 Set SVE VL 7808
3681 11:31:10.586018 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3682 11:31:10.586118 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3683 11:31:10.588815 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3684 11:31:10.588921 # ok 1957 Set SVE VL 7824
3685 11:31:10.589021 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3686 11:31:10.589106 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3687 11:31:10.589204 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3688 11:31:10.589764 # ok 1961 Set SVE VL 7840
3689 11:31:10.589894 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3690 11:31:10.589983 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3691 11:31:10.590062 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3692 11:31:10.590163 # ok 1965 Set SVE VL 7856
3693 11:31:10.590259 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3694 11:31:10.590560 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3695 11:31:10.590669 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3696 11:31:10.590778 # ok 1969 Set SVE VL 7872
3697 11:31:10.590864 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3698 11:31:10.590946 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3699 11:31:10.591028 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3700 11:31:10.591093 # ok 1973 Set SVE VL 7888
3701 11:31:10.591171 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3702 11:31:10.591249 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3703 11:31:10.591332 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3704 11:31:10.591412 # ok 1977 Set SVE VL 7904
3705 11:31:10.591489 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3706 11:31:10.591566 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3707 11:31:10.591660 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3708 11:31:10.591741 # ok 1981 Set SVE VL 7920
3709 11:31:10.591833 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3710 11:31:10.591935 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3711 11:31:10.592029 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3712 11:31:10.592119 # ok 1985 Set SVE VL 7936
3713 11:31:10.592184 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3714 11:31:10.592254 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3715 11:31:10.592331 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3716 11:31:10.592406 # ok 1989 Set SVE VL 7952
3717 11:31:10.592500 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3718 11:31:10.592574 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3719 11:31:10.592638 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3720 11:31:10.592719 # ok 1993 Set SVE VL 7968
3721 11:31:10.592793 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3722 11:31:10.592877 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3723 11:31:10.592954 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3724 11:31:10.593040 # ok 1997 Set SVE VL 7984
3725 11:31:10.593126 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3726 11:31:10.593206 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3727 11:31:10.593479 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3728 11:31:10.593583 # ok 2001 Set SVE VL 8000
3729 11:31:10.593691 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3730 11:31:10.593783 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3731 11:31:10.593886 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3732 11:31:10.597829 # ok 2005 Set SVE VL 8016
3733 11:31:10.597939 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3734 11:31:10.598026 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3735 11:31:10.598110 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3736 11:31:10.598194 # ok 2009 Set SVE VL 8032
3737 11:31:10.598277 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3738 11:31:10.598362 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3739 11:31:10.598443 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3740 11:31:10.598525 # ok 2013 Set SVE VL 8048
3741 11:31:10.598608 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3742 11:31:10.598691 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3743 11:31:10.598775 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3744 11:31:10.598858 # ok 2017 Set SVE VL 8064
3745 11:31:10.598940 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3746 11:31:10.599022 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3747 11:31:10.599106 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3748 11:31:10.599187 # ok 2021 Set SVE VL 8080
3749 11:31:10.599270 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3750 11:31:10.599359 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3751 11:31:10.599442 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3752 11:31:10.599526 # ok 2025 Set SVE VL 8096
3753 11:31:10.599608 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3754 11:31:10.599691 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3755 11:31:10.599774 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3756 11:31:10.599857 # ok 2029 Set SVE VL 8112
3757 11:31:10.599941 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3758 11:31:10.600027 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3759 11:31:10.600109 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3760 11:31:10.600196 # ok 2033 Set SVE VL 8128
3761 11:31:10.600280 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3762 11:31:10.600368 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3763 11:31:10.600450 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3764 11:31:10.600534 # ok 2037 Set SVE VL 8144
3765 11:31:10.600616 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3766 11:31:10.600699 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3767 11:31:10.600783 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3768 11:31:10.600866 # ok 2041 Set SVE VL 8160
3769 11:31:10.600949 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3770 11:31:10.601031 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3771 11:31:10.601115 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3772 11:31:10.601196 # ok 2045 Set SVE VL 8176
3773 11:31:10.601277 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3774 11:31:10.601364 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3775 11:31:10.601673 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3776 11:31:10.601782 # ok 2049 Set SVE VL 8192
3777 11:31:10.601879 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3778 11:31:10.601963 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3779 11:31:10.602054 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3780 11:31:10.602152 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3781 11:31:10.602238 # ok 2054 Streaming SVE get_fpsimd() gave same state
3782 11:31:10.602330 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3783 11:31:10.602437 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3784 11:31:10.602519 # ok 2057 Set Streaming SVE VL 16
3785 11:31:10.602600 # ok 2058 Set and get Streaming SVE data for VL 16
3786 11:31:10.602679 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3787 11:31:10.602763 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3788 11:31:10.602856 # ok 2061 Set Streaming SVE VL 32
3789 11:31:10.602943 # ok 2062 Set and get Streaming SVE data for VL 32
3790 11:31:10.603024 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3791 11:31:10.603105 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3792 11:31:10.603183 # ok 2065 Set Streaming SVE VL 48
3793 11:31:10.603264 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3794 11:31:10.603372 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3795 11:31:10.603470 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3796 11:31:10.603559 # ok 2069 Set Streaming SVE VL 64
3797 11:31:10.603643 # ok 2070 Set and get Streaming SVE data for VL 64
3798 11:31:10.603730 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3799 11:31:10.603863 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3800 11:31:10.603963 # ok 2073 Set Streaming SVE VL 80
3801 11:31:10.604066 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3802 11:31:10.604141 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3803 11:31:10.604225 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3804 11:31:10.604322 # ok 2077 Set Streaming SVE VL 96
3805 11:31:10.604403 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3806 11:31:10.604483 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3807 11:31:10.604558 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3808 11:31:10.604638 # ok 2081 Set Streaming SVE VL 112
3809 11:31:10.604718 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3810 11:31:10.604820 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3811 11:31:10.604901 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3812 11:31:10.604984 # ok 2085 Set Streaming SVE VL 128
3813 11:31:10.605273 # ok 2086 Set and get Streaming SVE data for VL 128
3814 11:31:10.605378 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3815 11:31:10.605463 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3816 11:31:10.605547 # ok 2089 Set Streaming SVE VL 144
3817 11:31:10.605629 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3818 11:31:10.605717 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3819 11:31:10.605795 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3820 11:31:10.605875 # ok 2093 Set Streaming SVE VL 160
3821 11:31:10.605941 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3822 11:31:10.606018 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3823 11:31:10.606097 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3824 11:31:10.606175 # ok 2097 Set Streaming SVE VL 176
3825 11:31:10.606252 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3826 11:31:10.606333 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3827 11:31:10.606402 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3828 11:31:10.606462 # ok 2101 Set Streaming SVE VL 192
3829 11:31:10.606522 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3830 11:31:10.606581 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3831 11:31:10.606640 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3832 11:31:10.606697 # ok 2105 Set Streaming SVE VL 208
3833 11:31:10.606755 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3834 11:31:10.606814 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3835 11:31:10.606872 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3836 11:31:10.606931 # ok 2109 Set Streaming SVE VL 224
3837 11:31:10.606989 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3838 11:31:10.607047 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3839 11:31:10.607104 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3840 11:31:10.607163 # ok 2113 Set Streaming SVE VL 240
3841 11:31:10.607221 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3842 11:31:10.607279 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3843 11:31:10.607342 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3844 11:31:10.607415 # ok 2117 Set Streaming SVE VL 256
3845 11:31:10.607477 # ok 2118 Set and get Streaming SVE data for VL 256
3846 11:31:10.607536 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3847 11:31:10.607595 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3848 11:31:10.607653 # ok 2121 Set Streaming SVE VL 272
3849 11:31:10.607894 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3850 11:31:10.607958 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3851 11:31:10.608017 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3852 11:31:10.608076 # ok 2125 Set Streaming SVE VL 288
3853 11:31:10.609878 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3854 11:31:10.609976 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3855 11:31:10.610262 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3856 11:31:10.610345 # ok 2129 Set Streaming SVE VL 304
3857 11:31:10.610409 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3858 11:31:10.610684 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3859 11:31:10.610779 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3860 11:31:10.610858 # ok 2133 Set Streaming SVE VL 320
3861 11:31:10.610950 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3862 11:31:10.611054 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3863 11:31:10.611148 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3864 11:31:10.611228 # ok 2137 Set Streaming SVE VL 336
3865 11:31:10.611322 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3866 11:31:10.611406 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3867 11:31:10.611482 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3868 11:31:10.611573 # ok 2141 Set Streaming SVE VL 352
3869 11:31:10.611651 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3870 11:31:10.611750 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3871 11:31:10.611844 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3872 11:31:10.611938 # ok 2145 Set Streaming SVE VL 368
3873 11:31:10.612027 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3874 11:31:10.612514 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3875 11:31:10.612814 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3876 11:31:10.612911 # ok 2149 Set Streaming SVE VL 384
3877 11:31:10.612994 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3878 11:31:10.613084 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3879 11:31:10.613373 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3880 11:31:10.613463 # ok 2153 Set Streaming SVE VL 400
3881 11:31:10.613536 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3882 11:31:10.613669 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3883 11:31:10.613769 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3884 11:31:10.613889 # ok 2157 Set Streaming SVE VL 416
3885 11:31:10.613985 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3886 11:31:10.614107 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3887 11:31:10.614228 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3888 11:31:10.614328 # ok 2161 Set Streaming SVE VL 432
3889 11:31:10.614455 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3890 11:31:10.614547 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3891 11:31:10.614669 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3892 11:31:10.614773 # ok 2165 Set Streaming SVE VL 448
3893 11:31:10.614894 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3894 11:31:10.615000 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3895 11:31:10.615125 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3896 11:31:10.615229 # ok 2169 Set Streaming SVE VL 464
3897 11:31:10.615359 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3898 11:31:10.615490 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3899 11:31:10.615605 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3900 11:31:10.615690 # ok 2173 Set Streaming SVE VL 480
3901 11:31:10.615793 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3902 11:31:10.615948 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3903 11:31:10.616060 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3904 11:31:10.616360 # ok 2177 Set Streaming SVE VL 496
3905 11:31:10.616506 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3906 11:31:10.616685 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3907 11:31:10.616825 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3908 11:31:10.616971 # ok 2181 Set Streaming SVE VL 512
3909 11:31:10.617097 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3910 11:31:10.617219 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3911 11:31:10.617365 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3912 11:31:10.617507 # ok 2185 Set Streaming SVE VL 528
3913 11:31:10.617682 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3914 11:31:10.617863 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3915 11:31:10.618014 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3916 11:31:10.618168 # ok 2189 Set Streaming SVE VL 544
3917 11:31:10.618316 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3918 11:31:10.618405 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3919 11:31:10.618482 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3920 11:31:10.618559 # ok 2193 Set Streaming SVE VL 560
3921 11:31:10.618660 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3922 11:31:10.618762 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3923 11:31:10.618890 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3924 11:31:10.618989 # ok 2197 Set Streaming SVE VL 576
3925 11:31:10.619084 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3926 11:31:10.619186 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3927 11:31:10.619259 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3928 11:31:10.619368 # ok 2201 Set Streaming SVE VL 592
3929 11:31:10.619463 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3930 11:31:10.619537 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3931 11:31:10.619634 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3932 11:31:10.619726 # ok 2205 Set Streaming SVE VL 608
3933 11:31:10.619817 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3934 11:31:10.619945 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3935 11:31:10.620034 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3936 11:31:10.620105 # ok 2209 Set Streaming SVE VL 624
3937 11:31:10.620214 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3938 11:31:10.620311 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3939 11:31:10.620406 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3940 11:31:10.620681 # ok 2213 Set Streaming SVE VL 640
3941 11:31:10.620873 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3942 11:31:10.620983 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3943 11:31:10.621090 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3944 11:31:10.621180 # ok 2217 Set Streaming SVE VL 656
3945 11:31:10.621307 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3946 11:31:10.621434 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3947 11:31:10.621531 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3948 11:31:10.621622 # ok 2221 Set Streaming SVE VL 672
3949 11:31:10.621736 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3950 11:31:10.621819 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3951 11:31:10.621903 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3952 11:31:10.622002 # ok 2225 Set Streaming SVE VL 688
3953 11:31:10.622113 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3954 11:31:10.622204 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3955 11:31:10.622299 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3956 11:31:10.622380 # ok 2229 Set Streaming SVE VL 704
3957 11:31:10.622471 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3958 11:31:10.622555 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3959 11:31:10.622651 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3960 11:31:10.622733 # ok 2233 Set Streaming SVE VL 720
3961 11:31:10.622819 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3962 11:31:10.622906 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3963 11:31:10.623211 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3964 11:31:10.623296 # ok 2237 Set Streaming SVE VL 736
3965 11:31:10.623380 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3966 11:31:10.623463 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3967 11:31:10.623761 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3968 11:31:10.623868 # ok 2241 Set Streaming SVE VL 752
3969 11:31:10.623987 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3970 11:31:10.624079 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3971 11:31:10.624191 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3972 11:31:10.624303 # ok 2245 Set Streaming SVE VL 768
3973 11:31:10.624389 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3974 11:31:10.624498 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3975 11:31:10.624602 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3976 11:31:10.624717 # ok 2249 Set Streaming SVE VL 784
3977 11:31:10.624807 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3978 11:31:10.624898 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3979 11:31:10.625183 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3980 11:31:10.625278 # ok 2253 Set Streaming SVE VL 800
3981 11:31:10.625374 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3982 11:31:10.625474 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3983 11:31:10.625748 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3984 11:31:10.625842 # ok 2257 Set Streaming SVE VL 816
3985 11:31:10.625929 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3986 11:31:10.626021 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3987 11:31:10.626111 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3988 11:31:10.626219 # ok 2261 Set Streaming SVE VL 832
3989 11:31:10.626333 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3990 11:31:10.626434 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3991 11:31:10.626532 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3992 11:31:10.626639 # ok 2265 Set Streaming SVE VL 848
3993 11:31:10.626723 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3994 11:31:10.626826 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3995 11:31:10.626911 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3996 11:31:10.627011 # ok 2269 Set Streaming SVE VL 864
3997 11:31:10.627094 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
3998 11:31:10.627188 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
3999 11:31:10.627279 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4000 11:31:10.627390 # ok 2273 Set Streaming SVE VL 880
4001 11:31:10.627481 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4002 11:31:10.627606 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4003 11:31:10.627902 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4004 11:31:10.627980 # ok 2277 Set Streaming SVE VL 896
4005 11:31:10.628041 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4006 11:31:10.630237 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4007 11:31:10.630358 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4008 11:31:10.630448 # ok 2281 Set Streaming SVE VL 912
4009 11:31:10.630549 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4010 11:31:10.630649 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4011 11:31:10.630734 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4012 11:31:10.630833 # ok 2285 Set Streaming SVE VL 928
4013 11:31:10.630935 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4014 11:31:10.631023 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4015 11:31:10.631123 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4016 11:31:10.631224 # ok 2289 Set Streaming SVE VL 944
4017 11:31:10.631323 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4018 11:31:10.631424 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4019 11:31:10.631560 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4020 11:31:10.631679 # ok 2293 Set Streaming SVE VL 960
4021 11:31:10.631789 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4022 11:31:10.632074 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4023 11:31:10.632464 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4024 11:31:10.632808 # ok 2297 Set Streaming SVE VL 976
4025 11:31:10.632910 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4026 11:31:10.632996 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4027 11:31:10.633098 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4028 11:31:10.633185 # ok 2301 Set Streaming SVE VL 992
4029 11:31:10.633282 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4030 11:31:10.633384 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4031 11:31:10.633482 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4032 11:31:10.633581 # ok 2305 Set Streaming SVE VL 1008
4033 11:31:10.633685 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4034 11:31:10.633785 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4035 11:31:10.634083 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4036 11:31:10.634183 # ok 2309 Set Streaming SVE VL 1024
4037 11:31:10.634278 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4038 11:31:10.634359 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4039 11:31:10.634453 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4040 11:31:10.634549 # ok 2313 Set Streaming SVE VL 1040
4041 11:31:10.634643 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4042 11:31:10.634749 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4043 11:31:10.635002 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4044 11:31:10.635126 # ok 2317 Set Streaming SVE VL 1056
4045 11:31:10.635220 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4046 11:31:10.635344 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4047 11:31:10.635447 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4048 11:31:10.635549 # ok 2321 Set Streaming SVE VL 1072
4049 11:31:10.635662 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4050 11:31:10.635761 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4051 11:31:10.636073 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4052 11:31:10.636168 # ok 2325 Set Streaming SVE VL 1088
4053 11:31:10.636280 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4054 11:31:10.636398 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4055 11:31:10.636518 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4056 11:31:10.636623 # ok 2329 Set Streaming SVE VL 1104
4057 11:31:10.636725 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4058 11:31:10.636835 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4059 11:31:10.637134 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4060 11:31:10.637268 # ok 2333 Set Streaming SVE VL 1120
4061 11:31:10.637389 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4062 11:31:10.637487 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4063 11:31:10.637600 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4064 11:31:10.637721 # ok 2337 Set Streaming SVE VL 1136
4065 11:31:10.637834 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4066 11:31:10.637946 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4067 11:31:10.638256 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4068 11:31:10.638338 # ok 2341 Set Streaming SVE VL 1152
4069 11:31:10.638424 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4070 11:31:10.638676 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4071 11:31:10.638801 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4072 11:31:10.638913 # ok 2345 Set Streaming SVE VL 1168
4073 11:31:10.639025 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4074 11:31:10.639328 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4075 11:31:10.639436 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4076 11:31:10.639548 # ok 2349 Set Streaming SVE VL 1184
4077 11:31:10.639644 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4078 11:31:10.639755 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4079 11:31:10.639867 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4080 11:31:10.639964 # ok 2353 Set Streaming SVE VL 1200
4081 11:31:10.640074 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4082 11:31:10.640383 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4083 11:31:10.640493 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4084 11:31:10.640579 # ok 2357 Set Streaming SVE VL 1216
4085 11:31:10.640864 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4086 11:31:10.640946 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4087 11:31:10.641031 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4088 11:31:10.641109 # ok 2361 Set Streaming SVE VL 1232
4089 11:31:10.641204 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4090 11:31:10.641285 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4091 11:31:10.641365 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4092 11:31:10.641458 # ok 2365 Set Streaming SVE VL 1248
4093 11:31:10.641539 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4094 11:31:10.641618 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4095 11:31:10.641742 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4096 11:31:10.641836 # ok 2369 Set Streaming SVE VL 1264
4097 11:31:10.642113 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4098 11:31:10.642207 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4099 11:31:10.642307 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4100 11:31:10.642406 # ok 2373 Set Streaming SVE VL 1280
4101 11:31:10.642513 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4102 11:31:10.642626 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4103 11:31:10.642728 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4104 11:31:10.643026 # ok 2377 Set Streaming SVE VL 1296
4105 11:31:10.643130 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4106 11:31:10.643254 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4107 11:31:10.643350 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4108 11:31:10.643476 # ok 2381 Set Streaming SVE VL 1312
4109 11:31:10.643583 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4110 11:31:10.643702 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4111 11:31:10.643831 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4112 11:31:10.643954 # ok 2385 Set Streaming SVE VL 1328
4113 11:31:10.644067 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4114 11:31:10.644363 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4115 11:31:10.644468 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4116 11:31:10.644570 # ok 2389 Set Streaming SVE VL 1344
4117 11:31:10.644663 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4118 11:31:10.644762 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4119 11:31:10.644882 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4120 11:31:10.644995 # ok 2393 Set Streaming SVE VL 1360
4121 11:31:10.645098 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4122 11:31:10.645209 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4123 11:31:10.645319 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4124 11:31:10.645415 # ok 2397 Set Streaming SVE VL 1376
4125 11:31:10.645493 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4126 11:31:10.645747 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4127 11:31:10.645830 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4128 11:31:10.646160 # ok 2401 Set Streaming SVE VL 1392
4129 11:31:10.646257 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4130 11:31:10.646372 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4131 11:31:10.646459 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4132 11:31:10.646555 # ok 2405 Set Streaming SVE VL 1408
4133 11:31:10.646670 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4134 11:31:10.646760 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4135 11:31:10.646851 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4136 11:31:10.646940 # ok 2409 Set Streaming SVE VL 1424
4137 11:31:10.647040 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4138 11:31:10.647143 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4139 11:31:10.647242 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4140 11:31:10.647335 # ok 2413 Set Streaming SVE VL 1440
4141 11:31:10.647658 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4142 11:31:10.647751 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4143 11:31:10.647860 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4144 11:31:10.647957 # ok 2417 Set Streaming SVE VL 1456
4145 11:31:10.648062 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4146 11:31:10.648161 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4147 11:31:10.648458 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4148 11:31:10.648566 # ok 2421 Set Streaming SVE VL 1472
4149 11:31:10.648681 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4150 11:31:10.648766 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4151 11:31:10.648847 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4152 11:31:10.648921 # ok 2425 Set Streaming SVE VL 1488
4153 11:31:10.649012 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4154 11:31:10.649100 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4155 11:31:10.649201 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4156 11:31:10.651452 # ok 2429 Set Streaming SVE VL 1504
4157 11:31:10.651588 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4158 11:31:10.651708 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4159 11:31:10.651829 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4160 11:31:10.651962 # ok 2433 Set Streaming SVE VL 1520
4161 11:31:10.652080 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4162 11:31:10.652558 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4163 11:31:10.652855 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4164 11:31:10.652946 # ok 2437 Set Streaming SVE VL 1536
4165 11:31:10.653063 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4166 11:31:10.653188 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4167 11:31:10.653298 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4168 11:31:10.653402 # ok 2441 Set Streaming SVE VL 1552
4169 11:31:10.653536 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4170 11:31:10.653667 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4171 11:31:10.653982 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4172 11:31:10.654081 # ok 2445 Set Streaming SVE VL 1568
4173 11:31:10.654184 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4174 11:31:10.654274 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4175 11:31:10.654376 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4176 11:31:10.654465 # ok 2449 Set Streaming SVE VL 1584
4177 11:31:10.654567 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4178 11:31:10.654667 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4179 11:31:10.654965 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4180 11:31:10.655075 # ok 2453 Set Streaming SVE VL 1600
4181 11:31:10.655178 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4182 11:31:10.655265 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4183 11:31:10.655363 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4184 11:31:10.655466 # ok 2457 Set Streaming SVE VL 1616
4185 11:31:10.655566 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4186 11:31:10.655665 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4187 11:31:10.655981 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4188 11:31:10.656069 # ok 2461 Set Streaming SVE VL 1632
4189 11:31:10.656141 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4190 11:31:10.656233 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4191 11:31:10.656330 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4192 11:31:10.656431 # ok 2465 Set Streaming SVE VL 1648
4193 11:31:10.656660 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4194 11:31:10.656767 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4195 11:31:10.656853 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4196 11:31:10.656948 # ok 2469 Set Streaming SVE VL 1664
4197 11:31:10.657064 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4198 11:31:10.657368 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4199 11:31:10.657472 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4200 11:31:10.657543 # ok 2473 Set Streaming SVE VL 1680
4201 11:31:10.657662 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4202 11:31:10.657772 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4203 11:31:10.657872 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4204 11:31:10.657964 # ok 2477 Set Streaming SVE VL 1696
4205 11:31:10.658276 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4206 11:31:10.658382 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4207 11:31:10.658485 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4208 11:31:10.658591 # ok 2481 Set Streaming SVE VL 1712
4209 11:31:10.658692 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4210 11:31:10.658791 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4211 11:31:10.658891 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4212 11:31:10.658990 # ok 2485 Set Streaming SVE VL 1728
4213 11:31:10.659287 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4214 11:31:10.659392 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4215 11:31:10.659497 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4216 11:31:10.659621 # ok 2489 Set Streaming SVE VL 1744
4217 11:31:10.659725 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4218 11:31:10.660028 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4219 11:31:10.660132 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4220 11:31:10.660221 # ok 2493 Set Streaming SVE VL 1760
4221 11:31:10.660321 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4222 11:31:10.660423 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4223 11:31:10.660523 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4224 11:31:10.660625 # ok 2497 Set Streaming SVE VL 1776
4225 11:31:10.660933 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4226 11:31:10.661038 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4227 11:31:10.661140 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4228 11:31:10.661240 # ok 2501 Set Streaming SVE VL 1792
4229 11:31:10.661341 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4230 11:31:10.661642 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4231 11:31:10.661752 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4232 11:31:10.661855 # ok 2505 Set Streaming SVE VL 1808
4233 11:31:10.661944 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4234 11:31:10.662059 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4235 11:31:10.662356 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4236 11:31:10.662446 # ok 2509 Set Streaming SVE VL 1824
4237 11:31:10.662538 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4238 11:31:10.662651 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4239 11:31:10.662751 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4240 11:31:10.662857 # ok 2513 Set Streaming SVE VL 1840
4241 11:31:10.662941 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4242 11:31:10.663240 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4243 11:31:10.663338 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4244 11:31:10.663433 # ok 2517 Set Streaming SVE VL 1856
4245 11:31:10.663550 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4246 11:31:10.663669 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4247 11:31:10.663946 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4248 11:31:10.664040 # ok 2521 Set Streaming SVE VL 1872
4249 11:31:10.664112 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4250 11:31:10.664238 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4251 11:31:10.664359 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4252 11:31:10.664464 # ok 2525 Set Streaming SVE VL 1888
4253 11:31:10.664585 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4254 11:31:10.664684 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4255 11:31:10.664789 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4256 11:31:10.664885 # ok 2529 Set Streaming SVE VL 1904
4257 11:31:10.664958 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4258 11:31:10.665061 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4259 11:31:10.665179 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4260 11:31:10.665309 # ok 2533 Set Streaming SVE VL 1920
4261 11:31:10.665430 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4262 11:31:10.665536 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4263 11:31:10.665637 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4264 11:31:10.665765 # ok 2537 Set Streaming SVE VL 1936
4265 11:31:10.666066 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4266 11:31:10.666180 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4267 11:31:10.666291 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4268 11:31:10.666410 # ok 2541 Set Streaming SVE VL 1952
4269 11:31:10.666487 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4270 11:31:10.666746 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4271 11:31:10.666834 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4272 11:31:10.666928 # ok 2545 Set Streaming SVE VL 1968
4273 11:31:10.667005 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4274 11:31:10.667277 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4275 11:31:10.667387 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4276 11:31:10.667471 # ok 2549 Set Streaming SVE VL 1984
4277 11:31:10.667564 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4278 11:31:10.667659 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4279 11:31:10.667754 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4280 11:31:10.667984 # ok 2553 Set Streaming SVE VL 2000
4281 11:31:10.668081 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4282 11:31:10.668182 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4283 11:31:10.668496 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4284 11:31:10.668596 # ok 2557 Set Streaming SVE VL 2016
4285 11:31:10.668716 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4286 11:31:10.668830 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4287 11:31:10.669156 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4288 11:31:10.669258 # ok 2561 Set Streaming SVE VL 2032
4289 11:31:10.669356 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4290 11:31:10.669632 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4291 11:31:10.669753 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4292 11:31:10.670042 # ok 2565 Set Streaming SVE VL 2048
4293 11:31:10.670148 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4294 11:31:10.670446 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4295 11:31:10.670556 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4296 11:31:10.670835 # ok 2569 Set Streaming SVE VL 2064
4297 11:31:10.670915 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4298 11:31:10.670988 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4299 11:31:10.671259 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4300 11:31:10.671339 # ok 2573 Set Streaming SVE VL 2080
4301 11:31:10.671450 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4302 11:31:10.671549 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4303 11:31:10.671648 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4304 11:31:10.671922 # ok 2577 Set Streaming SVE VL 2096
4305 11:31:10.672002 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4306 11:31:10.674022 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4307 11:31:10.674140 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4308 11:31:10.674265 # ok 2581 Set Streaming SVE VL 2112
4309 11:31:10.674371 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4310 11:31:10.674500 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4311 11:31:10.674609 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4312 11:31:10.674711 # ok 2585 Set Streaming SVE VL 2128
4313 11:31:10.674798 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4314 11:31:10.675089 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4315 11:31:10.675177 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4316 11:31:10.675273 # ok 2589 Set Streaming SVE VL 2144
4317 11:31:10.675374 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4318 11:31:10.675648 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4319 11:31:10.675746 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4320 11:31:10.675823 # ok 2593 Set Streaming SVE VL 2160
4321 11:31:10.675925 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4322 11:31:10.676023 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4323 11:31:10.676407 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4324 11:31:10.676716 # ok 2597 Set Streaming SVE VL 2176
4325 11:31:10.676813 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4326 11:31:10.676935 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4327 11:31:10.677037 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4328 11:31:10.677115 # ok 2601 Set Streaming SVE VL 2192
4329 11:31:10.677201 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4330 11:31:10.677479 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4331 11:31:10.677588 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4332 11:31:10.677693 # ok 2605 Set Streaming SVE VL 2208
4333 11:31:10.677784 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4334 11:31:10.678076 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4335 11:31:10.678195 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4336 11:31:10.678279 # ok 2609 Set Streaming SVE VL 2224
4337 11:31:10.678389 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4338 11:31:10.678679 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4339 11:31:10.678766 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4340 11:31:10.678874 # ok 2613 Set Streaming SVE VL 2240
4341 11:31:10.678967 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4342 11:31:10.679254 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4343 11:31:10.679336 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4344 11:31:10.679460 # ok 2617 Set Streaming SVE VL 2256
4345 11:31:10.679569 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4346 11:31:10.679674 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4347 11:31:10.679785 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4348 11:31:10.680097 # ok 2621 Set Streaming SVE VL 2272
4349 11:31:10.680188 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4350 11:31:10.680519 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4351 11:31:10.680623 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4352 11:31:10.680737 # ok 2625 Set Streaming SVE VL 2288
4353 11:31:10.680854 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4354 11:31:10.680937 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4355 11:31:10.681047 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4356 11:31:10.681143 # ok 2629 Set Streaming SVE VL 2304
4357 11:31:10.681249 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4358 11:31:10.681344 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4359 11:31:10.681444 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4360 11:31:10.681693 # ok 2633 Set Streaming SVE VL 2320
4361 11:31:10.681800 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4362 11:31:10.682080 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4363 11:31:10.682170 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4364 11:31:10.682278 # ok 2637 Set Streaming SVE VL 2336
4365 11:31:10.682398 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4366 11:31:10.682528 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4367 11:31:10.682650 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4368 11:31:10.682744 # ok 2641 Set Streaming SVE VL 2352
4369 11:31:10.682836 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4370 11:31:10.683132 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4371 11:31:10.683237 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4372 11:31:10.683324 # ok 2645 Set Streaming SVE VL 2368
4373 11:31:10.683414 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4374 11:31:10.683702 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4375 11:31:10.683791 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4376 11:31:10.683893 # ok 2649 Set Streaming SVE VL 2384
4377 11:31:10.683975 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4378 11:31:10.684264 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4379 11:31:10.684539 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4380 11:31:10.684617 # ok 2653 Set Streaming SVE VL 2400
4381 11:31:10.684711 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4382 11:31:10.685002 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4383 11:31:10.685110 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4384 11:31:10.685213 # ok 2657 Set Streaming SVE VL 2416
4385 11:31:10.685314 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4386 11:31:10.685603 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4387 11:31:10.685721 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4388 11:31:10.685823 # ok 2661 Set Streaming SVE VL 2432
4389 11:31:10.685972 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4390 11:31:10.686091 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4391 11:31:10.686392 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4392 11:31:10.686503 # ok 2665 Set Streaming SVE VL 2448
4393 11:31:10.686602 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4394 11:31:10.686702 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4395 11:31:10.686802 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4396 11:31:10.686903 # ok 2669 Set Streaming SVE VL 2464
4397 11:31:10.687002 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4398 11:31:10.687300 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4399 11:31:10.687406 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4400 11:31:10.687505 # ok 2673 Set Streaming SVE VL 2480
4401 11:31:10.687589 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4402 11:31:10.687686 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4403 11:31:10.687919 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4404 11:31:10.688026 # ok 2677 Set Streaming SVE VL 2496
4405 11:31:10.688127 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4406 11:31:10.688421 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4407 11:31:10.688519 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4408 11:31:10.688635 # ok 2681 Set Streaming SVE VL 2512
4409 11:31:10.688737 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4410 11:31:10.688828 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4411 11:31:10.689111 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4412 11:31:10.689214 # ok 2685 Set Streaming SVE VL 2528
4413 11:31:10.689314 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4414 11:31:10.689412 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4415 11:31:10.689699 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4416 11:31:10.689799 # ok 2689 Set Streaming SVE VL 2544
4417 11:31:10.689898 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4418 11:31:10.689992 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4419 11:31:10.690278 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4420 11:31:10.690367 # ok 2693 Set Streaming SVE VL 2560
4421 11:31:10.690461 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4422 11:31:10.690542 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4423 11:31:10.690633 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4424 11:31:10.690737 # ok 2697 Set Streaming SVE VL 2576
4425 11:31:10.690854 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4426 11:31:10.691156 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4427 11:31:10.691240 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4428 11:31:10.691529 # ok 2701 Set Streaming SVE VL 2592
4429 11:31:10.691631 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4430 11:31:10.691720 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4431 11:31:10.691843 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4432 11:31:10.691938 # ok 2705 Set Streaming SVE VL 2608
4433 11:31:10.692044 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4434 11:31:10.692140 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4435 11:31:10.692233 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4436 11:31:10.692341 # ok 2709 Set Streaming SVE VL 2624
4437 11:31:10.692667 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4438 11:31:10.692797 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4439 11:31:10.692892 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4440 11:31:10.692998 # ok 2713 Set Streaming SVE VL 2640
4441 11:31:10.693090 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4442 11:31:10.693192 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4443 11:31:10.693296 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4444 11:31:10.693382 # ok 2717 Set Streaming SVE VL 2656
4445 11:31:10.693481 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4446 11:31:10.693581 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4447 11:31:10.693688 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4448 11:31:10.693790 # ok 2721 Set Streaming SVE VL 2672
4449 11:31:10.694088 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4450 11:31:10.694191 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4451 11:31:10.694292 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4452 11:31:10.694377 # ok 2725 Set Streaming SVE VL 2688
4453 11:31:10.694676 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4454 11:31:10.694781 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4455 11:31:10.696019 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4456 11:31:10.696122 # ok 2729 Set Streaming SVE VL 2704
4457 11:31:10.696420 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4458 11:31:10.696534 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4459 11:31:10.696647 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4460 11:31:10.696778 # ok 2733 Set Streaming SVE VL 2720
4461 11:31:10.697067 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4462 11:31:10.697166 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4463 11:31:10.697262 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4464 11:31:10.697357 # ok 2737 Set Streaming SVE VL 2736
4465 11:31:10.697444 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4466 11:31:10.697691 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4467 11:31:10.697796 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4468 11:31:10.697888 # ok 2741 Set Streaming SVE VL 2752
4469 11:31:10.698181 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4470 11:31:10.698297 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4471 11:31:10.698398 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4472 11:31:10.698699 # ok 2745 Set Streaming SVE VL 2768
4473 11:31:10.698808 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4474 11:31:10.698893 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4475 11:31:10.698993 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4476 11:31:10.699078 # ok 2749 Set Streaming SVE VL 2784
4477 11:31:10.699178 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4478 11:31:10.699265 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4479 11:31:10.699363 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4480 11:31:10.699461 # ok 2753 Set Streaming SVE VL 2800
4481 11:31:10.699563 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4482 11:31:10.699672 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4483 11:31:10.699974 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4484 11:31:10.700071 # ok 2757 Set Streaming SVE VL 2816
4485 11:31:10.700161 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4486 11:31:10.700262 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4487 11:31:10.700365 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4488 11:31:10.700453 # ok 2761 Set Streaming SVE VL 2832
4489 11:31:10.700538 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4490 11:31:10.700808 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4491 11:31:10.700910 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4492 11:31:10.701021 # ok 2765 Set Streaming SVE VL 2848
4493 11:31:10.701133 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4494 11:31:10.701249 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4495 11:31:10.701367 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4496 11:31:10.701485 # ok 2769 Set Streaming SVE VL 2864
4497 11:31:10.701609 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4498 11:31:10.701741 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4499 11:31:10.702039 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4500 11:31:10.702147 # ok 2773 Set Streaming SVE VL 2880
4501 11:31:10.702253 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4502 11:31:10.702356 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4503 11:31:10.702458 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4504 11:31:10.702673 # ok 2777 Set Streaming SVE VL 2896
4505 11:31:10.702780 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4506 11:31:10.702884 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4507 11:31:10.702987 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4508 11:31:10.703093 # ok 2781 Set Streaming SVE VL 2912
4509 11:31:10.703194 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4510 11:31:10.703310 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4511 11:31:10.703427 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4512 11:31:10.703740 # ok 2785 Set Streaming SVE VL 2928
4513 11:31:10.703838 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4514 11:31:10.703950 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4515 11:31:10.704045 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4516 11:31:10.704303 # ok 2789 Set Streaming SVE VL 2944
4517 11:31:10.704376 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4518 11:31:10.704664 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4519 11:31:10.704753 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4520 11:31:10.704838 # ok 2793 Set Streaming SVE VL 2960
4521 11:31:10.704936 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4522 11:31:10.705033 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4523 11:31:10.705352 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4524 11:31:10.705451 # ok 2797 Set Streaming SVE VL 2976
4525 11:31:10.705553 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4526 11:31:10.705662 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4527 11:31:10.705925 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4528 11:31:10.706018 # ok 2801 Set Streaming SVE VL 2992
4529 11:31:10.706102 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4530 11:31:10.706181 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4531 11:31:10.706488 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4532 11:31:10.706610 # ok 2805 Set Streaming SVE VL 3008
4533 11:31:10.706701 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4534 11:31:10.706801 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4535 11:31:10.706900 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4536 11:31:10.706999 # ok 2809 Set Streaming SVE VL 3024
4537 11:31:10.707097 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4538 11:31:10.707394 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4539 11:31:10.707501 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4540 11:31:10.707604 # ok 2813 Set Streaming SVE VL 3040
4541 11:31:10.707690 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4542 11:31:10.707787 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4543 11:31:10.707887 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4544 11:31:10.707989 # ok 2817 Set Streaming SVE VL 3056
4545 11:31:10.708285 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4546 11:31:10.708387 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4547 11:31:10.708466 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4548 11:31:10.708743 # ok 2821 Set Streaming SVE VL 3072
4549 11:31:10.708840 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4550 11:31:10.708931 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4551 11:31:10.709214 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4552 11:31:10.709308 # ok 2825 Set Streaming SVE VL 3088
4553 11:31:10.709403 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4554 11:31:10.709497 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4555 11:31:10.709581 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4556 11:31:10.709677 # ok 2829 Set Streaming SVE VL 3104
4557 11:31:10.709973 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4558 11:31:10.710083 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4559 11:31:10.710161 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4560 11:31:10.710252 # ok 2833 Set Streaming SVE VL 3120
4561 11:31:10.710346 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4562 11:31:10.710665 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4563 11:31:10.710766 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4564 11:31:10.710850 # ok 2837 Set Streaming SVE VL 3136
4565 11:31:10.711121 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4566 11:31:10.711218 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4567 11:31:10.711310 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4568 11:31:10.711381 # ok 2841 Set Streaming SVE VL 3152
4569 11:31:10.711463 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4570 11:31:10.711545 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4571 11:31:10.711803 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4572 11:31:10.711876 # ok 2845 Set Streaming SVE VL 3168
4573 11:31:10.711953 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4574 11:31:10.712213 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4575 11:31:10.712479 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4576 11:31:10.712570 # ok 2849 Set Streaming SVE VL 3184
4577 11:31:10.712664 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4578 11:31:10.712926 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4579 11:31:10.713029 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4580 11:31:10.713114 # ok 2853 Set Streaming SVE VL 3200
4581 11:31:10.713217 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4582 11:31:10.713365 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4583 11:31:10.713669 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4584 11:31:10.713778 # ok 2857 Set Streaming SVE VL 3216
4585 11:31:10.713879 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4586 11:31:10.713966 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4587 11:31:10.714063 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4588 11:31:10.714160 # ok 2861 Set Streaming SVE VL 3232
4589 11:31:10.714255 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4590 11:31:10.714352 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4591 11:31:10.714603 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4592 11:31:10.714720 # ok 2865 Set Streaming SVE VL 3248
4593 11:31:10.715018 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4594 11:31:10.715132 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4595 11:31:10.715229 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4596 11:31:10.715324 # ok 2869 Set Streaming SVE VL 3264
4597 11:31:10.715418 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4598 11:31:10.715512 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4599 11:31:10.715821 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4600 11:31:10.715923 # ok 2873 Set Streaming SVE VL 3280
4601 11:31:10.716017 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4602 11:31:10.716112 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4603 11:31:10.716403 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4604 11:31:10.716505 # ok 2877 Set Streaming SVE VL 3296
4605 11:31:10.735106 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4606 11:31:10.735344 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4607 11:31:10.735464 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4608 11:31:10.735558 # ok 2881 Set Streaming SVE VL 3312
4609 11:31:10.735633 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4610 11:31:10.735706 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4611 11:31:10.735783 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4612 11:31:10.735860 # ok 2885 Set Streaming SVE VL 3328
4613 11:31:10.736110 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4614 11:31:10.743052 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4615 11:31:10.743414 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4616 11:31:10.743533 # ok 2889 Set Streaming SVE VL 3344
4617 11:31:10.743639 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4618 11:31:10.743718 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4619 11:31:10.743802 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4620 11:31:10.743890 # ok 2893 Set Streaming SVE VL 3360
4621 11:31:10.744141 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4622 11:31:10.745249 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4623 11:31:10.745519 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4624 11:31:10.745607 # ok 2897 Set Streaming SVE VL 3376
4625 11:31:10.745698 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4626 11:31:10.745977 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4627 11:31:10.746073 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4628 11:31:10.746162 # ok 2901 Set Streaming SVE VL 3392
4629 11:31:10.746257 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4630 11:31:10.746534 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4631 11:31:10.746639 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4632 11:31:10.746734 # ok 2905 Set Streaming SVE VL 3408
4633 11:31:10.747027 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4634 11:31:10.747111 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4635 11:31:10.747188 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4636 11:31:10.747271 # ok 2909 Set Streaming SVE VL 3424
4637 11:31:10.747540 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4638 11:31:10.747640 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4639 11:31:10.747921 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4640 11:31:10.748012 # ok 2913 Set Streaming SVE VL 3440
4641 11:31:10.748093 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4642 11:31:10.753772 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4643 11:31:10.753890 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4644 11:31:10.753968 # ok 2917 Set Streaming SVE VL 3456
4645 11:31:10.754057 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4646 11:31:10.754330 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4647 11:31:10.754439 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4648 11:31:10.754544 # ok 2921 Set Streaming SVE VL 3472
4649 11:31:10.754711 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4650 11:31:10.754893 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4651 11:31:10.755293 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4652 11:31:10.755446 # ok 2925 Set Streaming SVE VL 3488
4653 11:31:10.755612 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4654 11:31:10.755757 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4655 11:31:10.755904 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4656 11:31:10.756026 # ok 2929 Set Streaming SVE VL 3504
4657 11:31:10.756167 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4658 11:31:10.756321 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4659 11:31:10.765559 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4660 11:31:10.765697 # ok 2933 Set Streaming SVE VL 3520
4661 11:31:10.765975 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4662 11:31:10.766056 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4663 11:31:10.766133 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4664 11:31:10.766198 # ok 2937 Set Streaming SVE VL 3536
4665 11:31:10.766452 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4666 11:31:10.766532 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4667 11:31:10.766785 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4668 11:31:10.766862 # ok 2941 Set Streaming SVE VL 3552
4669 11:31:10.767129 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4670 11:31:10.767208 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4671 11:31:10.767297 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4672 11:31:10.767391 # ok 2945 Set Streaming SVE VL 3568
4673 11:31:10.767696 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4674 11:31:10.767896 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4675 11:31:10.768108 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4676 11:31:10.768258 # ok 2949 Set Streaming SVE VL 3584
4677 11:31:10.768376 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4678 11:31:10.773447 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4679 11:31:10.773836 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4680 11:31:10.773927 # ok 2953 Set Streaming SVE VL 3600
4681 11:31:10.773989 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4682 11:31:10.774062 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4683 11:31:10.774364 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4684 11:31:10.774546 # ok 2957 Set Streaming SVE VL 3616
4685 11:31:10.774708 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4686 11:31:10.774846 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4687 11:31:10.774985 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4688 11:31:10.775105 # ok 2961 Set Streaming SVE VL 3632
4689 11:31:10.775240 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4690 11:31:10.775360 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4691 11:31:10.775496 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4692 11:31:10.775643 # ok 2965 Set Streaming SVE VL 3648
4693 11:31:10.775771 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4694 11:31:10.775920 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4695 11:31:10.776067 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4696 11:31:10.776215 # ok 2969 Set Streaming SVE VL 3664
4697 11:31:10.781723 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4698 11:31:10.782134 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4699 11:31:10.782308 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4700 11:31:10.782472 # ok 2973 Set Streaming SVE VL 3680
4701 11:31:10.782664 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4702 11:31:10.782826 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4703 11:31:10.782979 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4704 11:31:10.783131 # ok 2977 Set Streaming SVE VL 3696
4705 11:31:10.783268 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4706 11:31:10.783423 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4707 11:31:10.783621 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4708 11:31:10.783773 # ok 2981 Set Streaming SVE VL 3712
4709 11:31:10.783917 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4710 11:31:10.784101 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4711 11:31:10.784318 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4712 11:31:10.784450 # ok 2985 Set Streaming SVE VL 3728
4713 11:31:10.784565 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4714 11:31:10.784683 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4715 11:31:10.788084 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4716 11:31:10.788469 # ok 2989 Set Streaming SVE VL 3744
4717 11:31:10.793405 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4718 11:31:10.793558 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4719 11:31:10.793699 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4720 11:31:10.793845 # ok 2993 Set Streaming SVE VL 3760
4721 11:31:10.793941 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4722 11:31:10.794058 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4723 11:31:10.794187 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4724 11:31:10.794310 # ok 2997 Set Streaming SVE VL 3776
4725 11:31:10.794424 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4726 11:31:10.794537 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4727 11:31:10.794653 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4728 11:31:10.794785 # ok 3001 Set Streaming SVE VL 3792
4729 11:31:10.794921 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4730 11:31:10.795052 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4731 11:31:10.795171 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4732 11:31:10.795321 # ok 3005 Set Streaming SVE VL 3808
4733 11:31:10.795476 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4734 11:31:10.795640 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4735 11:31:10.795784 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4736 11:31:10.795914 # ok 3009 Set Streaming SVE VL 3824
4737 11:31:10.796060 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4738 11:31:10.796164 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4739 11:31:10.801373 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4740 11:31:10.801734 # ok 3013 Set Streaming SVE VL 3840
4741 11:31:10.801917 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4742 11:31:10.802082 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4743 11:31:10.802296 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4744 11:31:10.802490 # ok 3017 Set Streaming SVE VL 3856
4745 11:31:10.802659 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4746 11:31:10.802817 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4747 11:31:10.802997 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4748 11:31:10.803169 # ok 3021 Set Streaming SVE VL 3872
4749 11:31:10.803313 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4750 11:31:10.803432 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4751 11:31:10.803547 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4752 11:31:10.803689 # ok 3025 Set Streaming SVE VL 3888
4753 11:31:10.803826 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4754 11:31:10.804227 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4755 11:31:10.809217 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4756 11:31:10.809405 # ok 3029 Set Streaming SVE VL 3904
4757 11:31:10.809716 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4758 11:31:10.809846 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4759 11:31:10.809963 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4760 11:31:10.810103 # ok 3033 Set Streaming SVE VL 3920
4761 11:31:10.810231 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4762 11:31:10.810382 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4763 11:31:10.810570 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4764 11:31:10.810740 # ok 3037 Set Streaming SVE VL 3936
4765 11:31:10.810900 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4766 11:31:10.811084 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4767 11:31:10.811237 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4768 11:31:10.811397 # ok 3041 Set Streaming SVE VL 3952
4769 11:31:10.811553 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4770 11:31:10.811755 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4771 11:31:10.811919 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4772 11:31:10.812077 # ok 3045 Set Streaming SVE VL 3968
4773 11:31:10.812231 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4774 11:31:10.812348 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4775 11:31:10.812460 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4776 11:31:10.812596 # ok 3049 Set Streaming SVE VL 3984
4777 11:31:10.812715 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4778 11:31:10.812829 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4779 11:31:10.817690 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4780 11:31:10.818130 # ok 3053 Set Streaming SVE VL 4000
4781 11:31:10.818321 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4782 11:31:10.818480 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4783 11:31:10.818657 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4784 11:31:10.818835 # ok 3057 Set Streaming SVE VL 4016
4785 11:31:10.819009 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4786 11:31:10.819220 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4787 11:31:10.819430 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4788 11:31:10.819666 # ok 3061 Set Streaming SVE VL 4032
4789 11:31:10.819868 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4790 11:31:10.820064 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4791 11:31:10.820263 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4792 11:31:10.820450 # ok 3065 Set Streaming SVE VL 4048
4793 11:31:10.820585 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4794 11:31:10.820743 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4795 11:31:10.820904 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4796 11:31:10.821111 # ok 3069 Set Streaming SVE VL 4064
4797 11:31:10.821280 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4798 11:31:10.821437 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4799 11:31:10.821633 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4800 11:31:10.821823 # ok 3073 Set Streaming SVE VL 4080
4801 11:31:10.821991 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4802 11:31:10.822188 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4803 11:31:10.822360 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4804 11:31:10.822560 # ok 3077 Set Streaming SVE VL 4096
4805 11:31:10.822823 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4806 11:31:10.823017 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4807 11:31:10.823167 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4808 11:31:10.823326 # ok 3081 Set Streaming SVE VL 4112
4809 11:31:10.823486 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4810 11:31:10.823640 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4811 11:31:10.823802 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4812 11:31:10.823966 # ok 3085 Set Streaming SVE VL 4128
4813 11:31:10.824124 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4814 11:31:10.824244 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4815 11:31:10.824609 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4816 11:31:10.824768 # ok 3089 Set Streaming SVE VL 4144
4817 11:31:10.824890 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4818 11:31:10.825010 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4819 11:31:10.825128 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4820 11:31:10.825245 # ok 3093 Set Streaming SVE VL 4160
4821 11:31:10.825361 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4822 11:31:10.825478 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4823 11:31:10.825596 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4824 11:31:10.825731 # ok 3097 Set Streaming SVE VL 4176
4825 11:31:10.825850 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4826 11:31:10.825966 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4827 11:31:10.826083 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4828 11:31:10.826199 # ok 3101 Set Streaming SVE VL 4192
4829 11:31:10.826313 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4830 11:31:10.826429 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4831 11:31:10.826545 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4832 11:31:10.826660 # ok 3105 Set Streaming SVE VL 4208
4833 11:31:10.826779 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4834 11:31:10.826896 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4835 11:31:10.827012 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4836 11:31:10.827128 # ok 3109 Set Streaming SVE VL 4224
4837 11:31:10.827244 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4838 11:31:10.831766 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4839 11:31:10.832123 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4840 11:31:10.832281 # ok 3113 Set Streaming SVE VL 4240
4841 11:31:10.832406 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4842 11:31:10.832526 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4843 11:31:10.833036 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4844 11:31:10.833468 # ok 3117 Set Streaming SVE VL 4256
4845 11:31:10.833670 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4846 11:31:10.833843 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4847 11:31:10.834009 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4848 11:31:10.834206 # ok 3121 Set Streaming SVE VL 4272
4849 11:31:10.834372 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4850 11:31:10.834539 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4851 11:31:10.834700 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4852 11:31:10.834852 # ok 3125 Set Streaming SVE VL 4288
4853 11:31:10.835014 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4854 11:31:10.835208 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4855 11:31:10.835376 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4856 11:31:10.835534 # ok 3129 Set Streaming SVE VL 4304
4857 11:31:10.835670 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4858 11:31:10.835818 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4859 11:31:10.835972 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4860 11:31:10.836121 # ok 3133 Set Streaming SVE VL 4320
4861 11:31:10.836242 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4862 11:31:10.836358 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4863 11:31:10.836504 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4864 11:31:10.836626 # ok 3137 Set Streaming SVE VL 4336
4865 11:31:10.836741 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4866 11:31:10.836858 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4867 11:31:10.836972 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4868 11:31:10.837087 # ok 3141 Set Streaming SVE VL 4352
4869 11:31:10.837202 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4870 11:31:10.837316 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4871 11:31:10.841035 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4872 11:31:10.841455 # ok 3145 Set Streaming SVE VL 4368
4873 11:31:10.841640 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4874 11:31:10.841820 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4875 11:31:10.841983 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4876 11:31:10.842167 # ok 3149 Set Streaming SVE VL 4384
4877 11:31:10.842340 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4878 11:31:10.842505 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4879 11:31:10.842664 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4880 11:31:10.842823 # ok 3153 Set Streaming SVE VL 4400
4881 11:31:10.843015 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4882 11:31:10.843179 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4883 11:31:10.843338 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4884 11:31:10.843504 # ok 3157 Set Streaming SVE VL 4416
4885 11:31:10.843670 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4886 11:31:10.843829 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4887 11:31:10.844017 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4888 11:31:10.844201 # ok 3161 Set Streaming SVE VL 4432
4889 11:31:10.844326 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4890 11:31:10.844442 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4891 11:31:10.844557 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4892 11:31:10.844671 # ok 3165 Set Streaming SVE VL 4448
4893 11:31:10.844787 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4894 11:31:10.844903 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4895 11:31:10.845017 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4896 11:31:10.845132 # ok 3169 Set Streaming SVE VL 4464
4897 11:31:10.845246 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4898 11:31:10.857297 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4899 11:31:10.857580 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4900 11:31:10.857767 # ok 3173 Set Streaming SVE VL 4480
4901 11:31:10.857914 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4902 11:31:10.858056 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4903 11:31:10.858231 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4904 11:31:10.858428 # ok 3177 Set Streaming SVE VL 4496
4905 11:31:10.858677 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4906 11:31:10.859213 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4907 11:31:10.859409 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4908 11:31:10.859606 # ok 3181 Set Streaming SVE VL 4512
4909 11:31:10.859847 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4910 11:31:10.860039 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4911 11:31:10.860222 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4912 11:31:10.860350 # ok 3185 Set Streaming SVE VL 4528
4913 11:31:10.860467 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4914 11:31:10.860583 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4915 11:31:10.860698 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4916 11:31:10.860815 # ok 3189 Set Streaming SVE VL 4544
4917 11:31:10.860930 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4918 11:31:10.861044 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4919 11:31:10.873187 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4920 11:31:10.873642 # ok 3193 Set Streaming SVE VL 4560
4921 11:31:10.873764 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4922 11:31:10.873854 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4923 11:31:10.873940 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4924 11:31:10.874045 # ok 3197 Set Streaming SVE VL 4576
4925 11:31:10.874132 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4926 11:31:10.874216 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4927 11:31:10.874316 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4928 11:31:10.874402 # ok 3201 Set Streaming SVE VL 4592
4929 11:31:10.874485 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4930 11:31:10.874582 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4931 11:31:10.874666 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4932 11:31:10.874765 # ok 3205 Set Streaming SVE VL 4608
4933 11:31:10.874863 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4934 11:31:10.874961 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4935 11:31:10.875297 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4936 11:31:10.875525 # ok 3209 Set Streaming SVE VL 4624
4937 11:31:10.875687 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4938 11:31:10.875899 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4939 11:31:10.876088 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4940 11:31:10.876229 # ok 3213 Set Streaming SVE VL 4640
4941 11:31:10.876347 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4942 11:31:10.876489 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4943 11:31:10.876610 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4944 11:31:10.876727 # ok 3217 Set Streaming SVE VL 4656
4945 11:31:10.893383 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4946 11:31:10.893832 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4947 11:31:10.893946 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4948 11:31:10.894037 # ok 3221 Set Streaming SVE VL 4672
4949 11:31:10.894144 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4950 11:31:10.894233 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4951 11:31:10.894333 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4952 11:31:10.894420 # ok 3225 Set Streaming SVE VL 4688
4953 11:31:10.894524 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4954 11:31:10.894626 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4955 11:31:10.894932 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4956 11:31:10.895052 # ok 3229 Set Streaming SVE VL 4704
4957 11:31:10.895154 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4958 11:31:10.895319 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4959 11:31:10.895671 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4960 11:31:10.895861 # ok 3233 Set Streaming SVE VL 4720
4961 11:31:10.896073 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4962 11:31:10.896266 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4963 11:31:10.896421 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4964 11:31:10.896608 # ok 3237 Set Streaming SVE VL 4736
4965 11:31:10.903635 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4966 11:31:10.904199 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4967 11:31:10.904361 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4968 11:31:10.904505 # ok 3241 Set Streaming SVE VL 4752
4969 11:31:10.904628 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4970 11:31:10.904745 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4971 11:31:10.907621 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4972 11:31:10.908065 # ok 3245 Set Streaming SVE VL 4768
4973 11:31:10.908254 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4974 11:31:10.908389 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4975 11:31:10.908565 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4976 11:31:10.909329 # ok 3249 Set Streaming SVE VL 4784
4977 11:31:10.909735 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4978 11:31:10.909948 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4979 11:31:10.910173 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4980 11:31:10.910366 # ok 3253 Set Streaming SVE VL 4800
4981 11:31:10.910584 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4982 11:31:10.910803 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4983 11:31:10.910981 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4984 11:31:10.911197 # ok 3257 Set Streaming SVE VL 4816
4985 11:31:10.911400 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4986 11:31:10.911582 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4987 11:31:10.911798 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4988 11:31:10.912024 # ok 3261 Set Streaming SVE VL 4832
4989 11:31:10.912208 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4990 11:31:10.912345 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4991 11:31:10.912471 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4992 11:31:10.912588 # ok 3265 Set Streaming SVE VL 4848
4993 11:31:10.912703 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4994 11:31:10.912847 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4995 11:31:10.912970 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4996 11:31:10.913086 # ok 3269 Set Streaming SVE VL 4864
4997 11:31:10.915963 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
4998 11:31:10.916297 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
4999 11:31:10.921792 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5000 11:31:10.922225 # ok 3273 Set Streaming SVE VL 4880
5001 11:31:10.922333 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5002 11:31:10.922423 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5003 11:31:10.922529 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5004 11:31:10.922619 # ok 3277 Set Streaming SVE VL 4896
5005 11:31:10.922708 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5006 11:31:10.922812 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5007 11:31:10.922917 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5008 11:31:10.923020 # ok 3281 Set Streaming SVE VL 4912
5009 11:31:10.923349 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5010 11:31:10.923542 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5011 11:31:10.923759 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5012 11:31:10.923910 # ok 3285 Set Streaming SVE VL 4928
5013 11:31:10.924091 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5014 11:31:10.924233 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5015 11:31:10.924381 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5016 11:31:10.924504 # ok 3289 Set Streaming SVE VL 4944
5017 11:31:10.929318 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5018 11:31:10.929821 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5019 11:31:10.929986 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5020 11:31:10.930137 # ok 3293 Set Streaming SVE VL 4960
5021 11:31:10.930282 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5022 11:31:10.930480 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5023 11:31:10.930678 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5024 11:31:10.930834 # ok 3297 Set Streaming SVE VL 4976
5025 11:31:10.930993 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5026 11:31:10.931229 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5027 11:31:10.931423 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5028 11:31:10.931588 # ok 3301 Set Streaming SVE VL 4992
5029 11:31:10.931746 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5030 11:31:10.931902 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5031 11:31:10.932078 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5032 11:31:10.932255 # ok 3305 Set Streaming SVE VL 5008
5033 11:31:10.932419 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5034 11:31:10.932541 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5035 11:31:10.932659 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5036 11:31:10.932775 # ok 3309 Set Streaming SVE VL 5024
5037 11:31:10.932890 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5038 11:31:10.933007 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5039 11:31:10.937468 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5040 11:31:10.937930 # ok 3313 Set Streaming SVE VL 5040
5041 11:31:10.938039 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5042 11:31:10.938140 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5043 11:31:10.938254 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5044 11:31:10.938360 # ok 3317 Set Streaming SVE VL 5056
5045 11:31:10.938658 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5046 11:31:10.938761 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5047 11:31:10.938863 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5048 11:31:10.938973 # ok 3321 Set Streaming SVE VL 5072
5049 11:31:10.939294 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5050 11:31:10.939409 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5051 11:31:10.939515 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5052 11:31:10.939615 # ok 3325 Set Streaming SVE VL 5088
5053 11:31:10.939905 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5054 11:31:10.946055 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5055 11:31:10.946265 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5056 11:31:10.946358 # ok 3329 Set Streaming SVE VL 5104
5057 11:31:10.946459 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5058 11:31:10.946561 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5059 11:31:10.946662 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5060 11:31:10.946760 # ok 3333 Set Streaming SVE VL 5120
5061 11:31:10.947096 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5062 11:31:10.947302 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5063 11:31:10.947528 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5064 11:31:10.947720 # ok 3337 Set Streaming SVE VL 5136
5065 11:31:10.947895 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5066 11:31:10.948085 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5067 11:31:10.948250 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5068 11:31:10.948393 # ok 3341 Set Streaming SVE VL 5152
5069 11:31:10.948546 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5070 11:31:10.948706 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5071 11:31:10.950753 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5072 11:31:10.951163 # ok 3345 Set Streaming SVE VL 5168
5073 11:31:10.951336 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5074 11:31:10.951550 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5075 11:31:10.951805 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5076 11:31:10.952030 # ok 3349 Set Streaming SVE VL 5184
5077 11:31:10.952215 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5078 11:31:10.952350 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5079 11:31:10.952510 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5080 11:31:10.952639 # ok 3353 Set Streaming SVE VL 5200
5081 11:31:10.952782 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5082 11:31:10.952906 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5083 11:31:10.953024 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5084 11:31:10.955666 # ok 3357 Set Streaming SVE VL 5216
5085 11:31:10.956084 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5086 11:31:10.956255 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5087 11:31:10.956380 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5088 11:31:10.956512 # ok 3361 Set Streaming SVE VL 5232
5089 11:31:10.960164 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5090 11:31:10.961196 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5091 11:31:10.961629 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5092 11:31:10.961823 # ok 3365 Set Streaming SVE VL 5248
5093 11:31:10.962029 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5094 11:31:10.962249 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5095 11:31:10.962441 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5096 11:31:10.962650 # ok 3369 Set Streaming SVE VL 5264
5097 11:31:10.962844 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5098 11:31:10.963059 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5099 11:31:10.963237 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5100 11:31:10.963435 # ok 3373 Set Streaming SVE VL 5280
5101 11:31:10.963601 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5102 11:31:10.963757 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5103 11:31:10.963912 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5104 11:31:10.964114 # ok 3377 Set Streaming SVE VL 5296
5105 11:31:10.964280 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5106 11:31:10.964410 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5107 11:31:10.964527 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5108 11:31:10.964642 # ok 3381 Set Streaming SVE VL 5312
5109 11:31:10.964757 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5110 11:31:10.964872 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5111 11:31:10.964987 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5112 11:31:10.965128 # ok 3385 Set Streaming SVE VL 5328
5113 11:31:10.968044 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5114 11:31:10.968243 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5115 11:31:10.968390 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5116 11:31:10.969266 # ok 3389 Set Streaming SVE VL 5344
5117 11:31:10.969568 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5118 11:31:10.969671 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5119 11:31:10.969774 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5120 11:31:10.969876 # ok 3393 Set Streaming SVE VL 5360
5121 11:31:10.969962 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5122 11:31:10.970256 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5123 11:31:10.970348 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5124 11:31:10.970450 # ok 3397 Set Streaming SVE VL 5376
5125 11:31:10.970548 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5126 11:31:10.970648 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5127 11:31:10.971046 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5128 11:31:10.971282 # ok 3401 Set Streaming SVE VL 5392
5129 11:31:10.971466 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5130 11:31:10.971646 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5131 11:31:10.971840 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5132 11:31:10.972067 # ok 3405 Set Streaming SVE VL 5408
5133 11:31:10.972258 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5134 11:31:10.972428 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5135 11:31:10.972625 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5136 11:31:10.972838 # ok 3409 Set Streaming SVE VL 5424
5137 11:31:10.979610 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5138 11:31:10.980030 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5139 11:31:10.980244 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5140 11:31:10.980383 # ok 3413 Set Streaming SVE VL 5440
5141 11:31:10.980505 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5142 11:31:10.980743 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5143 11:31:10.980944 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5144 11:31:10.981146 # ok 3417 Set Streaming SVE VL 5456
5145 11:31:10.981388 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5146 11:31:10.981581 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5147 11:31:10.981811 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5148 11:31:10.982028 # ok 3421 Set Streaming SVE VL 5472
5149 11:31:10.982234 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5150 11:31:10.982460 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5151 11:31:10.982615 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5152 11:31:10.982754 # ok 3425 Set Streaming SVE VL 5488
5153 11:31:10.982902 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5154 11:31:10.983040 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5155 11:31:10.983241 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5156 11:31:10.983408 # ok 3429 Set Streaming SVE VL 5504
5157 11:31:10.983598 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5158 11:31:10.983832 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5159 11:31:10.984013 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5160 11:31:10.984212 # ok 3433 Set Streaming SVE VL 5520
5161 11:31:10.984348 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5162 11:31:10.984466 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5163 11:31:10.984582 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5164 11:31:10.984697 # ok 3437 Set Streaming SVE VL 5536
5165 11:31:10.984812 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5166 11:31:10.984926 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5167 11:31:10.985040 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5168 11:31:10.985183 # ok 3441 Set Streaming SVE VL 5552
5169 11:31:10.985305 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5170 11:31:10.991176 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5171 11:31:10.991574 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5172 11:31:10.991699 # ok 3445 Set Streaming SVE VL 5568
5173 11:31:10.991803 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5174 11:31:10.991904 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5175 11:31:10.991995 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5176 11:31:10.992128 # ok 3449 Set Streaming SVE VL 5584
5177 11:31:10.992288 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5178 11:31:10.992413 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5179 11:31:10.992773 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5180 11:31:10.992959 # ok 3453 Set Streaming SVE VL 5600
5181 11:31:10.993149 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5182 11:31:10.993311 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5183 11:31:10.993472 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5184 11:31:10.993673 # ok 3457 Set Streaming SVE VL 5616
5185 11:31:10.993837 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5186 11:31:10.993993 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5187 11:31:10.994154 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5188 11:31:10.994304 # ok 3461 Set Streaming SVE VL 5632
5189 11:31:10.994485 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5190 11:31:10.994654 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5191 11:31:10.994819 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5192 11:31:10.995034 # ok 3465 Set Streaming SVE VL 5648
5193 11:31:10.995240 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5194 11:31:10.995452 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5195 11:31:10.995616 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5196 11:31:10.995740 # ok 3469 Set Streaming SVE VL 5664
5197 11:31:10.995854 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5198 11:31:10.995969 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5199 11:31:10.996084 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5200 11:31:10.996203 # ok 3473 Set Streaming SVE VL 5680
5201 11:31:10.996316 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5202 11:31:10.996454 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5203 11:31:11.005886 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5204 11:31:11.006198 # ok 3477 Set Streaming SVE VL 5696
5205 11:31:11.006379 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5206 11:31:11.006583 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5207 11:31:11.006759 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5208 11:31:11.006914 # ok 3481 Set Streaming SVE VL 5712
5209 11:31:11.007069 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5210 11:31:11.007230 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5211 11:31:11.007386 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5212 11:31:11.007578 # ok 3485 Set Streaming SVE VL 5728
5213 11:31:11.007735 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5214 11:31:11.007896 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5215 11:31:11.008054 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5216 11:31:11.008193 # ok 3489 Set Streaming SVE VL 5744
5217 11:31:11.008312 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5218 11:31:11.008427 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5219 11:31:11.008570 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5220 11:31:11.008687 # ok 3493 Set Streaming SVE VL 5760
5221 11:31:11.008800 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5222 11:31:11.008912 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5223 11:31:11.009025 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5224 11:31:11.021081 # ok 3497 Set Streaming SVE VL 5776
5225 11:31:11.021629 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5226 11:31:11.021805 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5227 11:31:11.021962 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5228 11:31:11.022129 # ok 3501 Set Streaming SVE VL 5792
5229 11:31:11.022291 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5230 11:31:11.022488 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5231 11:31:11.022654 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5232 11:31:11.022812 # ok 3505 Set Streaming SVE VL 5808
5233 11:31:11.022960 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5234 11:31:11.023117 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5235 11:31:11.023280 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5236 11:31:11.023440 # ok 3509 Set Streaming SVE VL 5824
5237 11:31:11.023632 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5238 11:31:11.023797 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5239 11:31:11.023959 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5240 11:31:11.024121 # ok 3513 Set Streaming SVE VL 5840
5241 11:31:11.024244 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5242 11:31:11.024358 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5243 11:31:11.024473 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5244 11:31:11.024587 # ok 3517 Set Streaming SVE VL 5856
5245 11:31:11.024700 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5246 11:31:11.024841 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5247 11:31:11.024961 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5248 11:31:11.025075 # ok 3521 Set Streaming SVE VL 5872
5249 11:31:11.025187 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5250 11:31:11.025300 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5251 11:31:11.033602 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5252 11:31:11.033916 # ok 3525 Set Streaming SVE VL 5888
5253 11:31:11.034087 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5254 11:31:11.034284 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5255 11:31:11.034452 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5256 11:31:11.034615 # ok 3529 Set Streaming SVE VL 5904
5257 11:31:11.034778 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5258 11:31:11.034937 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5259 11:31:11.035126 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5260 11:31:11.035277 # ok 3533 Set Streaming SVE VL 5920
5261 11:31:11.035432 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5262 11:31:11.035580 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5263 11:31:11.035736 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5264 11:31:11.035887 # ok 3537 Set Streaming SVE VL 5936
5265 11:31:11.036070 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5266 11:31:11.036223 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5267 11:31:11.036342 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5268 11:31:11.036456 # ok 3541 Set Streaming SVE VL 5952
5269 11:31:11.036570 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5270 11:31:11.036685 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5271 11:31:11.036799 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5272 11:31:11.036913 # ok 3545 Set Streaming SVE VL 5968
5273 11:31:11.037053 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5274 11:31:11.045171 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5275 11:31:11.045743 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5276 11:31:11.045949 # ok 3549 Set Streaming SVE VL 5984
5277 11:31:11.046115 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5278 11:31:11.046285 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5279 11:31:11.046452 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5280 11:31:11.046654 # ok 3553 Set Streaming SVE VL 6000
5281 11:31:11.046823 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5282 11:31:11.046987 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5283 11:31:11.047152 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5284 11:31:11.047298 # ok 3557 Set Streaming SVE VL 6016
5285 11:31:11.047455 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5286 11:31:11.047603 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5287 11:31:11.047780 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5288 11:31:11.047948 # ok 3561 Set Streaming SVE VL 6032
5289 11:31:11.048096 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5290 11:31:11.048229 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5291 11:31:11.048349 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5292 11:31:11.048467 # ok 3565 Set Streaming SVE VL 6048
5293 11:31:11.048583 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5294 11:31:11.048699 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5295 11:31:11.048815 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5296 11:31:11.048958 # ok 3569 Set Streaming SVE VL 6064
5297 11:31:11.049079 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5298 11:31:11.049196 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5299 11:31:11.053423 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5300 11:31:11.053937 # ok 3573 Set Streaming SVE VL 6080
5301 11:31:11.054123 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5302 11:31:11.054327 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5303 11:31:11.054589 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5304 11:31:11.054762 # ok 3577 Set Streaming SVE VL 6096
5305 11:31:11.054908 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5306 11:31:11.055085 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5307 11:31:11.055284 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5308 11:31:11.055458 # ok 3581 Set Streaming SVE VL 6112
5309 11:31:11.055636 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5310 11:31:11.055892 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5311 11:31:11.056101 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5312 11:31:11.056273 # ok 3585 Set Streaming SVE VL 6128
5313 11:31:11.056394 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5314 11:31:11.056509 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5315 11:31:11.056624 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5316 11:31:11.056738 # ok 3589 Set Streaming SVE VL 6144
5317 11:31:11.056850 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5318 11:31:11.056964 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5319 11:31:11.057105 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5320 11:31:11.057228 # ok 3593 Set Streaming SVE VL 6160
5321 11:31:11.057343 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5322 11:31:11.061367 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5323 11:31:11.061857 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5324 11:31:11.062080 # ok 3597 Set Streaming SVE VL 6176
5325 11:31:11.062262 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5326 11:31:11.062429 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5327 11:31:11.062628 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5328 11:31:11.062806 # ok 3601 Set Streaming SVE VL 6192
5329 11:31:11.062979 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5330 11:31:11.063169 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5331 11:31:11.063365 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5332 11:31:11.063566 # ok 3605 Set Streaming SVE VL 6208
5333 11:31:11.063703 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5334 11:31:11.063856 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5335 11:31:11.064035 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5336 11:31:11.064214 # ok 3609 Set Streaming SVE VL 6224
5337 11:31:11.064344 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5338 11:31:11.064460 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5339 11:31:11.064603 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5340 11:31:11.064725 # ok 3613 Set Streaming SVE VL 6240
5341 11:31:11.064840 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5342 11:31:11.064956 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5343 11:31:11.069478 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5344 11:31:11.069687 # ok 3617 Set Streaming SVE VL 6256
5345 11:31:11.069996 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5346 11:31:11.070100 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5347 11:31:11.070190 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5348 11:31:11.070296 # ok 3621 Set Streaming SVE VL 6272
5349 11:31:11.070398 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5350 11:31:11.070498 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5351 11:31:11.070598 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5352 11:31:11.070892 # ok 3625 Set Streaming SVE VL 6288
5353 11:31:11.072018 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5354 11:31:11.072121 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5355 11:31:11.072220 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5356 11:31:11.077632 # ok 3629 Set Streaming SVE VL 6304
5357 11:31:11.078586 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5358 11:31:11.078768 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5359 11:31:11.078964 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5360 11:31:11.079130 # ok 3633 Set Streaming SVE VL 6320
5361 11:31:11.079279 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5362 11:31:11.079511 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5363 11:31:11.079698 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5364 11:31:11.079870 # ok 3637 Set Streaming SVE VL 6336
5365 11:31:11.080016 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5366 11:31:11.080218 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5367 11:31:11.080376 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5368 11:31:11.080495 # ok 3641 Set Streaming SVE VL 6352
5369 11:31:11.080651 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5370 11:31:11.080782 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5371 11:31:11.085121 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5372 11:31:11.085971 # ok 3645 Set Streaming SVE VL 6368
5373 11:31:11.086168 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5374 11:31:11.086373 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5375 11:31:11.086523 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5376 11:31:11.086662 # ok 3649 Set Streaming SVE VL 6384
5377 11:31:11.086787 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5378 11:31:11.086968 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5379 11:31:11.087125 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5380 11:31:11.087280 # ok 3653 Set Streaming SVE VL 6400
5381 11:31:11.087428 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5382 11:31:11.087612 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5383 11:31:11.087767 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5384 11:31:11.087888 # ok 3657 Set Streaming SVE VL 6416
5385 11:31:11.088002 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5386 11:31:11.088135 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5387 11:31:11.088332 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5388 11:31:11.088514 # ok 3661 Set Streaming SVE VL 6432
5389 11:31:11.088712 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5390 11:31:11.094086 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5391 11:31:11.094493 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5392 11:31:11.094699 # ok 3665 Set Streaming SVE VL 6448
5393 11:31:11.094875 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5394 11:31:11.095066 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5395 11:31:11.095227 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5396 11:31:11.095385 # ok 3669 Set Streaming SVE VL 6464
5397 11:31:11.095525 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5398 11:31:11.095666 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5399 11:31:11.095842 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5400 11:31:11.095974 # ok 3673 Set Streaming SVE VL 6480
5401 11:31:11.096100 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5402 11:31:11.096247 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5403 11:31:11.096370 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5404 11:31:11.096487 # ok 3677 Set Streaming SVE VL 6496
5405 11:31:11.096627 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5406 11:31:11.096749 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5407 11:31:11.096865 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5408 11:31:11.096981 # ok 3681 Set Streaming SVE VL 6512
5409 11:31:11.101680 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5410 11:31:11.102533 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5411 11:31:11.102698 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5412 11:31:11.102851 # ok 3685 Set Streaming SVE VL 6528
5413 11:31:11.103024 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5414 11:31:11.103229 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5415 11:31:11.103450 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5416 11:31:11.103620 # ok 3689 Set Streaming SVE VL 6544
5417 11:31:11.103776 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5418 11:31:11.103913 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5419 11:31:11.104042 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5420 11:31:11.104253 # ok 3693 Set Streaming SVE VL 6560
5421 11:31:11.104397 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5422 11:31:11.104518 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5423 11:31:11.104683 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5424 11:31:11.104815 # ok 3697 Set Streaming SVE VL 6576
5425 11:31:11.104933 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5426 11:31:11.105051 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5427 11:31:11.110956 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5428 11:31:11.111340 # ok 3701 Set Streaming SVE VL 6592
5429 11:31:11.111483 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5430 11:31:11.111614 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5431 11:31:11.111763 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5432 11:31:11.111896 # ok 3705 Set Streaming SVE VL 6608
5433 11:31:11.112025 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5434 11:31:11.112198 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5435 11:31:11.112413 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5436 11:31:11.112554 # ok 3709 Set Streaming SVE VL 6624
5437 11:31:11.112720 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5438 11:31:11.112894 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5439 11:31:11.117006 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5440 11:31:11.117378 # ok 3713 Set Streaming SVE VL 6640
5441 11:31:11.117693 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5442 11:31:11.117814 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5443 11:31:11.117920 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5444 11:31:11.118023 # ok 3717 Set Streaming SVE VL 6656
5445 11:31:11.118374 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5446 11:31:11.118550 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5447 11:31:11.118762 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5448 11:31:11.118957 # ok 3721 Set Streaming SVE VL 6672
5449 11:31:11.119158 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5450 11:31:11.119355 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5451 11:31:11.119527 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5452 11:31:11.119696 # ok 3725 Set Streaming SVE VL 6688
5453 11:31:11.119851 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5454 11:31:11.120009 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5455 11:31:11.120202 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5456 11:31:11.120347 # ok 3729 Set Streaming SVE VL 6704
5457 11:31:11.120464 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5458 11:31:11.120578 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5459 11:31:11.120694 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5460 11:31:11.120807 # ok 3733 Set Streaming SVE VL 6720
5461 11:31:11.120920 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5462 11:31:11.130264 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5463 11:31:11.130681 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5464 11:31:11.130810 # ok 3737 Set Streaming SVE VL 6736
5465 11:31:11.130993 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5466 11:31:11.131183 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5467 11:31:11.131323 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5468 11:31:11.131493 # ok 3741 Set Streaming SVE VL 6752
5469 11:31:11.131645 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5470 11:31:11.131824 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5471 11:31:11.131990 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5472 11:31:11.132154 # ok 3745 Set Streaming SVE VL 6768
5473 11:31:11.132305 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5474 11:31:11.132428 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5475 11:31:11.132544 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5476 11:31:11.133488 # ok 3749 Set Streaming SVE VL 6784
5477 11:31:11.133594 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5478 11:31:11.133707 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5479 11:31:11.133814 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5480 11:31:11.133921 # ok 3753 Set Streaming SVE VL 6800
5481 11:31:11.134221 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5482 11:31:11.134345 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5483 11:31:11.134448 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5484 11:31:11.134548 # ok 3757 Set Streaming SVE VL 6816
5485 11:31:11.134844 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5486 11:31:11.134948 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5487 11:31:11.135054 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5488 11:31:11.135156 # ok 3761 Set Streaming SVE VL 6832
5489 11:31:11.135455 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5490 11:31:11.135574 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5491 11:31:11.135676 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5492 11:31:11.135777 # ok 3765 Set Streaming SVE VL 6848
5493 11:31:11.136080 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5494 11:31:11.136195 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5495 11:31:11.144652 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5496 11:31:11.144985 # ok 3769 Set Streaming SVE VL 6864
5497 11:31:11.145081 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5498 11:31:11.145185 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5499 11:31:11.145271 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5500 11:31:11.145368 # ok 3773 Set Streaming SVE VL 6880
5501 11:31:11.145467 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5502 11:31:11.167477 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5503 11:31:11.167695 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5504 11:31:11.168000 # ok 3777 Set Streaming SVE VL 6896
5505 11:31:11.168104 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5506 11:31:11.168192 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5507 11:31:11.168295 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5508 11:31:11.168386 # ok 3781 Set Streaming SVE VL 6912
5509 11:31:11.178195 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5510 11:31:11.178568 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5511 11:31:11.178766 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5512 11:31:11.178935 # ok 3785 Set Streaming SVE VL 6928
5513 11:31:11.179121 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5514 11:31:11.179283 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5515 11:31:11.179450 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5516 11:31:11.179607 # ok 3789 Set Streaming SVE VL 6944
5517 11:31:11.179788 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5518 11:31:11.179954 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5519 11:31:11.180111 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5520 11:31:11.180289 # ok 3793 Set Streaming SVE VL 6960
5521 11:31:11.180422 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5522 11:31:11.180567 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5523 11:31:11.180689 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5524 11:31:11.180806 # ok 3797 Set Streaming SVE VL 6976
5525 11:31:11.185203 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5526 11:31:11.185667 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5527 11:31:11.185868 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5528 11:31:11.186030 # ok 3801 Set Streaming SVE VL 6992
5529 11:31:11.186196 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5530 11:31:11.186330 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5531 11:31:11.186474 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5532 11:31:11.186620 # ok 3805 Set Streaming SVE VL 7008
5533 11:31:11.186868 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5534 11:31:11.187039 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5535 11:31:11.187216 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5536 11:31:11.187399 # ok 3809 Set Streaming SVE VL 7024
5537 11:31:11.187578 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5538 11:31:11.187723 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5539 11:31:11.187895 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5540 11:31:11.188045 # ok 3813 Set Streaming SVE VL 7040
5541 11:31:11.188194 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5542 11:31:11.188334 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5543 11:31:11.188453 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5544 11:31:11.188569 # ok 3817 Set Streaming SVE VL 7056
5545 11:31:11.188682 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5546 11:31:11.188824 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5547 11:31:11.188945 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5548 11:31:11.189061 # ok 3821 Set Streaming SVE VL 7072
5549 11:31:11.192785 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5550 11:31:11.193270 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5551 11:31:11.193461 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5552 11:31:11.193606 # ok 3825 Set Streaming SVE VL 7088
5553 11:31:11.193802 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5554 11:31:11.194021 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5555 11:31:11.194215 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5556 11:31:11.194429 # ok 3829 Set Streaming SVE VL 7104
5557 11:31:11.194607 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5558 11:31:11.194771 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5559 11:31:11.194935 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5560 11:31:11.195136 # ok 3833 Set Streaming SVE VL 7120
5561 11:31:11.195297 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5562 11:31:11.195442 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5563 11:31:11.195586 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5564 11:31:11.195743 # ok 3837 Set Streaming SVE VL 7136
5565 11:31:11.195893 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5566 11:31:11.196053 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5567 11:31:11.196199 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5568 11:31:11.196349 # ok 3841 Set Streaming SVE VL 7152
5569 11:31:11.196468 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5570 11:31:11.196584 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5571 11:31:11.196698 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5572 11:31:11.196814 # ok 3845 Set Streaming SVE VL 7168
5573 11:31:11.196927 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5574 11:31:11.197042 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5575 11:31:11.197157 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5576 11:31:11.197273 # ok 3849 Set Streaming SVE VL 7184
5577 11:31:11.200553 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5578 11:31:11.200991 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5579 11:31:11.201180 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5580 11:31:11.201333 # ok 3853 Set Streaming SVE VL 7200
5581 11:31:11.201509 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5582 11:31:11.201726 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5583 11:31:11.201922 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5584 11:31:11.202119 # ok 3857 Set Streaming SVE VL 7216
5585 11:31:11.202288 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5586 11:31:11.202462 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5587 11:31:11.202636 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5588 11:31:11.202849 # ok 3861 Set Streaming SVE VL 7232
5589 11:31:11.203016 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5590 11:31:11.203172 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5591 11:31:11.203328 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5592 11:31:11.203483 # ok 3865 Set Streaming SVE VL 7248
5593 11:31:11.203638 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5594 11:31:11.203792 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5595 11:31:11.203947 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5596 11:31:11.204101 # ok 3869 Set Streaming SVE VL 7264
5597 11:31:11.204291 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5598 11:31:11.204453 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5599 11:31:11.204612 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5600 11:31:11.204768 # ok 3873 Set Streaming SVE VL 7280
5601 11:31:11.204922 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5602 11:31:11.205077 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5603 11:31:11.205232 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5604 11:31:11.205387 # ok 3877 Set Streaming SVE VL 7296
5605 11:31:11.205542 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5606 11:31:11.205705 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5607 11:31:11.205863 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5608 11:31:11.206018 # ok 3881 Set Streaming SVE VL 7312
5609 11:31:11.208441 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5610 11:31:11.208868 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5611 11:31:11.209037 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5612 11:31:11.209195 # ok 3885 Set Streaming SVE VL 7328
5613 11:31:11.209350 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5614 11:31:11.209533 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5615 11:31:11.209707 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5616 11:31:11.209867 # ok 3889 Set Streaming SVE VL 7344
5617 11:31:11.210026 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5618 11:31:11.210212 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5619 11:31:11.210374 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5620 11:31:11.210531 # ok 3893 Set Streaming SVE VL 7360
5621 11:31:11.210685 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5622 11:31:11.210840 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5623 11:31:11.210995 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5624 11:31:11.211180 # ok 3897 Set Streaming SVE VL 7376
5625 11:31:11.211340 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5626 11:31:11.211495 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5627 11:31:11.211655 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5628 11:31:11.211811 # ok 3901 Set Streaming SVE VL 7392
5629 11:31:11.211966 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5630 11:31:11.212121 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5631 11:31:11.212277 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5632 11:31:11.212465 # ok 3905 Set Streaming SVE VL 7408
5633 11:31:11.212625 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5634 11:31:11.212781 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5635 11:31:11.212937 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5636 11:31:11.213093 # ok 3909 Set Streaming SVE VL 7424
5637 11:31:11.213248 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5638 11:31:11.213403 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5639 11:31:11.216631 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5640 11:31:11.217016 # ok 3913 Set Streaming SVE VL 7440
5641 11:31:11.217172 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5642 11:31:11.217320 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5643 11:31:11.217490 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5644 11:31:11.217636 # ok 3917 Set Streaming SVE VL 7456
5645 11:31:11.217790 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5646 11:31:11.217957 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5647 11:31:11.218102 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5648 11:31:11.218244 # ok 3921 Set Streaming SVE VL 7472
5649 11:31:11.218385 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5650 11:31:11.218566 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5651 11:31:11.218749 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5652 11:31:11.218952 # ok 3925 Set Streaming SVE VL 7488
5653 11:31:11.219096 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5654 11:31:11.219253 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5655 11:31:11.219408 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5656 11:31:11.219612 # ok 3929 Set Streaming SVE VL 7504
5657 11:31:11.219788 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5658 11:31:11.219992 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5659 11:31:11.220172 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5660 11:31:11.220351 # ok 3933 Set Streaming SVE VL 7520
5661 11:31:11.220523 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5662 11:31:11.220687 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5663 11:31:11.222308 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5664 11:31:11.222770 # ok 3937 Set Streaming SVE VL 7536
5665 11:31:11.222906 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5666 11:31:11.223019 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5667 11:31:11.223143 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5668 11:31:11.223288 # ok 3941 Set Streaming SVE VL 7552
5669 11:31:11.223452 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5670 11:31:11.223613 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5671 11:31:11.223777 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5672 11:31:11.223970 # ok 3945 Set Streaming SVE VL 7568
5673 11:31:11.224134 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5674 11:31:11.224271 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5675 11:31:11.224437 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5676 11:31:11.224561 # ok 3949 Set Streaming SVE VL 7584
5677 11:31:11.224706 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5678 11:31:11.224836 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5679 11:31:11.224996 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5680 11:31:11.225167 # ok 3953 Set Streaming SVE VL 7600
5681 11:31:11.225338 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5682 11:31:11.225500 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5683 11:31:11.225698 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5684 11:31:11.225854 # ok 3957 Set Streaming SVE VL 7616
5685 11:31:11.225979 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5686 11:31:11.226155 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5687 11:31:11.226282 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5688 11:31:11.226380 # ok 3961 Set Streaming SVE VL 7632
5689 11:31:11.226493 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5690 11:31:11.226636 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5691 11:31:11.226729 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5692 11:31:11.226834 # ok 3965 Set Streaming SVE VL 7648
5693 11:31:11.226939 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5694 11:31:11.227016 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5695 11:31:11.227099 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5696 11:31:11.227203 # ok 3969 Set Streaming SVE VL 7664
5697 11:31:11.227301 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5698 11:31:11.227404 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5699 11:31:11.227732 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5700 11:31:11.227814 # ok 3973 Set Streaming SVE VL 7680
5701 11:31:11.227876 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5702 11:31:11.228139 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5703 11:31:11.228228 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5704 11:31:11.228307 # ok 3977 Set Streaming SVE VL 7696
5705 11:31:11.236673 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5706 11:31:11.237106 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5707 11:31:11.237214 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5708 11:31:11.237301 # ok 3981 Set Streaming SVE VL 7712
5709 11:31:11.237379 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5710 11:31:11.237466 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5711 11:31:11.237566 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5712 11:31:11.237651 # ok 3985 Set Streaming SVE VL 7728
5713 11:31:11.237718 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5714 11:31:11.237816 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5715 11:31:11.237911 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5716 11:31:11.237993 # ok 3989 Set Streaming SVE VL 7744
5717 11:31:11.238070 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5718 11:31:11.238156 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5719 11:31:11.238227 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5720 11:31:11.238319 # ok 3993 Set Streaming SVE VL 7760
5721 11:31:11.238407 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5722 11:31:11.238489 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5723 11:31:11.238573 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5724 11:31:11.238636 # ok 3997 Set Streaming SVE VL 7776
5725 11:31:11.238703 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5726 11:31:11.238775 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5727 11:31:11.238876 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5728 11:31:11.238987 # ok 4001 Set Streaming SVE VL 7792
5729 11:31:11.239088 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5730 11:31:11.239187 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5731 11:31:11.239266 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5732 11:31:11.239357 # ok 4005 Set Streaming SVE VL 7808
5733 11:31:11.239450 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5734 11:31:11.239533 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5735 11:31:11.239650 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5736 11:31:11.239752 # ok 4009 Set Streaming SVE VL 7824
5737 11:31:11.239837 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5738 11:31:11.239913 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5739 11:31:11.240185 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5740 11:31:11.240261 # ok 4013 Set Streaming SVE VL 7840
5741 11:31:11.240335 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5742 11:31:11.244819 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5743 11:31:11.245180 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5744 11:31:11.245349 # ok 4017 Set Streaming SVE VL 7856
5745 11:31:11.245497 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5746 11:31:11.245633 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5747 11:31:11.245802 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5748 11:31:11.245939 # ok 4021 Set Streaming SVE VL 7872
5749 11:31:11.246076 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5750 11:31:11.246209 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5751 11:31:11.246342 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5752 11:31:11.246497 # ok 4025 Set Streaming SVE VL 7888
5753 11:31:11.246619 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5754 11:31:11.246746 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5755 11:31:11.246879 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5756 11:31:11.247011 # ok 4029 Set Streaming SVE VL 7904
5757 11:31:11.247143 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5758 11:31:11.247300 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5759 11:31:11.247437 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5760 11:31:11.247574 # ok 4033 Set Streaming SVE VL 7920
5761 11:31:11.247705 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5762 11:31:11.247837 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5763 11:31:11.247970 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5764 11:31:11.248136 # ok 4037 Set Streaming SVE VL 7936
5765 11:31:11.248273 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5766 11:31:11.248408 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5767 11:31:11.248534 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5768 11:31:11.248654 # ok 4041 Set Streaming SVE VL 7952
5769 11:31:11.248796 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5770 11:31:11.248919 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5771 11:31:11.249037 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5772 11:31:11.249142 # ok 4045 Set Streaming SVE VL 7968
5773 11:31:11.249272 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5774 11:31:11.249429 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5775 11:31:11.249566 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5776 11:31:11.249705 # ok 4049 Set Streaming SVE VL 7984
5777 11:31:11.249834 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5778 11:31:11.249965 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5779 11:31:11.250340 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5780 11:31:11.250496 # ok 4053 Set Streaming SVE VL 8000
5781 11:31:11.250633 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5782 11:31:11.250767 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5783 11:31:11.250899 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5784 11:31:11.251014 # ok 4057 Set Streaming SVE VL 8016
5785 11:31:11.256621 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5786 11:31:11.256962 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5787 11:31:11.257063 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5788 11:31:11.257164 # ok 4061 Set Streaming SVE VL 8032
5789 11:31:11.257251 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5790 11:31:11.257347 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5791 11:31:11.257447 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5792 11:31:11.257735 # ok 4065 Set Streaming SVE VL 8048
5793 11:31:11.257826 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5794 11:31:11.257924 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5795 11:31:11.258208 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5796 11:31:11.258296 # ok 4069 Set Streaming SVE VL 8064
5797 11:31:11.258394 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5798 11:31:11.258490 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5799 11:31:11.258592 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5800 11:31:11.258882 # ok 4073 Set Streaming SVE VL 8080
5801 11:31:11.258970 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5802 11:31:11.259679 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5803 11:31:11.259788 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5804 11:31:11.259874 # ok 4077 Set Streaming SVE VL 8096
5805 11:31:11.259972 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5806 11:31:11.260069 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5807 11:31:11.260352 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5808 11:31:11.264759 # ok 4081 Set Streaming SVE VL 8112
5809 11:31:11.265103 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5810 11:31:11.265204 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5811 11:31:11.265307 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5812 11:31:11.265392 # ok 4085 Set Streaming SVE VL 8128
5813 11:31:11.265490 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5814 11:31:11.265589 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5815 11:31:11.265701 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5816 11:31:11.265998 # ok 4089 Set Streaming SVE VL 8144
5817 11:31:11.266111 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5818 11:31:11.266210 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5819 11:31:11.266318 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5820 11:31:11.266613 # ok 4093 Set Streaming SVE VL 8160
5821 11:31:11.266725 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5822 11:31:11.266824 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5823 11:31:11.267110 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5824 11:31:11.267200 # ok 4097 Set Streaming SVE VL 8176
5825 11:31:11.267298 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5826 11:31:11.267395 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5827 11:31:11.267691 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5828 11:31:11.267789 # ok 4101 Set Streaming SVE VL 8192
5829 11:31:11.267889 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5830 11:31:11.267987 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5831 11:31:11.268084 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5832 11:31:11.272856 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5833 11:31:11.273023 ok 30 selftests: arm64: sve-ptrace
5834 11:31:11.273113 # selftests: arm64: sve-probe-vls
5835 11:31:11.273392 # TAP version 13
5836 11:31:11.273494 # 1..2
5837 11:31:11.273582 # ok 1 Enumerated 16 vector lengths
5838 11:31:11.273676 # ok 2 All vector lengths valid
5839 11:31:11.273760 # # 16
5840 11:31:11.273843 # # 32
5841 11:31:11.273926 # # 48
5842 11:31:11.274009 # # 64
5843 11:31:11.274089 # # 80
5844 11:31:11.274166 # # 96
5845 11:31:11.274245 # # 112
5846 11:31:11.274338 # # 128
5847 11:31:11.274420 # # 144
5848 11:31:11.274502 # # 160
5849 11:31:11.274585 # # 176
5850 11:31:11.274675 # # 192
5851 11:31:11.274755 # # 208
5852 11:31:11.274838 # # 224
5853 11:31:11.274923 # # 240
5854 11:31:11.275005 # # 256
5855 11:31:11.275090 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5856 11:31:11.275179 ok 31 selftests: arm64: sve-probe-vls
5857 11:31:11.340849 # selftests: arm64: vec-syscfg
5858 11:31:12.064065 # TAP version 13
5859 11:31:12.064515 # 1..20
5860 11:31:12.064638 # ok 1 SVE default vector length 64
5861 11:31:12.064737 # ok 2 SVE minimum vector length 16
5862 11:31:12.064828 # ok 3 SVE maximum vector length 256
5863 11:31:12.064920 # ok 4 SVE current VL is 64
5864 11:31:12.070628 # ok 5 SVE set VL 64 and have VL 64
5865 11:31:12.071070 # ok 6 SVE prctl() set min/max
5866 11:31:12.071246 # ok 7 SVE vector length used default
5867 11:31:12.071428 # ok 8 SVE vector length was inherited
5868 11:31:12.071579 # ok 9 SVE vector length set on exec
5869 11:31:12.071701 # ok 10 SVE prctl() set all VLs, 0 errors
5870 11:31:12.071846 # ok 11 SME default vector length 32
5871 11:31:12.071969 # ok 12 SME minimum vector length 16
5872 11:31:12.072148 # ok 13 SME maximum vector length 256
5873 11:31:12.072321 # ok 14 SME current VL is 32
5874 11:31:12.072487 # ok 15 SME set VL 32 and have VL 32
5875 11:31:12.072623 # ok 16 SME prctl() set min/max
5876 11:31:12.072747 # ok 17 SME vector length used default
5877 11:31:12.072879 # ok 18 SME vector length was inherited
5878 11:31:12.073079 # ok 19 SME vector length set on exec
5879 11:31:12.073242 # ok 20 SME prctl() set all VLs, 0 errors
5880 11:31:12.073368 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5881 11:31:12.084467 ok 32 selftests: arm64: vec-syscfg
5882 11:31:12.369839 # selftests: arm64: za-fork
5883 11:31:12.531438 # TAP version 13
5884 11:31:12.531723 # 1..1
5885 11:31:12.532061 # # PID: 1015
5886 11:31:12.532191 # ok 1 fork_test
5887 11:31:12.532311 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5888 11:31:12.571759 ok 33 selftests: arm64: za-fork
5889 11:31:12.731390 # selftests: arm64: za-ptrace
5890 11:31:12.901953 # TAP version 13
5891 11:31:12.902290 # 1..1536
5892 11:31:12.902665 # # Parent is 1033, child is 1034
5893 11:31:12.902838 # ok 1 Set VL 16
5894 11:31:12.902965 # ok 2 Disabled ZA for VL 16
5895 11:31:12.903085 # ok 3 Data match for VL 16
5896 11:31:12.903203 # ok 4 Set VL 32
5897 11:31:12.903337 # ok 5 Disabled ZA for VL 32
5898 11:31:12.903476 # ok 6 Data match for VL 32
5899 11:31:12.903601 # ok 7 Set VL 48
5900 11:31:12.903728 # ok 8 # SKIP Disabled ZA for VL 48
5901 11:31:12.903852 # ok 9 # SKIP Get and set data for VL 48
5902 11:31:12.903975 # ok 10 Set VL 64
5903 11:31:12.904137 # ok 11 Disabled ZA for VL 64
5904 11:31:12.904270 # ok 12 Data match for VL 64
5905 11:31:12.904395 # ok 13 Set VL 80
5906 11:31:12.904518 # ok 14 # SKIP Disabled ZA for VL 80
5907 11:31:12.904694 # ok 15 # SKIP Get and set data for VL 80
5908 11:31:12.904833 # ok 16 Set VL 96
5909 11:31:12.904957 # ok 17 # SKIP Disabled ZA for VL 96
5910 11:31:12.905079 # ok 18 # SKIP Get and set data for VL 96
5911 11:31:12.905200 # ok 19 Set VL 112
5912 11:31:12.905321 # ok 20 # SKIP Disabled ZA for VL 112
5913 11:31:12.905442 # ok 21 # SKIP Get and set data for VL 112
5914 11:31:12.905566 # ok 22 Set VL 128
5915 11:31:12.905701 # ok 23 Disabled ZA for VL 128
5916 11:31:12.905830 # ok 24 Data match for VL 128
5917 11:31:12.905949 # ok 25 Set VL 144
5918 11:31:12.906065 # ok 26 # SKIP Disabled ZA for VL 144
5919 11:31:12.906182 # ok 27 # SKIP Get and set data for VL 144
5920 11:31:12.906300 # ok 28 Set VL 160
5921 11:31:12.906413 # ok 29 # SKIP Disabled ZA for VL 160
5922 11:31:12.906527 # ok 30 # SKIP Get and set data for VL 160
5923 11:31:12.906646 # ok 31 Set VL 176
5924 11:31:12.906792 # ok 32 # SKIP Disabled ZA for VL 176
5925 11:31:12.906914 # ok 33 # SKIP Get and set data for VL 176
5926 11:31:12.907029 # ok 34 Set VL 192
5927 11:31:12.907143 # ok 35 # SKIP Disabled ZA for VL 192
5928 11:31:12.907261 # ok 36 # SKIP Get and set data for VL 192
5929 11:31:12.907374 # ok 37 Set VL 208
5930 11:31:12.907485 # ok 38 # SKIP Disabled ZA for VL 208
5931 11:31:12.909895 # ok 39 # SKIP Get and set data for VL 208
5932 11:31:12.910079 # ok 40 Set VL 224
5933 11:31:12.910478 # ok 41 # SKIP Disabled ZA for VL 224
5934 11:31:12.910634 # ok 42 # SKIP Get and set data for VL 224
5935 11:31:12.910791 # ok 43 Set VL 240
5936 11:31:12.910923 # ok 44 # SKIP Disabled ZA for VL 240
5937 11:31:12.911044 # ok 45 # SKIP Get and set data for VL 240
5938 11:31:12.911166 # ok 46 Set VL 256
5939 11:31:12.911340 # ok 47 Disabled ZA for VL 256
5940 11:31:12.911494 # ok 48 Data match for VL 256
5941 11:31:12.911667 # ok 49 Set VL 272
5942 11:31:12.911816 # ok 50 # SKIP Disabled ZA for VL 272
5943 11:31:12.911996 # ok 51 # SKIP Get and set data for VL 272
5944 11:31:12.912171 # ok 52 Set VL 288
5945 11:31:12.912316 # ok 53 # SKIP Disabled ZA for VL 288
5946 11:31:12.912459 # ok 54 # SKIP Get and set data for VL 288
5947 11:31:12.912658 # ok 55 Set VL 304
5948 11:31:12.912833 # ok 56 # SKIP Disabled ZA for VL 304
5949 11:31:12.912979 # ok 57 # SKIP Get and set data for VL 304
5950 11:31:12.913202 # ok 58 Set VL 320
5951 11:31:12.913361 # ok 59 # SKIP Disabled ZA for VL 320
5952 11:31:12.913507 # ok 60 # SKIP Get and set data for VL 320
5953 11:31:12.913661 # ok 61 Set VL 336
5954 11:31:12.913806 # ok 62 # SKIP Disabled ZA for VL 336
5955 11:31:12.913947 # ok 63 # SKIP Get and set data for VL 336
5956 11:31:12.914088 # ok 64 Set VL 352
5957 11:31:12.914229 # ok 65 # SKIP Disabled ZA for VL 352
5958 11:31:12.914370 # ok 66 # SKIP Get and set data for VL 352
5959 11:31:12.914510 # ok 67 Set VL 368
5960 11:31:12.914649 # ok 68 # SKIP Disabled ZA for VL 368
5961 11:31:12.914789 # ok 69 # SKIP Get and set data for VL 368
5962 11:31:12.914929 # ok 70 Set VL 384
5963 11:31:12.915069 # ok 71 # SKIP Disabled ZA for VL 384
5964 11:31:12.915210 # ok 72 # SKIP Get and set data for VL 384
5965 11:31:12.915351 # ok 73 Set VL 400
5966 11:31:12.917463 # ok 74 # SKIP Disabled ZA for VL 400
5967 11:31:12.917682 # ok 75 # SKIP Get and set data for VL 400
5968 11:31:12.917847 # ok 76 Set VL 416
5969 11:31:12.918045 # ok 77 # SKIP Disabled ZA for VL 416
5970 11:31:12.918203 # ok 78 # SKIP Get and set data for VL 416
5971 11:31:12.918392 # ok 79 Set VL 432
5972 11:31:12.918533 # ok 80 # SKIP Disabled ZA for VL 432
5973 11:31:12.918660 # ok 81 # SKIP Get and set data for VL 432
5974 11:31:12.918801 # ok 82 Set VL 448
5975 11:31:12.918940 # ok 83 # SKIP Disabled ZA for VL 448
5976 11:31:12.919102 # ok 84 # SKIP Get and set data for VL 448
5977 11:31:12.919224 # ok 85 Set VL 464
5978 11:31:12.919339 # ok 86 # SKIP Disabled ZA for VL 464
5979 11:31:12.919453 # ok 87 # SKIP Get and set data for VL 464
5980 11:31:12.919594 # ok 88 Set VL 480
5981 11:31:12.919731 # ok 89 # SKIP Disabled ZA for VL 480
5982 11:31:12.919868 # ok 90 # SKIP Get and set data for VL 480
5983 11:31:12.920024 # ok 91 Set VL 496
5984 11:31:12.920150 # ok 92 # SKIP Disabled ZA for VL 496
5985 11:31:12.920268 # ok 93 # SKIP Get and set data for VL 496
5986 11:31:12.920382 # ok 94 Set VL 512
5987 11:31:12.920495 # ok 95 # SKIP Disabled ZA for VL 512
5988 11:31:12.920660 # ok 96 # SKIP Get and set data for VL 512
5989 11:31:12.920829 # ok 97 Set VL 528
5990 11:31:12.920952 # ok 98 # SKIP Disabled ZA for VL 528
5991 11:31:12.921069 # ok 99 # SKIP Get and set data for VL 528
5992 11:31:12.921184 # ok 100 Set VL 544
5993 11:31:12.921300 # ok 101 # SKIP Disabled ZA for VL 544
5994 11:31:12.921413 # ok 102 # SKIP Get and set data for VL 544
5995 11:31:12.921529 # ok 103 Set VL 560
5996 11:31:12.921645 # ok 104 # SKIP Disabled ZA for VL 560
5997 11:31:12.921776 # ok 105 # SKIP Get and set data for VL 560
5998 11:31:12.921891 # ok 106 Set VL 576
5999 11:31:12.922005 # ok 107 # SKIP Disabled ZA for VL 576
6000 11:31:12.922119 # ok 108 # SKIP Get and set data for VL 576
6001 11:31:12.922235 # ok 109 Set VL 592
6002 11:31:12.922349 # ok 110 # SKIP Disabled ZA for VL 592
6003 11:31:12.922465 # ok 111 # SKIP Get and set data for VL 592
6004 11:31:12.922580 # ok 112 Set VL 608
6005 11:31:12.922695 # ok 113 # SKIP Disabled ZA for VL 608
6006 11:31:12.922812 # ok 114 # SKIP Get and set data for VL 608
6007 11:31:12.922929 # ok 115 Set VL 624
6008 11:31:12.923043 # ok 116 # SKIP Disabled ZA for VL 624
6009 11:31:12.927907 # ok 117 # SKIP Get and set data for VL 624
6010 11:31:12.928104 # ok 118 Set VL 640
6011 11:31:12.928250 # ok 119 # SKIP Disabled ZA for VL 640
6012 11:31:12.928373 # ok 120 # SKIP Get and set data for VL 640
6013 11:31:12.928490 # ok 121 Set VL 656
6014 11:31:12.928654 # ok 122 # SKIP Disabled ZA for VL 656
6015 11:31:12.928788 # ok 123 # SKIP Get and set data for VL 656
6016 11:31:12.928905 # ok 124 Set VL 672
6017 11:31:12.940789 # ok 125 # SKIP Disabled ZA for VL 672
6018 11:31:12.941031 # ok 126 # SKIP Get and set data for VL 672
6019 11:31:12.941376 # ok 127 Set VL 688
6020 11:31:12.941541 # ok 128 # SKIP Disabled ZA for VL 688
6021 11:31:12.941748 # ok 129 # SKIP Get and set data for VL 688
6022 11:31:12.941945 # ok 130 Set VL 704
6023 11:31:12.942130 # ok 131 # SKIP Disabled ZA for VL 704
6024 11:31:12.942303 # ok 132 # SKIP Get and set data for VL 704
6025 11:31:12.942501 # ok 133 Set VL 720
6026 11:31:12.942688 # ok 134 # SKIP Disabled ZA for VL 720
6027 11:31:12.942840 # ok 135 # SKIP Get and set data for VL 720
6028 11:31:12.942994 # ok 136 Set VL 736
6029 11:31:12.943160 # ok 137 # SKIP Disabled ZA for VL 736
6030 11:31:12.943367 # ok 138 # SKIP Get and set data for VL 736
6031 11:31:12.943574 # ok 139 Set VL 752
6032 11:31:12.943732 # ok 140 # SKIP Disabled ZA for VL 752
6033 11:31:12.943872 # ok 141 # SKIP Get and set data for VL 752
6034 11:31:12.944022 # ok 142 Set VL 768
6035 11:31:12.944166 # ok 143 # SKIP Disabled ZA for VL 768
6036 11:31:12.944322 # ok 144 # SKIP Get and set data for VL 768
6037 11:31:12.944508 # ok 145 Set VL 784
6038 11:31:12.944698 # ok 146 # SKIP Disabled ZA for VL 784
6039 11:31:12.944867 # ok 147 # SKIP Get and set data for VL 784
6040 11:31:12.945012 # ok 148 Set VL 800
6041 11:31:12.945153 # ok 149 # SKIP Disabled ZA for VL 800
6042 11:31:12.945291 # ok 150 # SKIP Get and set data for VL 800
6043 11:31:12.945469 # ok 151 Set VL 816
6044 11:31:12.945603 # ok 152 # SKIP Disabled ZA for VL 816
6045 11:31:12.945755 # ok 153 # SKIP Get and set data for VL 816
6046 11:31:12.945903 # ok 154 Set VL 832
6047 11:31:12.946044 # ok 155 # SKIP Disabled ZA for VL 832
6048 11:31:12.946185 # ok 156 # SKIP Get and set data for VL 832
6049 11:31:12.946325 # ok 157 Set VL 848
6050 11:31:12.946464 # ok 158 # SKIP Disabled ZA for VL 848
6051 11:31:12.946606 # ok 159 # SKIP Get and set data for VL 848
6052 11:31:12.946748 # ok 160 Set VL 864
6053 11:31:12.946887 # ok 161 # SKIP Disabled ZA for VL 864
6054 11:31:12.947027 # ok 162 # SKIP Get and set data for VL 864
6055 11:31:12.952003 # ok 163 Set VL 880
6056 11:31:12.952446 # ok 164 # SKIP Disabled ZA for VL 880
6057 11:31:12.952602 # ok 165 # SKIP Get and set data for VL 880
6058 11:31:12.952725 # ok 166 Set VL 896
6059 11:31:12.952841 # ok 167 # SKIP Disabled ZA for VL 896
6060 11:31:12.952957 # ok 168 # SKIP Get and set data for VL 896
6061 11:31:12.953074 # ok 169 Set VL 912
6062 11:31:12.953226 # ok 170 # SKIP Disabled ZA for VL 912
6063 11:31:12.953378 # ok 171 # SKIP Get and set data for VL 912
6064 11:31:12.953535 # ok 172 Set VL 928
6065 11:31:12.953749 # ok 173 # SKIP Disabled ZA for VL 928
6066 11:31:12.953954 # ok 174 # SKIP Get and set data for VL 928
6067 11:31:12.954156 # ok 175 Set VL 944
6068 11:31:12.954330 # ok 176 # SKIP Disabled ZA for VL 944
6069 11:31:12.954487 # ok 177 # SKIP Get and set data for VL 944
6070 11:31:12.954646 # ok 178 Set VL 960
6071 11:31:12.954804 # ok 179 # SKIP Disabled ZA for VL 960
6072 11:31:12.955013 # ok 180 # SKIP Get and set data for VL 960
6073 11:31:12.955150 # ok 181 Set VL 976
6074 11:31:12.955267 # ok 182 # SKIP Disabled ZA for VL 976
6075 11:31:12.955408 # ok 183 # SKIP Get and set data for VL 976
6076 11:31:12.955582 # ok 184 Set VL 992
6077 11:31:12.955744 # ok 185 # SKIP Disabled ZA for VL 992
6078 11:31:12.955907 # ok 186 # SKIP Get and set data for VL 992
6079 11:31:12.956072 # ok 187 Set VL 1008
6080 11:31:12.956225 # ok 188 # SKIP Disabled ZA for VL 1008
6081 11:31:12.956380 # ok 189 # SKIP Get and set data for VL 1008
6082 11:31:12.956546 # ok 190 Set VL 1024
6083 11:31:12.956691 # ok 191 # SKIP Disabled ZA for VL 1024
6084 11:31:12.956811 # ok 192 # SKIP Get and set data for VL 1024
6085 11:31:12.956922 # ok 193 Set VL 1040
6086 11:31:12.957064 # ok 194 # SKIP Disabled ZA for VL 1040
6087 11:31:12.957181 # ok 195 # SKIP Get and set data for VL 1040
6088 11:31:12.957293 # ok 196 Set VL 1056
6089 11:31:12.957404 # ok 197 # SKIP Disabled ZA for VL 1056
6090 11:31:12.957514 # ok 198 # SKIP Get and set data for VL 1056
6091 11:31:12.957625 # ok 199 Set VL 1072
6092 11:31:12.957856 # ok 200 # SKIP Disabled ZA for VL 1072
6093 11:31:12.958052 # ok 201 # SKIP Get and set data for VL 1072
6094 11:31:12.958235 # ok 202 Set VL 1088
6095 11:31:12.958415 # ok 203 # SKIP Disabled ZA for VL 1088
6096 11:31:12.958596 # ok 204 # SKIP Get and set data for VL 1088
6097 11:31:12.958758 # ok 205 Set VL 1104
6098 11:31:12.958907 # ok 206 # SKIP Disabled ZA for VL 1104
6099 11:31:12.959049 # ok 207 # SKIP Get and set data for VL 1104
6100 11:31:12.959191 # ok 208 Set VL 1120
6101 11:31:12.959333 # ok 209 # SKIP Disabled ZA for VL 1120
6102 11:31:12.959475 # ok 210 # SKIP Get and set data for VL 1120
6103 11:31:12.959617 # ok 211 Set VL 1136
6104 11:31:12.962613 # ok 212 # SKIP Disabled ZA for VL 1136
6105 11:31:12.962997 # ok 213 # SKIP Get and set data for VL 1136
6106 11:31:12.963104 # ok 214 Set VL 1152
6107 11:31:12.963196 # ok 215 # SKIP Disabled ZA for VL 1152
6108 11:31:12.963283 # ok 216 # SKIP Get and set data for VL 1152
6109 11:31:12.963368 # ok 217 Set VL 1168
6110 11:31:12.963468 # ok 218 # SKIP Disabled ZA for VL 1168
6111 11:31:12.963555 # ok 219 # SKIP Get and set data for VL 1168
6112 11:31:12.963639 # ok 220 Set VL 1184
6113 11:31:12.963723 # ok 221 # SKIP Disabled ZA for VL 1184
6114 11:31:12.963830 # ok 222 # SKIP Get and set data for VL 1184
6115 11:31:12.963918 # ok 223 Set VL 1200
6116 11:31:12.964002 # ok 224 # SKIP Disabled ZA for VL 1200
6117 11:31:12.964099 # ok 225 # SKIP Get and set data for VL 1200
6118 11:31:12.964187 # ok 226 Set VL 1216
6119 11:31:12.964285 # ok 227 # SKIP Disabled ZA for VL 1216
6120 11:31:12.964372 # ok 228 # SKIP Get and set data for VL 1216
6121 11:31:12.964457 # ok 229 Set VL 1232
6122 11:31:12.964559 # ok 230 # SKIP Disabled ZA for VL 1232
6123 11:31:12.964644 # ok 231 # SKIP Get and set data for VL 1232
6124 11:31:12.964733 # ok 232 Set VL 1248
6125 11:31:12.965468 # ok 233 # SKIP Disabled ZA for VL 1248
6126 11:31:12.965857 # ok 234 # SKIP Get and set data for VL 1248
6127 11:31:12.966033 # ok 235 Set VL 1264
6128 11:31:12.966190 # ok 236 # SKIP Disabled ZA for VL 1264
6129 11:31:12.966347 # ok 237 # SKIP Get and set data for VL 1264
6130 11:31:12.966541 # ok 238 Set VL 1280
6131 11:31:12.966737 # ok 239 # SKIP Disabled ZA for VL 1280
6132 11:31:12.966912 # ok 240 # SKIP Get and set data for VL 1280
6133 11:31:12.967063 # ok 241 Set VL 1296
6134 11:31:12.967218 # ok 242 # SKIP Disabled ZA for VL 1296
6135 11:31:12.967379 # ok 243 # SKIP Get and set data for VL 1296
6136 11:31:12.967539 # ok 244 Set VL 1312
6137 11:31:12.967697 # ok 245 # SKIP Disabled ZA for VL 1312
6138 11:31:12.967858 # ok 246 # SKIP Get and set data for VL 1312
6139 11:31:12.968023 # ok 247 Set VL 1328
6140 11:31:12.968215 # ok 248 # SKIP Disabled ZA for VL 1328
6141 11:31:12.968361 # ok 249 # SKIP Get and set data for VL 1328
6142 11:31:12.968520 # ok 250 Set VL 1344
6143 11:31:12.968675 # ok 251 # SKIP Disabled ZA for VL 1344
6144 11:31:12.968794 # ok 252 # SKIP Get and set data for VL 1344
6145 11:31:12.968909 # ok 253 Set VL 1360
6146 11:31:12.969022 # ok 254 # SKIP Disabled ZA for VL 1360
6147 11:31:12.969136 # ok 255 # SKIP Get and set data for VL 1360
6148 11:31:12.969250 # ok 256 Set VL 1376
6149 11:31:12.969362 # ok 257 # SKIP Disabled ZA for VL 1376
6150 11:31:12.969476 # ok 258 # SKIP Get and set data for VL 1376
6151 11:31:12.969588 # ok 259 Set VL 1392
6152 11:31:12.969762 # ok 260 # SKIP Disabled ZA for VL 1392
6153 11:31:12.969961 # ok 261 # SKIP Get and set data for VL 1392
6154 11:31:12.970142 # ok 262 Set VL 1408
6155 11:31:12.970284 # ok 263 # SKIP Disabled ZA for VL 1408
6156 11:31:12.970426 # ok 264 # SKIP Get and set data for VL 1408
6157 11:31:12.970565 # ok 265 Set VL 1424
6158 11:31:12.970706 # ok 266 # SKIP Disabled ZA for VL 1424
6159 11:31:12.970884 # ok 267 # SKIP Get and set data for VL 1424
6160 11:31:12.971019 # ok 268 Set VL 1440
6161 11:31:12.971159 # ok 269 # SKIP Disabled ZA for VL 1440
6162 11:31:12.971300 # ok 270 # SKIP Get and set data for VL 1440
6163 11:31:12.971439 # ok 271 Set VL 1456
6164 11:31:12.971578 # ok 272 # SKIP Disabled ZA for VL 1456
6165 11:31:12.975808 # ok 273 # SKIP Get and set data for VL 1456
6166 11:31:12.976254 # ok 274 Set VL 1472
6167 11:31:12.976416 # ok 275 # SKIP Disabled ZA for VL 1472
6168 11:31:12.976572 # ok 276 # SKIP Get and set data for VL 1472
6169 11:31:12.976716 # ok 277 Set VL 1488
6170 11:31:12.976890 # ok 278 # SKIP Disabled ZA for VL 1488
6171 11:31:12.977098 # ok 279 # SKIP Get and set data for VL 1488
6172 11:31:12.977239 # ok 280 Set VL 1504
6173 11:31:12.977381 # ok 281 # SKIP Disabled ZA for VL 1504
6174 11:31:12.977521 # ok 282 # SKIP Get and set data for VL 1504
6175 11:31:12.977673 # ok 283 Set VL 1520
6176 11:31:12.977816 # ok 284 # SKIP Disabled ZA for VL 1520
6177 11:31:12.977994 # ok 285 # SKIP Get and set data for VL 1520
6178 11:31:12.978135 # ok 286 Set VL 1536
6179 11:31:12.978281 # ok 287 # SKIP Disabled ZA for VL 1536
6180 11:31:12.978421 # ok 288 # SKIP Get and set data for VL 1536
6181 11:31:12.978617 # ok 289 Set VL 1552
6182 11:31:12.978789 # ok 290 # SKIP Disabled ZA for VL 1552
6183 11:31:12.978959 # ok 291 # SKIP Get and set data for VL 1552
6184 11:31:12.979166 # ok 292 Set VL 1568
6185 11:31:12.979334 # ok 293 # SKIP Disabled ZA for VL 1568
6186 11:31:12.979541 # ok 294 # SKIP Get and set data for VL 1568
6187 11:31:12.979705 # ok 295 Set VL 1584
6188 11:31:12.979830 # ok 296 # SKIP Disabled ZA for VL 1584
6189 11:31:12.979949 # ok 297 # SKIP Get and set data for VL 1584
6190 11:31:12.980066 # ok 298 Set VL 1600
6191 11:31:12.980181 # ok 299 # SKIP Disabled ZA for VL 1600
6192 11:31:12.980296 # ok 300 # SKIP Get and set data for VL 1600
6193 11:31:12.980412 # ok 301 Set VL 1616
6194 11:31:12.980528 # ok 302 # SKIP Disabled ZA for VL 1616
6195 11:31:12.980644 # ok 303 # SKIP Get and set data for VL 1616
6196 11:31:12.980760 # ok 304 Set VL 1632
6197 11:31:12.980877 # ok 305 # SKIP Disabled ZA for VL 1632
6198 11:31:12.980990 # ok 306 # SKIP Get and set data for VL 1632
6199 11:31:12.981105 # ok 307 Set VL 1648
6200 11:31:12.981220 # ok 308 # SKIP Disabled ZA for VL 1648
6201 11:31:12.981335 # ok 309 # SKIP Get and set data for VL 1648
6202 11:31:12.981449 # ok 310 Set VL 1664
6203 11:31:12.981563 # ok 311 # SKIP Disabled ZA for VL 1664
6204 11:31:12.981689 # ok 312 # SKIP Get and set data for VL 1664
6205 11:31:12.981843 # ok 313 Set VL 1680
6206 11:31:12.981965 # ok 314 # SKIP Disabled ZA for VL 1680
6207 11:31:12.982081 # ok 315 # SKIP Get and set data for VL 1680
6208 11:31:12.982197 # ok 316 Set VL 1696
6209 11:31:12.982312 # ok 317 # SKIP Disabled ZA for VL 1696
6210 11:31:12.982434 # ok 318 # SKIP Get and set data for VL 1696
6211 11:31:12.982609 # ok 319 Set VL 1712
6212 11:31:12.982753 # ok 320 # SKIP Disabled ZA for VL 1712
6213 11:31:12.982893 # ok 321 # SKIP Get and set data for VL 1712
6214 11:31:12.983032 # ok 322 Set VL 1728
6215 11:31:12.983171 # ok 323 # SKIP Disabled ZA for VL 1728
6216 11:31:12.983309 # ok 324 # SKIP Get and set data for VL 1728
6217 11:31:12.983448 # ok 325 Set VL 1744
6218 11:31:12.983586 # ok 326 # SKIP Disabled ZA for VL 1744
6219 11:31:12.990003 # ok 327 # SKIP Get and set data for VL 1744
6220 11:31:12.990301 # ok 328 Set VL 1760
6221 11:31:12.990694 # ok 329 # SKIP Disabled ZA for VL 1760
6222 11:31:12.990854 # ok 330 # SKIP Get and set data for VL 1760
6223 11:31:12.991003 # ok 331 Set VL 1776
6224 11:31:12.991146 # ok 332 # SKIP Disabled ZA for VL 1776
6225 11:31:12.991309 # ok 333 # SKIP Get and set data for VL 1776
6226 11:31:12.991501 # ok 334 Set VL 1792
6227 11:31:12.991676 # ok 335 # SKIP Disabled ZA for VL 1792
6228 11:31:12.991837 # ok 336 # SKIP Get and set data for VL 1792
6229 11:31:12.992018 # ok 337 Set VL 1808
6230 11:31:12.992205 # ok 338 # SKIP Disabled ZA for VL 1808
6231 11:31:12.992367 # ok 339 # SKIP Get and set data for VL 1808
6232 11:31:12.992534 # ok 340 Set VL 1824
6233 11:31:12.992681 # ok 341 # SKIP Disabled ZA for VL 1824
6234 11:31:12.992820 # ok 342 # SKIP Get and set data for VL 1824
6235 11:31:12.992960 # ok 343 Set VL 1840
6236 11:31:12.993099 # ok 344 # SKIP Disabled ZA for VL 1840
6237 11:31:12.993237 # ok 345 # SKIP Get and set data for VL 1840
6238 11:31:12.993377 # ok 346 Set VL 1856
6239 11:31:12.993516 # ok 347 # SKIP Disabled ZA for VL 1856
6240 11:31:12.993669 # ok 348 # SKIP Get and set data for VL 1856
6241 11:31:12.993811 # ok 349 Set VL 1872
6242 11:31:12.993950 # ok 350 # SKIP Disabled ZA for VL 1872
6243 11:31:12.994089 # ok 351 # SKIP Get and set data for VL 1872
6244 11:31:12.994227 # ok 352 Set VL 1888
6245 11:31:12.994366 # ok 353 # SKIP Disabled ZA for VL 1888
6246 11:31:12.994547 # ok 354 # SKIP Get and set data for VL 1888
6247 11:31:12.994681 # ok 355 Set VL 1904
6248 11:31:12.994821 # ok 356 # SKIP Disabled ZA for VL 1904
6249 11:31:12.994964 # ok 357 # SKIP Get and set data for VL 1904
6250 11:31:12.995103 # ok 358 Set VL 1920
6251 11:31:12.995745 # ok 359 # SKIP Disabled ZA for VL 1920
6252 11:31:12.995946 # ok 360 # SKIP Get and set data for VL 1920
6253 11:31:12.996181 # ok 361 Set VL 1936
6254 11:31:12.996373 # ok 362 # SKIP Disabled ZA for VL 1936
6255 11:31:12.996580 # ok 363 # SKIP Get and set data for VL 1936
6256 11:31:12.996761 # ok 364 Set VL 1952
6257 11:31:12.996905 # ok 365 # SKIP Disabled ZA for VL 1952
6258 11:31:12.997071 # ok 366 # SKIP Get and set data for VL 1952
6259 11:31:12.997228 # ok 367 Set VL 1968
6260 11:31:12.997368 # ok 368 # SKIP Disabled ZA for VL 1968
6261 11:31:12.997511 # ok 369 # SKIP Get and set data for VL 1968
6262 11:31:12.997662 # ok 370 Set VL 1984
6263 11:31:12.997823 # ok 371 # SKIP Disabled ZA for VL 1984
6264 11:31:12.997985 # ok 372 # SKIP Get and set data for VL 1984
6265 11:31:12.998147 # ok 373 Set VL 2000
6266 11:31:12.998328 # ok 374 # SKIP Disabled ZA for VL 2000
6267 11:31:12.998496 # ok 375 # SKIP Get and set data for VL 2000
6268 11:31:12.998670 # ok 376 Set VL 2016
6269 11:31:12.998893 # ok 377 # SKIP Disabled ZA for VL 2016
6270 11:31:12.999045 # ok 378 # SKIP Get and set data for VL 2016
6271 11:31:12.999181 # ok 379 Set VL 2032
6272 11:31:12.999318 # ok 380 # SKIP Disabled ZA for VL 2032
6273 11:31:12.999453 # ok 381 # SKIP Get and set data for VL 2032
6274 11:31:12.999603 # ok 382 Set VL 2048
6275 11:31:12.999753 # ok 383 # SKIP Disabled ZA for VL 2048
6276 11:31:12.999902 # ok 384 # SKIP Get and set data for VL 2048
6277 11:31:13.000043 # ok 385 Set VL 2064
6278 11:31:13.000180 # ok 386 # SKIP Disabled ZA for VL 2064
6279 11:31:13.000332 # ok 387 # SKIP Get and set data for VL 2064
6280 11:31:13.000485 # ok 388 Set VL 2080
6281 11:31:13.000640 # ok 389 # SKIP Disabled ZA for VL 2080
6282 11:31:13.000783 # ok 390 # SKIP Get and set data for VL 2080
6283 11:31:13.000908 # ok 391 Set VL 2096
6284 11:31:13.001055 # ok 392 # SKIP Disabled ZA for VL 2096
6285 11:31:13.001208 # ok 393 # SKIP Get and set data for VL 2096
6286 11:31:13.001357 # ok 394 Set VL 2112
6287 11:31:13.001520 # ok 395 # SKIP Disabled ZA for VL 2112
6288 11:31:13.002211 # ok 396 # SKIP Get and set data for VL 2112
6289 11:31:13.002389 # ok 397 Set VL 2128
6290 11:31:13.002512 # ok 398 # SKIP Disabled ZA for VL 2128
6291 11:31:13.002630 # ok 399 # SKIP Get and set data for VL 2128
6292 11:31:13.002746 # ok 400 Set VL 2144
6293 11:31:13.002861 # ok 401 # SKIP Disabled ZA for VL 2144
6294 11:31:13.002974 # ok 402 # SKIP Get and set data for VL 2144
6295 11:31:13.003088 # ok 403 Set VL 2160
6296 11:31:13.003203 # ok 404 # SKIP Disabled ZA for VL 2160
6297 11:31:13.003317 # ok 405 # SKIP Get and set data for VL 2160
6298 11:31:13.003431 # ok 406 Set VL 2176
6299 11:31:13.003546 # ok 407 # SKIP Disabled ZA for VL 2176
6300 11:31:13.003659 # ok 408 # SKIP Get and set data for VL 2176
6301 11:31:13.003774 # ok 409 Set VL 2192
6302 11:31:13.003888 # ok 410 # SKIP Disabled ZA for VL 2192
6303 11:31:13.004004 # ok 411 # SKIP Get and set data for VL 2192
6304 11:31:13.004118 # ok 412 Set VL 2208
6305 11:31:13.004452 # ok 413 # SKIP Disabled ZA for VL 2208
6306 11:31:13.004578 # ok 414 # SKIP Get and set data for VL 2208
6307 11:31:13.004694 # ok 415 Set VL 2224
6308 11:31:13.004810 # ok 416 # SKIP Disabled ZA for VL 2224
6309 11:31:13.004928 # ok 417 # SKIP Get and set data for VL 2224
6310 11:31:13.005045 # ok 418 Set VL 2240
6311 11:31:13.005160 # ok 419 # SKIP Disabled ZA for VL 2240
6312 11:31:13.005275 # ok 420 # SKIP Get and set data for VL 2240
6313 11:31:13.005390 # ok 421 Set VL 2256
6314 11:31:13.005504 # ok 422 # SKIP Disabled ZA for VL 2256
6315 11:31:13.005618 # ok 423 # SKIP Get and set data for VL 2256
6316 11:31:13.005748 # ok 424 Set VL 2272
6317 11:31:13.005860 # ok 425 # SKIP Disabled ZA for VL 2272
6318 11:31:13.005976 # ok 426 # SKIP Get and set data for VL 2272
6319 11:31:13.006088 # ok 427 Set VL 2288
6320 11:31:13.006200 # ok 428 # SKIP Disabled ZA for VL 2288
6321 11:31:13.006312 # ok 429 # SKIP Get and set data for VL 2288
6322 11:31:13.006424 # ok 430 Set VL 2304
6323 11:31:13.006536 # ok 431 # SKIP Disabled ZA for VL 2304
6324 11:31:13.060573 # ok 432 # SKIP Get and set data for VL 2304
6325 11:31:13.060864 # ok 433 Set VL 2320
6326 11:31:13.061259 # ok 434 # SKIP Disabled ZA for VL 2320
6327 11:31:13.061402 # ok 435 # SKIP Get and set data for VL 2320
6328 11:31:13.066073 # ok 436 Set VL 2336
6329 11:31:13.066310 # ok 437 # SKIP Disabled ZA for VL 2336
6330 11:31:13.066623 # ok 438 # SKIP Get and set data for VL 2336
6331 11:31:13.066730 # ok 439 Set VL 2352
6332 11:31:13.066821 # ok 440 # SKIP Disabled ZA for VL 2352
6333 11:31:13.066907 # ok 441 # SKIP Get and set data for VL 2352
6334 11:31:13.066991 # ok 442 Set VL 2368
6335 11:31:13.067076 # ok 443 # SKIP Disabled ZA for VL 2368
6336 11:31:13.067161 # ok 444 # SKIP Get and set data for VL 2368
6337 11:31:13.067245 # ok 445 Set VL 2384
6338 11:31:13.067348 # ok 446 # SKIP Disabled ZA for VL 2384
6339 11:31:13.067436 # ok 447 # SKIP Get and set data for VL 2384
6340 11:31:13.067522 # ok 448 Set VL 2400
6341 11:31:13.067604 # ok 449 # SKIP Disabled ZA for VL 2400
6342 11:31:13.067686 # ok 450 # SKIP Get and set data for VL 2400
6343 11:31:13.067769 # ok 451 Set VL 2416
6344 11:31:13.067853 # ok 452 # SKIP Disabled ZA for VL 2416
6345 11:31:13.067937 # ok 453 # SKIP Get and set data for VL 2416
6346 11:31:13.068023 # ok 454 Set VL 2432
6347 11:31:13.068125 # ok 455 # SKIP Disabled ZA for VL 2432
6348 11:31:13.068208 # ok 456 # SKIP Get and set data for VL 2432
6349 11:31:13.068290 # ok 457 Set VL 2448
6350 11:31:13.068372 # ok 458 # SKIP Disabled ZA for VL 2448
6351 11:31:13.068454 # ok 459 # SKIP Get and set data for VL 2448
6352 11:31:13.068536 # ok 460 Set VL 2464
6353 11:31:13.068617 # ok 461 # SKIP Disabled ZA for VL 2464
6354 11:31:13.068701 # ok 462 # SKIP Get and set data for VL 2464
6355 11:31:13.068783 # ok 463 Set VL 2480
6356 11:31:13.068883 # ok 464 # SKIP Disabled ZA for VL 2480
6357 11:31:13.068968 # ok 465 # SKIP Get and set data for VL 2480
6358 11:31:13.069055 # ok 466 Set VL 2496
6359 11:31:13.069136 # ok 467 # SKIP Disabled ZA for VL 2496
6360 11:31:13.069215 # ok 468 # SKIP Get and set data for VL 2496
6361 11:31:13.069297 # ok 469 Set VL 2512
6362 11:31:13.084637 # ok 470 # SKIP Disabled ZA for VL 2512
6363 11:31:13.085033 # ok 471 # SKIP Get and set data for VL 2512
6364 11:31:13.095537 # ok 472 Set VL 2528
6365 11:31:13.095888 # ok 473 # SKIP Disabled ZA for VL 2528
6366 11:31:13.095997 # ok 474 # SKIP Get and set data for VL 2528
6367 11:31:13.096091 # ok 475 Set VL 2544
6368 11:31:13.096177 # ok 476 # SKIP Disabled ZA for VL 2544
6369 11:31:13.096279 # ok 477 # SKIP Get and set data for VL 2544
6370 11:31:13.096365 # ok 478 Set VL 2560
6371 11:31:13.096447 # ok 479 # SKIP Disabled ZA for VL 2560
6372 11:31:13.096531 # ok 480 # SKIP Get and set data for VL 2560
6373 11:31:13.096631 # ok 481 Set VL 2576
6374 11:31:13.096718 # ok 482 # SKIP Disabled ZA for VL 2576
6375 11:31:13.096803 # ok 483 # SKIP Get and set data for VL 2576
6376 11:31:13.096903 # ok 484 Set VL 2592
6377 11:31:13.104279 # ok 485 # SKIP Disabled ZA for VL 2592
6378 11:31:13.104755 # ok 486 # SKIP Get and set data for VL 2592
6379 11:31:13.104916 # ok 487 Set VL 2608
6380 11:31:13.105040 # ok 488 # SKIP Disabled ZA for VL 2608
6381 11:31:13.105157 # ok 489 # SKIP Get and set data for VL 2608
6382 11:31:13.105271 # ok 490 Set VL 2624
6383 11:31:13.106247 # ok 491 # SKIP Disabled ZA for VL 2624
6384 11:31:13.106676 # ok 492 # SKIP Get and set data for VL 2624
6385 11:31:13.106862 # ok 493 Set VL 2640
6386 11:31:13.106999 # ok 494 # SKIP Disabled ZA for VL 2640
6387 11:31:13.107127 # ok 495 # SKIP Get and set data for VL 2640
6388 11:31:13.107298 # ok 496 Set VL 2656
6389 11:31:13.107494 # ok 497 # SKIP Disabled ZA for VL 2656
6390 11:31:13.107693 # ok 498 # SKIP Get and set data for VL 2656
6391 11:31:13.107887 # ok 499 Set VL 2672
6392 11:31:13.108093 # ok 500 # SKIP Disabled ZA for VL 2672
6393 11:31:13.108279 # ok 501 # SKIP Get and set data for VL 2672
6394 11:31:13.108484 # ok 502 Set VL 2688
6395 11:31:13.108722 # ok 503 # SKIP Disabled ZA for VL 2688
6396 11:31:13.108884 # ok 504 # SKIP Get and set data for VL 2688
6397 11:31:13.109015 # ok 505 Set VL 2704
6398 11:31:13.109134 # ok 506 # SKIP Disabled ZA for VL 2704
6399 11:31:13.109249 # ok 507 # SKIP Get and set data for VL 2704
6400 11:31:13.109363 # ok 508 Set VL 2720
6401 11:31:13.109477 # ok 509 # SKIP Disabled ZA for VL 2720
6402 11:31:13.109590 # ok 510 # SKIP Get and set data for VL 2720
6403 11:31:13.109724 # ok 511 Set VL 2736
6404 11:31:13.109839 # ok 512 # SKIP Disabled ZA for VL 2736
6405 11:31:13.109952 # ok 513 # SKIP Get and set data for VL 2736
6406 11:31:13.110067 # ok 514 Set VL 2752
6407 11:31:13.110183 # ok 515 # SKIP Disabled ZA for VL 2752
6408 11:31:13.110304 # ok 516 # SKIP Get and set data for VL 2752
6409 11:31:13.110477 # ok 517 Set VL 2768
6410 11:31:13.110620 # ok 518 # SKIP Disabled ZA for VL 2768
6411 11:31:13.114247 # ok 519 # SKIP Get and set data for VL 2768
6412 11:31:13.114657 # ok 520 Set VL 2784
6413 11:31:13.114849 # ok 521 # SKIP Disabled ZA for VL 2784
6414 11:31:13.115041 # ok 522 # SKIP Get and set data for VL 2784
6415 11:31:13.115246 # ok 523 Set VL 2800
6416 11:31:13.115442 # ok 524 # SKIP Disabled ZA for VL 2800
6417 11:31:13.115622 # ok 525 # SKIP Get and set data for VL 2800
6418 11:31:13.115779 # ok 526 Set VL 2816
6419 11:31:13.115982 # ok 527 # SKIP Disabled ZA for VL 2816
6420 11:31:13.116157 # ok 528 # SKIP Get and set data for VL 2816
6421 11:31:13.116298 # ok 529 Set VL 2832
6422 11:31:13.116447 # ok 530 # SKIP Disabled ZA for VL 2832
6423 11:31:13.116603 # ok 531 # SKIP Get and set data for VL 2832
6424 11:31:13.116785 # ok 532 Set VL 2848
6425 11:31:13.116913 # ok 533 # SKIP Disabled ZA for VL 2848
6426 11:31:13.117057 # ok 534 # SKIP Get and set data for VL 2848
6427 11:31:13.117207 # ok 535 Set VL 2864
6428 11:31:13.117325 # ok 536 # SKIP Disabled ZA for VL 2864
6429 11:31:13.117439 # ok 537 # SKIP Get and set data for VL 2864
6430 11:31:13.117554 # ok 538 Set VL 2880
6431 11:31:13.117704 # ok 539 # SKIP Disabled ZA for VL 2880
6432 11:31:13.117911 # ok 540 # SKIP Get and set data for VL 2880
6433 11:31:13.118099 # ok 541 Set VL 2896
6434 11:31:13.118282 # ok 542 # SKIP Disabled ZA for VL 2896
6435 11:31:13.118442 # ok 543 # SKIP Get and set data for VL 2896
6436 11:31:13.118582 # ok 544 Set VL 2912
6437 11:31:13.118722 # ok 545 # SKIP Disabled ZA for VL 2912
6438 11:31:13.118861 # ok 546 # SKIP Get and set data for VL 2912
6439 11:31:13.122694 # ok 547 Set VL 2928
6440 11:31:13.122922 # ok 548 # SKIP Disabled ZA for VL 2928
6441 11:31:13.123109 # ok 549 # SKIP Get and set data for VL 2928
6442 11:31:13.123276 # ok 550 Set VL 2944
6443 11:31:13.123489 # ok 551 # SKIP Disabled ZA for VL 2944
6444 11:31:13.123668 # ok 552 # SKIP Get and set data for VL 2944
6445 11:31:13.123842 # ok 553 Set VL 2960
6446 11:31:13.124005 # ok 554 # SKIP Disabled ZA for VL 2960
6447 11:31:13.124204 # ok 555 # SKIP Get and set data for VL 2960
6448 11:31:13.124374 # ok 556 Set VL 2976
6449 11:31:13.124538 # ok 557 # SKIP Disabled ZA for VL 2976
6450 11:31:13.124699 # ok 558 # SKIP Get and set data for VL 2976
6451 11:31:13.124822 # ok 559 Set VL 2992
6452 11:31:13.124937 # ok 560 # SKIP Disabled ZA for VL 2992
6453 11:31:13.125049 # ok 561 # SKIP Get and set data for VL 2992
6454 11:31:13.125160 # ok 562 Set VL 3008
6455 11:31:13.125271 # ok 563 # SKIP Disabled ZA for VL 3008
6456 11:31:13.125383 # ok 564 # SKIP Get and set data for VL 3008
6457 11:31:13.125493 # ok 565 Set VL 3024
6458 11:31:13.125604 # ok 566 # SKIP Disabled ZA for VL 3024
6459 11:31:13.125806 # ok 567 # SKIP Get and set data for VL 3024
6460 11:31:13.125939 # ok 568 Set VL 3040
6461 11:31:13.126055 # ok 569 # SKIP Disabled ZA for VL 3040
6462 11:31:13.126220 # ok 570 # SKIP Get and set data for VL 3040
6463 11:31:13.126381 # ok 571 Set VL 3056
6464 11:31:13.126525 # ok 572 # SKIP Disabled ZA for VL 3056
6465 11:31:13.126666 # ok 573 # SKIP Get and set data for VL 3056
6466 11:31:13.126807 # ok 574 Set VL 3072
6467 11:31:13.130387 # ok 575 # SKIP Disabled ZA for VL 3072
6468 11:31:13.130804 # ok 576 # SKIP Get and set data for VL 3072
6469 11:31:13.130984 # ok 577 Set VL 3088
6470 11:31:13.131176 # ok 578 # SKIP Disabled ZA for VL 3088
6471 11:31:13.131345 # ok 579 # SKIP Get and set data for VL 3088
6472 11:31:13.131572 # ok 580 Set VL 3104
6473 11:31:13.131745 # ok 581 # SKIP Disabled ZA for VL 3104
6474 11:31:13.131917 # ok 582 # SKIP Get and set data for VL 3104
6475 11:31:13.132062 # ok 583 Set VL 3120
6476 11:31:13.132207 # ok 584 # SKIP Disabled ZA for VL 3120
6477 11:31:13.132348 # ok 585 # SKIP Get and set data for VL 3120
6478 11:31:13.132487 # ok 586 Set VL 3136
6479 11:31:13.132656 # ok 587 # SKIP Disabled ZA for VL 3136
6480 11:31:13.132844 # ok 588 # SKIP Get and set data for VL 3136
6481 11:31:13.133015 # ok 589 Set VL 3152
6482 11:31:13.133193 # ok 590 # SKIP Disabled ZA for VL 3152
6483 11:31:13.136213 # ok 591 # SKIP Get and set data for VL 3152
6484 11:31:13.136638 # ok 592 Set VL 3168
6485 11:31:13.136799 # ok 593 # SKIP Disabled ZA for VL 3168
6486 11:31:13.136919 # ok 594 # SKIP Get and set data for VL 3168
6487 11:31:13.137035 # ok 595 Set VL 3184
6488 11:31:13.137149 # ok 596 # SKIP Disabled ZA for VL 3184
6489 11:31:13.138569 # ok 597 # SKIP Get and set data for VL 3184
6490 11:31:13.138974 # ok 598 Set VL 3200
6491 11:31:13.139172 # ok 599 # SKIP Disabled ZA for VL 3200
6492 11:31:13.139346 # ok 600 # SKIP Get and set data for VL 3200
6493 11:31:13.139500 # ok 601 Set VL 3216
6494 11:31:13.139628 # ok 602 # SKIP Disabled ZA for VL 3216
6495 11:31:13.139786 # ok 603 # SKIP Get and set data for VL 3216
6496 11:31:13.139968 # ok 604 Set VL 3232
6497 11:31:13.140109 # ok 605 # SKIP Disabled ZA for VL 3232
6498 11:31:13.140236 # ok 606 # SKIP Get and set data for VL 3232
6499 11:31:13.140371 # ok 607 Set VL 3248
6500 11:31:13.140544 # ok 608 # SKIP Disabled ZA for VL 3248
6501 11:31:13.140690 # ok 609 # SKIP Get and set data for VL 3248
6502 11:31:13.140871 # ok 610 Set VL 3264
6503 11:31:13.141008 # ok 611 # SKIP Disabled ZA for VL 3264
6504 11:31:13.141149 # ok 612 # SKIP Get and set data for VL 3264
6505 11:31:13.141291 # ok 613 Set VL 3280
6506 11:31:13.141432 # ok 614 # SKIP Disabled ZA for VL 3280
6507 11:31:13.141573 # ok 615 # SKIP Get and set data for VL 3280
6508 11:31:13.141732 # ok 616 Set VL 3296
6509 11:31:13.141873 # ok 617 # SKIP Disabled ZA for VL 3296
6510 11:31:13.142015 # ok 618 # SKIP Get and set data for VL 3296
6511 11:31:13.142156 # ok 619 Set VL 3312
6512 11:31:13.144019 # ok 620 # SKIP Disabled ZA for VL 3312
6513 11:31:13.144438 # ok 621 # SKIP Get and set data for VL 3312
6514 11:31:13.144635 # ok 622 Set VL 3328
6515 11:31:13.144805 # ok 623 # SKIP Disabled ZA for VL 3328
6516 11:31:13.144950 # ok 624 # SKIP Get and set data for VL 3328
6517 11:31:13.145091 # ok 625 Set VL 3344
6518 11:31:13.145264 # ok 626 # SKIP Disabled ZA for VL 3344
6519 11:31:13.151019 # ok 627 # SKIP Get and set data for VL 3344
6520 11:31:13.151458 # ok 628 Set VL 3360
6521 11:31:13.151637 # ok 629 # SKIP Disabled ZA for VL 3360
6522 11:31:13.151839 # ok 630 # SKIP Get and set data for VL 3360
6523 11:31:13.152056 # ok 631 Set VL 3376
6524 11:31:13.152242 # ok 632 # SKIP Disabled ZA for VL 3376
6525 11:31:13.152476 # ok 633 # SKIP Get and set data for VL 3376
6526 11:31:13.152655 # ok 634 Set VL 3392
6527 11:31:13.152782 # ok 635 # SKIP Disabled ZA for VL 3392
6528 11:31:13.152897 # ok 636 # SKIP Get and set data for VL 3392
6529 11:31:13.153010 # ok 637 Set VL 3408
6530 11:31:13.153122 # ok 638 # SKIP Disabled ZA for VL 3408
6531 11:31:13.153234 # ok 639 # SKIP Get and set data for VL 3408
6532 11:31:13.153345 # ok 640 Set VL 3424
6533 11:31:13.153456 # ok 641 # SKIP Disabled ZA for VL 3424
6534 11:31:13.153566 # ok 642 # SKIP Get and set data for VL 3424
6535 11:31:13.153695 # ok 643 Set VL 3440
6536 11:31:13.153809 # ok 644 # SKIP Disabled ZA for VL 3440
6537 11:31:13.153944 # ok 645 # SKIP Get and set data for VL 3440
6538 11:31:13.154062 # ok 646 Set VL 3456
6539 11:31:13.158344 # ok 647 # SKIP Disabled ZA for VL 3456
6540 11:31:13.158787 # ok 648 # SKIP Get and set data for VL 3456
6541 11:31:13.158982 # ok 649 Set VL 3472
6542 11:31:13.159148 # ok 650 # SKIP Disabled ZA for VL 3472
6543 11:31:13.159310 # ok 651 # SKIP Get and set data for VL 3472
6544 11:31:13.159469 # ok 652 Set VL 3488
6545 11:31:13.159666 # ok 653 # SKIP Disabled ZA for VL 3488
6546 11:31:13.159840 # ok 654 # SKIP Get and set data for VL 3488
6547 11:31:13.160018 # ok 655 Set VL 3504
6548 11:31:13.160173 # ok 656 # SKIP Disabled ZA for VL 3504
6549 11:31:13.160347 # ok 657 # SKIP Get and set data for VL 3504
6550 11:31:13.160529 # ok 658 Set VL 3520
6551 11:31:13.160683 # ok 659 # SKIP Disabled ZA for VL 3520
6552 11:31:13.160802 # ok 660 # SKIP Get and set data for VL 3520
6553 11:31:13.160919 # ok 661 Set VL 3536
6554 11:31:13.161035 # ok 662 # SKIP Disabled ZA for VL 3536
6555 11:31:13.161183 # ok 663 # SKIP Get and set data for VL 3536
6556 11:31:13.161306 # ok 664 Set VL 3552
6557 11:31:13.161422 # ok 665 # SKIP Disabled ZA for VL 3552
6558 11:31:13.161536 # ok 666 # SKIP Get and set data for VL 3552
6559 11:31:13.161663 # ok 667 Set VL 3568
6560 11:31:13.161829 # ok 668 # SKIP Disabled ZA for VL 3568
6561 11:31:13.161954 # ok 669 # SKIP Get and set data for VL 3568
6562 11:31:13.162071 # ok 670 Set VL 3584
6563 11:31:13.162189 # ok 671 # SKIP Disabled ZA for VL 3584
6564 11:31:13.162304 # ok 672 # SKIP Get and set data for VL 3584
6565 11:31:13.162420 # ok 673 Set VL 3600
6566 11:31:13.162533 # ok 674 # SKIP Disabled ZA for VL 3600
6567 11:31:13.166427 # ok 675 # SKIP Get and set data for VL 3600
6568 11:31:13.166861 # ok 676 Set VL 3616
6569 11:31:13.167052 # ok 677 # SKIP Disabled ZA for VL 3616
6570 11:31:13.167222 # ok 678 # SKIP Get and set data for VL 3616
6571 11:31:13.167425 # ok 679 Set VL 3632
6572 11:31:13.167626 # ok 680 # SKIP Disabled ZA for VL 3632
6573 11:31:13.167830 # ok 681 # SKIP Get and set data for VL 3632
6574 11:31:13.168028 # ok 682 Set VL 3648
6575 11:31:13.168220 # ok 683 # SKIP Disabled ZA for VL 3648
6576 11:31:13.168384 # ok 684 # SKIP Get and set data for VL 3648
6577 11:31:13.168529 # ok 685 Set VL 3664
6578 11:31:13.168686 # ok 686 # SKIP Disabled ZA for VL 3664
6579 11:31:13.168818 # ok 687 # SKIP Get and set data for VL 3664
6580 11:31:13.168940 # ok 688 Set VL 3680
6581 11:31:13.169055 # ok 689 # SKIP Disabled ZA for VL 3680
6582 11:31:13.169168 # ok 690 # SKIP Get and set data for VL 3680
6583 11:31:13.169280 # ok 691 Set VL 3696
6584 11:31:13.169391 # ok 692 # SKIP Disabled ZA for VL 3696
6585 11:31:13.169505 # ok 693 # SKIP Get and set data for VL 3696
6586 11:31:13.169618 # ok 694 Set VL 3712
6587 11:31:13.169818 # ok 695 # SKIP Disabled ZA for VL 3712
6588 11:31:13.170009 # ok 696 # SKIP Get and set data for VL 3712
6589 11:31:13.170177 # ok 697 Set VL 3728
6590 11:31:13.170341 # ok 698 # SKIP Disabled ZA for VL 3728
6591 11:31:13.170511 # ok 699 # SKIP Get and set data for VL 3728
6592 11:31:13.170681 # ok 700 Set VL 3744
6593 11:31:13.170893 # ok 701 # SKIP Disabled ZA for VL 3744
6594 11:31:13.171056 # ok 702 # SKIP Get and set data for VL 3744
6595 11:31:13.171210 # ok 703 Set VL 3760
6596 11:31:13.171363 # ok 704 # SKIP Disabled ZA for VL 3760
6597 11:31:13.171516 # ok 705 # SKIP Get and set data for VL 3760
6598 11:31:13.171669 # ok 706 Set VL 3776
6599 11:31:13.171821 # ok 707 # SKIP Disabled ZA for VL 3776
6600 11:31:13.171973 # ok 708 # SKIP Get and set data for VL 3776
6601 11:31:13.172125 # ok 709 Set VL 3792
6602 11:31:13.172275 # ok 710 # SKIP Disabled ZA for VL 3792
6603 11:31:13.172426 # ok 711 # SKIP Get and set data for VL 3792
6604 11:31:13.172577 # ok 712 Set VL 3808
6605 11:31:13.172728 # ok 713 # SKIP Disabled ZA for VL 3808
6606 11:31:13.172917 # ok 714 # SKIP Get and set data for VL 3808
6607 11:31:13.173075 # ok 715 Set VL 3824
6608 11:31:13.173230 # ok 716 # SKIP Disabled ZA for VL 3824
6609 11:31:13.173384 # ok 717 # SKIP Get and set data for VL 3824
6610 11:31:13.173536 # ok 718 Set VL 3840
6611 11:31:13.173697 # ok 719 # SKIP Disabled ZA for VL 3840
6612 11:31:13.173851 # ok 720 # SKIP Get and set data for VL 3840
6613 11:31:13.174007 # ok 721 Set VL 3856
6614 11:31:13.174159 # ok 722 # SKIP Disabled ZA for VL 3856
6615 11:31:13.174311 # ok 723 # SKIP Get and set data for VL 3856
6616 11:31:13.174463 # ok 724 Set VL 3872
6617 11:31:13.174614 # ok 725 # SKIP Disabled ZA for VL 3872
6618 11:31:13.174765 # ok 726 # SKIP Get and set data for VL 3872
6619 11:31:13.174915 # ok 727 Set VL 3888
6620 11:31:13.175065 # ok 728 # SKIP Disabled ZA for VL 3888
6621 11:31:13.175451 # ok 729 # SKIP Get and set data for VL 3888
6622 11:31:13.175614 # ok 730 Set VL 3904
6623 11:31:13.175766 # ok 731 # SKIP Disabled ZA for VL 3904
6624 11:31:13.175917 # ok 732 # SKIP Get and set data for VL 3904
6625 11:31:13.176068 # ok 733 Set VL 3920
6626 11:31:13.178369 # ok 734 # SKIP Disabled ZA for VL 3920
6627 11:31:13.178838 # ok 735 # SKIP Get and set data for VL 3920
6628 11:31:13.179047 # ok 736 Set VL 3936
6629 11:31:13.179214 # ok 737 # SKIP Disabled ZA for VL 3936
6630 11:31:13.179406 # ok 738 # SKIP Get and set data for VL 3936
6631 11:31:13.179576 # ok 739 Set VL 3952
6632 11:31:13.179776 # ok 740 # SKIP Disabled ZA for VL 3952
6633 11:31:13.179988 # ok 741 # SKIP Get and set data for VL 3952
6634 11:31:13.180170 # ok 742 Set VL 3968
6635 11:31:13.180304 # ok 743 # SKIP Disabled ZA for VL 3968
6636 11:31:13.180424 # ok 744 # SKIP Get and set data for VL 3968
6637 11:31:13.180548 # ok 745 Set VL 3984
6638 11:31:13.180662 # ok 746 # SKIP Disabled ZA for VL 3984
6639 11:31:13.180785 # ok 747 # SKIP Get and set data for VL 3984
6640 11:31:13.180900 # ok 748 Set VL 4000
6641 11:31:13.181012 # ok 749 # SKIP Disabled ZA for VL 4000
6642 11:31:13.181125 # ok 750 # SKIP Get and set data for VL 4000
6643 11:31:13.181238 # ok 751 Set VL 4016
6644 11:31:13.181351 # ok 752 # SKIP Disabled ZA for VL 4016
6645 11:31:13.181494 # ok 753 # SKIP Get and set data for VL 4016
6646 11:31:13.181613 # ok 754 Set VL 4032
6647 11:31:13.181748 # ok 755 # SKIP Disabled ZA for VL 4032
6648 11:31:13.181862 # ok 756 # SKIP Get and set data for VL 4032
6649 11:31:13.181976 # ok 757 Set VL 4048
6650 11:31:13.182089 # ok 758 # SKIP Disabled ZA for VL 4048
6651 11:31:13.182203 # ok 759 # SKIP Get and set data for VL 4048
6652 11:31:13.182318 # ok 760 Set VL 4064
6653 11:31:13.182432 # ok 761 # SKIP Disabled ZA for VL 4064
6654 11:31:13.182545 # ok 762 # SKIP Get and set data for VL 4064
6655 11:31:13.186140 # ok 763 Set VL 4080
6656 11:31:13.186643 # ok 764 # SKIP Disabled ZA for VL 4080
6657 11:31:13.186838 # ok 765 # SKIP Get and set data for VL 4080
6658 11:31:13.187056 # ok 766 Set VL 4096
6659 11:31:13.187264 # ok 767 # SKIP Disabled ZA for VL 4096
6660 11:31:13.187476 # ok 768 # SKIP Get and set data for VL 4096
6661 11:31:13.187702 # ok 769 Set VL 4112
6662 11:31:13.187903 # ok 770 # SKIP Disabled ZA for VL 4112
6663 11:31:13.188096 # ok 771 # SKIP Get and set data for VL 4112
6664 11:31:13.188293 # ok 772 Set VL 4128
6665 11:31:13.188460 # ok 773 # SKIP Disabled ZA for VL 4128
6666 11:31:13.188632 # ok 774 # SKIP Get and set data for VL 4128
6667 11:31:13.188800 # ok 775 Set VL 4144
6668 11:31:13.188950 # ok 776 # SKIP Disabled ZA for VL 4144
6669 11:31:13.189069 # ok 777 # SKIP Get and set data for VL 4144
6670 11:31:13.189182 # ok 778 Set VL 4160
6671 11:31:13.189298 # ok 779 # SKIP Disabled ZA for VL 4160
6672 11:31:13.189413 # ok 780 # SKIP Get and set data for VL 4160
6673 11:31:13.189524 # ok 781 Set VL 4176
6674 11:31:13.189635 # ok 782 # SKIP Disabled ZA for VL 4176
6675 11:31:13.189798 # ok 783 # SKIP Get and set data for VL 4176
6676 11:31:13.189919 # ok 784 Set VL 4192
6677 11:31:13.190031 # ok 785 # SKIP Disabled ZA for VL 4192
6678 11:31:13.190144 # ok 786 # SKIP Get and set data for VL 4192
6679 11:31:13.190258 # ok 787 Set VL 4208
6680 11:31:13.190368 # ok 788 # SKIP Disabled ZA for VL 4208
6681 11:31:13.190480 # ok 789 # SKIP Get and set data for VL 4208
6682 11:31:13.190591 # ok 790 Set VL 4224
6683 11:31:13.190702 # ok 791 # SKIP Disabled ZA for VL 4224
6684 11:31:13.190813 # ok 792 # SKIP Get and set data for VL 4224
6685 11:31:13.190924 # ok 793 Set VL 4240
6686 11:31:13.191032 # ok 794 # SKIP Disabled ZA for VL 4240
6687 11:31:13.195192 # ok 795 # SKIP Get and set data for VL 4240
6688 11:31:13.195411 # ok 796 Set VL 4256
6689 11:31:13.195607 # ok 797 # SKIP Disabled ZA for VL 4256
6690 11:31:13.196016 # ok 798 # SKIP Get and set data for VL 4256
6691 11:31:13.196208 # ok 799 Set VL 4272
6692 11:31:13.196348 # ok 800 # SKIP Disabled ZA for VL 4272
6693 11:31:13.196472 # ok 801 # SKIP Get and set data for VL 4272
6694 11:31:13.196591 # ok 802 Set VL 4288
6695 11:31:13.196708 # ok 803 # SKIP Disabled ZA for VL 4288
6696 11:31:13.196821 # ok 804 # SKIP Get and set data for VL 4288
6697 11:31:13.196932 # ok 805 Set VL 4304
6698 11:31:13.197043 # ok 806 # SKIP Disabled ZA for VL 4304
6699 11:31:13.197155 # ok 807 # SKIP Get and set data for VL 4304
6700 11:31:13.197293 # ok 808 Set VL 4320
6701 11:31:13.197409 # ok 809 # SKIP Disabled ZA for VL 4320
6702 11:31:13.197520 # ok 810 # SKIP Get and set data for VL 4320
6703 11:31:13.197631 # ok 811 Set VL 4336
6704 11:31:13.197775 # ok 812 # SKIP Disabled ZA for VL 4336
6705 11:31:13.197894 # ok 813 # SKIP Get and set data for VL 4336
6706 11:31:13.198005 # ok 814 Set VL 4352
6707 11:31:13.198137 # ok 815 # SKIP Disabled ZA for VL 4352
6708 11:31:13.204302 # ok 816 # SKIP Get and set data for VL 4352
6709 11:31:13.204728 # ok 817 Set VL 4368
6710 11:31:13.204871 # ok 818 # SKIP Disabled ZA for VL 4368
6711 11:31:13.204990 # ok 819 # SKIP Get and set data for VL 4368
6712 11:31:13.205103 # ok 820 Set VL 4384
6713 11:31:13.205216 # ok 821 # SKIP Disabled ZA for VL 4384
6714 11:31:13.207234 # ok 822 # SKIP Get and set data for VL 4384
6715 11:31:13.207425 # ok 823 Set VL 4400
6716 11:31:13.207574 # ok 824 # SKIP Disabled ZA for VL 4400
6717 11:31:13.207693 # ok 825 # SKIP Get and set data for VL 4400
6718 11:31:13.207866 # ok 826 Set VL 4416
6719 11:31:13.208035 # ok 827 # SKIP Disabled ZA for VL 4416
6720 11:31:13.208196 # ok 828 # SKIP Get and set data for VL 4416
6721 11:31:13.208354 # ok 829 Set VL 4432
6722 11:31:13.208510 # ok 830 # SKIP Disabled ZA for VL 4432
6723 11:31:13.208658 # ok 831 # SKIP Get and set data for VL 4432
6724 11:31:13.208774 # ok 832 Set VL 4448
6725 11:31:13.208885 # ok 833 # SKIP Disabled ZA for VL 4448
6726 11:31:13.209027 # ok 834 # SKIP Get and set data for VL 4448
6727 11:31:13.209143 # ok 835 Set VL 4464
6728 11:31:13.209256 # ok 836 # SKIP Disabled ZA for VL 4464
6729 11:31:13.209368 # ok 837 # SKIP Get and set data for VL 4464
6730 11:31:13.209483 # ok 838 Set VL 4480
6731 11:31:13.209596 # ok 839 # SKIP Disabled ZA for VL 4480
6732 11:31:13.209727 # ok 840 # SKIP Get and set data for VL 4480
6733 11:31:13.209840 # ok 841 Set VL 4496
6734 11:31:13.209952 # ok 842 # SKIP Disabled ZA for VL 4496
6735 11:31:13.210064 # ok 843 # SKIP Get and set data for VL 4496
6736 11:31:13.210175 # ok 844 Set VL 4512
6737 11:31:13.210288 # ok 845 # SKIP Disabled ZA for VL 4512
6738 11:31:13.210400 # ok 846 # SKIP Get and set data for VL 4512
6739 11:31:13.214824 # ok 847 Set VL 4528
6740 11:31:13.215012 # ok 848 # SKIP Disabled ZA for VL 4528
6741 11:31:13.215172 # ok 849 # SKIP Get and set data for VL 4528
6742 11:31:13.215368 # ok 850 Set VL 4544
6743 11:31:13.215532 # ok 851 # SKIP Disabled ZA for VL 4544
6744 11:31:13.215689 # ok 852 # SKIP Get and set data for VL 4544
6745 11:31:13.215862 # ok 853 Set VL 4560
6746 11:31:13.216037 # ok 854 # SKIP Disabled ZA for VL 4560
6747 11:31:13.216187 # ok 855 # SKIP Get and set data for VL 4560
6748 11:31:13.216346 # ok 856 Set VL 4576
6749 11:31:13.216548 # ok 857 # SKIP Disabled ZA for VL 4576
6750 11:31:13.216715 # ok 858 # SKIP Get and set data for VL 4576
6751 11:31:13.216840 # ok 859 Set VL 4592
6752 11:31:13.216953 # ok 860 # SKIP Disabled ZA for VL 4592
6753 11:31:13.217065 # ok 861 # SKIP Get and set data for VL 4592
6754 11:31:13.217178 # ok 862 Set VL 4608
6755 11:31:13.217290 # ok 863 # SKIP Disabled ZA for VL 4608
6756 11:31:13.217404 # ok 864 # SKIP Get and set data for VL 4608
6757 11:31:13.217517 # ok 865 Set VL 4624
6758 11:31:13.217674 # ok 866 # SKIP Disabled ZA for VL 4624
6759 11:31:13.217838 # ok 867 # SKIP Get and set data for VL 4624
6760 11:31:13.217989 # ok 868 Set VL 4640
6761 11:31:13.218146 # ok 869 # SKIP Disabled ZA for VL 4640
6762 11:31:13.218307 # ok 870 # SKIP Get and set data for VL 4640
6763 11:31:13.218465 # ok 871 Set VL 4656
6764 11:31:13.218621 # ok 872 # SKIP Disabled ZA for VL 4656
6765 11:31:13.218819 # ok 873 # SKIP Get and set data for VL 4656
6766 11:31:13.218978 # ok 874 Set VL 4672
6767 11:31:13.219111 # ok 875 # SKIP Disabled ZA for VL 4672
6768 11:31:13.219262 # ok 876 # SKIP Get and set data for VL 4672
6769 11:31:13.219418 # ok 877 Set VL 4688
6770 11:31:13.219569 # ok 878 # SKIP Disabled ZA for VL 4688
6771 11:31:13.219723 # ok 879 # SKIP Get and set data for VL 4688
6772 11:31:13.219861 # ok 880 Set VL 4704
6773 11:31:13.220011 # ok 881 # SKIP Disabled ZA for VL 4704
6774 11:31:13.220150 # ok 882 # SKIP Get and set data for VL 4704
6775 11:31:13.220305 # ok 883 Set VL 4720
6776 11:31:13.220460 # ok 884 # SKIP Disabled ZA for VL 4720
6777 11:31:13.220606 # ok 885 # SKIP Get and set data for VL 4720
6778 11:31:13.220747 # ok 886 Set VL 4736
6779 11:31:13.220864 # ok 887 # SKIP Disabled ZA for VL 4736
6780 11:31:13.220975 # ok 888 # SKIP Get and set data for VL 4736
6781 11:31:13.221086 # ok 889 Set VL 4752
6782 11:31:13.221197 # ok 890 # SKIP Disabled ZA for VL 4752
6783 11:31:13.221312 # ok 891 # SKIP Get and set data for VL 4752
6784 11:31:13.221425 # ok 892 Set VL 4768
6785 11:31:13.221563 # ok 893 # SKIP Disabled ZA for VL 4768
6786 11:31:13.221693 # ok 894 # SKIP Get and set data for VL 4768
6787 11:31:13.221808 # ok 895 Set VL 4784
6788 11:31:13.221919 # ok 896 # SKIP Disabled ZA for VL 4784
6789 11:31:13.222028 # ok 897 # SKIP Get and set data for VL 4784
6790 11:31:13.222137 # ok 898 Set VL 4800
6791 11:31:13.222246 # ok 899 # SKIP Disabled ZA for VL 4800
6792 11:31:13.222355 # ok 900 # SKIP Get and set data for VL 4800
6793 11:31:13.222676 # ok 901 Set VL 4816
6794 11:31:13.222796 # ok 902 # SKIP Disabled ZA for VL 4816
6795 11:31:13.222907 # ok 903 # SKIP Get and set data for VL 4816
6796 11:31:13.223018 # ok 904 Set VL 4832
6797 11:31:13.223128 # ok 905 # SKIP Disabled ZA for VL 4832
6798 11:31:13.223238 # ok 906 # SKIP Get and set data for VL 4832
6799 11:31:13.223349 # ok 907 Set VL 4848
6800 11:31:13.223458 # ok 908 # SKIP Disabled ZA for VL 4848
6801 11:31:13.223568 # ok 909 # SKIP Get and set data for VL 4848
6802 11:31:13.223678 # ok 910 Set VL 4864
6803 11:31:13.223787 # ok 911 # SKIP Disabled ZA for VL 4864
6804 11:31:13.223897 # ok 912 # SKIP Get and set data for VL 4864
6805 11:31:13.224007 # ok 913 Set VL 4880
6806 11:31:13.234658 # ok 914 # SKIP Disabled ZA for VL 4880
6807 11:31:13.235024 # ok 915 # SKIP Get and set data for VL 4880
6808 11:31:13.235202 # ok 916 Set VL 4896
6809 11:31:13.235351 # ok 917 # SKIP Disabled ZA for VL 4896
6810 11:31:13.235504 # ok 918 # SKIP Get and set data for VL 4896
6811 11:31:13.235688 # ok 919 Set VL 4912
6812 11:31:13.235834 # ok 920 # SKIP Disabled ZA for VL 4912
6813 11:31:13.235975 # ok 921 # SKIP Get and set data for VL 4912
6814 11:31:13.236128 # ok 922 Set VL 4928
6815 11:31:13.236279 # ok 923 # SKIP Disabled ZA for VL 4928
6816 11:31:13.236436 # ok 924 # SKIP Get and set data for VL 4928
6817 11:31:13.236572 # ok 925 Set VL 4944
6818 11:31:13.236694 # ok 926 # SKIP Disabled ZA for VL 4944
6819 11:31:13.236836 # ok 927 # SKIP Get and set data for VL 4944
6820 11:31:13.236954 # ok 928 Set VL 4960
6821 11:31:13.237067 # ok 929 # SKIP Disabled ZA for VL 4960
6822 11:31:13.237179 # ok 930 # SKIP Get and set data for VL 4960
6823 11:31:13.237293 # ok 931 Set VL 4976
6824 11:31:13.237406 # ok 932 # SKIP Disabled ZA for VL 4976
6825 11:31:13.237518 # ok 933 # SKIP Get and set data for VL 4976
6826 11:31:13.237628 # ok 934 Set VL 4992
6827 11:31:13.237757 # ok 935 # SKIP Disabled ZA for VL 4992
6828 11:31:13.237867 # ok 936 # SKIP Get and set data for VL 4992
6829 11:31:13.237976 # ok 937 Set VL 5008
6830 11:31:13.250494 # ok 938 # SKIP Disabled ZA for VL 5008
6831 11:31:13.250768 # ok 939 # SKIP Get and set data for VL 5008
6832 11:31:13.251187 # ok 940 Set VL 5024
6833 11:31:13.251291 # ok 941 # SKIP Disabled ZA for VL 5024
6834 11:31:13.251378 # ok 942 # SKIP Get and set data for VL 5024
6835 11:31:13.251463 # ok 943 Set VL 5040
6836 11:31:13.251546 # ok 944 # SKIP Disabled ZA for VL 5040
6837 11:31:13.251629 # ok 945 # SKIP Get and set data for VL 5040
6838 11:31:13.251713 # ok 946 Set VL 5056
6839 11:31:13.251838 # ok 947 # SKIP Disabled ZA for VL 5056
6840 11:31:13.251941 # ok 948 # SKIP Get and set data for VL 5056
6841 11:31:13.252029 # ok 949 Set VL 5072
6842 11:31:13.252114 # ok 950 # SKIP Disabled ZA for VL 5072
6843 11:31:13.252216 # ok 951 # SKIP Get and set data for VL 5072
6844 11:31:13.252301 # ok 952 Set VL 5088
6845 11:31:13.252390 # ok 953 # SKIP Disabled ZA for VL 5088
6846 11:31:13.252471 # ok 954 # SKIP Get and set data for VL 5088
6847 11:31:13.252555 # ok 955 Set VL 5104
6848 11:31:13.252635 # ok 956 # SKIP Disabled ZA for VL 5104
6849 11:31:13.252716 # ok 957 # SKIP Get and set data for VL 5104
6850 11:31:13.252797 # ok 958 Set VL 5120
6851 11:31:13.252877 # ok 959 # SKIP Disabled ZA for VL 5120
6852 11:31:13.252957 # ok 960 # SKIP Get and set data for VL 5120
6853 11:31:13.253038 # ok 961 Set VL 5136
6854 11:31:13.253119 # ok 962 # SKIP Disabled ZA for VL 5136
6855 11:31:13.253220 # ok 963 # SKIP Get and set data for VL 5136
6856 11:31:13.253304 # ok 964 Set VL 5152
6857 11:31:13.253385 # ok 965 # SKIP Disabled ZA for VL 5152
6858 11:31:13.253465 # ok 966 # SKIP Get and set data for VL 5152
6859 11:31:13.253546 # ok 967 Set VL 5168
6860 11:31:13.253628 # ok 968 # SKIP Disabled ZA for VL 5168
6861 11:31:13.266634 # ok 969 # SKIP Get and set data for VL 5168
6862 11:31:13.266878 # ok 970 Set VL 5184
6863 11:31:13.267048 # ok 971 # SKIP Disabled ZA for VL 5184
6864 11:31:13.267234 # ok 972 # SKIP Get and set data for VL 5184
6865 11:31:13.267387 # ok 973 Set VL 5200
6866 11:31:13.267544 # ok 974 # SKIP Disabled ZA for VL 5200
6867 11:31:13.267670 # ok 975 # SKIP Get and set data for VL 5200
6868 11:31:13.267816 # ok 976 Set VL 5216
6869 11:31:13.267957 # ok 977 # SKIP Disabled ZA for VL 5216
6870 11:31:13.268140 # ok 978 # SKIP Get and set data for VL 5216
6871 11:31:13.268302 # ok 979 Set VL 5232
6872 11:31:13.268458 # ok 980 # SKIP Disabled ZA for VL 5232
6873 11:31:13.268614 # ok 981 # SKIP Get and set data for VL 5232
6874 11:31:13.268759 # ok 982 Set VL 5248
6875 11:31:13.268876 # ok 983 # SKIP Disabled ZA for VL 5248
6876 11:31:13.268990 # ok 984 # SKIP Get and set data for VL 5248
6877 11:31:13.269102 # ok 985 Set VL 5264
6878 11:31:13.269214 # ok 986 # SKIP Disabled ZA for VL 5264
6879 11:31:13.269327 # ok 987 # SKIP Get and set data for VL 5264
6880 11:31:13.269447 # ok 988 Set VL 5280
6881 11:31:13.269639 # ok 989 # SKIP Disabled ZA for VL 5280
6882 11:31:13.269779 # ok 990 # SKIP Get and set data for VL 5280
6883 11:31:13.269891 # ok 991 Set VL 5296
6884 11:31:13.270003 # ok 992 # SKIP Disabled ZA for VL 5296
6885 11:31:13.270114 # ok 993 # SKIP Get and set data for VL 5296
6886 11:31:13.270228 # ok 994 Set VL 5312
6887 11:31:13.286264 # ok 995 # SKIP Disabled ZA for VL 5312
6888 11:31:13.286612 # ok 996 # SKIP Get and set data for VL 5312
6889 11:31:13.286717 # ok 997 Set VL 5328
6890 11:31:13.286806 # ok 998 # SKIP Disabled ZA for VL 5328
6891 11:31:13.286892 # ok 999 # SKIP Get and set data for VL 5328
6892 11:31:13.286973 # ok 1000 Set VL 5344
6893 11:31:13.287072 # ok 1001 # SKIP Disabled ZA for VL 5344
6894 11:31:13.287159 # ok 1002 # SKIP Get and set data for VL 5344
6895 11:31:13.287244 # ok 1003 Set VL 5360
6896 11:31:13.287326 # ok 1004 # SKIP Disabled ZA for VL 5360
6897 11:31:13.287428 # ok 1005 # SKIP Get and set data for VL 5360
6898 11:31:13.287512 # ok 1006 Set VL 5376
6899 11:31:13.287594 # ok 1007 # SKIP Disabled ZA for VL 5376
6900 11:31:13.287678 # ok 1008 # SKIP Get and set data for VL 5376
6901 11:31:13.287762 # ok 1009 Set VL 5392
6902 11:31:13.287861 # ok 1010 # SKIP Disabled ZA for VL 5392
6903 11:31:13.287949 # ok 1011 # SKIP Get and set data for VL 5392
6904 11:31:13.288034 # ok 1012 Set VL 5408
6905 11:31:13.288119 # ok 1013 # SKIP Disabled ZA for VL 5408
6906 11:31:13.288202 # ok 1014 # SKIP Get and set data for VL 5408
6907 11:31:13.288302 # ok 1015 Set VL 5424
6908 11:31:13.288387 # ok 1016 # SKIP Disabled ZA for VL 5424
6909 11:31:13.288475 # ok 1017 # SKIP Get and set data for VL 5424
6910 11:31:13.288558 # ok 1018 Set VL 5440
6911 11:31:13.288642 # ok 1019 # SKIP Disabled ZA for VL 5440
6912 11:31:13.288741 # ok 1020 # SKIP Get and set data for VL 5440
6913 11:31:13.288822 # ok 1021 Set VL 5456
6914 11:31:13.288901 # ok 1022 # SKIP Disabled ZA for VL 5456
6915 11:31:13.288983 # ok 1023 # SKIP Get and set data for VL 5456
6916 11:31:13.289065 # ok 1024 Set VL 5472
6917 11:31:13.289147 # ok 1025 # SKIP Disabled ZA for VL 5472
6918 11:31:13.303529 # ok 1026 # SKIP Get and set data for VL 5472
6919 11:31:13.303753 # ok 1027 Set VL 5488
6920 11:31:13.303959 # ok 1028 # SKIP Disabled ZA for VL 5488
6921 11:31:13.304412 # ok 1029 # SKIP Get and set data for VL 5488
6922 11:31:13.304613 # ok 1030 Set VL 5504
6923 11:31:13.304756 # ok 1031 # SKIP Disabled ZA for VL 5504
6924 11:31:13.304875 # ok 1032 # SKIP Get and set data for VL 5504
6925 11:31:13.304990 # ok 1033 Set VL 5520
6926 11:31:13.305103 # ok 1034 # SKIP Disabled ZA for VL 5520
6927 11:31:13.305217 # ok 1035 # SKIP Get and set data for VL 5520
6928 11:31:13.305337 # ok 1036 Set VL 5536
6929 11:31:13.305491 # ok 1037 # SKIP Disabled ZA for VL 5536
6930 11:31:13.305678 # ok 1038 # SKIP Get and set data for VL 5536
6931 11:31:13.305831 # ok 1039 Set VL 5552
6932 11:31:13.305964 # ok 1040 # SKIP Disabled ZA for VL 5552
6933 11:31:13.306124 # ok 1041 # SKIP Get and set data for VL 5552
6934 11:31:13.306281 # ok 1042 Set VL 5568
6935 11:31:13.306443 # ok 1043 # SKIP Disabled ZA for VL 5568
6936 11:31:13.306564 # ok 1044 # SKIP Get and set data for VL 5568
6937 11:31:13.306678 # ok 1045 Set VL 5584
6938 11:31:13.306791 # ok 1046 # SKIP Disabled ZA for VL 5584
6939 11:31:13.306903 # ok 1047 # SKIP Get and set data for VL 5584
6940 11:31:13.307015 # ok 1048 Set VL 5600
6941 11:31:13.307126 # ok 1049 # SKIP Disabled ZA for VL 5600
6942 11:31:13.307239 # ok 1050 # SKIP Get and set data for VL 5600
6943 11:31:13.307351 # ok 1051 Set VL 5616
6944 11:31:13.307463 # ok 1052 # SKIP Disabled ZA for VL 5616
6945 11:31:13.308062 # ok 1053 # SKIP Get and set data for VL 5616
6946 11:31:13.308256 # ok 1054 Set VL 5632
6947 11:31:13.308427 # ok 1055 # SKIP Disabled ZA for VL 5632
6948 11:31:13.308629 # ok 1056 # SKIP Get and set data for VL 5632
6949 11:31:13.308774 # ok 1057 Set VL 5648
6950 11:31:13.308893 # ok 1058 # SKIP Disabled ZA for VL 5648
6951 11:31:13.309009 # ok 1059 # SKIP Get and set data for VL 5648
6952 11:31:13.309124 # ok 1060 Set VL 5664
6953 11:31:13.309240 # ok 1061 # SKIP Disabled ZA for VL 5664
6954 11:31:13.309377 # ok 1062 # SKIP Get and set data for VL 5664
6955 11:31:13.309526 # ok 1063 Set VL 5680
6956 11:31:13.309645 # ok 1064 # SKIP Disabled ZA for VL 5680
6957 11:31:13.309800 # ok 1065 # SKIP Get and set data for VL 5680
6958 11:31:13.319459 # ok 1066 Set VL 5696
6959 11:31:13.319776 # ok 1067 # SKIP Disabled ZA for VL 5696
6960 11:31:13.320181 # ok 1068 # SKIP Get and set data for VL 5696
6961 11:31:13.320291 # ok 1069 Set VL 5712
6962 11:31:13.320384 # ok 1070 # SKIP Disabled ZA for VL 5712
6963 11:31:13.320472 # ok 1071 # SKIP Get and set data for VL 5712
6964 11:31:13.320559 # ok 1072 Set VL 5728
6965 11:31:13.320648 # ok 1073 # SKIP Disabled ZA for VL 5728
6966 11:31:13.320735 # ok 1074 # SKIP Get and set data for VL 5728
6967 11:31:13.320820 # ok 1075 Set VL 5744
6968 11:31:13.320904 # ok 1076 # SKIP Disabled ZA for VL 5744
6969 11:31:13.320987 # ok 1077 # SKIP Get and set data for VL 5744
6970 11:31:13.321088 # ok 1078 Set VL 5760
6971 11:31:13.321172 # ok 1079 # SKIP Disabled ZA for VL 5760
6972 11:31:13.321254 # ok 1080 # SKIP Get and set data for VL 5760
6973 11:31:13.321334 # ok 1081 Set VL 5776
6974 11:31:13.321417 # ok 1082 # SKIP Disabled ZA for VL 5776
6975 11:31:13.321501 # ok 1083 # SKIP Get and set data for VL 5776
6976 11:31:13.321584 # ok 1084 Set VL 5792
6977 11:31:13.321689 # ok 1085 # SKIP Disabled ZA for VL 5792
6978 11:31:13.321769 # ok 1086 # SKIP Get and set data for VL 5792
6979 11:31:13.321842 # ok 1087 Set VL 5808
6980 11:31:13.321916 # ok 1088 # SKIP Disabled ZA for VL 5808
6981 11:31:13.321988 # ok 1089 # SKIP Get and set data for VL 5808
6982 11:31:13.322059 # ok 1090 Set VL 5824
6983 11:31:13.328361 # ok 1091 # SKIP Disabled ZA for VL 5824
6984 11:31:13.328806 # ok 1092 # SKIP Get and set data for VL 5824
6985 11:31:13.328898 # ok 1093 Set VL 5840
6986 11:31:13.328967 # ok 1094 # SKIP Disabled ZA for VL 5840
6987 11:31:13.329029 # ok 1095 # SKIP Get and set data for VL 5840
6988 11:31:13.335428 # ok 1096 Set VL 5856
6989 11:31:13.335678 # ok 1097 # SKIP Disabled ZA for VL 5856
6990 11:31:13.335966 # ok 1098 # SKIP Get and set data for VL 5856
6991 11:31:13.336072 # ok 1099 Set VL 5872
6992 11:31:13.336161 # ok 1100 # SKIP Disabled ZA for VL 5872
6993 11:31:13.336247 # ok 1101 # SKIP Get and set data for VL 5872
6994 11:31:13.336332 # ok 1102 Set VL 5888
6995 11:31:13.336416 # ok 1103 # SKIP Disabled ZA for VL 5888
6996 11:31:13.336501 # ok 1104 # SKIP Get and set data for VL 5888
6997 11:31:13.336605 # ok 1105 Set VL 5904
6998 11:31:13.336689 # ok 1106 # SKIP Disabled ZA for VL 5904
6999 11:31:13.336769 # ok 1107 # SKIP Get and set data for VL 5904
7000 11:31:13.336843 # ok 1108 Set VL 5920
7001 11:31:13.336930 # ok 1109 # SKIP Disabled ZA for VL 5920
7002 11:31:13.344259 # ok 1110 # SKIP Get and set data for VL 5920
7003 11:31:13.344708 # ok 1111 Set VL 5936
7004 11:31:13.344802 # ok 1112 # SKIP Disabled ZA for VL 5936
7005 11:31:13.344878 # ok 1113 # SKIP Get and set data for VL 5936
7006 11:31:13.344951 # ok 1114 Set VL 5952
7007 11:31:13.345022 # ok 1115 # SKIP Disabled ZA for VL 5952
7008 11:31:13.346386 # ok 1116 # SKIP Get and set data for VL 5952
7009 11:31:13.346725 # ok 1117 Set VL 5968
7010 11:31:13.346917 # ok 1118 # SKIP Disabled ZA for VL 5968
7011 11:31:13.347078 # ok 1119 # SKIP Get and set data for VL 5968
7012 11:31:13.347224 # ok 1120 Set VL 5984
7013 11:31:13.347408 # ok 1121 # SKIP Disabled ZA for VL 5984
7014 11:31:13.347551 # ok 1122 # SKIP Get and set data for VL 5984
7015 11:31:13.347704 # ok 1123 Set VL 6000
7016 11:31:13.347869 # ok 1124 # SKIP Disabled ZA for VL 6000
7017 11:31:13.348260 # ok 1125 # SKIP Get and set data for VL 6000
7018 11:31:13.348447 # ok 1126 Set VL 6016
7019 11:31:13.348681 # ok 1127 # SKIP Disabled ZA for VL 6016
7020 11:31:13.348839 # ok 1128 # SKIP Get and set data for VL 6016
7021 11:31:13.348958 # ok 1129 Set VL 6032
7022 11:31:13.349073 # ok 1130 # SKIP Disabled ZA for VL 6032
7023 11:31:13.349196 # ok 1131 # SKIP Get and set data for VL 6032
7024 11:31:13.349349 # ok 1132 Set VL 6048
7025 11:31:13.349465 # ok 1133 # SKIP Disabled ZA for VL 6048
7026 11:31:13.349582 # ok 1134 # SKIP Get and set data for VL 6048
7027 11:31:13.349742 # ok 1135 Set VL 6064
7028 11:31:13.349939 # ok 1136 # SKIP Disabled ZA for VL 6064
7029 11:31:13.350122 # ok 1137 # SKIP Get and set data for VL 6064
7030 11:31:13.350263 # ok 1138 Set VL 6080
7031 11:31:13.354572 # ok 1139 # SKIP Disabled ZA for VL 6080
7032 11:31:13.354848 # ok 1140 # SKIP Get and set data for VL 6080
7033 11:31:13.355039 # ok 1141 Set VL 6096
7034 11:31:13.355246 # ok 1142 # SKIP Disabled ZA for VL 6096
7035 11:31:13.355674 # ok 1143 # SKIP Get and set data for VL 6096
7036 11:31:13.355845 # ok 1144 Set VL 6112
7037 11:31:13.355985 # ok 1145 # SKIP Disabled ZA for VL 6112
7038 11:31:13.356112 # ok 1146 # SKIP Get and set data for VL 6112
7039 11:31:13.356279 # ok 1147 Set VL 6128
7040 11:31:13.356444 # ok 1148 # SKIP Disabled ZA for VL 6128
7041 11:31:13.356598 # ok 1149 # SKIP Get and set data for VL 6128
7042 11:31:13.356728 # ok 1150 Set VL 6144
7043 11:31:13.356850 # ok 1151 # SKIP Disabled ZA for VL 6144
7044 11:31:13.356966 # ok 1152 # SKIP Get and set data for VL 6144
7045 11:31:13.357082 # ok 1153 Set VL 6160
7046 11:31:13.357196 # ok 1154 # SKIP Disabled ZA for VL 6160
7047 11:31:13.357343 # ok 1155 # SKIP Get and set data for VL 6160
7048 11:31:13.357467 # ok 1156 Set VL 6176
7049 11:31:13.357585 # ok 1157 # SKIP Disabled ZA for VL 6176
7050 11:31:13.357720 # ok 1158 # SKIP Get and set data for VL 6176
7051 11:31:13.357837 # ok 1159 Set VL 6192
7052 11:31:13.357950 # ok 1160 # SKIP Disabled ZA for VL 6192
7053 11:31:13.358065 # ok 1161 # SKIP Get and set data for VL 6192
7054 11:31:13.358180 # ok 1162 Set VL 6208
7055 11:31:13.358294 # ok 1163 # SKIP Disabled ZA for VL 6208
7056 11:31:13.358410 # ok 1164 # SKIP Get and set data for VL 6208
7057 11:31:13.358526 # ok 1165 Set VL 6224
7058 11:31:13.358643 # ok 1166 # SKIP Disabled ZA for VL 6224
7059 11:31:13.358758 # ok 1167 # SKIP Get and set data for VL 6224
7060 11:31:13.358874 # ok 1168 Set VL 6240
7061 11:31:13.362450 # ok 1169 # SKIP Disabled ZA for VL 6240
7062 11:31:13.362931 # ok 1170 # SKIP Get and set data for VL 6240
7063 11:31:13.363129 # ok 1171 Set VL 6256
7064 11:31:13.363334 # ok 1172 # SKIP Disabled ZA for VL 6256
7065 11:31:13.363536 # ok 1173 # SKIP Get and set data for VL 6256
7066 11:31:13.363722 # ok 1174 Set VL 6272
7067 11:31:13.363921 # ok 1175 # SKIP Disabled ZA for VL 6272
7068 11:31:13.364135 # ok 1176 # SKIP Get and set data for VL 6272
7069 11:31:13.364314 # ok 1177 Set VL 6288
7070 11:31:13.364495 # ok 1178 # SKIP Disabled ZA for VL 6288
7071 11:31:13.364655 # ok 1179 # SKIP Get and set data for VL 6288
7072 11:31:13.364775 # ok 1180 Set VL 6304
7073 11:31:13.364888 # ok 1181 # SKIP Disabled ZA for VL 6304
7074 11:31:13.365001 # ok 1182 # SKIP Get and set data for VL 6304
7075 11:31:13.365115 # ok 1183 Set VL 6320
7076 11:31:13.365227 # ok 1184 # SKIP Disabled ZA for VL 6320
7077 11:31:13.365339 # ok 1185 # SKIP Get and set data for VL 6320
7078 11:31:13.365450 # ok 1186 Set VL 6336
7079 11:31:13.365561 # ok 1187 # SKIP Disabled ZA for VL 6336
7080 11:31:13.365706 # ok 1188 # SKIP Get and set data for VL 6336
7081 11:31:13.365910 # ok 1189 Set VL 6352
7082 11:31:13.366093 # ok 1190 # SKIP Disabled ZA for VL 6352
7083 11:31:13.366315 # ok 1191 # SKIP Get and set data for VL 6352
7084 11:31:13.366457 # ok 1192 Set VL 6368
7085 11:31:13.366598 # ok 1193 # SKIP Disabled ZA for VL 6368
7086 11:31:13.366746 # ok 1194 # SKIP Get and set data for VL 6368
7087 11:31:13.366889 # ok 1195 Set VL 6384
7088 11:31:13.367031 # ok 1196 # SKIP Disabled ZA for VL 6384
7089 11:31:13.370892 # ok 1197 # SKIP Get and set data for VL 6384
7090 11:31:13.371160 # ok 1198 Set VL 6400
7091 11:31:13.371557 # ok 1199 # SKIP Disabled ZA for VL 6400
7092 11:31:13.371746 # ok 1200 # SKIP Get and set data for VL 6400
7093 11:31:13.371916 # ok 1201 Set VL 6416
7094 11:31:13.372077 # ok 1202 # SKIP Disabled ZA for VL 6416
7095 11:31:13.372238 # ok 1203 # SKIP Get and set data for VL 6416
7096 11:31:13.372454 # ok 1204 Set VL 6432
7097 11:31:13.372653 # ok 1205 # SKIP Disabled ZA for VL 6432
7098 11:31:13.372819 # ok 1206 # SKIP Get and set data for VL 6432
7099 11:31:13.372942 # ok 1207 Set VL 6448
7100 11:31:13.373090 # ok 1208 # SKIP Disabled ZA for VL 6448
7101 11:31:13.373213 # ok 1209 # SKIP Get and set data for VL 6448
7102 11:31:13.373330 # ok 1210 Set VL 6464
7103 11:31:13.373445 # ok 1211 # SKIP Disabled ZA for VL 6464
7104 11:31:13.373571 # ok 1212 # SKIP Get and set data for VL 6464
7105 11:31:13.373764 # ok 1213 Set VL 6480
7106 11:31:13.373945 # ok 1214 # SKIP Disabled ZA for VL 6480
7107 11:31:13.374137 # ok 1215 # SKIP Get and set data for VL 6480
7108 11:31:13.374324 # ok 1216 Set VL 6496
7109 11:31:13.374492 # ok 1217 # SKIP Disabled ZA for VL 6496
7110 11:31:13.374696 # ok 1218 # SKIP Get and set data for VL 6496
7111 11:31:13.374906 # ok 1219 Set VL 6512
7112 11:31:13.375094 # ok 1220 # SKIP Disabled ZA for VL 6512
7113 11:31:13.375309 # ok 1221 # SKIP Get and set data for VL 6512
7114 11:31:13.375471 # ok 1222 Set VL 6528
7115 11:31:13.375625 # ok 1223 # SKIP Disabled ZA for VL 6528
7116 11:31:13.375774 # ok 1224 # SKIP Get and set data for VL 6528
7117 11:31:13.375922 # ok 1225 Set VL 6544
7118 11:31:13.376071 # ok 1226 # SKIP Disabled ZA for VL 6544
7119 11:31:13.376230 # ok 1227 # SKIP Get and set data for VL 6544
7120 11:31:13.376389 # ok 1228 Set VL 6560
7121 11:31:13.376552 # ok 1229 # SKIP Disabled ZA for VL 6560
7122 11:31:13.376711 # ok 1230 # SKIP Get and set data for VL 6560
7123 11:31:13.376865 # ok 1231 Set VL 6576
7124 11:31:13.376983 # ok 1232 # SKIP Disabled ZA for VL 6576
7125 11:31:13.377095 # ok 1233 # SKIP Get and set data for VL 6576
7126 11:31:13.377207 # ok 1234 Set VL 6592
7127 11:31:13.377317 # ok 1235 # SKIP Disabled ZA for VL 6592
7128 11:31:13.377428 # ok 1236 # SKIP Get and set data for VL 6592
7129 11:31:13.377540 # ok 1237 Set VL 6608
7130 11:31:13.377695 # ok 1238 # SKIP Disabled ZA for VL 6608
7131 11:31:13.377906 # ok 1239 # SKIP Get and set data for VL 6608
7132 11:31:13.378088 # ok 1240 Set VL 6624
7133 11:31:13.378277 # ok 1241 # SKIP Disabled ZA for VL 6624
7134 11:31:13.378502 # ok 1242 # SKIP Get and set data for VL 6624
7135 11:31:13.378695 # ok 1243 Set VL 6640
7136 11:31:13.378838 # ok 1244 # SKIP Disabled ZA for VL 6640
7137 11:31:13.378979 # ok 1245 # SKIP Get and set data for VL 6640
7138 11:31:13.379119 # ok 1246 Set VL 6656
7139 11:31:13.379260 # ok 1247 # SKIP Disabled ZA for VL 6656
7140 11:31:13.379399 # ok 1248 # SKIP Get and set data for VL 6656
7141 11:31:13.379540 # ok 1249 Set VL 6672
7142 11:31:13.379679 # ok 1250 # SKIP Disabled ZA for VL 6672
7143 11:31:13.380043 # ok 1251 # SKIP Get and set data for VL 6672
7144 11:31:13.380180 # ok 1252 Set VL 6688
7145 11:31:13.380324 # ok 1253 # SKIP Disabled ZA for VL 6688
7146 11:31:13.380466 # ok 1254 # SKIP Get and set data for VL 6688
7147 11:31:13.380610 # ok 1255 Set VL 6704
7148 11:31:13.380749 # ok 1256 # SKIP Disabled ZA for VL 6704
7149 11:31:13.380888 # ok 1257 # SKIP Get and set data for VL 6704
7150 11:31:13.386134 # ok 1258 Set VL 6720
7151 11:31:13.386693 # ok 1259 # SKIP Disabled ZA for VL 6720
7152 11:31:13.386893 # ok 1260 # SKIP Get and set data for VL 6720
7153 11:31:13.387038 # ok 1261 Set VL 6736
7154 11:31:13.387210 # ok 1262 # SKIP Disabled ZA for VL 6736
7155 11:31:13.387378 # ok 1263 # SKIP Get and set data for VL 6736
7156 11:31:13.387519 # ok 1264 Set VL 6752
7157 11:31:13.387657 # ok 1265 # SKIP Disabled ZA for VL 6752
7158 11:31:13.387806 # ok 1266 # SKIP Get and set data for VL 6752
7159 11:31:13.387930 # ok 1267 Set VL 6768
7160 11:31:13.388048 # ok 1268 # SKIP Disabled ZA for VL 6768
7161 11:31:13.388162 # ok 1269 # SKIP Get and set data for VL 6768
7162 11:31:13.388286 # ok 1270 Set VL 6784
7163 11:31:13.388400 # ok 1271 # SKIP Disabled ZA for VL 6784
7164 11:31:13.388515 # ok 1272 # SKIP Get and set data for VL 6784
7165 11:31:13.388655 # ok 1273 Set VL 6800
7166 11:31:13.388805 # ok 1274 # SKIP Disabled ZA for VL 6800
7167 11:31:13.388927 # ok 1275 # SKIP Get and set data for VL 6800
7168 11:31:13.389043 # ok 1276 Set VL 6816
7169 11:31:13.389156 # ok 1277 # SKIP Disabled ZA for VL 6816
7170 11:31:13.389298 # ok 1278 # SKIP Get and set data for VL 6816
7171 11:31:13.391156 # ok 1279 Set VL 6832
7172 11:31:13.391274 # ok 1280 # SKIP Disabled ZA for VL 6832
7173 11:31:13.391379 # ok 1281 # SKIP Get and set data for VL 6832
7174 11:31:13.391470 # ok 1282 Set VL 6848
7175 11:31:13.391555 # ok 1283 # SKIP Disabled ZA for VL 6848
7176 11:31:13.391654 # ok 1284 # SKIP Get and set data for VL 6848
7177 11:31:13.391744 # ok 1285 Set VL 6864
7178 11:31:13.391841 # ok 1286 # SKIP Disabled ZA for VL 6864
7179 11:31:13.391939 # ok 1287 # SKIP Get and set data for VL 6864
7180 11:31:13.392038 # ok 1288 Set VL 6880
7181 11:31:13.392123 # ok 1289 # SKIP Disabled ZA for VL 6880
7182 11:31:13.392222 # ok 1290 # SKIP Get and set data for VL 6880
7183 11:31:13.392329 # ok 1291 Set VL 6896
7184 11:31:13.392427 # ok 1292 # SKIP Disabled ZA for VL 6896
7185 11:31:13.392760 # ok 1293 # SKIP Get and set data for VL 6896
7186 11:31:13.392936 # ok 1294 Set VL 6912
7187 11:31:13.393092 # ok 1295 # SKIP Disabled ZA for VL 6912
7188 11:31:13.399552 # ok 1296 # SKIP Get and set data for VL 6912
7189 11:31:13.400061 # ok 1297 Set VL 6928
7190 11:31:13.400250 # ok 1298 # SKIP Disabled ZA for VL 6928
7191 11:31:13.400427 # ok 1299 # SKIP Get and set data for VL 6928
7192 11:31:13.400574 # ok 1300 Set VL 6944
7193 11:31:13.400755 # ok 1301 # SKIP Disabled ZA for VL 6944
7194 11:31:13.400927 # ok 1302 # SKIP Get and set data for VL 6944
7195 11:31:13.401072 # ok 1303 Set VL 6960
7196 11:31:13.401250 # ok 1304 # SKIP Disabled ZA for VL 6960
7197 11:31:13.401387 # ok 1305 # SKIP Get and set data for VL 6960
7198 11:31:13.401531 # ok 1306 Set VL 6976
7199 11:31:13.401688 # ok 1307 # SKIP Disabled ZA for VL 6976
7200 11:31:13.401833 # ok 1308 # SKIP Get and set data for VL 6976
7201 11:31:13.401972 # ok 1309 Set VL 6992
7202 11:31:13.402111 # ok 1310 # SKIP Disabled ZA for VL 6992
7203 11:31:13.402270 # ok 1311 # SKIP Get and set data for VL 6992
7204 11:31:13.402480 # ok 1312 Set VL 7008
7205 11:31:13.402679 # ok 1313 # SKIP Disabled ZA for VL 7008
7206 11:31:13.402928 # ok 1314 # SKIP Get and set data for VL 7008
7207 11:31:13.403088 # ok 1315 Set VL 7024
7208 11:31:13.403217 # ok 1316 # SKIP Disabled ZA for VL 7024
7209 11:31:13.403342 # ok 1317 # SKIP Get and set data for VL 7024
7210 11:31:13.403470 # ok 1318 Set VL 7040
7211 11:31:13.403595 # ok 1319 # SKIP Disabled ZA for VL 7040
7212 11:31:13.403724 # ok 1320 # SKIP Get and set data for VL 7040
7213 11:31:13.403855 # ok 1321 Set VL 7056
7214 11:31:13.404106 # ok 1322 # SKIP Disabled ZA for VL 7056
7215 11:31:13.404283 # ok 1323 # SKIP Get and set data for VL 7056
7216 11:31:13.404474 # ok 1324 Set VL 7072
7217 11:31:13.404646 # ok 1325 # SKIP Disabled ZA for VL 7072
7218 11:31:13.404793 # ok 1326 # SKIP Get and set data for VL 7072
7219 11:31:13.404935 # ok 1327 Set VL 7088
7220 11:31:13.405073 # ok 1328 # SKIP Disabled ZA for VL 7088
7221 11:31:13.405212 # ok 1329 # SKIP Get and set data for VL 7088
7222 11:31:13.405353 # ok 1330 Set VL 7104
7223 11:31:13.405492 # ok 1331 # SKIP Disabled ZA for VL 7104
7224 11:31:13.405633 # ok 1332 # SKIP Get and set data for VL 7104
7225 11:31:13.405785 # ok 1333 Set VL 7120
7226 11:31:13.405925 # ok 1334 # SKIP Disabled ZA for VL 7120
7227 11:31:13.406065 # ok 1335 # SKIP Get and set data for VL 7120
7228 11:31:13.406247 # ok 1336 Set VL 7136
7229 11:31:13.406383 # ok 1337 # SKIP Disabled ZA for VL 7136
7230 11:31:13.406525 # ok 1338 # SKIP Get and set data for VL 7136
7231 11:31:13.406666 # ok 1339 Set VL 7152
7232 11:31:13.406805 # ok 1340 # SKIP Disabled ZA for VL 7152
7233 11:31:13.406944 # ok 1341 # SKIP Get and set data for VL 7152
7234 11:31:13.407085 # ok 1342 Set VL 7168
7235 11:31:13.410512 # ok 1343 # SKIP Disabled ZA for VL 7168
7236 11:31:13.410749 # ok 1344 # SKIP Get and set data for VL 7168
7237 11:31:13.410927 # ok 1345 Set VL 7184
7238 11:31:13.411109 # ok 1346 # SKIP Disabled ZA for VL 7184
7239 11:31:13.411246 # ok 1347 # SKIP Get and set data for VL 7184
7240 11:31:13.411387 # ok 1348 Set VL 7200
7241 11:31:13.411527 # ok 1349 # SKIP Disabled ZA for VL 7200
7242 11:31:13.411679 # ok 1350 # SKIP Get and set data for VL 7200
7243 11:31:13.411821 # ok 1351 Set VL 7216
7244 11:31:13.411980 # ok 1352 # SKIP Disabled ZA for VL 7216
7245 11:31:13.412207 # ok 1353 # SKIP Get and set data for VL 7216
7246 11:31:13.412375 # ok 1354 Set VL 7232
7247 11:31:13.412541 # ok 1355 # SKIP Disabled ZA for VL 7232
7248 11:31:13.412732 # ok 1356 # SKIP Get and set data for VL 7232
7249 11:31:13.412890 # ok 1357 Set VL 7248
7250 11:31:13.413011 # ok 1358 # SKIP Disabled ZA for VL 7248
7251 11:31:13.413126 # ok 1359 # SKIP Get and set data for VL 7248
7252 11:31:13.413242 # ok 1360 Set VL 7264
7253 11:31:13.413356 # ok 1361 # SKIP Disabled ZA for VL 7264
7254 11:31:13.413472 # ok 1362 # SKIP Get and set data for VL 7264
7255 11:31:13.413587 # ok 1363 Set VL 7280
7256 11:31:13.413717 # ok 1364 # SKIP Disabled ZA for VL 7280
7257 11:31:13.413833 # ok 1365 # SKIP Get and set data for VL 7280
7258 11:31:13.413947 # ok 1366 Set VL 7296
7259 11:31:13.414061 # ok 1367 # SKIP Disabled ZA for VL 7296
7260 11:31:13.414207 # ok 1368 # SKIP Get and set data for VL 7296
7261 11:31:13.414330 # ok 1369 Set VL 7312
7262 11:31:13.414447 # ok 1370 # SKIP Disabled ZA for VL 7312
7263 11:31:13.414563 # ok 1371 # SKIP Get and set data for VL 7312
7264 11:31:13.414679 # ok 1372 Set VL 7328
7265 11:31:13.414795 # ok 1373 # SKIP Disabled ZA for VL 7328
7266 11:31:13.418097 # ok 1374 # SKIP Get and set data for VL 7328
7267 11:31:13.418286 # ok 1375 Set VL 7344
7268 11:31:13.418468 # ok 1376 # SKIP Disabled ZA for VL 7344
7269 11:31:13.418683 # ok 1377 # SKIP Get and set data for VL 7344
7270 11:31:13.418871 # ok 1378 Set VL 7360
7271 11:31:13.419008 # ok 1379 # SKIP Disabled ZA for VL 7360
7272 11:31:13.419191 # ok 1380 # SKIP Get and set data for VL 7360
7273 11:31:13.419383 # ok 1381 Set VL 7376
7274 11:31:13.419554 # ok 1382 # SKIP Disabled ZA for VL 7376
7275 11:31:13.419756 # ok 1383 # SKIP Get and set data for VL 7376
7276 11:31:13.419947 # ok 1384 Set VL 7392
7277 11:31:13.420127 # ok 1385 # SKIP Disabled ZA for VL 7392
7278 11:31:13.420281 # ok 1386 # SKIP Get and set data for VL 7392
7279 11:31:13.420419 # ok 1387 Set VL 7408
7280 11:31:13.420571 # ok 1388 # SKIP Disabled ZA for VL 7408
7281 11:31:13.420722 # ok 1389 # SKIP Get and set data for VL 7408
7282 11:31:13.420839 # ok 1390 Set VL 7424
7283 11:31:13.420949 # ok 1391 # SKIP Disabled ZA for VL 7424
7284 11:31:13.421057 # ok 1392 # SKIP Get and set data for VL 7424
7285 11:31:13.421167 # ok 1393 Set VL 7440
7286 11:31:13.421276 # ok 1394 # SKIP Disabled ZA for VL 7440
7287 11:31:13.421384 # ok 1395 # SKIP Get and set data for VL 7440
7288 11:31:13.421494 # ok 1396 Set VL 7456
7289 11:31:13.421630 # ok 1397 # SKIP Disabled ZA for VL 7456
7290 11:31:13.421872 # ok 1398 # SKIP Get and set data for VL 7456
7291 11:31:13.422066 # ok 1399 Set VL 7472
7292 11:31:13.422247 # ok 1400 # SKIP Disabled ZA for VL 7472
7293 11:31:13.422396 # ok 1401 # SKIP Get and set data for VL 7472
7294 11:31:13.422537 # ok 1402 Set VL 7488
7295 11:31:13.422678 # ok 1403 # SKIP Disabled ZA for VL 7488
7296 11:31:13.422817 # ok 1404 # SKIP Get and set data for VL 7488
7297 11:31:13.422957 # ok 1405 Set VL 7504
7298 11:31:13.424555 # ok 1406 # SKIP Disabled ZA for VL 7504
7299 11:31:13.424975 # ok 1407 # SKIP Get and set data for VL 7504
7300 11:31:13.425129 # ok 1408 Set VL 7520
7301 11:31:13.425701 # ok 1409 # SKIP Disabled ZA for VL 7520
7302 11:31:13.425892 # ok 1410 # SKIP Get and set data for VL 7520
7303 11:31:13.426059 # ok 1411 Set VL 7536
7304 11:31:13.426246 # ok 1412 # SKIP Disabled ZA for VL 7536
7305 11:31:13.426385 # ok 1413 # SKIP Get and set data for VL 7536
7306 11:31:13.426578 # ok 1414 Set VL 7552
7307 11:31:13.426800 # ok 1415 # SKIP Disabled ZA for VL 7552
7308 11:31:13.426991 # ok 1416 # SKIP Get and set data for VL 7552
7309 11:31:13.427223 # ok 1417 Set VL 7568
7310 11:31:13.427439 # ok 1418 # SKIP Disabled ZA for VL 7568
7311 11:31:13.427654 # ok 1419 # SKIP Get and set data for VL 7568
7312 11:31:13.427850 # ok 1420 Set VL 7584
7313 11:31:13.428015 # ok 1421 # SKIP Disabled ZA for VL 7584
7314 11:31:13.428174 # ok 1422 # SKIP Get and set data for VL 7584
7315 11:31:13.428335 # ok 1423 Set VL 7600
7316 11:31:13.428631 # ok 1424 # SKIP Disabled ZA for VL 7600
7317 11:31:13.428852 # ok 1425 # SKIP Get and set data for VL 7600
7318 11:31:13.429001 # ok 1426 Set VL 7616
7319 11:31:13.429163 # ok 1427 # SKIP Disabled ZA for VL 7616
7320 11:31:13.429288 # ok 1428 # SKIP Get and set data for VL 7616
7321 11:31:13.429404 # ok 1429 Set VL 7632
7322 11:31:13.429519 # ok 1430 # SKIP Disabled ZA for VL 7632
7323 11:31:13.429634 # ok 1431 # SKIP Get and set data for VL 7632
7324 11:31:13.429765 # ok 1432 Set VL 7648
7325 11:31:13.429877 # ok 1433 # SKIP Disabled ZA for VL 7648
7326 11:31:13.429989 # ok 1434 # SKIP Get and set data for VL 7648
7327 11:31:13.430101 # ok 1435 Set VL 7664
7328 11:31:13.430212 # ok 1436 # SKIP Disabled ZA for VL 7664
7329 11:31:13.430322 # ok 1437 # SKIP Get and set data for VL 7664
7330 11:31:13.430433 # ok 1438 Set VL 7680
7331 11:31:13.430544 # ok 1439 # SKIP Disabled ZA for VL 7680
7332 11:31:13.430656 # ok 1440 # SKIP Get and set data for VL 7680
7333 11:31:13.430767 # ok 1441 Set VL 7696
7334 11:31:13.430878 # ok 1442 # SKIP Disabled ZA for VL 7696
7335 11:31:13.430989 # ok 1443 # SKIP Get and set data for VL 7696
7336 11:31:13.431100 # ok 1444 Set VL 7712
7337 11:31:13.436819 # ok 1445 # SKIP Disabled ZA for VL 7712
7338 11:31:13.437612 # ok 1446 # SKIP Get and set data for VL 7712
7339 11:31:13.438036 # ok 1447 Set VL 7728
7340 11:31:13.438142 # ok 1448 # SKIP Disabled ZA for VL 7728
7341 11:31:13.438231 # ok 1449 # SKIP Get and set data for VL 7728
7342 11:31:13.438316 # ok 1450 Set VL 7744
7343 11:31:13.438415 # ok 1451 # SKIP Disabled ZA for VL 7744
7344 11:31:13.438501 # ok 1452 # SKIP Get and set data for VL 7744
7345 11:31:13.438584 # ok 1453 Set VL 7760
7346 11:31:13.438681 # ok 1454 # SKIP Disabled ZA for VL 7760
7347 11:31:13.438770 # ok 1455 # SKIP Get and set data for VL 7760
7348 11:31:13.438855 # ok 1456 Set VL 7776
7349 11:31:13.438952 # ok 1457 # SKIP Disabled ZA for VL 7776
7350 11:31:13.439049 # ok 1458 # SKIP Get and set data for VL 7776
7351 11:31:13.439132 # ok 1459 Set VL 7792
7352 11:31:13.439227 # ok 1460 # SKIP Disabled ZA for VL 7792
7353 11:31:13.439327 # ok 1461 # SKIP Get and set data for VL 7792
7354 11:31:13.439412 # ok 1462 Set VL 7808
7355 11:31:13.439506 # ok 1463 # SKIP Disabled ZA for VL 7808
7356 11:31:13.439606 # ok 1464 # SKIP Get and set data for VL 7808
7357 11:31:13.439703 # ok 1465 Set VL 7824
7358 11:31:13.439808 # ok 1466 # SKIP Disabled ZA for VL 7824
7359 11:31:13.440221 # ok 1467 # SKIP Get and set data for VL 7824
7360 11:31:13.440326 # ok 1468 Set VL 7840
7361 11:31:13.440410 # ok 1469 # SKIP Disabled ZA for VL 7840
7362 11:31:13.440508 # ok 1470 # SKIP Get and set data for VL 7840
7363 11:31:13.440593 # ok 1471 Set VL 7856
7364 11:31:13.440695 # ok 1472 # SKIP Disabled ZA for VL 7856
7365 11:31:13.440784 # ok 1473 # SKIP Get and set data for VL 7856
7366 11:31:13.440880 # ok 1474 Set VL 7872
7367 11:31:13.440965 # ok 1475 # SKIP Disabled ZA for VL 7872
7368 11:31:13.441061 # ok 1476 # SKIP Get and set data for VL 7872
7369 11:31:13.441159 # ok 1477 Set VL 7888
7370 11:31:13.441255 # ok 1478 # SKIP Disabled ZA for VL 7888
7371 11:31:13.441587 # ok 1479 # SKIP Get and set data for VL 7888
7372 11:31:13.441697 # ok 1480 Set VL 7904
7373 11:31:13.441785 # ok 1481 # SKIP Disabled ZA for VL 7904
7374 11:31:13.441883 # ok 1482 # SKIP Get and set data for VL 7904
7375 11:31:13.441970 # ok 1483 Set VL 7920
7376 11:31:13.442071 # ok 1484 # SKIP Disabled ZA for VL 7920
7377 11:31:13.442169 # ok 1485 # SKIP Get and set data for VL 7920
7378 11:31:13.442256 # ok 1486 Set VL 7936
7379 11:31:13.442355 # ok 1487 # SKIP Disabled ZA for VL 7936
7380 11:31:13.442456 # ok 1488 # SKIP Get and set data for VL 7936
7381 11:31:13.442554 # ok 1489 Set VL 7952
7382 11:31:13.442650 # ok 1490 # SKIP Disabled ZA for VL 7952
7383 11:31:13.442980 # ok 1491 # SKIP Get and set data for VL 7952
7384 11:31:13.443138 # ok 1492 Set VL 7968
7385 11:31:13.458917 # ok 1493 # SKIP Disabled ZA for VL 7968
7386 11:31:13.459239 # ok 1494 # SKIP Get and set data for VL 7968
7387 11:31:13.459655 # ok 1495 Set VL 7984
7388 11:31:13.459815 # ok 1496 # SKIP Disabled ZA for VL 7984
7389 11:31:13.459943 # ok 1497 # SKIP Get and set data for VL 7984
7390 11:31:13.460066 # ok 1498 Set VL 8000
7391 11:31:13.460188 # ok 1499 # SKIP Disabled ZA for VL 8000
7392 11:31:13.460310 # ok 1500 # SKIP Get and set data for VL 8000
7393 11:31:13.460434 # ok 1501 Set VL 8016
7394 11:31:13.460591 # ok 1502 # SKIP Disabled ZA for VL 8016
7395 11:31:13.460769 # ok 1503 # SKIP Get and set data for VL 8016
7396 11:31:13.460895 # ok 1504 Set VL 8032
7397 11:31:13.461010 # ok 1505 # SKIP Disabled ZA for VL 8032
7398 11:31:13.466135 # ok 1506 # SKIP Get and set data for VL 8032
7399 11:31:13.466540 # ok 1507 Set VL 8048
7400 11:31:13.466735 # ok 1508 # SKIP Disabled ZA for VL 8048
7401 11:31:13.466902 # ok 1509 # SKIP Get and set data for VL 8048
7402 11:31:13.467070 # ok 1510 Set VL 8064
7403 11:31:13.467236 # ok 1511 # SKIP Disabled ZA for VL 8064
7404 11:31:13.467428 # ok 1512 # SKIP Get and set data for VL 8064
7405 11:31:13.467589 # ok 1513 Set VL 8080
7406 11:31:13.467750 # ok 1514 # SKIP Disabled ZA for VL 8080
7407 11:31:13.467909 # ok 1515 # SKIP Get and set data for VL 8080
7408 11:31:13.468058 # ok 1516 Set VL 8096
7409 11:31:13.468195 # ok 1517 # SKIP Disabled ZA for VL 8096
7410 11:31:13.468330 # ok 1518 # SKIP Get and set data for VL 8096
7411 11:31:13.468473 # ok 1519 Set VL 8112
7412 11:31:13.468614 # ok 1520 # SKIP Disabled ZA for VL 8112
7413 11:31:13.468760 # ok 1521 # SKIP Get and set data for VL 8112
7414 11:31:13.468886 # ok 1522 Set VL 8128
7415 11:31:13.469032 # ok 1523 # SKIP Disabled ZA for VL 8128
7416 11:31:13.469150 # ok 1524 # SKIP Get and set data for VL 8128
7417 11:31:13.469263 # ok 1525 Set VL 8144
7418 11:31:13.469375 # ok 1526 # SKIP Disabled ZA for VL 8144
7419 11:31:13.469487 # ok 1527 # SKIP Get and set data for VL 8144
7420 11:31:13.469598 # ok 1528 Set VL 8160
7421 11:31:13.469786 # ok 1529 # SKIP Disabled ZA for VL 8160
7422 11:31:13.469981 # ok 1530 # SKIP Get and set data for VL 8160
7423 11:31:13.470162 # ok 1531 Set VL 8176
7424 11:31:13.470342 # ok 1532 # SKIP Disabled ZA for VL 8176
7425 11:31:13.470504 # ok 1533 # SKIP Get and set data for VL 8176
7426 11:31:13.470647 # ok 1534 Set VL 8192
7427 11:31:13.470791 # ok 1535 # SKIP Disabled ZA for VL 8192
7428 11:31:13.478467 # ok 1536 # SKIP Get and set data for VL 8192
7429 11:31:13.478846 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7430 11:31:13.478994 ok 34 selftests: arm64: za-ptrace
7431 11:31:13.479143 # selftests: arm64: check_buffer_fill
7432 11:31:13.880453 # 1..20
7433 11:31:13.881003 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7434 11:31:13.881165 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7435 11:31:13.882719 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7436 11:31:13.883073 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7437 11:31:13.883271 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7438 11:31:13.883466 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7439 11:31:13.883632 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7440 11:31:13.883841 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7441 11:31:13.884002 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7442 11:31:13.884169 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 11:31:13.884366 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7444 11:31:13.884535 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7445 11:31:13.884697 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7446 11:31:13.884868 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7447 11:31:13.884992 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7448 11:31:13.886538 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7449 11:31:13.887039 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7450 11:31:13.887240 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7451 11:31:13.887370 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7452 11:31:13.887512 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7453 11:31:13.887634 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7454 11:31:13.910856 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7455 11:31:14.056451 # selftests: arm64: check_child_memory
7456 11:31:14.519045 # 1..12
7457 11:31:14.519519 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7458 11:31:14.519700 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7459 11:31:14.519933 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7460 11:31:14.520095 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7461 11:31:14.520318 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7462 11:31:14.520511 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7463 11:31:14.520708 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7464 11:31:14.520886 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7465 11:31:14.521038 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7466 11:31:14.521185 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7467 11:31:14.528245 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7468 11:31:14.528589 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7469 11:31:14.528756 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7470 11:31:14.551749 not ok 36 selftests: arm64: check_child_memory # exit=1
7471 11:31:14.696175 # selftests: arm64: check_gcr_el1_cswitch
7472 11:31:59.946749 <47>[ 100.376090] systemd-journald[105]: Sent WATCHDOG=1 notification.
7473 11:32:01.590402 <47>[ 102.021388] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3329 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
7474 11:32:01.592027 <47>[ 102.022977] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
7475 11:32:01.592257 <47>[ 102.023494] systemd-journald[105]: Rotating...
7476 11:32:01.633467 <47>[ 102.064745] systemd-journald[105]: Reserving 333 entries in field hash table.
7477 11:32:01.697524 <47>[ 102.128789] systemd-journald[105]: Reserving 4437 entries in data hash table.
7478 11:32:01.729219 <47>[ 102.160518] systemd-journald[105]: Vacuuming...
7479 11:32:01.747973 <47>[ 102.179093] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
7480 11:32:02.093218 # 1..1
7481 11:32:02.093502 # 1..1
7482 11:32:02.093638 # 1..1
7483 11:32:02.093816 # 1..1
7484 11:32:02.094230 # 1..1
7485 11:32:02.094387 # 1..1
7486 11:32:02.094509 # 1..1
7487 11:32:02.094625 # 1..1
7488 11:32:02.094739 # 1..1
7489 11:32:02.094851 # 1..1
7490 11:32:02.094965 # 1..1
7491 11:32:02.095079 # 1..1
7492 11:32:02.095193 # 1..1
7493 11:32:02.095311 # 1..1
7494 11:32:02.095489 # 1..1
7495 11:32:02.095637 # 1..1
7496 11:32:02.095780 # 1..1
7497 11:32:02.095922 # 1..1
7498 11:32:02.096068 # 1..1
7499 11:32:02.096209 # 1..1
7500 11:32:02.096349 # 1..1
7501 11:32:02.096490 # 1..1
7502 11:32:02.096630 # 1..1
7503 11:32:02.096771 # 1..1
7504 11:32:02.096914 # 1..1
7505 11:32:02.097055 # 1..1
7506 11:32:02.097196 # 1..1
7507 11:32:02.097337 # 1..1
7508 11:32:02.097478 # 1..1
7509 11:32:02.097620 # 1..1
7510 11:32:02.097774 # 1..1
7511 11:32:02.097917 # 1..1
7512 11:32:02.098058 # 1..1
7513 11:32:02.098198 # 1..1
7514 11:32:02.098339 # 1..1
7515 11:32:02.098480 # 1..1
7516 11:32:02.116630 # 1..1
7517 11:32:02.116879 # 1..1
7518 11:32:02.116986 # 1..1
7519 11:32:02.117091 # 1..1
7520 11:32:02.117190 # 1..1
7521 11:32:02.117539 # 1..1
7522 11:32:02.117659 # 1..1
7523 11:32:02.117773 # 1..1
7524 11:32:02.117877 # 1..1
7525 11:32:02.117984 # 1..1
7526 11:32:02.118087 # 1..1
7527 11:32:02.118191 # 1..1
7528 11:32:02.118274 # 1..1
7529 11:32:02.118343 # 1..1
7530 11:32:02.118405 # 1..1
7531 11:32:02.118468 # 1..1
7532 11:32:02.118531 # 1..1
7533 11:32:02.118593 # 1..1
7534 11:32:02.118655 # 1..1
7535 11:32:02.118714 # 1..1
7536 11:32:02.118775 # 1..1
7537 11:32:02.118837 # 1..1
7538 11:32:02.118899 # 1..1
7539 11:32:02.118960 # 1..1
7540 11:32:02.119021 # 1..1
7541 11:32:02.119081 # 1..1
7542 11:32:02.119143 # 1..1
7543 11:32:02.119204 # 1..1
7544 11:32:02.119266 # 1..1
7545 11:32:02.119326 # 1..1
7546 11:32:02.119387 # 1..1
7547 11:32:02.119447 # 1..1
7548 11:32:02.119508 # 1..1
7549 11:32:02.119569 # 1..1
7550 11:32:02.119629 # 1..1
7551 11:32:02.119690 # 1..1
7552 11:32:02.119749 # 1..1
7553 11:32:02.119809 # 1..1
7554 11:32:02.119871 # 1..1
7555 11:32:02.119932 # 1..1
7556 11:32:02.119992 # 1..1
7557 11:32:02.120052 # 1..1
7558 11:32:02.120112 # 1..1
7559 11:32:02.120173 # 1..1
7560 11:32:02.120235 # 1..1
7561 11:32:02.120296 # 1..1
7562 11:32:02.120378 # 1..1
7563 11:32:02.120443 # 1..1
7564 11:32:02.120505 # 1..1
7565 11:32:02.120566 # 1..1
7566 11:32:02.120628 # 1..1
7567 11:32:02.120689 # 1..1
7568 11:32:02.120750 # 1..1
7569 11:32:02.120810 # 1..1
7570 11:32:02.120869 # 1..1
7571 11:32:02.120931 # 1..1
7572 11:32:02.120991 # 1..1
7573 11:32:02.121057 # 1..1
7574 11:32:02.121116 # 1..1
7575 11:32:02.121174 # 1..1
7576 11:32:02.121234 # 1..1
7577 11:32:02.121295 # 1..1
7578 11:32:02.121353 # 1..1
7579 11:32:02.121415 # 1..1
7580 11:32:02.121474 # 1..1
7581 11:32:02.121532 # 1..1
7582 11:32:02.121591 # 1..1
7583 11:32:02.121678 # 1..1
7584 11:32:02.121788 # 1..1
7585 11:32:02.121884 # 1..1
7586 11:32:02.121978 # 1..1
7587 11:32:02.122071 # 1..1
7588 11:32:02.122164 # 1..1
7589 11:32:02.122258 # 1..1
7590 11:32:02.122358 # 1..1
7591 11:32:02.136959 # 1..1
7592 11:32:02.137183 # 1..1
7593 11:32:02.137549 # 1..1
7594 11:32:02.137664 # 1..1
7595 11:32:02.137756 # 1..1
7596 11:32:02.137868 # 1..1
7597 11:32:02.137972 # 1..1
7598 11:32:02.138091 # 1..1
7599 11:32:02.138199 # 1..1
7600 11:32:02.138286 # 1..1
7601 11:32:02.138356 # 1..1
7602 11:32:02.138419 # 1..1
7603 11:32:02.138479 # 1..1
7604 11:32:02.138540 # 1..1
7605 11:32:02.138599 # 1..1
7606 11:32:02.138660 # 1..1
7607 11:32:02.138719 # 1..1
7608 11:32:02.138797 # 1..1
7609 11:32:02.138860 # 1..1
7610 11:32:02.138920 # 1..1
7611 11:32:02.138981 # 1..1
7612 11:32:02.139046 # 1..1
7613 11:32:02.139104 # 1..1
7614 11:32:02.139164 # 1..1
7615 11:32:02.139223 # 1..1
7616 11:32:02.139283 # 1..1
7617 11:32:02.139344 # 1..1
7618 11:32:02.139403 # 1..1
7619 11:32:02.139464 # 1..1
7620 11:32:02.139524 # 1..1
7621 11:32:02.139583 # 1..1
7622 11:32:02.139653 # 1..1
7623 11:32:02.139733 # 1..1
7624 11:32:02.139804 # 1..1
7625 11:32:02.139865 # 1..1
7626 11:32:02.139925 # 1..1
7627 11:32:02.139985 # 1..1
7628 11:32:02.140049 # 1..1
7629 11:32:02.140109 # 1..1
7630 11:32:02.140170 # 1..1
7631 11:32:02.140230 # 1..1
7632 11:32:02.140289 # 1..1
7633 11:32:02.140348 # 1..1
7634 11:32:02.169811 # 1..1
7635 11:32:02.170164 # 1..1
7636 11:32:02.170364 # 1..1
7637 11:32:02.170731 # 1..1
7638 11:32:02.170866 # 1..1
7639 11:32:02.170988 # 1..1
7640 11:32:02.171105 # 1..1
7641 11:32:02.171222 # 1..1
7642 11:32:02.171338 # 1..1
7643 11:32:02.171455 # 1..1
7644 11:32:02.171570 # 1..1
7645 11:32:02.171685 # 1..1
7646 11:32:02.171801 # 1..1
7647 11:32:02.171919 # 1..1
7648 11:32:02.172035 # 1..1
7649 11:32:02.172151 # 1..1
7650 11:32:02.172268 # 1..1
7651 11:32:02.172382 # 1..1
7652 11:32:02.172497 # 1..1
7653 11:32:02.172613 # 1..1
7654 11:32:02.172729 # 1..1
7655 11:32:02.172843 # 1..1
7656 11:32:02.172959 # 1..1
7657 11:32:02.173075 # 1..1
7658 11:32:02.173190 # 1..1
7659 11:32:02.173306 # 1..1
7660 11:32:02.173423 # 1..1
7661 11:32:02.173538 # 1..1
7662 11:32:02.202509 # 1..1
7663 11:32:02.203779 # 1..1
7664 11:32:02.204051 # 1..1
7665 11:32:02.204247 # 1..1
7666 11:32:02.204329 # 1..1
7667 11:32:02.204400 # 1..1
7668 11:32:02.204469 # 1..1
7669 11:32:02.204538 # 1..1
7670 11:32:02.204608 # 1..1
7671 11:32:02.204677 # 1..1
7672 11:32:02.205032 # 1..1
7673 11:32:02.205241 # 1..1
7674 11:32:02.205316 # 1..1
7675 11:32:02.205385 # 1..1
7676 11:32:02.205459 # 1..1
7677 11:32:02.205535 # 1..1
7678 11:32:02.205608 # 1..1
7679 11:32:02.205699 # 1..1
7680 11:32:02.205782 # 1..1
7681 11:32:02.205861 # 1..1
7682 11:32:02.205941 # 1..1
7683 11:32:02.206022 # 1..1
7684 11:32:02.206106 # 1..1
7685 11:32:02.206193 # 1..1
7686 11:32:02.206272 # 1..1
7687 11:32:02.206348 # 1..1
7688 11:32:02.206420 # 1..1
7689 11:32:02.206512 # 1..1
7690 11:32:02.206594 # 1..1
7691 11:32:02.206678 # 1..1
7692 11:32:02.206765 # 1..1
7693 11:32:02.206843 # 1..1
7694 11:32:02.206904 # 1..1
7695 11:32:02.206963 # 1..1
7696 11:32:02.207046 # 1..1
7697 11:32:02.207133 # 1..1
7698 11:32:02.207215 # 1..1
7699 11:32:02.207296 # 1..1
7700 11:32:02.207379 # 1..1
7701 11:32:02.207444 # 1..1
7702 11:32:02.207503 # 1..1
7703 11:32:02.207562 # 1..1
7704 11:32:02.207621 # 1..1
7705 11:32:02.207685 # 1..1
7706 11:32:02.207744 # 1..1
7707 11:32:02.207803 # 1..1
7708 11:32:02.207862 # 1..1
7709 11:32:02.207933 # 1..1
7710 11:32:02.208019 # 1..1
7711 11:32:02.208100 # 1..1
7712 11:32:02.208182 # 1..1
7713 11:32:02.208263 # 1..1
7714 11:32:02.208345 # 1..1
7715 11:32:02.208459 # 1..1
7716 11:32:02.208535 # 1..1
7717 11:32:02.208603 # 1..1
7718 11:32:02.208670 # 1..1
7719 11:32:02.208738 # 1..1
7720 11:32:02.208805 # 1..1
7721 11:32:02.208872 # 1..1
7722 11:32:02.208939 # 1..1
7723 11:32:02.209006 # 1..1
7724 11:32:02.209074 # 1..1
7725 11:32:02.209150 # 1..1
7726 11:32:02.209235 # 1..1
7727 11:32:02.209317 # 1..1
7728 11:32:02.209403 # 1..1
7729 11:32:02.209487 # 1..1
7730 11:32:02.209570 # 1..1
7731 11:32:02.209661 # 1..1
7732 11:32:02.209734 # 1..1
7733 11:32:02.209803 # 1..1
7734 11:32:02.209872 # 1..1
7735 11:32:02.209940 # 1..1
7736 11:32:02.210010 # 1..1
7737 11:32:02.210083 # 1..1
7738 11:32:02.210152 # 1..1
7739 11:32:02.210221 # 1..1
7740 11:32:02.210290 # 1..1
7741 11:32:02.210359 # 1..1
7742 11:32:02.210427 # 1..1
7743 11:32:02.210496 # 1..1
7744 11:32:02.210565 # 1..1
7745 11:32:02.210634 # 1..1
7746 11:32:02.210703 # 1..1
7747 11:32:02.210772 # 1..1
7748 11:32:02.210842 # 1..1
7749 11:32:02.210910 # 1..1
7750 11:32:02.210979 # 1..1
7751 11:32:02.211048 # 1..1
7752 11:32:02.211117 # 1..1
7753 11:32:02.211186 # 1..1
7754 11:32:02.211261 # 1..1
7755 11:32:02.211343 # 1..1
7756 11:32:02.211416 # 1..1
7757 11:32:02.211484 # 1..1
7758 11:32:02.211552 # 1..1
7759 11:32:02.211620 # 1..1
7760 11:32:02.211688 # 1..1
7761 11:32:02.211756 # 1..1
7762 11:32:02.211824 # 1..1
7763 11:32:02.211892 # 1..1
7764 11:32:02.211960 # 1..1
7765 11:32:02.212027 # 1..1
7766 11:32:02.212094 # 1..1
7767 11:32:02.244927 # 1..1
7768 11:32:02.245466 # 1..1
7769 11:32:02.245583 # 1..1
7770 11:32:02.245688 # 1..1
7771 11:32:02.245777 # 1..1
7772 11:32:02.245862 # 1..1
7773 11:32:02.245945 # 1..1
7774 11:32:02.246030 # 1..1
7775 11:32:02.246112 # 1..1
7776 11:32:02.246194 # 1..1
7777 11:32:02.246277 # 1..1
7778 11:32:02.246360 # 1..1
7779 11:32:02.246443 # 1..1
7780 11:32:02.246525 # 1..1
7781 11:32:02.246608 # 1..1
7782 11:32:02.246690 # 1..1
7783 11:32:02.246773 # 1..1
7784 11:32:02.246854 # 1..1
7785 11:32:02.246936 # 1..1
7786 11:32:02.247018 # 1..1
7787 11:32:02.247100 # 1..1
7788 11:32:02.247182 # 1..1
7789 11:32:02.247271 # 1..1
7790 11:32:02.247356 # 1..1
7791 11:32:02.247440 # 1..1
7792 11:32:02.247547 # 1..1
7793 11:32:02.247634 # 1..1
7794 11:32:02.247718 # 1..1
7795 11:32:02.247803 # 1..1
7796 11:32:02.247886 # 1..1
7797 11:32:02.247970 # 1..1
7798 11:32:02.248053 # 1..1
7799 11:32:02.248135 # 1..1
7800 11:32:02.248218 # 1..1
7801 11:32:02.248303 # 1..1
7802 11:32:02.248389 # 1..1
7803 11:32:02.248474 # 1..1
7804 11:32:02.248557 # 1..1
7805 11:32:02.248640 # 1..1
7806 11:32:02.248724 # 1..1
7807 11:32:02.248811 # 1..1
7808 11:32:02.248901 # 1..1
7809 11:32:02.248992 # 1..1
7810 11:32:02.355969 #
7811 11:32:02.369153 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
7812 11:32:03.297485 # selftests: arm64: check_ksm_options
7813 11:32:04.160936 # 1..4
7814 11:32:04.161188 # # Invalid MTE synchronous exception caught!
7815 11:32:04.290116 not ok 38 selftests: arm64: check_ksm_options # exit=1
7816 11:32:05.146261 # selftests: arm64: check_mmap_options
7817 11:32:07.376961 # 1..22
7818 11:32:07.377453 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
7819 11:32:07.377573 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
7820 11:32:07.377694 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
7821 11:32:07.378069 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
7822 11:32:07.384226 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
7823 11:32:07.384877 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
7824 11:32:07.385067 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
7825 11:32:07.385204 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
7826 11:32:07.385597 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
7827 11:32:07.385763 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
7828 11:32:07.385918 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
7829 11:32:07.386067 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
7830 11:32:07.397367 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
7831 11:32:07.397944 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
7832 11:32:07.398064 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
7833 11:32:07.398463 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
7834 11:32:07.398576 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
7835 11:32:07.434372 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
7836 11:32:07.436086 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
7837 11:32:07.436646 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
7838 11:32:07.437057 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
7839 11:32:07.437284 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
7840 11:32:07.437719 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
7841 11:32:07.541836 not ok 39 selftests: arm64: check_mmap_options # exit=1
7842 11:32:08.352138 # selftests: arm64: check_prctl
7843 11:32:08.984930 # TAP version 13
7844 11:32:08.985152 # 1..5
7845 11:32:08.985245 # ok 1 check_basic_read
7846 11:32:08.985321 # ok 2 NONE
7847 11:32:08.985393 # ok 3 SYNC
7848 11:32:08.985463 # ok 4 ASYNC
7849 11:32:08.985533 # ok 5 SYNC+ASYNC
7850 11:32:08.985604 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
7851 11:32:09.017244 ok 40 selftests: arm64: check_prctl
7852 11:32:09.266115 # selftests: arm64: check_tags_inclusion
7853 11:32:09.718377 # 1..4
7854 11:32:09.718633 # # Unexpected fault recorded for 0xc00ffff9907c000-0xc00ffff9907c050 in mode 1
7855 11:32:09.718731 # not ok 1 Check an included tag value with sync mode
7856 11:32:09.719061 # # Unexpected fault recorded for 0x100ffff9907c000-0x100ffff9907c050 in mode 1
7857 11:32:09.726283 # not ok 2 Check different included tags value with sync mode
7858 11:32:09.729501 # ok 3 Check none included tags value with sync mode
7859 11:32:09.729741 # # Unexpected fault recorded for 0xf00ffff9907c000-0xf00ffff9907c050 in mode 1
7860 11:32:09.730050 # not ok 4 Check all included tags value with sync mode
7861 11:32:09.730159 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
7862 11:32:09.789352 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
7863 11:32:10.112994 # selftests: arm64: check_user_mem
7864 11:32:19.569458 # 1..64
7865 11:32:19.570461 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7866 11:32:19.570561 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7867 11:32:19.570662 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7868 11:32:19.570782 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7869 11:32:19.570883 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7870 11:32:19.573783 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7871 11:32:19.574155 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7872 11:32:19.574248 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7873 11:32:19.575488 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7874 11:32:19.575961 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7875 11:32:19.576085 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7876 11:32:19.576405 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7877 11:32:19.576829 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7878 11:32:19.576926 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7879 11:32:19.577234 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7880 11:32:19.577341 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7881 11:32:19.577434 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7882 11:32:19.577521 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7883 11:32:19.577633 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7884 11:32:19.577954 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7885 11:32:19.578272 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7886 11:32:19.583891 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7887 11:32:19.584332 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7888 11:32:19.584431 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7889 11:32:19.584515 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7890 11:32:19.584622 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7891 11:32:19.584713 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7892 11:32:19.585010 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7893 11:32:19.585273 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7894 11:32:19.585583 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7895 11:32:19.585716 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7896 11:32:19.586000 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7897 11:32:19.591929 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7898 11:32:19.592421 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7899 11:32:19.592515 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7900 11:32:19.592604 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7901 11:32:19.592708 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7902 11:32:19.592992 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7903 11:32:19.593091 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7904 11:32:19.593188 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7905 11:32:19.593484 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7906 11:32:19.593598 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7907 11:32:19.593709 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7908 11:32:19.594018 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7909 11:32:19.594152 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7910 11:32:19.600662 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7911 11:32:19.601167 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7912 11:32:19.601302 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7913 11:32:19.601398 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7914 11:32:19.601732 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7915 11:32:19.601829 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7916 11:32:21.649497 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7917 11:32:21.650093 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7918 11:32:21.650211 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7919 11:32:21.650318 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7920 11:32:21.650408 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7921 11:32:21.650656 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
7922 11:32:21.656604 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
7923 11:32:21.657218 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
7924 11:32:21.657320 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
7925 11:32:21.657406 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
7926 11:32:21.657507 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
7927 11:32:21.657612 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
7928 11:32:21.657922 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
7929 11:32:21.658023 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
7930 11:32:21.709056 ok 42 selftests: arm64: check_user_mem
7931 11:32:21.965215 # selftests: arm64: btitest
7932 11:32:22.173167 # TAP version 13
7933 11:32:22.173397 # 1..18
7934 11:32:22.173476 # # HWCAP_PACA present
7935 11:32:22.173549 # # HWCAP2_BTI present
7936 11:32:22.173620 # # Test binary built for BTI
7937 11:32:22.174082 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
7938 11:32:22.174183 # ok 1 nohint_func/call_using_br_x0
7939 11:32:22.174258 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
7940 11:32:22.174329 # ok 2 nohint_func/call_using_br_x16
7941 11:32:22.174398 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
7942 11:32:22.174467 # ok 3 nohint_func/call_using_blr
7943 11:32:22.174535 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
7944 11:32:22.174604 # ok 4 bti_none_func/call_using_br_x0
7945 11:32:22.181640 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
7946 11:32:22.182162 # ok 5 bti_none_func/call_using_br_x16
7947 11:32:22.182334 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
7948 11:32:22.182465 # ok 6 bti_none_func/call_using_blr
7949 11:32:22.182592 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
7950 11:32:22.197317 # ok 7 bti_c_func/call_using_br_x0
7951 11:32:22.197570 # ok 8 bti_c_func/call_using_br_x16
7952 11:32:22.197894 # ok 9 bti_c_func/call_using_blr
7953 11:32:22.198001 # ok 10 bti_j_func/call_using_br_x0
7954 11:32:22.198090 # ok 11 bti_j_func/call_using_br_x16
7955 11:32:22.198175 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
7956 11:32:22.198263 # ok 12 bti_j_func/call_using_blr
7957 11:32:22.198369 # ok 13 bti_jc_func/call_using_br_x0
7958 11:32:22.198459 # ok 14 bti_jc_func/call_using_br_x16
7959 11:32:22.198546 # ok 15 bti_jc_func/call_using_blr
7960 11:32:22.209272 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
7961 11:32:22.209704 # ok 16 paciasp_func/call_using_br_x0
7962 11:32:22.209802 # ok 17 paciasp_func/call_using_br_x16
7963 11:32:22.209879 # ok 18 paciasp_func/call_using_blr
7964 11:32:22.209951 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
7965 11:32:22.297119 ok 43 selftests: arm64: btitest
7966 11:32:22.573943 # selftests: arm64: nobtitest
7967 11:32:22.808721 # TAP version 13
7968 11:32:22.809069 # 1..18
7969 11:32:22.809517 # # HWCAP_PACA present
7970 11:32:22.809738 # # HWCAP2_BTI present
7971 11:32:22.809911 # # Test binary not built for BTI
7972 11:32:22.810078 # ok 1 nohint_func/call_using_br_x0
7973 11:32:22.810241 # ok 2 nohint_func/call_using_br_x16
7974 11:32:22.810384 # ok 3 nohint_func/call_using_blr
7975 11:32:22.810512 # ok 4 bti_none_func/call_using_br_x0
7976 11:32:22.810635 # ok 5 bti_none_func/call_using_br_x16
7977 11:32:22.810760 # ok 6 bti_none_func/call_using_blr
7978 11:32:22.810915 # ok 7 bti_c_func/call_using_br_x0
7979 11:32:22.811046 # ok 8 bti_c_func/call_using_br_x16
7980 11:32:22.811169 # ok 9 bti_c_func/call_using_blr
7981 11:32:22.811374 # ok 10 bti_j_func/call_using_br_x0
7982 11:32:22.811553 # ok 11 bti_j_func/call_using_br_x16
7983 11:32:22.811721 # ok 12 bti_j_func/call_using_blr
7984 11:32:22.817814 # ok 13 bti_jc_func/call_using_br_x0
7985 11:32:22.818121 # ok 14 bti_jc_func/call_using_br_x16
7986 11:32:22.818256 # ok 15 bti_jc_func/call_using_blr
7987 11:32:22.818386 # ok 16 paciasp_func/call_using_br_x0
7988 11:32:22.818509 # ok 17 paciasp_func/call_using_br_x16
7989 11:32:22.818635 # ok 18 paciasp_func/call_using_blr
7990 11:32:22.818764 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
7991 11:32:22.860608 ok 44 selftests: arm64: nobtitest
7992 11:32:23.197543 # selftests: arm64: hwcap
7993 11:32:23.641999 # TAP version 13
7994 11:32:23.642465 # 1..28
7995 11:32:23.642576 # # RNG present
7996 11:32:23.642668 # ok 1 cpuinfo_match_RNG
7997 11:32:23.642754 # ok 2 sigill_RNG
7998 11:32:23.642834 # # SME present
7999 11:32:23.642917 # ok 3 cpuinfo_match_SME
8000 11:32:23.643018 # ok 4 sigill_SME
8001 11:32:23.647555 # # SVE present
8002 11:32:23.648152 # ok 5 cpuinfo_match_SVE
8003 11:32:23.648267 # ok 6 sigill_SVE
8004 11:32:23.648362 # # SVE 2 present
8005 11:32:23.648449 # ok 7 cpuinfo_match_SVE 2
8006 11:32:23.648535 # ok 8 sigill_SVE 2
8007 11:32:23.648620 # # SVE AES present
8008 11:32:23.648706 # ok 9 cpuinfo_match_SVE AES
8009 11:32:23.648817 # ok 10 sigill_SVE AES
8010 11:32:23.648907 # # SVE2 PMULL present
8011 11:32:23.648994 # ok 11 cpuinfo_match_SVE2 PMULL
8012 11:32:23.649080 # ok 12 sigill_SVE2 PMULL
8013 11:32:23.649166 # # SVE2 BITPERM present
8014 11:32:23.649251 # ok 13 cpuinfo_match_SVE2 BITPERM
8015 11:32:23.649339 # ok 14 sigill_SVE2 BITPERM
8016 11:32:23.649425 # # SVE2 SHA3 present
8017 11:32:23.649530 # ok 15 cpuinfo_match_SVE2 SHA3
8018 11:32:23.649618 # ok 16 sigill_SVE2 SHA3
8019 11:32:23.649713 # # SVE2 SM4 present
8020 11:32:23.649802 # ok 17 cpuinfo_match_SVE2 SM4
8021 11:32:23.649890 # ok 18 sigill_SVE2 SM4
8022 11:32:23.649976 # # SVE2 I8MM present
8023 11:32:23.650077 # ok 19 cpuinfo_match_SVE2 I8MM
8024 11:32:23.650163 # ok 20 sigill_SVE2 I8MM
8025 11:32:23.650260 # # SVE2 F32MM present
8026 11:32:23.650339 # ok 21 cpuinfo_match_SVE2 F32MM
8027 11:32:23.650410 # ok 22 sigill_SVE2 F32MM
8028 11:32:23.650481 # # SVE2 F64MM present
8029 11:32:23.650551 # ok 23 cpuinfo_match_SVE2 F64MM
8030 11:32:23.650636 # ok 24 sigill_SVE2 F64MM
8031 11:32:23.650710 # # SVE2 BF16 present
8032 11:32:23.655949 # ok 25 cpuinfo_match_SVE2 BF16
8033 11:32:23.656539 # ok 26 sigill_SVE2 BF16
8034 11:32:23.656739 # ok 27 cpuinfo_match_SVE2 EBF16
8035 11:32:23.656924 # ok 28 # SKIP sigill_SVE2 EBF16
8036 11:32:23.657088 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8037 11:32:23.685551 ok 45 selftests: arm64: hwcap
8038 11:32:23.972738 # selftests: arm64: ptrace
8039 11:32:24.308810 # TAP version 13
8040 11:32:24.309056 # 1..7
8041 11:32:24.309154 # # Parent is 3249, child is 3250
8042 11:32:24.309245 # ok 1 read_tpidr_one
8043 11:32:24.309537 # ok 2 write_tpidr_one
8044 11:32:24.309656 # ok 3 verify_tpidr_one
8045 11:32:24.309739 # ok 4 count_tpidrs
8046 11:32:24.309814 # ok 5 tpidr2_write
8047 11:32:24.309887 # ok 6 tpidr2_read
8048 11:32:24.309961 # ok 7 write_tpidr_only
8049 11:32:24.310033 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8050 11:32:24.356557 ok 46 selftests: arm64: ptrace
8051 11:32:24.589002 # selftests: arm64: syscall-abi
8052 11:32:27.601551 # TAP version 13
8053 11:32:27.601818 # 1..514
8054 11:32:27.602150 # # SME with FA64
8055 11:32:27.602253 # ok 1 getpid() FPSIMD
8056 11:32:27.602343 # ok 2 getpid() SVE VL 256
8057 11:32:27.602431 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8058 11:32:27.602515 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8059 11:32:27.603192 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8060 11:32:27.603493 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8061 11:32:27.603593 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8062 11:32:27.604005 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8063 11:32:27.604097 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8064 11:32:27.604177 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8065 11:32:27.604264 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8066 11:32:27.604366 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8067 11:32:27.604452 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8068 11:32:27.604534 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8069 11:32:27.604620 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8070 11:32:27.604720 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8071 11:32:27.604805 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8072 11:32:27.604904 # ok 18 getpid() SVE VL 240
8073 11:32:27.604986 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8074 11:32:27.605083 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8075 11:32:27.605169 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8076 11:32:27.605265 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8077 11:32:27.605371 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8078 11:32:27.605697 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8079 11:32:27.605802 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8080 11:32:27.605886 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8081 11:32:27.605968 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8082 11:32:27.606066 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8083 11:32:27.606148 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8084 11:32:27.606231 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8085 11:32:27.606312 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8086 11:32:27.606412 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8087 11:32:27.611452 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8088 11:32:27.611911 # ok 34 getpid() SVE VL 224
8089 11:32:27.612014 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8090 11:32:27.612100 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8091 11:32:27.612183 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8092 11:32:27.612287 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8093 11:32:27.612373 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8094 11:32:27.612457 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8095 11:32:27.612557 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8096 11:32:27.612642 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8097 11:32:27.612727 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8098 11:32:27.612825 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8099 11:32:27.612910 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8100 11:32:27.613007 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8101 11:32:27.613104 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8102 11:32:27.613415 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8103 11:32:27.613529 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8104 11:32:27.613641 # ok 50 getpid() SVE VL 208
8105 11:32:27.613746 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8106 11:32:27.613855 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8107 11:32:27.613961 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8108 11:32:27.614064 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8109 11:32:27.614169 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8110 11:32:27.619649 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8111 11:32:27.619895 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8112 11:32:27.619986 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8113 11:32:27.620070 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8114 11:32:27.620372 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8115 11:32:27.620478 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8116 11:32:27.620576 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8117 11:32:27.620679 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8118 11:32:27.620773 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8119 11:32:27.620862 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8120 11:32:27.620948 # ok 66 getpid() SVE VL 192
8121 11:32:27.621035 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8122 11:32:27.621147 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8123 11:32:27.621258 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8124 11:32:27.621361 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8125 11:32:27.621484 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8126 11:32:27.621585 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8127 11:32:27.621695 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8128 11:32:27.621793 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8129 11:32:27.621895 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8130 11:32:27.622011 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8131 11:32:27.622109 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8132 11:32:27.622206 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8133 11:32:27.622302 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8134 11:32:27.622423 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8135 11:32:27.622522 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8136 11:32:27.626979 # ok 82 getpid() SVE VL 176
8137 11:32:27.627440 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8138 11:32:27.627550 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8139 11:32:27.627641 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8140 11:32:27.627729 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8141 11:32:27.627831 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8142 11:32:27.627919 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8143 11:32:27.628005 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8144 11:32:27.628108 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8145 11:32:27.628198 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8146 11:32:27.628304 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8147 11:32:27.628396 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8148 11:32:27.628501 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8149 11:32:27.628604 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8150 11:32:27.628706 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8151 11:32:27.628819 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8152 11:32:27.628922 # ok 98 getpid() SVE VL 160
8153 11:32:30.460348 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8154 11:32:30.460692 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8155 11:32:30.461170 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8156 11:32:30.461396 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8157 11:32:30.461585 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8158 11:32:30.461750 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8159 11:32:30.461886 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8160 11:32:30.462011 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8161 11:32:30.462138 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8162 11:32:30.462266 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8163 11:32:30.462421 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8164 11:32:30.462547 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8165 11:32:30.462673 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8166 11:32:30.462853 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8167 11:32:30.463034 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8168 11:32:30.463220 # ok 114 getpid() SVE VL 144
8169 11:32:30.463382 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8170 11:32:30.463512 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8171 11:32:30.463629 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8172 11:32:30.470870 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8173 11:32:30.471390 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8174 11:32:30.471599 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8175 11:32:30.471777 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8176 11:32:30.471948 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8177 11:32:30.472117 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8178 11:32:30.472243 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8179 11:32:30.472392 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8180 11:32:30.472516 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8181 11:32:30.472637 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8182 11:32:30.472757 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8183 11:32:30.472887 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8184 11:32:30.473065 # ok 130 getpid() SVE VL 128
8185 11:32:30.473214 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8186 11:32:30.473399 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8187 11:32:30.473536 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8188 11:32:30.473712 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8189 11:32:30.473908 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8190 11:32:30.474100 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8191 11:32:30.474258 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8192 11:32:30.474431 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8193 11:32:30.474579 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8194 11:32:30.474721 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8195 11:32:30.474866 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8196 11:32:30.475007 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8197 11:32:30.475234 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8198 11:32:30.475417 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8199 11:32:30.475606 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8200 11:32:30.475772 # ok 146 getpid() SVE VL 112
8201 11:32:30.475941 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8202 11:32:30.476106 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8203 11:32:30.476793 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8204 11:32:30.476913 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8205 11:32:30.477011 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8206 11:32:30.477101 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8207 11:32:30.477187 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8208 11:32:30.477274 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8209 11:32:30.477362 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8210 11:32:30.477448 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8211 11:32:30.477532 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8212 11:32:30.477615 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8213 11:32:30.477704 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8214 11:32:30.477781 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8215 11:32:30.477863 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8216 11:32:30.477939 # ok 162 getpid() SVE VL 96
8217 11:32:30.478014 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8218 11:32:30.478414 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8219 11:32:30.478579 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8220 11:32:30.478757 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8221 11:32:30.478911 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8222 11:32:30.479033 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8223 11:32:30.479209 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8224 11:32:30.479380 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8225 11:32:30.479550 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8226 11:32:30.479717 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8227 11:32:30.479837 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8228 11:32:30.479972 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8229 11:32:30.480140 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8230 11:32:30.483713 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8231 11:32:30.484142 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8232 11:32:30.484250 # ok 178 getpid() SVE VL 80
8233 11:32:30.484338 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8234 11:32:30.484441 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8235 11:32:30.484517 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8236 11:32:30.484588 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8237 11:32:30.484657 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8238 11:32:30.484741 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8239 11:32:30.484815 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8240 11:32:30.484900 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8241 11:32:30.484983 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8242 11:32:30.485261 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8243 11:32:30.485372 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8244 11:32:30.485480 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8245 11:32:30.485572 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8246 11:32:30.485685 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8247 11:32:30.485778 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8248 11:32:30.485882 # ok 194 getpid() SVE VL 64
8249 11:32:30.485968 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8250 11:32:33.054893 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8251 11:32:33.057751 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8252 11:32:33.057934 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8253 11:32:33.058032 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8254 11:32:33.058133 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8255 11:32:33.058213 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8256 11:32:33.058276 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8257 11:32:33.058336 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8258 11:32:33.058396 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8259 11:32:33.058480 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8260 11:32:33.058563 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8261 11:32:33.058626 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8262 11:32:33.058709 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8263 11:32:33.058802 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8264 11:32:33.058894 # ok 210 getpid() SVE VL 48
8265 11:32:33.058959 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8266 11:32:33.059019 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8267 11:32:33.059079 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8268 11:32:33.059139 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8269 11:32:33.059199 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8270 11:32:33.059290 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8271 11:32:33.059410 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8272 11:32:33.059512 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8273 11:32:33.059594 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8274 11:32:33.059656 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8275 11:32:33.059731 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8276 11:32:33.059810 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8277 11:32:33.059892 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8278 11:32:33.059973 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8279 11:32:33.060055 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8280 11:32:33.060132 # ok 226 getpid() SVE VL 32
8281 11:32:33.060193 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8282 11:32:33.060270 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8283 11:32:33.060334 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8284 11:32:33.060406 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8285 11:32:33.060489 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8286 11:32:33.060569 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8287 11:32:33.060652 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8288 11:32:33.061577 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8289 11:32:33.061801 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8290 11:32:33.061905 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8291 11:32:33.062000 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8292 11:32:33.062082 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8293 11:32:33.062163 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8294 11:32:33.062245 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8295 11:32:33.062343 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8296 11:32:33.062437 # ok 242 getpid() SVE VL 16
8297 11:32:33.062526 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8298 11:32:33.062591 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8299 11:32:33.062652 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8300 11:32:33.062712 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8301 11:32:33.062771 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8302 11:32:33.062830 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8303 11:32:33.062890 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8304 11:32:33.062950 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8305 11:32:33.063009 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8306 11:32:33.063333 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8307 11:32:33.063537 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8308 11:32:33.063701 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8309 11:32:33.063832 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8310 11:32:33.063952 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8311 11:32:33.064067 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8312 11:32:33.064184 # ok 258 sched_yield() FPSIMD
8313 11:32:33.064299 # ok 259 sched_yield() SVE VL 256
8314 11:32:33.067210 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8315 11:32:33.067722 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8316 11:32:33.067908 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8317 11:32:33.068057 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8318 11:32:33.068233 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8319 11:32:33.068386 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8320 11:32:33.068551 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8321 11:32:33.068715 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8322 11:32:33.068912 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8323 11:32:33.069081 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8324 11:32:33.069243 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8325 11:32:33.069405 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8326 11:32:33.069602 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8327 11:32:33.069790 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8328 11:32:33.069953 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8329 11:32:33.070114 # ok 275 sched_yield() SVE VL 240
8330 11:32:33.070274 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8331 11:32:33.070435 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8332 11:32:33.070625 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8333 11:32:33.070790 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8334 11:32:33.070915 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8335 11:32:33.074748 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8336 11:32:33.075151 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8337 11:32:33.075249 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8338 11:32:33.075337 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8339 11:32:33.075442 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8340 11:32:33.075537 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8341 11:32:33.075639 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8342 11:32:33.075746 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8343 11:32:33.075849 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8344 11:32:35.447121 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8345 11:32:35.447635 # ok 291 sched_yield() SVE VL 224
8346 11:32:35.447744 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8347 11:32:35.447833 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8348 11:32:35.448116 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8349 11:32:35.448227 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8350 11:32:35.448321 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8351 11:32:35.448455 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8352 11:32:35.448547 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8353 11:32:35.448664 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8354 11:32:35.448778 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8355 11:32:35.448909 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8356 11:32:35.449040 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8357 11:32:35.449164 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8358 11:32:35.449286 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8359 11:32:35.449420 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8360 11:32:35.449602 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8361 11:32:35.449746 # ok 307 sched_yield() SVE VL 208
8362 11:32:35.449876 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8363 11:32:35.450001 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8364 11:32:35.450132 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8365 11:32:35.451239 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8366 11:32:35.451595 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8367 11:32:35.451706 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8368 11:32:35.451810 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8369 11:32:35.451911 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8370 11:32:35.452224 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8371 11:32:35.452338 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8372 11:32:35.453042 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8373 11:32:35.453147 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8374 11:32:35.453234 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8375 11:32:35.453324 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8376 11:32:35.453409 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8377 11:32:35.453492 # ok 323 sched_yield() SVE VL 192
8378 11:32:35.453789 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8379 11:32:35.453893 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8380 11:32:35.453984 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8381 11:32:35.454070 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8382 11:32:35.454357 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8383 11:32:35.454462 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8384 11:32:35.454551 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8385 11:32:35.460352 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8386 11:32:35.460748 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8387 11:32:35.461066 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8388 11:32:35.461365 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8389 11:32:35.461472 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8390 11:32:35.461582 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8391 11:32:35.461710 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8392 11:32:35.461814 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8393 11:32:35.461914 # ok 339 sched_yield() SVE VL 176
8394 11:32:35.462015 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8395 11:32:35.462315 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8396 11:32:35.463284 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8397 11:32:35.463409 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8398 11:32:35.463532 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8399 11:32:35.463855 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8400 11:32:35.463968 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8401 11:32:35.464081 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8402 11:32:35.464180 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8403 11:32:35.464310 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8404 11:32:35.464414 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8405 11:32:35.464538 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8406 11:32:35.464645 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8407 11:32:35.464764 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8408 11:32:35.464863 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8409 11:32:35.464980 # ok 355 sched_yield() SVE VL 160
8410 11:32:35.465112 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8411 11:32:35.465222 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8412 11:32:35.465355 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8413 11:32:35.465461 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8414 11:32:35.465593 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8415 11:32:35.465730 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8416 11:32:35.465848 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8417 11:32:35.465949 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8418 11:32:35.466071 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8419 11:32:35.466175 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8420 11:32:35.466274 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8421 11:32:35.471622 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8422 11:32:35.471830 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8423 11:32:35.471930 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8424 11:32:35.472022 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8425 11:32:35.472128 # ok 371 sched_yield() SVE VL 144
8426 11:32:35.472219 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8427 11:32:35.472337 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8428 11:32:35.472439 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8429 11:32:35.472544 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8430 11:32:35.472637 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8431 11:32:38.048591 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8432 11:32:38.049034 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8433 11:32:38.049139 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8434 11:32:38.049236 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8435 11:32:38.049358 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8436 11:32:38.049456 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8437 11:32:38.049545 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8438 11:32:38.049639 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8439 11:32:38.049778 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8440 11:32:38.049882 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8441 11:32:38.049990 # ok 387 sched_yield() SVE VL 128
8442 11:32:38.050081 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8443 11:32:38.050183 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8444 11:32:38.050274 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8445 11:32:38.058885 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8446 11:32:38.059448 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8447 11:32:38.059559 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8448 11:32:38.059652 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8449 11:32:38.059754 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8450 11:32:38.059872 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8451 11:32:38.059962 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8452 11:32:38.060050 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8453 11:32:38.060152 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8454 11:32:38.060240 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8455 11:32:38.060527 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8456 11:32:38.060629 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8457 11:32:38.060715 # ok 403 sched_yield() SVE VL 112
8458 11:32:38.060799 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8459 11:32:38.060881 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8460 11:32:38.060955 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8461 11:32:38.061054 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8462 11:32:38.061308 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8463 11:32:38.061396 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8464 11:32:38.061462 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8465 11:32:38.061542 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8466 11:32:38.061608 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8467 11:32:38.061689 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8468 11:32:38.061758 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8469 11:32:38.061855 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8470 11:32:38.061939 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8471 11:32:38.062006 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8472 11:32:38.062065 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8473 11:32:38.062137 # ok 419 sched_yield() SVE VL 96
8474 11:32:38.063344 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8475 11:32:38.063474 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8476 11:32:38.063578 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8477 11:32:38.063677 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8478 11:32:38.063970 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8479 11:32:38.064095 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8480 11:32:38.064215 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8481 11:32:38.064348 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8482 11:32:38.064472 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8483 11:32:38.064795 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8484 11:32:38.064903 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8485 11:32:38.065025 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8486 11:32:38.065136 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8487 11:32:38.065267 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8488 11:32:38.065393 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8489 11:32:38.065515 # ok 435 sched_yield() SVE VL 80
8490 11:32:38.065639 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8491 11:32:38.065760 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8492 11:32:38.065884 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8493 11:32:38.066205 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8494 11:32:38.066311 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8495 11:32:38.066625 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8496 11:32:38.066770 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8497 11:32:38.066906 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8498 11:32:38.074374 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8499 11:32:38.074694 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8500 11:32:38.074984 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8501 11:32:38.075089 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8502 11:32:38.075196 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8503 11:32:38.075304 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8504 11:32:38.075431 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8505 11:32:38.075549 # ok 451 sched_yield() SVE VL 64
8506 11:32:38.075690 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8507 11:32:38.075806 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8508 11:32:38.075925 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8509 11:32:38.076247 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8510 11:32:38.076336 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8511 11:32:38.076583 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8512 11:32:38.076696 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8513 11:32:38.076795 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8514 11:32:38.076903 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8515 11:32:38.076994 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8516 11:32:38.077113 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8517 11:32:38.077226 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8518 11:32:38.809731 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8519 11:32:38.810207 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8520 11:32:38.810325 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8521 11:32:38.810421 # ok 467 sched_yield() SVE VL 48
8522 11:32:38.812266 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8523 11:32:38.812659 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8524 11:32:38.812771 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8525 11:32:38.813102 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8526 11:32:38.813216 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8527 11:32:38.813310 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8528 11:32:38.813416 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8529 11:32:38.813507 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8530 11:32:38.813615 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8531 11:32:38.813720 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8532 11:32:38.813823 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8533 11:32:38.814128 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8534 11:32:38.814235 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8535 11:32:38.821340 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8536 11:32:38.821798 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8537 11:32:38.821910 # ok 483 sched_yield() SVE VL 32
8538 11:32:38.822001 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8539 11:32:38.822098 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8540 11:32:38.822214 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8541 11:32:38.822305 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8542 11:32:38.822390 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8543 11:32:38.823482 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8544 11:32:38.823594 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8545 11:32:38.823703 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8546 11:32:38.823808 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8547 11:32:38.823913 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8548 11:32:38.824265 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8549 11:32:38.824372 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8550 11:32:38.824476 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8551 11:32:38.824567 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8552 11:32:38.824673 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8553 11:32:38.824962 # ok 499 sched_yield() SVE VL 16
8554 11:32:38.825067 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8555 11:32:38.825172 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8556 11:32:38.825261 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8557 11:32:38.825361 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8558 11:32:38.825700 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8559 11:32:38.825806 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8560 11:32:38.825910 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8561 11:32:38.826000 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8562 11:32:38.826106 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8563 11:32:38.830655 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8564 11:32:38.830989 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8565 11:32:38.831140 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8566 11:32:38.831343 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8567 11:32:38.831430 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8568 11:32:38.831501 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8569 11:32:38.831592 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8570 11:32:38.831973 ok 47 selftests: arm64: syscall-abi
8571 11:32:38.903305 # selftests: arm64: tpidr2
8572 11:32:39.081822 # TAP version 13
8573 11:32:39.082092 # 1..5
8574 11:32:39.082333 # # PID: 3284
8575 11:32:39.082526 # ok 1 default_value
8576 11:32:39.082706 # ok 2 write_read
8577 11:32:39.082851 # ok 3 write_sleep_read
8578 11:32:39.083027 # ok 4 write_fork_read
8579 11:32:39.083187 # ok 5 write_clone_read
8580 11:32:39.083317 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8581 11:32:39.098337 ok 48 selftests: arm64: tpidr2
8582 11:32:39.676576 arm64_tags_test pass
8583 11:32:39.677024 arm64_run_tags_test_sh pass
8584 11:32:39.677133 arm64_fake_sigreturn_bad_magic pass
8585 11:32:39.677227 arm64_fake_sigreturn_bad_size pass
8586 11:32:39.677314 arm64_fake_sigreturn_bad_size_for_magic0 pass
8587 11:32:39.677416 arm64_fake_sigreturn_duplicated_fpsimd pass
8588 11:32:39.677505 arm64_fake_sigreturn_misaligned_sp pass
8589 11:32:39.677590 arm64_fake_sigreturn_missing_fpsimd pass
8590 11:32:39.677687 arm64_fake_sigreturn_sme_change_vl pass
8591 11:32:39.677792 arm64_fake_sigreturn_sve_change_vl pass
8592 11:32:39.677881 arm64_mangle_pstate_invalid_compat_toggle pass
8593 11:32:39.677984 arm64_mangle_pstate_invalid_daif_bits pass
8594 11:32:39.678072 arm64_mangle_pstate_invalid_mode_el1h pass
8595 11:32:39.678173 arm64_mangle_pstate_invalid_mode_el1t pass
8596 11:32:39.678470 arm64_mangle_pstate_invalid_mode_el2h pass
8597 11:32:39.678569 arm64_mangle_pstate_invalid_mode_el2t pass
8598 11:32:39.678671 arm64_mangle_pstate_invalid_mode_el3h pass
8599 11:32:39.678774 arm64_mangle_pstate_invalid_mode_el3t pass
8600 11:32:39.678875 arm64_sme_trap_no_sm pass
8601 11:32:39.678973 arm64_sme_trap_non_streaming skip
8602 11:32:39.679071 arm64_sme_trap_za pass
8603 11:32:39.679171 arm64_sme_vl pass
8604 11:32:39.679252 arm64_ssve_regs pass
8605 11:32:39.679382 arm64_sve_regs pass
8606 11:32:39.679489 arm64_sve_vl pass
8607 11:32:39.679616 arm64_za_no_regs pass
8608 11:32:39.679717 arm64_za_regs pass
8609 11:32:39.679805 arm64_pac_global_corrupt_pac pass
8610 11:32:39.679905 arm64_pac_global_pac_instructions_not_nop pass
8611 11:32:39.679991 arm64_pac_global_pac_instructions_not_nop_generic pass
8612 11:32:39.680087 arm64_pac_global_single_thread_different_keys pass
8613 11:32:39.680191 arm64_pac_global_exec_changed_keys pass
8614 11:32:39.680325 arm64_pac_global_context_switch_keep_keys pass
8615 11:32:39.680450 arm64_pac_global_context_switch_keep_keys_generic pass
8616 11:32:39.680558 arm64_pac pass
8617 11:32:39.680682 arm64_fp-stress_FPSIMD-0-0 pass
8618 11:32:39.680800 arm64_fp-stress_SVE-VL-256-0 pass
8619 11:32:39.680903 arm64_fp-stress_SVE-VL-240-0 pass
8620 11:32:39.680991 arm64_fp-stress_SVE-VL-224-0 pass
8621 11:32:39.681091 arm64_fp-stress_SVE-VL-208-0 pass
8622 11:32:39.681162 arm64_fp-stress_SVE-VL-192-0 pass
8623 11:32:39.681235 arm64_fp-stress_SVE-VL-176-0 pass
8624 11:32:39.681301 arm64_fp-stress_SVE-VL-160-0 pass
8625 11:32:39.681375 arm64_fp-stress_SVE-VL-144-0 pass
8626 11:32:39.681451 arm64_fp-stress_SVE-VL-128-0 pass
8627 11:32:39.681525 arm64_fp-stress_SVE-VL-112-0 pass
8628 11:32:39.681597 arm64_fp-stress_SVE-VL-96-0 pass
8629 11:32:39.681937 arm64_fp-stress_SVE-VL-80-0 pass
8630 11:32:39.682051 arm64_fp-stress_SVE-VL-64-0 pass
8631 11:32:39.682166 arm64_fp-stress_SVE-VL-48-0 pass
8632 11:32:39.682268 arm64_fp-stress_SVE-VL-32-0 pass
8633 11:32:39.686512 arm64_fp-stress_SVE-VL-16-0 pass
8634 11:32:39.686951 arm64_fp-stress_SSVE-VL-256-0 pass
8635 11:32:39.687058 arm64_fp-stress_ZA-VL-256-0 pass
8636 11:32:39.687144 arm64_fp-stress_SSVE-VL-128-0 pass
8637 11:32:39.687227 arm64_fp-stress_ZA-VL-128-0 pass
8638 11:32:39.687311 arm64_fp-stress_SSVE-VL-64-0 pass
8639 11:32:39.687395 arm64_fp-stress_ZA-VL-64-0 pass
8640 11:32:39.687478 arm64_fp-stress_SSVE-VL-32-0 pass
8641 11:32:39.687580 arm64_fp-stress_ZA-VL-32-0 pass
8642 11:32:39.687667 arm64_fp-stress_SSVE-VL-16-0 pass
8643 11:32:39.687751 arm64_fp-stress_ZA-VL-16-0 pass
8644 11:32:39.687835 arm64_fp-stress pass
8645 11:32:39.687918 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8646 11:32:39.688000 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8647 11:32:39.688100 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8648 11:32:39.688188 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8649 11:32:39.688272 arm64_sve-ptrace_Set_SVE_VL_16 pass
8650 11:32:39.688356 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8651 11:32:39.688438 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8652 11:32:39.688528 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8653 11:32:39.688624 arm64_sve-ptrace_Set_SVE_VL_32 pass
8654 11:32:39.688726 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8655 11:32:39.688815 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8656 11:32:39.688914 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8657 11:32:39.689013 arm64_sve-ptrace_Set_SVE_VL_48 pass
8658 11:32:39.689328 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8659 11:32:39.689440 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8660 11:32:39.689539 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8661 11:32:39.689616 arm64_sve-ptrace_Set_SVE_VL_64 pass
8662 11:32:39.689716 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8663 11:32:39.689805 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8664 11:32:39.690091 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8665 11:32:39.690185 arm64_sve-ptrace_Set_SVE_VL_80 pass
8666 11:32:39.694369 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8667 11:32:39.694809 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8668 11:32:39.694919 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8669 11:32:39.695016 arm64_sve-ptrace_Set_SVE_VL_96 pass
8670 11:32:39.695128 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8671 11:32:39.695217 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8672 11:32:39.695314 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8673 11:32:39.695616 arm64_sve-ptrace_Set_SVE_VL_112 pass
8674 11:32:39.695722 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8675 11:32:39.695825 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8676 11:32:39.696123 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8677 11:32:39.696228 arm64_sve-ptrace_Set_SVE_VL_128 pass
8678 11:32:39.696332 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8679 11:32:39.696434 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8680 11:32:39.696735 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8681 11:32:39.696850 arm64_sve-ptrace_Set_SVE_VL_144 pass
8682 11:32:39.697139 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8683 11:32:39.697243 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8684 11:32:39.697345 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8685 11:32:39.697443 arm64_sve-ptrace_Set_SVE_VL_160 pass
8686 11:32:39.697543 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8687 11:32:39.697843 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8688 11:32:39.697949 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8689 11:32:39.698247 arm64_sve-ptrace_Set_SVE_VL_176 pass
8690 11:32:39.698355 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8691 11:32:39.698441 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8692 11:32:39.702644 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8693 11:32:39.702850 arm64_sve-ptrace_Set_SVE_VL_192 pass
8694 11:32:39.702960 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8695 11:32:39.703053 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8696 11:32:39.703160 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8697 11:32:39.703250 arm64_sve-ptrace_Set_SVE_VL_208 pass
8698 11:32:39.703366 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8699 11:32:39.703673 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8700 11:32:39.703793 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8701 11:32:39.703902 arm64_sve-ptrace_Set_SVE_VL_224 pass
8702 11:32:39.704003 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8703 11:32:39.704291 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8704 11:32:39.704402 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8705 11:32:39.704503 arm64_sve-ptrace_Set_SVE_VL_240 pass
8706 11:32:39.704791 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8707 11:32:39.704898 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8708 11:32:39.705185 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8709 11:32:39.705289 arm64_sve-ptrace_Set_SVE_VL_256 pass
8710 11:32:39.705575 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8711 11:32:39.705678 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8712 11:32:39.705980 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8713 11:32:39.706084 arm64_sve-ptrace_Set_SVE_VL_272 pass
8714 11:32:39.706186 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8715 11:32:39.710411 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8716 11:32:39.710847 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8717 11:32:39.710947 arm64_sve-ptrace_Set_SVE_VL_288 pass
8718 11:32:39.711023 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8719 11:32:39.711109 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8720 11:32:39.711185 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8721 11:32:39.711273 arm64_sve-ptrace_Set_SVE_VL_304 pass
8722 11:32:39.711376 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8723 11:32:39.711666 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8724 11:32:39.711773 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8725 11:32:39.712056 arm64_sve-ptrace_Set_SVE_VL_320 pass
8726 11:32:39.712157 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8727 11:32:39.712257 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8728 11:32:39.712557 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8729 11:32:39.712659 arm64_sve-ptrace_Set_SVE_VL_336 pass
8730 11:32:39.712751 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8731 11:32:39.712840 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8732 11:32:39.713127 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8733 11:32:39.713228 arm64_sve-ptrace_Set_SVE_VL_352 pass
8734 11:32:39.713321 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8735 11:32:39.713607 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8736 11:32:39.713720 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8737 11:32:39.713829 arm64_sve-ptrace_Set_SVE_VL_368 pass
8738 11:32:39.713902 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8739 11:32:39.714193 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8740 11:32:39.714300 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8741 11:32:39.718657 arm64_sve-ptrace_Set_SVE_VL_384 pass
8742 11:32:39.718878 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8743 11:32:39.718975 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8744 11:32:39.719080 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8745 11:32:39.719182 arm64_sve-ptrace_Set_SVE_VL_400 pass
8746 11:32:39.719282 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8747 11:32:39.719598 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8748 11:32:39.719704 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8749 11:32:39.719801 arm64_sve-ptrace_Set_SVE_VL_416 pass
8750 11:32:39.719891 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8751 11:32:39.719981 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8752 11:32:39.720187 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8753 11:32:39.720303 arm64_sve-ptrace_Set_SVE_VL_432 pass
8754 11:32:39.720392 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
8755 11:32:39.720669 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
8756 11:32:39.720788 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
8757 11:32:39.720872 arm64_sve-ptrace_Set_SVE_VL_448 pass
8758 11:32:39.720977 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
8759 11:32:39.721289 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
8760 11:32:39.739097 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
8761 11:32:39.739586 arm64_sve-ptrace_Set_SVE_VL_464 pass
8762 11:32:39.739851 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
8763 11:32:39.740112 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
8764 11:32:39.740311 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
8765 11:32:39.740490 arm64_sve-ptrace_Set_SVE_VL_480 pass
8766 11:32:39.740621 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
8767 11:32:39.740747 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
8768 11:32:39.740874 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
8769 11:32:39.741021 arm64_sve-ptrace_Set_SVE_VL_496 pass
8770 11:32:39.741172 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
8771 11:32:39.741330 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
8772 11:32:39.741497 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
8773 11:32:39.741665 arm64_sve-ptrace_Set_SVE_VL_512 pass
8774 11:32:39.741800 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
8775 11:32:39.741924 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
8776 11:32:39.742052 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
8777 11:32:39.742177 arm64_sve-ptrace_Set_SVE_VL_528 pass
8778 11:32:39.742308 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
8779 11:32:39.742406 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
8780 11:32:39.742475 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
8781 11:32:39.742544 arm64_sve-ptrace_Set_SVE_VL_544 pass
8782 11:32:39.742612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
8783 11:32:39.746363 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
8784 11:32:39.746800 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
8785 11:32:39.746909 arm64_sve-ptrace_Set_SVE_VL_560 pass
8786 11:32:39.746998 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
8787 11:32:39.747103 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
8788 11:32:39.747208 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
8789 11:32:39.747292 arm64_sve-ptrace_Set_SVE_VL_576 pass
8790 11:32:39.747394 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
8791 11:32:39.747691 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
8792 11:32:39.747809 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
8793 11:32:39.748099 arm64_sve-ptrace_Set_SVE_VL_592 pass
8794 11:32:39.748207 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
8795 11:32:39.748308 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
8796 11:32:39.748601 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
8797 11:32:39.748715 arm64_sve-ptrace_Set_SVE_VL_608 pass
8798 11:32:39.748809 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
8799 11:32:39.748919 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
8800 11:32:39.749243 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
8801 11:32:39.749555 arm64_sve-ptrace_Set_SVE_VL_624 pass
8802 11:32:39.749664 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
8803 11:32:39.749751 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
8804 11:32:39.750047 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
8805 11:32:39.750152 arm64_sve-ptrace_Set_SVE_VL_640 pass
8806 11:32:39.750239 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
8807 11:32:39.750325 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
8808 11:32:39.750412 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
8809 11:32:39.750512 arm64_sve-ptrace_Set_SVE_VL_656 pass
8810 11:32:39.754493 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
8811 11:32:39.754927 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
8812 11:32:39.755039 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
8813 11:32:39.755132 arm64_sve-ptrace_Set_SVE_VL_672 pass
8814 11:32:39.755233 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
8815 11:32:39.755319 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
8816 11:32:39.755421 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
8817 11:32:39.755522 arm64_sve-ptrace_Set_SVE_VL_688 pass
8818 11:32:39.755618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
8819 11:32:39.755918 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
8820 11:32:39.756035 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
8821 11:32:39.756137 arm64_sve-ptrace_Set_SVE_VL_704 pass
8822 11:32:39.756236 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
8823 11:32:39.756337 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
8824 11:32:39.756628 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
8825 11:32:39.756723 arm64_sve-ptrace_Set_SVE_VL_720 pass
8826 11:32:39.756824 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
8827 11:32:39.756922 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
8828 11:32:39.757021 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
8829 11:32:39.757318 arm64_sve-ptrace_Set_SVE_VL_736 pass
8830 11:32:39.757423 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
8831 11:32:39.757525 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
8832 11:32:39.757624 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
8833 11:32:39.757731 arm64_sve-ptrace_Set_SVE_VL_752 pass
8834 11:32:39.758028 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
8835 11:32:39.758131 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
8836 11:32:39.762365 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
8837 11:32:39.762812 arm64_sve-ptrace_Set_SVE_VL_768 pass
8838 11:32:39.762922 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
8839 11:32:39.763010 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
8840 11:32:39.763112 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
8841 11:32:39.763205 arm64_sve-ptrace_Set_SVE_VL_784 pass
8842 11:32:39.763306 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
8843 11:32:39.763407 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
8844 11:32:39.763687 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
8845 11:32:39.763781 arm64_sve-ptrace_Set_SVE_VL_800 pass
8846 11:32:39.763867 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
8847 11:32:39.763951 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
8848 11:32:39.764240 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
8849 11:32:39.764350 arm64_sve-ptrace_Set_SVE_VL_816 pass
8850 11:32:39.764455 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
8851 11:32:39.764557 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
8852 11:32:39.764859 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
8853 11:32:39.764965 arm64_sve-ptrace_Set_SVE_VL_832 pass
8854 11:32:39.765067 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
8855 11:32:39.765170 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
8856 11:32:39.765280 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
8857 11:32:39.765382 arm64_sve-ptrace_Set_SVE_VL_848 pass
8858 11:32:39.765701 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
8859 11:32:39.766013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
8860 11:32:39.766119 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
8861 11:32:39.766207 arm64_sve-ptrace_Set_SVE_VL_864 pass
8862 11:32:39.770395 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
8863 11:32:39.770816 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
8864 11:32:39.770923 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
8865 11:32:39.771009 arm64_sve-ptrace_Set_SVE_VL_880 pass
8866 11:32:39.771109 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
8867 11:32:39.771216 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
8868 11:32:39.771319 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
8869 11:32:39.771427 arm64_sve-ptrace_Set_SVE_VL_896 pass
8870 11:32:39.771716 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
8871 11:32:39.771819 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
8872 11:32:39.772098 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
8873 11:32:39.772193 arm64_sve-ptrace_Set_SVE_VL_912 pass
8874 11:32:39.772284 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
8875 11:32:39.772374 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
8876 11:32:39.772462 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
8877 11:32:39.772680 arm64_sve-ptrace_Set_SVE_VL_928 pass
8878 11:32:39.772798 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
8879 11:32:39.772900 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
8880 11:32:39.773201 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
8881 11:32:39.773289 arm64_sve-ptrace_Set_SVE_VL_944 pass
8882 11:32:39.773416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
8883 11:32:39.773530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
8884 11:32:39.773632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
8885 11:32:39.773750 arm64_sve-ptrace_Set_SVE_VL_960 pass
8886 11:32:39.774057 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
8887 11:32:39.774165 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
8888 11:32:39.778346 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
8889 11:32:39.778761 arm64_sve-ptrace_Set_SVE_VL_976 pass
8890 11:32:39.778858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
8891 11:32:39.778932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
8892 11:32:39.779015 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
8893 11:32:39.779100 arm64_sve-ptrace_Set_SVE_VL_992 pass
8894 11:32:39.779309 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
8895 11:32:39.779421 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
8896 11:32:39.779507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
8897 11:32:39.779780 arm64_sve-ptrace_Set_SVE_VL_1008 pass
8898 11:32:39.779874 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
8899 11:32:39.779959 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
8900 11:32:39.780044 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
8901 11:32:39.780221 arm64_sve-ptrace_Set_SVE_VL_1024 pass
8902 11:32:39.780327 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
8903 11:32:39.780487 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
8904 11:32:39.780601 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
8905 11:32:39.780883 arm64_sve-ptrace_Set_SVE_VL_1040 pass
8906 11:32:39.780987 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
8907 11:32:39.781073 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
8908 11:32:39.781353 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
8909 11:32:39.781449 arm64_sve-ptrace_Set_SVE_VL_1056 pass
8910 11:32:39.781547 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
8911 11:32:39.781655 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
8912 11:32:39.781953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
8913 11:32:39.782074 arm64_sve-ptrace_Set_SVE_VL_1072 pass
8914 11:32:39.782164 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
8915 11:32:39.786347 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
8916 11:32:39.786777 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
8917 11:32:39.786883 arm64_sve-ptrace_Set_SVE_VL_1088 pass
8918 11:32:39.786967 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
8919 11:32:39.787044 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
8920 11:32:39.787108 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
8921 11:32:39.787186 arm64_sve-ptrace_Set_SVE_VL_1104 pass
8922 11:32:39.799920 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
8923 11:32:39.800375 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
8924 11:32:39.800487 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
8925 11:32:39.800579 arm64_sve-ptrace_Set_SVE_VL_1120 pass
8926 11:32:39.800684 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
8927 11:32:39.800775 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
8928 11:32:39.800880 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
8929 11:32:39.800969 arm64_sve-ptrace_Set_SVE_VL_1136 pass
8930 11:32:39.801072 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
8931 11:32:39.801359 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
8932 11:32:39.801472 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
8933 11:32:39.801762 arm64_sve-ptrace_Set_SVE_VL_1152 pass
8934 11:32:39.801873 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
8935 11:32:39.801963 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
8936 11:32:39.802066 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
8937 11:32:39.802350 arm64_sve-ptrace_Set_SVE_VL_1168 pass
8938 11:32:39.802445 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
8939 11:32:39.802741 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
8940 11:32:39.802835 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
8941 11:32:39.802935 arm64_sve-ptrace_Set_SVE_VL_1184 pass
8942 11:32:39.803039 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
8943 11:32:39.803344 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
8944 11:32:39.803450 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
8945 11:32:39.803553 arm64_sve-ptrace_Set_SVE_VL_1200 pass
8946 11:32:39.803685 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
8947 11:32:39.804010 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
8948 11:32:39.804131 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
8949 11:32:39.804238 arm64_sve-ptrace_Set_SVE_VL_1216 pass
8950 11:32:39.804532 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
8951 11:32:39.804641 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
8952 11:32:39.804743 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
8953 11:32:39.805033 arm64_sve-ptrace_Set_SVE_VL_1232 pass
8954 11:32:39.805140 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
8955 11:32:39.805241 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
8956 11:32:39.805857 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
8957 11:32:39.805967 arm64_sve-ptrace_Set_SVE_VL_1248 pass
8958 11:32:39.806053 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
8959 11:32:39.806336 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
8960 11:32:39.806440 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
8961 11:32:39.806529 arm64_sve-ptrace_Set_SVE_VL_1264 pass
8962 11:32:39.810422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
8963 11:32:39.810870 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
8964 11:32:39.810987 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
8965 11:32:39.811098 arm64_sve-ptrace_Set_SVE_VL_1280 pass
8966 11:32:39.811196 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
8967 11:32:39.811295 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
8968 11:32:39.811391 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
8969 11:32:39.811490 arm64_sve-ptrace_Set_SVE_VL_1296 pass
8970 11:32:39.811786 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
8971 11:32:39.811905 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
8972 11:32:39.812014 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
8973 11:32:39.812306 arm64_sve-ptrace_Set_SVE_VL_1312 pass
8974 11:32:39.812418 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
8975 11:32:39.812521 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
8976 11:32:39.812819 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
8977 11:32:39.812925 arm64_sve-ptrace_Set_SVE_VL_1328 pass
8978 11:32:39.813026 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
8979 11:32:39.813311 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
8980 11:32:39.813418 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
8981 11:32:39.813515 arm64_sve-ptrace_Set_SVE_VL_1344 pass
8982 11:32:39.813614 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
8983 11:32:39.813733 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
8984 11:32:39.814041 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
8985 11:32:39.814149 arm64_sve-ptrace_Set_SVE_VL_1360 pass
8986 11:32:39.814250 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
8987 11:32:39.818587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
8988 11:32:39.818792 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
8989 11:32:39.818870 arm64_sve-ptrace_Set_SVE_VL_1376 pass
8990 11:32:39.818962 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
8991 11:32:39.819256 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
8992 11:32:39.819378 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
8993 11:32:39.819484 arm64_sve-ptrace_Set_SVE_VL_1392 pass
8994 11:32:39.819776 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
8995 11:32:39.819883 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
8996 11:32:39.819987 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
8997 11:32:39.820279 arm64_sve-ptrace_Set_SVE_VL_1408 pass
8998 11:32:39.820375 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
8999 11:32:39.820476 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9000 11:32:39.820769 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9001 11:32:39.820865 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9002 11:32:39.821165 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9003 11:32:39.821272 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9004 11:32:39.821377 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9005 11:32:39.821481 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9006 11:32:39.821785 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9007 11:32:39.821906 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9008 11:32:39.822007 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9009 11:32:39.822106 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9010 11:32:39.830399 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9011 11:32:39.830858 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9012 11:32:39.830947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9013 11:32:39.831041 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9014 11:32:39.831139 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9015 11:32:39.831224 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9016 11:32:39.831341 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9017 11:32:39.831430 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9018 11:32:39.831533 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9019 11:32:39.831835 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9020 11:32:39.831951 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9021 11:32:39.832055 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9022 11:32:39.832156 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9023 11:32:39.832461 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9024 11:32:39.832569 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9025 11:32:39.832669 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9026 11:32:39.832756 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9027 11:32:39.832853 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9028 11:32:39.833151 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9029 11:32:39.833257 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9030 11:32:39.833356 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9031 11:32:39.833454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9032 11:32:39.833556 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9033 11:32:39.833862 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9034 11:32:39.833966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9035 11:32:39.834066 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9036 11:32:39.834165 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9037 11:32:39.838509 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9038 11:32:39.838682 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9039 11:32:39.838937 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9040 11:32:39.839003 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9041 11:32:39.839212 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9042 11:32:39.839310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9043 11:32:39.839616 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9044 11:32:39.839721 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9045 11:32:39.839810 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9046 11:32:39.839912 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9047 11:32:39.840001 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9048 11:32:39.840104 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9049 11:32:39.840194 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9050 11:32:39.840297 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9051 11:32:39.840401 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9052 11:32:39.840508 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9053 11:32:39.840825 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9054 11:32:39.840933 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9055 11:32:39.841038 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9056 11:32:39.841144 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9057 11:32:39.841248 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9058 11:32:39.841350 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9059 11:32:39.841665 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9060 11:32:39.841786 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9061 11:32:39.841875 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9062 11:32:39.841974 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9063 11:32:39.842270 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9064 11:32:39.846308 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9065 11:32:39.846670 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9066 11:32:39.846775 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9067 11:32:39.846879 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9068 11:32:39.846982 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9069 11:32:39.847084 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9070 11:32:39.847186 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9071 11:32:39.847289 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9072 11:32:39.847592 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9073 11:32:39.847699 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9074 11:32:39.847802 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9075 11:32:39.847904 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9076 11:32:39.848008 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9077 11:32:39.848224 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9078 11:32:39.848534 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9079 11:32:39.848640 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9080 11:32:39.848747 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9081 11:32:39.848834 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9082 11:32:39.860247 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9083 11:32:39.860705 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9084 11:32:39.860791 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9085 11:32:39.860885 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9086 11:32:39.860982 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9087 11:32:39.861057 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9088 11:32:39.861147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9089 11:32:39.861475 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9090 11:32:39.861579 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9091 11:32:39.862089 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9092 11:32:39.862162 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9093 11:32:39.862399 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9094 11:32:39.862464 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9095 11:32:39.862525 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9096 11:32:39.862586 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9097 11:32:39.862656 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9098 11:32:39.863011 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9099 11:32:39.863077 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9100 11:32:39.863137 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9101 11:32:39.863392 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9102 11:32:39.863473 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9103 11:32:39.863536 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9104 11:32:39.863608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9105 11:32:39.863681 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9106 11:32:39.863978 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9107 11:32:39.864082 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9108 11:32:39.864184 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9109 11:32:39.864285 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9110 11:32:39.864571 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9111 11:32:39.864680 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9112 11:32:39.864933 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9113 11:32:39.865000 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9114 11:32:39.865072 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9115 11:32:39.865321 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9116 11:32:39.865409 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9117 11:32:39.865669 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9118 11:32:39.865749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9119 11:32:39.865824 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9120 11:32:39.866093 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9121 11:32:39.866218 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9122 11:32:39.870586 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9123 11:32:39.870791 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9124 11:32:39.870900 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9125 11:32:39.871008 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9126 11:32:39.871097 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9127 11:32:39.871197 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9128 11:32:39.871300 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9129 11:32:39.871606 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9130 11:32:39.871726 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9131 11:32:39.871829 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9132 11:32:39.871928 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9133 11:32:39.872228 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9134 11:32:39.872329 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9135 11:32:39.872428 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9136 11:32:39.872525 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9137 11:32:39.872812 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9138 11:32:39.872927 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9139 11:32:39.873029 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9140 11:32:39.873325 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9141 11:32:39.873431 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9142 11:32:39.873531 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9143 11:32:39.873831 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9144 11:32:39.873934 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9145 11:32:39.874032 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9146 11:32:39.874115 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9147 11:32:39.878353 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9148 11:32:39.878768 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9149 11:32:39.878875 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9150 11:32:39.878963 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9151 11:32:39.879073 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9152 11:32:39.879162 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9153 11:32:39.879248 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9154 11:32:39.879350 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9155 11:32:39.879453 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9156 11:32:39.879558 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9157 11:32:39.879867 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9158 11:32:39.879970 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9159 11:32:39.880069 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9160 11:32:39.880371 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9161 11:32:39.880479 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9162 11:32:39.880582 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9163 11:32:39.880690 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9164 11:32:39.880999 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9165 11:32:39.881104 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9166 11:32:39.881206 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9167 11:32:39.881494 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9168 11:32:39.881592 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9169 11:32:39.881690 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9170 11:32:39.881777 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9171 11:32:39.882069 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9172 11:32:39.882193 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9173 11:32:39.886415 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9174 11:32:39.886857 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9175 11:32:39.886966 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9176 11:32:39.887066 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9177 11:32:39.887153 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9178 11:32:39.887251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9179 11:32:39.887556 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9180 11:32:39.887662 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9181 11:32:39.887756 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9182 11:32:39.887840 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9183 11:32:39.888121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9184 11:32:39.888216 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9185 11:32:39.888309 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9186 11:32:39.888589 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9187 11:32:39.888672 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9188 11:32:39.888930 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9189 11:32:39.888997 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9190 11:32:39.889080 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9191 11:32:39.889174 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9192 11:32:39.889424 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9193 11:32:39.889507 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9194 11:32:39.889752 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9195 11:32:39.889841 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9196 11:32:39.890088 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9197 11:32:39.890329 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9198 11:32:39.898594 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9199 11:32:39.899052 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9200 11:32:39.899164 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9201 11:32:39.899277 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9202 11:32:39.899409 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9203 11:32:39.899522 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9204 11:32:39.899654 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9205 11:32:39.899760 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9206 11:32:39.899888 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9207 11:32:39.900210 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9208 11:32:39.900313 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9209 11:32:39.900416 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9210 11:32:39.900505 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9211 11:32:39.900607 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9212 11:32:39.900694 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9213 11:32:39.900794 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9214 11:32:39.901088 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9215 11:32:39.901182 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9216 11:32:39.901252 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9217 11:32:39.901355 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9218 11:32:39.901455 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9219 11:32:39.901749 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9220 11:32:39.901854 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9221 11:32:39.901941 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9222 11:32:39.902215 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9223 11:32:39.906445 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9224 11:32:39.906853 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9225 11:32:39.906956 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9226 11:32:39.907048 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9227 11:32:39.907153 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9228 11:32:39.907241 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9229 11:32:39.907346 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9230 11:32:39.907445 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9231 11:32:39.907762 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9232 11:32:39.907870 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9233 11:32:39.907972 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9234 11:32:39.908272 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9235 11:32:39.908378 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9236 11:32:39.908478 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9237 11:32:39.908580 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9238 11:32:39.908683 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9239 11:32:39.908982 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9240 11:32:39.909288 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9241 11:32:39.909384 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9242 11:32:39.922709 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9243 11:32:39.923180 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9244 11:32:39.923296 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9245 11:32:39.923385 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9246 11:32:39.923469 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9247 11:32:39.923576 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9248 11:32:39.923662 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9249 11:32:39.923763 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9250 11:32:39.923864 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9251 11:32:39.924169 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9252 11:32:39.924292 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9253 11:32:39.924396 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9254 11:32:39.924703 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9255 11:32:39.924819 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9256 11:32:39.924949 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9257 11:32:39.925065 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9258 11:32:39.925176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9259 11:32:39.925487 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9260 11:32:39.925605 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9261 11:32:39.925719 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9262 11:32:39.926020 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9263 11:32:39.926113 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9264 11:32:39.930436 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9265 11:32:39.930852 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9266 11:32:39.930951 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9267 11:32:39.931036 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9268 11:32:39.931129 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9269 11:32:39.931211 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9270 11:32:39.931307 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9271 11:32:39.931405 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9272 11:32:39.931702 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9273 11:32:39.931814 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9274 11:32:39.931918 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9275 11:32:39.932210 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9276 11:32:39.932314 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9277 11:32:39.932403 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9278 11:32:39.932506 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9279 11:32:39.932595 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9280 11:32:39.932696 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9281 11:32:39.932788 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9282 11:32:39.932888 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9283 11:32:39.933199 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9284 11:32:39.933310 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9285 11:32:39.933412 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9286 11:32:39.933515 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9287 11:32:39.933821 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9288 11:32:39.933931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9289 11:32:39.934020 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9290 11:32:39.934123 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9291 11:32:39.938361 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9292 11:32:39.938797 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9293 11:32:39.938900 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9294 11:32:39.938978 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9295 11:32:39.939066 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9296 11:32:39.939156 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9297 11:32:39.939239 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9298 11:32:39.939326 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9299 11:32:39.939414 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9300 11:32:39.939508 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9301 11:32:39.939822 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9302 11:32:39.939923 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9303 11:32:39.940027 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9304 11:32:39.940348 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9305 11:32:39.940455 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9306 11:32:39.940543 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9307 11:32:39.940631 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9308 11:32:39.940694 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9309 11:32:39.940766 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9310 11:32:39.941072 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9311 11:32:39.941196 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9312 11:32:39.941301 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9313 11:32:39.941401 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9314 11:32:39.941698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9315 11:32:39.941804 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9316 11:32:39.941904 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9317 11:32:39.942004 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9318 11:32:39.942303 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9319 11:32:39.946360 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9320 11:32:39.946788 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9321 11:32:39.946898 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9322 11:32:39.946990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9323 11:32:39.947098 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9324 11:32:39.947192 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9325 11:32:39.947293 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9326 11:32:39.947382 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9327 11:32:39.947492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9328 11:32:39.947596 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9329 11:32:39.947697 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9330 11:32:39.948025 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9331 11:32:39.948131 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9332 11:32:39.948233 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9333 11:32:39.948320 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9334 11:32:39.948419 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9335 11:32:39.948519 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9336 11:32:39.948824 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9337 11:32:39.948927 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9338 11:32:39.949026 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9339 11:32:39.949125 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9340 11:32:39.949221 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9341 11:32:39.949517 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9342 11:32:39.949620 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9343 11:32:39.949732 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9344 11:32:39.949831 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9345 11:32:39.949929 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9346 11:32:39.950027 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9347 11:32:39.950126 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9348 11:32:39.954364 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9349 11:32:39.954791 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9350 11:32:39.954886 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9351 11:32:39.954973 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9352 11:32:39.955046 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9353 11:32:39.955129 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9354 11:32:39.955408 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9355 11:32:39.955503 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9356 11:32:39.955772 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9357 11:32:39.955875 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9358 11:32:39.955979 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9359 11:32:39.956082 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9360 11:32:39.956385 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9361 11:32:39.956488 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9362 11:32:39.956591 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9363 11:32:39.956692 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9364 11:32:39.956794 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9365 11:32:39.957097 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9366 11:32:39.957200 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9367 11:32:39.957304 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9368 11:32:39.957405 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9369 11:32:39.957508 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9370 11:32:39.957881 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9371 11:32:39.957985 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9372 11:32:39.958271 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9373 11:32:39.958374 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9374 11:32:39.958460 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9375 11:32:39.962601 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9376 11:32:39.962813 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9377 11:32:39.962928 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9378 11:32:39.963229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9379 11:32:39.963334 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9380 11:32:39.963437 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9381 11:32:39.963730 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9382 11:32:39.963836 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9383 11:32:39.963935 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9384 11:32:39.964011 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9385 11:32:39.964112 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9386 11:32:39.964198 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9387 11:32:39.964303 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9388 11:32:39.964393 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9389 11:32:39.964468 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9390 11:32:39.964825 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9391 11:32:39.964931 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9392 11:32:39.965033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9393 11:32:39.965120 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9394 11:32:39.965419 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9395 11:32:39.965521 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9396 11:32:39.965618 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9397 11:32:39.965714 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9398 11:32:39.965810 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9399 11:32:39.965914 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9400 11:32:39.966214 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9401 11:32:39.966320 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9402 11:32:39.984433 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9403 11:32:39.984867 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9404 11:32:39.984946 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9405 11:32:39.985018 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9406 11:32:39.985108 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9407 11:32:39.985196 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9408 11:32:39.985490 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9409 11:32:39.985578 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9410 11:32:39.985699 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9411 11:32:39.985777 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9412 11:32:39.985852 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9413 11:32:39.986168 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9414 11:32:39.986290 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9415 11:32:39.986585 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9416 11:32:39.986695 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9417 11:32:39.986799 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9418 11:32:39.987099 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9419 11:32:39.987204 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9420 11:32:39.987305 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9421 11:32:39.987406 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9422 11:32:39.987504 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9423 11:32:39.987801 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9424 11:32:39.987927 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9425 11:32:39.988018 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9426 11:32:39.988124 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9427 11:32:39.988427 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9428 11:32:39.988522 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9429 11:32:39.988623 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9430 11:32:39.988711 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9431 11:32:39.988815 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9432 11:32:39.989291 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9433 11:32:39.989389 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9434 11:32:39.989479 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9435 11:32:39.989566 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9436 11:32:39.989866 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9437 11:32:39.989975 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9438 11:32:39.990064 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9439 11:32:39.990167 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9440 11:32:39.990257 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9441 11:32:39.990342 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9442 11:32:39.994481 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9443 11:32:39.994909 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9444 11:32:39.995013 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9445 11:32:39.995104 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9446 11:32:39.995206 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9447 11:32:39.995296 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9448 11:32:39.995397 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9449 11:32:39.995701 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9450 11:32:39.995807 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9451 11:32:39.995912 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9452 11:32:39.995998 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9453 11:32:39.996094 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9454 11:32:39.996192 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9455 11:32:39.996295 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9456 11:32:39.996596 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9457 11:32:39.996699 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9458 11:32:39.996800 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9459 11:32:39.996898 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9460 11:32:39.997198 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9461 11:32:39.997301 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9462 11:32:39.997405 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9463 11:32:39.997494 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9464 11:32:39.997595 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9465 11:32:39.997707 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9466 11:32:39.998021 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9467 11:32:39.998309 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9468 11:32:40.002484 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9469 11:32:40.002891 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9470 11:32:40.002994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9471 11:32:40.003080 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9472 11:32:40.003181 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9473 11:32:40.003265 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9474 11:32:40.003365 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9475 11:32:40.003460 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9476 11:32:40.003759 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9477 11:32:40.003863 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9478 11:32:40.003972 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9479 11:32:40.004076 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9480 11:32:40.004183 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9481 11:32:40.004299 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9482 11:32:40.004745 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9483 11:32:40.004829 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9484 11:32:40.004905 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9485 11:32:40.004979 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9486 11:32:40.005230 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9487 11:32:40.005306 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9488 11:32:40.005555 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9489 11:32:40.005631 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9490 11:32:40.005750 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9491 11:32:40.006058 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9492 11:32:40.006161 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9493 11:32:40.010496 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9494 11:32:40.010889 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9495 11:32:40.010975 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9496 11:32:40.011048 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9497 11:32:40.011131 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9498 11:32:40.011216 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9499 11:32:40.011560 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9500 11:32:40.011678 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9501 11:32:40.011761 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9502 11:32:40.012048 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9503 11:32:40.012154 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9504 11:32:40.012254 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9505 11:32:40.012555 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9506 11:32:40.012654 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9507 11:32:40.012747 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9508 11:32:40.012834 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9509 11:32:40.013125 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9510 11:32:40.013240 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9511 11:32:40.013342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9512 11:32:40.013641 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9513 11:32:40.013750 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9514 11:32:40.013843 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9515 11:32:40.013946 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9516 11:32:40.014249 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9517 11:32:40.018498 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9518 11:32:40.018927 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9519 11:32:40.019028 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9520 11:32:40.019131 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9521 11:32:40.019219 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9522 11:32:40.019520 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9523 11:32:40.019634 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9524 11:32:40.019743 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9525 11:32:40.020033 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9526 11:32:40.020139 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9527 11:32:40.020444 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9528 11:32:40.020758 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9529 11:32:40.020857 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9530 11:32:40.020957 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9531 11:32:40.021048 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9532 11:32:40.021163 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9533 11:32:40.021470 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9534 11:32:40.021746 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9535 11:32:40.021843 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9536 11:32:40.021945 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9537 11:32:40.022031 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9538 11:32:40.022129 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9539 11:32:40.026501 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9540 11:32:40.026951 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9541 11:32:40.027071 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9542 11:32:40.027160 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9543 11:32:40.027259 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9544 11:32:40.027362 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9545 11:32:40.027471 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9546 11:32:40.027763 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9547 11:32:40.028061 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9548 11:32:40.028156 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9549 11:32:40.028256 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9550 11:32:40.028514 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9551 11:32:40.028618 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9552 11:32:40.028899 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9553 11:32:40.028972 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9554 11:32:40.029045 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9555 11:32:40.029293 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9556 11:32:40.029359 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9557 11:32:40.029456 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9558 11:32:40.029557 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9559 11:32:40.029846 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9560 11:32:40.030103 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9561 11:32:40.030171 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9562 11:32:40.049601 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9563 11:32:40.049865 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9564 11:32:40.050170 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9565 11:32:40.050265 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9566 11:32:40.050353 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9567 11:32:40.050454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9568 11:32:40.050557 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9569 11:32:40.050657 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9570 11:32:40.050950 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9571 11:32:40.051270 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9572 11:32:40.051370 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9573 11:32:40.051459 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9574 11:32:40.051550 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9575 11:32:40.051817 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9576 11:32:40.052083 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9577 11:32:40.052169 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9578 11:32:40.052267 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9579 11:32:40.052567 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9580 11:32:40.052667 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9581 11:32:40.052758 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9582 11:32:40.052851 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9583 11:32:40.053150 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9584 11:32:40.053253 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9585 11:32:40.053353 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9586 11:32:40.053644 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9587 11:32:40.053764 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9588 11:32:40.054044 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9589 11:32:40.054135 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9590 11:32:40.054232 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9591 11:32:40.058751 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9592 11:32:40.059182 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9593 11:32:40.059277 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9594 11:32:40.059361 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9595 11:32:40.059446 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9596 11:32:40.059545 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9597 11:32:40.059629 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9598 11:32:40.059726 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9599 11:32:40.059825 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9600 11:32:40.060118 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9601 11:32:40.060224 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9602 11:32:40.060318 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9603 11:32:40.060608 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9604 11:32:40.060712 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9605 11:32:40.061003 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9606 11:32:40.061108 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9607 11:32:40.061206 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9608 11:32:40.061490 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9609 11:32:40.061581 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9610 11:32:40.061874 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9611 11:32:40.061969 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9612 11:32:40.062077 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9613 11:32:40.062180 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9614 11:32:40.066666 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9615 11:32:40.067109 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9616 11:32:40.067214 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9617 11:32:40.067306 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9618 11:32:40.067398 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9619 11:32:40.067470 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9620 11:32:40.067560 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9621 11:32:40.067643 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9622 11:32:40.067926 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9623 11:32:40.068028 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9624 11:32:40.068112 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9625 11:32:40.068391 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9626 11:32:40.068482 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9627 11:32:40.068566 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9628 11:32:40.068830 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9629 11:32:40.068905 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9630 11:32:40.069165 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9631 11:32:40.069240 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9632 11:32:40.069327 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9633 11:32:40.069604 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9634 11:32:40.069701 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9635 11:32:40.069963 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9636 11:32:40.070050 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9637 11:32:40.070319 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9638 11:32:40.074542 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9639 11:32:40.074961 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9640 11:32:40.075040 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9641 11:32:40.075113 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9642 11:32:40.075198 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9643 11:32:40.075505 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9644 11:32:40.075621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9645 11:32:40.075725 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9646 11:32:40.076022 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9647 11:32:40.076139 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9648 11:32:40.076429 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9649 11:32:40.076523 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9650 11:32:40.076620 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9651 11:32:40.076723 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9652 11:32:40.077013 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9653 11:32:40.077124 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9654 11:32:40.077413 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9655 11:32:40.077520 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9656 11:32:40.077618 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9657 11:32:40.077740 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9658 11:32:40.078051 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9659 11:32:40.078172 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9660 11:32:40.082539 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9661 11:32:40.082932 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9662 11:32:40.083032 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9663 11:32:40.083106 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9664 11:32:40.083181 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9665 11:32:40.083277 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9666 11:32:40.083382 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9667 11:32:40.083689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9668 11:32:40.083980 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9669 11:32:40.084097 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9670 11:32:40.084184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9671 11:32:40.084289 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9672 11:32:40.084390 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9673 11:32:40.084489 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9674 11:32:40.084771 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9675 11:32:40.084862 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9676 11:32:40.084972 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9677 11:32:40.085287 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9678 11:32:40.085389 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9679 11:32:40.085491 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9680 11:32:40.085585 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9681 11:32:40.085680 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9682 11:32:40.085953 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9683 11:32:40.086066 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9684 11:32:40.090441 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9685 11:32:40.090876 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9686 11:32:40.090983 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9687 11:32:40.091070 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9688 11:32:40.091170 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9689 11:32:40.091258 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9690 11:32:40.091363 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9691 11:32:40.091465 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9692 11:32:40.091759 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9693 11:32:40.091854 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9694 11:32:40.091953 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9695 11:32:40.092077 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9696 11:32:40.092407 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9697 11:32:40.092511 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9698 11:32:40.092596 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9699 11:32:40.092865 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9700 11:32:40.092981 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9701 11:32:40.093083 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9702 11:32:40.093379 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9703 11:32:40.093672 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9704 11:32:40.093767 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9705 11:32:40.093851 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9706 11:32:40.093950 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9707 11:32:40.094244 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9708 11:32:40.098389 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9709 11:32:40.098807 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9710 11:32:40.098899 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9711 11:32:40.098963 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9712 11:32:40.099039 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9713 11:32:40.099119 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9714 11:32:40.099401 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9715 11:32:40.099513 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9716 11:32:40.099601 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9717 11:32:40.099683 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9718 11:32:40.099974 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9719 11:32:40.100083 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9720 11:32:40.100353 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9721 11:32:40.100429 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9722 11:32:40.112691 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9723 11:32:40.113155 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9724 11:32:40.113261 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9725 11:32:40.113349 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9726 11:32:40.113423 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9727 11:32:40.113499 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9728 11:32:40.113573 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9729 11:32:40.113664 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9730 11:32:40.113959 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9731 11:32:40.114061 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9732 11:32:40.114388 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9733 11:32:40.114505 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9734 11:32:40.114796 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9735 11:32:40.114891 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9736 11:32:40.114991 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9737 11:32:40.115290 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9738 11:32:40.115393 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9739 11:32:40.115504 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9740 11:32:40.115606 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9741 11:32:40.115907 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9742 11:32:40.116014 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9743 11:32:40.116118 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9744 11:32:40.116222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9745 11:32:40.116514 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9746 11:32:40.116616 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9747 11:32:40.116709 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9748 11:32:40.116809 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9749 11:32:40.117103 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9750 11:32:40.117204 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9751 11:32:40.117297 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9752 11:32:40.117394 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9753 11:32:40.117484 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9754 11:32:40.117583 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
9755 11:32:40.117816 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
9756 11:32:40.118134 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
9757 11:32:40.118235 arm64_sve-ptrace_Set_SVE_VL_4448 pass
9758 11:32:40.122332 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
9759 11:32:40.122723 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
9760 11:32:40.122818 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
9761 11:32:40.122905 arm64_sve-ptrace_Set_SVE_VL_4464 pass
9762 11:32:40.122991 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
9763 11:32:40.123277 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
9764 11:32:40.123400 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
9765 11:32:40.123492 arm64_sve-ptrace_Set_SVE_VL_4480 pass
9766 11:32:40.123592 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
9767 11:32:40.123698 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
9768 11:32:40.123804 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
9769 11:32:40.124112 arm64_sve-ptrace_Set_SVE_VL_4496 pass
9770 11:32:40.124213 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
9771 11:32:40.124321 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
9772 11:32:40.124629 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
9773 11:32:40.124731 arm64_sve-ptrace_Set_SVE_VL_4512 pass
9774 11:32:40.124829 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
9775 11:32:40.125129 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
9776 11:32:40.125237 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
9777 11:32:40.125337 arm64_sve-ptrace_Set_SVE_VL_4528 pass
9778 11:32:40.125435 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
9779 11:32:40.125697 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
9780 11:32:40.125810 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
9781 11:32:40.125890 arm64_sve-ptrace_Set_SVE_VL_4544 pass
9782 11:32:40.125977 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
9783 11:32:40.126265 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
9784 11:32:40.130365 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
9785 11:32:40.130760 arm64_sve-ptrace_Set_SVE_VL_4560 pass
9786 11:32:40.130853 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
9787 11:32:40.130927 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
9788 11:32:40.131012 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
9789 11:32:40.131085 arm64_sve-ptrace_Set_SVE_VL_4576 pass
9790 11:32:40.131373 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
9791 11:32:40.131495 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
9792 11:32:40.131600 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
9793 11:32:40.131700 arm64_sve-ptrace_Set_SVE_VL_4592 pass
9794 11:32:40.131998 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
9795 11:32:40.132117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
9796 11:32:40.132219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
9797 11:32:40.132520 arm64_sve-ptrace_Set_SVE_VL_4608 pass
9798 11:32:40.132638 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
9799 11:32:40.132740 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
9800 11:32:40.133036 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
9801 11:32:40.133141 arm64_sve-ptrace_Set_SVE_VL_4624 pass
9802 11:32:40.133240 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
9803 11:32:40.133540 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
9804 11:32:40.133660 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
9805 11:32:40.133761 arm64_sve-ptrace_Set_SVE_VL_4640 pass
9806 11:32:40.134049 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
9807 11:32:40.134153 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
9808 11:32:40.134255 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
9809 11:32:40.138380 arm64_sve-ptrace_Set_SVE_VL_4656 pass
9810 11:32:40.138805 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
9811 11:32:40.138914 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
9812 11:32:40.139018 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
9813 11:32:40.139105 arm64_sve-ptrace_Set_SVE_VL_4672 pass
9814 11:32:40.139203 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
9815 11:32:40.139304 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
9816 11:32:40.139403 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
9817 11:32:40.139506 arm64_sve-ptrace_Set_SVE_VL_4688 pass
9818 11:32:40.139814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
9819 11:32:40.139919 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
9820 11:32:40.140019 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
9821 11:32:40.140119 arm64_sve-ptrace_Set_SVE_VL_4704 pass
9822 11:32:40.140218 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
9823 11:32:40.140316 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
9824 11:32:40.140620 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
9825 11:32:40.140738 arm64_sve-ptrace_Set_SVE_VL_4720 pass
9826 11:32:40.140837 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
9827 11:32:40.141135 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
9828 11:32:40.141255 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
9829 11:32:40.141358 arm64_sve-ptrace_Set_SVE_VL_4736 pass
9830 11:32:40.141666 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
9831 11:32:40.141772 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
9832 11:32:40.141875 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
9833 11:32:40.141976 arm64_sve-ptrace_Set_SVE_VL_4752 pass
9834 11:32:40.142075 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
9835 11:32:40.146340 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
9836 11:32:40.146778 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
9837 11:32:40.146889 arm64_sve-ptrace_Set_SVE_VL_4768 pass
9838 11:32:40.146980 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
9839 11:32:40.147083 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
9840 11:32:40.147189 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
9841 11:32:40.147283 arm64_sve-ptrace_Set_SVE_VL_4784 pass
9842 11:32:40.147585 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
9843 11:32:40.147689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
9844 11:32:40.147790 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
9845 11:32:40.148082 arm64_sve-ptrace_Set_SVE_VL_4800 pass
9846 11:32:40.148167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
9847 11:32:40.148276 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
9848 11:32:40.148367 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
9849 11:32:40.148634 arm64_sve-ptrace_Set_SVE_VL_4816 pass
9850 11:32:40.148899 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
9851 11:32:40.148971 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
9852 11:32:40.149062 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
9853 11:32:40.149183 arm64_sve-ptrace_Set_SVE_VL_4832 pass
9854 11:32:40.149287 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
9855 11:32:40.149587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
9856 11:32:40.149713 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
9857 11:32:40.149824 arm64_sve-ptrace_Set_SVE_VL_4848 pass
9858 11:32:40.150125 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
9859 11:32:40.150234 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
9860 11:32:40.154354 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
9861 11:32:40.154777 arm64_sve-ptrace_Set_SVE_VL_4864 pass
9862 11:32:40.154872 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
9863 11:32:40.154950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
9864 11:32:40.155033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
9865 11:32:40.155116 arm64_sve-ptrace_Set_SVE_VL_4880 pass
9866 11:32:40.155207 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
9867 11:32:40.155443 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
9868 11:32:40.155572 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
9869 11:32:40.155694 arm64_sve-ptrace_Set_SVE_VL_4896 pass
9870 11:32:40.155808 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
9871 11:32:40.156000 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
9872 11:32:40.156123 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
9873 11:32:40.156235 arm64_sve-ptrace_Set_SVE_VL_4912 pass
9874 11:32:40.156341 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
9875 11:32:40.156643 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
9876 11:32:40.156751 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
9877 11:32:40.156854 arm64_sve-ptrace_Set_SVE_VL_4928 pass
9878 11:32:40.156931 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
9879 11:32:40.157207 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
9880 11:32:40.157296 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
9881 11:32:40.157404 arm64_sve-ptrace_Set_SVE_VL_4944 pass
9882 11:32:40.170830 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
9883 11:32:40.171293 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
9884 11:32:40.171401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
9885 11:32:40.171484 arm64_sve-ptrace_Set_SVE_VL_4960 pass
9886 11:32:40.171580 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
9887 11:32:40.171652 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
9888 11:32:40.171727 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
9889 11:32:40.171994 arm64_sve-ptrace_Set_SVE_VL_4976 pass
9890 11:32:40.172080 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
9891 11:32:40.172189 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
9892 11:32:40.172279 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
9893 11:32:40.172548 arm64_sve-ptrace_Set_SVE_VL_4992 pass
9894 11:32:40.172645 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
9895 11:32:40.172744 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
9896 11:32:40.173021 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
9897 11:32:40.173112 arm64_sve-ptrace_Set_SVE_VL_5008 pass
9898 11:32:40.173188 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
9899 11:32:40.173267 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
9900 11:32:40.173518 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
9901 11:32:40.173585 arm64_sve-ptrace_Set_SVE_VL_5024 pass
9902 11:32:40.173843 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
9903 11:32:40.173923 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
9904 11:32:40.174172 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
9905 11:32:40.174254 arm64_sve-ptrace_Set_SVE_VL_5040 pass
9906 11:32:40.178379 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
9907 11:32:40.178735 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
9908 11:32:40.178804 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
9909 11:32:40.178918 arm64_sve-ptrace_Set_SVE_VL_5056 pass
9910 11:32:40.179015 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
9911 11:32:40.179122 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
9912 11:32:40.179229 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
9913 11:32:40.179317 arm64_sve-ptrace_Set_SVE_VL_5072 pass
9914 11:32:40.179622 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
9915 11:32:40.179714 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
9916 11:32:40.179811 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
9917 11:32:40.180075 arm64_sve-ptrace_Set_SVE_VL_5088 pass
9918 11:32:40.180144 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
9919 11:32:40.180396 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
9920 11:32:40.180486 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
9921 11:32:40.180599 arm64_sve-ptrace_Set_SVE_VL_5104 pass
9922 11:32:40.180875 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
9923 11:32:40.180958 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
9924 11:32:40.181197 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
9925 11:32:40.181287 arm64_sve-ptrace_Set_SVE_VL_5120 pass
9926 11:32:40.181379 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
9927 11:32:40.181476 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
9928 11:32:40.181571 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
9929 11:32:40.181680 arm64_sve-ptrace_Set_SVE_VL_5136 pass
9930 11:32:40.181786 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
9931 11:32:40.181892 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
9932 11:32:40.181996 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
9933 11:32:40.182097 arm64_sve-ptrace_Set_SVE_VL_5152 pass
9934 11:32:40.186454 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
9935 11:32:40.186911 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
9936 11:32:40.187026 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
9937 11:32:40.187118 arm64_sve-ptrace_Set_SVE_VL_5168 pass
9938 11:32:40.187202 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
9939 11:32:40.187309 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
9940 11:32:40.187417 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
9941 11:32:40.187509 arm64_sve-ptrace_Set_SVE_VL_5184 pass
9942 11:32:40.187612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
9943 11:32:40.187700 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
9944 11:32:40.187801 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
9945 11:32:40.187906 arm64_sve-ptrace_Set_SVE_VL_5200 pass
9946 11:32:40.188204 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
9947 11:32:40.188289 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
9948 11:32:40.188381 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
9949 11:32:40.188469 arm64_sve-ptrace_Set_SVE_VL_5216 pass
9950 11:32:40.188726 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
9951 11:32:40.188811 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
9952 11:32:40.189077 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
9953 11:32:40.189148 arm64_sve-ptrace_Set_SVE_VL_5232 pass
9954 11:32:40.189245 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
9955 11:32:40.189508 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
9956 11:32:40.189580 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
9957 11:32:40.189686 arm64_sve-ptrace_Set_SVE_VL_5248 pass
9958 11:32:40.189952 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
9959 11:32:40.190036 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
9960 11:32:40.190132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
9961 11:32:40.194618 arm64_sve-ptrace_Set_SVE_VL_5264 pass
9962 11:32:40.194831 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
9963 11:32:40.194909 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
9964 11:32:40.194993 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
9965 11:32:40.195078 arm64_sve-ptrace_Set_SVE_VL_5280 pass
9966 11:32:40.195381 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
9967 11:32:40.195499 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
9968 11:32:40.195599 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
9969 11:32:40.195698 arm64_sve-ptrace_Set_SVE_VL_5296 pass
9970 11:32:40.195994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
9971 11:32:40.196095 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
9972 11:32:40.196188 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
9973 11:32:40.196288 arm64_sve-ptrace_Set_SVE_VL_5312 pass
9974 11:32:40.196571 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
9975 11:32:40.196654 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
9976 11:32:40.196753 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
9977 11:32:40.197038 arm64_sve-ptrace_Set_SVE_VL_5328 pass
9978 11:32:40.197131 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
9979 11:32:40.197232 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
9980 11:32:40.197531 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
9981 11:32:40.197637 arm64_sve-ptrace_Set_SVE_VL_5344 pass
9982 11:32:40.197751 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
9983 11:32:40.198008 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
9984 11:32:40.198105 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
9985 11:32:40.198188 arm64_sve-ptrace_Set_SVE_VL_5360 pass
9986 11:32:40.202368 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
9987 11:32:40.202778 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
9988 11:32:40.202869 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
9989 11:32:40.202962 arm64_sve-ptrace_Set_SVE_VL_5376 pass
9990 11:32:40.203067 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
9991 11:32:40.203169 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
9992 11:32:40.203480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
9993 11:32:40.203584 arm64_sve-ptrace_Set_SVE_VL_5392 pass
9994 11:32:40.203871 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
9995 11:32:40.203952 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
9996 11:32:40.204036 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
9997 11:32:40.204109 arm64_sve-ptrace_Set_SVE_VL_5408 pass
9998 11:32:40.204191 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
9999 11:32:40.204274 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10000 11:32:40.204528 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10001 11:32:40.204788 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10002 11:32:40.204868 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10003 11:32:40.204957 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10004 11:32:40.205227 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10005 11:32:40.205298 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10006 11:32:40.205371 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10007 11:32:40.205619 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10008 11:32:40.205887 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10009 11:32:40.205973 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10010 11:32:40.206036 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10011 11:32:40.206291 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10012 11:32:40.210422 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10013 11:32:40.210858 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10014 11:32:40.210965 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10015 11:32:40.211070 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10016 11:32:40.211159 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10017 11:32:40.211244 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10018 11:32:40.211346 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10019 11:32:40.211451 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10020 11:32:40.211554 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10021 11:32:40.211860 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10022 11:32:40.211966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10023 11:32:40.212070 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10024 11:32:40.212173 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10025 11:32:40.212275 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10026 11:32:40.212577 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10027 11:32:40.212684 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10028 11:32:40.212786 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10029 11:32:40.212885 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10030 11:32:40.213184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10031 11:32:40.213304 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10032 11:32:40.213404 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10033 11:32:40.213503 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10034 11:32:40.213804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10035 11:32:40.213923 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10036 11:32:40.214024 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10037 11:32:40.214116 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10038 11:32:40.218358 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10039 11:32:40.218779 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10040 11:32:40.218886 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10041 11:32:40.218990 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10042 11:32:40.230967 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10043 11:32:40.231433 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10044 11:32:40.231547 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10045 11:32:40.231636 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10046 11:32:40.231739 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10047 11:32:40.231829 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10048 11:32:40.231930 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10049 11:32:40.232020 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10050 11:32:40.232121 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10051 11:32:40.232445 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10052 11:32:40.232552 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10053 11:32:40.232655 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10054 11:32:40.232790 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10055 11:32:40.232917 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10056 11:32:40.233021 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10057 11:32:40.233301 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10058 11:32:40.233403 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10059 11:32:40.233503 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10060 11:32:40.233605 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10061 11:32:40.233917 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10062 11:32:40.234025 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10063 11:32:40.234131 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10064 11:32:40.238491 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10065 11:32:40.238685 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10066 11:32:40.238992 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10067 11:32:40.239077 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10068 11:32:40.239174 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10069 11:32:40.239281 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10070 11:32:40.239404 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10071 11:32:40.239503 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10072 11:32:40.239629 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10073 11:32:40.239726 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10074 11:32:40.239820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10075 11:32:40.239894 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10076 11:32:40.239981 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10077 11:32:40.240284 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10078 11:32:40.240402 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10079 11:32:40.240502 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10080 11:32:40.240598 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10081 11:32:40.240878 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10082 11:32:40.240982 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10083 11:32:40.241092 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10084 11:32:40.241205 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10085 11:32:40.241306 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10086 11:32:40.241582 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10087 11:32:40.241876 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10088 11:32:40.241951 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10089 11:32:40.242040 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10090 11:32:40.242144 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10091 11:32:40.242230 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10092 11:32:40.246411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10093 11:32:40.246842 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10094 11:32:40.246943 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10095 11:32:40.247036 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10096 11:32:40.247137 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10097 11:32:40.247214 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10098 11:32:40.247301 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10099 11:32:40.247398 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10100 11:32:40.247712 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10101 11:32:40.247808 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10102 11:32:40.248049 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10103 11:32:40.248145 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10104 11:32:40.248217 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10105 11:32:40.248300 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10106 11:32:40.248573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10107 11:32:40.248669 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10108 11:32:40.248753 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10109 11:32:40.248825 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10110 11:32:40.249381 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10111 11:32:40.249486 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10112 11:32:40.249565 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10113 11:32:40.249640 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10114 11:32:40.249928 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10115 11:32:40.250031 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10116 11:32:40.250110 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10117 11:32:40.250192 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10118 11:32:40.250290 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10119 11:32:40.250374 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10120 11:32:40.254371 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10121 11:32:40.254757 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10122 11:32:40.254867 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10123 11:32:40.254955 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10124 11:32:40.255055 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10125 11:32:40.255144 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10126 11:32:40.255243 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10127 11:32:40.255329 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10128 11:32:40.255423 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10129 11:32:40.255527 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10130 11:32:40.255851 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10131 11:32:40.255952 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10132 11:32:40.256051 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10133 11:32:40.256136 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10134 11:32:40.256232 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10135 11:32:40.256518 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10136 11:32:40.256618 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10137 11:32:40.256716 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10138 11:32:40.256814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10139 11:32:40.256910 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10140 11:32:40.257006 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10141 11:32:40.257102 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10142 11:32:40.257352 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10143 11:32:40.257469 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10144 11:32:40.257576 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10145 11:32:40.257684 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10146 11:32:40.257987 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10147 11:32:40.258094 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10148 11:32:40.258194 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10149 11:32:40.262363 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10150 11:32:40.262804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10151 11:32:40.262916 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10152 11:32:40.263018 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10153 11:32:40.263104 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10154 11:32:40.263203 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10155 11:32:40.263286 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10156 11:32:40.263390 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10157 11:32:40.263493 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10158 11:32:40.263593 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10159 11:32:40.263694 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10160 11:32:40.264028 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10161 11:32:40.264132 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10162 11:32:40.264420 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10163 11:32:40.264529 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10164 11:32:40.264632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10165 11:32:40.264718 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10166 11:32:40.264815 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10167 11:32:40.264913 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10168 11:32:40.265214 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10169 11:32:40.265322 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10170 11:32:40.265427 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10171 11:32:40.265693 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10172 11:32:40.265797 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10173 11:32:40.265899 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10174 11:32:40.265998 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10175 11:32:40.266097 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10176 11:32:40.270354 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10177 11:32:40.270782 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10178 11:32:40.270894 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10179 11:32:40.270981 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10180 11:32:40.271081 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10181 11:32:40.271166 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10182 11:32:40.271268 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10183 11:32:40.271368 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10184 11:32:40.271678 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10185 11:32:40.271770 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10186 11:32:40.271847 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10187 11:32:40.271912 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10188 11:32:40.272180 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10189 11:32:40.272300 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10190 11:32:40.272402 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10191 11:32:40.272522 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10192 11:32:40.272848 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10193 11:32:40.272963 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10194 11:32:40.273091 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10195 11:32:40.273217 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10196 11:32:40.273342 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10197 11:32:40.273475 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10198 11:32:40.273581 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10199 11:32:40.273721 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10200 11:32:40.273845 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10201 11:32:40.273953 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10202 11:32:40.289211 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10203 11:32:40.289695 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10204 11:32:40.289867 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10205 11:32:40.290042 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10206 11:32:40.290192 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10207 11:32:40.290372 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10208 11:32:40.290515 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10209 11:32:40.290659 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10210 11:32:40.290801 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10211 11:32:40.290980 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10212 11:32:40.291117 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10213 11:32:40.291261 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10214 11:32:40.291435 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10215 11:32:40.291623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10216 11:32:40.291802 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10217 11:32:40.292026 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10218 11:32:40.292188 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10219 11:32:40.292335 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10220 11:32:40.292511 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10221 11:32:40.292651 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10222 11:32:40.292794 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10223 11:32:40.292971 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10224 11:32:40.293108 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10225 11:32:40.293252 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10226 11:32:40.293395 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10227 11:32:40.293575 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10228 11:32:40.293765 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10229 11:32:40.293953 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10230 11:32:40.294127 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10231 11:32:40.294334 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10232 11:32:40.294506 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10233 11:32:40.294672 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10234 11:32:40.294836 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10235 11:32:40.298444 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10236 11:32:40.298871 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10237 11:32:40.298974 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10238 11:32:40.299066 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10239 11:32:40.299168 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10240 11:32:40.299257 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10241 11:32:40.299347 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10242 11:32:40.299462 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10243 11:32:40.299555 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10244 11:32:40.299651 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10245 11:32:40.299753 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10246 11:32:40.299856 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10247 11:32:40.300165 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10248 11:32:40.300282 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10249 11:32:40.300370 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10250 11:32:40.300470 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10251 11:32:40.300569 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10252 11:32:40.300877 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10253 11:32:40.300986 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10254 11:32:40.301288 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10255 11:32:40.301431 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10256 11:32:40.301535 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10257 11:32:40.301639 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10258 11:32:40.301751 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10259 11:32:40.302055 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10260 11:32:40.302159 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10261 11:32:40.302261 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10262 11:32:40.306400 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10263 11:32:40.306837 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10264 11:32:40.306925 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10265 11:32:40.306992 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10266 11:32:40.307078 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10267 11:32:40.307161 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10268 11:32:40.307240 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10269 11:32:40.307361 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10270 11:32:40.307485 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10271 11:32:40.307597 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10272 11:32:40.307922 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10273 11:32:40.308040 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10274 11:32:40.308317 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10275 11:32:40.308391 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10276 11:32:40.308466 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10277 11:32:40.308709 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10278 11:32:40.308964 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10279 11:32:40.309056 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10280 11:32:40.309162 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10281 11:32:40.309261 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10282 11:32:40.309520 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10283 11:32:40.309631 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10284 11:32:40.309913 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10285 11:32:40.310003 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10286 11:32:40.310089 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10287 11:32:40.310449 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10288 11:32:40.314558 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10289 11:32:40.314914 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10290 11:32:40.314995 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10291 11:32:40.315067 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10292 11:32:40.315148 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10293 11:32:40.315232 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10294 11:32:40.315356 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10295 11:32:40.315484 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10296 11:32:40.315660 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10297 11:32:40.315785 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10298 11:32:40.315894 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10299 11:32:40.316014 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10300 11:32:40.316315 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10301 11:32:40.316413 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10302 11:32:40.316514 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10303 11:32:40.316822 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10304 11:32:40.316929 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10305 11:32:40.317031 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10306 11:32:40.317333 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10307 11:32:40.317454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10308 11:32:40.317560 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10309 11:32:40.317670 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10310 11:32:40.317984 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10311 11:32:40.318089 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10312 11:32:40.318192 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10313 11:32:40.322365 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10314 11:32:40.322782 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10315 11:32:40.322884 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10316 11:32:40.322990 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10317 11:32:40.323078 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10318 11:32:40.323179 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10319 11:32:40.323264 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10320 11:32:40.323576 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10321 11:32:40.323685 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10322 11:32:40.323789 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10323 11:32:40.324085 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10324 11:32:40.324181 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10325 11:32:40.324283 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10326 11:32:40.324388 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10327 11:32:40.324688 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10328 11:32:40.324795 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10329 11:32:40.324895 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10330 11:32:40.324985 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10331 11:32:40.325264 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10332 11:32:40.325389 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10333 11:32:40.325495 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10334 11:32:40.325766 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10335 11:32:40.325878 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10336 11:32:40.325978 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10337 11:32:40.326071 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10338 11:32:40.330385 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10339 11:32:40.330829 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10340 11:32:40.330930 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10341 11:32:40.331017 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10342 11:32:40.331116 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10343 11:32:40.331211 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10344 11:32:40.331312 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10345 11:32:40.331398 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10346 11:32:40.331707 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10347 11:32:40.331812 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10348 11:32:40.332470 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10349 11:32:40.332575 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10350 11:32:40.332667 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10351 11:32:40.332757 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10352 11:32:40.332847 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10353 11:32:40.333142 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10354 11:32:40.333245 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10355 11:32:40.333331 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10356 11:32:40.333417 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10357 11:32:40.333515 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10358 11:32:40.333599 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10359 11:32:40.333694 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10360 11:32:40.333799 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10361 11:32:40.333889 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10362 11:32:40.352419 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10363 11:32:40.352893 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10364 11:32:40.353006 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10365 11:32:40.353112 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10366 11:32:40.353206 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10367 11:32:40.353297 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10368 11:32:40.353401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10369 11:32:40.353493 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10370 11:32:40.353599 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10371 11:32:40.353902 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10372 11:32:40.354003 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10373 11:32:40.354104 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10374 11:32:40.354397 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10375 11:32:40.354486 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10376 11:32:40.354792 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10377 11:32:40.354896 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10378 11:32:40.355010 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10379 11:32:40.355121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10380 11:32:40.355210 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10381 11:32:40.355473 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10382 11:32:40.355542 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10383 11:32:40.355630 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10384 11:32:40.355881 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10385 11:32:40.355969 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10386 11:32:40.356069 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10387 11:32:40.356375 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10388 11:32:40.356495 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10389 11:32:40.356795 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10390 11:32:40.356903 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10391 11:32:40.357004 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10392 11:32:40.357102 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10393 11:32:40.357210 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10394 11:32:40.357514 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10395 11:32:40.357632 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10396 11:32:40.357931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10397 11:32:40.358034 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10398 11:32:40.358135 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10399 11:32:40.362383 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10400 11:32:40.362821 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10401 11:32:40.362923 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10402 11:32:40.363001 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10403 11:32:40.363081 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10404 11:32:40.363354 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10405 11:32:40.363436 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10406 11:32:40.363536 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10407 11:32:40.363823 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10408 11:32:40.363926 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10409 11:32:40.364028 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10410 11:32:40.364128 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10411 11:32:40.364228 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10412 11:32:40.364328 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10413 11:32:40.364428 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10414 11:32:40.364526 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10415 11:32:40.364814 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10416 11:32:40.364937 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10417 11:32:40.365043 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10418 11:32:40.365167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10419 11:32:40.365283 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10420 11:32:40.365579 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10421 11:32:40.365699 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10422 11:32:40.365803 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10423 11:32:40.365903 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10424 11:32:40.366201 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10425 11:32:40.366307 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10426 11:32:40.370706 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10427 11:32:40.370912 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10428 11:32:40.371024 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10429 11:32:40.371098 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10430 11:32:40.371397 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10431 11:32:40.371503 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10432 11:32:40.371609 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10433 11:32:40.371697 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10434 11:32:40.371797 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10435 11:32:40.372088 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10436 11:32:40.372217 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10437 11:32:40.372522 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10438 11:32:40.372663 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10439 11:32:40.372957 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10440 11:32:40.373252 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10441 11:32:40.373363 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10442 11:32:40.373679 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10443 11:32:40.373972 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10444 11:32:40.374094 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10445 11:32:40.374405 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10446 11:32:40.382360 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10447 11:32:40.382767 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10448 11:32:40.382864 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10449 11:32:40.382950 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10450 11:32:40.383034 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10451 11:32:40.383125 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10452 11:32:40.383416 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10453 11:32:40.383525 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10454 11:32:40.383767 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10455 11:32:40.383873 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10456 11:32:40.383958 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10457 11:32:40.384241 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10458 11:32:40.384344 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10459 11:32:40.386769 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10460 11:32:40.386935 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10461 11:32:40.387009 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10462 11:32:40.387081 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10463 11:32:40.387151 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10464 11:32:40.387221 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10465 11:32:40.387295 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10466 11:32:40.387378 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10467 11:32:40.387452 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10468 11:32:40.387541 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10469 11:32:40.387636 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10470 11:32:40.387730 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10471 11:32:40.387806 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10472 11:32:40.390568 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10473 11:32:40.390965 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10474 11:32:40.391059 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10475 11:32:40.391145 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10476 11:32:40.391247 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10477 11:32:40.391332 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10478 11:32:40.391433 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10479 11:32:40.393802 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10480 11:32:40.393936 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10481 11:32:40.394009 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10482 11:32:40.394095 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10483 11:32:40.394192 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10484 11:32:40.394265 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10485 11:32:40.394332 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10486 11:32:40.394414 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10487 11:32:40.394476 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10488 11:32:40.394537 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10489 11:32:40.394597 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10490 11:32:40.394657 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10491 11:32:40.394716 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10492 11:32:40.394775 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10493 11:32:40.394834 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10494 11:32:40.394893 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10495 11:32:40.394952 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10496 11:32:40.395031 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10497 11:32:40.395119 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10498 11:32:40.395407 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10499 11:32:40.395507 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10500 11:32:40.398505 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10501 11:32:40.398930 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10502 11:32:40.399032 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10503 11:32:40.399107 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10504 11:32:40.399195 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10505 11:32:40.399268 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10506 11:32:40.399350 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10507 11:32:40.399454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10508 11:32:40.399557 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10509 11:32:40.399821 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10510 11:32:40.399915 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10511 11:32:40.399994 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10512 11:32:40.400306 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10513 11:32:40.400427 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10514 11:32:40.400527 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10515 11:32:40.400833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10516 11:32:40.400955 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10517 11:32:40.401045 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10518 11:32:40.401330 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10519 11:32:40.401412 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10520 11:32:40.401678 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10521 11:32:40.401773 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10522 11:32:40.413767 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10523 11:32:40.414228 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10524 11:32:40.414332 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10525 11:32:40.414421 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10526 11:32:40.414522 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10527 11:32:40.414622 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10528 11:32:40.414734 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10529 11:32:40.415038 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10530 11:32:40.415147 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10531 11:32:40.415235 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10532 11:32:40.415352 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10533 11:32:40.415453 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10534 11:32:40.416054 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10535 11:32:40.416165 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10536 11:32:40.416252 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10537 11:32:40.416530 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10538 11:32:40.416622 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10539 11:32:40.416710 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10540 11:32:40.416815 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10541 11:32:40.416903 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10542 11:32:40.417001 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10543 11:32:40.417101 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10544 11:32:40.417208 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10545 11:32:40.417487 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10546 11:32:40.417577 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10547 11:32:40.417690 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10548 11:32:40.417788 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10549 11:32:40.417891 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10550 11:32:40.418176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10551 11:32:40.418282 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10552 11:32:40.422609 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10553 11:32:40.422831 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10554 11:32:40.422922 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10555 11:32:40.423023 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10556 11:32:40.423121 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10557 11:32:40.423431 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10558 11:32:40.423558 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10559 11:32:40.423667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10560 11:32:40.423964 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10561 11:32:40.424062 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10562 11:32:40.424167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10563 11:32:40.425032 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10564 11:32:40.425131 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10565 11:32:40.425215 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10566 11:32:40.425300 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10567 11:32:40.425383 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10568 11:32:40.425466 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10569 11:32:40.425547 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10570 11:32:40.425630 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10571 11:32:40.425727 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10572 11:32:40.425809 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10573 11:32:40.425889 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10574 11:32:40.426167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10575 11:32:40.426258 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10576 11:32:40.426341 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10577 11:32:40.426424 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10578 11:32:40.426509 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10579 11:32:40.426589 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10580 11:32:40.426694 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10581 11:32:40.430598 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10582 11:32:40.431031 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10583 11:32:40.431139 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10584 11:32:40.431227 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10585 11:32:40.431329 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10586 11:32:40.431414 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10587 11:32:40.431512 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10588 11:32:40.431598 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10589 11:32:40.431694 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10590 11:32:40.431994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10591 11:32:40.432108 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10592 11:32:40.432197 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10593 11:32:40.432297 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10594 11:32:40.432396 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10595 11:32:40.432497 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10596 11:32:40.432792 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10597 11:32:40.432896 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10598 11:32:40.432997 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10599 11:32:40.433289 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10600 11:32:40.433395 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10601 11:32:40.433837 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10602 11:32:40.433943 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10603 11:32:40.434231 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10604 11:32:40.434314 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10605 11:32:40.434396 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10606 11:32:40.434494 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10607 11:32:40.434579 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10608 11:32:40.438388 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10609 11:32:40.438786 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10610 11:32:40.438897 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10611 11:32:40.438985 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10612 11:32:40.439090 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10613 11:32:40.439185 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10614 11:32:40.439271 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10615 11:32:40.439348 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10616 11:32:40.439625 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10617 11:32:40.439743 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10618 11:32:40.439873 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10619 11:32:40.439977 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10620 11:32:40.440085 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10621 11:32:40.440175 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10622 11:32:40.440279 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10623 11:32:40.440582 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10624 11:32:40.440877 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10625 11:32:40.440978 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10626 11:32:40.441080 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10627 11:32:40.441193 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10628 11:32:40.441311 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10629 11:32:40.441439 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10630 11:32:40.441568 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10631 11:32:40.441706 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10632 11:32:40.441827 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10633 11:32:40.441953 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10634 11:32:40.442075 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10635 11:32:40.446406 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10636 11:32:40.446830 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10637 11:32:40.446936 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10638 11:32:40.447024 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10639 11:32:40.447127 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10640 11:32:40.447213 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10641 11:32:40.447311 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10642 11:32:40.447412 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10643 11:32:40.447517 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10644 11:32:40.447820 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10645 11:32:40.447925 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10646 11:32:40.448026 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10647 11:32:40.448326 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10648 11:32:40.448450 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10649 11:32:40.448553 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10650 11:32:40.448681 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10651 11:32:40.448807 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10652 11:32:40.448896 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10653 11:32:40.449188 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10654 11:32:40.449285 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10655 11:32:40.449384 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10656 11:32:40.449472 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10657 11:32:40.449573 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10658 11:32:40.449881 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10659 11:32:40.449986 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10660 11:32:40.450097 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10661 11:32:40.450202 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10662 11:32:40.454384 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10663 11:32:40.454827 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10664 11:32:40.454933 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10665 11:32:40.455021 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10666 11:32:40.455122 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10667 11:32:40.455210 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10668 11:32:40.455308 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10669 11:32:40.455421 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10670 11:32:40.455528 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10671 11:32:40.455833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10672 11:32:40.455957 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10673 11:32:40.456063 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10674 11:32:40.456166 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10675 11:32:40.456472 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10676 11:32:40.456580 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10677 11:32:40.456687 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10678 11:32:40.456779 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10679 11:32:40.456885 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10680 11:32:40.456990 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10681 11:32:40.457094 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10682 11:32:40.472090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10683 11:32:40.472573 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10684 11:32:40.472704 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10685 11:32:40.472825 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10686 11:32:40.472948 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10687 11:32:40.473061 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10688 11:32:40.473203 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10689 11:32:40.473316 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10690 11:32:40.473439 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10691 11:32:40.473564 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10692 11:32:40.473693 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10693 11:32:40.473851 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10694 11:32:40.473951 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10695 11:32:40.474038 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10696 11:32:40.474133 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10697 11:32:40.474247 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10698 11:32:40.474342 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10699 11:32:40.474634 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10700 11:32:40.474740 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10701 11:32:40.475027 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10702 11:32:40.475132 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10703 11:32:40.475236 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10704 11:32:40.475528 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10705 11:32:40.475816 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10706 11:32:40.475895 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10707 11:32:40.475980 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10708 11:32:40.476263 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10709 11:32:40.476334 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10710 11:32:40.476621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10711 11:32:40.476882 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10712 11:32:40.476981 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10713 11:32:40.477091 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10714 11:32:40.477194 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10715 11:32:40.477494 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10716 11:32:40.477602 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10717 11:32:40.477906 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10718 11:32:40.478017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10719 11:32:40.478321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10720 11:32:40.482539 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10721 11:32:40.482890 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10722 11:32:40.482977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10723 11:32:40.483086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10724 11:32:40.483400 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10725 11:32:40.483498 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10726 11:32:40.483578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10727 11:32:40.483654 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10728 11:32:40.483942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10729 11:32:40.484243 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10730 11:32:40.484362 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10731 11:32:40.484666 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10732 11:32:40.484976 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10733 11:32:40.485081 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10734 11:32:40.485191 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10735 11:32:40.485291 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10736 11:32:40.485567 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10737 11:32:40.485680 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10738 11:32:40.485967 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10739 11:32:40.486097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10740 11:32:40.494396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10741 11:32:40.494838 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10742 11:32:40.494919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10743 11:32:40.494984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10744 11:32:40.495084 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10745 11:32:40.495192 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10746 11:32:40.495280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10747 11:32:40.495601 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10748 11:32:40.495722 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10749 11:32:40.495976 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10750 11:32:40.496083 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10751 11:32:40.496403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10752 11:32:40.496510 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10753 11:32:40.496624 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10754 11:32:40.496914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
10755 11:32:40.497002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
10756 11:32:40.497303 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
10757 11:32:40.497412 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
10758 11:32:40.497522 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
10759 11:32:40.497628 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
10760 11:32:40.497914 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
10761 11:32:40.497994 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
10762 11:32:40.498279 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
10763 11:32:40.502409 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
10764 11:32:40.502848 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
10765 11:32:40.502975 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
10766 11:32:40.503087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
10767 11:32:40.503401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
10768 11:32:40.503524 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
10769 11:32:40.503635 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
10770 11:32:40.503940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
10771 11:32:40.504055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
10772 11:32:40.504142 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
10773 11:32:40.504427 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
10774 11:32:40.504549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
10775 11:32:40.504652 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
10776 11:32:40.504954 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
10777 11:32:40.505062 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
10778 11:32:40.505350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
10779 11:32:40.505453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
10780 11:32:40.505685 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
10781 11:32:40.505775 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
10782 11:32:40.506056 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
10783 11:32:40.506162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
10784 11:32:40.510372 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
10785 11:32:40.510799 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
10786 11:32:40.510897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
10787 11:32:40.510999 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
10788 11:32:40.511085 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
10789 11:32:40.511186 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
10790 11:32:40.511288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
10791 11:32:40.511392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
10792 11:32:40.511702 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
10793 11:32:40.511811 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
10794 11:32:40.511926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
10795 11:32:40.512093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
10796 11:32:40.512415 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
10797 11:32:40.512523 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
10798 11:32:40.512619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
10799 11:32:40.512888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
10800 11:32:40.512997 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
10801 11:32:40.513280 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
10802 11:32:40.513387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
10803 11:32:40.513473 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
10804 11:32:40.513754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
10805 11:32:40.513852 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
10806 11:32:40.513946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
10807 11:32:40.514230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
10808 11:32:40.518374 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
10809 11:32:40.518796 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
10810 11:32:40.519328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
10811 11:32:40.519432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
10812 11:32:40.519521 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
10813 11:32:40.519608 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
10814 11:32:40.519696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
10815 11:32:40.519782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
10816 11:32:40.519868 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
10817 11:32:40.520158 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
10818 11:32:40.520263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
10819 11:32:40.529359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
10820 11:32:40.529798 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
10821 11:32:40.529904 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
10822 11:32:40.529999 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
10823 11:32:40.530099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
10824 11:32:40.530185 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
10825 11:32:40.530284 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
10826 11:32:40.530579 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
10827 11:32:40.530703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
10828 11:32:40.530804 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
10829 11:32:40.530897 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
10830 11:32:40.531199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
10831 11:32:40.531323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
10832 11:32:40.531433 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
10833 11:32:40.531725 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
10834 11:32:40.531843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
10835 11:32:40.531946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
10836 11:32:40.532045 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
10837 11:32:40.532347 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
10838 11:32:40.532453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
10839 11:32:40.532556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
10840 11:32:40.532664 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
10841 11:32:40.532962 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
10842 11:32:40.533080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
10843 11:32:40.533368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
10844 11:32:40.533455 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
10845 11:32:40.533535 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
10846 11:32:40.533827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
10847 11:32:40.533947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
10848 11:32:40.534250 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
10849 11:32:40.538378 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
10850 11:32:40.538802 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
10851 11:32:40.538911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
10852 11:32:40.539045 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
10853 11:32:40.539172 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
10854 11:32:40.539294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
10855 11:32:40.539421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
10856 11:32:40.539732 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
10857 11:32:40.539840 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
10858 11:32:40.539946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
10859 11:32:40.540050 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
10860 11:32:40.540146 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
10861 11:32:40.540415 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
10862 11:32:40.540689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
10863 11:32:40.540769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
10864 11:32:40.541080 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
10865 11:32:40.541182 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
10866 11:32:40.541281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
10867 11:32:40.541382 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
10868 11:32:40.541692 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
10869 11:32:40.541799 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
10870 11:32:40.541899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
10871 11:32:40.541998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
10872 11:32:40.542307 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
10873 11:32:40.542415 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
10874 11:32:40.546425 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
10875 11:32:40.546849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
10876 11:32:40.546965 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
10877 11:32:40.547058 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
10878 11:32:40.547163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
10879 11:32:40.547268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
10880 11:32:40.547570 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
10881 11:32:40.548557 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
10882 11:32:40.548678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
10883 11:32:40.548766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
10884 11:32:40.548856 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
10885 11:32:40.548946 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
10886 11:32:40.549035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
10887 11:32:40.549124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
10888 11:32:40.549417 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
10889 11:32:40.549524 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
10890 11:32:40.549615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
10891 11:32:40.549712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
10892 11:32:40.549798 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
10893 11:32:40.549881 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
10894 11:32:40.549991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
10895 11:32:40.550082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
10896 11:32:40.550182 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
10897 11:32:40.550269 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
10898 11:32:40.554446 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
10899 11:32:40.554880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
10900 11:32:40.554993 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
10901 11:32:40.555080 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
10902 11:32:40.555182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
10903 11:32:40.555267 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
10904 11:32:40.555365 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
10905 11:32:40.555466 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
10906 11:32:40.555774 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
10907 11:32:40.555895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
10908 11:32:40.556004 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
10909 11:32:40.556313 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
10910 11:32:40.556417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
10911 11:32:40.556520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
10912 11:32:40.556622 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
10913 11:32:40.556933 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
10914 11:32:40.557042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
10915 11:32:40.557145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
10916 11:32:40.557247 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
10917 11:32:40.557559 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
10918 11:32:40.557672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
10919 11:32:40.557776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
10920 11:32:40.557880 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
10921 11:32:40.558191 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
10922 11:32:40.562662 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
10923 11:32:40.563062 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
10924 11:32:40.563167 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
10925 11:32:40.563254 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
10926 11:32:40.563360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
10927 11:32:40.563464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
10928 11:32:40.563574 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
10929 11:32:40.563903 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
10930 11:32:40.564006 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
10931 11:32:40.564308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
10932 11:32:40.564419 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
10933 11:32:40.564522 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
10934 11:32:40.564610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
10935 11:32:40.564712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
10936 11:32:40.564814 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
10937 11:32:40.564917 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
10938 11:32:40.565222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
10939 11:32:40.565328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
10940 11:32:40.565431 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
10941 11:32:40.565534 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
10942 11:32:40.565825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
10943 11:32:40.566141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
10944 11:32:40.566229 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
10945 11:32:40.566330 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
10946 11:32:40.566429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
10947 11:32:40.570401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
10948 11:32:40.570826 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
10949 11:32:40.570916 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
10950 11:32:40.571012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
10951 11:32:40.571128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
10952 11:32:40.571254 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
10953 11:32:40.571363 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
10954 11:32:40.571504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
10955 11:32:40.584744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
10956 11:32:40.585178 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
10957 11:32:40.585258 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
10958 11:32:40.585344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
10959 11:32:40.585430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
10960 11:32:40.585702 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
10961 11:32:40.585813 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
10962 11:32:40.585914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
10963 11:32:40.586192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
10964 11:32:40.586647 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
10965 11:32:40.586747 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
10966 11:32:40.587021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
10967 11:32:40.587296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
10968 11:32:40.587409 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
10969 11:32:40.587712 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
10970 11:32:40.587831 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
10971 11:32:40.588123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
10972 11:32:40.588227 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
10973 11:32:40.588337 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
10974 11:32:40.588650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
10975 11:32:40.588934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
10976 11:32:40.589040 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
10977 11:32:40.589146 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
10978 11:32:40.589246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
10979 11:32:40.589441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
10980 11:32:40.589758 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
10981 11:32:40.589863 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
10982 11:32:40.589963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
10983 11:32:40.590265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
10984 11:32:40.594396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
10985 11:32:40.594830 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
10986 11:32:40.594946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
10987 11:32:40.595033 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
10988 11:32:40.595135 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
10989 11:32:40.595224 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
10990 11:32:40.595324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
10991 11:32:40.595635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
10992 11:32:40.595759 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
10993 11:32:40.595861 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
10994 11:32:40.595965 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
10995 11:32:40.596282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
10996 11:32:40.596392 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
10997 11:32:40.596494 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
10998 11:32:40.596600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
10999 11:32:40.596912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11000 11:32:40.597024 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11001 11:32:40.597126 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11002 11:32:40.597412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11003 11:32:40.597506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11004 11:32:40.597607 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11005 11:32:40.597721 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11006 11:32:40.598006 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11007 11:32:40.598118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11008 11:32:40.602403 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11009 11:32:40.602815 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11010 11:32:40.602923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11011 11:32:40.603013 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11012 11:32:40.603110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11013 11:32:40.603185 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11014 11:32:40.603469 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11015 11:32:40.603736 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11016 11:32:40.603813 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11017 11:32:40.604095 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11018 11:32:40.604211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11019 11:32:40.604499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11020 11:32:40.604608 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11021 11:32:40.604714 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11022 11:32:40.605012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11023 11:32:40.605127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11024 11:32:40.605426 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11025 11:32:40.605534 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11026 11:32:40.605823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11027 11:32:40.605934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11028 11:32:40.606234 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11029 11:32:40.610659 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11030 11:32:40.610885 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11031 11:32:40.610966 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11032 11:32:40.611259 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11033 11:32:40.611366 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11034 11:32:40.611456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11035 11:32:40.611740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11036 11:32:40.611845 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11037 11:32:40.612110 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11038 11:32:40.612378 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11039 11:32:40.612643 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11040 11:32:40.612731 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11041 11:32:40.613000 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11042 11:32:40.613093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11043 11:32:40.613362 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11044 11:32:40.613630 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11045 11:32:40.613729 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11046 11:32:40.614017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11047 11:32:40.614140 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11048 11:32:40.622380 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11049 11:32:40.622834 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11050 11:32:40.622944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11051 11:32:40.623063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11052 11:32:40.623157 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11053 11:32:40.623472 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11054 11:32:40.623576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11055 11:32:40.623708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11056 11:32:40.624034 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11057 11:32:40.624160 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11058 11:32:40.624266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11059 11:32:40.624370 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11060 11:32:40.624665 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11061 11:32:40.624781 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11062 11:32:40.625081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11063 11:32:40.625192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11064 11:32:40.625500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11065 11:32:40.625615 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11066 11:32:40.625915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11067 11:32:40.626028 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11068 11:32:40.626340 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11069 11:32:40.630389 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11070 11:32:40.630827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11071 11:32:40.630939 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11072 11:32:40.631043 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11073 11:32:40.631134 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11074 11:32:40.631239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11075 11:32:40.631549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11076 11:32:40.631671 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11077 11:32:40.631977 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11078 11:32:40.632078 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11079 11:32:40.632178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11080 11:32:40.632449 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11081 11:32:40.632572 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11082 11:32:40.632871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11083 11:32:40.632970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11084 11:32:40.633073 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11085 11:32:40.633173 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11086 11:32:40.633473 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11087 11:32:40.633592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11088 11:32:40.633901 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11089 11:32:40.642683 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11090 11:32:40.643131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11091 11:32:40.643230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11092 11:32:40.643315 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11093 11:32:40.643417 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11094 11:32:40.643710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11095 11:32:40.643825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11096 11:32:40.643963 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11097 11:32:40.644102 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11098 11:32:40.644399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11099 11:32:40.644511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11100 11:32:40.644641 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11101 11:32:40.644765 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11102 11:32:40.644900 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11103 11:32:40.645232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11104 11:32:40.645360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11105 11:32:40.645464 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11106 11:32:40.645758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11107 11:32:40.645867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11108 11:32:40.645972 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11109 11:32:40.646079 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11110 11:32:40.650394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11111 11:32:40.650814 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11112 11:32:40.650904 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11113 11:32:40.651005 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11114 11:32:40.651123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11115 11:32:40.651251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11116 11:32:40.651568 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11117 11:32:40.651675 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11118 11:32:40.651786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11119 11:32:40.651876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11120 11:32:40.652173 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11121 11:32:40.652279 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11122 11:32:40.652382 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11123 11:32:40.652686 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11124 11:32:40.652971 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11125 11:32:40.653056 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11126 11:32:40.653137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11127 11:32:40.653394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11128 11:32:40.653476 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11129 11:32:40.653750 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11130 11:32:40.653871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11131 11:32:40.653981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11132 11:32:40.654094 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11133 11:32:40.654395 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11134 11:32:40.658338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11135 11:32:40.658720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11136 11:32:40.658823 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11137 11:32:40.658928 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11138 11:32:40.659032 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11139 11:32:40.659142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11140 11:32:40.659451 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11141 11:32:40.659569 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11142 11:32:40.659874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11143 11:32:40.659994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11144 11:32:40.660100 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11145 11:32:40.660408 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11146 11:32:40.660510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11147 11:32:40.660614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11148 11:32:40.660718 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11149 11:32:40.660830 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11150 11:32:40.661141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11151 11:32:40.661246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11152 11:32:40.661685 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11153 11:32:40.661793 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11154 11:32:40.661879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11155 11:32:40.662167 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11156 11:32:40.662273 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11157 11:32:40.662361 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11158 11:32:40.666945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11159 11:32:40.667145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11160 11:32:40.667238 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11161 11:32:40.667346 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11162 11:32:40.667435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11163 11:32:40.667544 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11164 11:32:40.667820 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11165 11:32:40.667917 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11166 11:32:40.668036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11167 11:32:40.668148 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11168 11:32:40.668461 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11169 11:32:40.668567 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11170 11:32:40.668667 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11171 11:32:40.668815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11172 11:32:40.669089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11173 11:32:40.669210 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11174 11:32:40.669311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11175 11:32:40.669606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11176 11:32:40.669738 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11177 11:32:40.670023 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11178 11:32:40.670148 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11179 11:32:40.674398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11180 11:32:40.674788 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11181 11:32:40.675093 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11182 11:32:40.675187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11183 11:32:40.675289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11184 11:32:40.675425 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11185 11:32:40.675525 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11186 11:32:40.675635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11187 11:32:40.675898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11188 11:32:40.675986 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11189 11:32:40.676253 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11190 11:32:40.676510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11191 11:32:40.676604 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11192 11:32:40.676867 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11193 11:32:40.676951 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11194 11:32:40.677069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11195 11:32:40.677179 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11196 11:32:40.677480 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11197 11:32:40.677565 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11198 11:32:40.677691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11199 11:32:40.677803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11200 11:32:40.678096 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11201 11:32:40.678210 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11202 11:32:40.682424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11203 11:32:40.682740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11204 11:32:40.682808 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11205 11:32:40.682911 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11206 11:32:40.683217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11207 11:32:40.683324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11208 11:32:40.683427 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11209 11:32:40.683726 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11210 11:32:40.683850 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11211 11:32:40.683952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11212 11:32:40.684251 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11213 11:32:40.684366 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11214 11:32:40.684467 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11215 11:32:40.684757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11216 11:32:40.684876 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11217 11:32:40.684982 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11218 11:32:40.685092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11219 11:32:40.685406 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11220 11:32:40.685518 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11221 11:32:40.685810 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11222 11:32:40.685908 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11223 11:32:40.701807 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11224 11:32:40.702274 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11225 11:32:40.702372 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11226 11:32:40.702463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11227 11:32:40.702750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11228 11:32:40.702835 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11229 11:32:40.703123 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11230 11:32:40.703252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11231 11:32:40.703349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11232 11:32:40.703461 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11233 11:32:40.703584 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11234 11:32:40.703890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11235 11:32:40.703985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11236 11:32:40.704242 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11237 11:32:40.704416 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11238 11:32:40.704785 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11239 11:32:40.704937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11240 11:32:40.705068 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11241 11:32:40.705233 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11242 11:32:40.705378 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11243 11:32:40.705554 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11244 11:32:40.705730 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11245 11:32:40.705961 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11246 11:32:40.706201 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11247 11:32:40.706461 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11248 11:32:40.710427 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11249 11:32:40.710844 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11250 11:32:40.710957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11251 11:32:40.711071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11252 11:32:40.711167 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11253 11:32:40.711278 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11254 11:32:40.711396 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11255 11:32:40.711705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11256 11:32:40.711829 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11257 11:32:40.711933 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11258 11:32:40.712234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11259 11:32:40.712351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11260 11:32:40.712457 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11261 11:32:40.712557 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11262 11:32:40.712857 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11263 11:32:40.712968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11264 11:32:40.713070 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11265 11:32:40.713355 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11266 11:32:40.713462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11267 11:32:40.713570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11268 11:32:40.713689 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11269 11:32:40.713982 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11270 11:32:40.714092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11271 11:32:40.714394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11272 11:32:40.718456 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11273 11:32:40.718845 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11274 11:32:40.718931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11275 11:32:40.719042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11276 11:32:40.719407 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11277 11:32:40.719614 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11278 11:32:40.719861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11279 11:32:40.720042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11280 11:32:40.720242 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11281 11:32:40.720407 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11282 11:32:40.720569 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11283 11:32:40.720768 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11284 11:32:40.720940 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11285 11:32:40.721106 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11286 11:32:40.721305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11287 11:32:40.721476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11288 11:32:40.721639 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11289 11:32:40.721818 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11290 11:32:40.721972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11291 11:32:40.722097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11292 11:32:40.722218 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11293 11:32:40.722337 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11294 11:32:40.722476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11295 11:32:40.726392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11296 11:32:40.726819 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11297 11:32:40.726927 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11298 11:32:40.727034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11299 11:32:40.727123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11300 11:32:40.727225 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11301 11:32:40.727531 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11302 11:32:40.727647 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11303 11:32:40.727751 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11304 11:32:40.728055 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11305 11:32:40.728159 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11306 11:32:40.728457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11307 11:32:40.728574 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11308 11:32:40.728875 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11309 11:32:40.728991 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11310 11:32:40.729294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11311 11:32:40.729409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11312 11:32:40.729513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11313 11:32:40.729814 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11314 11:32:40.729942 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11315 11:32:40.730254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11316 11:32:40.734417 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11317 11:32:40.734832 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11318 11:32:40.734944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11319 11:32:40.735046 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11320 11:32:40.735152 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11321 11:32:40.735254 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11322 11:32:40.735557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11323 11:32:40.735675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11324 11:32:40.735778 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11325 11:32:40.736086 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11326 11:32:40.736200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11327 11:32:40.736302 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11328 11:32:40.736607 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11329 11:32:40.736711 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11330 11:32:40.736813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11331 11:32:40.737114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11332 11:32:40.737233 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11333 11:32:40.737339 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11334 11:32:40.737642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11335 11:32:40.737769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11336 11:32:40.738077 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11337 11:32:40.738201 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11338 11:32:40.738310 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11339 11:32:40.738622 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11340 11:32:40.746370 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11341 11:32:40.746838 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11342 11:32:40.746948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11343 11:32:40.747041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11344 11:32:40.747147 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11345 11:32:40.747243 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11346 11:32:40.747350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11347 11:32:40.747456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11348 11:32:40.747599 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11349 11:32:40.747929 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11350 11:32:40.748044 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11351 11:32:40.748162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11352 11:32:40.748261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11353 11:32:40.748547 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11354 11:32:40.748655 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11355 11:32:40.748736 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11356 11:32:40.749013 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11357 11:32:40.758252 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11358 11:32:40.758726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11359 11:32:40.759061 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11360 11:32:40.759182 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11361 11:32:40.759483 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11362 11:32:40.759791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11363 11:32:40.760089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11364 11:32:40.760395 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11365 11:32:40.760506 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11366 11:32:40.760799 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11367 11:32:40.761105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11368 11:32:40.761403 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11369 11:32:40.761514 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11370 11:32:40.762030 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11371 11:32:40.762160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11372 11:32:40.766417 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11373 11:32:40.766853 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11374 11:32:40.766965 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11375 11:32:40.767051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11376 11:32:40.767155 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11377 11:32:40.767256 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11378 11:32:40.767554 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11379 11:32:40.767668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11380 11:32:40.767960 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11381 11:32:40.768048 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11382 11:32:40.768127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11383 11:32:40.768377 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11384 11:32:40.768630 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11385 11:32:40.768712 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11386 11:32:40.768790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11387 11:32:40.769065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11388 11:32:40.769341 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11389 11:32:40.769437 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11390 11:32:40.769683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11391 11:32:40.769793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11392 11:32:40.769898 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11393 11:32:40.770022 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11394 11:32:40.774434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11395 11:32:40.774845 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11396 11:32:40.774949 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11397 11:32:40.775052 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11398 11:32:40.775152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11399 11:32:40.775463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11400 11:32:40.775570 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11401 11:32:40.775671 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11402 11:32:40.775772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11403 11:32:40.776038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11404 11:32:40.776167 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11405 11:32:40.776471 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11406 11:32:40.776583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11407 11:32:40.776886 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11408 11:32:40.776989 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11409 11:32:40.777090 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11410 11:32:40.777381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11411 11:32:40.777475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11412 11:32:40.777574 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11413 11:32:40.777872 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11414 11:32:40.777980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11415 11:32:40.778081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11416 11:32:40.782372 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11417 11:32:40.782808 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11418 11:32:40.782908 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11419 11:32:40.782997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11420 11:32:40.783099 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11421 11:32:40.783202 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11422 11:32:40.783305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11423 11:32:40.783600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11424 11:32:40.783726 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11425 11:32:40.783848 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11426 11:32:40.784147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11427 11:32:40.784265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11428 11:32:40.784557 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11429 11:32:40.784658 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11430 11:32:40.784769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11431 11:32:40.784872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11432 11:32:40.784975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11433 11:32:40.785078 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11434 11:32:40.785372 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11435 11:32:40.785492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11436 11:32:40.785598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11437 11:32:40.785774 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11438 11:32:40.785879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11439 11:32:40.786163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11440 11:32:40.790399 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11441 11:32:40.790810 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11442 11:32:40.790910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11443 11:32:40.790995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11444 11:32:40.791100 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11445 11:32:40.791205 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11446 11:32:40.791510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11447 11:32:40.791627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11448 11:32:40.791725 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11449 11:32:40.791825 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11450 11:32:40.791981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11451 11:32:40.792285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11452 11:32:40.792394 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11453 11:32:40.792494 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11454 11:32:40.792774 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11455 11:32:40.792880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11456 11:32:40.793166 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11457 11:32:40.793272 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11458 11:32:40.793380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11459 11:32:40.793689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11460 11:32:40.793806 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11461 11:32:40.793908 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11462 11:32:40.794213 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11463 11:32:40.798437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11464 11:32:40.798874 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11465 11:32:40.798969 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11466 11:32:40.799043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11467 11:32:40.799128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11468 11:32:40.799214 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11469 11:32:40.799314 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11470 11:32:40.799600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11471 11:32:40.799703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11472 11:32:40.799815 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11473 11:32:40.799919 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11474 11:32:40.800201 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11475 11:32:40.800303 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11476 11:32:40.800585 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11477 11:32:40.800688 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11478 11:32:40.800795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11479 11:32:40.801091 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11480 11:32:40.801193 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11481 11:32:40.801282 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11482 11:32:40.801557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11483 11:32:40.801681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11484 11:32:40.801980 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11485 11:32:40.802068 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11486 11:32:40.802163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11487 11:32:40.806417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11488 11:32:40.806852 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11489 11:32:40.806957 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11490 11:32:40.807060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11491 11:32:40.815606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11492 11:32:40.816142 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11493 11:32:40.816248 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11494 11:32:40.816337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11495 11:32:40.816424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11496 11:32:40.816712 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11497 11:32:40.816817 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11498 11:32:40.816908 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11499 11:32:40.816993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11500 11:32:40.817091 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11501 11:32:40.817175 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11502 11:32:40.817271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11503 11:32:40.817371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11504 11:32:40.817457 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11505 11:32:40.817757 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11506 11:32:40.817862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11507 11:32:40.817949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11508 11:32:40.818051 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11509 11:32:40.818140 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11510 11:32:40.818236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11511 11:32:40.822871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11512 11:32:40.823071 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11513 11:32:40.823175 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11514 11:32:40.823260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11515 11:32:40.823360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11516 11:32:40.823464 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11517 11:32:40.823570 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11518 11:32:40.823861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11519 11:32:40.823975 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11520 11:32:40.824076 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11521 11:32:40.824363 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11522 11:32:40.824461 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11523 11:32:40.824568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11524 11:32:40.824856 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11525 11:32:40.824956 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11526 11:32:40.825057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11527 11:32:40.825353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11528 11:32:40.825476 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11529 11:32:40.825568 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11530 11:32:40.825889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11531 11:32:40.825991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11532 11:32:40.826089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11533 11:32:40.826188 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11534 11:32:40.830451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11535 11:32:40.830862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11536 11:32:40.830969 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11537 11:32:40.831070 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11538 11:32:40.831155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11539 11:32:40.831451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11540 11:32:40.831563 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11541 11:32:40.831661 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11542 11:32:40.831973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11543 11:32:40.832076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11544 11:32:40.832376 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11545 11:32:40.832476 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11546 11:32:40.832577 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11547 11:32:40.832875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11548 11:32:40.833166 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11549 11:32:40.833258 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11550 11:32:40.833343 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11551 11:32:40.833427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11552 11:32:40.833683 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11553 11:32:40.833778 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11554 11:32:40.834071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11555 11:32:40.834354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11556 11:32:40.834460 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11557 11:32:40.838627 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11558 11:32:40.838847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11559 11:32:40.838954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11560 11:32:40.839259 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11561 11:32:40.839361 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11562 11:32:40.839463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11563 11:32:40.839577 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11564 11:32:40.839879 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11565 11:32:40.839994 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11566 11:32:40.840300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11567 11:32:40.840421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11568 11:32:40.840739 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11569 11:32:40.840840 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11570 11:32:40.840940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11571 11:32:40.841245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11572 11:32:40.841365 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11573 11:32:40.841493 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11574 11:32:40.841794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11575 11:32:40.842159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11576 11:32:40.846459 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11577 11:32:40.846877 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11578 11:32:40.847215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11579 11:32:40.847320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11580 11:32:40.847411 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11581 11:32:40.847500 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11582 11:32:40.847789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11583 11:32:40.847888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11584 11:32:40.847954 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11585 11:32:40.848054 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11586 11:32:40.848162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11587 11:32:40.848266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11588 11:32:40.848567 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11589 11:32:40.848679 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11590 11:32:40.848978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11591 11:32:40.849273 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11592 11:32:40.849376 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11593 11:32:40.849476 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11594 11:32:40.849575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11595 11:32:40.849871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11596 11:32:40.849992 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11597 11:32:40.850102 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11598 11:32:40.854476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11599 11:32:40.854910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11600 11:32:40.855015 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11601 11:32:40.855120 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11602 11:32:40.855211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11603 11:32:40.855312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11604 11:32:40.855619 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11605 11:32:40.855727 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11606 11:32:40.855829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11607 11:32:40.856128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11608 11:32:40.856244 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11609 11:32:40.856344 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11610 11:32:40.856443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11611 11:32:40.856740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11612 11:32:40.857048 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11613 11:32:40.857150 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11614 11:32:40.857251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11615 11:32:40.857353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11616 11:32:40.857666 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11617 11:32:40.857771 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11618 11:32:40.857872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11619 11:32:40.858172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11620 11:32:40.862475 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11621 11:32:40.862906 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11622 11:32:40.863003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11623 11:32:40.863088 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11624 11:32:40.863194 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11625 11:32:40.873857 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11626 11:32:40.874327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11627 11:32:40.874424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11628 11:32:40.874501 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11629 11:32:40.874591 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11630 11:32:40.874695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11631 11:32:40.875196 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11632 11:32:40.875305 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11633 11:32:40.875393 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11634 11:32:40.875469 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11635 11:32:40.875673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11636 11:32:40.875895 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11637 11:32:40.876064 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11638 11:32:40.876207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11639 11:32:40.876349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11640 11:32:40.876490 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11641 11:32:40.876672 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11642 11:32:40.876872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11643 11:32:40.877072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11644 11:32:40.877270 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11645 11:32:40.877437 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11646 11:32:40.877581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11647 11:32:40.877792 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11648 11:32:40.877992 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11649 11:32:40.878201 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11650 11:32:40.878393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11651 11:32:40.878578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11652 11:32:40.878728 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11653 11:32:40.878876 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11654 11:32:40.879023 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11655 11:32:40.879165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11656 11:32:40.879556 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11657 11:32:40.886411 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11658 11:32:40.886865 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11659 11:32:40.886980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11660 11:32:40.887087 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11661 11:32:40.887174 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11662 11:32:40.887272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11663 11:32:40.887567 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11664 11:32:40.887683 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11665 11:32:40.887786 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11666 11:32:40.888084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11667 11:32:40.888203 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11668 11:32:40.888310 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11669 11:32:40.888615 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11670 11:32:40.888709 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11671 11:32:40.888992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11672 11:32:40.889101 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11673 11:32:40.889189 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11674 11:32:40.889287 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11675 11:32:40.889568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11676 11:32:40.889877 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11677 11:32:40.889987 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11678 11:32:40.890075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11679 11:32:40.894545 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11680 11:32:40.894978 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11681 11:32:40.895082 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11682 11:32:40.895172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11683 11:32:40.895280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11684 11:32:40.895575 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11685 11:32:40.895685 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11686 11:32:40.895785 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11687 11:32:40.896050 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11688 11:32:40.896132 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11689 11:32:40.896212 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11690 11:32:40.896459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11691 11:32:40.896539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11692 11:32:40.896794 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11693 11:32:40.896876 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11694 11:32:40.897132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11695 11:32:40.897388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11696 11:32:40.897470 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11697 11:32:40.897742 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11698 11:32:40.897829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11699 11:32:40.898090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11700 11:32:40.898189 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11701 11:32:40.902444 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11702 11:32:40.902830 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11703 11:32:40.902925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11704 11:32:40.903033 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11705 11:32:40.903140 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11706 11:32:40.903241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11707 11:32:40.903526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11708 11:32:40.903656 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11709 11:32:40.903950 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11710 11:32:40.904060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11711 11:32:40.904165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11712 11:32:40.904495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11713 11:32:40.904615 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11714 11:32:40.904919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11715 11:32:40.905037 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11716 11:32:40.905342 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11717 11:32:40.905452 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11718 11:32:40.905557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11719 11:32:40.905672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11720 11:32:40.905979 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11721 11:32:40.906084 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11722 11:32:40.906206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11723 11:32:40.910408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11724 11:32:40.910807 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11725 11:32:40.910895 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11726 11:32:40.910983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11727 11:32:40.911064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11728 11:32:40.911357 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11729 11:32:40.911493 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11730 11:32:40.911624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11731 11:32:40.911957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11732 11:32:40.912060 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11733 11:32:40.912164 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11734 11:32:40.912265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11735 11:32:40.912564 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11736 11:32:40.912681 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11737 11:32:40.912782 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11738 11:32:40.913076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11739 11:32:40.913188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11740 11:32:40.913491 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11741 11:32:40.913602 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11742 11:32:40.913717 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11743 11:32:40.914000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11744 11:32:40.914125 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11745 11:32:40.914228 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11746 11:32:40.914322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11747 11:32:40.914561 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11748 11:32:40.918392 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11749 11:32:40.918755 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11750 11:32:40.918837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11751 11:32:40.918913 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11752 11:32:40.918988 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11753 11:32:40.919279 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11754 11:32:40.919374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
11755 11:32:40.919468 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
11756 11:32:40.919756 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
11757 11:32:40.919861 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
11758 11:32:40.920162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
11759 11:32:40.929366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
11760 11:32:40.929790 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
11761 11:32:40.929897 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
11762 11:32:40.930002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
11763 11:32:40.930104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
11764 11:32:40.930394 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
11765 11:32:40.930510 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
11766 11:32:40.930617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
11767 11:32:40.930910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
11768 11:32:40.931020 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
11769 11:32:40.931121 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
11770 11:32:40.931226 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
11771 11:32:40.931557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
11772 11:32:40.931683 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
11773 11:32:40.931993 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
11774 11:32:40.932109 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
11775 11:32:40.932212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
11776 11:32:40.932506 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
11777 11:32:40.932602 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
11778 11:32:40.932860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
11779 11:32:40.933144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
11780 11:32:40.933264 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
11781 11:32:40.933368 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
11782 11:32:40.933687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
11783 11:32:40.933811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
11784 11:32:40.934143 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
11785 11:32:40.934250 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
11786 11:32:40.938477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
11787 11:32:40.938917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
11788 11:32:40.939026 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
11789 11:32:40.939117 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
11790 11:32:40.939220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
11791 11:32:40.939323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
11792 11:32:40.939426 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
11793 11:32:40.939746 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
11794 11:32:40.939864 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
11795 11:32:40.940144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
11796 11:32:40.940405 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
11797 11:32:40.940475 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
11798 11:32:40.940729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
11799 11:32:40.940810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
11800 11:32:40.941087 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
11801 11:32:40.941214 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
11802 11:32:40.941509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
11803 11:32:40.941616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
11804 11:32:40.941736 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
11805 11:32:40.941841 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
11806 11:32:40.942149 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
11807 11:32:40.942273 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
11808 11:32:40.946518 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
11809 11:32:40.946963 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
11810 11:32:40.947063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
11811 11:32:40.947166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
11812 11:32:40.947258 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
11813 11:32:40.947355 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
11814 11:32:40.947650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
11815 11:32:40.947763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
11816 11:32:40.947868 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
11817 11:32:40.947970 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
11818 11:32:40.948261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
11819 11:32:40.948371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
11820 11:32:40.948474 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
11821 11:32:40.948774 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
11822 11:32:40.948889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
11823 11:32:40.949210 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
11824 11:32:40.949312 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
11825 11:32:40.949599 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
11826 11:32:40.949732 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
11827 11:32:40.950036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
11828 11:32:40.950330 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
11829 11:32:40.954717 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
11830 11:32:40.954931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
11831 11:32:40.955237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
11832 11:32:40.955342 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
11833 11:32:40.955447 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
11834 11:32:40.955747 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
11835 11:32:40.955841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
11836 11:32:40.956100 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
11837 11:32:40.956183 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
11838 11:32:40.956441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
11839 11:32:40.956698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
11840 11:32:40.956960 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
11841 11:32:40.957033 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
11842 11:32:40.957304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
11843 11:32:40.957401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
11844 11:32:40.957499 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
11845 11:32:40.957766 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
11846 11:32:40.957892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
11847 11:32:40.958205 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
11848 11:32:40.962367 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
11849 11:32:40.962799 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
11850 11:32:40.962910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
11851 11:32:40.963013 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
11852 11:32:40.963115 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
11853 11:32:40.963392 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
11854 11:32:40.963496 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
11855 11:32:40.963600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
11856 11:32:40.963731 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
11857 11:32:40.963840 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
11858 11:32:40.964112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
11859 11:32:40.964376 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
11860 11:32:40.964461 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
11861 11:32:40.964763 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
11862 11:32:40.964881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
11863 11:32:40.964983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
11864 11:32:40.965254 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
11865 11:32:40.965350 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
11866 11:32:40.965607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
11867 11:32:40.965700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
11868 11:32:40.965956 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
11869 11:32:40.966040 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
11870 11:32:40.970455 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
11871 11:32:40.970872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
11872 11:32:40.970962 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
11873 11:32:40.971062 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
11874 11:32:40.971150 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
11875 11:32:40.971254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
11876 11:32:40.971555 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
11877 11:32:40.971662 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
11878 11:32:40.971957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
11879 11:32:40.972055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
11880 11:32:40.972158 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
11881 11:32:40.972448 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
11882 11:32:40.972540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
11883 11:32:40.972844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
11884 11:32:40.973137 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
11885 11:32:40.973248 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
11886 11:32:40.973352 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
11887 11:32:40.973656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
11888 11:32:40.973775 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
11889 11:32:40.973879 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
11890 11:32:40.973979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
11891 11:32:40.974277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
11892 11:32:40.978579 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
11893 11:32:40.988757 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
11894 11:32:40.989218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
11895 11:32:40.989331 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
11896 11:32:40.989443 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
11897 11:32:40.989533 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
11898 11:32:40.989632 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
11899 11:32:40.989933 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
11900 11:32:40.990043 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
11901 11:32:40.990149 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
11902 11:32:40.990484 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
11903 11:32:40.990769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
11904 11:32:40.990864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
11905 11:32:40.991165 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
11906 11:32:40.991270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
11907 11:32:40.991374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
11908 11:32:40.991673 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
11909 11:32:40.991796 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
11910 11:32:40.991898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
11911 11:32:40.992197 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
11912 11:32:40.992316 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
11913 11:32:40.992419 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
11914 11:32:40.992706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
11915 11:32:40.993029 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
11916 11:32:40.993137 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
11917 11:32:40.993237 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
11918 11:32:40.993338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
11919 11:32:40.993633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
11920 11:32:40.993750 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
11921 11:32:40.993861 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
11922 11:32:40.993994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
11923 11:32:40.994272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
11924 11:32:40.998679 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
11925 11:32:40.998916 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
11926 11:32:40.999009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
11927 11:32:40.999112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
11928 11:32:40.999414 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
11929 11:32:40.999532 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
11930 11:32:40.999836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
11931 11:32:40.999952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
11932 11:32:41.000237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
11933 11:32:41.000344 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
11934 11:32:41.000645 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
11935 11:32:41.000951 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
11936 11:32:41.001059 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
11937 11:32:41.001161 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
11938 11:32:41.001447 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
11939 11:32:41.001755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
11940 11:32:41.001872 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
11941 11:32:41.001975 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
11942 11:32:41.002074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
11943 11:32:41.006413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
11944 11:32:41.006839 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
11945 11:32:41.006943 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
11946 11:32:41.007048 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
11947 11:32:41.007153 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
11948 11:32:41.007453 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
11949 11:32:41.007558 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
11950 11:32:41.007661 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
11951 11:32:41.007963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
11952 11:32:41.008080 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
11953 11:32:41.008192 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
11954 11:32:41.008501 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
11955 11:32:41.008610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
11956 11:32:41.008897 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
11957 11:32:41.009004 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
11958 11:32:41.009286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
11959 11:32:41.009381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
11960 11:32:41.009666 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
11961 11:32:41.009774 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
11962 11:32:41.009878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
11963 11:32:41.009979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
11964 11:32:41.014415 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
11965 11:32:41.014854 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
11966 11:32:41.014952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
11967 11:32:41.015042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
11968 11:32:41.015131 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
11969 11:32:41.015218 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
11970 11:32:41.015518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
11971 11:32:41.015624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
11972 11:32:41.015906 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
11973 11:32:41.016015 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
11974 11:32:41.016310 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
11975 11:32:41.016591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
11976 11:32:41.016685 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
11977 11:32:41.016778 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
11978 11:32:41.017061 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
11979 11:32:41.017159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
11980 11:32:41.017282 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
11981 11:32:41.017585 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
11982 11:32:41.017702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
11983 11:32:41.017995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
11984 11:32:41.018264 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
11985 11:32:41.022402 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
11986 11:32:41.022814 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
11987 11:32:41.022907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
11988 11:32:41.022993 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
11989 11:32:41.023080 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
11990 11:32:41.023354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
11991 11:32:41.023672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
11992 11:32:41.023792 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
11993 11:32:41.023898 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
11994 11:32:41.024215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
11995 11:32:41.024337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
11996 11:32:41.024441 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
11997 11:32:41.024739 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
11998 11:32:41.024847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
11999 11:32:41.025128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12000 11:32:41.025394 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12001 11:32:41.025467 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12002 11:32:41.025748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12003 11:32:41.025865 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12004 11:32:41.026153 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12005 11:32:41.030472 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12006 11:32:41.030893 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12007 11:32:41.030978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12008 11:32:41.031044 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12009 11:32:41.031138 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12010 11:32:41.031221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12011 11:32:41.031537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12012 11:32:41.031642 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12013 11:32:41.031732 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12014 11:32:41.032033 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12015 11:32:41.032337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12016 11:32:41.032437 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12017 11:32:41.032540 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12018 11:32:41.032646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12019 11:32:41.032750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12020 11:32:41.033052 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12021 11:32:41.033149 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12022 11:32:41.033269 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12023 11:32:41.033388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12024 11:32:41.033691 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12025 11:32:41.033789 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12026 11:32:41.033897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12027 11:32:41.052420 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12028 11:32:41.052672 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12029 11:32:41.052995 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12030 11:32:41.053102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12031 11:32:41.053214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12032 11:32:41.053329 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12033 11:32:41.053475 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12034 11:32:41.053590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12035 11:32:41.053704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12036 11:32:41.053835 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12037 11:32:41.053929 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12038 11:32:41.054051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12039 11:32:41.054154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12040 11:32:41.054246 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12041 11:32:41.054698 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12042 11:32:41.055059 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12043 11:32:41.055164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12044 11:32:41.055256 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12045 11:32:41.055568 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12046 11:32:41.055672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12047 11:32:41.055760 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12048 11:32:41.055867 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12049 11:32:41.055963 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12050 11:32:41.056060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12051 11:32:41.056156 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12052 11:32:41.056454 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12053 11:32:41.056571 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12054 11:32:41.056880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12055 11:32:41.056983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12056 11:32:41.057277 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12057 11:32:41.057380 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12058 11:32:41.057465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12059 11:32:41.057755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12060 11:32:41.057864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12061 11:32:41.057951 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12062 11:32:41.058054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12063 11:32:41.058154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12064 11:32:41.058443 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12065 11:32:41.058546 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12066 11:32:41.062860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12067 11:32:41.063059 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12068 11:32:41.063164 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12069 11:32:41.063262 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12070 11:32:41.063349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12071 11:32:41.063450 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12072 11:32:41.063980 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12073 11:32:41.064087 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12074 11:32:41.064241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12075 11:32:41.064352 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12076 11:32:41.064443 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12077 11:32:41.064529 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12078 11:32:41.064637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12079 11:32:41.064727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12080 11:32:41.064833 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12081 11:32:41.064942 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12082 11:32:41.065036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12083 11:32:41.065349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12084 11:32:41.065453 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12085 11:32:41.065545 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12086 11:32:41.065644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12087 11:32:41.065741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12088 11:32:41.066037 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12089 11:32:41.066146 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12090 11:32:41.066235 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12091 11:32:41.066321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12092 11:32:41.066426 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12093 11:32:41.066515 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12094 11:32:41.066616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12095 11:32:41.066921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12096 11:32:41.067037 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12097 11:32:41.067131 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12098 11:32:41.067221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12099 11:32:41.074568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12100 11:32:41.075146 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12101 11:32:41.075302 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12102 11:32:41.075394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12103 11:32:41.075478 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12104 11:32:41.075560 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12105 11:32:41.075658 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12106 11:32:41.075988 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12107 11:32:41.076113 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12108 11:32:41.076204 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12109 11:32:41.076291 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12110 11:32:41.076372 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12111 11:32:41.076660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12112 11:32:41.076764 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12113 11:32:41.076853 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12114 11:32:41.076937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12115 11:32:41.077018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12116 11:32:41.077115 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12117 11:32:41.077202 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12118 11:32:41.077287 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12119 11:32:41.077386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12120 11:32:41.077490 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12121 11:32:41.077591 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12122 11:32:41.077702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12123 11:32:41.078052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12124 11:32:41.078157 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12125 11:32:41.078255 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12126 11:32:41.082455 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12127 11:32:41.082830 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12128 11:32:41.082950 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12129 11:32:41.083053 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12130 11:32:41.083154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12131 11:32:41.083459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12132 11:32:41.083584 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12133 11:32:41.083738 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12134 11:32:41.083854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12135 11:32:41.084157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12136 11:32:41.084261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12137 11:32:41.084362 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12138 11:32:41.084739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12139 11:32:41.085024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12140 11:32:41.085136 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12141 11:32:41.085226 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12142 11:32:41.085312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12143 11:32:41.085417 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12144 11:32:41.085511 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12145 11:32:41.085810 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12146 11:32:41.085912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12147 11:32:41.086022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12148 11:32:41.086127 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12149 11:32:41.090476 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12150 11:32:41.090906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12151 11:32:41.091009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12152 11:32:41.091108 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12153 11:32:41.091229 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12154 11:32:41.091327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12155 11:32:41.091458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12156 11:32:41.091583 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12157 11:32:41.091678 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12158 11:32:41.091777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12159 11:32:41.091967 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12160 11:32:41.092272 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12161 11:32:41.109322 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12162 11:32:41.109574 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12163 11:32:41.109892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12164 11:32:41.109996 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12165 11:32:41.110079 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12166 11:32:41.110172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12167 11:32:41.110252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12168 11:32:41.110910 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12169 11:32:41.111029 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12170 11:32:41.111313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12171 11:32:41.111437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12172 11:32:41.111735 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12173 11:32:41.111857 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12174 11:32:41.111960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12175 11:32:41.112259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12176 11:32:41.112381 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12177 11:32:41.112653 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12178 11:32:41.112762 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12179 11:32:41.112864 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12180 11:32:41.113060 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12181 11:32:41.113178 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12182 11:32:41.113279 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12183 11:32:41.113562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12184 11:32:41.113696 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12185 11:32:41.113796 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12186 11:32:41.114143 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12187 11:32:41.114421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12188 11:32:41.118525 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12189 11:32:41.118968 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12190 11:32:41.119079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12191 11:32:41.119172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12192 11:32:41.119280 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12193 11:32:41.119592 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12194 11:32:41.119681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12195 11:32:41.119990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12196 11:32:41.120111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12197 11:32:41.120191 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12198 11:32:41.120473 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12199 11:32:41.120761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12200 11:32:41.120879 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12201 11:32:41.121165 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12202 11:32:41.121259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12203 11:32:41.121524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12204 11:32:41.121629 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12205 11:32:41.121741 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12206 11:32:41.122009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12207 11:32:41.126487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12208 11:32:41.126864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12209 11:32:41.126957 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12210 11:32:41.127033 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12211 11:32:41.127125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12212 11:32:41.127602 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12213 11:32:41.127722 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12214 11:32:41.127850 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12215 11:32:41.127978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12216 11:32:41.128111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12217 11:32:41.128414 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12218 11:32:41.128534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12219 11:32:41.128642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12220 11:32:41.128938 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12221 11:32:41.129040 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12222 11:32:41.129142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12223 11:32:41.129438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12224 11:32:41.129547 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12225 11:32:41.129676 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12226 11:32:41.129988 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12227 11:32:41.130111 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12228 11:32:41.134640 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12229 11:32:41.134869 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12230 11:32:41.134990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12231 11:32:41.135070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12232 11:32:41.135167 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12233 11:32:41.135498 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12234 11:32:41.135632 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12235 11:32:41.135762 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12236 11:32:41.135887 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12237 11:32:41.136017 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12238 11:32:41.136343 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12239 11:32:41.136464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12240 11:32:41.136658 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12241 11:32:41.136958 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12242 11:32:41.137080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12243 11:32:41.137199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12244 11:32:41.137396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12245 11:32:41.137697 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12246 11:32:41.137816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12247 11:32:41.138146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12248 11:32:41.138271 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12249 11:32:41.143058 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12250 11:32:41.143276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12251 11:32:41.143369 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12252 11:32:41.143659 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12253 11:32:41.143764 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12254 11:32:41.143853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12255 11:32:41.143938 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12256 11:32:41.144042 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12257 11:32:41.144134 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12258 11:32:41.144241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12259 11:32:41.144349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12260 11:32:41.144657 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12261 11:32:41.144752 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12262 11:32:41.145020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12263 11:32:41.145114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12264 11:32:41.145406 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12265 11:32:41.145505 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12266 11:32:41.145593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12267 11:32:41.146070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12268 11:32:41.146176 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12269 11:32:41.146284 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12270 11:32:41.150658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12271 11:32:41.150885 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12272 11:32:41.150994 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12273 11:32:41.151103 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12274 11:32:41.151420 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12275 11:32:41.151546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12276 11:32:41.151841 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12277 11:32:41.151941 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12278 11:32:41.152043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12279 11:32:41.152337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12280 11:32:41.152632 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12281 11:32:41.152724 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12282 11:32:41.152824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12283 11:32:41.153112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12284 11:32:41.153218 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12285 11:32:41.153323 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12286 11:32:41.153592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12287 11:32:41.153728 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12288 11:32:41.154031 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12289 11:32:41.154135 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12290 11:32:41.158379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12291 11:32:41.158813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12292 11:32:41.158928 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12293 11:32:41.159038 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12294 11:32:41.159120 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12295 11:32:41.168390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12296 11:32:41.168806 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12297 11:32:41.168919 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12298 11:32:41.169012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12299 11:32:41.169116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12300 11:32:41.169219 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12301 11:32:41.169518 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12302 11:32:41.169625 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12303 11:32:41.169744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12304 11:32:41.170053 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12305 11:32:41.170176 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12306 11:32:41.170662 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12307 11:32:41.170787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12308 11:32:41.171081 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12309 11:32:41.171198 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12310 11:32:41.171309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12311 11:32:41.171607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12312 11:32:41.171724 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12313 11:32:41.172027 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12314 11:32:41.172134 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12315 11:32:41.172237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12316 11:32:41.172528 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12317 11:32:41.172638 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12318 11:32:41.172741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12319 11:32:41.173389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12320 11:32:41.173763 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12321 11:32:41.173873 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12322 11:32:41.173961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12323 11:32:41.174251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12324 11:32:41.174363 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12325 11:32:41.174449 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12326 11:32:41.174535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12327 11:32:41.178685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12328 11:32:41.179096 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12329 11:32:41.179197 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12330 11:32:41.179309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12331 11:32:41.179581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12332 11:32:41.180070 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12333 11:32:41.180157 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12334 11:32:41.180427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12335 11:32:41.180500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12336 11:32:41.180592 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12337 11:32:41.180681 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12338 11:32:41.180969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12339 11:32:41.181250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12340 11:32:41.181337 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12341 11:32:41.181690 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12342 11:32:41.181964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12343 11:32:41.182051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12344 11:32:41.182141 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12345 11:32:41.182225 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12346 11:32:41.182318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12347 11:32:41.182405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12348 11:32:41.185733 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12349 11:32:41.190509 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12350 11:32:41.190923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12351 11:32:41.191028 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12352 11:32:41.191122 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12353 11:32:41.191231 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12354 11:32:41.191328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12355 11:32:41.191426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12356 11:32:41.191741 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12357 11:32:41.191854 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12358 11:32:41.191956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12359 11:32:41.192255 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12360 11:32:41.192367 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12361 11:32:41.192485 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12362 11:32:41.192794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12363 11:32:41.192897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12364 11:32:41.193162 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12365 11:32:41.193231 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12366 11:32:41.193480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12367 11:32:41.193771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12368 11:32:41.194139 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12369 11:32:41.194251 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12370 11:32:41.198397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12371 11:32:41.198763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12372 11:32:41.198851 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12373 11:32:41.198968 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12374 11:32:41.199080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12375 11:32:41.199222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12376 11:32:41.199516 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12377 11:32:41.199619 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12378 11:32:41.199877 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12379 11:32:41.199956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12380 11:32:41.200205 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12381 11:32:41.200282 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12382 11:32:41.200536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12383 11:32:41.200613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12384 11:32:41.200866 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12385 11:32:41.200943 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12386 11:32:41.201190 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12387 11:32:41.201436 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12388 11:32:41.201675 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12389 11:32:41.201744 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12390 11:32:41.201991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12391 11:32:41.202079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12392 11:32:41.206506 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12393 11:32:41.206856 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12394 11:32:41.206941 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12395 11:32:41.207189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12396 11:32:41.207261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12397 11:32:41.207683 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12398 11:32:41.207797 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12399 11:32:41.207891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12400 11:32:41.208187 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12401 11:32:41.208292 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12402 11:32:41.208396 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12403 11:32:41.208484 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12404 11:32:41.208777 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12405 11:32:41.208890 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12406 11:32:41.208995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12407 11:32:41.209100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12408 11:32:41.209391 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12409 11:32:41.209498 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12410 11:32:41.209610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12411 11:32:41.209933 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12412 11:32:41.210054 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12413 11:32:41.214379 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12414 11:32:41.214819 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12415 11:32:41.214909 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12416 11:32:41.215021 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12417 11:32:41.215128 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12418 11:32:41.215248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12419 11:32:41.215362 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12420 11:32:41.215676 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12421 11:32:41.215774 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12422 11:32:41.215862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12423 11:32:41.215948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12424 11:32:41.216230 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12425 11:32:41.216322 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12426 11:32:41.216409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12427 11:32:41.216675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12428 11:32:41.216763 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12429 11:32:41.228925 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12430 11:32:41.229358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12431 11:32:41.229438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12432 11:32:41.229523 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12433 11:32:41.229598 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12434 11:32:41.229693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12435 11:32:41.229961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12436 11:32:41.230229 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12437 11:32:41.230490 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12438 11:32:41.230758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12439 11:32:41.230852 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12440 11:32:41.230939 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12441 11:32:41.231039 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12442 11:32:41.231140 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12443 11:32:41.231452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12444 11:32:41.231550 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12445 11:32:41.231629 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12446 11:32:41.231935 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12447 11:32:41.232051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12448 11:32:41.232355 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12449 11:32:41.232452 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12450 11:32:41.232527 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12451 11:32:41.232612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12452 11:32:41.232943 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12453 11:32:41.233049 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12454 11:32:41.233150 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12455 11:32:41.233262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12456 11:32:41.233545 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12457 11:32:41.233664 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12458 11:32:41.233787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12459 11:32:41.234112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12460 11:32:41.234218 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12461 11:32:41.238651 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12462 11:32:41.238868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12463 11:32:41.238971 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12464 11:32:41.239270 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12465 11:32:41.239372 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12466 11:32:41.239477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12467 11:32:41.239789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12468 11:32:41.239907 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12469 11:32:41.240010 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12470 11:32:41.240308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12471 11:32:41.240416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12472 11:32:41.240715 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12473 11:32:41.240823 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12474 11:32:41.240924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12475 11:32:41.241216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12476 11:32:41.241328 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12477 11:32:41.241608 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12478 11:32:41.241745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12479 11:32:41.241855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12480 11:32:41.242161 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12481 11:32:41.246604 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12482 11:32:41.247060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12483 11:32:41.247145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12484 11:32:41.247225 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12485 11:32:41.247345 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12486 11:32:41.247427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12487 11:32:41.247700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12488 11:32:41.248005 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12489 11:32:41.248106 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12490 11:32:41.248214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12491 11:32:41.248308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12492 11:32:41.248414 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12493 11:32:41.248712 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12494 11:32:41.249004 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12495 11:32:41.249382 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12496 11:32:41.249500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12497 11:32:41.249587 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12498 11:32:41.249684 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12499 11:32:41.249790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12500 11:32:41.250080 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12501 11:32:41.250186 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12502 11:32:41.250294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12503 11:32:41.254542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12504 11:32:41.254985 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12505 11:32:41.255087 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12506 11:32:41.255198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12507 11:32:41.255503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12508 11:32:41.255616 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12509 11:32:41.255720 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12510 11:32:41.256008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12511 11:32:41.256112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12512 11:32:41.256398 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12513 11:32:41.256503 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12514 11:32:41.256993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12515 11:32:41.257099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12516 11:32:41.257388 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12517 11:32:41.257481 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12518 11:32:41.257766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12519 11:32:41.257873 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12520 11:32:41.257975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12521 11:32:41.258263 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12522 11:32:41.262618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12523 11:32:41.263070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12524 11:32:41.263189 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12525 11:32:41.263285 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12526 11:32:41.263386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12527 11:32:41.263487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12528 11:32:41.263598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12529 11:32:41.263916 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12530 11:32:41.264043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12531 11:32:41.264141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12532 11:32:41.264250 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12533 11:32:41.264359 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12534 11:32:41.264658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12535 11:32:41.264997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12536 11:32:41.265285 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12537 11:32:41.265376 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12538 11:32:41.265466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12539 11:32:41.265575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12540 11:32:41.265701 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12541 11:32:41.265813 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12542 11:32:41.266110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12543 11:32:41.270602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12544 11:32:41.271025 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12545 11:32:41.271115 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12546 11:32:41.271196 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12547 11:32:41.271498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12548 11:32:41.271608 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12549 11:32:41.271706 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12550 11:32:41.271796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12551 11:32:41.271900 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12552 11:32:41.272193 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12553 11:32:41.272289 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12554 11:32:41.272551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12555 11:32:41.272811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12556 11:32:41.272892 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12557 11:32:41.273165 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12558 11:32:41.273256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12559 11:32:41.273333 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12560 11:32:41.273589 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12561 11:32:41.273687 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12562 11:32:41.273945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12563 11:32:41.297052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12564 11:32:41.297532 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12565 11:32:41.297644 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12566 11:32:41.297743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12567 11:32:41.297825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12568 11:32:41.297927 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12569 11:32:41.298013 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12570 11:32:41.298121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12571 11:32:41.298721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12572 11:32:41.299009 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12573 11:32:41.299311 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12574 11:32:41.299407 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12575 11:32:41.299705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12576 11:32:41.300001 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12577 11:32:41.300086 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12578 11:32:41.300178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12579 11:32:41.300444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12580 11:32:41.300574 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12581 11:32:41.300859 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12582 11:32:41.301157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12583 11:32:41.301251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12584 11:32:41.301349 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12585 11:32:41.301639 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12586 11:32:41.301762 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12587 11:32:41.301864 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12588 11:32:41.302168 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12589 11:32:41.306752 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12590 11:32:41.307185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12591 11:32:41.307291 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12592 11:32:41.307386 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12593 11:32:41.307684 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12594 11:32:41.307801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12595 11:32:41.308094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12596 11:32:41.308207 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12597 11:32:41.308493 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12598 11:32:41.308606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12599 11:32:41.308904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12600 11:32:41.309015 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12601 11:32:41.309305 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12602 11:32:41.309427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12603 11:32:41.309710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12604 11:32:41.309823 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12605 11:32:41.310116 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12606 11:32:41.314729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12607 11:32:41.315193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12608 11:32:41.315286 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12609 11:32:41.315383 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12610 11:32:41.315465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12611 11:32:41.315833 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12612 11:32:41.315932 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12613 11:32:41.316299 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12614 11:32:41.316398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12615 11:32:41.316478 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12616 11:32:41.316555 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12617 11:32:41.316817 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12618 11:32:41.316890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12619 11:32:41.316958 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12620 11:32:41.317039 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12621 11:32:41.317120 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12622 11:32:41.317690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12623 11:32:41.317767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12624 11:32:41.317856 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12625 11:32:41.318328 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12626 11:32:41.318424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12627 11:32:41.323179 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12628 11:32:41.323416 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12629 11:32:41.323509 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12630 11:32:41.323833 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12631 11:32:41.323925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12632 11:32:41.324010 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12633 11:32:41.324117 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12634 11:32:41.324412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12635 11:32:41.324513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12636 11:32:41.324839 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12637 11:32:41.324948 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12638 11:32:41.325229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12639 11:32:41.325310 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12640 11:32:41.325573 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12641 11:32:41.325709 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12642 11:32:41.325837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12643 11:32:41.325964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12644 11:32:41.326290 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12645 11:32:41.330804 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12646 11:32:41.331217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12647 11:32:41.331318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12648 11:32:41.331426 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12649 11:32:41.331529 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12650 11:32:41.331826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12651 11:32:41.331943 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12652 11:32:41.332044 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12653 11:32:41.332146 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12654 11:32:41.332457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12655 11:32:41.332593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12656 11:32:41.332912 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12657 11:32:41.333029 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12658 11:32:41.333142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12659 11:32:41.333252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12660 11:32:41.333573 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12661 11:32:41.333711 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12662 11:32:41.333824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12663 11:32:41.334618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12664 11:32:41.338470 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12665 11:32:41.338905 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12666 11:32:41.339009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12667 11:32:41.339108 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12668 11:32:41.339208 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12669 11:32:41.339492 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12670 11:32:41.339607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12671 11:32:41.339707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12672 11:32:41.339806 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12673 11:32:41.340102 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12674 11:32:41.340207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12675 11:32:41.340499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12676 11:32:41.340591 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12677 11:32:41.340690 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12678 11:32:41.340975 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12679 11:32:41.341077 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12680 11:32:41.341369 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12681 11:32:41.341484 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12682 11:32:41.341787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12683 11:32:41.341900 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12684 11:32:41.342004 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12685 11:32:41.346385 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12686 11:32:41.346833 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12687 11:32:41.347147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12688 11:32:41.347257 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12689 11:32:41.347352 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12690 11:32:41.347464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12691 11:32:41.347572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12692 11:32:41.347684 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12693 11:32:41.347795 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12694 11:32:41.347905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12695 11:32:41.348220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12696 11:32:41.348344 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12697 11:32:41.364967 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12698 11:32:41.365438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12699 11:32:41.365546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12700 11:32:41.365637 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12701 11:32:41.365758 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12702 11:32:41.365850 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12703 11:32:41.365957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12704 11:32:41.366270 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12705 11:32:41.366394 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12706 11:32:41.366691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12707 11:32:41.367009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12708 11:32:41.367133 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12709 11:32:41.367246 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12710 11:32:41.367560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12711 11:32:41.367680 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12712 11:32:41.367987 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12713 11:32:41.368091 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12714 11:32:41.368195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12715 11:32:41.368338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12716 11:32:41.368668 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12717 11:32:41.368778 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12718 11:32:41.368881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12719 11:32:41.369184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12720 11:32:41.369290 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12721 11:32:41.369394 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12722 11:32:41.369499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12723 11:32:41.369801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12724 11:32:41.369919 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12725 11:32:41.370023 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12726 11:32:41.374487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12727 11:32:41.374931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12728 11:32:41.375038 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12729 11:32:41.375129 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12730 11:32:41.375234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12731 11:32:41.375325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12732 11:32:41.375445 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12733 11:32:41.375551 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12734 11:32:41.375868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12735 11:32:41.375987 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12736 11:32:41.376089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12737 11:32:41.376196 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12738 11:32:41.376506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12739 11:32:41.376626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12740 11:32:41.376730 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12741 11:32:41.376840 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12742 11:32:41.377172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12743 11:32:41.377291 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12744 11:32:41.377396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12745 11:32:41.377712 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12746 11:32:41.377823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12747 11:32:41.377926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12748 11:32:41.378237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12749 11:32:41.382426 arm64_sve-ptrace pass
12750 11:32:41.382865 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12751 11:32:41.382976 arm64_sve-probe-vls_All_vector_lengths_valid pass
12752 11:32:41.383062 arm64_sve-probe-vls pass
12753 11:32:41.383164 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12754 11:32:41.383253 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
12755 11:32:41.383337 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
12756 11:32:41.383440 arm64_vec-syscfg_SVE_current_VL_is_64 pass
12757 11:32:41.383530 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
12758 11:32:41.383628 arm64_vec-syscfg_SVE_prctl_set_min_max pass
12759 11:32:41.383729 arm64_vec-syscfg_SVE_vector_length_used_default pass
12760 11:32:41.383832 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
12761 11:32:41.383940 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
12762 11:32:41.384320 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
12763 11:32:41.384427 arm64_vec-syscfg_SME_default_vector_length_32 pass
12764 11:32:41.384534 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
12765 11:32:41.384630 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
12766 11:32:41.384734 arm64_vec-syscfg_SME_current_VL_is_32 pass
12767 11:32:41.384839 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
12768 11:32:41.385147 arm64_vec-syscfg_SME_prctl_set_min_max pass
12769 11:32:41.385252 arm64_vec-syscfg_SME_vector_length_used_default pass
12770 11:32:41.385357 arm64_vec-syscfg_SME_vector_length_was_inherited pass
12771 11:32:41.385460 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
12772 11:32:41.385564 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
12773 11:32:41.385671 arm64_vec-syscfg pass
12774 11:32:41.385761 arm64_za-fork_fork_test pass
12775 11:32:41.385862 arm64_za-fork pass
12776 11:32:41.385949 arm64_za-ptrace_Set_VL_16 pass
12777 11:32:41.386050 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
12778 11:32:41.386136 arm64_za-ptrace_Data_match_for_VL_16 pass
12779 11:32:41.386235 arm64_za-ptrace_Set_VL_32 pass
12780 11:32:41.390392 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
12781 11:32:41.390837 arm64_za-ptrace_Data_match_for_VL_32 pass
12782 11:32:41.390945 arm64_za-ptrace_Set_VL_48 pass
12783 11:32:41.391034 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
12784 11:32:41.391123 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
12785 11:32:41.391230 arm64_za-ptrace_Set_VL_64 pass
12786 11:32:41.391318 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
12787 11:32:41.391405 arm64_za-ptrace_Data_match_for_VL_64 pass
12788 11:32:41.391491 arm64_za-ptrace_Set_VL_80 pass
12789 11:32:41.391602 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
12790 11:32:41.391692 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
12791 11:32:41.391781 arm64_za-ptrace_Set_VL_96 pass
12792 11:32:41.391885 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
12793 11:32:41.391974 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
12794 11:32:41.392076 arm64_za-ptrace_Set_VL_112 pass
12795 11:32:41.392164 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
12796 11:32:41.392265 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
12797 11:32:41.392355 arm64_za-ptrace_Set_VL_128 pass
12798 11:32:41.392456 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
12799 11:32:41.392561 arm64_za-ptrace_Data_match_for_VL_128 pass
12800 11:32:41.392664 arm64_za-ptrace_Set_VL_144 pass
12801 11:32:41.392767 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
12802 11:32:41.392870 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
12803 11:32:41.392974 arm64_za-ptrace_Set_VL_160 pass
12804 11:32:41.393075 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
12805 11:32:41.393176 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
12806 11:32:41.393316 arm64_za-ptrace_Set_VL_176 pass
12807 11:32:41.393438 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
12808 11:32:41.393753 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
12809 11:32:41.393860 arm64_za-ptrace_Set_VL_192 pass
12810 11:32:41.393966 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
12811 11:32:41.394056 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
12812 11:32:41.394156 arm64_za-ptrace_Set_VL_208 pass
12813 11:32:41.398372 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
12814 11:32:41.398796 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
12815 11:32:41.398909 arm64_za-ptrace_Set_VL_224 pass
12816 11:32:41.399023 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
12817 11:32:41.399126 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
12818 11:32:41.399258 arm64_za-ptrace_Set_VL_240 pass
12819 11:32:41.399367 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
12820 11:32:41.399483 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
12821 11:32:41.399590 arm64_za-ptrace_Set_VL_256 pass
12822 11:32:41.399665 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
12823 11:32:41.399741 arm64_za-ptrace_Data_match_for_VL_256 pass
12824 11:32:41.399831 arm64_za-ptrace_Set_VL_272 pass
12825 11:32:41.399965 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
12826 11:32:41.400062 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
12827 11:32:41.400153 arm64_za-ptrace_Set_VL_288 pass
12828 11:32:41.400249 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
12829 11:32:41.400322 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
12830 11:32:41.400397 arm64_za-ptrace_Set_VL_304 pass
12831 11:32:41.400488 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
12832 11:32:41.400560 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
12833 11:32:41.400651 arm64_za-ptrace_Set_VL_320 pass
12834 11:32:41.400722 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
12835 11:32:41.400813 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
12836 11:32:41.400885 arm64_za-ptrace_Set_VL_336 pass
12837 11:32:41.400994 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
12838 11:32:41.401103 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
12839 11:32:41.401233 arm64_za-ptrace_Set_VL_352 pass
12840 11:32:41.401343 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
12841 11:32:41.401441 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
12842 11:32:41.401529 arm64_za-ptrace_Set_VL_368 pass
12843 11:32:41.401615 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
12844 11:32:41.401742 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
12845 11:32:41.401849 arm64_za-ptrace_Set_VL_384 pass
12846 11:32:41.401966 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
12847 11:32:41.402282 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
12848 11:32:41.406442 arm64_za-ptrace_Set_VL_400 pass
12849 11:32:41.406660 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
12850 11:32:41.406956 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
12851 11:32:41.407065 arm64_za-ptrace_Set_VL_416 pass
12852 11:32:41.407156 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
12853 11:32:41.407245 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
12854 11:32:41.407378 arm64_za-ptrace_Set_VL_432 pass
12855 11:32:41.407463 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
12856 11:32:41.407541 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
12857 11:32:41.407624 arm64_za-ptrace_Set_VL_448 pass
12858 11:32:41.407738 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
12859 11:32:41.407812 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
12860 11:32:41.407903 arm64_za-ptrace_Set_VL_464 pass
12861 11:32:41.407983 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
12862 11:32:41.408116 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
12863 11:32:41.408223 arm64_za-ptrace_Set_VL_480 pass
12864 11:32:41.408334 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
12865 11:32:41.408464 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
12866 11:32:41.408570 arm64_za-ptrace_Set_VL_496 pass
12867 11:32:41.408701 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
12868 11:32:41.425873 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
12869 11:32:41.426122 arm64_za-ptrace_Set_VL_512 pass
12870 11:32:41.426385 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
12871 11:32:41.426481 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
12872 11:32:41.426582 arm64_za-ptrace_Set_VL_528 pass
12873 11:32:41.426702 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
12874 11:32:41.426793 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
12875 11:32:41.426891 arm64_za-ptrace_Set_VL_544 pass
12876 11:32:41.427009 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
12877 11:32:41.427099 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
12878 11:32:41.427217 arm64_za-ptrace_Set_VL_560 pass
12879 11:32:41.427315 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
12880 11:32:41.427444 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
12881 11:32:41.427549 arm64_za-ptrace_Set_VL_576 pass
12882 11:32:41.427655 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
12883 11:32:41.427755 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
12884 11:32:41.427846 arm64_za-ptrace_Set_VL_592 pass
12885 11:32:41.427922 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
12886 11:32:41.427999 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
12887 11:32:41.428077 arm64_za-ptrace_Set_VL_608 pass
12888 11:32:41.428350 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
12889 11:32:41.428455 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
12890 11:32:41.428551 arm64_za-ptrace_Set_VL_624 pass
12891 11:32:41.428666 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
12892 11:32:41.428775 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
12893 11:32:41.428864 arm64_za-ptrace_Set_VL_640 pass
12894 11:32:41.428979 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
12895 11:32:41.429088 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
12896 11:32:41.429197 arm64_za-ptrace_Set_VL_656 pass
12897 11:32:41.429306 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
12898 11:32:41.429610 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
12899 11:32:41.429710 arm64_za-ptrace_Set_VL_672 pass
12900 11:32:41.429807 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
12901 11:32:41.430095 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
12902 11:32:41.430182 arm64_za-ptrace_Set_VL_688 pass
12903 11:32:41.430281 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
12904 11:32:41.430389 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
12905 11:32:41.430463 arm64_za-ptrace_Set_VL_704 pass
12906 11:32:41.434444 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
12907 11:32:41.434675 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
12908 11:32:41.434986 arm64_za-ptrace_Set_VL_720 pass
12909 11:32:41.435092 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
12910 11:32:41.435184 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
12911 11:32:41.435274 arm64_za-ptrace_Set_VL_736 pass
12912 11:32:41.435377 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
12913 11:32:41.435469 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
12914 11:32:41.435556 arm64_za-ptrace_Set_VL_752 pass
12915 11:32:41.435657 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
12916 11:32:41.435742 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
12917 11:32:41.435843 arm64_za-ptrace_Set_VL_768 pass
12918 11:32:41.435932 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
12919 11:32:41.436035 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
12920 11:32:41.436139 arm64_za-ptrace_Set_VL_784 pass
12921 11:32:41.436225 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
12922 11:32:41.436362 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
12923 11:32:41.436486 arm64_za-ptrace_Set_VL_800 pass
12924 11:32:41.436590 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
12925 11:32:41.436891 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
12926 11:32:41.436977 arm64_za-ptrace_Set_VL_816 pass
12927 11:32:41.437095 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
12928 11:32:41.437187 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
12929 11:32:41.437296 arm64_za-ptrace_Set_VL_832 pass
12930 11:32:41.437372 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
12931 11:32:41.437463 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
12932 11:32:41.437741 arm64_za-ptrace_Set_VL_848 pass
12933 11:32:41.437858 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
12934 11:32:41.437987 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
12935 11:32:41.438094 arm64_za-ptrace_Set_VL_864 pass
12936 11:32:41.438221 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
12937 11:32:41.442374 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
12938 11:32:41.442722 arm64_za-ptrace_Set_VL_880 pass
12939 11:32:41.442812 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
12940 11:32:41.442910 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
12941 11:32:41.443024 arm64_za-ptrace_Set_VL_896 pass
12942 11:32:41.443153 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
12943 11:32:41.443261 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
12944 11:32:41.443376 arm64_za-ptrace_Set_VL_912 pass
12945 11:32:41.443469 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
12946 11:32:41.443570 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
12947 11:32:41.443657 arm64_za-ptrace_Set_VL_928 pass
12948 11:32:41.443750 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
12949 11:32:41.443824 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
12950 11:32:41.443896 arm64_za-ptrace_Set_VL_944 pass
12951 11:32:41.444164 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
12952 11:32:41.444249 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
12953 11:32:41.444358 arm64_za-ptrace_Set_VL_960 pass
12954 11:32:41.444433 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
12955 11:32:41.444524 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
12956 11:32:41.444805 arm64_za-ptrace_Set_VL_976 pass
12957 11:32:41.444908 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
12958 11:32:41.445011 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
12959 11:32:41.445095 arm64_za-ptrace_Set_VL_992 pass
12960 11:32:41.445171 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
12961 11:32:41.445422 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
12962 11:32:41.445489 arm64_za-ptrace_Set_VL_1008 pass
12963 11:32:41.445562 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
12964 11:32:41.445806 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
12965 11:32:41.445890 arm64_za-ptrace_Set_VL_1024 pass
12966 11:32:41.446175 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
12967 11:32:41.450402 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
12968 11:32:41.450821 arm64_za-ptrace_Set_VL_1040 pass
12969 11:32:41.450920 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
12970 11:32:41.450995 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
12971 11:32:41.451085 arm64_za-ptrace_Set_VL_1056 pass
12972 11:32:41.451160 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
12973 11:32:41.451260 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
12974 11:32:41.451349 arm64_za-ptrace_Set_VL_1072 pass
12975 11:32:41.451458 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
12976 11:32:41.451762 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
12977 11:32:41.451857 arm64_za-ptrace_Set_VL_1088 pass
12978 11:32:41.451942 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
12979 11:32:41.452028 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
12980 11:32:41.452293 arm64_za-ptrace_Set_VL_1104 pass
12981 11:32:41.452371 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
12982 11:32:41.452455 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
12983 11:32:41.452717 arm64_za-ptrace_Set_VL_1120 pass
12984 11:32:41.452794 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
12985 11:32:41.452877 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
12986 11:32:41.453138 arm64_za-ptrace_Set_VL_1136 pass
12987 11:32:41.453224 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
12988 11:32:41.453307 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
12989 11:32:41.453596 arm64_za-ptrace_Set_VL_1152 pass
12990 11:32:41.453711 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
12991 11:32:41.453813 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
12992 11:32:41.453915 arm64_za-ptrace_Set_VL_1168 pass
12993 11:32:41.454218 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
12994 11:32:41.458500 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
12995 11:32:41.458851 arm64_za-ptrace_Set_VL_1184 pass
12996 11:32:41.458948 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
12997 11:32:41.459022 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
12998 11:32:41.459108 arm64_za-ptrace_Set_VL_1200 pass
12999 11:32:41.459180 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13000 11:32:41.459263 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13001 11:32:41.459335 arm64_za-ptrace_Set_VL_1216 pass
13002 11:32:41.459416 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13003 11:32:41.459712 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13004 11:32:41.459805 arm64_za-ptrace_Set_VL_1232 pass
13005 11:32:41.459892 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13006 11:32:41.459978 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13007 11:32:41.460069 arm64_za-ptrace_Set_VL_1248 pass
13008 11:32:41.460355 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13009 11:32:41.460477 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13010 11:32:41.460571 arm64_za-ptrace_Set_VL_1264 pass
13011 11:32:41.460679 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13012 11:32:41.460771 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13013 11:32:41.460878 arm64_za-ptrace_Set_VL_1280 pass
13014 11:32:41.460981 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13015 11:32:41.461079 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13016 11:32:41.461183 arm64_za-ptrace_Set_VL_1296 pass
13017 11:32:41.461487 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13018 11:32:41.461592 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13019 11:32:41.461707 arm64_za-ptrace_Set_VL_1312 pass
13020 11:32:41.461796 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13021 11:32:41.461897 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13022 11:32:41.462000 arm64_za-ptrace_Set_VL_1328 pass
13023 11:32:41.462089 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13024 11:32:41.466483 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13025 11:32:41.466924 arm64_za-ptrace_Set_VL_1344 pass
13026 11:32:41.467034 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13027 11:32:41.467123 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13028 11:32:41.467229 arm64_za-ptrace_Set_VL_1360 pass
13029 11:32:41.467318 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13030 11:32:41.467415 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13031 11:32:41.467497 arm64_za-ptrace_Set_VL_1376 pass
13032 11:32:41.467592 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13033 11:32:41.467694 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13034 11:32:41.467778 arm64_za-ptrace_Set_VL_1392 pass
13035 11:32:41.467873 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13036 11:32:41.468168 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13037 11:32:41.468272 arm64_za-ptrace_Set_VL_1408 pass
13038 11:32:41.468375 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13039 11:32:41.468477 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13040 11:32:41.468565 arm64_za-ptrace_Set_VL_1424 pass
13041 11:32:41.468672 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13042 11:32:41.468775 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13043 11:32:41.468882 arm64_za-ptrace_Set_VL_1440 pass
13044 11:32:41.468983 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13045 11:32:41.469292 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13046 11:32:41.469394 arm64_za-ptrace_Set_VL_1456 pass
13047 11:32:41.469478 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13048 11:32:41.469579 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13049 11:32:41.469683 arm64_za-ptrace_Set_VL_1472 pass
13050 11:32:41.469786 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13051 11:32:41.469889 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13052 11:32:41.470145 arm64_za-ptrace_Set_VL_1488 pass
13053 11:32:41.470250 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13054 11:32:41.474385 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13055 11:32:41.475004 arm64_za-ptrace_Set_VL_1504 pass
13056 11:32:41.475113 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13057 11:32:41.475203 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13058 11:32:41.475275 arm64_za-ptrace_Set_VL_1520 pass
13059 11:32:41.475361 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13060 11:32:41.475638 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13061 11:32:41.475744 arm64_za-ptrace_Set_VL_1536 pass
13062 11:32:41.475820 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13063 11:32:41.490951 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13064 11:32:41.491389 arm64_za-ptrace_Set_VL_1552 pass
13065 11:32:41.491492 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13066 11:32:41.491572 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13067 11:32:41.491658 arm64_za-ptrace_Set_VL_1568 pass
13068 11:32:41.491746 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13069 11:32:41.492038 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13070 11:32:41.492143 arm64_za-ptrace_Set_VL_1584 pass
13071 11:32:41.492233 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13072 11:32:41.492311 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13073 11:32:41.492372 arm64_za-ptrace_Set_VL_1600 pass
13074 11:32:41.492431 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13075 11:32:41.492491 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13076 11:32:41.492550 arm64_za-ptrace_Set_VL_1616 pass
13077 11:32:41.492608 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13078 11:32:41.492682 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13079 11:32:41.492744 arm64_za-ptrace_Set_VL_1632 pass
13080 11:32:41.492804 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13081 11:32:41.492863 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13082 11:32:41.492922 arm64_za-ptrace_Set_VL_1648 pass
13083 11:32:41.492999 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13084 11:32:41.493060 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13085 11:32:41.493119 arm64_za-ptrace_Set_VL_1664 pass
13086 11:32:41.493190 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13087 11:32:41.493262 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13088 11:32:41.493364 arm64_za-ptrace_Set_VL_1680 pass
13089 11:32:41.493490 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13090 11:32:41.493602 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13091 11:32:41.493735 arm64_za-ptrace_Set_VL_1696 pass
13092 11:32:41.493848 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13093 11:32:41.493949 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13094 11:32:41.494046 arm64_za-ptrace_Set_VL_1712 pass
13095 11:32:41.494158 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13096 11:32:41.498471 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13097 11:32:41.498886 arm64_za-ptrace_Set_VL_1728 pass
13098 11:32:41.498994 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13099 11:32:41.499083 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13100 11:32:41.499168 arm64_za-ptrace_Set_VL_1744 pass
13101 11:32:41.499242 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13102 11:32:41.499333 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13103 11:32:41.499398 arm64_za-ptrace_Set_VL_1760 pass
13104 11:32:41.499493 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13105 11:32:41.499604 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13106 11:32:41.499679 arm64_za-ptrace_Set_VL_1776 pass
13107 11:32:41.499762 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13108 11:32:41.499834 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13109 11:32:41.499916 arm64_za-ptrace_Set_VL_1792 pass
13110 11:32:41.499999 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13111 11:32:41.500297 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13112 11:32:41.500392 arm64_za-ptrace_Set_VL_1808 pass
13113 11:32:41.500479 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13114 11:32:41.500745 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13115 11:32:41.500822 arm64_za-ptrace_Set_VL_1824 pass
13116 11:32:41.500906 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13117 11:32:41.501168 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13118 11:32:41.501245 arm64_za-ptrace_Set_VL_1840 pass
13119 11:32:41.501327 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13120 11:32:41.501599 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13121 11:32:41.501685 arm64_za-ptrace_Set_VL_1856 pass
13122 11:32:41.501774 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13123 11:32:41.501858 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13124 11:32:41.501943 arm64_za-ptrace_Set_VL_1872 pass
13125 11:32:41.502233 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13126 11:32:41.506439 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13127 11:32:41.506850 arm64_za-ptrace_Set_VL_1888 pass
13128 11:32:41.506959 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13129 11:32:41.507047 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13130 11:32:41.507148 arm64_za-ptrace_Set_VL_1904 pass
13131 11:32:41.507231 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13132 11:32:41.507314 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13133 11:32:41.507415 arm64_za-ptrace_Set_VL_1920 pass
13134 11:32:41.507516 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13135 11:32:41.507616 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13136 11:32:41.507716 arm64_za-ptrace_Set_VL_1936 pass
13137 11:32:41.507816 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13138 11:32:41.507918 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13139 11:32:41.508019 arm64_za-ptrace_Set_VL_1952 pass
13140 11:32:41.508373 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13141 11:32:41.508483 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13142 11:32:41.508589 arm64_za-ptrace_Set_VL_1968 pass
13143 11:32:41.508678 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13144 11:32:41.508783 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13145 11:32:41.508873 arm64_za-ptrace_Set_VL_1984 pass
13146 11:32:41.508975 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13147 11:32:41.509077 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13148 11:32:41.509181 arm64_za-ptrace_Set_VL_2000 pass
13149 11:32:41.509280 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13150 11:32:41.509382 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13151 11:32:41.509483 arm64_za-ptrace_Set_VL_2016 pass
13152 11:32:41.509790 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13153 11:32:41.509910 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13154 11:32:41.510013 arm64_za-ptrace_Set_VL_2032 pass
13155 11:32:41.510117 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13156 11:32:41.510216 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13157 11:32:41.510317 arm64_za-ptrace_Set_VL_2048 pass
13158 11:32:41.510424 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13159 11:32:41.510731 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13160 11:32:41.510836 arm64_za-ptrace_Set_VL_2064 pass
13161 11:32:41.510935 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13162 11:32:41.511019 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13163 11:32:41.511118 arm64_za-ptrace_Set_VL_2080 pass
13164 11:32:41.511224 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13165 11:32:41.511333 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13166 11:32:41.511646 arm64_za-ptrace_Set_VL_2096 pass
13167 11:32:41.511757 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13168 11:32:41.518398 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13169 11:32:41.518830 arm64_za-ptrace_Set_VL_2112 pass
13170 11:32:41.518927 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13171 11:32:41.519000 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13172 11:32:41.519070 arm64_za-ptrace_Set_VL_2128 pass
13173 11:32:41.519153 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13174 11:32:41.519229 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13175 11:32:41.519328 arm64_za-ptrace_Set_VL_2144 pass
13176 11:32:41.519406 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13177 11:32:41.519686 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13178 11:32:41.519781 arm64_za-ptrace_Set_VL_2160 pass
13179 11:32:41.519853 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13180 11:32:41.519935 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13181 11:32:41.520007 arm64_za-ptrace_Set_VL_2176 pass
13182 11:32:41.520088 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13183 11:32:41.520170 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13184 11:32:41.520254 arm64_za-ptrace_Set_VL_2192 pass
13185 11:32:41.520532 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13186 11:32:41.520625 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13187 11:32:41.520710 arm64_za-ptrace_Set_VL_2208 pass
13188 11:32:41.520792 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13189 11:32:41.520874 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13190 11:32:41.521150 arm64_za-ptrace_Set_VL_2224 pass
13191 11:32:41.521243 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13192 11:32:41.521327 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13193 11:32:41.521410 arm64_za-ptrace_Set_VL_2240 pass
13194 11:32:41.521497 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13195 11:32:41.521780 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13196 11:32:41.521885 arm64_za-ptrace_Set_VL_2256 pass
13197 11:32:41.521971 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13198 11:32:41.522259 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13199 11:32:41.526359 arm64_za-ptrace_Set_VL_2272 pass
13200 11:32:41.526764 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13201 11:32:41.526873 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13202 11:32:41.526961 arm64_za-ptrace_Set_VL_2288 pass
13203 11:32:41.527062 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13204 11:32:41.527148 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13205 11:32:41.527233 arm64_za-ptrace_Set_VL_2304 pass
13206 11:32:41.527331 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13207 11:32:41.527418 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13208 11:32:41.527523 arm64_za-ptrace_Set_VL_2320 pass
13209 11:32:41.527607 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13210 11:32:41.527702 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13211 11:32:41.527801 arm64_za-ptrace_Set_VL_2336 pass
13212 11:32:41.527908 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13213 11:32:41.528007 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13214 11:32:41.528304 arm64_za-ptrace_Set_VL_2352 pass
13215 11:32:41.528411 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13216 11:32:41.528512 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13217 11:32:41.528621 arm64_za-ptrace_Set_VL_2368 pass
13218 11:32:41.528729 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13219 11:32:41.528839 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13220 11:32:41.529147 arm64_za-ptrace_Set_VL_2384 pass
13221 11:32:41.529249 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13222 11:32:41.529350 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13223 11:32:41.529437 arm64_za-ptrace_Set_VL_2400 pass
13224 11:32:41.529690 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13225 11:32:41.529786 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13226 11:32:41.529875 arm64_za-ptrace_Set_VL_2416 pass
13227 11:32:41.529978 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13228 11:32:41.530067 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13229 11:32:41.530165 arm64_za-ptrace_Set_VL_2432 pass
13230 11:32:41.534410 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13231 11:32:41.534839 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13232 11:32:41.534950 arm64_za-ptrace_Set_VL_2448 pass
13233 11:32:41.535038 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13234 11:32:41.535124 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13235 11:32:41.535227 arm64_za-ptrace_Set_VL_2464 pass
13236 11:32:41.535315 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13237 11:32:41.535400 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13238 11:32:41.535489 arm64_za-ptrace_Set_VL_2480 pass
13239 11:32:41.535587 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13240 11:32:41.535671 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13241 11:32:41.535754 arm64_za-ptrace_Set_VL_2496 pass
13242 11:32:41.535851 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13243 11:32:41.535951 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13244 11:32:41.536049 arm64_za-ptrace_Set_VL_2512 pass
13245 11:32:41.536405 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13246 11:32:41.536513 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13247 11:32:41.536620 arm64_za-ptrace_Set_VL_2528 pass
13248 11:32:41.536713 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13249 11:32:41.536807 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13250 11:32:41.536914 arm64_za-ptrace_Set_VL_2544 pass
13251 11:32:41.537000 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13252 11:32:41.537096 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13253 11:32:41.537196 arm64_za-ptrace_Set_VL_2560 pass
13254 11:32:41.537296 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13255 11:32:41.537795 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13256 11:32:41.554724 arm64_za-ptrace_Set_VL_2576 pass
13257 11:32:41.555171 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13258 11:32:41.555327 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13259 11:32:41.555523 arm64_za-ptrace_Set_VL_2592 pass
13260 11:32:41.555647 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13261 11:32:41.555743 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13262 11:32:41.555837 arm64_za-ptrace_Set_VL_2608 pass
13263 11:32:41.555925 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13264 11:32:41.556031 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13265 11:32:41.556122 arm64_za-ptrace_Set_VL_2624 pass
13266 11:32:41.556209 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13267 11:32:41.556311 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13268 11:32:41.556400 arm64_za-ptrace_Set_VL_2640 pass
13269 11:32:41.556502 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13270 11:32:41.556607 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13271 11:32:41.556709 arm64_za-ptrace_Set_VL_2656 pass
13272 11:32:41.556815 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13273 11:32:41.557210 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13274 11:32:41.557317 arm64_za-ptrace_Set_VL_2672 pass
13275 11:32:41.557421 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13276 11:32:41.557511 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13277 11:32:41.557613 arm64_za-ptrace_Set_VL_2688 pass
13278 11:32:41.557727 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13279 11:32:41.557835 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13280 11:32:41.558134 arm64_za-ptrace_Set_VL_2704 pass
13281 11:32:41.558240 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13282 11:32:41.562451 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13283 11:32:41.562838 arm64_za-ptrace_Set_VL_2720 pass
13284 11:32:41.562948 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13285 11:32:41.563045 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13286 11:32:41.563132 arm64_za-ptrace_Set_VL_2736 pass
13287 11:32:41.563238 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13288 11:32:41.563329 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13289 11:32:41.563415 arm64_za-ptrace_Set_VL_2752 pass
13290 11:32:41.563516 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13291 11:32:41.563598 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13292 11:32:41.563696 arm64_za-ptrace_Set_VL_2768 pass
13293 11:32:41.563802 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13294 11:32:41.564107 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13295 11:32:41.564225 arm64_za-ptrace_Set_VL_2784 pass
13296 11:32:41.564315 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13297 11:32:41.564413 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13298 11:32:41.564509 arm64_za-ptrace_Set_VL_2800 pass
13299 11:32:41.564592 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13300 11:32:41.564692 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13301 11:32:41.564790 arm64_za-ptrace_Set_VL_2816 pass
13302 11:32:41.565083 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13303 11:32:41.565198 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13304 11:32:41.565317 arm64_za-ptrace_Set_VL_2832 pass
13305 11:32:41.565423 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13306 11:32:41.565545 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13307 11:32:41.565677 arm64_za-ptrace_Set_VL_2848 pass
13308 11:32:41.565800 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13309 11:32:41.565895 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13310 11:32:41.566027 arm64_za-ptrace_Set_VL_2864 pass
13311 11:32:41.566145 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13312 11:32:41.570359 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13313 11:32:41.570713 arm64_za-ptrace_Set_VL_2880 pass
13314 11:32:41.570823 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13315 11:32:41.570914 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13316 11:32:41.571238 arm64_za-ptrace_Set_VL_2896 pass
13317 11:32:41.571453 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13318 11:32:41.571641 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13319 11:32:41.571816 arm64_za-ptrace_Set_VL_2912 pass
13320 11:32:41.571990 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13321 11:32:41.572214 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13322 11:32:41.572409 arm64_za-ptrace_Set_VL_2928 pass
13323 11:32:41.572587 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13324 11:32:41.572794 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13325 11:32:41.572993 arm64_za-ptrace_Set_VL_2944 pass
13326 11:32:41.573194 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13327 11:32:41.573420 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13328 11:32:41.573622 arm64_za-ptrace_Set_VL_2960 pass
13329 11:32:41.573863 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13330 11:32:41.574037 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13331 11:32:41.574234 arm64_za-ptrace_Set_VL_2976 pass
13332 11:32:41.574371 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13333 11:32:41.574488 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13334 11:32:41.574603 arm64_za-ptrace_Set_VL_2992 pass
13335 11:32:41.574718 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13336 11:32:41.574833 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13337 11:32:41.574946 arm64_za-ptrace_Set_VL_3008 pass
13338 11:32:41.575060 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13339 11:32:41.575174 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13340 11:32:41.575289 arm64_za-ptrace_Set_VL_3024 pass
13341 11:32:41.575403 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13342 11:32:41.575544 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13343 11:32:41.575666 arm64_za-ptrace_Set_VL_3040 pass
13344 11:32:41.578398 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13345 11:32:41.578756 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13346 11:32:41.578901 arm64_za-ptrace_Set_VL_3056 pass
13347 11:32:41.579031 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13348 11:32:41.579140 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13349 11:32:41.579255 arm64_za-ptrace_Set_VL_3072 pass
13350 11:32:41.579636 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13351 11:32:41.579811 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13352 11:32:41.579945 arm64_za-ptrace_Set_VL_3088 pass
13353 11:32:41.580157 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13354 11:32:41.580572 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13355 11:32:41.580780 arm64_za-ptrace_Set_VL_3104 pass
13356 11:32:41.580937 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13357 11:32:41.581101 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13358 11:32:41.581268 arm64_za-ptrace_Set_VL_3120 pass
13359 11:32:41.581421 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13360 11:32:41.581560 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13361 11:32:41.581702 arm64_za-ptrace_Set_VL_3136 pass
13362 11:32:41.581840 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13363 11:32:41.581960 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13364 11:32:41.582066 arm64_za-ptrace_Set_VL_3152 pass
13365 11:32:41.582171 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13366 11:32:41.582263 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13367 11:32:41.582331 arm64_za-ptrace_Set_VL_3168 pass
13368 11:32:41.582391 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13369 11:32:41.582449 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13370 11:32:41.582507 arm64_za-ptrace_Set_VL_3184 pass
13371 11:32:41.582564 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13372 11:32:41.582622 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13373 11:32:41.582679 arm64_za-ptrace_Set_VL_3200 pass
13374 11:32:41.582750 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13375 11:32:41.586334 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13376 11:32:41.586708 arm64_za-ptrace_Set_VL_3216 pass
13377 11:32:41.586825 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13378 11:32:41.586913 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13379 11:32:41.587002 arm64_za-ptrace_Set_VL_3232 pass
13380 11:32:41.587280 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13381 11:32:41.587395 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13382 11:32:41.587494 arm64_za-ptrace_Set_VL_3248 pass
13383 11:32:41.587583 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13384 11:32:41.587686 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13385 11:32:41.587812 arm64_za-ptrace_Set_VL_3264 pass
13386 11:32:41.587913 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13387 11:32:41.587996 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13388 11:32:41.588080 arm64_za-ptrace_Set_VL_3280 pass
13389 11:32:41.588179 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13390 11:32:41.588285 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13391 11:32:41.588372 arm64_za-ptrace_Set_VL_3296 pass
13392 11:32:41.588461 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13393 11:32:41.588566 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13394 11:32:41.588706 arm64_za-ptrace_Set_VL_3312 pass
13395 11:32:41.588806 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13396 11:32:41.588914 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13397 11:32:41.589040 arm64_za-ptrace_Set_VL_3328 pass
13398 11:32:41.589158 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13399 11:32:41.589284 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13400 11:32:41.589403 arm64_za-ptrace_Set_VL_3344 pass
13401 11:32:41.589730 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13402 11:32:41.589832 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13403 11:32:41.589932 arm64_za-ptrace_Set_VL_3360 pass
13404 11:32:41.590018 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13405 11:32:41.590114 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13406 11:32:41.590197 arm64_za-ptrace_Set_VL_3376 pass
13407 11:32:41.594421 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13408 11:32:41.594997 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13409 11:32:41.595169 arm64_za-ptrace_Set_VL_3392 pass
13410 11:32:41.595382 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13411 11:32:41.595564 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13412 11:32:41.595729 arm64_za-ptrace_Set_VL_3408 pass
13413 11:32:41.595944 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13414 11:32:41.596161 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13415 11:32:41.596344 arm64_za-ptrace_Set_VL_3424 pass
13416 11:32:41.596517 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13417 11:32:41.596686 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13418 11:32:41.596852 arm64_za-ptrace_Set_VL_3440 pass
13419 11:32:41.597017 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13420 11:32:41.597222 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13421 11:32:41.597391 arm64_za-ptrace_Set_VL_3456 pass
13422 11:32:41.597538 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13423 11:32:41.597711 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13424 11:32:41.597881 arm64_za-ptrace_Set_VL_3472 pass
13425 11:32:41.598043 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13426 11:32:41.598201 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13427 11:32:41.598351 arm64_za-ptrace_Set_VL_3488 pass
13428 11:32:41.598475 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13429 11:32:41.598590 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13430 11:32:41.598733 arm64_za-ptrace_Set_VL_3504 pass
13431 11:32:41.598855 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13432 11:32:41.598975 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13433 11:32:41.599091 arm64_za-ptrace_Set_VL_3520 pass
13434 11:32:41.599205 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13435 11:32:41.599319 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13436 11:32:41.599434 arm64_za-ptrace_Set_VL_3536 pass
13437 11:32:41.602344 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13438 11:32:41.602675 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13439 11:32:41.602822 arm64_za-ptrace_Set_VL_3552 pass
13440 11:32:41.603010 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13441 11:32:41.603123 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13442 11:32:41.603215 arm64_za-ptrace_Set_VL_3568 pass
13443 11:32:41.603302 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13444 11:32:41.606065 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13445 11:32:41.606239 arm64_za-ptrace_Set_VL_3584 pass
13446 11:32:41.606438 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13447 11:32:41.610403 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13448 11:32:41.625756 arm64_za-ptrace_Set_VL_3600 pass
13449 11:32:41.626035 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13450 11:32:41.626358 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13451 11:32:41.626475 arm64_za-ptrace_Set_VL_3616 pass
13452 11:32:41.626574 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13453 11:32:41.626682 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13454 11:32:41.626760 arm64_za-ptrace_Set_VL_3632 pass
13455 11:32:41.626839 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13456 11:32:41.626926 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13457 11:32:41.627014 arm64_za-ptrace_Set_VL_3648 pass
13458 11:32:41.627356 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13459 11:32:41.627468 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13460 11:32:41.628010 arm64_za-ptrace_Set_VL_3664 pass
13461 11:32:41.628126 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13462 11:32:41.628215 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13463 11:32:41.628565 arm64_za-ptrace_Set_VL_3680 pass
13464 11:32:41.628681 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13465 11:32:41.628767 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13466 11:32:41.628924 arm64_za-ptrace_Set_VL_3696 pass
13467 11:32:41.629034 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13468 11:32:41.629117 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13469 11:32:41.629200 arm64_za-ptrace_Set_VL_3712 pass
13470 11:32:41.629299 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13471 11:32:41.629384 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13472 11:32:41.629467 arm64_za-ptrace_Set_VL_3728 pass
13473 11:32:41.629550 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13474 11:32:41.629632 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13475 11:32:41.629745 arm64_za-ptrace_Set_VL_3744 pass
13476 11:32:41.629869 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13477 11:32:41.629961 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13478 11:32:41.630045 arm64_za-ptrace_Set_VL_3760 pass
13479 11:32:41.630128 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13480 11:32:41.630225 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13481 11:32:41.630310 arm64_za-ptrace_Set_VL_3776 pass
13482 11:32:41.630395 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13483 11:32:41.634486 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13484 11:32:41.635012 arm64_za-ptrace_Set_VL_3792 pass
13485 11:32:41.635184 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13486 11:32:41.635275 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13487 11:32:41.635367 arm64_za-ptrace_Set_VL_3808 pass
13488 11:32:41.635474 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13489 11:32:41.635566 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13490 11:32:41.635657 arm64_za-ptrace_Set_VL_3824 pass
13491 11:32:41.635760 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13492 11:32:41.635853 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13493 11:32:41.635959 arm64_za-ptrace_Set_VL_3840 pass
13494 11:32:41.636067 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13495 11:32:41.636421 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13496 11:32:41.636578 arm64_za-ptrace_Set_VL_3856 pass
13497 11:32:41.636732 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13498 11:32:41.636839 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13499 11:32:41.636947 arm64_za-ptrace_Set_VL_3872 pass
13500 11:32:41.637040 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13501 11:32:41.637143 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13502 11:32:41.637251 arm64_za-ptrace_Set_VL_3888 pass
13503 11:32:41.637599 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13504 11:32:41.637716 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13505 11:32:41.637824 arm64_za-ptrace_Set_VL_3904 pass
13506 11:32:41.637915 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13507 11:32:41.638197 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13508 11:32:41.638321 arm64_za-ptrace_Set_VL_3920 pass
13509 11:32:41.642351 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13510 11:32:41.642715 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13511 11:32:41.642817 arm64_za-ptrace_Set_VL_3936 pass
13512 11:32:41.642894 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13513 11:32:41.643166 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13514 11:32:41.643275 arm64_za-ptrace_Set_VL_3952 pass
13515 11:32:41.643363 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13516 11:32:41.643473 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13517 11:32:41.643600 arm64_za-ptrace_Set_VL_3968 pass
13518 11:32:41.643686 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13519 11:32:41.643775 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13520 11:32:41.643920 arm64_za-ptrace_Set_VL_3984 pass
13521 11:32:41.644147 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13522 11:32:41.644464 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13523 11:32:41.644590 arm64_za-ptrace_Set_VL_4000 pass
13524 11:32:41.644666 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13525 11:32:41.644753 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13526 11:32:41.644837 arm64_za-ptrace_Set_VL_4016 pass
13527 11:32:41.644919 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13528 11:32:41.645154 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13529 11:32:41.645252 arm64_za-ptrace_Set_VL_4032 pass
13530 11:32:41.645540 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13531 11:32:41.645642 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13532 11:32:41.645739 arm64_za-ptrace_Set_VL_4048 pass
13533 11:32:41.645825 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13534 11:32:41.645926 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13535 11:32:41.646018 arm64_za-ptrace_Set_VL_4064 pass
13536 11:32:41.646299 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13537 11:32:41.646377 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13538 11:32:41.646438 arm64_za-ptrace_Set_VL_4080 pass
13539 11:32:41.650422 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13540 11:32:41.650765 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13541 11:32:41.650914 arm64_za-ptrace_Set_VL_4096 pass
13542 11:32:41.651024 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13543 11:32:41.651136 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13544 11:32:41.651424 arm64_za-ptrace_Set_VL_4112 pass
13545 11:32:41.651516 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13546 11:32:41.651601 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13547 11:32:41.651707 arm64_za-ptrace_Set_VL_4128 pass
13548 11:32:41.651796 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13549 11:32:41.651885 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13550 11:32:41.651986 arm64_za-ptrace_Set_VL_4144 pass
13551 11:32:41.652053 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13552 11:32:41.652333 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13553 11:32:41.652441 arm64_za-ptrace_Set_VL_4160 pass
13554 11:32:41.652533 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13555 11:32:41.652623 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13556 11:32:41.652729 arm64_za-ptrace_Set_VL_4176 pass
13557 11:32:41.652817 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13558 11:32:41.652921 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13559 11:32:41.653013 arm64_za-ptrace_Set_VL_4192 pass
13560 11:32:41.653112 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13561 11:32:41.653442 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13562 11:32:41.653545 arm64_za-ptrace_Set_VL_4208 pass
13563 11:32:41.653639 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13564 11:32:41.653737 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13565 11:32:41.653841 arm64_za-ptrace_Set_VL_4224 pass
13566 11:32:41.653953 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13567 11:32:41.654241 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13568 11:32:41.658415 arm64_za-ptrace_Set_VL_4240 pass
13569 11:32:41.658761 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13570 11:32:41.658888 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13571 11:32:41.659005 arm64_za-ptrace_Set_VL_4256 pass
13572 11:32:41.659092 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13573 11:32:41.659173 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13574 11:32:41.659574 arm64_za-ptrace_Set_VL_4272 pass
13575 11:32:41.659769 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13576 11:32:41.659866 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13577 11:32:41.659955 arm64_za-ptrace_Set_VL_4288 pass
13578 11:32:41.660048 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13579 11:32:41.660135 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13580 11:32:41.660223 arm64_za-ptrace_Set_VL_4304 pass
13581 11:32:41.660328 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13582 11:32:41.660478 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13583 11:32:41.660567 arm64_za-ptrace_Set_VL_4320 pass
13584 11:32:41.660652 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13585 11:32:41.660755 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13586 11:32:41.660844 arm64_za-ptrace_Set_VL_4336 pass
13587 11:32:41.660930 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13588 11:32:41.661016 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13589 11:32:41.661117 arm64_za-ptrace_Set_VL_4352 pass
13590 11:32:41.661207 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13591 11:32:41.661307 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13592 11:32:41.661793 arm64_za-ptrace_Set_VL_4368 pass
13593 11:32:41.662019 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13594 11:32:41.662162 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13595 11:32:41.662301 arm64_za-ptrace_Set_VL_4384 pass
13596 11:32:41.662635 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13597 11:32:41.662714 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13598 11:32:41.662776 arm64_za-ptrace_Set_VL_4400 pass
13599 11:32:41.662835 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13600 11:32:41.666464 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13601 11:32:41.666595 arm64_za-ptrace_Set_VL_4416 pass
13602 11:32:41.666892 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13603 11:32:41.666988 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13604 11:32:41.667053 arm64_za-ptrace_Set_VL_4432 pass
13605 11:32:41.667114 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13606 11:32:41.667391 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13607 11:32:41.667509 arm64_za-ptrace_Set_VL_4448 pass
13608 11:32:41.667606 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13609 11:32:41.667715 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13610 11:32:41.667824 arm64_za-ptrace_Set_VL_4464 pass
13611 11:32:41.667916 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13612 11:32:41.668218 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13613 11:32:41.668323 arm64_za-ptrace_Set_VL_4480 pass
13614 11:32:41.668413 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13615 11:32:41.668497 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13616 11:32:41.668579 arm64_za-ptrace_Set_VL_4496 pass
13617 11:32:41.668660 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13618 11:32:41.668986 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13619 11:32:41.669135 arm64_za-ptrace_Set_VL_4512 pass
13620 11:32:41.669262 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13621 11:32:41.669413 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13622 11:32:41.669551 arm64_za-ptrace_Set_VL_4528 pass
13623 11:32:41.669693 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13624 11:32:41.669827 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13625 11:32:41.669997 arm64_za-ptrace_Set_VL_4544 pass
13626 11:32:41.670124 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13627 11:32:41.670223 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13628 11:32:41.670312 arm64_za-ptrace_Set_VL_4560 pass
13629 11:32:41.670398 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13630 11:32:41.670487 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13631 11:32:41.670573 arm64_za-ptrace_Set_VL_4576 pass
13632 11:32:41.670679 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13633 11:32:41.674350 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13634 11:32:41.674693 arm64_za-ptrace_Set_VL_4592 pass
13635 11:32:41.674797 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13636 11:32:41.674887 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13637 11:32:41.674988 arm64_za-ptrace_Set_VL_4608 pass
13638 11:32:41.675077 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13639 11:32:41.675177 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13640 11:32:41.675758 arm64_za-ptrace_Set_VL_4624 pass
13641 11:32:41.695276 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13642 11:32:41.695479 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13643 11:32:41.695547 arm64_za-ptrace_Set_VL_4640 pass
13644 11:32:41.695609 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13645 11:32:41.695671 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13646 11:32:41.695732 arm64_za-ptrace_Set_VL_4656 pass
13647 11:32:41.695792 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13648 11:32:41.695854 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13649 11:32:41.695915 arm64_za-ptrace_Set_VL_4672 pass
13650 11:32:41.695975 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13651 11:32:41.696036 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13652 11:32:41.696102 arm64_za-ptrace_Set_VL_4688 pass
13653 11:32:41.696163 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13654 11:32:41.696223 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13655 11:32:41.696283 arm64_za-ptrace_Set_VL_4704 pass
13656 11:32:41.696344 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13657 11:32:41.696404 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13658 11:32:41.696465 arm64_za-ptrace_Set_VL_4720 pass
13659 11:32:41.696524 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13660 11:32:41.696585 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13661 11:32:41.696645 arm64_za-ptrace_Set_VL_4736 pass
13662 11:32:41.698389 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13663 11:32:41.698706 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13664 11:32:41.698808 arm64_za-ptrace_Set_VL_4752 pass
13665 11:32:41.698917 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13666 11:32:41.699048 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13667 11:32:41.699151 arm64_za-ptrace_Set_VL_4768 pass
13668 11:32:41.699278 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13669 11:32:41.699374 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13670 11:32:41.699467 arm64_za-ptrace_Set_VL_4784 pass
13671 11:32:41.699564 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13672 11:32:41.699856 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13673 11:32:41.699976 arm64_za-ptrace_Set_VL_4800 pass
13674 11:32:41.700110 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13675 11:32:41.700214 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13676 11:32:41.700335 arm64_za-ptrace_Set_VL_4816 pass
13677 11:32:41.700432 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13678 11:32:41.700558 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13679 11:32:41.700871 arm64_za-ptrace_Set_VL_4832 pass
13680 11:32:41.700980 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13681 11:32:41.701103 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13682 11:32:41.701207 arm64_za-ptrace_Set_VL_4848 pass
13683 11:32:41.701332 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13684 11:32:41.701433 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13685 11:32:41.701537 arm64_za-ptrace_Set_VL_4864 pass
13686 11:32:41.701641 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13687 11:32:41.701736 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13688 11:32:41.701835 arm64_za-ptrace_Set_VL_4880 pass
13689 11:32:41.701961 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13690 11:32:41.702083 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13691 11:32:41.702187 arm64_za-ptrace_Set_VL_4896 pass
13692 11:32:41.706357 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13693 11:32:41.706682 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13694 11:32:41.706793 arm64_za-ptrace_Set_VL_4912 pass
13695 11:32:41.706887 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13696 11:32:41.706999 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13697 11:32:41.707106 arm64_za-ptrace_Set_VL_4928 pass
13698 11:32:41.707550 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13699 11:32:41.707671 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13700 11:32:41.707788 arm64_za-ptrace_Set_VL_4944 pass
13701 11:32:41.707904 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13702 11:32:41.708015 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13703 11:32:41.708367 arm64_za-ptrace_Set_VL_4960 pass
13704 11:32:41.708483 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13705 11:32:41.708575 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13706 11:32:41.708663 arm64_za-ptrace_Set_VL_4976 pass
13707 11:32:41.708747 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13708 11:32:41.708829 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13709 11:32:41.708928 arm64_za-ptrace_Set_VL_4992 pass
13710 11:32:41.709015 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13711 11:32:41.709104 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13712 11:32:41.709194 arm64_za-ptrace_Set_VL_5008 pass
13713 11:32:41.709303 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13714 11:32:41.709416 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13715 11:32:41.709535 arm64_za-ptrace_Set_VL_5024 pass
13716 11:32:41.709669 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13717 11:32:41.709783 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13718 11:32:41.709895 arm64_za-ptrace_Set_VL_5040 pass
13719 11:32:41.710021 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13720 11:32:41.710324 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13721 11:32:41.710406 arm64_za-ptrace_Set_VL_5056 pass
13722 11:32:41.710497 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13723 11:32:41.714342 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13724 11:32:41.714640 arm64_za-ptrace_Set_VL_5072 pass
13725 11:32:41.714742 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13726 11:32:41.714865 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13727 11:32:41.714954 arm64_za-ptrace_Set_VL_5088 pass
13728 11:32:41.715074 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13729 11:32:41.715200 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13730 11:32:41.715327 arm64_za-ptrace_Set_VL_5104 pass
13731 11:32:41.715453 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13732 11:32:41.715578 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13733 11:32:41.715672 arm64_za-ptrace_Set_VL_5120 pass
13734 11:32:41.715780 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13735 11:32:41.715905 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13736 11:32:41.716010 arm64_za-ptrace_Set_VL_5136 pass
13737 11:32:41.716136 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13738 11:32:41.716277 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13739 11:32:41.716376 arm64_za-ptrace_Set_VL_5152 pass
13740 11:32:41.716477 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13741 11:32:41.716568 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13742 11:32:41.716646 arm64_za-ptrace_Set_VL_5168 pass
13743 11:32:41.716757 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13744 11:32:41.716877 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13745 11:32:41.717162 arm64_za-ptrace_Set_VL_5184 pass
13746 11:32:41.717271 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13747 11:32:41.717375 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13748 11:32:41.717459 arm64_za-ptrace_Set_VL_5200 pass
13749 11:32:41.717744 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13750 11:32:41.717858 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13751 11:32:41.717986 arm64_za-ptrace_Set_VL_5216 pass
13752 11:32:41.718093 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13753 11:32:41.718214 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13754 11:32:41.718307 arm64_za-ptrace_Set_VL_5232 pass
13755 11:32:41.722331 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
13756 11:32:41.722684 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
13757 11:32:41.722817 arm64_za-ptrace_Set_VL_5248 pass
13758 11:32:41.722974 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
13759 11:32:41.723101 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
13760 11:32:41.723215 arm64_za-ptrace_Set_VL_5264 pass
13761 11:32:41.723341 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
13762 11:32:41.723454 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
13763 11:32:41.723559 arm64_za-ptrace_Set_VL_5280 pass
13764 11:32:41.723683 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
13765 11:32:41.723795 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
13766 11:32:41.723921 arm64_za-ptrace_Set_VL_5296 pass
13767 11:32:41.724044 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
13768 11:32:41.724153 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
13769 11:32:41.724276 arm64_za-ptrace_Set_VL_5312 pass
13770 11:32:41.724375 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
13771 11:32:41.724476 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
13772 11:32:41.724580 arm64_za-ptrace_Set_VL_5328 pass
13773 11:32:41.724699 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
13774 11:32:41.725154 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
13775 11:32:41.725268 arm64_za-ptrace_Set_VL_5344 pass
13776 11:32:41.725377 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
13777 11:32:41.725491 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
13778 11:32:41.725613 arm64_za-ptrace_Set_VL_5360 pass
13779 11:32:41.725815 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
13780 11:32:41.725918 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
13781 11:32:41.726017 arm64_za-ptrace_Set_VL_5376 pass
13782 11:32:41.726140 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
13783 11:32:41.726252 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
13784 11:32:41.726371 arm64_za-ptrace_Set_VL_5392 pass
13785 11:32:41.730336 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
13786 11:32:41.730656 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
13787 11:32:41.730765 arm64_za-ptrace_Set_VL_5408 pass
13788 11:32:41.730849 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
13789 11:32:41.731121 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
13790 11:32:41.731221 arm64_za-ptrace_Set_VL_5424 pass
13791 11:32:41.731308 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
13792 11:32:41.731414 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
13793 11:32:41.731531 arm64_za-ptrace_Set_VL_5440 pass
13794 11:32:41.731626 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
13795 11:32:41.731725 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
13796 11:32:41.731810 arm64_za-ptrace_Set_VL_5456 pass
13797 11:32:41.731892 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
13798 11:32:41.732020 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
13799 11:32:41.732117 arm64_za-ptrace_Set_VL_5472 pass
13800 11:32:41.732220 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
13801 11:32:41.732340 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
13802 11:32:41.732454 arm64_za-ptrace_Set_VL_5488 pass
13803 11:32:41.732787 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
13804 11:32:41.732885 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
13805 11:32:41.732984 arm64_za-ptrace_Set_VL_5504 pass
13806 11:32:41.733078 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
13807 11:32:41.733213 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
13808 11:32:41.733309 arm64_za-ptrace_Set_VL_5520 pass
13809 11:32:41.733411 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
13810 11:32:41.733525 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
13811 11:32:41.733652 arm64_za-ptrace_Set_VL_5536 pass
13812 11:32:41.733778 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
13813 11:32:41.734120 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
13814 11:32:41.734232 arm64_za-ptrace_Set_VL_5552 pass
13815 11:32:41.734317 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
13816 11:32:41.738416 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
13817 11:32:41.738803 arm64_za-ptrace_Set_VL_5568 pass
13818 11:32:41.738918 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
13819 11:32:41.739028 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
13820 11:32:41.739179 arm64_za-ptrace_Set_VL_5584 pass
13821 11:32:41.739284 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
13822 11:32:41.739387 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
13823 11:32:41.739497 arm64_za-ptrace_Set_VL_5600 pass
13824 11:32:41.739603 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
13825 11:32:41.739732 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
13826 11:32:41.739845 arm64_za-ptrace_Set_VL_5616 pass
13827 11:32:41.739955 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
13828 11:32:41.740045 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
13829 11:32:41.740144 arm64_za-ptrace_Set_VL_5632 pass
13830 11:32:41.740243 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
13831 11:32:41.740564 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
13832 11:32:41.740728 arm64_za-ptrace_Set_VL_5648 pass
13833 11:32:41.758788 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
13834 11:32:41.759286 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
13835 11:32:41.759527 arm64_za-ptrace_Set_VL_5664 pass
13836 11:32:41.759748 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
13837 11:32:41.759970 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
13838 11:32:41.760195 arm64_za-ptrace_Set_VL_5680 pass
13839 11:32:41.760430 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
13840 11:32:41.760594 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
13841 11:32:41.760734 arm64_za-ptrace_Set_VL_5696 pass
13842 11:32:41.760887 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
13843 11:32:41.761030 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
13844 11:32:41.761186 arm64_za-ptrace_Set_VL_5712 pass
13845 11:32:41.761352 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
13846 11:32:41.761515 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
13847 11:32:41.761667 arm64_za-ptrace_Set_VL_5728 pass
13848 11:32:41.761847 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
13849 11:32:41.762007 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
13850 11:32:41.762153 arm64_za-ptrace_Set_VL_5744 pass
13851 11:32:41.762276 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
13852 11:32:41.762392 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
13853 11:32:41.762562 arm64_za-ptrace_Set_VL_5760 pass
13854 11:32:41.762745 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
13855 11:32:41.762910 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
13856 11:32:41.763077 arm64_za-ptrace_Set_VL_5776 pass
13857 11:32:41.763229 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
13858 11:32:41.763350 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
13859 11:32:41.763481 arm64_za-ptrace_Set_VL_5792 pass
13860 11:32:41.763575 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
13861 11:32:41.766502 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
13862 11:32:41.766853 arm64_za-ptrace_Set_VL_5808 pass
13863 11:32:41.766961 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
13864 11:32:41.767069 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
13865 11:32:41.767185 arm64_za-ptrace_Set_VL_5824 pass
13866 11:32:41.767287 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
13867 11:32:41.767401 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
13868 11:32:41.767521 arm64_za-ptrace_Set_VL_5840 pass
13869 11:32:41.767622 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
13870 11:32:41.767746 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
13871 11:32:41.767862 arm64_za-ptrace_Set_VL_5856 pass
13872 11:32:41.767983 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
13873 11:32:41.768098 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
13874 11:32:41.768216 arm64_za-ptrace_Set_VL_5872 pass
13875 11:32:41.768327 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
13876 11:32:41.768442 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
13877 11:32:41.768545 arm64_za-ptrace_Set_VL_5888 pass
13878 11:32:41.768667 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
13879 11:32:41.768783 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
13880 11:32:41.768908 arm64_za-ptrace_Set_VL_5904 pass
13881 11:32:41.769033 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
13882 11:32:41.769385 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
13883 11:32:41.769560 arm64_za-ptrace_Set_VL_5920 pass
13884 11:32:41.769980 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
13885 11:32:41.770152 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
13886 11:32:41.770275 arm64_za-ptrace_Set_VL_5936 pass
13887 11:32:41.770391 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
13888 11:32:41.770506 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
13889 11:32:41.770645 arm64_za-ptrace_Set_VL_5952 pass
13890 11:32:41.770766 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
13891 11:32:41.774583 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
13892 11:32:41.774917 arm64_za-ptrace_Set_VL_5968 pass
13893 11:32:41.775043 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
13894 11:32:41.775161 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
13895 11:32:41.775288 arm64_za-ptrace_Set_VL_5984 pass
13896 11:32:41.775519 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
13897 11:32:41.775727 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
13898 11:32:41.775912 arm64_za-ptrace_Set_VL_6000 pass
13899 11:32:41.776085 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
13900 11:32:41.776242 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
13901 11:32:41.776402 arm64_za-ptrace_Set_VL_6016 pass
13902 11:32:41.776532 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
13903 11:32:41.776640 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
13904 11:32:41.776745 arm64_za-ptrace_Set_VL_6032 pass
13905 11:32:41.776848 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
13906 11:32:41.776950 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
13907 11:32:41.777053 arm64_za-ptrace_Set_VL_6048 pass
13908 11:32:41.777155 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
13909 11:32:41.777284 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
13910 11:32:41.777400 arm64_za-ptrace_Set_VL_6064 pass
13911 11:32:41.777523 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
13912 11:32:41.777658 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
13913 11:32:41.777786 arm64_za-ptrace_Set_VL_6080 pass
13914 11:32:41.777908 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
13915 11:32:41.778033 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
13916 11:32:41.778180 arm64_za-ptrace_Set_VL_6096 pass
13917 11:32:41.778316 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
13918 11:32:41.778400 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
13919 11:32:41.778478 arm64_za-ptrace_Set_VL_6112 pass
13920 11:32:41.778553 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
13921 11:32:41.778628 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
13922 11:32:41.778704 arm64_za-ptrace_Set_VL_6128 pass
13923 11:32:41.778778 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
13924 11:32:41.782457 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
13925 11:32:41.782790 arm64_za-ptrace_Set_VL_6144 pass
13926 11:32:41.782905 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
13927 11:32:41.782990 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
13928 11:32:41.783106 arm64_za-ptrace_Set_VL_6160 pass
13929 11:32:41.783200 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
13930 11:32:41.783309 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
13931 11:32:41.783430 arm64_za-ptrace_Set_VL_6176 pass
13932 11:32:41.783562 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
13933 11:32:41.783677 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
13934 11:32:41.783803 arm64_za-ptrace_Set_VL_6192 pass
13935 11:32:41.783901 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
13936 11:32:41.784020 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
13937 11:32:41.784120 arm64_za-ptrace_Set_VL_6208 pass
13938 11:32:41.784252 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
13939 11:32:41.784362 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
13940 11:32:41.784491 arm64_za-ptrace_Set_VL_6224 pass
13941 11:32:41.784578 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
13942 11:32:41.784680 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
13943 11:32:41.784782 arm64_za-ptrace_Set_VL_6240 pass
13944 11:32:41.784892 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
13945 11:32:41.784992 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
13946 11:32:41.785097 arm64_za-ptrace_Set_VL_6256 pass
13947 11:32:41.785401 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
13948 11:32:41.785536 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
13949 11:32:41.785619 arm64_za-ptrace_Set_VL_6272 pass
13950 11:32:41.785740 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
13951 11:32:41.785843 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
13952 11:32:41.785938 arm64_za-ptrace_Set_VL_6288 pass
13953 11:32:41.786023 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
13954 11:32:41.786107 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
13955 11:32:41.790839 arm64_za-ptrace_Set_VL_6304 pass
13956 11:32:41.791073 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
13957 11:32:41.791381 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
13958 11:32:41.791490 arm64_za-ptrace_Set_VL_6320 pass
13959 11:32:41.791587 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
13960 11:32:41.791688 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
13961 11:32:41.791776 arm64_za-ptrace_Set_VL_6336 pass
13962 11:32:41.791895 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
13963 11:32:41.791998 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
13964 11:32:41.792106 arm64_za-ptrace_Set_VL_6352 pass
13965 11:32:41.792230 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
13966 11:32:41.792332 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
13967 11:32:41.792421 arm64_za-ptrace_Set_VL_6368 pass
13968 11:32:41.792507 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
13969 11:32:41.792610 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
13970 11:32:41.792702 arm64_za-ptrace_Set_VL_6384 pass
13971 11:32:41.792794 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
13972 11:32:41.792886 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
13973 11:32:41.792995 arm64_za-ptrace_Set_VL_6400 pass
13974 11:32:41.793084 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
13975 11:32:41.793174 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
13976 11:32:41.793285 arm64_za-ptrace_Set_VL_6416 pass
13977 11:32:41.793373 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
13978 11:32:41.793475 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
13979 11:32:41.793565 arm64_za-ptrace_Set_VL_6432 pass
13980 11:32:41.793707 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
13981 11:32:41.793823 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
13982 11:32:41.793915 arm64_za-ptrace_Set_VL_6448 pass
13983 11:32:41.794023 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
13984 11:32:41.794128 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
13985 11:32:41.798707 arm64_za-ptrace_Set_VL_6464 pass
13986 11:32:41.799106 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
13987 11:32:41.799201 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
13988 11:32:41.799305 arm64_za-ptrace_Set_VL_6480 pass
13989 11:32:41.799390 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
13990 11:32:41.799455 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
13991 11:32:41.799552 arm64_za-ptrace_Set_VL_6496 pass
13992 11:32:41.799632 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
13993 11:32:41.799695 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
13994 11:32:41.799758 arm64_za-ptrace_Set_VL_6512 pass
13995 11:32:41.799824 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
13996 11:32:41.799938 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
13997 11:32:41.800012 arm64_za-ptrace_Set_VL_6528 pass
13998 11:32:41.800089 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
13999 11:32:41.800166 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14000 11:32:41.800261 arm64_za-ptrace_Set_VL_6544 pass
14001 11:32:41.800332 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14002 11:32:41.800425 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14003 11:32:41.800497 arm64_za-ptrace_Set_VL_6560 pass
14004 11:32:41.800590 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14005 11:32:41.800870 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14006 11:32:41.800952 arm64_za-ptrace_Set_VL_6576 pass
14007 11:32:41.801045 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14008 11:32:41.801132 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14009 11:32:41.801230 arm64_za-ptrace_Set_VL_6592 pass
14010 11:32:41.801315 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14011 11:32:41.801597 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14012 11:32:41.801692 arm64_za-ptrace_Set_VL_6608 pass
14013 11:32:41.801810 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14014 11:32:41.801922 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14015 11:32:41.802009 arm64_za-ptrace_Set_VL_6624 pass
14016 11:32:41.802103 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14017 11:32:41.806399 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14018 11:32:41.806728 arm64_za-ptrace_Set_VL_6640 pass
14019 11:32:41.806825 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14020 11:32:41.806901 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14021 11:32:41.806973 arm64_za-ptrace_Set_VL_6656 pass
14022 11:32:41.807064 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14023 11:32:41.807153 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14024 11:32:41.807242 arm64_za-ptrace_Set_VL_6672 pass
14025 11:32:41.807632 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14026 11:32:41.828127 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14027 11:32:41.828487 arm64_za-ptrace_Set_VL_6688 pass
14028 11:32:41.828593 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14029 11:32:41.828683 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14030 11:32:41.828771 arm64_za-ptrace_Set_VL_6704 pass
14031 11:32:41.828878 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14032 11:32:41.828961 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14033 11:32:41.829033 arm64_za-ptrace_Set_VL_6720 pass
14034 11:32:41.829102 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14035 11:32:41.829186 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14036 11:32:41.829258 arm64_za-ptrace_Set_VL_6736 pass
14037 11:32:41.829332 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14038 11:32:41.829421 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14039 11:32:41.829524 arm64_za-ptrace_Set_VL_6752 pass
14040 11:32:41.829612 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14041 11:32:41.829803 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14042 11:32:41.829900 arm64_za-ptrace_Set_VL_6768 pass
14043 11:32:41.829975 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14044 11:32:41.830046 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14045 11:32:41.830117 arm64_za-ptrace_Set_VL_6784 pass
14046 11:32:41.830200 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14047 11:32:41.830272 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14048 11:32:41.830619 arm64_za-ptrace_Set_VL_6800 pass
14049 11:32:41.830714 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14050 11:32:41.830974 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14051 11:32:41.831071 arm64_za-ptrace_Set_VL_6816 pass
14052 11:32:41.831143 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14053 11:32:41.831226 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14054 11:32:41.831298 arm64_za-ptrace_Set_VL_6832 pass
14055 11:32:41.831585 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14056 11:32:41.831701 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14057 11:32:41.831838 arm64_za-ptrace_Set_VL_6848 pass
14058 11:32:41.831949 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14059 11:32:41.832074 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14060 11:32:41.832179 arm64_za-ptrace_Set_VL_6864 pass
14061 11:32:41.832286 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14062 11:32:41.832375 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14063 11:32:41.832473 arm64_za-ptrace_Set_VL_6880 pass
14064 11:32:41.832557 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14065 11:32:41.832655 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14066 11:32:41.832752 arm64_za-ptrace_Set_VL_6896 pass
14067 11:32:41.833099 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14068 11:32:41.833200 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14069 11:32:41.833293 arm64_za-ptrace_Set_VL_6912 pass
14070 11:32:41.833386 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14071 11:32:41.833508 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14072 11:32:41.833621 arm64_za-ptrace_Set_VL_6928 pass
14073 11:32:41.833781 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14074 11:32:41.833897 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14075 11:32:41.834004 arm64_za-ptrace_Set_VL_6944 pass
14076 11:32:41.834107 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14077 11:32:41.838436 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14078 11:32:41.838829 arm64_za-ptrace_Set_VL_6960 pass
14079 11:32:41.838936 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14080 11:32:41.839026 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14081 11:32:41.839129 arm64_za-ptrace_Set_VL_6976 pass
14082 11:32:41.839219 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14083 11:32:41.839320 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14084 11:32:41.839410 arm64_za-ptrace_Set_VL_6992 pass
14085 11:32:41.839515 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14086 11:32:41.839619 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14087 11:32:41.839723 arm64_za-ptrace_Set_VL_7008 pass
14088 11:32:41.839826 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14089 11:32:41.839966 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14090 11:32:41.840085 arm64_za-ptrace_Set_VL_7024 pass
14091 11:32:41.840394 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14092 11:32:41.840501 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14093 11:32:41.840605 arm64_za-ptrace_Set_VL_7040 pass
14094 11:32:41.840694 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14095 11:32:41.840795 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14096 11:32:41.840896 arm64_za-ptrace_Set_VL_7056 pass
14097 11:32:41.840996 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14098 11:32:41.841098 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14099 11:32:41.841195 arm64_za-ptrace_Set_VL_7072 pass
14100 11:32:41.841293 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14101 11:32:41.841605 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14102 11:32:41.841734 arm64_za-ptrace_Set_VL_7088 pass
14103 11:32:41.841833 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14104 11:32:41.841937 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14105 11:32:41.842251 arm64_za-ptrace_Set_VL_7104 pass
14106 11:32:41.846597 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14107 11:32:41.847019 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14108 11:32:41.847133 arm64_za-ptrace_Set_VL_7120 pass
14109 11:32:41.847242 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14110 11:32:41.847334 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14111 11:32:41.847427 arm64_za-ptrace_Set_VL_7136 pass
14112 11:32:41.847529 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14113 11:32:41.847617 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14114 11:32:41.847705 arm64_za-ptrace_Set_VL_7152 pass
14115 11:32:41.847792 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14116 11:32:41.847895 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14117 11:32:41.847974 arm64_za-ptrace_Set_VL_7168 pass
14118 11:32:41.848045 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14119 11:32:41.848136 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14120 11:32:41.848214 arm64_za-ptrace_Set_VL_7184 pass
14121 11:32:41.848307 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14122 11:32:41.848379 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14123 11:32:41.848470 arm64_za-ptrace_Set_VL_7200 pass
14124 11:32:41.848542 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14125 11:32:41.848616 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14126 11:32:41.848705 arm64_za-ptrace_Set_VL_7216 pass
14127 11:32:41.848792 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14128 11:32:41.848904 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14129 11:32:41.849020 arm64_za-ptrace_Set_VL_7232 pass
14130 11:32:41.849130 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14131 11:32:41.849418 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14132 11:32:41.849506 arm64_za-ptrace_Set_VL_7248 pass
14133 11:32:41.849597 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14134 11:32:41.849724 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14135 11:32:41.849860 arm64_za-ptrace_Set_VL_7264 pass
14136 11:32:41.849968 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14137 11:32:41.850088 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14138 11:32:41.850187 arm64_za-ptrace_Set_VL_7280 pass
14139 11:32:41.850298 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14140 11:32:41.854522 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14141 11:32:41.854903 arm64_za-ptrace_Set_VL_7296 pass
14142 11:32:41.855009 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14143 11:32:41.855097 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14144 11:32:41.855199 arm64_za-ptrace_Set_VL_7312 pass
14145 11:32:41.855287 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14146 11:32:41.855372 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14147 11:32:41.855471 arm64_za-ptrace_Set_VL_7328 pass
14148 11:32:41.855556 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14149 11:32:41.855640 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14150 11:32:41.855738 arm64_za-ptrace_Set_VL_7344 pass
14151 11:32:41.855824 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14152 11:32:41.855927 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14153 11:32:41.856018 arm64_za-ptrace_Set_VL_7360 pass
14154 11:32:41.856127 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14155 11:32:41.856219 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14156 11:32:41.856328 arm64_za-ptrace_Set_VL_7376 pass
14157 11:32:41.856422 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14158 11:32:41.856527 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14159 11:32:41.856624 arm64_za-ptrace_Set_VL_7392 pass
14160 11:32:41.856735 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14161 11:32:41.856846 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14162 11:32:41.856935 arm64_za-ptrace_Set_VL_7408 pass
14163 11:32:41.857047 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14164 11:32:41.857131 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14165 11:32:41.857233 arm64_za-ptrace_Set_VL_7424 pass
14166 11:32:41.857337 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14167 11:32:41.857427 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14168 11:32:41.857538 arm64_za-ptrace_Set_VL_7440 pass
14169 11:32:41.857628 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14170 11:32:41.857783 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14171 11:32:41.857892 arm64_za-ptrace_Set_VL_7456 pass
14172 11:32:41.858572 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14173 11:32:41.858671 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14174 11:32:41.858743 arm64_za-ptrace_Set_VL_7472 pass
14175 11:32:41.862574 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14176 11:32:41.862973 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14177 11:32:41.863090 arm64_za-ptrace_Set_VL_7488 pass
14178 11:32:41.863211 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14179 11:32:41.863305 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14180 11:32:41.863414 arm64_za-ptrace_Set_VL_7504 pass
14181 11:32:41.863522 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14182 11:32:41.863628 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14183 11:32:41.863735 arm64_za-ptrace_Set_VL_7520 pass
14184 11:32:41.863866 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14185 11:32:41.863957 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14186 11:32:41.864040 arm64_za-ptrace_Set_VL_7536 pass
14187 11:32:41.864123 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14188 11:32:41.864189 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14189 11:32:41.864254 arm64_za-ptrace_Set_VL_7552 pass
14190 11:32:41.864330 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14191 11:32:41.864398 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14192 11:32:41.864476 arm64_za-ptrace_Set_VL_7568 pass
14193 11:32:41.864542 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14194 11:32:41.864617 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14195 11:32:41.864691 arm64_za-ptrace_Set_VL_7584 pass
14196 11:32:41.864965 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14197 11:32:41.865072 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14198 11:32:41.865162 arm64_za-ptrace_Set_VL_7600 pass
14199 11:32:41.865262 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14200 11:32:41.865350 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14201 11:32:41.865450 arm64_za-ptrace_Set_VL_7616 pass
14202 11:32:41.865538 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14203 11:32:41.865640 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14204 11:32:41.865752 arm64_za-ptrace_Set_VL_7632 pass
14205 11:32:41.865853 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14206 11:32:41.866145 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14207 11:32:41.866238 arm64_za-ptrace_Set_VL_7648 pass
14208 11:32:41.866322 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14209 11:32:41.874635 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14210 11:32:41.874866 arm64_za-ptrace_Set_VL_7664 pass
14211 11:32:41.875185 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14212 11:32:41.875284 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14213 11:32:41.875371 arm64_za-ptrace_Set_VL_7680 pass
14214 11:32:41.875454 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14215 11:32:41.875540 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14216 11:32:41.875645 arm64_za-ptrace_Set_VL_7696 pass
14217 11:32:41.875735 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14218 11:32:41.897204 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14219 11:32:41.897448 arm64_za-ptrace_Set_VL_7712 pass
14220 11:32:41.897783 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14221 11:32:41.897897 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14222 11:32:41.897992 arm64_za-ptrace_Set_VL_7728 pass
14223 11:32:41.898085 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14224 11:32:41.898176 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14225 11:32:41.898286 arm64_za-ptrace_Set_VL_7744 pass
14226 11:32:41.898379 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14227 11:32:41.898445 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14228 11:32:41.898546 arm64_za-ptrace_Set_VL_7760 pass
14229 11:32:41.898630 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14230 11:32:41.898906 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14231 11:32:41.899001 arm64_za-ptrace_Set_VL_7776 pass
14232 11:32:41.899105 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14233 11:32:41.899208 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14234 11:32:41.899335 arm64_za-ptrace_Set_VL_7792 pass
14235 11:32:41.899433 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14236 11:32:41.899520 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14237 11:32:41.899620 arm64_za-ptrace_Set_VL_7808 pass
14238 11:32:41.899708 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14239 11:32:41.899784 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14240 11:32:41.899856 arm64_za-ptrace_Set_VL_7824 pass
14241 11:32:41.899956 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14242 11:32:41.900070 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14243 11:32:41.900179 arm64_za-ptrace_Set_VL_7840 pass
14244 11:32:41.900280 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14245 11:32:41.900381 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14246 11:32:41.900485 arm64_za-ptrace_Set_VL_7856 pass
14247 11:32:41.900571 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14248 11:32:41.900670 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14249 11:32:41.900770 arm64_za-ptrace_Set_VL_7872 pass
14250 11:32:41.900854 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14251 11:32:41.900960 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14252 11:32:41.901065 arm64_za-ptrace_Set_VL_7888 pass
14253 11:32:41.901166 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14254 11:32:41.901282 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14255 11:32:41.901392 arm64_za-ptrace_Set_VL_7904 pass
14256 11:32:41.901696 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14257 11:32:41.901801 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14258 11:32:41.901906 arm64_za-ptrace_Set_VL_7920 pass
14259 11:32:41.901993 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14260 11:32:41.902266 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14261 11:32:41.906678 arm64_za-ptrace_Set_VL_7936 pass
14262 11:32:41.907107 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14263 11:32:41.907211 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14264 11:32:41.907297 arm64_za-ptrace_Set_VL_7952 pass
14265 11:32:41.907400 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14266 11:32:41.907527 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14267 11:32:41.907625 arm64_za-ptrace_Set_VL_7968 pass
14268 11:32:41.907714 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14269 11:32:41.907817 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14270 11:32:41.907905 arm64_za-ptrace_Set_VL_7984 pass
14271 11:32:41.908001 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14272 11:32:41.908104 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14273 11:32:41.908202 arm64_za-ptrace_Set_VL_8000 pass
14274 11:32:41.908313 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14275 11:32:41.908944 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14276 11:32:41.909144 arm64_za-ptrace_Set_VL_8016 pass
14277 11:32:41.909326 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14278 11:32:41.909494 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14279 11:32:41.909705 arm64_za-ptrace_Set_VL_8032 pass
14280 11:32:41.909886 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14281 11:32:41.910055 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14282 11:32:41.910203 arm64_za-ptrace_Set_VL_8048 pass
14283 11:32:41.910323 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14284 11:32:41.910464 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14285 11:32:41.910590 arm64_za-ptrace_Set_VL_8064 pass
14286 11:32:41.910706 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14287 11:32:41.914638 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14288 11:32:41.914858 arm64_za-ptrace_Set_VL_8080 pass
14289 11:32:41.915292 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14290 11:32:41.915547 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14291 11:32:41.915722 arm64_za-ptrace_Set_VL_8096 pass
14292 11:32:41.915876 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14293 11:32:41.916010 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14294 11:32:41.916156 arm64_za-ptrace_Set_VL_8112 pass
14295 11:32:41.916285 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14296 11:32:41.916421 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14297 11:32:41.916587 arm64_za-ptrace_Set_VL_8128 pass
14298 11:32:41.916695 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14299 11:32:41.916800 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14300 11:32:41.916916 arm64_za-ptrace_Set_VL_8144 pass
14301 11:32:41.917013 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14302 11:32:41.917123 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14303 11:32:41.917257 arm64_za-ptrace_Set_VL_8160 pass
14304 11:32:41.917361 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14305 11:32:41.917465 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14306 11:32:41.917577 arm64_za-ptrace_Set_VL_8176 pass
14307 11:32:41.917708 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14308 11:32:41.917801 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14309 11:32:41.917920 arm64_za-ptrace_Set_VL_8192 pass
14310 11:32:41.918038 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14311 11:32:41.918130 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14312 11:32:41.918259 arm64_za-ptrace pass
14313 11:32:41.918371 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14314 11:32:41.918469 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14315 11:32:41.918545 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14316 11:32:41.918635 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14317 11:32:41.922600 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14318 11:32:41.923164 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14319 11:32:41.923378 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14320 11:32:41.923753 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14321 11:32:41.923861 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14322 11:32:41.924000 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14323 11:32:41.924120 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14324 11:32:41.924475 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14325 11:32:41.924721 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14326 11:32:41.924905 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14327 11:32:41.925139 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14328 11:32:41.925546 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14329 11:32:41.925782 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14330 11:32:41.926021 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14331 11:32:41.926203 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14332 11:32:41.930622 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14333 11:32:41.930833 arm64_check_buffer_fill fail
14334 11:32:41.931150 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14335 11:32:41.931269 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14336 11:32:41.931812 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14337 11:32:41.931945 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14338 11:32:41.932438 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14339 11:32:41.932564 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14340 11:32:41.933078 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14341 11:32:41.933404 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14342 11:32:41.933524 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14343 11:32:41.933864 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14344 11:32:41.934185 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14345 11:32:41.942506 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14346 11:32:41.942712 arm64_check_child_memory fail
14347 11:32:41.943014 arm64_check_gcr_el1_cswitch fail
14348 11:32:41.943123 arm64_check_ksm_options fail
14349 11:32:41.943230 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14350 11:32:41.943344 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14351 11:32:41.943629 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14352 11:32:41.943944 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14353 11:32:41.944263 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14354 11:32:41.953674 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14355 11:32:41.954084 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14356 11:32:41.954601 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14357 11:32:41.954932 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14358 11:32:41.955306 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14359 11:32:41.955674 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14360 11:32:41.955834 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14361 11:32:41.956240 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14362 11:32:41.956551 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14363 11:32:41.956904 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14364 11:32:41.957260 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14365 11:32:41.957582 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14366 11:32:41.957719 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14367 11:32:41.958220 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14368 11:32:41.962453 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14369 11:32:41.962794 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14370 11:32:41.963134 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14371 11:32:41.963259 arm64_check_mmap_options fail
14372 11:32:41.963428 arm64_check_prctl_check_basic_read pass
14373 11:32:41.963539 arm64_check_prctl_NONE pass
14374 11:32:41.963639 arm64_check_prctl_SYNC pass
14375 11:32:41.963722 arm64_check_prctl_ASYNC pass
14376 11:32:41.963809 arm64_check_prctl_SYNC_ASYNC pass
14377 11:32:41.963909 arm64_check_prctl pass
14378 11:32:41.963992 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14379 11:32:41.964099 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14380 11:32:41.964220 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14381 11:32:41.964344 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14382 11:32:41.964473 arm64_check_tags_inclusion fail
14383 11:32:41.964592 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14384 11:32:41.964697 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14385 11:32:41.964994 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14386 11:32:41.965110 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14387 11:32:41.965467 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14388 11:32:41.965568 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14389 11:32:41.965684 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14390 11:32:41.965784 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14391 11:32:41.966087 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14392 11:32:41.966190 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14393 11:32:41.970477 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14394 11:32:41.970867 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14395 11:32:41.971021 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14396 11:32:41.971416 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14397 11:32:41.971592 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14398 11:32:41.971789 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14399 11:32:41.971962 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14400 11:32:41.972345 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14401 11:32:41.972501 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14402 11:32:41.972689 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14403 11:32:41.972911 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14404 11:32:41.973150 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14405 11:32:41.973365 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14406 11:32:41.973568 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14407 11:32:41.973983 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14408 11:32:41.974116 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14409 11:32:41.974219 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14410 11:32:41.978522 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14411 11:32:41.978943 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14412 11:32:41.979049 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14413 11:32:41.979182 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14414 11:32:41.979492 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14415 11:32:41.979843 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14416 11:32:41.979953 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14417 11:32:41.980083 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14418 11:32:41.980403 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14419 11:32:41.980522 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14420 11:32:41.980814 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14421 11:32:41.980921 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14422 11:32:41.981231 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14423 11:32:41.981577 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14424 11:32:41.981815 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14425 11:32:41.982017 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14426 11:32:41.986475 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14427 11:32:41.986838 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14428 11:32:41.986962 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14429 11:32:41.987083 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14430 11:32:41.987377 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14431 11:32:41.987705 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14432 11:32:41.988090 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14433 11:32:41.988334 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14434 11:32:41.988596 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14435 11:32:41.988819 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14436 11:32:41.989025 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14437 11:32:41.989232 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14438 11:32:41.989487 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14439 11:32:41.989954 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14440 11:32:41.990068 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14441 11:32:41.994564 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14442 11:32:41.994926 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14443 11:32:41.995049 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14444 11:32:41.995359 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14445 11:32:42.020917 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14446 11:32:42.021467 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14447 11:32:42.021573 arm64_check_user_mem pass
14448 11:32:42.021671 arm64_btitest_nohint_func_call_using_br_x0 pass
14449 11:32:42.021759 arm64_btitest_nohint_func_call_using_br_x16 pass
14450 11:32:42.021862 arm64_btitest_nohint_func_call_using_blr pass
14451 11:32:42.021950 arm64_btitest_bti_none_func_call_using_br_x0 pass
14452 11:32:42.022035 arm64_btitest_bti_none_func_call_using_br_x16 pass
14453 11:32:42.022122 arm64_btitest_bti_none_func_call_using_blr pass
14454 11:32:42.022226 arm64_btitest_bti_c_func_call_using_br_x0 pass
14455 11:32:42.022317 arm64_btitest_bti_c_func_call_using_br_x16 pass
14456 11:32:42.022400 arm64_btitest_bti_c_func_call_using_blr pass
14457 11:32:42.022915 arm64_btitest_bti_j_func_call_using_br_x0 pass
14458 11:32:42.023018 arm64_btitest_bti_j_func_call_using_br_x16 pass
14459 11:32:42.023104 arm64_btitest_bti_j_func_call_using_blr pass
14460 11:32:42.023188 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14461 11:32:42.023508 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14462 11:32:42.023694 arm64_btitest_bti_jc_func_call_using_blr pass
14463 11:32:42.023853 arm64_btitest_paciasp_func_call_using_br_x0 pass
14464 11:32:42.024038 arm64_btitest_paciasp_func_call_using_br_x16 pass
14465 11:32:42.024207 arm64_btitest_paciasp_func_call_using_blr pass
14466 11:32:42.024378 arm64_btitest pass
14467 11:32:42.024533 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14468 11:32:42.024698 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14469 11:32:42.024867 arm64_nobtitest_nohint_func_call_using_blr pass
14470 11:32:42.025053 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14471 11:32:42.025233 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14472 11:32:42.025401 arm64_nobtitest_bti_none_func_call_using_blr pass
14473 11:32:42.025544 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14474 11:32:42.025721 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14475 11:32:42.025881 arm64_nobtitest_bti_c_func_call_using_blr pass
14476 11:32:42.026071 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14477 11:32:42.026216 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14478 11:32:42.026337 arm64_nobtitest_bti_j_func_call_using_blr pass
14479 11:32:42.026452 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14480 11:32:42.026568 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14481 11:32:42.026683 arm64_nobtitest_bti_jc_func_call_using_blr pass
14482 11:32:42.026799 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14483 11:32:42.026915 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14484 11:32:42.027029 arm64_nobtitest_paciasp_func_call_using_blr pass
14485 11:32:42.027166 arm64_nobtitest pass
14486 11:32:42.030665 arm64_hwcap_cpuinfo_match_RNG pass
14487 11:32:42.031089 arm64_hwcap_sigill_RNG pass
14488 11:32:42.031239 arm64_hwcap_cpuinfo_match_SME pass
14489 11:32:42.031378 arm64_hwcap_sigill_SME pass
14490 11:32:42.031506 arm64_hwcap_cpuinfo_match_SVE pass
14491 11:32:42.031635 arm64_hwcap_sigill_SVE pass
14492 11:32:42.031803 arm64_hwcap_cpuinfo_match_SVE_2 pass
14493 11:32:42.031896 arm64_hwcap_sigill_SVE_2 pass
14494 11:32:42.031965 arm64_hwcap_cpuinfo_match_SVE_AES pass
14495 11:32:42.032026 arm64_hwcap_sigill_SVE_AES pass
14496 11:32:42.032087 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14497 11:32:42.032148 arm64_hwcap_sigill_SVE2_PMULL pass
14498 11:32:42.032208 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14499 11:32:42.032282 arm64_hwcap_sigill_SVE2_BITPERM pass
14500 11:32:42.032510 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14501 11:32:42.032628 arm64_hwcap_sigill_SVE2_SHA3 pass
14502 11:32:42.032742 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14503 11:32:42.032848 arm64_hwcap_sigill_SVE2_SM4 pass
14504 11:32:42.032944 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14505 11:32:42.033014 arm64_hwcap_sigill_SVE2_I8MM pass
14506 11:32:42.033075 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14507 11:32:42.033135 arm64_hwcap_sigill_SVE2_F32MM pass
14508 11:32:42.033195 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14509 11:32:42.033269 arm64_hwcap_sigill_SVE2_F64MM pass
14510 11:32:42.033344 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14511 11:32:42.033439 arm64_hwcap_sigill_SVE2_BF16 pass
14512 11:32:42.033524 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14513 11:32:42.033602 arm64_hwcap_sigill_SVE2_EBF16 skip
14514 11:32:42.033677 arm64_hwcap pass
14515 11:32:42.033781 arm64_ptrace_read_tpidr_one pass
14516 11:32:42.033895 arm64_ptrace_write_tpidr_one pass
14517 11:32:42.033992 arm64_ptrace_verify_tpidr_one pass
14518 11:32:42.034106 arm64_ptrace_count_tpidrs pass
14519 11:32:42.034197 arm64_ptrace_tpidr2_write pass
14520 11:32:42.034283 arm64_ptrace_tpidr2_read pass
14521 11:32:42.034388 arm64_ptrace_write_tpidr_only pass
14522 11:32:42.034464 arm64_ptrace pass
14523 11:32:42.034524 arm64_syscall-abi_getpid_FPSIMD pass
14524 11:32:42.034584 arm64_syscall-abi_getpid_SVE_VL_256 pass
14525 11:32:42.034642 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14526 11:32:42.034716 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14527 11:32:42.034779 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14528 11:32:42.034839 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14529 11:32:42.038646 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14530 11:32:42.038994 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14531 11:32:42.039105 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14532 11:32:42.039204 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14533 11:32:42.039324 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14534 11:32:42.039434 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14535 11:32:42.039554 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14536 11:32:42.039658 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14537 11:32:42.039757 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14538 11:32:42.039854 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14539 11:32:42.039950 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14540 11:32:42.040054 arm64_syscall-abi_getpid_SVE_VL_240 pass
14541 11:32:42.040146 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14542 11:32:42.040453 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14543 11:32:42.040566 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14544 11:32:42.040927 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14545 11:32:42.041038 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14546 11:32:42.041150 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14547 11:32:42.041281 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14548 11:32:42.041372 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14549 11:32:42.041505 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14550 11:32:42.041604 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14551 11:32:42.041736 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14552 11:32:42.042041 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14553 11:32:42.042141 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14554 11:32:42.042260 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14555 11:32:42.042352 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14556 11:32:42.047100 arm64_syscall-abi_getpid_SVE_VL_224 pass
14557 11:32:42.047295 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14558 11:32:42.047385 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14559 11:32:42.047474 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14560 11:32:42.047581 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14561 11:32:42.047679 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14562 11:32:42.047816 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14563 11:32:42.047909 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14564 11:32:42.047989 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14565 11:32:42.048081 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14566 11:32:42.048174 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14567 11:32:42.048305 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14568 11:32:42.048439 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14569 11:32:42.048571 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14570 11:32:42.048682 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14571 11:32:42.048808 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14572 11:32:42.048911 arm64_syscall-abi_getpid_SVE_VL_208 pass
14573 11:32:42.049027 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14574 11:32:42.049115 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14575 11:32:42.049447 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14576 11:32:42.049686 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14577 11:32:42.049795 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14578 11:32:42.049917 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14579 11:32:42.050017 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14580 11:32:42.050139 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14581 11:32:42.050252 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14582 11:32:42.054700 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14583 11:32:42.054920 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14584 11:32:42.055244 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14585 11:32:42.055351 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14586 11:32:42.055444 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14587 11:32:42.055525 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14588 11:32:42.055624 arm64_syscall-abi_getpid_SVE_VL_192 pass
14589 11:32:42.055744 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14590 11:32:42.055841 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14591 11:32:42.055970 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14592 11:32:42.056066 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14593 11:32:42.056194 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14594 11:32:42.056327 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14595 11:32:42.056411 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14596 11:32:42.056495 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14597 11:32:42.056597 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14598 11:32:42.056694 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14599 11:32:42.056816 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14600 11:32:42.056948 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14601 11:32:42.057061 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14602 11:32:42.057193 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14603 11:32:42.057309 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14604 11:32:42.057435 arm64_syscall-abi_getpid_SVE_VL_176 pass
14605 11:32:42.057568 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14606 11:32:42.057685 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14607 11:32:42.057796 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14608 11:32:42.057915 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14609 11:32:42.058218 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14610 11:32:42.058324 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14611 11:32:42.058412 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14612 11:32:42.062775 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14613 11:32:42.062994 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14614 11:32:42.063462 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14615 11:32:42.082333 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14616 11:32:42.083213 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14617 11:32:42.083311 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14618 11:32:42.083385 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14619 11:32:42.083479 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14620 11:32:42.083586 arm64_syscall-abi_getpid_SVE_VL_160 pass
14621 11:32:42.083700 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14622 11:32:42.083809 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14623 11:32:42.083934 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14624 11:32:42.084037 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14625 11:32:42.084156 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14626 11:32:42.084258 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14627 11:32:42.084395 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14628 11:32:42.084503 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14629 11:32:42.084633 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14630 11:32:42.084748 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14631 11:32:42.084885 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14632 11:32:42.085021 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14633 11:32:42.085148 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14634 11:32:42.085281 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14635 11:32:42.085416 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14636 11:32:42.085553 arm64_syscall-abi_getpid_SVE_VL_144 pass
14637 11:32:42.085700 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14638 11:32:42.086013 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14639 11:32:42.086125 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14640 11:32:42.086230 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14641 11:32:42.090496 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14642 11:32:42.090843 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14643 11:32:42.090932 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14644 11:32:42.091214 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14645 11:32:42.091325 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14646 11:32:42.091444 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14647 11:32:42.091554 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14648 11:32:42.091657 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14649 11:32:42.091750 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14650 11:32:42.092050 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14651 11:32:42.092161 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14652 11:32:42.092270 arm64_syscall-abi_getpid_SVE_VL_128 pass
14653 11:32:42.092367 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14654 11:32:42.092495 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14655 11:32:42.092847 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14656 11:32:42.092965 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14657 11:32:42.093071 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14658 11:32:42.093175 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14659 11:32:42.093277 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14660 11:32:42.093624 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14661 11:32:42.093738 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14662 11:32:42.093840 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14663 11:32:42.094038 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14664 11:32:42.094160 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14665 11:32:42.098625 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14666 11:32:42.099038 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14667 11:32:42.099146 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14668 11:32:42.099234 arm64_syscall-abi_getpid_SVE_VL_112 pass
14669 11:32:42.099318 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14670 11:32:42.099420 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14671 11:32:42.099512 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14672 11:32:42.099598 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14673 11:32:42.099699 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14674 11:32:42.099800 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14675 11:32:42.100111 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14676 11:32:42.100228 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14677 11:32:42.100347 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14678 11:32:42.100444 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14679 11:32:42.100573 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14680 11:32:42.100876 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14681 11:32:42.100990 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14682 11:32:42.101102 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14683 11:32:42.101204 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14684 11:32:42.101303 arm64_syscall-abi_getpid_SVE_VL_96 pass
14685 11:32:42.101623 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14686 11:32:42.101734 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14687 11:32:42.101859 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14688 11:32:42.101975 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14689 11:32:42.102124 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14690 11:32:42.102428 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14691 11:32:42.106490 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14692 11:32:42.106852 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14693 11:32:42.106956 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14694 11:32:42.107083 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14695 11:32:42.107176 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14696 11:32:42.107476 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14697 11:32:42.107582 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14698 11:32:42.107688 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14699 11:32:42.107800 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14700 11:32:42.107903 arm64_syscall-abi_getpid_SVE_VL_80 pass
14701 11:32:42.108030 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14702 11:32:42.108141 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14703 11:32:42.108273 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14704 11:32:42.108393 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14705 11:32:42.108732 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14706 11:32:42.108847 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14707 11:32:42.108972 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14708 11:32:42.109071 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14709 11:32:42.109194 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14710 11:32:42.109322 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14711 11:32:42.109616 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14712 11:32:42.109749 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14713 11:32:42.109870 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14714 11:32:42.109976 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14715 11:32:42.110079 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14716 11:32:42.110159 arm64_syscall-abi_getpid_SVE_VL_64 pass
14717 11:32:42.114606 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14718 11:32:42.115055 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14719 11:32:42.115166 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14720 11:32:42.115262 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14721 11:32:42.115355 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14722 11:32:42.115456 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14723 11:32:42.115548 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14724 11:32:42.115635 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14725 11:32:42.115738 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14726 11:32:42.115825 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14727 11:32:42.115909 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14728 11:32:42.116009 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14729 11:32:42.116333 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14730 11:32:42.116448 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14731 11:32:42.116538 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14732 11:32:42.116640 arm64_syscall-abi_getpid_SVE_VL_48 pass
14733 11:32:42.116741 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14734 11:32:42.116845 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14735 11:32:42.116954 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14736 11:32:42.117259 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14737 11:32:42.117367 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14738 11:32:42.117452 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14739 11:32:42.117553 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14740 11:32:42.117661 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14741 11:32:42.117968 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14742 11:32:42.118072 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14743 11:32:42.118171 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14744 11:32:42.122467 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14745 11:32:42.122785 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14746 11:32:42.122891 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14747 11:32:42.122982 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14748 11:32:42.123082 arm64_syscall-abi_getpid_SVE_VL_32 pass
14749 11:32:42.123169 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14750 11:32:42.123269 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14751 11:32:42.123374 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14752 11:32:42.123479 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14753 11:32:42.123579 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14754 11:32:42.123879 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
14755 11:32:42.123975 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
14756 11:32:42.124259 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
14757 11:32:42.124349 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
14758 11:32:42.124439 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
14759 11:32:42.124709 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
14760 11:32:42.124810 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
14761 11:32:42.124913 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
14762 11:32:42.125013 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
14763 11:32:42.125096 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
14764 11:32:42.125176 arm64_syscall-abi_getpid_SVE_VL_16 pass
14765 11:32:42.125252 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
14766 11:32:42.125316 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
14767 11:32:42.145260 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
14768 11:32:42.145531 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
14769 11:32:42.145841 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
14770 11:32:42.145943 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
14771 11:32:42.146021 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
14772 11:32:42.146097 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
14773 11:32:42.146170 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
14774 11:32:42.146256 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
14775 11:32:42.146329 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
14776 11:32:42.146400 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
14777 11:32:42.146484 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
14778 11:32:42.146758 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
14779 11:32:42.146864 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
14780 11:32:42.147342 arm64_syscall-abi_sched_yield_FPSIMD pass
14781 11:32:42.147449 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
14782 11:32:42.147734 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
14783 11:32:42.148027 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
14784 11:32:42.148120 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
14785 11:32:42.148205 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
14786 11:32:42.148484 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
14787 11:32:42.148577 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
14788 11:32:42.148664 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
14789 11:32:42.148749 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
14790 11:32:42.149230 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
14791 11:32:42.149341 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
14792 11:32:42.149446 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
14793 11:32:42.149752 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
14794 11:32:42.149855 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
14795 11:32:42.150154 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
14796 11:32:42.150255 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
14797 11:32:42.154611 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
14798 11:32:42.155030 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
14799 11:32:42.155139 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
14800 11:32:42.155225 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
14801 11:32:42.155325 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
14802 11:32:42.155413 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
14803 11:32:42.155711 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
14804 11:32:42.155815 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
14805 11:32:42.155916 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
14806 11:32:42.156020 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
14807 11:32:42.156118 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
14808 11:32:42.156333 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
14809 11:32:42.156452 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
14810 11:32:42.156752 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
14811 11:32:42.156857 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
14812 11:32:42.156958 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
14813 11:32:42.157062 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
14814 11:32:42.157162 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
14815 11:32:42.157259 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
14816 11:32:42.157556 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
14817 11:32:42.157670 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
14818 11:32:42.157771 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
14819 11:32:42.157855 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
14820 11:32:42.157951 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
14821 11:32:42.158257 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
14822 11:32:42.162432 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
14823 11:32:42.162831 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
14824 11:32:42.162929 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
14825 11:32:42.163023 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
14826 11:32:42.163126 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
14827 11:32:42.163231 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
14828 11:32:42.163517 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
14829 11:32:42.163606 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
14830 11:32:42.163717 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
14831 11:32:42.163990 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
14832 11:32:42.164077 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
14833 11:32:42.164359 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
14834 11:32:42.164447 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
14835 11:32:42.164751 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
14836 11:32:42.164873 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
14837 11:32:42.164981 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
14838 11:32:42.165281 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
14839 11:32:42.165391 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
14840 11:32:42.165685 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
14841 11:32:42.165783 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
14842 11:32:42.165894 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
14843 11:32:42.166092 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
14844 11:32:42.170380 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
14845 11:32:42.170813 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
14846 11:32:42.170911 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
14847 11:32:42.171000 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
14848 11:32:42.171100 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
14849 11:32:42.171203 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
14850 11:32:42.171411 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
14851 11:32:42.171534 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
14852 11:32:42.171831 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
14853 11:32:42.171928 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
14854 11:32:42.172028 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
14855 11:32:42.172319 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
14856 11:32:42.172417 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
14857 11:32:42.172517 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
14858 11:32:42.172808 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
14859 11:32:42.172905 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
14860 11:32:42.173195 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
14861 11:32:42.173291 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
14862 11:32:42.173394 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
14863 11:32:42.173498 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
14864 11:32:42.173602 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
14865 11:32:42.173919 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
14866 11:32:42.174040 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
14867 11:32:42.178360 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
14868 11:32:42.178801 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
14869 11:32:42.178911 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
14870 11:32:42.179001 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
14871 11:32:42.179102 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
14872 11:32:42.179209 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
14873 11:32:42.179320 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
14874 11:32:42.179623 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
14875 11:32:42.179745 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
14876 11:32:42.179853 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
14877 11:32:42.179990 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
14878 11:32:42.180123 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
14879 11:32:42.180429 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
14880 11:32:42.180547 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
14881 11:32:42.180651 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
14882 11:32:42.180783 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
14883 11:32:42.181091 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
14884 11:32:42.181197 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
14885 11:32:42.181299 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
14886 11:32:42.181400 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
14887 11:32:42.181499 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
14888 11:32:42.181796 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
14889 11:32:42.181902 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
14890 11:32:42.182003 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
14891 11:32:42.186402 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
14892 11:32:42.186835 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
14893 11:32:42.186924 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
14894 11:32:42.187016 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
14895 11:32:42.187114 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
14896 11:32:42.187401 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
14897 11:32:42.187494 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
14898 11:32:42.187590 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
14899 11:32:42.187867 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
14900 11:32:42.187976 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
14901 11:32:42.188072 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
14902 11:32:42.188171 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
14903 11:32:42.188475 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
14904 11:32:42.188578 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
14905 11:32:42.188875 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
14906 11:32:42.188978 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
14907 11:32:42.199014 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
14908 11:32:42.199467 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
14909 11:32:42.199565 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
14910 11:32:42.199640 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
14911 11:32:42.199726 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
14912 11:32:42.200009 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
14913 11:32:42.200116 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
14914 11:32:42.200218 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
14915 11:32:42.200514 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
14916 11:32:42.200632 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
14917 11:32:42.200718 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
14918 11:32:42.200912 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
14919 11:32:42.201038 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
14920 11:32:42.201146 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
14921 11:32:42.201454 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
14922 11:32:42.201557 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
14923 11:32:42.201665 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
14924 11:32:42.201771 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
14925 11:32:42.202075 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
14926 11:32:42.202193 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
14927 11:32:42.202293 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
14928 11:32:42.202390 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
14929 11:32:42.202686 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
14930 11:32:42.206415 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
14931 11:32:42.206847 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
14932 11:32:42.206955 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
14933 11:32:42.207049 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
14934 11:32:42.207151 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
14935 11:32:42.207235 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
14936 11:32:42.207333 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
14937 11:32:42.207435 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
14938 11:32:42.207756 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
14939 11:32:42.207858 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
14940 11:32:42.207961 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
14941 11:32:42.208069 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
14942 11:32:42.208364 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
14943 11:32:42.208468 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
14944 11:32:42.208566 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
14945 11:32:42.208666 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
14946 11:32:42.208964 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
14947 11:32:42.209074 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
14948 11:32:42.209175 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
14949 11:32:42.209276 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
14950 11:32:42.209575 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
14951 11:32:42.209689 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
14952 11:32:42.209792 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
14953 11:32:42.210112 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
14954 11:32:42.210218 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
14955 11:32:42.210319 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
14956 11:32:42.210406 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
14957 11:32:42.210504 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
14958 11:32:42.210605 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
14959 11:32:42.210904 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
14960 11:32:42.214367 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
14961 11:32:42.214794 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
14962 11:32:42.214901 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
14963 11:32:42.215005 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
14964 11:32:42.215100 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
14965 11:32:42.215195 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
14966 11:32:42.215293 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
14967 11:32:42.215401 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
14968 11:32:42.215715 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
14969 11:32:42.215832 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
14970 11:32:42.215933 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
14971 11:32:42.216044 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
14972 11:32:42.216350 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
14973 11:32:42.216466 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
14974 11:32:42.216771 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
14975 11:32:42.216877 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
14976 11:32:42.216984 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
14977 11:32:42.217094 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
14978 11:32:42.217201 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
14979 11:32:42.217511 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
14980 11:32:42.217628 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
14981 11:32:42.217738 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
14982 11:32:42.218050 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
14983 11:32:42.218169 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
14984 11:32:42.218276 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
14985 11:32:42.218564 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
14986 11:32:42.226376 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
14987 11:32:42.226841 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
14988 11:32:42.226949 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
14989 11:32:42.227042 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
14990 11:32:42.227144 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
14991 11:32:42.227241 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
14992 11:32:42.227345 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
14993 11:32:42.227626 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
14994 11:32:42.227712 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
14995 11:32:42.228195 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
14996 11:32:42.228279 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
14997 11:32:42.228343 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
14998 11:32:42.228405 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
14999 11:32:42.228467 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15000 11:32:42.228721 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15001 11:32:42.228802 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15002 11:32:42.228865 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15003 11:32:42.228939 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15004 11:32:42.229003 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15005 11:32:42.229075 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15006 11:32:42.229337 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15007 11:32:42.229430 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15008 11:32:42.229505 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15009 11:32:42.229756 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15010 11:32:42.229825 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15011 11:32:42.229906 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15012 11:32:42.230173 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15013 11:32:42.234442 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15014 11:32:42.234860 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15015 11:32:42.234955 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15016 11:32:42.235046 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15017 11:32:42.235149 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15018 11:32:42.235238 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15019 11:32:42.235529 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15020 11:32:42.235634 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15021 11:32:42.235734 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15022 11:32:42.236011 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15023 11:32:42.236127 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15024 11:32:42.236624 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15025 11:32:42.236729 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15026 11:32:42.237011 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15027 11:32:42.237112 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15028 11:32:42.237218 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15029 11:32:42.237320 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15030 11:32:42.237618 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15031 11:32:42.237749 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15032 11:32:42.237853 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15033 11:32:42.237954 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15034 11:32:42.242369 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15035 11:32:42.242774 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15036 11:32:42.242881 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15037 11:32:42.242984 arm64_syscall-abi pass
15038 11:32:42.243076 arm64_tpidr2_default_value pass
15039 11:32:42.243160 arm64_tpidr2_write_read pass
15040 11:32:42.243255 arm64_tpidr2_write_sleep_read pass
15041 11:32:42.243341 arm64_tpidr2_write_fork_read pass
15042 11:32:42.243443 arm64_tpidr2_write_clone_read pass
15043 11:32:42.243529 arm64_tpidr2 pass
15044 11:32:42.252101 + ../../utils/send-to-lava.sh ./output/result.txt
15045 11:32:42.314048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15046 11:32:42.315039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15048 11:32:42.360723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15049 11:32:42.361289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15051 11:32:42.402919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15052 11:32:42.403490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15054 11:32:42.445821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15055 11:32:42.446225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15057 11:32:42.485928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15058 11:32:42.486356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15060 11:32:42.528930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15061 11:32:42.529356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15063 11:32:42.570119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15064 11:32:42.570546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15066 11:32:42.612982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15067 11:32:42.613543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15069 11:32:42.655781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15070 11:32:42.656291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15072 11:32:42.702262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15073 11:32:42.702665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15075 11:32:42.745940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15076 11:32:42.746338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15078 11:32:42.784834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15079 11:32:42.785251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15081 11:32:42.828550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15082 11:32:42.828953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15084 11:32:42.863703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15086 11:32:42.864130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15087 11:32:42.901595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15088 11:32:42.902004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15090 11:32:42.943395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15091 11:32:42.943786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15093 11:32:42.992473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15094 11:32:42.992912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15096 11:32:43.040319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15098 11:32:43.040791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15099 11:32:43.095892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15101 11:32:43.096643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15102 11:32:43.135279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15104 11:32:43.135878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15105 11:32:43.171712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15106 11:32:43.172126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15108 11:32:43.209208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15110 11:32:43.209626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15111 11:32:43.245700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15112 11:32:43.246095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15114 11:32:43.286604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15116 11:32:43.288596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15117 11:32:43.324039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15118 11:32:43.324504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15120 11:32:43.367606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15121 11:32:43.368045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15123 11:32:43.409128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15124 11:32:43.409558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15126 11:32:43.446123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15127 11:32:43.446614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15129 11:32:43.492972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15131 11:32:43.493693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15132 11:32:43.533157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15133 11:32:43.533675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15135 11:32:43.572182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15136 11:32:43.572640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15138 11:32:43.614163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15140 11:32:43.614917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15141 11:32:43.657192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15143 11:32:43.657668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15144 11:32:43.696983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15146 11:32:43.697449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15147 11:32:43.751069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15148 11:32:43.751498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15150 11:32:43.789366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15152 11:32:43.789754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15153 11:32:43.831559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15154 11:32:43.832106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15156 11:32:43.876406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15157 11:32:43.876861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15159 11:32:43.921026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15161 11:32:43.921972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15162 11:32:43.964298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15164 11:32:43.964944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15165 11:32:44.013724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15166 11:32:44.014166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15168 11:32:44.056926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15170 11:32:44.057400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15171 11:32:44.101656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15172 11:32:44.102092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15174 11:32:44.142695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15176 11:32:44.143170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15177 11:32:44.190315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15178 11:32:44.190893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15180 11:32:44.237625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15182 11:32:44.238080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15183 11:32:44.283311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15184 11:32:44.283766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15186 11:32:44.323317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15187 11:32:44.323782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15189 11:32:44.367875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15191 11:32:44.371142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15192 11:32:44.407358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15194 11:32:44.407823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15195 11:32:44.449789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15197 11:32:44.450236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15198 11:32:44.486350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15200 11:32:44.486826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15201 11:32:44.527700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15202 11:32:44.528146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15204 11:32:44.567354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15206 11:32:44.567802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15207 11:32:44.609945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15208 11:32:44.610389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15210 11:32:44.654146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15211 11:32:44.654566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15213 11:32:44.690602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15215 11:32:44.691368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15216 11:32:44.729148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15217 11:32:44.729661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15219 11:32:44.766290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15221 11:32:44.766764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15222 11:32:44.812293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15223 11:32:44.812743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15225 11:32:44.846246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15227 11:32:44.846722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15228 11:32:44.893029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15229 11:32:44.893469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15231 11:32:44.931383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15232 11:32:44.931832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15234 11:32:44.971698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15236 11:32:44.972413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15237 11:32:45.009466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15238 11:32:45.009895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15240 11:32:45.051237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15241 11:32:45.051658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15243 11:32:45.096762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15244 11:32:45.097258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15246 11:32:45.139831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15247 11:32:45.140260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15249 11:32:45.179259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15251 11:32:45.179727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15252 11:32:45.216393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15253 11:32:45.216785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15255 11:32:45.255971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15257 11:32:45.256390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15258 11:32:45.296941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15260 11:32:45.297406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15261 11:32:45.332549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15262 11:32:45.332972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15264 11:32:45.371604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15266 11:32:45.371991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15267 11:32:45.408790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15269 11:32:45.409549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15270 11:32:45.447272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15271 11:32:45.447840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15273 11:32:45.489791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15274 11:32:45.490198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15276 11:32:45.532409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15278 11:32:45.532887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15279 11:32:45.574179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15280 11:32:45.574606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15282 11:32:45.613767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15283 11:32:45.614212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15285 11:32:45.659859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15286 11:32:45.660277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15288 11:32:45.706291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15290 11:32:45.706665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15291 11:32:45.748362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15292 11:32:45.748900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15294 11:32:45.785583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15295 11:32:45.786076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15297 11:32:45.830011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15298 11:32:45.830442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15300 11:32:45.873090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15301 11:32:45.873474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15303 11:32:45.915413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15304 11:32:45.915867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15306 11:32:45.953322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15307 11:32:45.953797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15309 11:32:46.000146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15311 11:32:46.000612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15312 11:32:46.045816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15313 11:32:46.046241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15315 11:32:46.097316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15316 11:32:46.097748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15318 11:32:46.144769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15319 11:32:46.145295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15321 11:32:46.187782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15322 11:32:46.188194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15324 11:32:46.226489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15326 11:32:46.227188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15327 11:32:46.269143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15328 11:32:46.269573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15330 11:32:46.308755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15331 11:32:46.309185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15333 11:32:46.347848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15334 11:32:46.348272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15336 11:32:46.386249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15337 11:32:46.386676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15339 11:32:46.425976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15340 11:32:46.426406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15342 11:32:46.465637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15343 11:32:46.466066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15345 11:32:46.508020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15347 11:32:46.508685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15348 11:32:46.546230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15349 11:32:46.546680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15351 11:32:46.585825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15353 11:32:46.586286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15354 11:32:46.629894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15356 11:32:46.630371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15357 11:32:46.677884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15358 11:32:46.678329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15360 11:32:46.728412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15361 11:32:46.728846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15363 11:32:46.780413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15365 11:32:46.780853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15366 11:32:46.827007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15367 11:32:46.827468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15369 11:32:46.870097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15370 11:32:46.870530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15372 11:32:46.911985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15373 11:32:46.912420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15375 11:32:46.956693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15376 11:32:46.957104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15378 11:32:47.007572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15380 11:32:47.008054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15381 11:32:47.059220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15382 11:32:47.059648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15384 11:32:47.111400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15386 11:32:47.111866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15387 11:32:47.156892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15388 11:32:47.157323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15390 11:32:47.200318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15392 11:32:47.200784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15393 11:32:47.239383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15394 11:32:47.239813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15396 11:32:47.286116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15397 11:32:47.286541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15399 11:32:47.336861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15400 11:32:47.337291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15402 11:32:47.380084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15404 11:32:47.380459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15405 11:32:47.430053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15407 11:32:47.430503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15408 11:32:47.475840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15409 11:32:47.476275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15411 11:32:47.517951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15412 11:32:47.518401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15414 11:32:47.558843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15415 11:32:47.559270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15417 11:32:47.600399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15419 11:32:47.600844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15420 11:32:47.639918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15422 11:32:47.640378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15423 11:32:47.681174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15424 11:32:47.681623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15426 11:32:47.725152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15427 11:32:47.725583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15429 11:32:47.775741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15430 11:32:47.776179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15432 11:32:47.814616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15434 11:32:47.815233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15435 11:32:47.853722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15437 11:32:47.854321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15438 11:32:47.904313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15439 11:32:47.904722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15441 11:32:47.951126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15442 11:32:47.951709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15444 11:32:47.996179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15445 11:32:47.996610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15447 11:32:48.044675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15448 11:32:48.045236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15450 11:32:48.086760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15452 11:32:48.087227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15453 11:32:48.126608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15455 11:32:48.127080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15456 11:32:48.165596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15457 11:32:48.165991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15459 11:32:48.204937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15460 11:32:48.205357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15462 11:32:48.246336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15463 11:32:48.246771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15465 11:32:48.288752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15466 11:32:48.289176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15468 11:32:48.328271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15469 11:32:48.328658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15471 11:32:48.377435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15472 11:32:48.377851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15474 11:32:48.429124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15476 11:32:48.429728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15477 11:32:48.477998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15479 11:32:48.478439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15480 11:32:48.524607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15481 11:32:48.525075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15483 11:32:48.572638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15485 11:32:48.573117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15486 11:32:48.619626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15487 11:32:48.620078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15489 11:32:48.664677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15490 11:32:48.665231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15492 11:32:48.709545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15493 11:32:48.710007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15495 11:32:48.753767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15496 11:32:48.754213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15498 11:32:48.796047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15499 11:32:48.796553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15501 11:32:48.840308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15503 11:32:48.841071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15504 11:32:48.882806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15506 11:32:48.883274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15507 11:32:48.926969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15508 11:32:48.927410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15510 11:32:48.966177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15512 11:32:48.966653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15513 11:32:49.005163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15514 11:32:49.005705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15516 11:32:49.046308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15517 11:32:49.046851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15519 11:32:49.084093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15520 11:32:49.084517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15522 11:32:49.120654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15524 11:32:49.121147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15525 11:32:49.160767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15526 11:32:49.161195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15528 11:32:49.199803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15529 11:32:49.200230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15531 11:32:49.237715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15533 11:32:49.238186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15534 11:32:49.279504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15535 11:32:49.280016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15537 11:32:49.323036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15538 11:32:49.323456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15540 11:32:49.358152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15542 11:32:49.358621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15543 11:32:49.400480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15545 11:32:49.400955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15546 11:32:49.445925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15547 11:32:49.446382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15549 11:32:49.494037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15550 11:32:49.494500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15552 11:32:49.544417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15553 11:32:49.544864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15555 11:32:49.595133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15556 11:32:49.595662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15558 11:32:49.633681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15560 11:32:49.634034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15561 11:32:49.684751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15562 11:32:49.685138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15564 11:32:49.737277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15565 11:32:49.737695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15567 11:32:49.788157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15569 11:32:49.788904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15570 11:32:49.830159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15571 11:32:49.830639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15573 11:32:49.868229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15574 11:32:49.868610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15576 11:32:49.910241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15578 11:32:49.910666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15579 11:32:49.952481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15581 11:32:49.952962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15582 11:32:49.987761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15583 11:32:49.988202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15585 11:32:50.026634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15587 11:32:50.027356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15588 11:32:50.074691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15590 11:32:50.075121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15591 11:32:50.121432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15592 11:32:50.121880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15594 11:32:50.170415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15596 11:32:50.170833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15597 11:32:50.218904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15599 11:32:50.219518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15600 11:32:50.256628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15602 11:32:50.257212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15603 11:32:50.293422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15604 11:32:50.293877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15606 11:32:50.330289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15607 11:32:50.330743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15609 11:32:50.368395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15610 11:32:50.368918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15612 11:32:50.405069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15613 11:32:50.405556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15615 11:32:50.448492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15616 11:32:50.448924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15618 11:32:50.491740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15620 11:32:50.492202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15621 11:32:50.528912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15623 11:32:50.529333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15624 11:32:50.565622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15626 11:32:50.566114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15627 11:32:50.607182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15628 11:32:50.607607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15630 11:32:50.645641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15632 11:32:50.646113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15633 11:32:50.681366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15634 11:32:50.681805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15636 11:32:50.718208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15637 11:32:50.718705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15639 11:32:50.753782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15641 11:32:50.754237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15642 11:32:50.794214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15644 11:32:50.794698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15645 11:32:50.831730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15646 11:32:50.832154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15648 11:32:50.878684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15650 11:32:50.879452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15651 11:32:50.926111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15652 11:32:50.926542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15654 11:32:50.973229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15656 11:32:50.973608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15657 11:32:51.015996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15659 11:32:51.016410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15660 11:32:51.055143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15661 11:32:51.055577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15663 11:32:51.104729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15664 11:32:51.105133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15666 11:32:51.143356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15667 11:32:51.143789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15669 11:32:51.191726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15670 11:32:51.192143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15672 11:32:51.227063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15673 11:32:51.227490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15675 11:32:51.262589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15677 11:32:51.263052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15678 11:32:51.297627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15679 11:32:51.298058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15681 11:32:51.340677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15682 11:32:51.341107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15684 11:32:51.380495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15686 11:32:51.380957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15687 11:32:51.420481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15688 11:32:51.420904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15690 11:32:51.461792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15691 11:32:51.462284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15693 11:32:51.504394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15694 11:32:51.504944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15696 11:32:51.551516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15697 11:32:51.551993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15699 11:32:51.593281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15701 11:32:51.593743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15702 11:32:51.636150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15704 11:32:51.636563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15705 11:32:51.684633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15706 11:32:51.685027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15708 11:32:51.730658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15710 11:32:51.731105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15711 11:32:51.772077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15713 11:32:51.772457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15714 11:32:51.810506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15716 11:32:51.810963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15717 11:32:51.851916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15719 11:32:51.852492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15720 11:32:51.896419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15722 11:32:51.897033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15723 11:32:51.943190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15724 11:32:51.943693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15726 11:32:51.991507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15727 11:32:51.991939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15729 11:32:52.031117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15731 11:32:52.031900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15732 11:32:52.088198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15734 11:32:52.088675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15735 11:32:52.134136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15736 11:32:52.134527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15738 11:32:52.189899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15739 11:32:52.190339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15741 11:32:52.240699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15743 11:32:52.241164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15744 11:32:52.280019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15745 11:32:52.280407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15747 11:32:52.326746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15749 11:32:52.327213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15750 11:32:52.365223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15752 11:32:52.365813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15753 11:32:52.402068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15754 11:32:52.402537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
15756 11:32:52.440343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
15757 11:32:52.440760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
15759 11:32:52.479113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
15761 11:32:52.479564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
15762 11:32:52.517893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
15763 11:32:52.518332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
15765 11:32:52.557291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
15766 11:32:52.557683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
15768 11:32:52.595983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
15769 11:32:52.596414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
15771 11:32:52.647669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
15773 11:32:52.648156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
15774 11:32:52.700330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
15775 11:32:52.700758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
15777 11:32:52.749923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
15778 11:32:52.750357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
15780 11:32:52.797052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
15782 11:32:52.797644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
15783 11:32:52.846417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
15784 11:32:52.846987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
15786 11:32:52.890603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
15788 11:32:52.891161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
15789 11:32:52.942935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
15790 11:32:52.943368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
15792 11:32:52.980952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
15793 11:32:52.981373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
15795 11:32:53.021256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
15796 11:32:53.021671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
15798 11:32:53.057371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
15800 11:32:53.057806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
15801 11:32:53.095498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
15802 11:32:53.095923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
15804 11:32:53.140870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
15805 11:32:53.141419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
15807 11:32:53.180513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
15808 11:32:53.181091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
15810 11:32:53.217302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
15811 11:32:53.217786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
15813 11:32:53.255636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
15814 11:32:53.256068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
15816 11:32:53.295229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
15817 11:32:53.295679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
15819 11:32:53.336617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
15820 11:32:53.337114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
15822 11:32:53.373310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
15823 11:32:53.373798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
15825 11:32:53.410637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
15827 11:32:53.411236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
15828 11:32:53.446118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
15829 11:32:53.446612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
15831 11:32:53.488149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
15832 11:32:53.488545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
15834 11:32:53.521682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
15835 11:32:53.522154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
15837 11:32:53.555238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
15838 11:32:53.555780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
15840 11:32:53.589549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
15841 11:32:53.589981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
15843 11:32:53.625424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
15844 11:32:53.625859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
15846 11:32:53.660104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
15847 11:32:53.660622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
15849 11:32:53.698633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
15851 11:32:53.699093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
15852 11:32:53.739797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
15854 11:32:53.740259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
15855 11:32:53.777496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
15857 11:32:53.778268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
15858 11:32:53.816802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
15860 11:32:53.817452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
15861 11:32:53.853932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
15863 11:32:53.854361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
15864 11:32:53.892452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
15865 11:32:53.892855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
15867 11:32:53.944369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
15868 11:32:53.944772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
15870 11:32:53.979719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
15872 11:32:53.980143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
15873 11:32:54.018213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
15874 11:32:54.018616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
15876 11:32:54.058099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
15877 11:32:54.058516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
15879 11:32:54.096048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
15880 11:32:54.096537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
15882 11:32:54.132687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
15884 11:32:54.133274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
15885 11:32:54.172397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
15887 11:32:54.172871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
15888 11:32:54.213250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
15889 11:32:54.213696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
15891 11:32:54.257613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
15892 11:32:54.258049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
15894 11:32:54.302075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
15896 11:32:54.302545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
15897 11:32:54.345817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
15898 11:32:54.346331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
15900 11:32:54.382209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
15902 11:32:54.382871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
15903 11:32:54.418090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
15905 11:32:54.418541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
15906 11:32:54.454374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
15908 11:32:54.454834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
15909 11:32:54.490742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
15911 11:32:54.491312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
15912 11:32:54.527767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
15913 11:32:54.528209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
15915 11:32:54.572599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
15917 11:32:54.573078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
15918 11:32:54.615129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
15919 11:32:54.615584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
15921 11:32:54.652563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
15922 11:32:54.653010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
15924 11:32:54.688772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
15925 11:32:54.689145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
15927 11:32:54.727456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
15929 11:32:54.728217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
15930 11:32:54.763860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
15932 11:32:54.764445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
15933 11:32:54.804866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
15935 11:32:54.805326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
15936 11:32:54.842163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
15938 11:32:54.842647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
15939 11:32:54.880479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
15940 11:32:54.880863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
15942 11:32:54.928886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
15943 11:32:54.929315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
15945 11:32:54.979315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
15946 11:32:54.979844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
15948 11:32:55.028483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
15949 11:32:55.028900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
15951 11:32:55.075536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
15952 11:32:55.075914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
15954 11:32:55.125820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
15955 11:32:55.126323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
15957 11:32:55.166543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
15959 11:32:55.167023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
15960 11:32:55.207701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
15961 11:32:55.208079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
15963 11:32:55.260941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
15964 11:32:55.261495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
15966 11:32:55.301509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
15968 11:32:55.301946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
15969 11:32:55.340586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
15970 11:32:55.341077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
15972 11:32:55.379628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
15973 11:32:55.380035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
15975 11:32:55.418308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
15976 11:32:55.418743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
15978 11:32:55.463246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
15979 11:32:55.463670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
15981 11:32:55.511834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
15983 11:32:55.512224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
15984 11:32:55.563894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
15985 11:32:55.564331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
15987 11:32:55.606506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
15989 11:32:55.606987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
15990 11:32:55.652115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
15992 11:32:55.652535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
15993 11:32:55.697890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
15994 11:32:55.698298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
15996 11:32:55.745732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
15998 11:32:55.746318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
15999 11:32:55.793855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16000 11:32:55.794305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16002 11:32:55.842600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16004 11:32:55.843247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16005 11:32:55.890239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16007 11:32:55.890872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16008 11:32:55.939443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16009 11:32:55.939956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16011 11:32:55.980093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16012 11:32:55.980445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16014 11:32:56.014229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16015 11:32:56.014639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16017 11:32:56.049682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16019 11:32:56.050270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16020 11:32:56.084440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16022 11:32:56.085184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16023 11:32:56.119076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16025 11:32:56.119558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16026 11:32:56.152861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16027 11:32:56.153360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16029 11:32:56.188399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16030 11:32:56.188804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16032 11:32:56.227402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16033 11:32:56.227848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16035 11:32:56.277491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16036 11:32:56.277972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16038 11:32:56.333819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16040 11:32:56.334586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16041 11:32:56.390299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16042 11:32:56.390693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16044 11:32:56.439250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16045 11:32:56.439692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16047 11:32:56.475990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16048 11:32:56.476442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16050 11:32:56.512737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16051 11:32:56.513187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16053 11:32:56.549423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16055 11:32:56.549896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16056 11:32:56.584970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16057 11:32:56.585386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16059 11:32:56.620460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16060 11:32:56.620879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16062 11:32:56.657288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16064 11:32:56.657738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16065 11:32:56.695412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16066 11:32:56.695856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16068 11:32:56.732598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16070 11:32:56.733082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16071 11:32:56.770229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16072 11:32:56.770733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16074 11:32:56.818052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16076 11:32:56.818529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16077 11:32:56.857147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16078 11:32:56.857569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16080 11:32:56.902201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16081 11:32:56.902735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16083 11:32:56.944374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16084 11:32:56.944814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16086 11:32:56.985994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16087 11:32:56.986435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16089 11:32:57.025760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16090 11:32:57.026193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16092 11:32:57.061529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16093 11:32:57.061984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16095 11:32:57.098228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16096 11:32:57.098624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16098 11:32:57.145381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16099 11:32:57.145799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16101 11:32:57.193706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16102 11:32:57.194085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16104 11:32:57.246404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16106 11:32:57.246868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16107 11:32:57.286693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16109 11:32:57.287107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16110 11:32:57.321795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16112 11:32:57.322250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16113 11:32:57.360083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16114 11:32:57.360488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16116 11:32:57.401255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16118 11:32:57.401740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16119 11:32:57.441374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16120 11:32:57.441857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16122 11:32:57.481307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16123 11:32:57.481752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16125 11:32:57.516819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16126 11:32:57.517318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16128 11:32:57.551011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16129 11:32:57.551469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16131 11:32:57.587658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16132 11:32:57.588060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16134 11:32:57.628170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16136 11:32:57.628658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16137 11:32:57.663995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16138 11:32:57.664490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16140 11:32:57.708366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16141 11:32:57.708868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16143 11:32:57.755638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16144 11:32:57.756054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16146 11:32:57.791489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16148 11:32:57.791951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16149 11:32:57.831844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16150 11:32:57.832289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16152 11:32:57.872659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16153 11:32:57.873086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16155 11:32:57.909711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16157 11:32:57.910189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16158 11:32:57.959701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16159 11:32:57.960196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16161 11:32:58.008080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16163 11:32:58.008753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16164 11:32:58.057192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16166 11:32:58.057787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16167 11:32:58.107580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16169 11:32:58.108260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16170 11:32:58.154299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16171 11:32:58.154764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16173 11:32:58.202620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16175 11:32:58.203268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16176 11:32:58.241172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16178 11:32:58.241848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16179 11:32:58.289359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16180 11:32:58.289778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16182 11:32:58.349268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16183 11:32:58.349819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16185 11:32:58.408664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16186 11:32:58.409083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16188 11:32:58.465074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16189 11:32:58.465496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16191 11:32:58.522714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16193 11:32:58.523432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16194 11:32:58.574209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16196 11:32:58.574674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16197 11:32:58.615975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16198 11:32:58.616404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16200 11:32:58.676724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16202 11:32:58.677387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16203 11:32:58.735980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16205 11:32:58.736611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16206 11:32:58.793620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16207 11:32:58.794119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16209 11:32:58.848859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16211 11:32:58.849339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16212 11:32:58.900835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16213 11:32:58.901214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16215 11:32:58.948296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16217 11:32:58.948767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16218 11:32:58.997807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16219 11:32:58.998297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16221 11:32:59.039181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16222 11:32:59.039609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16224 11:32:59.092847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16225 11:32:59.093358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16227 11:32:59.146678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16229 11:32:59.147148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16230 11:32:59.187990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16231 11:32:59.188439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16233 11:32:59.230675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16235 11:32:59.231143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16236 11:32:59.292358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16237 11:32:59.292748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16239 11:32:59.352627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16240 11:32:59.353074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16242 11:32:59.412597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16244 11:32:59.413053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16245 11:32:59.472278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16246 11:32:59.472706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16248 11:32:59.515973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16250 11:32:59.516452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16251 11:32:59.562347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16253 11:32:59.562814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16254 11:32:59.599489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16255 11:32:59.599986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16257 11:32:59.637574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16259 11:32:59.638058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16260 11:32:59.675773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16261 11:32:59.676207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16263 11:32:59.709892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16264 11:32:59.710345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16266 11:32:59.749597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16268 11:32:59.749991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16269 11:32:59.791743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16270 11:32:59.792117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16272 11:32:59.828866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16274 11:32:59.829316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16275 11:32:59.867294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16276 11:32:59.867705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16278 11:32:59.909787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16279 11:32:59.910188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16281 11:32:59.948343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16283 11:32:59.948701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16284 11:32:59.987703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16285 11:32:59.988104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16287 11:33:00.026116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16289 11:33:00.026674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16290 11:33:00.065275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16292 11:33:00.066019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16293 11:33:00.103871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16294 11:33:00.104339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16296 11:33:00.147902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16298 11:33:00.148378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16299 11:33:00.193200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16300 11:33:00.193707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16302 11:33:00.240255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16303 11:33:00.240700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16305 11:33:00.297579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16306 11:33:00.298004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16308 11:33:00.349910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16310 11:33:00.350618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16311 11:33:00.399076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16312 11:33:00.399542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16314 11:33:00.441863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16315 11:33:00.442368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16317 11:33:00.490227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16319 11:33:00.490626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16320 11:33:00.551644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16321 11:33:00.552068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16323 11:33:00.599577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16324 11:33:00.600007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16326 11:33:00.647406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16327 11:33:00.647979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16329 11:33:00.698014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16330 11:33:00.698443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16332 11:33:00.743665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16333 11:33:00.744121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16335 11:33:00.787846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16337 11:33:00.788319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16338 11:33:00.840757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16340 11:33:00.841176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16341 11:33:00.893501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16342 11:33:00.893963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16344 11:33:00.946138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16346 11:33:00.946814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16347 11:33:00.995299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16349 11:33:00.995784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16350 11:33:01.036954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16352 11:33:01.037329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16353 11:33:01.076102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16354 11:33:01.076483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16356 11:33:01.114359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16357 11:33:01.114831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16359 11:33:01.160583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16360 11:33:01.161077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16362 11:33:01.197836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16364 11:33:01.198235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16365 11:33:01.239736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16366 11:33:01.240159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16368 11:33:01.286159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16369 11:33:01.286640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16371 11:33:01.331636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16372 11:33:01.332029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16374 11:33:01.370476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16376 11:33:01.371162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16377 11:33:01.411151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16378 11:33:01.411709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16380 11:33:01.453715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16382 11:33:01.454163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16383 11:33:01.496163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16384 11:33:01.496581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16386 11:33:01.535770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16387 11:33:01.536201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16389 11:33:01.574300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16391 11:33:01.574774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16392 11:33:01.613230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16394 11:33:01.613724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16395 11:33:01.651966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16396 11:33:01.652415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16398 11:33:01.689834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16399 11:33:01.690271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16401 11:33:01.728005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16402 11:33:01.728423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16404 11:33:01.765834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16405 11:33:01.766294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16407 11:33:01.805144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16409 11:33:01.805569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16410 11:33:01.843416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16411 11:33:01.843857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16413 11:33:01.891657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16414 11:33:01.892060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16416 11:33:01.927043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16417 11:33:01.927508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16419 11:33:01.963185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16421 11:33:01.963998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16422 11:33:01.999467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16424 11:33:01.999888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16425 11:33:02.035428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16426 11:33:02.035877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16428 11:33:02.083730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16429 11:33:02.084166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16431 11:33:02.120094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16432 11:33:02.120477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16434 11:33:02.170565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16436 11:33:02.171186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16437 11:33:02.209789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16438 11:33:02.210222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16440 11:33:02.254173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16441 11:33:02.254584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16443 11:33:02.301288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16444 11:33:02.301689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16446 11:33:02.347626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16448 11:33:02.348049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16449 11:33:02.382974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16451 11:33:02.383430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16452 11:33:02.435906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16453 11:33:02.436332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16455 11:33:02.492025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16456 11:33:02.492516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16458 11:33:02.541370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16459 11:33:02.541752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16461 11:33:02.577483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16462 11:33:02.577999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16464 11:33:02.613307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16465 11:33:02.613776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16467 11:33:02.649821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16468 11:33:02.650339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16470 11:33:02.687572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16472 11:33:02.687969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16473 11:33:02.725126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16474 11:33:02.725481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16476 11:33:02.769198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16477 11:33:02.769627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16479 11:33:02.810029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16480 11:33:02.810481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16482 11:33:02.849057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16484 11:33:02.849525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16485 11:33:02.891818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16487 11:33:02.892574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16488 11:33:02.939309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16490 11:33:02.940071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16491 11:33:02.977140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16493 11:33:02.977710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16494 11:33:03.013832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16495 11:33:03.014213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16497 11:33:03.070231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16498 11:33:03.070627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16500 11:33:03.115447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16502 11:33:03.115893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16503 11:33:03.168193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16504 11:33:03.168684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16506 11:33:03.220370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16507 11:33:03.220957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16509 11:33:03.268895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16511 11:33:03.269301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16512 11:33:03.312179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16513 11:33:03.312530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16515 11:33:03.365269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16516 11:33:03.365676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16518 11:33:03.416598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16519 11:33:03.417054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16521 11:33:03.459783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16522 11:33:03.460244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16524 11:33:03.506705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16526 11:33:03.507436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16527 11:33:03.547669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16528 11:33:03.548052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16530 11:33:03.594359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16532 11:33:03.595114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16533 11:33:03.637451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16535 11:33:03.637900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16536 11:33:03.683540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16538 11:33:03.684025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16539 11:33:03.731852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16540 11:33:03.732346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16542 11:33:03.773852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16544 11:33:03.774444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16545 11:33:03.820642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16547 11:33:03.821111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16548 11:33:03.873470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16549 11:33:03.874030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16551 11:33:03.931245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16553 11:33:03.931722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16554 11:33:03.988758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16556 11:33:03.989217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16557 11:33:04.044678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16558 11:33:04.045156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16560 11:33:04.102771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16562 11:33:04.103530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16563 11:33:04.149575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16564 11:33:04.150026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16566 11:33:04.202170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16567 11:33:04.202616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16569 11:33:04.249072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16570 11:33:04.249528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16572 11:33:04.289762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16574 11:33:04.290248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16575 11:33:04.338638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16577 11:33:04.339085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16578 11:33:04.389016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16579 11:33:04.389423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16581 11:33:04.440444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16583 11:33:04.441070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16584 11:33:04.483333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16585 11:33:04.483761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16587 11:33:04.530034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16589 11:33:04.530474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16590 11:33:04.574063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16591 11:33:04.574535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16593 11:33:04.616873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16595 11:33:04.617600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16596 11:33:04.658663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16598 11:33:04.659224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16599 11:33:04.702694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16601 11:33:04.703115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16602 11:33:04.739985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16603 11:33:04.740388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16605 11:33:04.783506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16606 11:33:04.783923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16608 11:33:04.825094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16609 11:33:04.825528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16611 11:33:04.924360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16612 11:33:04.924830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16614 11:33:04.993150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16615 11:33:04.993571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16617 11:33:05.028864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16618 11:33:05.029305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16620 11:33:05.068736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16621 11:33:05.069138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16623 11:33:05.105335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16624 11:33:05.105897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16626 11:33:05.145722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16627 11:33:05.146272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16629 11:33:05.187389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16630 11:33:05.187777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16632 11:33:05.229359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16634 11:33:05.229832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16635 11:33:05.273204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16636 11:33:05.273663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16638 11:33:05.321260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16639 11:33:05.321820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16641 11:33:05.356683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16643 11:33:05.357062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16644 11:33:05.400092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16645 11:33:05.400514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16647 11:33:05.446348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16649 11:33:05.447016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16650 11:33:05.486323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16652 11:33:05.487085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16653 11:33:05.532875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16654 11:33:05.533297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16656 11:33:05.572492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16657 11:33:05.572926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16659 11:33:05.615232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16660 11:33:05.615633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16662 11:33:05.657462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16664 11:33:05.657889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16665 11:33:05.708076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16666 11:33:05.708509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16668 11:33:05.756133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16669 11:33:05.756579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16671 11:33:05.808294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16672 11:33:05.808728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16674 11:33:05.855630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16676 11:33:05.856055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16677 11:33:05.907953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16678 11:33:05.908394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16680 11:33:05.945493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16681 11:33:05.945948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16683 11:33:05.992156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16684 11:33:05.992617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16686 11:33:06.030153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16687 11:33:06.030603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16689 11:33:06.077842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16690 11:33:06.078289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16692 11:33:06.124551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16694 11:33:06.125035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16695 11:33:06.166305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16696 11:33:06.166754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16698 11:33:06.204620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16699 11:33:06.205067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16701 11:33:06.252540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16703 11:33:06.253019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16704 11:33:06.300259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16705 11:33:06.300697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16707 11:33:06.342236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16709 11:33:06.342709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16710 11:33:06.379520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16711 11:33:06.379934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16713 11:33:06.416103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16714 11:33:06.416485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16716 11:33:06.452729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16717 11:33:06.453299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16719 11:33:06.496096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16721 11:33:06.496870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16722 11:33:06.537675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16724 11:33:06.538052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16725 11:33:06.587784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16727 11:33:06.588515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16728 11:33:06.634488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16730 11:33:06.635254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16731 11:33:06.683579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16732 11:33:06.683981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16734 11:33:06.733041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16735 11:33:06.733599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16737 11:33:06.783687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16738 11:33:06.784193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16740 11:33:06.832933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16741 11:33:06.833424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16743 11:33:06.883586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16744 11:33:06.884076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16746 11:33:06.929699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16748 11:33:06.930457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16749 11:33:06.977922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16750 11:33:06.978332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16752 11:33:07.032117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
16754 11:33:07.032537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16755 11:33:07.070606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
16757 11:33:07.071080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
16758 11:33:07.109496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
16760 11:33:07.109968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
16761 11:33:07.155880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
16762 11:33:07.156305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
16764 11:33:07.201322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
16766 11:33:07.201796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
16767 11:33:07.245740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
16769 11:33:07.246349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
16770 11:33:07.288283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
16771 11:33:07.288731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
16773 11:33:07.334715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
16775 11:33:07.335430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
16776 11:33:07.380370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
16778 11:33:07.380842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
16779 11:33:07.425422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
16780 11:33:07.425848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
16782 11:33:07.471481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
16783 11:33:07.471926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
16785 11:33:07.513505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
16786 11:33:07.513943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
16788 11:33:07.553630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
16789 11:33:07.554057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
16791 11:33:07.595259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
16792 11:33:07.595669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
16794 11:33:07.636450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
16795 11:33:07.636987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
16797 11:33:07.679505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
16798 11:33:07.680043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
16800 11:33:07.723873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
16801 11:33:07.724271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
16803 11:33:07.768349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
16804 11:33:07.768738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
16806 11:33:07.813357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
16807 11:33:07.813781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
16809 11:33:07.860289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
16811 11:33:07.860757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
16812 11:33:07.901855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
16813 11:33:07.902280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
16815 11:33:07.950549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
16817 11:33:07.951037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
16818 11:33:07.988695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
16820 11:33:07.989188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
16821 11:33:08.028159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
16823 11:33:08.028629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
16824 11:33:08.077027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
16825 11:33:08.077421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
16827 11:33:08.124586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
16828 11:33:08.124987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
16830 11:33:08.178383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
16832 11:33:08.178777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
16833 11:33:08.228909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
16834 11:33:08.229445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
16836 11:33:08.276003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
16837 11:33:08.276486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
16839 11:33:08.323554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
16840 11:33:08.324028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
16842 11:33:08.359116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
16843 11:33:08.359531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
16845 11:33:08.395181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
16846 11:33:08.395755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
16848 11:33:08.431530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
16850 11:33:08.432304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
16851 11:33:08.476214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
16852 11:33:08.476618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
16854 11:33:08.520069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
16856 11:33:08.520505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
16857 11:33:08.564923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
16858 11:33:08.565359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
16860 11:33:08.604419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
16861 11:33:08.604798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
16863 11:33:08.645826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
16864 11:33:08.646314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
16866 11:33:08.688299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
16867 11:33:08.688700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
16869 11:33:08.725927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
16870 11:33:08.726311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
16872 11:33:08.764731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
16873 11:33:08.765214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
16875 11:33:08.804079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
16877 11:33:08.804562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
16878 11:33:08.848628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
16879 11:33:08.849070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
16881 11:33:08.895311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
16882 11:33:08.895719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
16884 11:33:08.932468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
16885 11:33:08.932891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
16887 11:33:08.967238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
16889 11:33:08.967708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
16890 11:33:09.010739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
16892 11:33:09.011212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
16893 11:33:09.054022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
16894 11:33:09.054519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
16896 11:33:09.103689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
16897 11:33:09.104113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
16899 11:33:09.154493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
16901 11:33:09.154958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
16902 11:33:09.195012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
16904 11:33:09.195499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
16905 11:33:09.241217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
16907 11:33:09.241990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
16908 11:33:09.293544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
16909 11:33:09.294054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
16911 11:33:09.345179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
16912 11:33:09.345602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
16914 11:33:09.391430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
16915 11:33:09.391902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
16917 11:33:09.432623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
16918 11:33:09.433020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
16920 11:33:09.475730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
16921 11:33:09.476244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
16923 11:33:09.517770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
16925 11:33:09.518422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
16926 11:33:09.560684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
16928 11:33:09.561157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
16929 11:33:09.599420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
16930 11:33:09.599791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
16932 11:33:09.637568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
16934 11:33:09.638042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
16935 11:33:09.685352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
16936 11:33:09.685771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
16938 11:33:09.736501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
16939 11:33:09.736916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
16941 11:33:09.781497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
16942 11:33:09.781938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
16944 11:33:09.828731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
16945 11:33:09.829148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
16947 11:33:09.874747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
16949 11:33:09.875210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
16950 11:33:09.915388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
16951 11:33:09.915920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
16953 11:33:09.951981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
16955 11:33:09.952599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
16956 11:33:09.995625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
16958 11:33:09.996253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
16959 11:33:10.037401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
16961 11:33:10.038030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
16962 11:33:10.078039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
16964 11:33:10.078758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
16965 11:33:10.116764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
16966 11:33:10.117260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
16968 11:33:10.161384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
16969 11:33:10.161903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
16971 11:33:10.201046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
16972 11:33:10.201534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
16974 11:33:10.246001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
16976 11:33:10.246475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
16977 11:33:10.283692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
16978 11:33:10.284130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
16980 11:33:10.325064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
16982 11:33:10.325515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
16983 11:33:10.379775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
16984 11:33:10.380328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
16986 11:33:10.423052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
16987 11:33:10.423596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
16989 11:33:10.461969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
16990 11:33:10.462441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
16992 11:33:10.501910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
16993 11:33:10.502460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
16995 11:33:10.540249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
16996 11:33:10.540733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
16998 11:33:10.576352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
16999 11:33:10.576853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17001 11:33:10.614179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17002 11:33:10.614701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17004 11:33:10.656814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17005 11:33:10.657312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17007 11:33:10.704545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17008 11:33:10.704966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17010 11:33:10.745472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17012 11:33:10.746206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17013 11:33:10.793635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17014 11:33:10.794010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17016 11:33:10.844289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17017 11:33:10.844700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17019 11:33:10.887772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17021 11:33:10.888266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17022 11:33:10.929325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17023 11:33:10.929749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17025 11:33:10.967679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17027 11:33:10.968224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17028 11:33:11.003609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17029 11:33:11.004032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17031 11:33:11.044467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17032 11:33:11.044860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17034 11:33:11.087098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17036 11:33:11.087555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17037 11:33:11.127497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17038 11:33:11.128029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17040 11:33:11.168546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17041 11:33:11.169031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17043 11:33:11.216137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17044 11:33:11.216577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17046 11:33:11.267286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17048 11:33:11.267712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17049 11:33:11.317672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17051 11:33:11.318098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17052 11:33:11.369869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17053 11:33:11.370316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17055 11:33:11.414049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17056 11:33:11.414483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17058 11:33:11.455847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17059 11:33:11.456244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17061 11:33:11.496744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17062 11:33:11.497170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17064 11:33:11.544040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17066 11:33:11.544498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17067 11:33:11.595722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17069 11:33:11.596206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17070 11:33:11.638185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17071 11:33:11.638678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17073 11:33:11.686188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17075 11:33:11.686823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17076 11:33:11.730811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17078 11:33:11.731502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17079 11:33:11.780049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17080 11:33:11.780458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17082 11:33:11.818003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17084 11:33:11.818413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17085 11:33:11.857037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17087 11:33:11.857442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17088 11:33:11.895753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17089 11:33:11.896125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17091 11:33:11.934256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17092 11:33:11.934632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17094 11:33:11.973037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17095 11:33:11.973430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17097 11:33:12.010704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17099 11:33:12.011682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17100 11:33:12.053398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17101 11:33:12.053820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17103 11:33:12.091352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17104 11:33:12.091784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17106 11:33:12.140441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17108 11:33:12.140898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17109 11:33:12.189389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17111 11:33:12.190143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17112 11:33:12.235741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17113 11:33:12.236140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17115 11:33:12.286094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17117 11:33:12.286493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17118 11:33:12.336709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17120 11:33:12.337179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17121 11:33:12.382229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17122 11:33:12.382605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17124 11:33:12.429530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17125 11:33:12.430103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17127 11:33:12.474354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17129 11:33:12.474868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17130 11:33:12.522200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17132 11:33:12.522699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17133 11:33:12.582236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17134 11:33:12.582672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17136 11:33:12.638738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17138 11:33:12.639309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17139 11:33:12.685457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17140 11:33:12.685944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17142 11:33:12.738145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17143 11:33:12.738620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17145 11:33:12.786316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17147 11:33:12.786927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17148 11:33:12.845092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17149 11:33:12.845527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17151 11:33:12.904792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17152 11:33:12.905257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17154 11:33:12.958342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17156 11:33:12.958959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17157 11:33:12.997086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17158 11:33:12.997551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17160 11:33:13.046558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17162 11:33:13.047252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17163 11:33:13.093864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17164 11:33:13.094327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17166 11:33:13.141371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17168 11:33:13.141940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17169 11:33:13.184737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17170 11:33:13.185204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17172 11:33:13.221466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17174 11:33:13.222242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17175 11:33:13.263603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17176 11:33:13.264102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17178 11:33:13.302339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17180 11:33:13.302893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17181 11:33:13.339564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17182 11:33:13.340070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17184 11:33:13.384851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17185 11:33:13.385305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17187 11:33:13.425008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17189 11:33:13.425692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17190 11:33:13.468322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17191 11:33:13.468812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17193 11:33:13.506753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17195 11:33:13.507506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17196 11:33:13.547389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17197 11:33:13.547782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17199 11:33:13.584303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17200 11:33:13.584850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17202 11:33:13.621644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17204 11:33:13.622272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17205 11:33:13.663627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17206 11:33:13.664054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17208 11:33:13.710506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17210 11:33:13.710982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17211 11:33:13.757653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17212 11:33:13.758068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17214 11:33:13.804511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17215 11:33:13.804933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17217 11:33:13.844582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17218 11:33:13.844981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17220 11:33:13.883897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17221 11:33:13.884329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17223 11:33:13.923266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17224 11:33:13.923695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17226 11:33:13.965089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17228 11:33:13.965560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17229 11:33:13.999433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17230 11:33:13.999884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17232 11:33:14.042543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17234 11:33:14.043184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17235 11:33:14.087388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17236 11:33:14.087843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17238 11:33:14.137844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17239 11:33:14.138411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17241 11:33:14.188900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17242 11:33:14.189463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17244 11:33:14.230118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17245 11:33:14.230525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17247 11:33:14.273148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17248 11:33:14.273589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17250 11:33:14.320778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17252 11:33:14.321416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17253 11:33:14.368978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17254 11:33:14.369426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17256 11:33:14.413705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17258 11:33:14.414182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17259 11:33:14.463983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17260 11:33:14.464405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17262 11:33:14.512394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17263 11:33:14.512827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17265 11:33:14.561086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17266 11:33:14.561517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17268 11:33:14.603461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17269 11:33:14.603885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17271 11:33:14.645778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17272 11:33:14.646197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17274 11:33:14.687703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17275 11:33:14.688115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17277 11:33:14.724573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17278 11:33:14.724932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17280 11:33:14.774622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17282 11:33:14.775055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17283 11:33:14.820643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17285 11:33:14.821104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17286 11:33:14.862515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17288 11:33:14.862994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17289 11:33:14.907358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17290 11:33:14.907824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17292 11:33:14.950288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17294 11:33:14.950770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17295 11:33:14.985960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17296 11:33:14.986385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17298 11:33:15.025949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17300 11:33:15.026371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17301 11:33:15.064244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17303 11:33:15.064678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17304 11:33:15.099859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17305 11:33:15.100258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17307 11:33:15.136736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17308 11:33:15.137170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17310 11:33:15.173480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17312 11:33:15.173952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17313 11:33:15.218671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17315 11:33:15.219132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17316 11:33:15.255111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17317 11:33:15.255560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17319 11:33:15.291032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17321 11:33:15.291503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17322 11:33:15.327062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17323 11:33:15.327610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17325 11:33:15.367165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17326 11:33:15.367667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17328 11:33:15.409713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17329 11:33:15.410144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17331 11:33:15.448663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17332 11:33:15.449043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17334 11:33:15.491745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17335 11:33:15.492235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17337 11:33:15.529730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17338 11:33:15.530229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17340 11:33:15.566379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17342 11:33:15.566859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17343 11:33:15.605932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17344 11:33:15.606357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17346 11:33:15.651317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17347 11:33:15.651762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17349 11:33:15.694537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17351 11:33:15.694962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17352 11:33:15.740677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17354 11:33:15.741119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17355 11:33:15.796592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17357 11:33:15.797007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17358 11:33:15.849680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17359 11:33:15.850205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17361 11:33:15.905786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17363 11:33:15.906534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17364 11:33:15.957825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17365 11:33:15.958212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17367 11:33:16.007790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17369 11:33:16.008262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17370 11:33:16.056231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17371 11:33:16.056681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17373 11:33:16.094440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17374 11:33:16.094947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17376 11:33:16.136964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17377 11:33:16.137389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17379 11:33:16.176125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17381 11:33:16.176604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17382 11:33:16.213536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17384 11:33:16.214020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17385 11:33:16.250462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17386 11:33:16.250892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17388 11:33:16.290117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17389 11:33:16.290529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17391 11:33:16.327121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17392 11:33:16.327542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17394 11:33:16.363836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17395 11:33:16.364251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17397 11:33:16.411797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17398 11:33:16.412221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17400 11:33:16.456129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17401 11:33:16.456550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17403 11:33:16.497474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17405 11:33:16.498130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17406 11:33:16.546089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17407 11:33:16.546472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17409 11:33:16.588420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17410 11:33:16.588849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17412 11:33:16.623622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17413 11:33:16.624117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17415 11:33:16.665294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17417 11:33:16.666062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17418 11:33:16.703393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17420 11:33:16.704141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17421 11:33:16.743282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17423 11:33:16.743752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17424 11:33:16.783330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17425 11:33:16.783729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17427 11:33:16.824141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17429 11:33:16.824613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17430 11:33:16.869796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17431 11:33:16.870236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17433 11:33:16.907587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17435 11:33:16.907965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17436 11:33:16.949971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17438 11:33:16.950560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17439 11:33:16.988017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17440 11:33:16.988453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17442 11:33:17.028171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17443 11:33:17.028706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17445 11:33:17.067463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17446 11:33:17.067840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17448 11:33:17.108882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17449 11:33:17.109321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17451 11:33:17.151030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17452 11:33:17.151499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17454 11:33:17.189312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17455 11:33:17.189686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17457 11:33:17.239920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17458 11:33:17.240299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17460 11:33:17.292303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17461 11:33:17.292753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17463 11:33:17.347611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17464 11:33:17.348070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17466 11:33:17.383572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17468 11:33:17.384011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17469 11:33:17.428351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17470 11:33:17.428799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17472 11:33:17.472728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17474 11:33:17.473098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17475 11:33:17.518165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17476 11:33:17.518593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17478 11:33:17.556523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17479 11:33:17.557008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17481 11:33:17.596959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17482 11:33:17.597381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17484 11:33:17.637032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17485 11:33:17.637595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17487 11:33:17.682123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17488 11:33:17.682515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17490 11:33:17.719161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17492 11:33:17.719922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17493 11:33:17.762701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17495 11:33:17.763122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17496 11:33:17.798351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17498 11:33:17.799024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17499 11:33:17.836920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17501 11:33:17.837396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17502 11:33:17.876178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17504 11:33:17.876937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17505 11:33:17.914833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17507 11:33:17.915302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17508 11:33:17.952424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17509 11:33:17.952885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17511 11:33:17.989723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17512 11:33:17.990167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17514 11:33:18.039043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17515 11:33:18.039482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17517 11:33:18.079287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17518 11:33:18.079718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17520 11:33:18.118317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17521 11:33:18.118698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17523 11:33:18.159946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17524 11:33:18.160351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17526 11:33:18.202226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17528 11:33:18.202694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17529 11:33:18.243466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17531 11:33:18.243938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17532 11:33:18.284558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17534 11:33:18.285296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17535 11:33:18.327551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17536 11:33:18.328081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17538 11:33:18.381305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17539 11:33:18.381742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17541 11:33:18.424909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17542 11:33:18.425291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17544 11:33:18.471896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17545 11:33:18.472337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17547 11:33:18.517658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17548 11:33:18.518127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17550 11:33:18.564467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17551 11:33:18.564916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17553 11:33:18.611528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17554 11:33:18.611954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17556 11:33:18.665513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17558 11:33:18.666001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17559 11:33:18.720806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17560 11:33:18.721247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17562 11:33:18.768184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17564 11:33:18.768646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17565 11:33:18.814609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17567 11:33:18.815084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17568 11:33:18.858274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17569 11:33:18.858703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17571 11:33:18.904528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17572 11:33:18.905039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17574 11:33:18.947731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17575 11:33:18.948193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17577 11:33:18.998278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17579 11:33:18.998841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17580 11:33:19.048767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17582 11:33:19.049479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17583 11:33:19.091383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17584 11:33:19.091763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17586 11:33:19.135154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17587 11:33:19.135558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17589 11:33:19.186172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17590 11:33:19.186642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17592 11:33:19.223635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17593 11:33:19.224041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17595 11:33:19.265991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17596 11:33:19.266447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17598 11:33:19.320622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17600 11:33:19.321078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17601 11:33:19.357977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17603 11:33:19.358454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17604 11:33:19.397454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17605 11:33:19.397909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17607 11:33:19.440585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17608 11:33:19.441043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17610 11:33:19.484240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17611 11:33:19.484679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17613 11:33:19.527848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17615 11:33:19.528319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17616 11:33:19.573341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17617 11:33:19.573763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17619 11:33:19.617714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17621 11:33:19.618175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17622 11:33:19.663954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17624 11:33:19.664442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17625 11:33:19.709435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17626 11:33:19.709827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17628 11:33:19.750097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17629 11:33:19.750556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17631 11:33:19.800277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17633 11:33:19.800714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17634 11:33:19.848533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17635 11:33:19.848982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17637 11:33:19.905101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17638 11:33:19.905536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17640 11:33:19.963465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17641 11:33:19.963873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17643 11:33:20.011459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17644 11:33:20.011993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17646 11:33:20.053370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17647 11:33:20.053755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17649 11:33:20.098787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17651 11:33:20.099799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17652 11:33:20.141683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17653 11:33:20.142061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17655 11:33:20.187906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17656 11:33:20.188287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17658 11:33:20.235233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17660 11:33:20.235636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17661 11:33:20.279062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17662 11:33:20.279460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17664 11:33:20.323549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17666 11:33:20.323962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17667 11:33:20.372579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17669 11:33:20.373347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17670 11:33:20.421870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17671 11:33:20.422302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17673 11:33:20.469390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17674 11:33:20.469890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17676 11:33:20.520940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17678 11:33:20.521582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17679 11:33:20.571945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17680 11:33:20.572380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17682 11:33:20.610357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17684 11:33:20.610888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17685 11:33:20.648953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17686 11:33:20.649374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17688 11:33:20.687544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17689 11:33:20.687977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17691 11:33:20.726010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17692 11:33:20.726481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17694 11:33:20.768793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17695 11:33:20.769272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17697 11:33:20.804840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17699 11:33:20.805301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17700 11:33:20.844553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17702 11:33:20.845009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17703 11:33:20.887255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17705 11:33:20.887716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17706 11:33:20.924636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17708 11:33:20.925378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17709 11:33:20.962156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17711 11:33:20.962765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17712 11:33:20.999848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17713 11:33:21.000319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17715 11:33:21.038453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17717 11:33:21.039072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17718 11:33:21.078692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17720 11:33:21.079150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17721 11:33:21.117982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17722 11:33:21.118408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17724 11:33:21.160985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17725 11:33:21.161399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17727 11:33:21.201217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17728 11:33:21.201569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17730 11:33:21.237490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17731 11:33:21.237878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17733 11:33:21.273731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17735 11:33:21.274465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17736 11:33:21.313410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17737 11:33:21.313875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17739 11:33:21.352395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17740 11:33:21.352877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17742 11:33:21.390194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17744 11:33:21.390866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17745 11:33:21.430206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17746 11:33:21.430719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17748 11:33:21.471947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17749 11:33:21.472426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17751 11:33:21.510048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17752 11:33:21.510462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17754 11:33:21.548389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
17755 11:33:21.548843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
17757 11:33:21.608403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
17758 11:33:21.608831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
17760 11:33:21.656109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
17762 11:33:21.656571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
17763 11:33:21.691608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
17764 11:33:21.692040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
17766 11:33:21.729841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
17767 11:33:21.730277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
17769 11:33:21.776552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
17770 11:33:21.776985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
17772 11:33:21.829157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
17773 11:33:21.829609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
17775 11:33:21.881665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
17776 11:33:21.882115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
17778 11:33:21.934270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
17779 11:33:21.934701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
17781 11:33:21.983296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
17783 11:33:21.983768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
17784 11:33:22.025035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
17785 11:33:22.025453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
17787 11:33:22.062063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
17788 11:33:22.062543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
17790 11:33:22.105039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
17791 11:33:22.105469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
17793 11:33:22.144459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
17794 11:33:22.145002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
17796 11:33:22.179978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
17798 11:33:22.180555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
17799 11:33:22.215947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
17800 11:33:22.216366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
17802 11:33:22.257344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
17804 11:33:22.257808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
17805 11:33:22.299166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
17807 11:33:22.299653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
17808 11:33:22.348394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
17809 11:33:22.348770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
17811 11:33:22.385704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
17812 11:33:22.386146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
17814 11:33:22.433694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
17815 11:33:22.434165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
17817 11:33:22.471751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
17818 11:33:22.472144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
17820 11:33:22.508112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
17821 11:33:22.508536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
17823 11:33:22.554640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
17825 11:33:22.555106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
17826 11:33:22.591757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
17828 11:33:22.592137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
17829 11:33:22.633721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
17830 11:33:22.634146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
17832 11:33:22.681160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
17834 11:33:22.681622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
17835 11:33:22.719555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
17836 11:33:22.720100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
17838 11:33:22.763446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
17839 11:33:22.763885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
17841 11:33:22.812358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
17842 11:33:22.812756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
17844 11:33:22.854233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
17845 11:33:22.854589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
17847 11:33:22.893286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
17849 11:33:22.893769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
17850 11:33:22.948017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
17852 11:33:22.948497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
17853 11:33:22.987571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
17854 11:33:22.988001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
17856 11:33:23.037641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
17857 11:33:23.038040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
17859 11:33:23.089376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
17860 11:33:23.089840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
17862 11:33:23.142167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
17863 11:33:23.142615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
17865 11:33:23.190945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
17866 11:33:23.191351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
17868 11:33:23.230438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
17870 11:33:23.231132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
17871 11:33:23.268503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
17872 11:33:23.268988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
17874 11:33:23.307417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
17875 11:33:23.307863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
17877 11:33:23.357143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
17878 11:33:23.357672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
17880 11:33:23.402261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
17881 11:33:23.402647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
17883 11:33:23.457619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
17884 11:33:23.458069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
17886 11:33:23.515226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
17887 11:33:23.515702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
17889 11:33:23.570286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
17890 11:33:23.570825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
17892 11:33:23.626134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
17894 11:33:23.626797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
17895 11:33:23.671383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
17897 11:33:23.672100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
17898 11:33:23.709442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
17899 11:33:23.709888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
17901 11:33:23.762474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
17903 11:33:23.763087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
17904 11:33:23.800632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
17905 11:33:23.801062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
17907 11:33:23.838573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
17909 11:33:23.839205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
17910 11:33:23.877118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
17911 11:33:23.877559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
17913 11:33:23.914804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
17914 11:33:23.915263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
17916 11:33:23.955720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
17918 11:33:23.956101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
17919 11:33:23.998043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
17920 11:33:23.998429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
17922 11:33:24.043802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
17923 11:33:24.044245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
17925 11:33:24.084825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
17926 11:33:24.085252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
17928 11:33:24.130147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
17929 11:33:24.130614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
17931 11:33:24.182148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
17932 11:33:24.182590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
17934 11:33:24.225848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
17935 11:33:24.226272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
17937 11:33:24.273346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
17938 11:33:24.273784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
17940 11:33:24.325332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
17941 11:33:24.325758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
17943 11:33:24.372469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
17944 11:33:24.372926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
17946 11:33:24.415019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
17947 11:33:24.415512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
17949 11:33:24.464246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
17950 11:33:24.464694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
17952 11:33:24.508348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
17953 11:33:24.508780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
17955 11:33:24.560566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
17956 11:33:24.561035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
17958 11:33:24.612060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
17959 11:33:24.612502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
17961 11:33:24.664068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
17962 11:33:24.664488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
17964 11:33:24.706825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
17966 11:33:24.707294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
17967 11:33:24.751603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
17968 11:33:24.752013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
17970 11:33:24.803498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
17971 11:33:24.803920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
17973 11:33:24.840812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
17974 11:33:24.841264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
17976 11:33:24.879564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
17977 11:33:24.879969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
17979 11:33:24.917377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
17981 11:33:24.917950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
17982 11:33:24.957963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
17984 11:33:24.958379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
17985 11:33:24.996211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
17987 11:33:24.996915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
17988 11:33:25.048451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
17989 11:33:25.048988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
17991 11:33:25.087089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
17993 11:33:25.087797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
17994 11:33:25.135402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
17995 11:33:25.135830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
17997 11:33:25.175187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
17999 11:33:25.175677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18000 11:33:25.229210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18002 11:33:25.229732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18003 11:33:25.276445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18004 11:33:25.276850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18006 11:33:25.328523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18008 11:33:25.328897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18009 11:33:25.372143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18010 11:33:25.372628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18012 11:33:25.429059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18013 11:33:25.429728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18015 11:33:25.477945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18017 11:33:25.478707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18018 11:33:25.527251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18019 11:33:25.527798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18021 11:33:25.572957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18023 11:33:25.573694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18024 11:33:25.628500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18025 11:33:25.628856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18027 11:33:25.677213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18029 11:33:25.677663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18030 11:33:25.720872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18031 11:33:25.721334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18033 11:33:25.757976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18034 11:33:25.758481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18036 11:33:25.797823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18037 11:33:25.798267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18039 11:33:25.840053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18040 11:33:25.840473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18042 11:33:25.881501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18043 11:33:25.881964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18045 11:33:25.930195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18046 11:33:25.930632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18048 11:33:25.973175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18050 11:33:25.973660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18051 11:33:26.019746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18052 11:33:26.020192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18054 11:33:26.062108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18056 11:33:26.062593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18057 11:33:26.113014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18058 11:33:26.113570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18060 11:33:26.154526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18062 11:33:26.155144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18063 11:33:26.195907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18064 11:33:26.196325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18066 11:33:26.241003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18067 11:33:26.241460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18069 11:33:26.283770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18070 11:33:26.284213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18072 11:33:26.324709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18074 11:33:26.325187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18075 11:33:26.362627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18077 11:33:26.363099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18078 11:33:26.403482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18079 11:33:26.403877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18081 11:33:26.444868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18083 11:33:26.445342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18084 11:33:26.491624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18085 11:33:26.492120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18087 11:33:26.532387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18088 11:33:26.532816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18090 11:33:26.573364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18091 11:33:26.573944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18093 11:33:26.611497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18095 11:33:26.611975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18096 11:33:26.655471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18097 11:33:26.655860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18099 11:33:26.689968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18100 11:33:26.690407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18102 11:33:26.731507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18103 11:33:26.731919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18105 11:33:26.779568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18106 11:33:26.779996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18108 11:33:26.833696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18110 11:33:26.834077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18111 11:33:26.891557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18112 11:33:26.892081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18114 11:33:26.947807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18115 11:33:26.948216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18117 11:33:26.984257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18118 11:33:26.984706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18120 11:33:27.025582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18121 11:33:27.026035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18123 11:33:27.061203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18125 11:33:27.061620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18126 11:33:27.101839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18127 11:33:27.102279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18129 11:33:27.135976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18130 11:33:27.136411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18132 11:33:27.172416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18134 11:33:27.172878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18135 11:33:27.208451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18136 11:33:27.208842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18138 11:33:27.245158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18140 11:33:27.245619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18141 11:33:27.286339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18142 11:33:27.286773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18144 11:33:27.330653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18146 11:33:27.331116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18147 11:33:27.373111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18149 11:33:27.373532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18150 11:33:27.411746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18151 11:33:27.412163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18153 11:33:27.449038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18155 11:33:27.449490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18156 11:33:27.487629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18157 11:33:27.488014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18159 11:33:27.524172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18161 11:33:27.524821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18162 11:33:27.564425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18163 11:33:27.564838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18165 11:33:27.601197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18167 11:33:27.601678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18168 11:33:27.637324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18169 11:33:27.637739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18171 11:33:27.675270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18173 11:33:27.675758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18174 11:33:27.716436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18176 11:33:27.717094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18177 11:33:27.766434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18178 11:33:27.766909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18180 11:33:27.809397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18181 11:33:27.809957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18183 11:33:27.855412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18184 11:33:27.855865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18186 11:33:27.899586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18188 11:33:27.900006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18189 11:33:27.948998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18190 11:33:27.949563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18192 11:33:27.992795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18193 11:33:27.993251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18195 11:33:28.036360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18196 11:33:28.036741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18198 11:33:28.079130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18199 11:33:28.079649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18201 11:33:28.124288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18203 11:33:28.124709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18204 11:33:28.173429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18205 11:33:28.173869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18207 11:33:28.229145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18208 11:33:28.229671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18210 11:33:28.272729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18211 11:33:28.273182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18213 11:33:28.314432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18215 11:33:28.314915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18216 11:33:28.358269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18218 11:33:28.358750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18219 11:33:28.403978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18220 11:33:28.404362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18222 11:33:28.443183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18223 11:33:28.443613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18225 11:33:28.487274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18227 11:33:28.487746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18228 11:33:28.529091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18229 11:33:28.529580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18231 11:33:28.575942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18232 11:33:28.576370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18234 11:33:28.624327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18235 11:33:28.624743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18237 11:33:28.666047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18238 11:33:28.666482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18240 11:33:28.708938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18241 11:33:28.709378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18243 11:33:28.756921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18244 11:33:28.757378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18246 11:33:28.802505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18248 11:33:28.803269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18249 11:33:28.844392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18250 11:33:28.844813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18252 11:33:28.884671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18254 11:33:28.885150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18255 11:33:28.924934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18256 11:33:28.925382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18258 11:33:28.968264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18259 11:33:28.968713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18261 11:33:29.017377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18262 11:33:29.017949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18264 11:33:29.065361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18266 11:33:29.065762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18267 11:33:29.106650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18269 11:33:29.107086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18270 11:33:29.150139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18272 11:33:29.150631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18273 11:33:29.189815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18274 11:33:29.190309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18276 11:33:29.229033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18277 11:33:29.229445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18279 11:33:29.268948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18280 11:33:29.269385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18282 11:33:29.305112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18284 11:33:29.305550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18285 11:33:29.344632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18286 11:33:29.344984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18288 11:33:29.386491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18290 11:33:29.387156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18291 11:33:29.425301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18292 11:33:29.425837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18294 11:33:29.463880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18296 11:33:29.464560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18297 11:33:29.503377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18298 11:33:29.503816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18300 11:33:29.540361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18301 11:33:29.540753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18303 11:33:29.580229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18304 11:33:29.580671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18306 11:33:29.617056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18307 11:33:29.617484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18309 11:33:29.655661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18310 11:33:29.656094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18312 11:33:29.706197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18313 11:33:29.706631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18315 11:33:29.761701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18316 11:33:29.762105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18318 11:33:29.816161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18319 11:33:29.816680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18321 11:33:29.872800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18322 11:33:29.873228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18324 11:33:29.909607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18325 11:33:29.910041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18327 11:33:29.951735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18329 11:33:29.952240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18330 11:33:29.991930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18331 11:33:29.992426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18333 11:33:30.035462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18334 11:33:30.035931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18336 11:33:30.093437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18337 11:33:30.093877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18339 11:33:30.137467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18341 11:33:30.138239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18342 11:33:30.181156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18343 11:33:30.181553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18345 11:33:30.221543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18346 11:33:30.221941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18348 11:33:30.267785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18349 11:33:30.268280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18351 11:33:30.305402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18352 11:33:30.305855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18354 11:33:30.345174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18355 11:33:30.345694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18357 11:33:30.386090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18358 11:33:30.386547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18360 11:33:30.434621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18362 11:33:30.435091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18363 11:33:30.475755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18364 11:33:30.476180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18366 11:33:30.517121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18367 11:33:30.517578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18369 11:33:30.558423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18371 11:33:30.558900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18372 11:33:30.596098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18374 11:33:30.596570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18375 11:33:30.633356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18376 11:33:30.633857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18378 11:33:30.672431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18379 11:33:30.672840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18381 11:33:30.711433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18382 11:33:30.711886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18384 11:33:30.768785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18385 11:33:30.769215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18387 11:33:30.820519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18388 11:33:30.821091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18390 11:33:30.867816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18391 11:33:30.868258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18393 11:33:30.914603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18395 11:33:30.915065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18396 11:33:30.960325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18397 11:33:30.960813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18399 11:33:30.999618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18400 11:33:31.000019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18402 11:33:31.038072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18404 11:33:31.038551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18405 11:33:31.075876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18406 11:33:31.076365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18408 11:33:31.113758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18409 11:33:31.114305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18411 11:33:31.156813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18413 11:33:31.157277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18414 11:33:31.197383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18416 11:33:31.197861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18417 11:33:31.238493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18419 11:33:31.238969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18420 11:33:31.281262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18421 11:33:31.281681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18423 11:33:31.321287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18425 11:33:31.321738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18426 11:33:31.367246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18428 11:33:31.367671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18429 11:33:31.421122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18430 11:33:31.421571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18432 11:33:31.470385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18434 11:33:31.470857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18435 11:33:31.517152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18436 11:33:31.517577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18438 11:33:31.564333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18440 11:33:31.564809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18441 11:33:31.605784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18442 11:33:31.606218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18444 11:33:31.652423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18446 11:33:31.652892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18447 11:33:31.702762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18449 11:33:31.703236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18450 11:33:31.748374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18452 11:33:31.748760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18453 11:33:31.803060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18454 11:33:31.803514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18456 11:33:31.844845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18458 11:33:31.845265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18459 11:33:31.888348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18460 11:33:31.888841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18462 11:33:31.928479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18463 11:33:31.929032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18465 11:33:31.967661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18466 11:33:31.968107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18468 11:33:32.021619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18469 11:33:32.022036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18471 11:33:32.077424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18473 11:33:32.078026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18474 11:33:32.132580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18476 11:33:32.133051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18477 11:33:32.181745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18478 11:33:32.182272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18480 11:33:32.232530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18481 11:33:32.232917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18483 11:33:32.282441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18484 11:33:32.282994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18486 11:33:32.333005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18487 11:33:32.333472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18489 11:33:32.385039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18490 11:33:32.385454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18492 11:33:32.429586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18493 11:33:32.430039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18495 11:33:32.484244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18497 11:33:32.484703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18498 11:33:32.531676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18499 11:33:32.532079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18501 11:33:32.579265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18502 11:33:32.579688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18504 11:33:32.621003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18506 11:33:32.621534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18507 11:33:32.662233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18509 11:33:32.662976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18510 11:33:32.701549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18512 11:33:32.702040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18513 11:33:32.740810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18514 11:33:32.741205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18516 11:33:32.785057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18517 11:33:32.785480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18519 11:33:32.824773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18520 11:33:32.825202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18522 11:33:32.866680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18524 11:33:32.867258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18525 11:33:32.923549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18527 11:33:32.923973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18528 11:33:32.979520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18529 11:33:32.979972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18531 11:33:33.033356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18532 11:33:33.033927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18534 11:33:33.072647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18536 11:33:33.073030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18537 11:33:33.112781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18538 11:33:33.113103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18540 11:33:33.156035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18541 11:33:33.156437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18543 11:33:33.198300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18545 11:33:33.198710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18546 11:33:33.245022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18547 11:33:33.245413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18549 11:33:33.294459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18550 11:33:33.295026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18552 11:33:33.346174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18554 11:33:33.346635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18555 11:33:33.400767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18556 11:33:33.401201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18558 11:33:33.447591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18560 11:33:33.447992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18561 11:33:33.490080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18562 11:33:33.490488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18564 11:33:33.537606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18565 11:33:33.538054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18567 11:33:33.591904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18568 11:33:33.592325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18570 11:33:33.644151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18571 11:33:33.644566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18573 11:33:33.684216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18575 11:33:33.684684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18576 11:33:33.724240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18577 11:33:33.724650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18579 11:33:33.767349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18580 11:33:33.767772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18582 11:33:33.814707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18584 11:33:33.815138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18585 11:33:33.861417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18586 11:33:33.861817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18588 11:33:33.907249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18589 11:33:33.907670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18591 11:33:33.950039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18592 11:33:33.950478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18594 11:33:34.002255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18596 11:33:34.002741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18597 11:33:34.041196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18598 11:33:34.041624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18600 11:33:34.088530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18601 11:33:34.088955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18603 11:33:34.139228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18604 11:33:34.139598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18606 11:33:34.178287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18607 11:33:34.178704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18609 11:33:34.229488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18610 11:33:34.229927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18612 11:33:34.279306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18613 11:33:34.279736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18615 11:33:34.323901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18616 11:33:34.324347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18618 11:33:34.373060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18619 11:33:34.373491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18621 11:33:34.418990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18622 11:33:34.419545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18624 11:33:34.467552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18625 11:33:34.467961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18627 11:33:34.516234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18629 11:33:34.516731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18630 11:33:34.562360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18632 11:33:34.563039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18633 11:33:34.604657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18634 11:33:34.605100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18636 11:33:34.654004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18637 11:33:34.654487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18639 11:33:34.710857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18641 11:33:34.711622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18642 11:33:34.766022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18643 11:33:34.766573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18645 11:33:34.807122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18646 11:33:34.807571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18648 11:33:34.847600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18649 11:33:34.848003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18651 11:33:34.898580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18653 11:33:34.899005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18654 11:33:34.956061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18655 11:33:34.956668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18657 11:33:35.009685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18658 11:33:35.010147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18660 11:33:35.054506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18661 11:33:35.054921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18663 11:33:35.099444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18664 11:33:35.099869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18666 11:33:35.143083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18668 11:33:35.143552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18669 11:33:35.189096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18671 11:33:35.189570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18672 11:33:35.238610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18674 11:33:35.239083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18675 11:33:35.285127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18676 11:33:35.285545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18678 11:33:35.329496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18679 11:33:35.329912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18681 11:33:35.378392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18683 11:33:35.378839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18684 11:33:35.421070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18685 11:33:35.421570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18687 11:33:35.476454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18689 11:33:35.476891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18690 11:33:35.523033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18691 11:33:35.523470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18693 11:33:35.565644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18694 11:33:35.566076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18696 11:33:35.610213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18698 11:33:35.610594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18699 11:33:35.657595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18700 11:33:35.658029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18702 11:33:35.708502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18704 11:33:35.708889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18705 11:33:35.754011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18706 11:33:35.754441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18708 11:33:35.807594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18710 11:33:35.807974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18711 11:33:35.853233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18712 11:33:35.853666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18714 11:33:35.895557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18715 11:33:35.895959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18717 11:33:35.936846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18718 11:33:35.937365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18720 11:33:35.979181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18721 11:33:35.979690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18723 11:33:36.017083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18724 11:33:36.017463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18726 11:33:36.059128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18727 11:33:36.059670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18729 11:33:36.097366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18730 11:33:36.097788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18732 11:33:36.148185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18734 11:33:36.148861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18735 11:33:36.189703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18736 11:33:36.190292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18738 11:33:36.245726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18740 11:33:36.246176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18741 11:33:36.300843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18742 11:33:36.301287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18744 11:33:36.347339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18745 11:33:36.347857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18747 11:33:36.391285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18748 11:33:36.391701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18750 11:33:36.444543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18751 11:33:36.444982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18753 11:33:36.481621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18754 11:33:36.482071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
18756 11:33:36.522328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
18757 11:33:36.522928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
18759 11:33:36.563692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
18760 11:33:36.564188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
18762 11:33:36.611801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
18763 11:33:36.612341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
18765 11:33:36.667756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
18767 11:33:36.668244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
18768 11:33:36.724371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
18769 11:33:36.724798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
18771 11:33:36.780439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
18773 11:33:36.780913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
18774 11:33:36.836094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
18775 11:33:36.836518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
18777 11:33:36.890266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
18778 11:33:36.890694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
18780 11:33:36.945482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
18782 11:33:36.946138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
18783 11:33:37.001805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
18784 11:33:37.002327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
18786 11:33:37.056077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
18788 11:33:37.056727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
18789 11:33:37.103482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
18791 11:33:37.104237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
18792 11:33:37.142367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
18794 11:33:37.143063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
18795 11:33:37.184678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
18796 11:33:37.185106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
18798 11:33:37.227019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
18799 11:33:37.227457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
18801 11:33:37.275410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
18803 11:33:37.276079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
18804 11:33:37.314616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
18806 11:33:37.320498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
18807 11:33:37.366175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
18808 11:33:37.366596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
18810 11:33:37.415802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
18811 11:33:37.416256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
18813 11:33:37.463516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
18814 11:33:37.463940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
18816 11:33:37.513040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
18817 11:33:37.513489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
18819 11:33:37.556168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
18820 11:33:37.556571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
18822 11:33:37.602537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
18823 11:33:37.602960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
18825 11:33:37.649905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
18826 11:33:37.650353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
18828 11:33:37.692009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
18830 11:33:37.692461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
18831 11:33:37.739259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
18832 11:33:37.739717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
18834 11:33:37.777698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
18835 11:33:37.778101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
18837 11:33:37.819244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
18838 11:33:37.819703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
18840 11:33:37.867088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
18842 11:33:37.867540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
18843 11:33:37.909528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
18844 11:33:37.910111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
18846 11:33:37.952138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
18847 11:33:37.952629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
18849 11:33:37.995547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
18850 11:33:37.995987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
18852 11:33:38.043590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
18853 11:33:38.044027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
18855 11:33:38.090684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
18857 11:33:38.091164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
18858 11:33:38.131813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
18860 11:33:38.132280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
18861 11:33:38.174142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
18863 11:33:38.174617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
18864 11:33:38.220372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
18865 11:33:38.220798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
18867 11:33:38.269258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
18868 11:33:38.269801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
18870 11:33:38.325499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
18871 11:33:38.325918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
18873 11:33:38.377609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
18874 11:33:38.378053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
18876 11:33:38.428375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
18878 11:33:38.428831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
18879 11:33:38.469307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
18880 11:33:38.469746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
18882 11:33:38.508985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
18884 11:33:38.509367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
18885 11:33:38.549567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
18887 11:33:38.550041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
18888 11:33:38.589283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
18889 11:33:38.589690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
18891 11:33:38.630170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
18892 11:33:38.630602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
18894 11:33:38.676107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
18896 11:33:38.676572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
18897 11:33:38.719585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
18899 11:33:38.719963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
18900 11:33:38.758585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
18902 11:33:38.759060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
18903 11:33:38.802154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
18905 11:33:38.802530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
18906 11:33:38.841405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
18908 11:33:38.841879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
18909 11:33:38.882402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
18911 11:33:38.882879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
18912 11:33:38.921375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
18913 11:33:38.921814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
18915 11:33:38.961129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
18916 11:33:38.961566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
18918 11:33:39.008367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
18920 11:33:39.008833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
18921 11:33:39.051563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
18923 11:33:39.052028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
18924 11:33:39.088332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
18926 11:33:39.088785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
18927 11:33:39.145198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
18929 11:33:39.145972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
18930 11:33:39.194089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
18931 11:33:39.194524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
18933 11:33:39.242747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
18935 11:33:39.243199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
18936 11:33:39.296953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
18937 11:33:39.297387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
18939 11:33:39.335995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
18940 11:33:39.336420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
18942 11:33:39.379442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
18943 11:33:39.379869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
18945 11:33:39.427264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
18947 11:33:39.427917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
18948 11:33:39.471451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
18949 11:33:39.471867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
18951 11:33:39.518001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
18953 11:33:39.518479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
18954 11:33:39.562619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
18956 11:33:39.563166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
18957 11:33:39.604991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
18958 11:33:39.605437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
18960 11:33:39.650729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
18962 11:33:39.651211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
18963 11:33:39.697581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
18964 11:33:39.698019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
18966 11:33:39.740501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
18967 11:33:39.741000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
18969 11:33:39.791784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
18971 11:33:39.792255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
18972 11:33:39.829401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
18973 11:33:39.829825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
18975 11:33:39.872218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
18976 11:33:39.872776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
18978 11:33:39.916434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
18980 11:33:39.916915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
18981 11:33:39.956617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
18982 11:33:39.957037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
18984 11:33:39.998787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
18986 11:33:39.999189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
18987 11:33:40.042417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
18989 11:33:40.043138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
18990 11:33:40.087388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
18992 11:33:40.088072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
18993 11:33:40.131588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
18994 11:33:40.132007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
18996 11:33:40.168970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
18998 11:33:40.169430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
18999 11:33:40.208201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19001 11:33:40.208959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19002 11:33:40.251864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19003 11:33:40.252318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19005 11:33:40.295870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19006 11:33:40.296315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19008 11:33:40.339571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19009 11:33:40.339977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19011 11:33:40.388705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19012 11:33:40.389122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19014 11:33:40.431094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19015 11:33:40.431527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19017 11:33:40.473657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19019 11:33:40.474067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19020 11:33:40.525367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19021 11:33:40.525766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19023 11:33:40.581440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19024 11:33:40.581834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19026 11:33:40.631906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19027 11:33:40.632353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19029 11:33:40.675451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19030 11:33:40.675886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19032 11:33:40.721099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19033 11:33:40.721531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19035 11:33:40.762493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19037 11:33:40.763239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19038 11:33:40.802463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19039 11:33:40.802896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19041 11:33:40.848411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19043 11:33:40.848878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19044 11:33:40.892181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19046 11:33:40.892771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19047 11:33:40.963557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19048 11:33:40.963945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19050 11:33:41.012951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19051 11:33:41.013359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19053 11:33:41.058697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19055 11:33:41.059091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19056 11:33:41.105833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19057 11:33:41.106255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19059 11:33:41.149954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19060 11:33:41.150419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19062 11:33:41.197969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19064 11:33:41.198441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19065 11:33:41.239739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19066 11:33:41.240166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19068 11:33:41.280090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19069 11:33:41.280545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19071 11:33:41.325889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19072 11:33:41.326324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19074 11:33:41.375927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19076 11:33:41.376402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19077 11:33:41.425133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19078 11:33:41.425553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19080 11:33:41.464930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19081 11:33:41.465376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19083 11:33:41.513070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19084 11:33:41.513503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19086 11:33:41.553629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19087 11:33:41.554061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19089 11:33:41.593675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19090 11:33:41.594103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19092 11:33:41.632744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19094 11:33:41.633124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19095 11:33:41.673820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19096 11:33:41.674276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19098 11:33:41.722167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19099 11:33:41.722573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19101 11:33:41.772281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19102 11:33:41.772695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19104 11:33:41.820507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19105 11:33:41.820918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19107 11:33:41.868273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19108 11:33:41.868706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19110 11:33:41.917825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19111 11:33:41.918208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19113 11:33:41.966606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19115 11:33:41.967071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19116 11:33:42.015082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19117 11:33:42.015641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19119 11:33:42.061092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19120 11:33:42.061522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19122 11:33:42.112467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19124 11:33:42.112937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19125 11:33:42.159290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19126 11:33:42.159742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19128 11:33:42.206709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19130 11:33:42.207176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19131 11:33:42.254133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19132 11:33:42.254520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19134 11:33:42.303219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19135 11:33:42.303650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19137 11:33:42.349949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19138 11:33:42.350340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19140 11:33:42.407273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19141 11:33:42.407697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19143 11:33:42.455159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19144 11:33:42.455582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19146 11:33:42.496199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19147 11:33:42.496645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19149 11:33:42.539454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19150 11:33:42.539894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19152 11:33:42.582275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19153 11:33:42.582701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19155 11:33:42.629986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19156 11:33:42.630416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19158 11:33:42.677901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19159 11:33:42.678331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19161 11:33:42.727463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19162 11:33:42.727889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19164 11:33:42.774800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19166 11:33:42.775222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19167 11:33:42.815728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19168 11:33:42.816156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19170 11:33:42.872062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19171 11:33:42.872631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19173 11:33:42.917091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19174 11:33:42.917531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19176 11:33:42.957160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19177 11:33:42.957602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19179 11:33:43.005039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19180 11:33:43.005481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19182 11:33:43.051732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19183 11:33:43.052188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19185 11:33:43.089716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19186 11:33:43.090178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19188 11:33:43.132346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19189 11:33:43.132748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19191 11:33:43.172660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19192 11:33:43.173083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19194 11:33:43.215733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19195 11:33:43.216188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19197 11:33:43.255469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19199 11:33:43.255936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19200 11:33:43.295511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19201 11:33:43.295932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19203 11:33:43.335845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19205 11:33:43.336303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19206 11:33:43.377573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19207 11:33:43.377997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19209 11:33:43.423990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19210 11:33:43.424497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19212 11:33:43.472449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19213 11:33:43.473013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19215 11:33:43.521385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19216 11:33:43.521949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19218 11:33:43.568256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19220 11:33:43.568726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19221 11:33:43.605236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19222 11:33:43.605658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19224 11:33:43.647648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19225 11:33:43.648123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19227 11:33:43.686260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19228 11:33:43.686693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19230 11:33:43.729682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19231 11:33:43.730069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19233 11:33:43.769226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19235 11:33:43.769898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19236 11:33:43.817512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19237 11:33:43.817953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19239 11:33:43.860981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19240 11:33:43.861427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19242 11:33:43.897202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19244 11:33:43.897667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19245 11:33:43.935607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19246 11:33:43.936026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19248 11:33:43.985015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19249 11:33:43.985443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19251 11:33:44.029091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19252 11:33:44.029512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19254 11:33:44.074145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19255 11:33:44.074566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19257 11:33:44.116751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19259 11:33:44.117203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19260 11:33:44.157750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19261 11:33:44.158285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19263 11:33:44.205292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19264 11:33:44.205694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19266 11:33:44.264201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19268 11:33:44.264640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19269 11:33:44.322108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19270 11:33:44.322550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19272 11:33:44.381680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19273 11:33:44.382119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19275 11:33:44.440980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19277 11:33:44.441453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19278 11:33:44.497000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19279 11:33:44.497442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19281 11:33:44.552864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19283 11:33:44.553595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19284 11:33:44.608757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19285 11:33:44.609141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19287 11:33:44.666006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19288 11:33:44.666444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19290 11:33:44.711709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19292 11:33:44.712182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19293 11:33:44.748067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19294 11:33:44.748625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19296 11:33:44.793201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19297 11:33:44.793630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19299 11:33:44.837714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19301 11:33:44.838181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19302 11:33:44.880649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19304 11:33:44.881108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19305 11:33:44.924361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19307 11:33:44.924787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19308 11:33:44.967514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19309 11:33:44.967938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19311 11:33:45.015855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19312 11:33:45.016253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19314 11:33:45.069676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19315 11:33:45.070180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19317 11:33:45.108917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19319 11:33:45.109334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19320 11:33:45.157420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19321 11:33:45.157839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19323 11:33:45.196025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19325 11:33:45.196675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19326 11:33:45.237140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19328 11:33:45.237607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19329 11:33:45.281328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19331 11:33:45.281932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19332 11:33:45.330294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19333 11:33:45.330788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19335 11:33:45.380925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19336 11:33:45.381315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19338 11:33:45.433047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19339 11:33:45.433426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19341 11:33:45.476048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19342 11:33:45.476473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19344 11:33:45.519957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19345 11:33:45.520375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19347 11:33:45.563737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19348 11:33:45.564156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19350 11:33:45.608501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19352 11:33:45.608969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19353 11:33:45.652235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19354 11:33:45.652652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19356 11:33:45.696914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19357 11:33:45.697344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19359 11:33:45.738338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19361 11:33:45.738856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19362 11:33:45.781712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19364 11:33:45.782181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19365 11:33:45.831739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19366 11:33:45.832221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19368 11:33:45.879658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19369 11:33:45.880101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19371 11:33:45.936700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19373 11:33:45.937376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19374 11:33:45.993686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19375 11:33:45.994272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19377 11:33:46.033407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19378 11:33:46.033842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19380 11:33:46.120699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19381 11:33:46.121126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19383 11:33:46.177552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19384 11:33:46.177986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19386 11:33:46.235656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19387 11:33:46.236149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19389 11:33:46.293378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19391 11:33:46.294043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19392 11:33:46.344141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19394 11:33:46.344898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19395 11:33:46.380934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19396 11:33:46.381382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19398 11:33:46.421297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19399 11:33:46.421682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19401 11:33:46.470275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19402 11:33:46.470734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19404 11:33:46.510228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19405 11:33:46.510649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19407 11:33:46.551435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19408 11:33:46.551995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19410 11:33:46.591910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19411 11:33:46.592415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19413 11:33:46.631802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19415 11:33:46.632177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19416 11:33:46.670764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19418 11:33:46.671230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19419 11:33:46.711702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19420 11:33:46.712245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19422 11:33:46.753558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19424 11:33:46.753988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19425 11:33:46.799580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19426 11:33:46.800002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19428 11:33:46.836892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19430 11:33:46.837358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19431 11:33:46.879618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19432 11:33:46.880173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19434 11:33:46.915365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19435 11:33:46.915851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19437 11:33:46.953889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19438 11:33:46.954337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19440 11:33:46.998613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19442 11:33:46.999106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19443 11:33:47.039275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19444 11:33:47.039726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19446 11:33:47.091777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19448 11:33:47.092265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19449 11:33:47.139272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19450 11:33:47.139704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19452 11:33:47.184624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19453 11:33:47.185021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19455 11:33:47.224311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19456 11:33:47.224758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19458 11:33:47.268956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19459 11:33:47.269360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19461 11:33:47.313440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19462 11:33:47.313863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19464 11:33:47.370313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19465 11:33:47.370738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19467 11:33:47.421209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19468 11:33:47.421635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19470 11:33:47.467643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19471 11:33:47.468102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19473 11:33:47.511320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19474 11:33:47.511756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19476 11:33:47.560083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19477 11:33:47.560473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19479 11:33:47.609737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19480 11:33:47.610186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19482 11:33:47.657896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19483 11:33:47.658327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19485 11:33:47.706265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19486 11:33:47.706691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19488 11:33:47.744438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19489 11:33:47.744815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19491 11:33:47.785976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19492 11:33:47.786413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19494 11:33:47.825713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19496 11:33:47.826184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19497 11:33:47.868779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19499 11:33:47.869253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19500 11:33:47.916202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19502 11:33:47.916639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19503 11:33:47.957734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19504 11:33:47.958162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19506 11:33:48.005690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19507 11:33:48.006089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19509 11:33:48.053958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19510 11:33:48.054399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19512 11:33:48.092067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19514 11:33:48.092551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19515 11:33:48.137087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19516 11:33:48.137518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19518 11:33:48.187644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19520 11:33:48.188113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19521 11:33:48.232427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19522 11:33:48.232872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19524 11:33:48.277997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19525 11:33:48.278445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19527 11:33:48.318888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19528 11:33:48.319340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19530 11:33:48.359410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19531 11:33:48.359799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19533 11:33:48.397434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19534 11:33:48.397830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19536 11:33:48.437887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19537 11:33:48.438308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19539 11:33:48.484332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19541 11:33:48.484799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19542 11:33:48.528047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19543 11:33:48.528483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19545 11:33:48.569721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19546 11:33:48.570148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19548 11:33:48.618747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19550 11:33:48.619215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19551 11:33:48.669501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19553 11:33:48.670027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19554 11:33:48.707848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19556 11:33:48.708320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19557 11:33:48.745689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19558 11:33:48.746091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19560 11:33:48.791768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19562 11:33:48.792241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19563 11:33:48.842046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19564 11:33:48.842488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19566 11:33:48.891673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19568 11:33:48.892158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19569 11:33:48.939797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19570 11:33:48.940244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19572 11:33:48.988114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19573 11:33:48.988503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19575 11:33:49.044739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19576 11:33:49.045197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19578 11:33:49.100747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19579 11:33:49.101206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19581 11:33:49.155775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19582 11:33:49.156208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19584 11:33:49.203341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19585 11:33:49.203765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19587 11:33:49.249404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19589 11:33:49.249867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19590 11:33:49.301521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19591 11:33:49.301960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19593 11:33:49.345088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19594 11:33:49.345546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19596 11:33:49.387480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19597 11:33:49.387929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19599 11:33:49.433154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19600 11:33:49.433579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19602 11:33:49.476135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19604 11:33:49.476519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19605 11:33:49.515096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19606 11:33:49.515547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19608 11:33:49.554552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19610 11:33:49.555014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19611 11:33:49.596230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19612 11:33:49.596638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19614 11:33:49.636574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19615 11:33:49.637007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19617 11:33:49.679059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19619 11:33:49.679773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19620 11:33:49.718267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19621 11:33:49.718682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19623 11:33:49.773979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19624 11:33:49.774516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19626 11:33:49.829871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19628 11:33:49.830349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19629 11:33:49.881140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19630 11:33:49.881571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19632 11:33:49.921706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19634 11:33:49.922519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19635 11:33:49.965358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19636 11:33:49.965952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19638 11:33:50.009301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19639 11:33:50.009746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19641 11:33:50.055277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19642 11:33:50.055722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19644 11:33:50.094036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19646 11:33:50.094427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19647 11:33:50.135740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19648 11:33:50.136122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19650 11:33:50.175370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19651 11:33:50.175932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19653 11:33:50.220268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19655 11:33:50.220644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19656 11:33:50.262025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19657 11:33:50.262438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19659 11:33:50.307405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19661 11:33:50.307884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19662 11:33:50.355636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19663 11:33:50.356058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19665 11:33:50.411695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19666 11:33:50.412230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19668 11:33:50.461510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19670 11:33:50.461993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19671 11:33:50.516339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19672 11:33:50.516886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19674 11:33:50.565331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19675 11:33:50.565763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19677 11:33:50.604611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19679 11:33:50.605085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19680 11:33:50.644481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19681 11:33:50.644892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19683 11:33:50.685641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19685 11:33:50.686082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19686 11:33:50.729821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19688 11:33:50.730548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19689 11:33:50.774153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19690 11:33:50.774656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19692 11:33:50.828668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19693 11:33:50.829137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19695 11:33:50.882117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19696 11:33:50.882612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19698 11:33:50.937099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19699 11:33:50.937549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19701 11:33:50.973624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19702 11:33:50.974081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19704 11:33:51.010018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19706 11:33:51.010486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19707 11:33:51.053522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19708 11:33:51.053917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19710 11:33:51.108420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19711 11:33:51.108859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19713 11:33:51.144590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19714 11:33:51.145009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19716 11:33:51.203105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19717 11:33:51.203629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19719 11:33:51.251244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19720 11:33:51.251674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19722 11:33:51.297134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19723 11:33:51.297560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19725 11:33:51.353406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19726 11:33:51.353861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19728 11:33:51.403400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19729 11:33:51.403847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19731 11:33:51.440122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19732 11:33:51.440619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19734 11:33:51.478627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19736 11:33:51.479056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19737 11:33:51.519945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19738 11:33:51.520436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19740 11:33:51.559249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19741 11:33:51.559751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19743 11:33:51.601722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19744 11:33:51.602231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19746 11:33:51.643412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19747 11:33:51.643867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19749 11:33:51.684672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19750 11:33:51.685101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19752 11:33:51.736005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
19754 11:33:51.736484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19755 11:33:51.783757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
19756 11:33:51.784279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
19758 11:33:51.820153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
19760 11:33:51.820616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
19761 11:33:51.857491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
19762 11:33:51.858013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
19764 11:33:51.900676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
19765 11:33:51.901118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
19767 11:33:51.937044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
19768 11:33:51.937462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
19770 11:33:51.973808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
19771 11:33:51.974231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
19773 11:33:52.012385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
19774 11:33:52.012807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
19776 11:33:52.050129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
19777 11:33:52.050591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
19779 11:33:52.093995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
19780 11:33:52.094423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
19782 11:33:52.135329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
19784 11:33:52.135731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
19785 11:33:52.176713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
19787 11:33:52.177177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
19788 11:33:52.215838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
19789 11:33:52.216263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
19791 11:33:52.253663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
19793 11:33:52.254142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
19794 11:33:52.294674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
19796 11:33:52.295134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
19797 11:33:52.331743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
19798 11:33:52.332130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
19800 11:33:52.372042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
19801 11:33:52.372605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
19803 11:33:52.412841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
19804 11:33:52.413253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
19806 11:33:52.458040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
19808 11:33:52.458515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
19809 11:33:52.511610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
19810 11:33:52.512030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
19812 11:33:52.551274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
19813 11:33:52.551694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
19815 11:33:52.593651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
19816 11:33:52.594106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
19818 11:33:52.637998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
19819 11:33:52.638423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
19821 11:33:52.685423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
19822 11:33:52.685890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
19824 11:33:52.731971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
19825 11:33:52.732403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
19827 11:33:52.772078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
19829 11:33:52.772532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
19830 11:33:52.812886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
19832 11:33:52.813347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
19833 11:33:52.851923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
19834 11:33:52.852357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
19836 11:33:52.901125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
19837 11:33:52.901560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
19839 11:33:52.952303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
19841 11:33:52.952790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
19842 11:33:52.999264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
19844 11:33:52.999726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
19845 11:33:53.041549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
19846 11:33:53.041961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
19848 11:33:53.081174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
19849 11:33:53.081601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
19851 11:33:53.124507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
19852 11:33:53.124942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
19854 11:33:53.162201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
19855 11:33:53.162656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
19857 11:33:53.198202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
19858 11:33:53.198602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
19860 11:33:53.234174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
19861 11:33:53.234630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
19863 11:33:53.274263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
19864 11:33:53.274771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
19866 11:33:53.313361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
19868 11:33:53.313836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
19869 11:33:53.349933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
19870 11:33:53.350447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
19872 11:33:53.397332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
19873 11:33:53.397753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
19875 11:33:53.436561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
19876 11:33:53.436979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
19878 11:33:53.479744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
19880 11:33:53.480212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
19881 11:33:53.524195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
19882 11:33:53.524624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
19884 11:33:53.567286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
19885 11:33:53.567716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
19887 11:33:53.609073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
19888 11:33:53.609520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
19890 11:33:53.656371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
19891 11:33:53.656796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
19893 11:33:53.704014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
19895 11:33:53.704493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
19896 11:33:53.742359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
19897 11:33:53.742784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
19899 11:33:53.784028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
19901 11:33:53.784705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
19902 11:33:53.823664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
19903 11:33:53.824095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
19905 11:33:53.861946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
19906 11:33:53.862434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
19908 11:33:53.916208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
19909 11:33:53.916757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
19911 11:33:53.970150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
19913 11:33:53.970622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
19914 11:33:54.024042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
19915 11:33:54.024485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
19917 11:33:54.059842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
19918 11:33:54.060287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
19920 11:33:54.099340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
19922 11:33:54.099804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
19923 11:33:54.132992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
19924 11:33:54.133417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
19926 11:33:54.171267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
19927 11:33:54.171729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
19929 11:33:54.219965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
19931 11:33:54.220700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
19932 11:33:54.256310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
19933 11:33:54.256697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
19935 11:33:54.292804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
19936 11:33:54.293226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
19938 11:33:54.332109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
19939 11:33:54.332539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
19941 11:33:54.372877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
19942 11:33:54.373255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
19944 11:33:54.419613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
19945 11:33:54.420164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
19947 11:33:54.461123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
19949 11:33:54.461892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
19950 11:33:54.504025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
19951 11:33:54.504451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
19953 11:33:54.540959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
19955 11:33:54.541425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
19956 11:33:54.577771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
19957 11:33:54.578156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
19959 11:33:54.616113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
19960 11:33:54.616537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
19962 11:33:54.663820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
19964 11:33:54.664569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
19965 11:33:54.703371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
19967 11:33:54.704065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
19968 11:33:54.739917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
19969 11:33:54.740315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
19971 11:33:54.779179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
19972 11:33:54.779618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
19974 11:33:54.813273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
19975 11:33:54.813667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
19977 11:33:54.847015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
19979 11:33:54.847724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
19980 11:33:54.885789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
19981 11:33:54.886205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
19983 11:33:54.929569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
19984 11:33:54.929996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
19986 11:33:54.968905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
19987 11:33:54.969283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
19989 11:33:55.023453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
19990 11:33:55.023886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
19992 11:33:55.074347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
19994 11:33:55.074953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
19995 11:33:55.122312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
19996 11:33:55.122749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
19998 11:33:55.175912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
19999 11:33:55.176336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20001 11:33:55.227996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20002 11:33:55.228413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20004 11:33:55.281690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20005 11:33:55.282127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20007 11:33:55.319646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20008 11:33:55.320096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20010 11:33:55.357205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20011 11:33:55.357668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20013 11:33:55.391738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20014 11:33:55.392138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20016 11:33:55.433851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20017 11:33:55.434433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20019 11:33:55.472287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20020 11:33:55.472799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20022 11:33:55.513839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20024 11:33:55.514338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20025 11:33:55.552156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20026 11:33:55.552594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20028 11:33:55.588956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20030 11:33:55.589735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20031 11:33:55.624889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20032 11:33:55.625428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20034 11:33:55.660379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20035 11:33:55.660826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20037 11:33:55.696667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20038 11:33:55.697087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20040 11:33:55.733502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20041 11:33:55.733953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20043 11:33:55.769276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20044 11:33:55.769689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20046 11:33:55.805149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20047 11:33:55.805596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20049 11:33:55.843578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20050 11:33:55.844025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20052 11:33:55.880780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20054 11:33:55.881201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20055 11:33:55.928428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20056 11:33:55.928811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20058 11:33:55.972081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20059 11:33:55.972535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20061 11:33:56.024917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20062 11:33:56.025372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20064 11:33:56.063404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20066 11:33:56.063875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20067 11:33:56.119746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20068 11:33:56.120172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20070 11:33:56.177353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20072 11:33:56.177780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20073 11:33:56.236972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20074 11:33:56.237443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20076 11:33:56.320087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20078 11:33:56.320624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20079 11:33:56.372089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20080 11:33:56.372524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20082 11:33:56.415974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20083 11:33:56.416425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20085 11:33:56.461642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20086 11:33:56.462074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20088 11:33:56.505369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20090 11:33:56.505859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20091 11:33:56.541203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20092 11:33:56.541656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20094 11:33:56.585514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20096 11:33:56.585939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20097 11:33:56.622311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20098 11:33:56.622738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20100 11:33:56.661340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20101 11:33:56.661771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20103 11:33:56.698487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20104 11:33:56.698910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20106 11:33:56.750332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20107 11:33:56.750857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20109 11:33:56.804560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20111 11:33:56.805031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20112 11:33:56.851780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20113 11:33:56.852208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20115 11:33:56.892492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20116 11:33:56.892916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20118 11:33:56.941359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20119 11:33:56.941786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20121 11:33:56.983671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20122 11:33:56.984072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20124 11:33:57.041325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20125 11:33:57.041679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20127 11:33:57.100147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20129 11:33:57.100604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20130 11:33:57.139416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20131 11:33:57.139847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20133 11:33:57.181872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20134 11:33:57.182317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20136 11:33:57.221701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20137 11:33:57.222124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20139 11:33:57.260198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20140 11:33:57.260652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20142 11:33:57.299555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20143 11:33:57.299977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20145 11:33:57.339436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20146 11:33:57.339884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20148 11:33:57.378655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20150 11:33:57.379298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20151 11:33:57.436780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20152 11:33:57.437220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20154 11:33:57.485378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20155 11:33:57.485800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20157 11:33:57.529920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20158 11:33:57.530364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20160 11:33:57.569342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20162 11:33:57.569927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20163 11:33:57.614316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20164 11:33:57.614738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20166 11:33:57.658122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20167 11:33:57.658557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20169 11:33:57.703862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20170 11:33:57.704348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20172 11:33:57.746884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20174 11:33:57.747360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20175 11:33:57.787552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20176 11:33:57.788001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20178 11:33:57.825642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20180 11:33:57.826428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20181 11:33:57.863587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20182 11:33:57.864135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20184 11:33:57.902670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20186 11:33:57.903140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20187 11:33:57.943796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20188 11:33:57.944216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20190 11:33:57.991362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20191 11:33:57.993782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20193 11:33:58.029778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20194 11:33:58.030179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20196 11:33:58.067709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20197 11:33:58.068139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20199 11:33:58.110325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20201 11:33:58.110809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20202 11:33:58.161242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20203 11:33:58.161684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20205 11:33:58.217798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20207 11:33:58.218236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20208 11:33:58.259543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20209 11:33:58.259991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20211 11:33:58.297924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20212 11:33:58.298369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20214 11:33:58.338404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20216 11:33:58.338886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20217 11:33:58.377742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20219 11:33:58.378427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20220 11:33:58.424847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20221 11:33:58.425280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20223 11:33:58.464710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20225 11:33:58.465164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20226 11:33:58.502633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20228 11:33:58.503096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20229 11:33:58.544359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20230 11:33:58.544743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20232 11:33:58.583797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20233 11:33:58.584223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20235 11:33:58.630048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20236 11:33:58.630453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20238 11:33:58.681474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20239 11:33:58.681929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20241 11:33:58.719104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20242 11:33:58.719513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20244 11:33:58.757581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20245 11:33:58.758015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20247 11:33:58.803756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20248 11:33:58.804184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20250 11:33:58.852701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20251 11:33:58.853133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20253 11:33:58.896920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20254 11:33:58.897344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20256 11:33:58.940595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20257 11:33:58.941016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20259 11:33:58.984378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20260 11:33:58.984805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20262 11:33:59.024608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20263 11:33:59.025050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20265 11:33:59.076424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20266 11:33:59.076828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20268 11:33:59.125326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20270 11:33:59.125782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20271 11:33:59.166364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20272 11:33:59.166943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20274 11:33:59.212075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20276 11:33:59.212494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20277 11:33:59.254234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20279 11:33:59.254688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20280 11:33:59.303007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20281 11:33:59.303438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20283 11:33:59.350601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20285 11:33:59.351029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20286 11:33:59.405426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20287 11:33:59.405848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20289 11:33:59.450213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20290 11:33:59.450638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20292 11:33:59.490855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20294 11:33:59.491552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20295 11:33:59.529268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20296 11:33:59.529684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20298 11:33:59.568267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20300 11:33:59.568877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20301 11:33:59.615699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20302 11:33:59.616109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20304 11:33:59.655583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20305 11:33:59.656022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20307 11:33:59.692541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20308 11:33:59.692981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20310 11:33:59.729451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20311 11:33:59.729889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20313 11:33:59.766891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20315 11:33:59.767347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20316 11:33:59.806695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20318 11:33:59.807154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20319 11:33:59.845061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20320 11:33:59.845499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20322 11:33:59.888645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20323 11:33:59.889071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20325 11:33:59.927501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20326 11:33:59.927935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20328 11:33:59.966205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20329 11:33:59.966633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20331 11:34:00.007801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20332 11:34:00.008222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20334 11:34:00.054430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20336 11:34:00.055208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20337 11:34:00.104340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20338 11:34:00.104833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20340 11:34:00.142789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20342 11:34:00.143217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20343 11:34:00.191477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20344 11:34:00.191915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20346 11:34:00.234550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20348 11:34:00.235148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20349 11:34:00.286105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20350 11:34:00.286612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20352 11:34:00.323564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20354 11:34:00.324039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20355 11:34:00.373574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20356 11:34:00.374007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20358 11:34:00.420132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20360 11:34:00.420601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20361 11:34:00.468815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20363 11:34:00.469288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20364 11:34:00.517488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20365 11:34:00.517876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20367 11:34:00.562386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20368 11:34:00.562806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20370 11:34:00.611986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20371 11:34:00.612416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20373 11:34:00.653930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20375 11:34:00.654359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20376 11:34:00.700299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20377 11:34:00.700730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20379 11:34:00.741292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20380 11:34:00.741680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20382 11:34:00.781270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20383 11:34:00.781685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20385 11:34:00.829058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20387 11:34:00.829524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20388 11:34:00.884331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20389 11:34:00.884734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20391 11:34:00.939160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20392 11:34:00.939587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20394 11:34:00.993724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20395 11:34:00.994110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20397 11:34:01.048471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20398 11:34:01.048978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20400 11:34:01.098258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20402 11:34:01.098748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20403 11:34:01.138002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20404 11:34:01.138426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20406 11:34:01.179812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20407 11:34:01.180237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20409 11:34:01.216105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20410 11:34:01.216491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20412 11:34:01.265699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20413 11:34:01.266145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20415 11:34:01.321788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20416 11:34:01.322229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20418 11:34:01.377264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20419 11:34:01.377696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20421 11:34:01.444206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20422 11:34:01.444630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20424 11:34:01.487709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20426 11:34:01.488346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20427 11:34:01.536769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20429 11:34:01.537241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20430 11:34:01.592510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20432 11:34:01.592937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20433 11:34:01.648554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20435 11:34:01.649030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20436 11:34:01.697853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20437 11:34:01.698279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20439 11:34:01.757170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20440 11:34:01.757557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20442 11:34:01.801772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20443 11:34:01.802201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20445 11:34:01.843682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20446 11:34:01.844114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20448 11:34:01.883911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20450 11:34:01.884408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20451 11:34:01.920481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20453 11:34:01.920959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20454 11:34:01.959490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20456 11:34:01.959972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20457 11:34:02.008728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20458 11:34:02.009292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20460 11:34:02.060618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20461 11:34:02.061086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20463 11:34:02.112438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20464 11:34:02.112806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20466 11:34:02.168734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20468 11:34:02.169189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20469 11:34:02.225250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20470 11:34:02.225686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20472 11:34:02.277139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20473 11:34:02.277564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20475 11:34:02.314231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20476 11:34:02.314688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20478 11:34:02.353081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20479 11:34:02.353487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20481 11:34:02.409473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20483 11:34:02.409986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20484 11:34:02.462173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20485 11:34:02.462608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20487 11:34:02.520434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20489 11:34:02.520940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20490 11:34:02.580351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20492 11:34:02.580834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20493 11:34:02.628765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20494 11:34:02.629196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20496 11:34:02.670195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20497 11:34:02.670653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20499 11:34:02.715281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20500 11:34:02.715715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20502 11:34:02.766724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20504 11:34:02.767169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20505 11:34:02.813487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20507 11:34:02.813967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20508 11:34:02.852956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20509 11:34:02.853384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20511 11:34:02.892311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20512 11:34:02.892752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20514 11:34:02.948774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20516 11:34:02.949199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20517 11:34:03.005773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20518 11:34:03.006212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20520 11:34:03.059961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20522 11:34:03.060437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20523 11:34:03.111983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20524 11:34:03.112423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20526 11:34:03.172391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20527 11:34:03.172843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20529 11:34:03.222541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20531 11:34:03.223011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20532 11:34:03.265356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20533 11:34:03.265779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20535 11:34:03.319207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20536 11:34:03.319631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20538 11:34:03.359482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20539 11:34:03.359901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20541 11:34:03.412043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20542 11:34:03.412464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20544 11:34:03.451566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20545 11:34:03.451993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20547 11:34:03.493787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20548 11:34:03.494219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20550 11:34:03.541888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20551 11:34:03.542329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20553 11:34:03.600856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20554 11:34:03.601293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20556 11:34:03.651941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20557 11:34:03.652332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20559 11:34:03.692625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20560 11:34:03.693121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20562 11:34:03.735790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20564 11:34:03.736556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20565 11:34:03.783975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20566 11:34:03.784402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20568 11:34:03.838138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20569 11:34:03.838577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20571 11:34:03.883647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20572 11:34:03.884072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20574 11:34:03.928839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20575 11:34:03.929261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20577 11:34:03.965391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20579 11:34:03.965859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20580 11:34:04.001485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20582 11:34:04.001963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20583 11:34:04.037660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20585 11:34:04.038095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20586 11:34:04.073681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20588 11:34:04.074159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20589 11:34:04.110266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20590 11:34:04.110695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20592 11:34:04.147712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20594 11:34:04.148177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20595 11:34:04.190840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20597 11:34:04.191303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20598 11:34:04.236497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20599 11:34:04.236936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20601 11:34:04.289084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20602 11:34:04.289690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20604 11:34:04.346698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20606 11:34:04.347177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20607 11:34:04.389980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20608 11:34:04.390525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20610 11:34:04.449684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20611 11:34:04.450088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20613 11:34:04.504066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20614 11:34:04.504485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20616 11:34:04.548083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20617 11:34:04.548500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20619 11:34:04.590002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20620 11:34:04.590442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20622 11:34:04.627517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20623 11:34:04.627939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20625 11:34:04.664230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20627 11:34:04.664717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20628 11:34:04.706067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20629 11:34:04.706504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20631 11:34:04.755862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20632 11:34:04.756256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20634 11:34:04.793386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20636 11:34:04.793844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20637 11:34:04.835744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20638 11:34:04.836127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20640 11:34:04.875916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20642 11:34:04.876369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20643 11:34:04.921708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20645 11:34:04.922152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20646 11:34:04.961621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20647 11:34:04.962077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20649 11:34:05.010671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20651 11:34:05.011138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20652 11:34:05.057797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20653 11:34:05.058237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20655 11:34:05.101677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20656 11:34:05.102102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20658 11:34:05.142010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20660 11:34:05.142481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20661 11:34:05.184842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20662 11:34:05.185214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20664 11:34:05.235624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20665 11:34:05.235990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20667 11:34:05.287593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20668 11:34:05.287947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20670 11:34:05.338453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20672 11:34:05.338929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20673 11:34:05.389303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20674 11:34:05.389680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20676 11:34:05.440453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20677 11:34:05.440890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20679 11:34:05.483806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20681 11:34:05.484394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20682 11:34:05.520839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20683 11:34:05.521237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20685 11:34:05.559951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20687 11:34:05.560601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20688 11:34:05.599485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20689 11:34:05.599908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20691 11:34:05.638620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20693 11:34:05.639077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20694 11:34:05.677905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20696 11:34:05.678376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20697 11:34:05.713707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20699 11:34:05.714166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20700 11:34:05.752430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20702 11:34:05.752886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20703 11:34:05.788791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20704 11:34:05.789194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20706 11:34:05.828516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20708 11:34:05.829105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20709 11:34:05.870170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20710 11:34:05.870621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20712 11:34:05.911568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20713 11:34:05.912014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20715 11:34:05.961363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20716 11:34:05.961766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20718 11:34:06.000464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20720 11:34:06.000899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20721 11:34:06.040202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20722 11:34:06.040643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20724 11:34:06.086629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20726 11:34:06.087135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20727 11:34:06.137484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20728 11:34:06.137923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20730 11:34:06.190347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20732 11:34:06.190822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20733 11:34:06.229037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20734 11:34:06.229436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20736 11:34:06.265006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20737 11:34:06.265431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20739 11:34:06.300859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20740 11:34:06.301281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20742 11:34:06.337027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20743 11:34:06.337452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20745 11:34:06.369113 <47>[ 226.800289] systemd-journald[105]: Sent WATCHDOG=1 notification.
20746 11:34:06.380381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20747 11:34:06.380768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20749 11:34:06.428421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20750 11:34:06.428843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20752 11:34:06.464472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20754 11:34:06.464949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20755 11:34:06.504607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
20757 11:34:06.505089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
20758 11:34:06.571593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
20759 11:34:06.572037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
20761 11:34:06.607709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
20762 11:34:06.608234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
20764 11:34:06.648191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
20765 11:34:06.648636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
20767 11:34:06.685655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
20769 11:34:06.686056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
20770 11:34:06.721582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
20772 11:34:06.722186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
20773 11:34:06.772640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
20774 11:34:06.773057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
20776 11:34:06.809203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
20778 11:34:06.809891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
20779 11:34:06.845099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
20780 11:34:06.845544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
20782 11:34:06.882137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
20783 11:34:06.882585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
20785 11:34:06.921237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
20786 11:34:06.921674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
20788 11:34:06.961047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
20790 11:34:06.961524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
20791 11:34:07.005570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
20792 11:34:07.006019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
20794 11:34:07.044692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
20795 11:34:07.045085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
20797 11:34:07.084388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
20798 11:34:07.084769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
20800 11:34:07.124768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
20801 11:34:07.125158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
20803 11:34:07.164018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
20805 11:34:07.164482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
20806 11:34:07.202033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
20807 11:34:07.202470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
20809 11:34:07.251220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
20810 11:34:07.251649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
20812 11:34:07.287492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
20813 11:34:07.287886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
20815 11:34:07.323146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
20816 11:34:07.323573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
20818 11:34:07.364923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
20820 11:34:07.365384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
20821 11:34:07.399885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
20822 11:34:07.400304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
20824 11:34:07.438177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
20825 11:34:07.439186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
20827 11:34:07.478322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
20828 11:34:07.478745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
20830 11:34:07.521550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
20832 11:34:07.522033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
20833 11:34:07.576886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
20835 11:34:07.577358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
20836 11:34:07.628602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
20837 11:34:07.629036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
20839 11:34:07.675660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
20840 11:34:07.676034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
20842 11:34:07.717626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
20843 11:34:07.718102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
20845 11:34:07.762140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
20846 11:34:07.762575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
20848 11:34:07.804534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
20849 11:34:07.804974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
20851 11:34:07.840820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
20852 11:34:07.841261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
20854 11:34:07.883044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
20855 11:34:07.883459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
20857 11:34:07.926350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
20858 11:34:07.926763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
20860 11:34:07.969769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
20861 11:34:07.970219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
20863 11:34:08.020827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
20864 11:34:08.021285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
20866 11:34:08.063924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
20867 11:34:08.064355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
20869 11:34:08.104580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
20871 11:34:08.105018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
20872 11:34:08.155794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
20873 11:34:08.156357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
20875 11:34:08.200189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
20877 11:34:08.200658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
20878 11:34:08.246161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
20879 11:34:08.246600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
20881 11:34:08.304415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
20883 11:34:08.304908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
20884 11:34:08.352601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
20886 11:34:08.353026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
20887 11:34:08.392524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
20888 11:34:08.392933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
20890 11:34:08.440673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
20892 11:34:08.441070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
20893 11:34:08.479795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
20894 11:34:08.480231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
20896 11:34:08.516947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
20897 11:34:08.517381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
20899 11:34:08.556728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
20900 11:34:08.557316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
20902 11:34:08.600147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
20904 11:34:08.600625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
20905 11:34:08.641372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
20906 11:34:08.641811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
20908 11:34:08.685938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
20909 11:34:08.686384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
20911 11:34:08.725415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
20912 11:34:08.725858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
20914 11:34:08.766944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
20915 11:34:08.767389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
20917 11:34:08.808408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
20918 11:34:08.808837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
20920 11:34:08.851890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
20921 11:34:08.852341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
20923 11:34:08.895415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
20924 11:34:08.895861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
20926 11:34:08.934859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
20927 11:34:08.935304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
20929 11:34:08.982278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
20930 11:34:08.982857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
20932 11:34:09.033513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
20934 11:34:09.034002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
20935 11:34:09.083648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
20936 11:34:09.084073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
20938 11:34:09.127377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
20939 11:34:09.127835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
20941 11:34:09.165430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
20942 11:34:09.165870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
20944 11:34:09.203577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
20945 11:34:09.203995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
20947 11:34:09.240054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
20949 11:34:09.240515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
20950 11:34:09.279452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
20951 11:34:09.279890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
20953 11:34:09.325716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
20954 11:34:09.326142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
20956 11:34:09.372380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
20957 11:34:09.372798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
20959 11:34:09.424574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
20960 11:34:09.425024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
20962 11:34:09.469041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
20963 11:34:09.469485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
20965 11:34:09.516763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
20967 11:34:09.517235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
20968 11:34:09.553961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
20969 11:34:09.554399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
20971 11:34:09.591844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
20972 11:34:09.592299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
20974 11:34:09.628618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
20975 11:34:09.629058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
20977 11:34:09.664941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
20978 11:34:09.665402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
20980 11:34:09.700346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
20981 11:34:09.700795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
20983 11:34:09.745713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
20985 11:34:09.746196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
20986 11:34:09.789033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
20988 11:34:09.789516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
20989 11:34:09.826338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
20990 11:34:09.826787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
20992 11:34:09.863954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
20993 11:34:09.864405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
20995 11:34:09.911270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
20996 11:34:09.911726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
20998 11:34:09.957910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
20999 11:34:09.958349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21001 11:34:09.998305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21002 11:34:09.998858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21004 11:34:10.039531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21006 11:34:10.039957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21007 11:34:10.077987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21008 11:34:10.078495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21010 11:34:10.132476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21011 11:34:10.132908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21013 11:34:10.182630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21015 11:34:10.183122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21016 11:34:10.237285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21018 11:34:10.237761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21019 11:34:10.291982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21020 11:34:10.292402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21022 11:34:10.337418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21023 11:34:10.337865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21025 11:34:10.375409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21026 11:34:10.375854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21028 11:34:10.412845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21029 11:34:10.413258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21031 11:34:10.449225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21032 11:34:10.449674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21034 11:34:10.493540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21035 11:34:10.493997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21037 11:34:10.540975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21038 11:34:10.541405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21040 11:34:10.577372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21041 11:34:10.577798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21043 11:34:10.616709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21044 11:34:10.617174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21046 11:34:10.661744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21047 11:34:10.662331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21049 11:34:10.710279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21051 11:34:10.710662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21052 11:34:10.755920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21053 11:34:10.756388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21055 11:34:10.805795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21056 11:34:10.806248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21058 11:34:10.853582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21059 11:34:10.854016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21061 11:34:10.899964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21062 11:34:10.900417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21064 11:34:10.951787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21066 11:34:10.952260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21067 11:34:10.991488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21068 11:34:10.991939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21070 11:34:11.044089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21071 11:34:11.044563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21073 11:34:11.097085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21074 11:34:11.097524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21076 11:34:11.133297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21078 11:34:11.133990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21079 11:34:11.170531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21081 11:34:11.171007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21082 11:34:11.215937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21084 11:34:11.216370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21085 11:34:11.254834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21087 11:34:11.255299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21088 11:34:11.295318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21090 11:34:11.295792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21091 11:34:11.334710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21093 11:34:11.335306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21094 11:34:11.378104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21095 11:34:11.378526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21097 11:34:11.424850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21099 11:34:11.425424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21100 11:34:11.473767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21101 11:34:11.474267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21103 11:34:11.524637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21105 11:34:11.525292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21106 11:34:11.577753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21107 11:34:11.578164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21109 11:34:11.627966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21110 11:34:11.628392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21112 11:34:11.691796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21113 11:34:11.692188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21115 11:34:11.733238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21116 11:34:11.733696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21118 11:34:11.772875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21119 11:34:11.773291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21121 11:34:11.813060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21122 11:34:11.813491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21124 11:34:11.857267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21125 11:34:11.857706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21127 11:34:11.897637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21128 11:34:11.898068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21130 11:34:11.940042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21131 11:34:11.940451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21133 11:34:11.984098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21134 11:34:11.984529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21136 11:34:12.022314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21137 11:34:12.022760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21139 11:34:12.066933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21140 11:34:12.067387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21142 11:34:12.103952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21143 11:34:12.104381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21145 11:34:12.140189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21146 11:34:12.140620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21148 11:34:12.176575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21149 11:34:12.176994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21151 11:34:12.219923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21152 11:34:12.220351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21154 11:34:12.265581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21155 11:34:12.266016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21157 11:34:12.305594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21159 11:34:12.306093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21160 11:34:12.343278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21161 11:34:12.343705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21163 11:34:12.379940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21164 11:34:12.380393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21166 11:34:12.416438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21167 11:34:12.416885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21169 11:34:12.452594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21171 11:34:12.453066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21172 11:34:12.491990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21174 11:34:12.492422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21175 11:34:12.535899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21176 11:34:12.536314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21178 11:34:12.585348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21179 11:34:12.585790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21181 11:34:12.632799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21183 11:34:12.633222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21184 11:34:12.676417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21185 11:34:12.676851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21187 11:34:12.715833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21188 11:34:12.716260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21190 11:34:12.766175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21191 11:34:12.766625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21193 11:34:12.803926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21195 11:34:12.804388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21196 11:34:12.843924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21197 11:34:12.844383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21199 11:34:12.885471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21200 11:34:12.885926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21202 11:34:12.930311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21203 11:34:12.930746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21205 11:34:12.972396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21206 11:34:12.972915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21208 11:34:13.008844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21209 11:34:13.009820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21211 11:34:13.047709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21212 11:34:13.048155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21214 11:34:13.086756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21216 11:34:13.087227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21217 11:34:13.132848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21218 11:34:13.133294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21220 11:34:13.187641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21221 11:34:13.188068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21223 11:34:13.243320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21225 11:34:13.243800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21226 11:34:13.290218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21227 11:34:13.290665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21229 11:34:13.328334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21230 11:34:13.328785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21232 11:34:13.375871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21233 11:34:13.376329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21235 11:34:13.421433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21236 11:34:13.421895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21238 11:34:13.461868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21239 11:34:13.462319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21241 11:34:13.506734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21243 11:34:13.507204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21244 11:34:13.551412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21245 11:34:13.551864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21247 11:34:13.601513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21248 11:34:13.601932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21250 11:34:13.656272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21251 11:34:13.656725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21253 11:34:13.692854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21254 11:34:13.693305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21256 11:34:13.737992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21257 11:34:13.738536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21259 11:34:13.792109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21261 11:34:13.792592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21262 11:34:13.834229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21263 11:34:13.834623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21265 11:34:13.879557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21266 11:34:13.879989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21268 11:34:13.921158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21269 11:34:13.921535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21271 11:34:13.963909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21273 11:34:13.964390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21274 11:34:14.006777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21276 11:34:14.007259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21277 11:34:14.049076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21278 11:34:14.049496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21280 11:34:14.086215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21281 11:34:14.086644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21283 11:34:14.132418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21284 11:34:14.132852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21286 11:34:14.175277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21288 11:34:14.175817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21289 11:34:14.215456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21291 11:34:14.215930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21292 11:34:14.257932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21294 11:34:14.258332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21295 11:34:14.297632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21297 11:34:14.298027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21298 11:34:14.341509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21299 11:34:14.341965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21301 11:34:14.389836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21303 11:34:14.390314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21304 11:34:14.430708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21306 11:34:14.431190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21307 11:34:14.469723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21309 11:34:14.470198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21310 11:34:14.515229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21311 11:34:14.515680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21313 11:34:14.555244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21314 11:34:14.555691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21316 11:34:14.596812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21317 11:34:14.597206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21319 11:34:14.641887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21320 11:34:14.642339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21322 11:34:14.680353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21323 11:34:14.680809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21325 11:34:14.720340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21326 11:34:14.720745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21328 11:34:14.766160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21330 11:34:14.766642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21331 11:34:14.804256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21332 11:34:14.804688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21334 11:34:14.846881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21336 11:34:14.847358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21337 11:34:14.884340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21339 11:34:14.884807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21340 11:34:14.920791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21342 11:34:14.921262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21343 11:34:14.961686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21344 11:34:14.962133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21346 11:34:15.000341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21347 11:34:15.000766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21349 11:34:15.047359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21350 11:34:15.047800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21352 11:34:15.085381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21353 11:34:15.085831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21355 11:34:15.136331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21356 11:34:15.136773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21358 11:34:15.190220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21359 11:34:15.190654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21361 11:34:15.245505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21362 11:34:15.245942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21364 11:34:15.296423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21365 11:34:15.296864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21367 11:34:15.345832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21368 11:34:15.346412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21370 11:34:15.402176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21372 11:34:15.402604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21373 11:34:15.445139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21374 11:34:15.445548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21376 11:34:15.488168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21377 11:34:15.488600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21379 11:34:15.526232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21381 11:34:15.526703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21382 11:34:15.568130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21383 11:34:15.568574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21385 11:34:15.615481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21386 11:34:15.615886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21388 11:34:15.661847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21389 11:34:15.662280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21391 11:34:15.709024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21393 11:34:15.709468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21394 11:34:15.750782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21396 11:34:15.751202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21397 11:34:15.791958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21399 11:34:15.792629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21400 11:34:15.846204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21401 11:34:15.846638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21403 11:34:15.883458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21404 11:34:15.883870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21406 11:34:15.928302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21408 11:34:15.928771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21409 11:34:15.980805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21410 11:34:15.981230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21412 11:34:16.023914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21414 11:34:16.024383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21415 11:34:16.068156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21416 11:34:16.068546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21418 11:34:16.107360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21419 11:34:16.107765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21421 11:34:16.156184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21422 11:34:16.156607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21424 11:34:16.210082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21425 11:34:16.210508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21427 11:34:16.265253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21428 11:34:16.265694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21430 11:34:16.316965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21431 11:34:16.317391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21433 11:34:16.364176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21435 11:34:16.364634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21436 11:34:16.424054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21437 11:34:16.424598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21439 11:34:16.468118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21441 11:34:16.468582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21442 11:34:16.515806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21443 11:34:16.516253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21445 11:34:16.563679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21446 11:34:16.564083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21448 11:34:16.607603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21449 11:34:16.608056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21451 11:34:16.661858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21452 11:34:16.662325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21454 11:34:16.707369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21455 11:34:16.707820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21457 11:34:16.748465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21459 11:34:16.748952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21460 11:34:16.806457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21461 11:34:16.806895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21463 11:34:16.850003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21464 11:34:16.850433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21466 11:34:16.892048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21467 11:34:16.892467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21469 11:34:16.936238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21471 11:34:16.936714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21472 11:34:16.978052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21473 11:34:16.978443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21475 11:34:17.016904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21477 11:34:17.017384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21478 11:34:17.053856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21479 11:34:17.054325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21481 11:34:17.095282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21482 11:34:17.095713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21484 11:34:17.134090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21486 11:34:17.134890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21487 11:34:17.176846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21488 11:34:17.177287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21490 11:34:17.215445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21491 11:34:17.215967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21493 11:34:17.252916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21494 11:34:17.253372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21496 11:34:17.290616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21498 11:34:17.291091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21499 11:34:17.336573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21500 11:34:17.337021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21502 11:34:17.385369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21504 11:34:17.385858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21505 11:34:17.428535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21507 11:34:17.429007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21508 11:34:17.467944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21509 11:34:17.468375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21511 11:34:17.522746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21513 11:34:17.523319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21514 11:34:17.574834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21516 11:34:17.575325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21517 11:34:17.620651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21518 11:34:17.621087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21520 11:34:17.659669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21521 11:34:17.660104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21523 11:34:17.708494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21524 11:34:17.708882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21526 11:34:17.752926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21527 11:34:17.753371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21529 11:34:17.789396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21531 11:34:17.789871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21532 11:34:17.828278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21533 11:34:17.828725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21535 11:34:17.867482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21536 11:34:17.867916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21538 11:34:17.905210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21540 11:34:17.905690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21541 11:34:17.943942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21543 11:34:17.944417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21544 11:34:17.979104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21545 11:34:17.979538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21547 11:34:18.016280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21548 11:34:18.016726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21550 11:34:18.052866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21551 11:34:18.053326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21553 11:34:18.101809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21554 11:34:18.102209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21556 11:34:18.145216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21558 11:34:18.145689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21559 11:34:18.202594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21561 11:34:18.203095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21562 11:34:18.256247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21564 11:34:18.256625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21565 11:34:18.300642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21566 11:34:18.301020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21568 11:34:18.340311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21569 11:34:18.340724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21571 11:34:18.381299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21572 11:34:18.381830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21574 11:34:18.428583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21575 11:34:18.429046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21577 11:34:18.479113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21578 11:34:18.479522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21580 11:34:18.521608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21581 11:34:18.522050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21583 11:34:18.565374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21584 11:34:18.565859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21586 11:34:18.608643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21587 11:34:18.609052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21589 11:34:18.657090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21591 11:34:18.657557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21592 11:34:18.700019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21593 11:34:18.700459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21595 11:34:18.744949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21596 11:34:18.745397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21598 11:34:18.787103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21599 11:34:18.787550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21601 11:34:18.829184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21603 11:34:18.829634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21604 11:34:18.880302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21606 11:34:18.880752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21607 11:34:18.937658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21608 11:34:18.938064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21610 11:34:18.995891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21611 11:34:18.996307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21613 11:34:19.045762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21614 11:34:19.046112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21616 11:34:19.092838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21617 11:34:19.093203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21619 11:34:19.142780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21621 11:34:19.143354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21622 11:34:19.201319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21623 11:34:19.201766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21625 11:34:19.257584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21626 11:34:19.258020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21628 11:34:19.293784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21629 11:34:19.294237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21631 11:34:19.344356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21632 11:34:19.344804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21634 11:34:19.383250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21636 11:34:19.383726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21637 11:34:19.424479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21638 11:34:19.424914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21640 11:34:19.464885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21641 11:34:19.465304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21643 11:34:19.510706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21645 11:34:19.511192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21646 11:34:19.556533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21647 11:34:19.556959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21649 11:34:19.597631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21651 11:34:19.598876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21652 11:34:19.645306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21653 11:34:19.645739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21655 11:34:19.697161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21656 11:34:19.697585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21658 11:34:19.743671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21659 11:34:19.744097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21661 11:34:19.791556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21663 11:34:19.792026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21664 11:34:19.841314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21665 11:34:19.841743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21667 11:34:19.895443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21668 11:34:19.895870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21670 11:34:19.940050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21671 11:34:19.940482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21673 11:34:19.984471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21674 11:34:19.984904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21676 11:34:20.021726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21677 11:34:20.022172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21679 11:34:20.061545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21681 11:34:20.062027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21682 11:34:20.101478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21683 11:34:20.101914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21685 11:34:20.150033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21686 11:34:20.150488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21688 11:34:20.201317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21690 11:34:20.201788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21691 11:34:20.252950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21692 11:34:20.253378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21694 11:34:20.304833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21696 11:34:20.305292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21697 11:34:20.344966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21698 11:34:20.345414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21700 11:34:20.392832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21701 11:34:20.393259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21703 11:34:20.433721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21704 11:34:20.434149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21706 11:34:20.473257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21708 11:34:20.473724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21709 11:34:20.510089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21710 11:34:20.510521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21712 11:34:20.552652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21713 11:34:20.553067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21715 11:34:20.602149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21717 11:34:20.602627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21718 11:34:20.652518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21720 11:34:20.652983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21721 11:34:20.701933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21723 11:34:20.702393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21724 11:34:20.747647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21726 11:34:20.748109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21727 11:34:20.792404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21729 11:34:20.792865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21730 11:34:20.829182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21732 11:34:20.829641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21733 11:34:20.868078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21734 11:34:20.868499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21736 11:34:20.907528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21737 11:34:20.907947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21739 11:34:20.947263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21740 11:34:20.947691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21742 11:34:20.987704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21743 11:34:20.988131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21745 11:34:21.026352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21747 11:34:21.026826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21748 11:34:21.066965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21749 11:34:21.067390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21751 11:34:21.116908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21752 11:34:21.117341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21754 11:34:21.154551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
21756 11:34:21.154998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
21757 11:34:21.199740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
21759 11:34:21.200217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
21760 11:34:21.240647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
21761 11:34:21.241010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
21763 11:34:21.283018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
21764 11:34:21.283466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
21766 11:34:21.324760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
21767 11:34:21.325143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
21769 11:34:21.361875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
21770 11:34:21.362289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
21772 11:34:21.403576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
21773 11:34:21.403991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
21775 11:34:21.438769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
21777 11:34:21.439238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
21778 11:34:21.474663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
21780 11:34:21.475124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
21781 11:34:21.508244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
21783 11:34:21.508771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
21784 11:34:21.552841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
21785 11:34:21.553364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
21787 11:34:21.597803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
21789 11:34:21.598226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
21790 11:34:21.637921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
21791 11:34:21.638320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
21793 11:34:21.679701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
21794 11:34:21.680085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
21796 11:34:21.718864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
21798 11:34:21.719320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
21799 11:34:21.757685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
21800 11:34:21.758070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
21802 11:34:21.796395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
21804 11:34:21.797081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
21805 11:34:21.850629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
21807 11:34:21.851066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
21808 11:34:21.915321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
21810 11:34:21.915801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
21811 11:34:21.956531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
21812 11:34:21.956967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
21814 11:34:21.995690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
21815 11:34:21.996126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
21817 11:34:22.036823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
21818 11:34:22.037255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
21820 11:34:22.080349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
21821 11:34:22.080694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
21823 11:34:22.121317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
21824 11:34:22.121679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
21826 11:34:22.160126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
21827 11:34:22.160615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
21829 11:34:22.201664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
21831 11:34:22.202419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
21832 11:34:22.240713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
21834 11:34:22.241177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
21835 11:34:22.279227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
21836 11:34:22.279649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
21838 11:34:22.320504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
21840 11:34:22.320986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
21841 11:34:22.365243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
21842 11:34:22.365669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
21844 11:34:22.406855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
21846 11:34:22.407694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
21847 11:34:22.457501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
21848 11:34:22.457941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
21850 11:34:22.513270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
21851 11:34:22.513680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
21853 11:34:22.566257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
21854 11:34:22.566699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
21856 11:34:22.623976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
21858 11:34:22.624442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
21859 11:34:22.661214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
21860 11:34:22.661634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
21862 11:34:22.711694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
21863 11:34:22.712125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
21865 11:34:22.755395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
21866 11:34:22.755815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
21868 11:34:22.805790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
21869 11:34:22.806177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
21871 11:34:22.847372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
21872 11:34:22.847802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
21874 11:34:22.888757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
21875 11:34:22.889173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
21877 11:34:22.926705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
21879 11:34:22.927188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
21880 11:34:22.972124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
21881 11:34:22.972511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
21883 11:34:23.022650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
21885 11:34:23.023132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
21886 11:34:23.061312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
21887 11:34:23.061822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
21889 11:34:23.101382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
21890 11:34:23.101813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
21892 11:34:23.149690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
21894 11:34:23.150149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
21895 11:34:23.188884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
21896 11:34:23.189307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
21898 11:34:23.235304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
21899 11:34:23.235737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
21901 11:34:23.273099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
21902 11:34:23.273480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
21904 11:34:23.316628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
21905 11:34:23.317061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
21907 11:34:23.365337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
21909 11:34:23.365810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
21910 11:34:23.408184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
21912 11:34:23.408680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
21913 11:34:23.445150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
21914 11:34:23.445544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
21916 11:34:23.481303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
21918 11:34:23.481789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
21919 11:34:23.523860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
21920 11:34:23.524284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
21922 11:34:23.578779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
21924 11:34:23.579176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
21925 11:34:23.615096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
21927 11:34:23.615564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
21928 11:34:23.652138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
21929 11:34:23.652572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
21931 11:34:23.701725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
21932 11:34:23.702159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
21934 11:34:23.752356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
21935 11:34:23.752739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
21937 11:34:23.793240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
21938 11:34:23.793711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
21940 11:34:23.849722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
21941 11:34:23.850162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
21943 11:34:23.890088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
21944 11:34:23.890566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
21946 11:34:23.928992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
21947 11:34:23.929427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
21949 11:34:23.966263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
21950 11:34:23.966697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
21952 11:34:24.004397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
21953 11:34:24.004773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
21955 11:34:24.044914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
21957 11:34:24.045377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
21958 11:34:24.086078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
21959 11:34:24.086486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
21961 11:34:24.132194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
21962 11:34:24.132572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
21964 11:34:24.187526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
21965 11:34:24.187949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
21967 11:34:24.244736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
21968 11:34:24.245166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
21970 11:34:24.295168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
21971 11:34:24.295617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
21973 11:34:24.336232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
21974 11:34:24.336678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
21976 11:34:24.382049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
21977 11:34:24.382477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
21979 11:34:24.416381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
21980 11:34:24.416787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
21982 11:34:24.453910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
21984 11:34:24.454368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
21985 11:34:24.494504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
21987 11:34:24.494975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
21988 11:34:24.536576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
21989 11:34:24.536997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
21991 11:34:24.577952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
21992 11:34:24.578451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
21994 11:34:24.618263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
21996 11:34:24.619018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
21997 11:34:24.666604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
21999 11:34:24.667187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22000 11:34:24.709730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22001 11:34:24.710134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22003 11:34:24.744213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22004 11:34:24.744640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22006 11:34:24.776982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22007 11:34:24.777427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22009 11:34:24.824197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22010 11:34:24.824618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22012 11:34:24.860447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22013 11:34:24.860875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22015 11:34:24.897097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22016 11:34:24.897530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22018 11:34:24.936589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22019 11:34:24.937035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22021 11:34:24.974657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22023 11:34:24.975075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22024 11:34:25.015356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22026 11:34:25.015819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22027 11:34:25.057889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22029 11:34:25.058363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22030 11:34:25.097291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22032 11:34:25.097758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22033 11:34:25.139478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22034 11:34:25.139876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22036 11:34:25.183862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22037 11:34:25.184280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22039 11:34:25.219128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22040 11:34:25.219574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22042 11:34:25.257860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22043 11:34:25.258297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22045 11:34:25.297791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22047 11:34:25.298370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22048 11:34:25.335946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22049 11:34:25.336452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22051 11:34:25.378668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22053 11:34:25.379131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22054 11:34:25.418989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22056 11:34:25.419466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22057 11:34:25.456800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22058 11:34:25.457237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22060 11:34:25.497505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22061 11:34:25.497917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22063 11:34:25.533624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22064 11:34:25.534020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22066 11:34:25.577116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22067 11:34:25.577548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22069 11:34:25.616965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22070 11:34:25.617406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22072 11:34:25.662808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22074 11:34:25.663265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22075 11:34:25.700845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22076 11:34:25.701262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22078 11:34:25.735141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22079 11:34:25.735578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22081 11:34:25.770752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22083 11:34:25.771380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22084 11:34:25.808023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22085 11:34:25.808462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22087 11:34:25.843280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22088 11:34:25.843727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22090 11:34:25.885952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22091 11:34:25.886382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22093 11:34:25.940039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22094 11:34:25.940463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22096 11:34:25.980768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22097 11:34:25.981170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22099 11:34:26.027743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22101 11:34:26.028211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22102 11:34:26.076719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22104 11:34:26.077177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22105 11:34:26.117813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22107 11:34:26.118305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22108 11:34:26.166657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22110 11:34:26.167139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22111 11:34:26.204632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22112 11:34:26.205056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22114 11:34:26.249592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22115 11:34:26.250107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22117 11:34:26.292236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22118 11:34:26.292673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22120 11:34:26.332537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22121 11:34:26.332986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22123 11:34:26.373721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22124 11:34:26.374149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22126 11:34:26.421560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22127 11:34:26.422012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22129 11:34:26.461609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22130 11:34:26.462122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22132 11:34:26.515605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22134 11:34:26.516037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22135 11:34:26.563962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22136 11:34:26.564379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22138 11:34:26.611277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22139 11:34:26.611709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22141 11:34:26.655581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22142 11:34:26.656029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22144 11:34:26.695811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22145 11:34:26.696232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22147 11:34:26.745439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22148 11:34:26.745876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22150 11:34:26.798226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22151 11:34:26.798647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22153 11:34:26.844052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22154 11:34:26.844466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22156 11:34:26.889834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22158 11:34:26.890303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22159 11:34:26.934067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22160 11:34:26.934505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22162 11:34:26.976543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22163 11:34:26.976993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22165 11:34:27.039064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22166 11:34:27.039514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22168 11:34:27.084371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22169 11:34:27.084790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22171 11:34:27.123643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22172 11:34:27.124069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22174 11:34:27.165225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22175 11:34:27.165686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22177 11:34:27.204652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22179 11:34:27.205129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22180 11:34:27.256102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22182 11:34:27.256576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22183 11:34:27.293022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22184 11:34:27.293461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22186 11:34:27.332914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22187 11:34:27.333351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22189 11:34:27.372593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22190 11:34:27.372982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22192 11:34:27.420759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22193 11:34:27.421176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22195 11:34:27.456387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22196 11:34:27.456835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22198 11:34:27.495337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22199 11:34:27.495780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22201 11:34:27.534254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22203 11:34:27.534718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22204 11:34:27.581566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22206 11:34:27.582046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22207 11:34:27.631956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22208 11:34:27.632398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22210 11:34:27.681525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22211 11:34:27.681959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22213 11:34:27.736438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22214 11:34:27.736861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22216 11:34:27.779097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22217 11:34:27.779561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22219 11:34:27.818607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22221 11:34:27.819094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22222 11:34:27.860383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22224 11:34:27.860851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22225 11:34:27.904801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22226 11:34:27.905254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22228 11:34:27.956446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22229 11:34:27.956864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22231 11:34:28.006489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22233 11:34:28.007012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22234 11:34:28.048020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22235 11:34:28.048465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22237 11:34:28.093724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22238 11:34:28.094151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22240 11:34:28.144218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22241 11:34:28.144644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22243 11:34:28.182955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22244 11:34:28.183381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22246 11:34:28.223421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22248 11:34:28.223896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22249 11:34:28.270673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22251 11:34:28.271156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22252 11:34:28.312588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22253 11:34:28.313034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22255 11:34:28.349372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22256 11:34:28.349806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22258 11:34:28.386515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22260 11:34:28.386994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22261 11:34:28.428922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22262 11:34:28.429343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22264 11:34:28.468604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22265 11:34:28.468998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22267 11:34:28.505644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22268 11:34:28.506084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22270 11:34:28.542152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22271 11:34:28.542591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22273 11:34:28.580208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22274 11:34:28.580627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22276 11:34:28.618031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22278 11:34:28.618506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22279 11:34:28.655222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22281 11:34:28.655696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22282 11:34:28.697445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22283 11:34:28.697873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22285 11:34:28.736181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22287 11:34:28.736861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22288 11:34:28.777546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22290 11:34:28.778022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22291 11:34:28.819288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22292 11:34:28.819857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22294 11:34:28.864741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22296 11:34:28.865121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22297 11:34:28.903750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22298 11:34:28.904204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22300 11:34:28.940944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22301 11:34:28.941364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22303 11:34:28.987647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22305 11:34:28.988118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22306 11:34:29.037807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22307 11:34:29.038225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22309 11:34:29.076793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22311 11:34:29.077216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22312 11:34:29.130611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22314 11:34:29.131088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22315 11:34:29.180836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22316 11:34:29.181285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22318 11:34:29.221116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22319 11:34:29.221558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22321 11:34:29.275852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22322 11:34:29.276276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22324 11:34:29.324430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22325 11:34:29.324855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22327 11:34:29.361296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22328 11:34:29.361781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22330 11:34:29.404566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22331 11:34:29.405002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22333 11:34:29.448454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22334 11:34:29.448876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22336 11:34:29.485975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22337 11:34:29.486396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22339 11:34:29.540472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22340 11:34:29.540901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22342 11:34:29.585018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22343 11:34:29.585451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22345 11:34:29.622674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22347 11:34:29.623282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22348 11:34:29.658124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22350 11:34:29.658601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22351 11:34:29.699143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22353 11:34:29.699615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22354 11:34:29.735872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22355 11:34:29.736322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22357 11:34:29.774252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22358 11:34:29.774688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22360 11:34:29.814565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22362 11:34:29.815059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22363 11:34:29.858172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22364 11:34:29.858559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22366 11:34:29.894341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22367 11:34:29.894725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22369 11:34:29.936468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22370 11:34:29.936911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22372 11:34:29.978733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22374 11:34:29.979301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22375 11:34:30.017049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22377 11:34:30.017804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22378 11:34:30.053326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22379 11:34:30.053811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22381 11:34:30.093267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22382 11:34:30.093690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22384 11:34:30.132951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22385 11:34:30.133453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22387 11:34:30.169877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22388 11:34:30.170370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22390 11:34:30.205776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22391 11:34:30.206202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22393 11:34:30.241276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22395 11:34:30.241752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22396 11:34:30.289596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22397 11:34:30.290021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22399 11:34:30.325770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22400 11:34:30.326301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22402 11:34:30.364001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22403 11:34:30.364468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22405 11:34:30.405969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22406 11:34:30.406409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22408 11:34:30.449964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22409 11:34:30.450403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22411 11:34:30.489905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22413 11:34:30.490374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22414 11:34:30.528186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22415 11:34:30.528608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22417 11:34:30.564443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22418 11:34:30.564839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22420 11:34:30.612781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22421 11:34:30.613159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22423 11:34:30.649592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22425 11:34:30.650075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22426 11:34:30.693871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22427 11:34:30.694273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22429 11:34:30.735098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22430 11:34:30.735491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22432 11:34:30.789285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22433 11:34:30.789685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22435 11:34:30.841105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22436 11:34:30.841529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22438 11:34:30.880128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22439 11:34:30.880555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22441 11:34:30.920619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22442 11:34:30.921064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22444 11:34:30.966353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22446 11:34:30.966788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22447 11:34:31.017180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22449 11:34:31.017591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22450 11:34:31.067157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22452 11:34:31.067615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22453 11:34:31.104567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22454 11:34:31.104999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22456 11:34:31.143428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22457 11:34:31.143831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22459 11:34:31.181132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22460 11:34:31.181548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22462 11:34:31.219735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22463 11:34:31.220159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22465 11:34:31.261453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22466 11:34:31.261889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22468 11:34:31.308722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22470 11:34:31.309184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22471 11:34:31.356742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22473 11:34:31.357521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22474 11:34:31.396235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22475 11:34:31.396713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22477 11:34:31.437180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22478 11:34:31.437599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22480 11:34:31.494836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22482 11:34:31.495310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22483 11:34:31.537037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22484 11:34:31.537472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22486 11:34:31.584943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22487 11:34:31.585370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22489 11:34:31.625286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22490 11:34:31.625692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22492 11:34:31.664095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22494 11:34:31.664564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22495 11:34:31.716470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22497 11:34:31.716959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22498 11:34:31.756853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22499 11:34:31.757259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22501 11:34:31.800638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22502 11:34:31.801067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22504 11:34:31.844184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22505 11:34:31.844607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22507 11:34:31.887616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22508 11:34:31.888000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22510 11:34:31.945277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22511 11:34:31.945701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22513 11:34:32.004626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22514 11:34:32.004950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22516 11:34:32.055934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22517 11:34:32.056331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22519 11:34:32.094248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22520 11:34:32.094645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22522 11:34:32.160803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22523 11:34:32.161288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22525 11:34:32.206069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22526 11:34:32.206465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22528 11:34:32.245555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22529 11:34:32.245959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22531 11:34:32.285972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22532 11:34:32.286452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22534 11:34:32.335835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22535 11:34:32.336192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22537 11:34:32.384579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22538 11:34:32.385048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22540 11:34:32.440614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22541 11:34:32.441028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22543 11:34:32.485697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22544 11:34:32.486060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22546 11:34:32.524259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22547 11:34:32.524672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22549 11:34:32.569160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22550 11:34:32.569568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22552 11:34:32.615710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22554 11:34:32.616084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22555 11:34:32.661683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22557 11:34:32.662111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22558 11:34:32.708627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22559 11:34:32.709054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22561 11:34:32.755353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22562 11:34:32.755792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22564 11:34:32.795722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22565 11:34:32.796180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22567 11:34:32.836804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22568 11:34:32.837186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22570 11:34:32.878563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22572 11:34:32.879009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22573 11:34:32.918873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22574 11:34:32.919256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22576 11:34:32.958180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22577 11:34:32.958688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22579 11:34:33.007119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22580 11:34:33.007655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22582 11:34:33.065252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22583 11:34:33.065637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22585 11:34:33.107839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22586 11:34:33.108264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22588 11:34:33.144720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22589 11:34:33.145143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22591 11:34:33.189920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22593 11:34:33.190399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22594 11:34:33.233158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22596 11:34:33.233568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22597 11:34:33.278228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22599 11:34:33.278655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22600 11:34:33.329423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22601 11:34:33.329819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22603 11:34:33.373391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22604 11:34:33.373802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22606 11:34:33.414230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22607 11:34:33.414705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22609 11:34:33.455870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22610 11:34:33.456308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22612 11:34:33.511465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22614 11:34:33.511936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22615 11:34:33.553286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22616 11:34:33.553653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22618 11:34:33.590729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22620 11:34:33.591144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22621 11:34:33.631800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22622 11:34:33.632195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22624 11:34:33.672120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22625 11:34:33.672591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22627 11:34:33.719433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22629 11:34:33.719897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22630 11:34:33.771986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22631 11:34:33.772403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22633 11:34:33.817722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22634 11:34:33.818161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22636 11:34:33.867506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22637 11:34:33.867964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22639 11:34:33.911544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22640 11:34:33.911971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22642 11:34:33.951117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22643 11:34:33.951553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22645 11:34:33.989940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22646 11:34:33.990375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22648 11:34:34.029531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22650 11:34:34.030016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22651 11:34:34.069146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22652 11:34:34.069588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22654 11:34:34.107957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22656 11:34:34.108420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22657 11:34:34.147217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22658 11:34:34.147643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22660 11:34:34.189540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22661 11:34:34.190012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22663 11:34:34.233826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22665 11:34:34.234271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22666 11:34:34.277001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22667 11:34:34.277343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22669 11:34:34.315008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22671 11:34:34.315465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22672 11:34:34.353967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22674 11:34:34.354429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22675 11:34:34.408022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22676 11:34:34.408577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22678 11:34:34.448156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22680 11:34:34.448777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22681 11:34:34.495021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22682 11:34:34.495567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22684 11:34:34.535469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22685 11:34:34.535867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22687 11:34:34.579981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22689 11:34:34.580608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22690 11:34:34.623913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22692 11:34:34.624304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22693 11:34:34.671297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22695 11:34:34.671776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22696 11:34:34.716489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22697 11:34:34.716877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22699 11:34:34.756829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22700 11:34:34.757248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22702 11:34:34.804645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22703 11:34:34.805074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22705 11:34:34.845179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22706 11:34:34.845623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22708 11:34:34.895632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22709 11:34:34.896072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22711 11:34:34.943366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22713 11:34:34.943803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22714 11:34:34.981201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22715 11:34:34.981563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22717 11:34:35.019531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22718 11:34:35.020031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22720 11:34:35.064149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22721 11:34:35.064527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22723 11:34:35.111279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22724 11:34:35.111667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22726 11:34:35.167985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22728 11:34:35.168607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22729 11:34:35.225322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22731 11:34:35.225950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22732 11:34:35.278200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22733 11:34:35.278559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22735 11:34:35.315744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22736 11:34:35.316128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22738 11:34:35.352099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22739 11:34:35.352535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22741 11:34:35.387459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22742 11:34:35.387885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22744 11:34:35.425911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22745 11:34:35.426323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22747 11:34:35.463363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22748 11:34:35.463830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22750 11:34:35.500369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22751 11:34:35.500799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22753 11:34:35.540626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22754 11:34:35.541066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
22756 11:34:35.584067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
22757 11:34:35.584489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
22759 11:34:35.624527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
22761 11:34:35.625001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
22762 11:34:35.667749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
22763 11:34:35.668175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
22765 11:34:35.713273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
22766 11:34:35.713693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
22768 11:34:35.750670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
22770 11:34:35.751151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
22771 11:34:35.787495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
22773 11:34:35.787978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
22774 11:34:35.823527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
22775 11:34:35.823951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
22777 11:34:35.859346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
22778 11:34:35.859773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
22780 11:34:35.895570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
22781 11:34:35.895990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
22783 11:34:35.931804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
22784 11:34:35.932228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
22786 11:34:35.968263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
22787 11:34:35.968663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
22789 11:34:36.011279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
22790 11:34:36.011644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
22792 11:34:36.049094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
22793 11:34:36.049485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
22795 11:34:36.085079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
22796 11:34:36.085497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
22798 11:34:36.121998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
22799 11:34:36.122431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
22801 11:34:36.159545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
22802 11:34:36.159974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
22804 11:34:36.195745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
22805 11:34:36.196182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
22807 11:34:36.231753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
22808 11:34:36.232156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
22810 11:34:36.267500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
22811 11:34:36.268055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
22813 11:34:36.309777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
22814 11:34:36.310177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
22816 11:34:36.343674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
22817 11:34:36.344087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
22819 11:34:36.378543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
22821 11:34:36.379023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
22822 11:34:36.413940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
22823 11:34:36.414367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
22825 11:34:36.451282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
22826 11:34:36.451692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
22828 11:34:36.487341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
22829 11:34:36.487759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
22831 11:34:36.523350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
22832 11:34:36.523778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
22834 11:34:36.559347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
22835 11:34:36.559762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
22837 11:34:36.595915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
22838 11:34:36.596334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
22840 11:34:36.632538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
22841 11:34:36.633091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
22843 11:34:36.667976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
22844 11:34:36.668395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
22846 11:34:36.704144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
22848 11:34:36.704601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
22849 11:34:36.740353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
22850 11:34:36.740906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
22852 11:34:36.781229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
22853 11:34:36.781573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
22855 11:34:36.830296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
22857 11:34:36.830781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
22858 11:34:36.866571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
22860 11:34:36.867028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
22861 11:34:36.908221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
22862 11:34:36.908669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
22864 11:34:36.944029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
22866 11:34:36.944482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
22867 11:34:36.979860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
22868 11:34:36.980269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
22870 11:34:37.015930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
22871 11:34:37.016345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
22873 11:34:37.051963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
22874 11:34:37.052380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
22876 11:34:37.087209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
22878 11:34:37.087664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
22879 11:34:37.124578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
22880 11:34:37.124991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
22882 11:34:37.164277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
22883 11:34:37.164685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
22885 11:34:37.205761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
22886 11:34:37.206196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
22888 11:34:37.261112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
22889 11:34:37.261531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
22891 11:34:37.307196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
22892 11:34:37.307658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
22894 11:34:37.348576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
22895 11:34:37.349035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
22897 11:34:37.384437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
22898 11:34:37.384868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
22900 11:34:37.430187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
22902 11:34:37.430678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
22903 11:34:37.469899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
22904 11:34:37.470312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
22906 11:34:37.507759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
22907 11:34:37.508186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
22909 11:34:37.558076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
22910 11:34:37.558536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
22912 11:34:37.597715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
22913 11:34:37.598109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
22915 11:34:37.645548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
22916 11:34:37.646113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
22918 11:34:37.683624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
22920 11:34:37.684320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
22921 11:34:37.724832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
22922 11:34:37.725247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
22924 11:34:37.762629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
22926 11:34:37.763090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
22927 11:34:37.799919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
22929 11:34:37.800295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
22930 11:34:37.843858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
22931 11:34:37.844282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
22933 11:34:37.880317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
22935 11:34:37.880786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
22936 11:34:37.917114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
22938 11:34:37.917525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
22939 11:34:37.954605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
22941 11:34:37.955070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
22942 11:34:37.990745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
22944 11:34:37.991206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
22945 11:34:38.027338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
22946 11:34:38.027731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
22948 11:34:38.071865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
22950 11:34:38.072286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
22951 11:34:38.116420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
22953 11:34:38.117008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
22954 11:34:38.163190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
22955 11:34:38.163767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
22957 11:34:38.203995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
22959 11:34:38.204463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
22960 11:34:38.239622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
22961 11:34:38.240092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
22963 11:34:38.279263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
22964 11:34:38.279784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
22966 11:34:38.323438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
22967 11:34:38.323884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
22969 11:34:38.367613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
22970 11:34:38.368098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
22972 11:34:38.401624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
22973 11:34:38.402207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
22975 11:34:38.445916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
22976 11:34:38.446455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
22978 11:34:38.489804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
22979 11:34:38.490288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
22981 11:34:38.540581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
22982 11:34:38.541008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
22984 11:34:38.593632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
22986 11:34:38.594111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
22987 11:34:38.634109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
22988 11:34:38.634515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
22990 11:34:38.668302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
22991 11:34:38.668701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
22993 11:34:38.702287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
22994 11:34:38.702700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
22996 11:34:38.736758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
22997 11:34:38.737169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
22999 11:34:38.773076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23001 11:34:38.773502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23002 11:34:38.811652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23003 11:34:38.812067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23005 11:34:38.849910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23007 11:34:38.850335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23008 11:34:38.893201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23009 11:34:38.893586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23011 11:34:38.928865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23013 11:34:38.929250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23014 11:34:38.971299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23015 11:34:38.971731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23017 11:34:39.020854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23018 11:34:39.021364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23020 11:34:39.061932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23021 11:34:39.062506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23023 11:34:39.108442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23024 11:34:39.109024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23026 11:34:39.147482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23028 11:34:39.147954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23029 11:34:39.184773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23030 11:34:39.185207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23032 11:34:39.227713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23033 11:34:39.228160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23035 11:34:39.269216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23037 11:34:39.269707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23038 11:34:39.314806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23040 11:34:39.315279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23041 11:34:39.362677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23043 11:34:39.363139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23044 11:34:39.407577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23046 11:34:39.408058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23047 11:34:39.444838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23048 11:34:39.445260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23050 11:34:39.498990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23052 11:34:39.499723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23053 11:34:39.540067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23054 11:34:39.540553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23056 11:34:39.588871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23057 11:34:39.589291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23059 11:34:39.626600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23061 11:34:39.627071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23062 11:34:39.665502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23063 11:34:39.665963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23065 11:34:39.714194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23066 11:34:39.714652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23068 11:34:39.764121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23069 11:34:39.764552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23071 11:34:39.801731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23072 11:34:39.802205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23074 11:34:39.855831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23075 11:34:39.856208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23077 11:34:39.911365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23078 11:34:39.911813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23080 11:34:39.951745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23082 11:34:39.952215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23083 11:34:39.989851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23084 11:34:39.990236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23086 11:34:40.047281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23087 11:34:40.047809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23089 11:34:40.098637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23091 11:34:40.099101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23092 11:34:40.148843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23093 11:34:40.149325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23095 11:34:40.194092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23096 11:34:40.194644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23098 11:34:40.230118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23099 11:34:40.230604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23101 11:34:40.268650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23102 11:34:40.269153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23104 11:34:40.324209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23106 11:34:40.324956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23107 11:34:40.368502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23108 11:34:40.368893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23110 11:34:40.416065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23111 11:34:40.416492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23113 11:34:40.456135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23114 11:34:40.456576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23116 11:34:40.501250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23118 11:34:40.501734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23119 11:34:40.543768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23120 11:34:40.544155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23122 11:34:40.580111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23123 11:34:40.580534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23125 11:34:40.625523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23126 11:34:40.625968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23128 11:34:40.669709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23129 11:34:40.670138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23131 11:34:40.718629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23133 11:34:40.719083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23134 11:34:40.761671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23135 11:34:40.762083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23137 11:34:40.797141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23138 11:34:40.797586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23140 11:34:40.832312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23141 11:34:40.832758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23143 11:34:40.871890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23144 11:34:40.872273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23146 11:34:40.921837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23147 11:34:40.922399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23149 11:34:40.964298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23150 11:34:40.964786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23152 11:34:41.003994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23153 11:34:41.004465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23155 11:34:41.044174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23157 11:34:41.044652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23158 11:34:41.085043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23159 11:34:41.085438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23161 11:34:41.124755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23162 11:34:41.125215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23164 11:34:41.163123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23165 11:34:41.163580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23167 11:34:41.200317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23168 11:34:41.201744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23170 11:34:41.255672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23171 11:34:41.256059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23173 11:34:41.299701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23174 11:34:41.300090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23176 11:34:41.337802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23177 11:34:41.338258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23179 11:34:41.371709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23180 11:34:41.372160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23182 11:34:41.408339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23183 11:34:41.408792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23185 11:34:41.448947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23186 11:34:41.449371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23188 11:34:41.496130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23189 11:34:41.496550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23191 11:34:41.533185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23192 11:34:41.533627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23194 11:34:41.577418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23195 11:34:41.577857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23197 11:34:41.617063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23198 11:34:41.617494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23200 11:34:41.658178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23201 11:34:41.658610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23203 11:34:41.710091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23204 11:34:41.710526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23206 11:34:41.753843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23207 11:34:41.754233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23209 11:34:41.792151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23210 11:34:41.792555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23212 11:34:41.839352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23213 11:34:41.839854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23215 11:34:41.882195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23216 11:34:41.882635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23218 11:34:41.920486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23219 11:34:41.920874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23221 11:34:41.960351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23222 11:34:41.960710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23224 11:34:41.999483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23225 11:34:41.999933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23227 11:34:42.048075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23228 11:34:42.048560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23230 11:34:42.087823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23231 11:34:42.088258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23233 11:34:42.127477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23234 11:34:42.127898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23236 11:34:42.170523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23238 11:34:42.171018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23239 11:34:42.211364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23240 11:34:42.211745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23242 11:34:42.252792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23243 11:34:42.253232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23245 11:34:42.290290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23246 11:34:42.290681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23248 11:34:42.335953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23249 11:34:42.336371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23251 11:34:42.391806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23252 11:34:42.392246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23254 11:34:42.427869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23255 11:34:42.428218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23257 11:34:42.466347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23258 11:34:42.466765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23260 11:34:42.503823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23261 11:34:42.504238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23263 11:34:42.549565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23265 11:34:42.551352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23266 11:34:42.593384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23267 11:34:42.593759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23269 11:34:42.632195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23270 11:34:42.632680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23272 11:34:42.672941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23273 11:34:42.673389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23275 11:34:42.721257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23277 11:34:42.721734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23278 11:34:42.764244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23279 11:34:42.764727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23281 11:34:42.804043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23282 11:34:42.804489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23284 11:34:42.840019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23286 11:34:42.840488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23287 11:34:42.875413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23288 11:34:42.875826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23290 11:34:42.914715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23292 11:34:42.915137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23293 11:34:42.949965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23294 11:34:42.950355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23296 11:34:42.990120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23297 11:34:42.990550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23299 11:34:43.025838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23300 11:34:43.026218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23302 11:34:43.074031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23303 11:34:43.074467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23305 11:34:43.131683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23306 11:34:43.132107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23308 11:34:43.173922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23309 11:34:43.174349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23311 11:34:43.208624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23312 11:34:43.209170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23314 11:34:43.251721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23315 11:34:43.252144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23317 11:34:43.287354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23318 11:34:43.287783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23320 11:34:43.323333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23321 11:34:43.323855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23323 11:34:43.358229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23325 11:34:43.358694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23326 11:34:43.394040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23327 11:34:43.394469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23329 11:34:43.429524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23330 11:34:43.429948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23332 11:34:43.467614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23333 11:34:43.468032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23335 11:34:43.505805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23337 11:34:43.506272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23338 11:34:43.547863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23339 11:34:43.548283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23341 11:34:43.601625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23342 11:34:43.602153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23344 11:34:43.639725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23346 11:34:43.640354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23347 11:34:43.692007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23348 11:34:43.692571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23350 11:34:43.731794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23351 11:34:43.732237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23353 11:34:43.768530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23354 11:34:43.768956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23356 11:34:43.806128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23357 11:34:43.806561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23359 11:34:43.849316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23361 11:34:43.849810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23362 11:34:43.887465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23364 11:34:43.887849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23365 11:34:43.925208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23367 11:34:43.925823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23368 11:34:43.964986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23369 11:34:43.965429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23371 11:34:44.008599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23372 11:34:44.009020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23374 11:34:44.056067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23375 11:34:44.056456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23377 11:34:44.105602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23378 11:34:44.106031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23380 11:34:44.148384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23382 11:34:44.148839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23383 11:34:44.189837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23384 11:34:44.190367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23386 11:34:44.242107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23387 11:34:44.242554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23389 11:34:44.289164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23390 11:34:44.289580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23392 11:34:44.340411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23393 11:34:44.340831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23395 11:34:44.394301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23396 11:34:44.394770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23398 11:34:44.433263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23399 11:34:44.433691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23401 11:34:44.475319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23402 11:34:44.475753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23404 11:34:44.524392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23405 11:34:44.524821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23407 11:34:44.569336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23408 11:34:44.569743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23410 11:34:44.615720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23412 11:34:44.616180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23413 11:34:44.658172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23414 11:34:44.658596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23416 11:34:44.699206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23418 11:34:44.699677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23419 11:34:44.747114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23421 11:34:44.747591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23422 11:34:44.782783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23424 11:34:44.783250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23425 11:34:44.828701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23427 11:34:44.829121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23428 11:34:44.870237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23429 11:34:44.870662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23431 11:34:44.925720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23433 11:34:44.926190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23434 11:34:44.973134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23436 11:34:44.973599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23437 11:34:45.025723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23439 11:34:45.026199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23440 11:34:45.073305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23441 11:34:45.073750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23443 11:34:45.127005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23444 11:34:45.127428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23446 11:34:45.161217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23447 11:34:45.161685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23449 11:34:45.195542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23451 11:34:45.195990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23452 11:34:45.230621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23454 11:34:45.231048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23455 11:34:45.268298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23456 11:34:45.268749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23458 11:34:45.318318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23459 11:34:45.318764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23461 11:34:45.358204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23462 11:34:45.358645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23464 11:34:45.399316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23465 11:34:45.399758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23467 11:34:45.447444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23468 11:34:45.447852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23470 11:34:45.487402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23471 11:34:45.487820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23473 11:34:45.527812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23474 11:34:45.528239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23476 11:34:45.569380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23477 11:34:45.569813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23479 11:34:45.608364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23480 11:34:45.608806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23482 11:34:45.656897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23483 11:34:45.657343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23485 11:34:45.696643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23487 11:34:45.697085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23488 11:34:45.755539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23489 11:34:45.755976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23491 11:34:45.813679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23493 11:34:45.814082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23494 11:34:45.873246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23495 11:34:45.873677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23497 11:34:45.931316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23498 11:34:45.931775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23500 11:34:45.989794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23501 11:34:45.990169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23503 11:34:46.043239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23504 11:34:46.043655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23506 11:34:46.079945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23507 11:34:46.080360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23509 11:34:46.124539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23510 11:34:46.124978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23512 11:34:46.179606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23513 11:34:46.180032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23515 11:34:46.221514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23516 11:34:46.221912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23518 11:34:46.275370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23520 11:34:46.275838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23521 11:34:46.313081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23522 11:34:46.313495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23524 11:34:46.352474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23525 11:34:46.352866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23527 11:34:46.393423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23528 11:34:46.393935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23530 11:34:46.435504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23531 11:34:46.435988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23533 11:34:46.494297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23535 11:34:46.494950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23536 11:34:46.551807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23537 11:34:46.552315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23539 11:34:46.606010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23540 11:34:46.606531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23542 11:34:46.647062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23543 11:34:46.647486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23545 11:34:46.684018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23546 11:34:46.684448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23548 11:34:46.729596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23549 11:34:46.730047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23551 11:34:46.777796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23553 11:34:46.778257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23554 11:34:46.816763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23556 11:34:46.817225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23557 11:34:46.857523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23559 11:34:46.857992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23560 11:34:46.901287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23561 11:34:46.901687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23563 11:34:46.943461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23564 11:34:46.943887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23566 11:34:46.993005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23567 11:34:46.993451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23569 11:34:47.044102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23570 11:34:47.044539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23572 11:34:47.100901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23573 11:34:47.101280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23575 11:34:47.141446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23576 11:34:47.141838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23578 11:34:47.187874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23579 11:34:47.188367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23581 11:34:47.227442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23583 11:34:47.228082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23584 11:34:47.276092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23585 11:34:47.276547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23587 11:34:47.313867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23588 11:34:47.314319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23590 11:34:47.352614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23591 11:34:47.353058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23593 11:34:47.394842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23595 11:34:47.395724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23596 11:34:47.442900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23598 11:34:47.443550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23599 11:34:47.514921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23600 11:34:47.515306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23602 11:34:47.554338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23603 11:34:47.554779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23605 11:34:47.596451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23607 11:34:47.596923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23608 11:34:47.635406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23610 11:34:47.635854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23611 11:34:47.683508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23612 11:34:47.683920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23614 11:34:47.746126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23615 11:34:47.746545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23617 11:34:47.796906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23618 11:34:47.797344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23620 11:34:47.836543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23621 11:34:47.836953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23623 11:34:47.887839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23624 11:34:47.888262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23626 11:34:47.938077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23628 11:34:47.938530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23629 11:34:47.988870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23630 11:34:47.989262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23632 11:34:48.046065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23633 11:34:48.046499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23635 11:34:48.104439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23636 11:34:48.104900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23638 11:34:48.161564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23639 11:34:48.162037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23641 11:34:48.219716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23642 11:34:48.220114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23644 11:34:48.277571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23645 11:34:48.278013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23647 11:34:48.329403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23649 11:34:48.329896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23650 11:34:48.367519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23652 11:34:48.367994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23653 11:34:48.416987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23654 11:34:48.417420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23656 11:34:48.467149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23657 11:34:48.467570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23659 11:34:48.503665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23661 11:34:48.504140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23662 11:34:48.545370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23663 11:34:48.545805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23665 11:34:48.584646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23666 11:34:48.585089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23668 11:34:48.630154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23670 11:34:48.630636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23671 11:34:48.671465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23672 11:34:48.671927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23674 11:34:48.707042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23675 11:34:48.707434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23677 11:34:48.755225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23679 11:34:48.756043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23680 11:34:48.804882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23682 11:34:48.805348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23683 11:34:48.859173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23685 11:34:48.859648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23686 11:34:48.908453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23687 11:34:48.908795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23689 11:34:48.952241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23690 11:34:48.952617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23692 11:34:48.992893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23693 11:34:48.993242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23695 11:34:49.034019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23696 11:34:49.034395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23698 11:34:49.075581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23700 11:34:49.075994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23701 11:34:49.113016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23702 11:34:49.113410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23704 11:34:49.149614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23706 11:34:49.150060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23707 11:34:49.189190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23709 11:34:49.189930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23710 11:34:49.242054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23712 11:34:49.242508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23713 11:34:49.278199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23714 11:34:49.278658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23716 11:34:49.330074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23717 11:34:49.330500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23719 11:34:49.368412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23721 11:34:49.368882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23722 11:34:49.405406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23724 11:34:49.406195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23725 11:34:49.444429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23726 11:34:49.444835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23728 11:34:49.489557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23729 11:34:49.489956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23731 11:34:49.536276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23732 11:34:49.536696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23734 11:34:49.583994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23735 11:34:49.584431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23737 11:34:49.633336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23738 11:34:49.633766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23740 11:34:49.689722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23741 11:34:49.690094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23743 11:34:49.731881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23745 11:34:49.732317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23746 11:34:49.777939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23747 11:34:49.778371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23749 11:34:49.824234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23750 11:34:49.824670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23752 11:34:49.871171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23753 11:34:49.871603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
23755 11:34:49.920024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
23756 11:34:49.920443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
23758 11:34:49.959708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
23760 11:34:49.960173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
23761 11:34:50.009512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
23762 11:34:50.009910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
23764 11:34:50.055810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
23765 11:34:50.056246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
23767 11:34:50.105249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
23768 11:34:50.105696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
23770 11:34:50.148331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
23771 11:34:50.148712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
23773 11:34:50.206069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
23774 11:34:50.206510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
23776 11:34:50.259394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
23778 11:34:50.259768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
23779 11:34:50.295283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
23780 11:34:50.295700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
23782 11:34:50.332311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
23784 11:34:50.332742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
23785 11:34:50.379827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
23786 11:34:50.380248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
23788 11:34:50.420074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
23789 11:34:50.420485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
23791 11:34:50.460783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
23792 11:34:50.461220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
23794 11:34:50.500688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
23796 11:34:50.501144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
23797 11:34:50.547450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
23798 11:34:50.547859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
23800 11:34:50.595470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
23801 11:34:50.595875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
23803 11:34:50.645064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
23804 11:34:50.645503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
23806 11:34:50.695853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
23807 11:34:50.696236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
23809 11:34:50.737812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
23810 11:34:50.738389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
23812 11:34:50.788578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
23814 11:34:50.789335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
23815 11:34:50.835780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
23816 11:34:50.836212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
23818 11:34:50.885656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
23819 11:34:50.886038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
23821 11:34:50.936575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
23822 11:34:50.937012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
23824 11:34:50.977968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
23825 11:34:50.978395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
23827 11:34:51.032613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
23828 11:34:51.033057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
23830 11:34:51.077149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
23831 11:34:51.077576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
23833 11:34:51.130650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
23835 11:34:51.131127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
23836 11:34:51.178378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
23838 11:34:51.178863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
23839 11:34:51.219096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
23840 11:34:51.219476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
23842 11:34:51.267959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
23843 11:34:51.268381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
23845 11:34:51.305270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
23846 11:34:51.305686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
23848 11:34:51.342084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
23849 11:34:51.342558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
23851 11:34:51.379770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
23852 11:34:51.380192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
23854 11:34:51.427189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
23855 11:34:51.427611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
23857 11:34:51.470266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
23858 11:34:51.470699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
23860 11:34:51.516782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
23862 11:34:51.517243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
23863 11:34:51.568110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
23864 11:34:51.568539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
23866 11:34:51.607012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
23867 11:34:51.607444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
23869 11:34:51.655940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
23870 11:34:51.656360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
23872 11:34:51.695260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
23874 11:34:51.695665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
23875 11:34:51.735247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
23876 11:34:51.735622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
23878 11:34:51.775826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
23879 11:34:51.776215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
23881 11:34:51.831995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
23883 11:34:51.832492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
23884 11:34:51.870180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
23886 11:34:51.870580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
23887 11:34:51.907072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
23888 11:34:51.907519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
23890 11:34:51.942187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
23891 11:34:51.942688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
23893 11:34:51.993676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
23894 11:34:51.994116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
23896 11:34:52.032799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
23898 11:34:52.033274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
23899 11:34:52.075700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
23900 11:34:52.076117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
23902 11:34:52.112972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
23904 11:34:52.113392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
23905 11:34:52.152725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
23907 11:34:52.153157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
23908 11:34:52.189101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
23909 11:34:52.189513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
23911 11:34:52.230053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
23912 11:34:52.230442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
23914 11:34:52.287938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
23915 11:34:52.288367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
23917 11:34:52.343736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
23918 11:34:52.344161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
23920 11:34:52.400484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
23921 11:34:52.400942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
23923 11:34:52.456777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
23924 11:34:52.457249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
23926 11:34:52.516101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
23928 11:34:52.517777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
23929 11:34:52.563070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
23930 11:34:52.563539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
23932 11:34:52.617360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
23933 11:34:52.617806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
23935 11:34:52.674016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
23937 11:34:52.674484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
23938 11:34:52.716484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
23939 11:34:52.716930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
23941 11:34:52.753907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
23942 11:34:52.754327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
23944 11:34:52.794537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
23946 11:34:52.795055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
23947 11:34:52.832502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
23948 11:34:52.832941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
23950 11:34:52.869035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
23951 11:34:52.869449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
23953 11:34:52.918678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
23955 11:34:52.919138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
23956 11:34:52.954761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
23958 11:34:52.955192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
23959 11:34:52.997758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
23960 11:34:52.998148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
23962 11:34:53.045928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
23963 11:34:53.046363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
23965 11:34:53.094071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
23966 11:34:53.094472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
23968 11:34:53.138232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
23970 11:34:53.138844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
23971 11:34:53.175918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
23972 11:34:53.176330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
23974 11:34:53.221451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
23975 11:34:53.221884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
23977 11:34:53.270112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
23979 11:34:53.270572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
23980 11:34:53.308604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
23981 11:34:53.309025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
23983 11:34:53.356346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
23984 11:34:53.356706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
23986 11:34:53.400165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
23987 11:34:53.400573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
23989 11:34:53.449072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
23990 11:34:53.449439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
23992 11:34:53.488816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
23994 11:34:53.489286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
23995 11:34:53.537689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
23996 11:34:53.538138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
23998 11:34:53.584978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
23999 11:34:53.585413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24001 11:34:53.633982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24003 11:34:53.634445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24004 11:34:53.670277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24006 11:34:53.670738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24007 11:34:53.707424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24009 11:34:53.707891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24010 11:34:53.749664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24012 11:34:53.750138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24013 11:34:53.792873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24014 11:34:53.793291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24016 11:34:53.829865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24017 11:34:53.830316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24019 11:34:53.867677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24020 11:34:53.868124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24022 11:34:53.903106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24023 11:34:53.903532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24025 11:34:53.938085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24027 11:34:53.938562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24028 11:34:53.973691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24030 11:34:53.974153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24031 11:34:54.009736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24032 11:34:54.010189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24034 11:34:54.061253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24035 11:34:54.061670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24037 11:34:54.097295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24038 11:34:54.097695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24040 11:34:54.133010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24041 11:34:54.133434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24043 11:34:54.175683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24044 11:34:54.176117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24046 11:34:54.219585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24047 11:34:54.220001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24049 11:34:54.257924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24050 11:34:54.258359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24052 11:34:54.296188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24054 11:34:54.296670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24055 11:34:54.333286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24056 11:34:54.333744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24058 11:34:54.373279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24059 11:34:54.373768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24061 11:34:54.416971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24063 11:34:54.417436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24064 11:34:54.455996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24065 11:34:54.456413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24067 11:34:54.491749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24068 11:34:54.492185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24070 11:34:54.528083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24071 11:34:54.528516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24073 11:34:54.568867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24074 11:34:54.569303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24076 11:34:54.621820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24077 11:34:54.622252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24079 11:34:54.666375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24081 11:34:54.666962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24082 11:34:54.717565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24083 11:34:54.717993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24085 11:34:54.755642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24086 11:34:54.756062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24088 11:34:54.805325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24089 11:34:54.805755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24091 11:34:54.845165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24092 11:34:54.845596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24094 11:34:54.881126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24095 11:34:54.881548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24097 11:34:54.926562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24099 11:34:54.927047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24100 11:34:54.963408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24101 11:34:54.963848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24103 11:34:55.000714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24104 11:34:55.001090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24106 11:34:55.039504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24107 11:34:55.039936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24109 11:34:55.075941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24110 11:34:55.076376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24112 11:34:55.128317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24113 11:34:55.128744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24115 11:34:55.167555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24116 11:34:55.168015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24118 11:34:55.213298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24119 11:34:55.213679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24121 11:34:55.256354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24123 11:34:55.256816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24124 11:34:55.293242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24125 11:34:55.293667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24127 11:34:55.332078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24128 11:34:55.332495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24130 11:34:55.367225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24131 11:34:55.367649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24133 11:34:55.403301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24135 11:34:55.403763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24136 11:34:55.440820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24138 11:34:55.441279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24139 11:34:55.476642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24140 11:34:55.477051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24142 11:34:55.512983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24143 11:34:55.513397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24145 11:34:55.559771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24146 11:34:55.560205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24148 11:34:55.599615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24149 11:34:55.600054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24151 11:34:55.643390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24152 11:34:55.643821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24154 11:34:55.693252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24155 11:34:55.693689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24157 11:34:55.743894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24158 11:34:55.744294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24160 11:34:55.793758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24161 11:34:55.794200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24163 11:34:55.844117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24164 11:34:55.844547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24166 11:34:55.893921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24168 11:34:55.894389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24169 11:34:55.941838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24170 11:34:55.942288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24172 11:34:55.990009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24174 11:34:55.990433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24175 11:34:56.034086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24176 11:34:56.034505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24178 11:34:56.077859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24180 11:34:56.078582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24181 11:34:56.123915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24182 11:34:56.124313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24184 11:34:56.161592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24186 11:34:56.161982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24187 11:34:56.195372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24189 11:34:56.195841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24190 11:34:56.239157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24191 11:34:56.239564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24193 11:34:56.293284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24194 11:34:56.293681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24196 11:34:56.339566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24198 11:34:56.339989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24199 11:34:56.376472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24200 11:34:56.376868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24202 11:34:56.411433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24203 11:34:56.411845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24205 11:34:56.451325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24206 11:34:56.451753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24208 11:34:56.484469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24209 11:34:56.484913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24211 11:34:56.518592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24213 11:34:56.519071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24214 11:34:56.553539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24215 11:34:56.553986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24217 11:34:56.596445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24218 11:34:56.596844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24220 11:34:56.633794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24222 11:34:56.634271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24223 11:34:56.676718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24224 11:34:56.677094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24226 11:34:56.730592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24228 11:34:56.731163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24229 11:34:56.768594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24230 11:34:56.769020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24232 11:34:56.808695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24233 11:34:56.809135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24235 11:34:56.848745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24237 11:34:56.849214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24238 11:34:56.888016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24239 11:34:56.888450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24241 11:34:56.927767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24243 11:34:56.928250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24244 11:34:56.966769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24246 11:34:56.967219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24247 11:34:57.005095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24249 11:34:57.005564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24250 11:34:57.057491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24251 11:34:57.057942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24253 11:34:57.105731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24254 11:34:57.106172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24256 11:34:57.140236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24258 11:34:57.140702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24259 11:34:57.175206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24261 11:34:57.175690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24262 11:34:57.222313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24263 11:34:57.222735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24265 11:34:57.263734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24266 11:34:57.264168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24268 11:34:57.303698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24269 11:34:57.304131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24271 11:34:57.340375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24273 11:34:57.340831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24274 11:34:57.383727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24275 11:34:57.384151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24277 11:34:57.419757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24278 11:34:57.420190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24280 11:34:57.453242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24281 11:34:57.453683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24283 11:34:57.492384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24285 11:34:57.492875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24286 11:34:57.539384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24287 11:34:57.539787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24289 11:34:57.574600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24291 11:34:57.575066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24292 11:34:57.621378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24293 11:34:57.621804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24295 11:34:57.661258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24296 11:34:57.661696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24298 11:34:57.707211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24299 11:34:57.707673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24301 11:34:57.787850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24303 11:34:57.788313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24304 11:34:57.833984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24305 11:34:57.834434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24307 11:34:57.880313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24308 11:34:57.880757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24310 11:34:57.933892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24311 11:34:57.934315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24313 11:34:57.982692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24315 11:34:57.983068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24316 11:34:58.033273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24318 11:34:58.033785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24319 11:34:58.072659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24320 11:34:58.073087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24322 11:34:58.107648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24324 11:34:58.108126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24325 11:34:58.147458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24327 11:34:58.147930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24328 11:34:58.194204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24329 11:34:58.194618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24331 11:34:58.237072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24332 11:34:58.237497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24334 11:34:58.272393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24336 11:34:58.272859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24337 11:34:58.307745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24338 11:34:58.308174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24340 11:34:58.353174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24341 11:34:58.353561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24343 11:34:58.396920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24344 11:34:58.397385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24346 11:34:58.444111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24347 11:34:58.444544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24349 11:34:58.488137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24350 11:34:58.488555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24352 11:34:58.540031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24353 11:34:58.540458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24355 11:34:58.574570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24357 11:34:58.575048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24358 11:34:58.608654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24360 11:34:58.609114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24361 11:34:58.643296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24362 11:34:58.643713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24364 11:34:58.681091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24365 11:34:58.681495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24367 11:34:58.720092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24369 11:34:58.720550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24370 11:34:58.754044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24372 11:34:58.754523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24373 11:34:58.792764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24374 11:34:58.793180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24376 11:34:58.835235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24377 11:34:58.835663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24379 11:34:58.889722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24380 11:34:58.890158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24382 11:34:58.944371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24383 11:34:58.944798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24385 11:34:58.989207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24386 11:34:58.989641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24388 11:34:59.044611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24389 11:34:59.045175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24391 11:34:59.086099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24392 11:34:59.086569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24394 11:34:59.128342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24395 11:34:59.128893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24397 11:34:59.183892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24398 11:34:59.184285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24400 11:34:59.234007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24401 11:34:59.234465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24403 11:34:59.270930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24405 11:34:59.271430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24406 11:34:59.317021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24407 11:34:59.317444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24409 11:34:59.365404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24410 11:34:59.365807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24412 11:34:59.416555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24413 11:34:59.416947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24415 11:34:59.456358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24416 11:34:59.456742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24418 11:34:59.498101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24419 11:34:59.498495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24421 11:34:59.534263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24422 11:34:59.534693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24424 11:34:59.584311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24425 11:34:59.584734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24427 11:34:59.625613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24429 11:34:59.626079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24430 11:34:59.663216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24431 11:34:59.663649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24433 11:34:59.704643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24435 11:34:59.705093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24436 11:34:59.747124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24437 11:34:59.747570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24439 11:34:59.791399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24440 11:34:59.791832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24442 11:34:59.829529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24443 11:34:59.829918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24445 11:34:59.870445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24447 11:34:59.870839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24448 11:34:59.907042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24449 11:34:59.907468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24451 11:34:59.954589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24453 11:34:59.955053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24454 11:35:00.005546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24455 11:35:00.005974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24457 11:35:00.054064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24458 11:35:00.054487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24460 11:35:00.107707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24461 11:35:00.108149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24463 11:35:00.147965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24464 11:35:00.148389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24466 11:35:00.195748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24468 11:35:00.196204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24469 11:35:00.232949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24470 11:35:00.233340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24472 11:35:00.276706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24474 11:35:00.277172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24475 11:35:00.315850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24476 11:35:00.316260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24478 11:35:00.358767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24480 11:35:00.359261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24481 11:35:00.410409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24482 11:35:00.410851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24484 11:35:00.465716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24486 11:35:00.466197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24487 11:35:00.520691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24489 11:35:00.521156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24490 11:35:00.568831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24492 11:35:00.569288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24493 11:35:00.610769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24495 11:35:00.611337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24496 11:35:00.649723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24497 11:35:00.650129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24499 11:35:00.704750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24500 11:35:00.705162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24502 11:35:00.747480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24504 11:35:00.747894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24505 11:35:00.783953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24506 11:35:00.784381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24508 11:35:00.819116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24509 11:35:00.819536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24511 11:35:00.873448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24512 11:35:00.873865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24514 11:35:00.922811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24516 11:35:00.923284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24517 11:35:00.962179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24518 11:35:00.962585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24520 11:35:01.000270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24521 11:35:01.000680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24523 11:35:01.041726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24524 11:35:01.042153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24526 11:35:01.078480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24528 11:35:01.078948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24529 11:35:01.114492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24531 11:35:01.114980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24532 11:35:01.151850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24534 11:35:01.152312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24535 11:35:01.192419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24536 11:35:01.192798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24538 11:35:01.228374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24539 11:35:01.228809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24541 11:35:01.267856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24542 11:35:01.268297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24544 11:35:01.324025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24545 11:35:01.324467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24547 11:35:01.364419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24549 11:35:01.365037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24550 11:35:01.401305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24551 11:35:01.401677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24553 11:35:01.443250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24555 11:35:01.443733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24556 11:35:01.478774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24558 11:35:01.479241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24559 11:35:01.517302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24561 11:35:01.517779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24562 11:35:01.556405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24563 11:35:01.556828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24565 11:35:01.594027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24566 11:35:01.594445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24568 11:35:01.639676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24569 11:35:01.640125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24571 11:35:01.676780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24572 11:35:01.677217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24574 11:35:01.717853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24575 11:35:01.718284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24577 11:35:01.755761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24578 11:35:01.756185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24580 11:35:01.799924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24581 11:35:01.800347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24583 11:35:01.838903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24584 11:35:01.839349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24586 11:35:01.876354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24588 11:35:01.876820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24589 11:35:01.917800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24590 11:35:01.918267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24592 11:35:01.956908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24593 11:35:01.957327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24595 11:35:01.999486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24597 11:35:01.999958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24598 11:35:02.043931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24599 11:35:02.044358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24601 11:35:02.081531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24602 11:35:02.081985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24604 11:35:02.128518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24605 11:35:02.128913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24607 11:35:02.173553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24608 11:35:02.173987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24610 11:35:02.209675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24612 11:35:02.210146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24613 11:35:02.253399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24614 11:35:02.253864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24616 11:35:02.287868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24617 11:35:02.288306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24619 11:35:02.325539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24620 11:35:02.325996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24622 11:35:02.365611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24624 11:35:02.366089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24625 11:35:02.408702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24626 11:35:02.409081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24628 11:35:02.463716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24629 11:35:02.464145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24631 11:35:02.500435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24633 11:35:02.500897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24634 11:35:02.547425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24635 11:35:02.547855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24637 11:35:02.590739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24639 11:35:02.591206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24640 11:35:02.644986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24641 11:35:02.645407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24643 11:35:02.682001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24644 11:35:02.682445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24646 11:35:02.729975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24647 11:35:02.730400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24649 11:35:02.775079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24650 11:35:02.775509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24652 11:35:02.824523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24653 11:35:02.824943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24655 11:35:02.896240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24656 11:35:02.896655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24658 11:35:02.938522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24659 11:35:02.938935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24661 11:35:02.993936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24662 11:35:02.994478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24664 11:35:03.047328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24665 11:35:03.047760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24667 11:35:03.085422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24668 11:35:03.085850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24670 11:35:03.121937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24671 11:35:03.122369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24673 11:35:03.161613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24674 11:35:03.162055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24676 11:35:03.210046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24677 11:35:03.210506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24679 11:35:03.259572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24680 11:35:03.260000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24682 11:35:03.297117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24684 11:35:03.297888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24685 11:35:03.343315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24686 11:35:03.343906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24688 11:35:03.388461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24690 11:35:03.388924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24691 11:35:03.429792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24693 11:35:03.430280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24694 11:35:03.481980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24695 11:35:03.482496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24697 11:35:03.522276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24699 11:35:03.522748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24700 11:35:03.560770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24701 11:35:03.561187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24703 11:35:03.600672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24705 11:35:03.601133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24706 11:35:03.637940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24707 11:35:03.638384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24709 11:35:03.689233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24710 11:35:03.689712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24712 11:35:03.727662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24713 11:35:03.728118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24715 11:35:03.775666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24716 11:35:03.776073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24718 11:35:03.812110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24719 11:35:03.812537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24721 11:35:03.849265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24722 11:35:03.849689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24724 11:35:03.887387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24725 11:35:03.887841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24727 11:35:03.944674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24728 11:35:03.945089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24730 11:35:03.994695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24732 11:35:03.995137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24733 11:35:04.040453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24734 11:35:04.040882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24736 11:35:04.099612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24737 11:35:04.100039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24739 11:35:04.154157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24740 11:35:04.154584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24742 11:35:04.209987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24744 11:35:04.210449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24745 11:35:04.269398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24747 11:35:04.269876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24748 11:35:04.328602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24749 11:35:04.329030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24751 11:35:04.386262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24752 11:35:04.386695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24754 11:35:04.445204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
24755 11:35:04.445625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
24757 11:35:04.504521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
24758 11:35:04.504922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
24760 11:35:04.563384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
24762 11:35:04.563859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
24763 11:35:04.617481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
24765 11:35:04.617950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
24766 11:35:04.672343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
24768 11:35:04.672809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
24769 11:35:04.727135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
24771 11:35:04.727604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
24772 11:35:04.781371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
24774 11:35:04.781849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
24775 11:35:04.834337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
24776 11:35:04.834752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
24778 11:35:04.888819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
24779 11:35:04.889250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
24781 11:35:04.943502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
24782 11:35:04.943908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
24784 11:35:04.997196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
24785 11:35:04.997613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
24787 11:35:05.042117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
24789 11:35:05.042575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
24790 11:35:05.078663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
24792 11:35:05.079112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
24793 11:35:05.122289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
24794 11:35:05.122712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
24796 11:35:05.157887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
24797 11:35:05.158313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
24799 11:35:05.193930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
24800 11:35:05.194353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
24802 11:35:05.230804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
24804 11:35:05.233815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
24805 11:35:05.276613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
24807 11:35:05.277022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
24808 11:35:05.316150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
24809 11:35:05.316528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
24811 11:35:05.359000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
24812 11:35:05.359380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
24814 11:35:05.397084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
24815 11:35:05.397473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
24817 11:35:05.436447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
24818 11:35:05.436796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
24820 11:35:05.485826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
24821 11:35:05.486244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
24823 11:35:05.533140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
24824 11:35:05.533565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
24826 11:35:05.571830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
24827 11:35:05.572249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
24829 11:35:05.607920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
24830 11:35:05.608334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
24832 11:35:05.644209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
24834 11:35:05.644686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
24835 11:35:05.680976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
24837 11:35:05.681440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
24838 11:35:05.719725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
24839 11:35:05.720106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
24841 11:35:05.757577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
24842 11:35:05.758010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
24844 11:35:05.796531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
24845 11:35:05.796956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
24847 11:35:05.834036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
24848 11:35:05.834459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
24850 11:35:05.885904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
24851 11:35:05.886332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
24853 11:35:05.935876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
24854 11:35:05.936233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
24856 11:35:05.979611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
24857 11:35:05.979986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
24859 11:35:06.016991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
24861 11:35:06.017435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
24862 11:35:06.054505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
24864 11:35:06.054957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
24865 11:35:06.097712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
24866 11:35:06.098093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
24868 11:35:06.140593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
24870 11:35:06.140980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
24871 11:35:06.179174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
24872 11:35:06.179603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
24874 11:35:06.225561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
24875 11:35:06.225993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
24877 11:35:06.264033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
24878 11:35:06.264460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
24880 11:35:06.300141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
24881 11:35:06.300559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
24883 11:35:06.336582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
24884 11:35:06.336998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
24886 11:35:06.375898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
24887 11:35:06.376374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
24889 11:35:06.421160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
24891 11:35:06.421717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
24892 11:35:06.468123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
24893 11:35:06.468588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
24895 11:35:06.525838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
24897 11:35:06.526426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
24898 11:35:06.569051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
24899 11:35:06.569475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
24901 11:35:06.607346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
24902 11:35:06.607870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
24904 11:35:06.647807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
24905 11:35:06.648163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
24907 11:35:06.684007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
24908 11:35:06.684466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
24910 11:35:06.722027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
24912 11:35:06.722493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
24913 11:35:06.760760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
24914 11:35:06.761127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
24916 11:35:06.801349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
24917 11:35:06.801771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
24919 11:35:06.852962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
24921 11:35:06.853393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
24922 11:35:06.901286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
24923 11:35:06.901685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
24925 11:35:06.940403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
24926 11:35:06.940805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
24928 11:35:06.985447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
24929 11:35:06.985889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
24931 11:35:07.036717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
24932 11:35:07.037150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
24934 11:35:07.075125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
24935 11:35:07.075546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
24937 11:35:07.116286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
24938 11:35:07.116708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
24940 11:35:07.174768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
24942 11:35:07.175445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
24943 11:35:07.216698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
24944 11:35:07.217061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
24946 11:35:07.256417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
24947 11:35:07.256821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
24949 11:35:07.292485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
24950 11:35:07.292902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
24952 11:35:07.331417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
24953 11:35:07.331838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
24955 11:35:07.370054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
24957 11:35:07.370526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
24958 11:35:07.405279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
24960 11:35:07.405710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
24961 11:35:07.447592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
24963 11:35:07.448063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
24964 11:35:07.488473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
24965 11:35:07.488886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
24967 11:35:07.528432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
24968 11:35:07.528808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
24970 11:35:07.577069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
24971 11:35:07.577499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
24973 11:35:07.627744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
24975 11:35:07.628309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
24976 11:35:07.667173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
24977 11:35:07.667560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
24979 11:35:07.705416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
24980 11:35:07.705837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
24982 11:35:07.747643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
24983 11:35:07.748080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
24985 11:35:07.795972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
24986 11:35:07.796410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
24988 11:35:07.843527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
24989 11:35:07.843961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
24991 11:35:07.897808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
24992 11:35:07.898260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
24994 11:35:07.938272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
24995 11:35:07.938696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
24997 11:35:08.012102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
24999 11:35:08.012564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25000 11:35:08.053077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25001 11:35:08.053636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25003 11:35:08.091554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25005 11:35:08.092219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25006 11:35:08.135881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25007 11:35:08.136314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25009 11:35:08.176139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25010 11:35:08.176699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25012 11:35:08.213315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25013 11:35:08.213874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25015 11:35:08.265469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25016 11:35:08.265964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25018 11:35:08.303936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25020 11:35:08.304411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25021 11:35:08.342159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25022 11:35:08.342594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25024 11:35:08.381524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25025 11:35:08.381950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25027 11:35:08.421820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25028 11:35:08.422250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25030 11:35:08.471605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25031 11:35:08.471992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25033 11:35:08.521717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25035 11:35:08.522214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25036 11:35:08.559982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25037 11:35:08.560424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25039 11:35:08.616383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25040 11:35:08.616806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25042 11:35:08.655631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25043 11:35:08.656057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25045 11:35:08.694158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25046 11:35:08.694598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25048 11:35:08.738720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25050 11:35:08.739188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25051 11:35:08.777292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25052 11:35:08.777687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25054 11:35:08.816682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25055 11:35:08.817128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25057 11:35:08.855499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25058 11:35:08.855932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25060 11:35:08.893841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25062 11:35:08.894292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25063 11:35:08.937520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25065 11:35:08.937984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25066 11:35:08.983469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25068 11:35:08.983935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25069 11:35:09.020669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25070 11:35:09.021089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25072 11:35:09.057513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25074 11:35:09.058008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25075 11:35:09.094124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25076 11:35:09.094526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25078 11:35:09.135116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25079 11:35:09.135546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25081 11:35:09.180074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25082 11:35:09.180513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25084 11:35:09.221583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25085 11:35:09.222062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25087 11:35:09.260959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25088 11:35:09.261344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25090 11:35:09.316011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25091 11:35:09.316434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25093 11:35:09.365989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25094 11:35:09.366433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25096 11:35:09.406777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25098 11:35:09.407244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25099 11:35:09.449474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25100 11:35:09.449910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25102 11:35:09.493553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25103 11:35:09.493981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25105 11:35:09.538815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25107 11:35:09.539290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25108 11:35:09.577899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25109 11:35:09.578326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25111 11:35:09.622785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25113 11:35:09.623370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25114 11:35:09.659942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25115 11:35:09.660362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25117 11:35:09.701068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25118 11:35:09.701487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25120 11:35:09.750680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25122 11:35:09.751480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25123 11:35:09.796942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25124 11:35:09.797403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25126 11:35:09.837069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25127 11:35:09.837460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25129 11:35:09.884619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25130 11:35:09.885046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25132 11:35:09.930194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25133 11:35:09.930624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25135 11:35:09.969296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25137 11:35:09.969776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25138 11:35:10.009431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25140 11:35:10.009773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25141 11:35:10.050168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25142 11:35:10.050583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25144 11:35:10.092631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25145 11:35:10.093049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25147 11:35:10.131039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25148 11:35:10.131443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25150 11:35:10.178364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25151 11:35:10.178795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25153 11:35:10.227400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25154 11:35:10.227791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25156 11:35:10.277177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25157 11:35:10.277598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25159 11:35:10.326637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25161 11:35:10.327097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25162 11:35:10.371868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25163 11:35:10.372275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25165 11:35:10.409779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25166 11:35:10.410187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25168 11:35:10.450175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25169 11:35:10.450539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25171 11:35:10.498082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25172 11:35:10.498396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25174 11:35:10.554457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25176 11:35:10.554918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25177 11:35:10.599178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25178 11:35:10.599559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25180 11:35:10.638564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25182 11:35:10.639048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25183 11:35:10.687108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25184 11:35:10.687472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25186 11:35:10.724972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25187 11:35:10.725371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25189 11:35:10.764111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25191 11:35:10.764580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25192 11:35:10.809704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25193 11:35:10.810051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25195 11:35:10.857365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25197 11:35:10.858094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25198 11:35:10.905295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25199 11:35:10.905762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25201 11:35:10.947761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25202 11:35:10.948239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25204 11:35:10.985431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25205 11:35:10.985949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25207 11:35:11.041173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25208 11:35:11.041710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25210 11:35:11.087178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25212 11:35:11.087897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25213 11:35:11.141011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25214 11:35:11.141522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25216 11:35:11.189781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25217 11:35:11.190196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25219 11:35:11.228748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25220 11:35:11.229162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25222 11:35:11.273119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25223 11:35:11.273488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25225 11:35:11.313475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25226 11:35:11.313880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25228 11:35:11.365388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25229 11:35:11.365835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25231 11:35:11.420244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25232 11:35:11.420629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25234 11:35:11.475369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25236 11:35:11.475823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25237 11:35:11.530251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25238 11:35:11.530665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25240 11:35:11.573299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25242 11:35:11.573674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25243 11:35:11.611471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25245 11:35:11.611864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25246 11:35:11.649559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25247 11:35:11.650042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25249 11:35:11.691461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25250 11:35:11.691865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25252 11:35:11.736859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25254 11:35:11.737537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25255 11:35:11.775702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25257 11:35:11.776159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25258 11:35:11.816319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25260 11:35:11.816690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25261 11:35:11.852275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25262 11:35:11.852602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25264 11:35:11.896594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25266 11:35:11.897045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25267 11:35:11.933742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25268 11:35:11.934155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25270 11:35:11.975561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25271 11:35:11.975951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25273 11:35:12.016938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25275 11:35:12.017545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25276 11:35:12.054036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25277 11:35:12.054445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25279 11:35:12.095334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25280 11:35:12.095769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25282 11:35:12.132878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25284 11:35:12.133261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25285 11:35:12.169950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25286 11:35:12.170376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25288 11:35:12.209393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25289 11:35:12.209830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25291 11:35:12.249213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25293 11:35:12.249685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25294 11:35:12.288844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25295 11:35:12.289282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25297 11:35:12.327764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25298 11:35:12.328189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25300 11:35:12.382812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25302 11:35:12.383223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25303 11:35:12.423826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25304 11:35:12.424263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25306 11:35:12.468734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25308 11:35:12.469177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25309 11:35:12.515734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25310 11:35:12.516151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25312 11:35:12.570524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25314 11:35:12.570988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25315 11:35:12.607578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25316 11:35:12.607982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25318 11:35:12.647997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25320 11:35:12.648427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25321 11:35:12.691833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25322 11:35:12.692258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25324 11:35:12.738675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25326 11:35:12.739096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25327 11:35:12.786160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25329 11:35:12.786635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25330 11:35:12.827793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25331 11:35:12.828228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25333 11:35:12.874837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25335 11:35:12.875312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25336 11:35:12.916477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25337 11:35:12.916860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25339 11:35:12.961708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25341 11:35:12.962338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25342 11:35:13.003591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25343 11:35:13.004147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25345 11:35:13.043350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25346 11:35:13.043774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25348 11:35:13.088005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25350 11:35:13.088386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25351 11:35:13.145821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25352 11:35:13.146243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25354 11:35:13.194252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25356 11:35:13.194739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25357 11:35:13.236937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25358 11:35:13.237338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25360 11:35:13.292465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25361 11:35:13.292880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25363 11:35:13.339317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25365 11:35:13.339790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25366 11:35:13.376747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25367 11:35:13.377164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25369 11:35:13.412914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25370 11:35:13.413460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25372 11:35:13.450454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25374 11:35:13.450986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25375 11:35:13.496178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25377 11:35:13.496706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25378 11:35:13.542299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25380 11:35:13.542781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25381 11:35:13.589577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25383 11:35:13.590054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25384 11:35:13.627373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25385 11:35:13.627818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25387 11:35:13.668188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25388 11:35:13.668591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25390 11:35:13.704682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25392 11:35:13.705147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25393 11:35:13.742235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25395 11:35:13.742716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25396 11:35:13.780736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25397 11:35:13.781224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25399 11:35:13.824960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25401 11:35:13.825453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25402 11:35:13.865716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25403 11:35:13.866129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25405 11:35:13.903794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25406 11:35:13.904246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25408 11:35:13.955634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25409 11:35:13.956061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25411 11:35:13.992883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25412 11:35:13.993333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25414 11:35:14.033279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25415 11:35:14.033684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25417 11:35:14.078657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25419 11:35:14.079124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25420 11:35:14.115493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25421 11:35:14.115891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25423 11:35:14.152417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25424 11:35:14.152844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25426 11:35:14.188982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25427 11:35:14.189395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25429 11:35:14.225084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25430 11:35:14.225468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25432 11:35:14.261313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25433 11:35:14.261736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25435 11:35:14.298257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25436 11:35:14.298690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25438 11:35:14.336980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25439 11:35:14.337402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25441 11:35:14.383601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25442 11:35:14.384022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25444 11:35:14.419858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25446 11:35:14.420326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25447 11:35:14.456153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25448 11:35:14.456572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25450 11:35:14.501707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25451 11:35:14.502160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25453 11:35:14.548657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25454 11:35:14.549085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25456 11:35:14.596109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25457 11:35:14.596533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25459 11:35:14.644116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25460 11:35:14.644541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25462 11:35:14.684089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25464 11:35:14.684847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25465 11:35:14.724476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25466 11:35:14.724924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25468 11:35:14.766149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25470 11:35:14.766631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25471 11:35:14.811625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25472 11:35:14.812052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25474 11:35:14.853191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25476 11:35:14.853662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25477 11:35:14.894681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25479 11:35:14.895208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25480 11:35:14.934088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25481 11:35:14.934519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25483 11:35:14.970063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25484 11:35:14.970490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25486 11:35:15.006007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25487 11:35:15.006432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25489 11:35:15.057642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25491 11:35:15.058118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25492 11:35:15.100846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25494 11:35:15.101302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25495 11:35:15.152493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25496 11:35:15.152905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25498 11:35:15.192811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25499 11:35:15.193239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25501 11:35:15.241460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25502 11:35:15.241911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25504 11:35:15.289245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25505 11:35:15.289678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25507 11:35:15.330295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25508 11:35:15.330720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25510 11:35:15.378289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25511 11:35:15.378723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25513 11:35:15.420261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25515 11:35:15.420731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25516 11:35:15.458198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25518 11:35:15.458683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25519 11:35:15.502197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25520 11:35:15.502642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25522 11:35:15.551224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25523 11:35:15.551656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25525 11:35:15.588221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25526 11:35:15.588638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25528 11:35:15.625300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25529 11:35:15.625733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25531 11:35:15.671818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25532 11:35:15.672236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25534 11:35:15.708212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25536 11:35:15.708678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25537 11:35:15.744523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25538 11:35:15.744965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25540 11:35:15.780391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25541 11:35:15.780846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25543 11:35:15.817623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25544 11:35:15.818081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25546 11:35:15.854242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25547 11:35:15.854667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25549 11:35:15.891326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25550 11:35:15.891778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25552 11:35:15.937540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25553 11:35:15.937966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25555 11:35:15.975395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25557 11:35:15.975955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25558 11:35:16.012791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25559 11:35:16.013136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25561 11:35:16.052629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25562 11:35:16.053053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25564 11:35:16.106063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25565 11:35:16.106509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25567 11:35:16.160670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25569 11:35:16.161130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25570 11:35:16.209221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25571 11:35:16.209643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25573 11:35:16.257369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25575 11:35:16.258047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25576 11:35:16.307351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25578 11:35:16.308076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25579 11:35:16.347097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25580 11:35:16.347512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25582 11:35:16.369412 <47>[ 296.800697] systemd-journald[105]: Sent WATCHDOG=1 notification.
25583 11:35:16.392590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25585 11:35:16.393055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25586 11:35:16.449907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25587 11:35:16.450318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25589 11:35:16.501511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25591 11:35:16.501897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25592 11:35:16.543902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25593 11:35:16.544400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25595 11:35:16.582474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25597 11:35:16.582871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25598 11:35:16.625283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25600 11:35:16.625675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25601 11:35:16.664695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25602 11:35:16.665027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25604 11:35:16.705555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25605 11:35:16.705963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25607 11:35:16.744865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25608 11:35:16.745246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25610 11:35:16.784026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25611 11:35:16.784456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25613 11:35:16.820573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25615 11:35:16.821285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25616 11:35:16.855993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25618 11:35:16.856463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25619 11:35:16.893320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25620 11:35:16.893755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25622 11:35:16.929667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25623 11:35:16.930087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25625 11:35:16.968321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25626 11:35:16.968746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25628 11:35:17.010757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25630 11:35:17.011251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25631 11:35:17.056911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25632 11:35:17.057362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25634 11:35:17.100872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25635 11:35:17.101268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25637 11:35:17.138221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25638 11:35:17.138651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25640 11:35:17.184624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25642 11:35:17.185089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25643 11:35:17.227302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25644 11:35:17.227744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25646 11:35:17.267706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25648 11:35:17.268177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25649 11:35:17.303332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25650 11:35:17.303733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25652 11:35:17.337977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25653 11:35:17.338427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25655 11:35:17.374720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25657 11:35:17.375329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25658 11:35:17.415959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25659 11:35:17.416389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25661 11:35:17.452865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25662 11:35:17.453263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25664 11:35:17.489862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25665 11:35:17.490306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25667 11:35:17.537345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25668 11:35:17.537766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25670 11:35:17.589010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25671 11:35:17.589434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25673 11:35:17.624431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25674 11:35:17.624910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25676 11:35:17.661285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25678 11:35:17.661778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25679 11:35:17.698684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25681 11:35:17.699142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25682 11:35:17.738861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25684 11:35:17.739574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25685 11:35:17.791671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25686 11:35:17.792092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25688 11:35:17.834725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25690 11:35:17.835188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25691 11:35:17.883131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25692 11:35:17.883576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25694 11:35:17.924726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25695 11:35:17.925151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25697 11:35:17.971725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25699 11:35:17.972192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25700 11:35:18.012544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25701 11:35:18.013129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25703 11:35:18.049620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25704 11:35:18.050082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25706 11:35:18.088921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25707 11:35:18.089353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25709 11:35:18.131413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25710 11:35:18.131819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25712 11:35:18.171249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25713 11:35:18.171682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25715 11:35:18.232873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25716 11:35:18.233297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25718 11:35:18.286445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25720 11:35:18.286924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25721 11:35:18.335813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25722 11:35:18.336255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25724 11:35:18.390020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25725 11:35:18.390453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25727 11:35:18.431657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25729 11:35:18.432124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25730 11:35:18.474124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25732 11:35:18.474603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25733 11:35:18.512048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25734 11:35:18.512469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25736 11:35:18.551741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25738 11:35:18.552321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25739 11:35:18.592552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25740 11:35:18.592976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25742 11:35:18.642682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25744 11:35:18.643142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25745 11:35:18.696638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25746 11:35:18.697197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25748 11:35:18.752570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25750 11:35:18.753226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25751 11:35:18.809165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25752 11:35:18.809590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25754 11:35:18.854678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
25756 11:35:18.855343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25757 11:35:18.913422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
25758 11:35:18.913795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
25760 11:35:18.952764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
25761 11:35:18.953099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
25763 11:35:18.988605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
25765 11:35:18.989072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
25766 11:35:19.025453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
25767 11:35:19.025913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
25769 11:35:19.062638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
25771 11:35:19.063112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
25772 11:35:19.099061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
25774 11:35:19.099544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
25775 11:35:19.148041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
25777 11:35:19.148510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
25778 11:35:19.184983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
25779 11:35:19.185410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
25781 11:35:19.224203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
25782 11:35:19.224618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
25784 11:35:19.266538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
25786 11:35:19.267112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
25787 11:35:19.315859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
25788 11:35:19.316295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
25790 11:35:19.367641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
25792 11:35:19.368118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
25793 11:35:19.421471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
25794 11:35:19.421913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
25796 11:35:19.456039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
25797 11:35:19.456441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
25799 11:35:19.491453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
25800 11:35:19.491904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
25802 11:35:19.530019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
25803 11:35:19.530426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
25805 11:35:19.571359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
25806 11:35:19.571768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
25808 11:35:19.607716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
25809 11:35:19.608133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
25811 11:35:19.645153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
25813 11:35:19.645623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
25814 11:35:19.683814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
25815 11:35:19.684254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
25817 11:35:19.720338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
25818 11:35:19.720754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
25820 11:35:19.759056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
25821 11:35:19.759510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
25823 11:35:19.801251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
25824 11:35:19.801682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
25826 11:35:19.846287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
25827 11:35:19.846727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
25829 11:35:19.895896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
25830 11:35:19.896331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
25832 11:35:19.943385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
25833 11:35:19.943807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
25835 11:35:19.981211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
25836 11:35:19.981673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
25838 11:35:20.018623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
25840 11:35:20.019091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
25841 11:35:20.061418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
25842 11:35:20.061874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
25844 11:35:20.107648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
25845 11:35:20.108072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
25847 11:35:20.156063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
25848 11:35:20.156488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
25850 11:35:20.195218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
25852 11:35:20.195693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
25853 11:35:20.235314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
25855 11:35:20.235799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
25856 11:35:20.273256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
25858 11:35:20.273754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
25859 11:35:20.313719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
25860 11:35:20.314156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
25862 11:35:20.354090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
25863 11:35:20.354454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
25865 11:35:20.403135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
25866 11:35:20.403525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
25868 11:35:20.442002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
25870 11:35:20.442473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
25871 11:35:20.486233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
25873 11:35:20.486713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
25874 11:35:20.530649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
25876 11:35:20.531072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
25877 11:35:20.572733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
25878 11:35:20.573156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
25880 11:35:20.613416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
25881 11:35:20.613849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
25883 11:35:20.653952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
25884 11:35:20.654316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
25886 11:35:20.695111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
25888 11:35:20.695549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
25889 11:35:20.744920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
25890 11:35:20.745344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
25892 11:35:20.780838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
25894 11:35:20.781299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
25895 11:35:20.819169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
25896 11:35:20.819600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
25898 11:35:20.858070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
25899 11:35:20.858491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
25901 11:35:20.905602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
25903 11:35:20.906091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
25904 11:35:20.950011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
25906 11:35:20.950472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
25907 11:35:20.984668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
25908 11:35:20.985083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
25910 11:35:21.019439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
25911 11:35:21.019871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
25913 11:35:21.064491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
25914 11:35:21.064920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
25916 11:35:21.104419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
25917 11:35:21.104851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
25919 11:35:21.142642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
25921 11:35:21.143116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
25922 11:35:21.182073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
25923 11:35:21.182466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
25925 11:35:21.240936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
25927 11:35:21.241399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
25928 11:35:21.296724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
25929 11:35:21.297112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
25931 11:35:21.352524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
25932 11:35:21.352978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
25934 11:35:21.408730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
25935 11:35:21.409099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
25937 11:35:21.462349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
25938 11:35:21.462786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
25940 11:35:21.498228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
25942 11:35:21.498664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
25943 11:35:21.533831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
25944 11:35:21.534272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
25946 11:35:21.572997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
25947 11:35:21.573376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
25949 11:35:21.616182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
25950 11:35:21.616567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
25952 11:35:21.653242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
25953 11:35:21.653638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
25955 11:35:21.707260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
25957 11:35:21.707724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
25958 11:35:21.744229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
25959 11:35:21.744595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
25961 11:35:21.789601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
25962 11:35:21.790177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
25964 11:35:21.827785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
25965 11:35:21.828216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
25967 11:35:21.869291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
25968 11:35:21.869690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
25970 11:35:21.915814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
25971 11:35:21.916241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
25973 11:35:21.955476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
25974 11:35:21.955912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
25976 11:35:21.993096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
25977 11:35:21.993532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
25979 11:35:22.029557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
25980 11:35:22.029984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
25982 11:35:22.070666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
25984 11:35:22.071090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
25985 11:35:22.107431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
25986 11:35:22.107841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
25988 11:35:22.144682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
25989 11:35:22.145027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
25991 11:35:22.186263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
25993 11:35:22.186676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
25994 11:35:22.225802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
25995 11:35:22.226210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
25997 11:35:22.268612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
25998 11:35:22.268995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26000 11:35:22.324645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26001 11:35:22.325089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26003 11:35:22.373902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26004 11:35:22.374318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26006 11:35:22.411539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26007 11:35:22.411897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26009 11:35:22.459672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26011 11:35:22.460151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26012 11:35:22.498802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26014 11:35:22.499268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26015 11:35:22.551446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26016 11:35:22.551968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26018 11:35:22.607552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26020 11:35:22.608012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26021 11:35:22.646734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26023 11:35:22.647353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26024 11:35:22.703958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26025 11:35:22.704411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26027 11:35:22.744567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26028 11:35:22.745013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26030 11:35:22.779630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26032 11:35:22.780099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26033 11:35:22.817373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26035 11:35:22.817850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26036 11:35:22.864237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26037 11:35:22.864659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26039 11:35:22.906345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26041 11:35:22.906815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26042 11:35:22.949532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26044 11:35:22.950009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26045 11:35:23.007377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26046 11:35:23.007800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26048 11:35:23.060931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26049 11:35:23.061352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26051 11:35:23.097182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26052 11:35:23.097601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26054 11:35:23.140351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26055 11:35:23.140779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26057 11:35:23.189058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26058 11:35:23.189503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26060 11:35:23.233213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26061 11:35:23.233665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26063 11:35:23.288660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26064 11:35:23.289091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26066 11:35:23.368742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26067 11:35:23.369167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26069 11:35:23.424436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26070 11:35:23.424825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26072 11:35:23.481527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26074 11:35:23.482018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26075 11:35:23.538742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26077 11:35:23.539592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26078 11:35:23.594807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26080 11:35:23.595277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26081 11:35:23.633374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26082 11:35:23.633814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26084 11:35:23.677606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26085 11:35:23.678047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26087 11:35:23.728469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26089 11:35:23.728959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26090 11:35:23.772430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26091 11:35:23.772799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26093 11:35:23.818254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26094 11:35:23.818752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26096 11:35:23.855698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26097 11:35:23.856138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26099 11:35:23.903914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26100 11:35:23.904334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26102 11:35:23.942241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26103 11:35:23.942742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26105 11:35:23.983897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26107 11:35:23.984361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26108 11:35:24.019754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26110 11:35:24.020141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26111 11:35:24.056715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26113 11:35:24.057335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26114 11:35:24.092510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26116 11:35:24.093300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26117 11:35:24.128569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26118 11:35:24.129058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26120 11:35:24.173135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26121 11:35:24.173581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26123 11:35:24.208865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26125 11:35:24.209330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26126 11:35:24.244854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26127 11:35:24.245292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26129 11:35:24.281687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26130 11:35:24.282108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26132 11:35:24.319736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26133 11:35:24.320165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26135 11:35:24.360799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26137 11:35:24.361384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26138 11:35:24.405290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26139 11:35:24.405684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26141 11:35:24.455321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26142 11:35:24.455767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26144 11:35:24.504014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26145 11:35:24.504439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26147 11:35:24.551825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26149 11:35:24.552304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26150 11:35:24.600553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26152 11:35:24.601037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26153 11:35:24.642253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26154 11:35:24.642675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26156 11:35:24.678523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26158 11:35:24.679225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26159 11:35:24.722468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26161 11:35:24.723030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26162 11:35:24.780540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26163 11:35:24.780926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26165 11:35:24.819767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26166 11:35:24.820197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26168 11:35:24.858632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26170 11:35:24.859095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26171 11:35:24.893356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26172 11:35:24.893798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26174 11:35:24.932908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26175 11:35:24.933339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26177 11:35:24.968265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26179 11:35:24.968696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26180 11:35:25.003469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26181 11:35:25.003862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26183 11:35:25.042355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26184 11:35:25.042855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26186 11:35:25.093229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26187 11:35:25.093632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26189 11:35:25.133758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26190 11:35:25.134205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26192 11:35:25.173520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26193 11:35:25.174013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26195 11:35:25.213826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26196 11:35:25.214243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26198 11:35:25.253271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26199 11:35:25.253752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26201 11:35:25.295281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26202 11:35:25.295723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26204 11:35:25.332864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26205 11:35:25.333301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26207 11:35:25.374263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26208 11:35:25.374719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26210 11:35:25.420358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26211 11:35:25.420789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26213 11:35:25.465725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26214 11:35:25.466155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26216 11:35:25.503141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26218 11:35:25.503544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26219 11:35:25.540116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26221 11:35:25.540548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26222 11:35:25.579043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26224 11:35:25.579509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26225 11:35:25.634565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26227 11:35:25.635102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26228 11:35:25.676744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26229 11:35:25.677123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26231 11:35:25.721107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26232 11:35:25.721621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26234 11:35:25.765778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26235 11:35:25.766208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26237 11:35:25.808726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26238 11:35:25.809302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26240 11:35:25.857880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26241 11:35:25.858260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26243 11:35:25.895296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26244 11:35:25.895726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26246 11:35:25.930640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26248 11:35:25.931095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26249 11:35:25.972426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26251 11:35:25.972895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26252 11:35:26.013040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26253 11:35:26.013462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26255 11:35:26.057087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26256 11:35:26.057494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26258 11:35:26.094634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26260 11:35:26.095113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26261 11:35:26.129415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26262 11:35:26.129857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26264 11:35:26.176446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26266 11:35:26.176911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26267 11:35:26.211658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26269 11:35:26.212125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26270 11:35:26.248273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26272 11:35:26.248733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26273 11:35:26.286053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26275 11:35:26.286520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26276 11:35:26.321735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26277 11:35:26.322277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26279 11:35:26.356001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26280 11:35:26.356540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26282 11:35:26.401853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26283 11:35:26.402342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26285 11:35:26.450259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26286 11:35:26.450686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26288 11:35:26.494522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26290 11:35:26.494993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26291 11:35:26.529700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26293 11:35:26.530462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26294 11:35:26.564107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26295 11:35:26.564539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26297 11:35:26.613470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26298 11:35:26.614034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26300 11:35:26.650644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26302 11:35:26.651177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26303 11:35:26.696894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26305 11:35:26.697355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26306 11:35:26.737330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26307 11:35:26.737753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26309 11:35:26.773525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26310 11:35:26.773948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26312 11:35:26.810342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26313 11:35:26.810774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26315 11:35:26.849449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26316 11:35:26.849877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26318 11:35:26.887532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26320 11:35:26.888018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26321 11:35:26.926138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26323 11:35:26.926617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26324 11:35:26.964539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26326 11:35:26.965014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26327 11:35:27.008348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26328 11:35:27.008862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26330 11:35:27.043951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26332 11:35:27.044704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26333 11:35:27.098636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26335 11:35:27.099102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26336 11:35:27.144188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26338 11:35:27.144945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26339 11:35:27.189448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26340 11:35:27.189886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26342 11:35:27.239970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26343 11:35:27.240400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26345 11:35:27.279477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26346 11:35:27.279925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26348 11:35:27.316025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26349 11:35:27.316454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26351 11:35:27.353105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26352 11:35:27.353525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26354 11:35:27.390165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26355 11:35:27.390561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26357 11:35:27.434531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26359 11:35:27.434994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26360 11:35:27.483727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26361 11:35:27.484111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26363 11:35:27.524280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26364 11:35:27.524771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26366 11:35:27.561801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26367 11:35:27.562236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26369 11:35:27.615705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26370 11:35:27.616154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26372 11:35:27.658729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26374 11:35:27.659531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26375 11:35:27.714186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26376 11:35:27.714615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26378 11:35:27.760100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26380 11:35:27.760513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26381 11:35:27.801865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26382 11:35:27.802299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26384 11:35:27.845189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26385 11:35:27.845611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26387 11:35:27.897324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26388 11:35:27.897680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26390 11:35:27.950104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26391 11:35:27.950756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26393 11:35:28.011649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26395 11:35:28.012130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26396 11:35:28.063570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26397 11:35:28.064023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26399 11:35:28.113181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26400 11:35:28.113621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26402 11:35:28.164946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26404 11:35:28.165406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26405 11:35:28.221689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26407 11:35:28.222062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26408 11:35:28.267096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26409 11:35:28.267529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26411 11:35:28.310017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26413 11:35:28.310469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26414 11:35:28.350236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26415 11:35:28.350638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26417 11:35:28.394094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26419 11:35:28.394589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26420 11:35:28.456842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26422 11:35:28.457282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26423 11:35:28.507921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26424 11:35:28.508315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26426 11:35:28.552459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26428 11:35:28.552914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26429 11:35:28.592947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26431 11:35:28.593373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26432 11:35:28.632646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26433 11:35:28.633217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26435 11:35:28.672474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26436 11:35:28.672909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26438 11:35:28.716096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26439 11:35:28.716544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26441 11:35:28.751852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26442 11:35:28.752277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26444 11:35:28.789022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26445 11:35:28.789432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26447 11:35:28.840729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26449 11:35:28.841125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26450 11:35:28.882067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26452 11:35:28.882510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26453 11:35:28.927664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26454 11:35:28.928063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26456 11:35:28.982550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26458 11:35:28.982971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26459 11:35:29.032229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26460 11:35:29.032651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26462 11:35:29.076949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26463 11:35:29.077444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26465 11:35:29.118588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26467 11:35:29.119138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26468 11:35:29.155561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26469 11:35:29.156019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26471 11:35:29.194260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26472 11:35:29.194714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26474 11:35:29.231782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26475 11:35:29.232202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26477 11:35:29.284745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26479 11:35:29.285503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26480 11:35:29.332361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26481 11:35:29.332792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26483 11:35:29.369441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26484 11:35:29.369883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26486 11:35:29.417936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26487 11:35:29.418392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26489 11:35:29.466395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26491 11:35:29.466870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26492 11:35:29.505304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26493 11:35:29.505697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26495 11:35:29.541111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26497 11:35:29.541588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26498 11:35:29.587955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26499 11:35:29.588527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26501 11:35:29.628024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26502 11:35:29.628454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26504 11:35:29.681190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26506 11:35:29.681972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26507 11:35:29.721740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26509 11:35:29.722219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26510 11:35:29.767926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26511 11:35:29.768322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26513 11:35:29.817760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26514 11:35:29.818218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26516 11:35:29.852210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26517 11:35:29.852657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26519 11:35:29.888069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26520 11:35:29.888451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26522 11:35:29.928587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26523 11:35:29.929022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26525 11:35:29.969110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26526 11:35:29.969581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26528 11:35:30.006974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26529 11:35:30.007541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26531 11:35:30.049852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26533 11:35:30.050345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26534 11:35:30.085425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26535 11:35:30.085857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26537 11:35:30.126083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26538 11:35:30.126501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26540 11:35:30.163697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26541 11:35:30.164137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26543 11:35:30.202217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26545 11:35:30.202692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26546 11:35:30.236431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26547 11:35:30.236883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26549 11:35:30.273314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26551 11:35:30.274086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26552 11:35:30.316995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26554 11:35:30.317479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26555 11:35:30.371824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26556 11:35:30.372302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26558 11:35:30.408369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26559 11:35:30.408921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26561 11:35:30.447520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26563 11:35:30.447987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26564 11:35:30.485005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26565 11:35:30.485421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26567 11:35:30.521578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26569 11:35:30.522222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26570 11:35:30.561614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26571 11:35:30.562090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26573 11:35:30.595982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26574 11:35:30.596424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26576 11:35:30.629768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26577 11:35:30.630214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26579 11:35:30.663950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26581 11:35:30.664443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26582 11:35:30.700990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26584 11:35:30.701470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26585 11:35:30.742117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26586 11:35:30.742545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26588 11:35:30.780900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26589 11:35:30.781311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26591 11:35:30.824241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26592 11:35:30.824683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26594 11:35:30.861094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26596 11:35:30.861567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26597 11:35:30.896027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26599 11:35:30.896413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26600 11:35:30.934245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26602 11:35:30.934738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26603 11:35:30.976829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26605 11:35:30.977188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26606 11:35:31.012383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26607 11:35:31.012823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26609 11:35:31.045150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26611 11:35:31.045577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26612 11:35:31.091001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26614 11:35:31.091467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26615 11:35:31.146162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26617 11:35:31.146822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26618 11:35:31.191031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26619 11:35:31.191549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26621 11:35:31.232663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26622 11:35:31.233206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26624 11:35:31.285089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26625 11:35:31.285535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26627 11:35:31.333748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26628 11:35:31.334202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26630 11:35:31.373661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26631 11:35:31.374096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26633 11:35:31.414370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26635 11:35:31.414834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26636 11:35:31.459002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26637 11:35:31.459436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26639 11:35:31.493683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26641 11:35:31.494149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26642 11:35:31.533214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26643 11:35:31.533711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26645 11:35:31.577303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26646 11:35:31.577755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26648 11:35:31.612512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26649 11:35:31.613023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26651 11:35:31.645806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26652 11:35:31.646389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26654 11:35:31.679238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26656 11:35:31.680037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26657 11:35:31.720949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26659 11:35:31.721713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26660 11:35:31.755344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26661 11:35:31.755759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26663 11:35:31.790151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26665 11:35:31.790629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26666 11:35:31.834024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26667 11:35:31.834436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26669 11:35:31.877782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26670 11:35:31.878216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26672 11:35:31.915388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26673 11:35:31.915814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26675 11:35:31.949235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26676 11:35:31.949704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26678 11:35:31.983904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26679 11:35:31.984333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26681 11:35:32.021019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26682 11:35:32.021419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26684 11:35:32.056735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26685 11:35:32.057136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26687 11:35:32.101666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26688 11:35:32.102065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26690 11:35:32.138647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26692 11:35:32.139032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26693 11:35:32.174146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26694 11:35:32.174606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26696 11:35:32.209139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26697 11:35:32.209590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26699 11:35:32.245039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26701 11:35:32.245524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26702 11:35:32.280656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26704 11:35:32.281419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26705 11:35:32.316179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26706 11:35:32.316725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26708 11:35:32.356521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26709 11:35:32.356989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26711 11:35:32.407839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26712 11:35:32.408220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26714 11:35:32.442172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26715 11:35:32.442606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26717 11:35:32.476838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26718 11:35:32.477256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26720 11:35:32.511526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26721 11:35:32.511978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26723 11:35:32.546760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26725 11:35:32.547228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26726 11:35:32.587846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26727 11:35:32.588309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26729 11:35:32.619866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26730 11:35:32.620278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26732 11:35:32.653970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26733 11:35:32.654390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26735 11:35:32.692262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26736 11:35:32.692665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26738 11:35:32.737153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26739 11:35:32.737551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26741 11:35:32.772030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26742 11:35:32.772454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26744 11:35:32.817754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26745 11:35:32.818304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26747 11:35:32.853456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26749 11:35:32.853927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26750 11:35:32.893543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26751 11:35:32.893990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26753 11:35:32.948066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26754 11:35:32.948482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
26756 11:35:32.983020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
26757 11:35:32.983438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
26759 11:35:33.027474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
26760 11:35:33.027901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
26762 11:35:33.070596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
26764 11:35:33.071074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
26765 11:35:33.115828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
26766 11:35:33.116299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
26768 11:35:33.156116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
26769 11:35:33.156553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
26771 11:35:33.201146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
26772 11:35:33.201610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
26774 11:35:33.243211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
26776 11:35:33.243692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
26777 11:35:33.292644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
26778 11:35:33.293127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
26780 11:35:33.345702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
26782 11:35:33.346317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
26783 11:35:33.380080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
26784 11:35:33.380501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
26786 11:35:33.415532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
26787 11:35:33.416024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
26789 11:35:33.459824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
26790 11:35:33.460208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
26792 11:35:33.498560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
26794 11:35:33.499234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
26795 11:35:33.542786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
26797 11:35:33.543484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
26798 11:35:33.601027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
26799 11:35:33.601454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
26801 11:35:33.635355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
26802 11:35:33.635760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
26804 11:35:33.678889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
26806 11:35:33.679550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
26807 11:35:33.716316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
26808 11:35:33.716797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
26810 11:35:33.754152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
26811 11:35:33.754568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
26813 11:35:33.793418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
26814 11:35:33.793858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
26816 11:35:33.833852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
26817 11:35:33.834282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
26819 11:35:33.868578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
26820 11:35:33.869005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
26822 11:35:33.903768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
26823 11:35:33.904201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
26825 11:35:33.939738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
26826 11:35:33.940182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
26828 11:35:33.973833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
26829 11:35:33.974290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
26831 11:35:34.009913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
26833 11:35:34.010549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
26834 11:35:34.045512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
26835 11:35:34.045944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
26837 11:35:34.081586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
26838 11:35:34.082014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
26840 11:35:34.116850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
26842 11:35:34.117314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
26843 11:35:34.150754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
26845 11:35:34.151219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
26846 11:35:34.184544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
26847 11:35:34.184944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
26849 11:35:34.219500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
26850 11:35:34.219916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
26852 11:35:34.258085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
26853 11:35:34.258488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
26855 11:35:34.292397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
26856 11:35:34.292767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
26858 11:35:34.326953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
26859 11:35:34.327514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
26861 11:35:34.363205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
26862 11:35:34.363659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
26864 11:35:34.414251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
26866 11:35:34.414630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
26867 11:35:34.468976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
26868 11:35:34.469377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
26870 11:35:34.519763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
26871 11:35:34.520203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
26873 11:35:34.573551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
26875 11:35:34.573950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
26876 11:35:34.611911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
26877 11:35:34.612338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
26879 11:35:34.649218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
26880 11:35:34.649641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
26882 11:35:34.690173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
26883 11:35:34.690565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
26885 11:35:34.744130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
26886 11:35:34.744560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
26888 11:35:34.781463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
26889 11:35:34.781912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
26891 11:35:34.832342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
26892 11:35:34.832797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
26894 11:35:34.877289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
26895 11:35:34.877690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
26897 11:35:34.918617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
26899 11:35:34.919080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
26900 11:35:34.955721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
26901 11:35:34.956153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
26903 11:35:34.993720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
26904 11:35:34.994122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
26906 11:35:35.035942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
26907 11:35:35.036372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
26909 11:35:35.078151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
26910 11:35:35.078599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
26912 11:35:35.121633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
26913 11:35:35.122138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
26915 11:35:35.160047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
26916 11:35:35.160435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
26918 11:35:35.201857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
26919 11:35:35.202316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
26921 11:35:35.253350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
26922 11:35:35.253760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
26924 11:35:35.300405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
26926 11:35:35.300867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
26927 11:35:35.339040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
26928 11:35:35.339458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
26930 11:35:35.375595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
26931 11:35:35.376068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
26933 11:35:35.411434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
26934 11:35:35.411990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
26936 11:35:35.449572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
26937 11:35:35.450078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
26939 11:35:35.490839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
26941 11:35:35.491312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
26942 11:35:35.527407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
26944 11:35:35.527868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
26945 11:35:35.565220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
26946 11:35:35.565597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
26948 11:35:35.615789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
26950 11:35:35.616216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
26951 11:35:35.662449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
26953 11:35:35.663118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
26954 11:35:35.706149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
26955 11:35:35.706600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
26957 11:35:35.757829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
26958 11:35:35.758410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
26960 11:35:35.810742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
26962 11:35:35.811185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
26963 11:35:35.864699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
26964 11:35:35.865125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
26966 11:35:35.903986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
26968 11:35:35.904459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
26969 11:35:35.943953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
26970 11:35:35.944378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
26972 11:35:35.984925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
26973 11:35:35.985362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
26975 11:35:36.023818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
26976 11:35:36.024223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
26978 11:35:36.065033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
26979 11:35:36.065465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
26981 11:35:36.109028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
26983 11:35:36.109480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
26984 11:35:36.160974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
26985 11:35:36.161390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
26987 11:35:36.212312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
26989 11:35:36.212805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
26990 11:35:36.255124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
26991 11:35:36.255557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
26993 11:35:36.298083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
26994 11:35:36.298500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
26996 11:35:36.352111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
26997 11:35:36.352683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
26999 11:35:36.406124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27000 11:35:36.406595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27002 11:35:36.450283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27003 11:35:36.450730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27005 11:35:36.488761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27006 11:35:36.489193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27008 11:35:36.528966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27009 11:35:36.529388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27011 11:35:36.580583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27012 11:35:36.580961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27014 11:35:36.623855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27015 11:35:36.624282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27017 11:35:36.679792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27018 11:35:36.680170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27020 11:35:36.735613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27021 11:35:36.736023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27023 11:35:36.779777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27024 11:35:36.780335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27026 11:35:36.815382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27027 11:35:36.815808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27029 11:35:36.857372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27031 11:35:36.857816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27032 11:35:36.903598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27034 11:35:36.904017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27035 11:35:36.939778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27036 11:35:36.940178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27038 11:35:36.979395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27040 11:35:36.979862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27041 11:35:37.026634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27043 11:35:37.027105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27044 11:35:37.069604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27045 11:35:37.070038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27047 11:35:37.116385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27049 11:35:37.116803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27050 11:35:37.160582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27051 11:35:37.160969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27053 11:35:37.196898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27054 11:35:37.197395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27056 11:35:37.232073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27057 11:35:37.232556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27059 11:35:37.266264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27061 11:35:37.266738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27062 11:35:37.301363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27063 11:35:37.301749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27065 11:35:37.335798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27066 11:35:37.336228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27068 11:35:37.369022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27069 11:35:37.369448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27071 11:35:37.402722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27073 11:35:37.403148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27074 11:35:37.447139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27075 11:35:37.447564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27077 11:35:37.485894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27078 11:35:37.486322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27080 11:35:37.526018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27081 11:35:37.526441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27083 11:35:37.568209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27084 11:35:37.568628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27086 11:35:37.607763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27087 11:35:37.608193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27089 11:35:37.653403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27090 11:35:37.653856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27092 11:35:37.688941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27093 11:35:37.689375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27095 11:35:37.725644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27096 11:35:37.726070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27098 11:35:37.773215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27099 11:35:37.773641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27101 11:35:37.812955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27103 11:35:37.813438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27104 11:35:37.853598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27105 11:35:37.853995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27107 11:35:37.904947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27108 11:35:37.905364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27110 11:35:37.953287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27111 11:35:37.953684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27113 11:35:37.997283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27114 11:35:37.997697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27116 11:35:38.032336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27117 11:35:38.032752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27119 11:35:38.067704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27120 11:35:38.068128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27122 11:35:38.102590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27124 11:35:38.103018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27125 11:35:38.137228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27126 11:35:38.137621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27128 11:35:38.171035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27130 11:35:38.171490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27131 11:35:38.203694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27132 11:35:38.204104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27134 11:35:38.237300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27136 11:35:38.237977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27137 11:35:38.270932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27138 11:35:38.271358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27140 11:35:38.307056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27141 11:35:38.307538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27143 11:35:38.345243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27145 11:35:38.346008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27146 11:35:38.389987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27147 11:35:38.390530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27149 11:35:38.431882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27150 11:35:38.432385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27152 11:35:38.483904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27154 11:35:38.484328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27155 11:35:38.518161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27156 11:35:38.518589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27158 11:35:38.552038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27159 11:35:38.552454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27161 11:35:38.592149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27162 11:35:38.592529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27164 11:35:38.626212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27165 11:35:38.626627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27167 11:35:38.660138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27168 11:35:38.660548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27170 11:35:38.720137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27171 11:35:38.720516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27173 11:35:38.757027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27175 11:35:38.757494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27176 11:35:38.797174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27177 11:35:38.797598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27179 11:35:38.842659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27181 11:35:38.843074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27182 11:35:38.883126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27183 11:35:38.883706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27185 11:35:38.926023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27186 11:35:38.926445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27188 11:35:38.976098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27189 11:35:38.976468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27191 11:35:39.023250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27192 11:35:39.023693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27194 11:35:39.062997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27195 11:35:39.063489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27197 11:35:39.100754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27198 11:35:39.101274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27200 11:35:39.138691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27202 11:35:39.139171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27203 11:35:39.177456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27204 11:35:39.177890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27206 11:35:39.224996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27207 11:35:39.225432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27209 11:35:39.264750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27210 11:35:39.265191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27212 11:35:39.301114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27213 11:35:39.301547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27215 11:35:39.345310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27216 11:35:39.345679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27218 11:35:39.386484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27220 11:35:39.386957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27221 11:35:39.437937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27222 11:35:39.438361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27224 11:35:39.468502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27226 11:35:39.469035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27227 11:35:39.504542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27229 11:35:39.504953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27230 11:35:39.538501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27232 11:35:39.541141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27233 11:35:39.577114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27234 11:35:39.577567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27236 11:35:39.611163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27237 11:35:39.611601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27239 11:35:39.648708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27240 11:35:39.649110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27242 11:35:39.682996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27243 11:35:39.683412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27245 11:35:39.718029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27246 11:35:39.718455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27248 11:35:39.754011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27250 11:35:39.754562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27251 11:35:39.793849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27252 11:35:39.794268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27254 11:35:39.828009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27255 11:35:39.828458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27257 11:35:39.879804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27258 11:35:39.880250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27260 11:35:39.936764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27261 11:35:39.937196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27263 11:35:39.973208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27265 11:35:39.973683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27266 11:35:40.009665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27267 11:35:40.010084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27269 11:35:40.044865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27270 11:35:40.045282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27272 11:35:40.082851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27273 11:35:40.083302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27275 11:35:40.122264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27276 11:35:40.122673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27278 11:35:40.176921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27279 11:35:40.177356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27281 11:35:40.230589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27282 11:35:40.231018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27284 11:35:40.275402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27285 11:35:40.275824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27287 11:35:40.323681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27288 11:35:40.324068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27290 11:35:40.365021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27291 11:35:40.365454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27293 11:35:40.417367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27295 11:35:40.418194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27296 11:35:40.458787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27298 11:35:40.459257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27299 11:35:40.514775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27301 11:35:40.515200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27302 11:35:40.557730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27303 11:35:40.558176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27305 11:35:40.601314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27306 11:35:40.601747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27308 11:35:40.648576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27309 11:35:40.649027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27311 11:35:40.691817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27312 11:35:40.692252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27314 11:35:40.733478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27315 11:35:40.733929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27317 11:35:40.772849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27318 11:35:40.773280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27320 11:35:40.814210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27321 11:35:40.814631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27323 11:35:40.856225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27324 11:35:40.856642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27326 11:35:40.893887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27327 11:35:40.894340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27329 11:35:40.933532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27330 11:35:40.933981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27332 11:35:40.981788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27333 11:35:40.982189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27335 11:35:41.017879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27336 11:35:41.018391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27338 11:35:41.056063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27340 11:35:41.056535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27341 11:35:41.096944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27343 11:35:41.097412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27344 11:35:41.141325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27345 11:35:41.141836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27347 11:35:41.193852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27348 11:35:41.194348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27350 11:35:41.238623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27352 11:35:41.239121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27353 11:35:41.283428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27354 11:35:41.283853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27356 11:35:41.320058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27358 11:35:41.320529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27359 11:35:41.359297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27360 11:35:41.359743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27362 11:35:41.409500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27363 11:35:41.409941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27365 11:35:41.461374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27366 11:35:41.461932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27368 11:35:41.496324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27369 11:35:41.496765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27371 11:35:41.535636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27372 11:35:41.536079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27374 11:35:41.575656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27375 11:35:41.576077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27377 11:35:41.623882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27379 11:35:41.624367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27380 11:35:41.671911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27381 11:35:41.672340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27383 11:35:41.712343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27384 11:35:41.712765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27386 11:35:41.749345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27387 11:35:41.749775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27389 11:35:41.796959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27391 11:35:41.797351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27392 11:35:41.840253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27393 11:35:41.840744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27395 11:35:41.891826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27396 11:35:41.892403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27398 11:35:41.935537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27400 11:35:41.935920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27401 11:35:41.980275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27403 11:35:41.980764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27404 11:35:42.016408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27405 11:35:42.016842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27407 11:35:42.059938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27409 11:35:42.060400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27410 11:35:42.108106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27411 11:35:42.108556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27413 11:35:42.157161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27415 11:35:42.157642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27416 11:35:42.205315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27417 11:35:42.205710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27419 11:35:42.241720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27420 11:35:42.242151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27422 11:35:42.280907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27423 11:35:42.281311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27425 11:35:42.328344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27426 11:35:42.328785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27428 11:35:42.371278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27429 11:35:42.371738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27431 11:35:42.416504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27432 11:35:42.416895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27434 11:35:42.454629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27436 11:35:42.455076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27437 11:35:42.493871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27439 11:35:42.494261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27440 11:35:42.543886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27441 11:35:42.544322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27443 11:35:42.591244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27444 11:35:42.591679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27446 11:35:42.643763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27448 11:35:42.644230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27449 11:35:42.686184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27451 11:35:42.686615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27452 11:35:42.724555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27454 11:35:42.725023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27455 11:35:42.763993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27457 11:35:42.764496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27458 11:35:42.807455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27460 11:35:42.807908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27461 11:35:42.847897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27463 11:35:42.848308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27464 11:35:42.889832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27466 11:35:42.890334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27467 11:35:42.943505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27469 11:35:42.943966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27470 11:35:43.007607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27471 11:35:43.008044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27473 11:35:43.055379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27474 11:35:43.055809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27476 11:35:43.094620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27478 11:35:43.095042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27479 11:35:43.151229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27480 11:35:43.151686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27482 11:35:43.207208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27483 11:35:43.207613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27485 11:35:43.256452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27487 11:35:43.257024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27488 11:35:43.296690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27490 11:35:43.297160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27491 11:35:43.337119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27492 11:35:43.337570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27494 11:35:43.381474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27495 11:35:43.381890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27497 11:35:43.421698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27498 11:35:43.422126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27500 11:35:43.461051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27501 11:35:43.461464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27503 11:35:43.496898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27504 11:35:43.497317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27506 11:35:43.541089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27507 11:35:43.541638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27509 11:35:43.586047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27510 11:35:43.586482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27512 11:35:43.626843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27514 11:35:43.627303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27515 11:35:43.666003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27516 11:35:43.666432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27518 11:35:43.704220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27519 11:35:43.704659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27521 11:35:43.744489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27523 11:35:43.744951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27524 11:35:43.783629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27526 11:35:43.784101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27527 11:35:43.842976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27528 11:35:43.843410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27530 11:35:43.882053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27531 11:35:43.882465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27533 11:35:43.926111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27534 11:35:43.926432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27536 11:35:43.972282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27537 11:35:43.972663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27539 11:35:44.023597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27540 11:35:44.023987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27542 11:35:44.073571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27543 11:35:44.074039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27545 11:35:44.115149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27547 11:35:44.115895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27548 11:35:44.151691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27549 11:35:44.152066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27551 11:35:44.189821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27553 11:35:44.190285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27554 11:35:44.228696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27555 11:35:44.229124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27557 11:35:44.273210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27558 11:35:44.273676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27560 11:35:44.313680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27561 11:35:44.314098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27563 11:35:44.360003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27564 11:35:44.360435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27566 11:35:44.405717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27568 11:35:44.406188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27569 11:35:44.452742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27570 11:35:44.453162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27572 11:35:44.496520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27573 11:35:44.496947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27575 11:35:44.541041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27576 11:35:44.541511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27578 11:35:44.578192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27579 11:35:44.578740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27581 11:35:44.617472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27582 11:35:44.617902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27584 11:35:44.657062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27586 11:35:44.657524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27587 11:35:44.712317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27588 11:35:44.712745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27590 11:35:44.751741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27591 11:35:44.752196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27593 11:35:44.792144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27594 11:35:44.792570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27596 11:35:44.832080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27597 11:35:44.832469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27599 11:35:44.876338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27601 11:35:44.876764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27602 11:35:44.915877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27603 11:35:44.916247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27605 11:35:44.956721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27606 11:35:44.957094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27608 11:35:45.012676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27610 11:35:45.013146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27611 11:35:45.065789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27613 11:35:45.066259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27614 11:35:45.121794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27615 11:35:45.122194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27617 11:35:45.168734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27618 11:35:45.169119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27620 11:35:45.220780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27621 11:35:45.221265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27623 11:35:45.272999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27624 11:35:45.273569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27626 11:35:45.331237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27628 11:35:45.331721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27629 11:35:45.372583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27631 11:35:45.373038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27632 11:35:45.409110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27633 11:35:45.409563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27635 11:35:45.447160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27636 11:35:45.447618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27638 11:35:45.488484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27639 11:35:45.488924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27641 11:35:45.543261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27642 11:35:45.543670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27644 11:35:45.599370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27646 11:35:45.599864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27647 11:35:45.653804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27648 11:35:45.655261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27650 11:35:45.708659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27651 11:35:45.709121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27653 11:35:45.756437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27654 11:35:45.756853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27656 11:35:45.807932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27658 11:35:45.808392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27659 11:35:45.851171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27660 11:35:45.851616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27662 11:35:45.896066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27663 11:35:45.896473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27665 11:35:45.940896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27666 11:35:45.941339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27668 11:35:45.984040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27669 11:35:45.984467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27671 11:35:46.038666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27673 11:35:46.039136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27674 11:35:46.095569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27676 11:35:46.096049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27677 11:35:46.155226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27679 11:35:46.155714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27680 11:35:46.199895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27681 11:35:46.200324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27683 11:35:46.240145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27684 11:35:46.240592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27686 11:35:46.281644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27688 11:35:46.282329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27689 11:35:46.332441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27691 11:35:46.333056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27692 11:35:46.376302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27693 11:35:46.376822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27695 11:35:46.428378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27696 11:35:46.428765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27698 11:35:46.478287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27699 11:35:46.478741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27701 11:35:46.521673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27702 11:35:46.522116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27704 11:35:46.569604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27705 11:35:46.570043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27707 11:35:46.623349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27709 11:35:46.623828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27710 11:35:46.676345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27711 11:35:46.676790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27713 11:35:46.727210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27715 11:35:46.727689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27716 11:35:46.780886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27717 11:35:46.781340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27719 11:35:46.829357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27721 11:35:46.829847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27722 11:35:46.883880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27723 11:35:46.884246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27725 11:35:46.935279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27726 11:35:46.935705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27728 11:35:46.984220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27729 11:35:46.984891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27731 11:35:47.037218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27732 11:35:47.037630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27734 11:35:47.085203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27736 11:35:47.085675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27737 11:35:47.124043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27738 11:35:47.124493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27740 11:35:47.172590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27741 11:35:47.173022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27743 11:35:47.211103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27744 11:35:47.211501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27746 11:35:47.263601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27747 11:35:47.264023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27749 11:35:47.301080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27750 11:35:47.301525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27752 11:35:47.343275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
27754 11:35:47.343750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27755 11:35:47.393641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
27757 11:35:47.394189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
27758 11:35:47.435830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
27759 11:35:47.436284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
27761 11:35:47.487161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
27762 11:35:47.487556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
27764 11:35:47.529022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
27766 11:35:47.529507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
27767 11:35:47.583428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
27768 11:35:47.583824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
27770 11:35:47.638014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
27771 11:35:47.638435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
27773 11:35:47.677220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
27774 11:35:47.677673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
27776 11:35:47.727305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
27778 11:35:47.727922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
27779 11:35:47.778044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
27780 11:35:47.778528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
27782 11:35:47.826068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
27784 11:35:47.826487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
27785 11:35:47.872571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
27786 11:35:47.873009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
27788 11:35:47.913232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
27790 11:35:47.913726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
27791 11:35:47.958248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
27792 11:35:47.958640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
27794 11:35:48.013513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
27795 11:35:48.013979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
27797 11:35:48.067360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
27799 11:35:48.067776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
27800 11:35:48.111862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
27801 11:35:48.112254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
27803 11:35:48.157483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
27804 11:35:48.157961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
27806 11:35:48.202133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
27807 11:35:48.202571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
27809 11:35:48.257166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
27810 11:35:48.257674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
27812 11:35:48.300675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
27814 11:35:48.301094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
27815 11:35:48.353049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
27816 11:35:48.353613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
27818 11:35:48.400752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
27819 11:35:48.401308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
27821 11:35:48.447136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
27822 11:35:48.447576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
27824 11:35:48.487459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
27825 11:35:48.487896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
27827 11:35:48.539725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
27829 11:35:48.540190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
27830 11:35:48.578087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
27832 11:35:48.578551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
27833 11:35:48.620722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
27835 11:35:48.621200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
27836 11:35:48.668296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
27838 11:35:48.668741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
27839 11:35:48.719500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
27840 11:35:48.719932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
27842 11:35:48.759840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
27844 11:35:48.760289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
27845 11:35:48.813112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
27846 11:35:48.813554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
27848 11:35:48.850561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
27850 11:35:48.851035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
27851 11:35:48.893659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
27852 11:35:48.894091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
27854 11:35:48.949749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
27855 11:35:48.950197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
27857 11:35:48.991024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
27858 11:35:48.991455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
27860 11:35:49.039620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
27862 11:35:49.040200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
27863 11:35:49.090356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
27864 11:35:49.090733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
27866 11:35:49.132770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
27867 11:35:49.133133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
27869 11:35:49.171486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
27870 11:35:49.171969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
27872 11:35:49.210247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
27873 11:35:49.210696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
27875 11:35:49.257484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
27876 11:35:49.257934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
27878 11:35:49.300519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
27879 11:35:49.300943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
27881 11:35:49.339197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
27883 11:35:49.339600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
27884 11:35:49.376371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
27885 11:35:49.376791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
27887 11:35:49.413002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
27889 11:35:49.413489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
27890 11:35:49.456864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
27892 11:35:49.457345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
27893 11:35:49.496264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
27895 11:35:49.496749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
27896 11:35:49.534399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
27898 11:35:49.535147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
27899 11:35:49.572803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
27900 11:35:49.573302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
27902 11:35:49.613315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
27903 11:35:49.613793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
27905 11:35:49.668291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
27906 11:35:49.668834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
27908 11:35:49.713745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
27909 11:35:49.714311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
27911 11:35:49.747766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
27912 11:35:49.748183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
27914 11:35:49.789491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
27916 11:35:49.789957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
27917 11:35:49.823976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
27919 11:35:49.824508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
27920 11:35:49.860007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
27922 11:35:49.860497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
27923 11:35:49.907646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
27925 11:35:49.908079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
27926 11:35:49.952509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
27927 11:35:49.952950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
27929 11:35:50.000211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
27931 11:35:50.000799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
27932 11:35:50.044593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
27933 11:35:50.045152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
27935 11:35:50.086078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
27937 11:35:50.086707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
27938 11:35:50.127541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
27939 11:35:50.128051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
27941 11:35:50.162188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
27942 11:35:50.162592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
27944 11:35:50.195414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
27946 11:35:50.195853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
27947 11:35:50.237179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
27948 11:35:50.237660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
27950 11:35:50.272369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
27952 11:35:50.272795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
27953 11:35:50.308231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
27954 11:35:50.308677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
27956 11:35:50.351966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
27957 11:35:50.352344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
27959 11:35:50.389195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
27961 11:35:50.389787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
27962 11:35:50.424865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
27964 11:35:50.425362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
27965 11:35:50.461532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
27967 11:35:50.461902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
27968 11:35:50.512106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
27969 11:35:50.512533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
27971 11:35:50.549294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
27972 11:35:50.549767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
27974 11:35:50.586965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
27976 11:35:50.587365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
27977 11:35:50.622559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
27979 11:35:50.623128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
27980 11:35:50.657349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
27981 11:35:50.657918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
27983 11:35:50.692922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
27984 11:35:50.693308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
27986 11:35:50.729008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
27987 11:35:50.729425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
27989 11:35:50.763184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
27990 11:35:50.763610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
27992 11:35:50.796843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
27993 11:35:50.797281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
27995 11:35:50.830217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
27997 11:35:50.830645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
27998 11:35:50.865455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28000 11:35:50.865881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28001 11:35:50.912333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28002 11:35:50.912810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28004 11:35:50.949708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28005 11:35:50.950113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28007 11:35:50.984572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28009 11:35:50.985042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28010 11:35:51.021461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28012 11:35:51.021839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28013 11:35:51.059262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28014 11:35:51.059695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28016 11:35:51.092001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28017 11:35:51.092441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28019 11:35:51.128361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28020 11:35:51.128787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28022 11:35:51.168521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28023 11:35:51.168942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28025 11:35:51.215937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28027 11:35:51.216410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28028 11:35:51.263943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28029 11:35:51.264330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28031 11:35:51.299841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28033 11:35:51.300463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28034 11:35:51.335978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28035 11:35:51.336549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28037 11:35:51.372000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28039 11:35:51.372721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28040 11:35:51.419513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28041 11:35:51.419892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28043 11:35:51.459785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28045 11:35:51.460246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28046 11:35:51.496075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28048 11:35:51.496539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28049 11:35:51.532766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28051 11:35:51.533240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28052 11:35:51.573934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28053 11:35:51.574390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28055 11:35:51.611853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28056 11:35:51.612287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28058 11:35:51.647301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28059 11:35:51.647861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28061 11:35:51.682517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28063 11:35:51.682996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28064 11:35:51.733846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28065 11:35:51.734275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28067 11:35:51.790673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28069 11:35:51.791161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28070 11:35:51.842612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28072 11:35:51.843082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28073 11:35:51.885805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28074 11:35:51.886162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28076 11:35:51.921898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28077 11:35:51.922247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28079 11:35:51.958742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28081 11:35:51.959219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28082 11:35:52.006056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28083 11:35:52.006504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28085 11:35:52.045035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28086 11:35:52.045450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28088 11:35:52.082041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28089 11:35:52.082490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28091 11:35:52.131838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28092 11:35:52.132410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28094 11:35:52.168034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28095 11:35:52.168474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28097 11:35:52.204247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28099 11:35:52.204705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28100 11:35:52.239843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28101 11:35:52.240271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28103 11:35:52.275825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28104 11:35:52.276258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28106 11:35:52.321239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28107 11:35:52.321694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28109 11:35:52.364388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28110 11:35:52.364832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28112 11:35:52.400432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28114 11:35:52.400891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28115 11:35:52.441883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28117 11:35:52.442372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28118 11:35:52.481187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28119 11:35:52.481605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28121 11:35:52.520514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28122 11:35:52.520948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28124 11:35:52.556491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28125 11:35:52.556899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28127 11:35:52.592541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28128 11:35:52.592963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28130 11:35:52.627598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28131 11:35:52.628033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28133 11:35:52.664884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28134 11:35:52.665331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28136 11:35:52.717098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28138 11:35:52.717757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28139 11:35:52.766555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28141 11:35:52.766969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28142 11:35:52.803315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28143 11:35:52.803798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28145 11:35:52.839746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28146 11:35:52.840266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28148 11:35:52.877099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28149 11:35:52.877579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28151 11:35:52.913965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28152 11:35:52.914463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28154 11:35:52.951376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28155 11:35:52.951820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28157 11:35:53.003326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28158 11:35:53.003720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28160 11:35:53.045523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28161 11:35:53.045980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28163 11:35:53.087476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28165 11:35:53.087972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28166 11:35:53.128116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28168 11:35:53.128547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28169 11:35:53.166364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28171 11:35:53.166734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28172 11:35:53.208326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28173 11:35:53.208641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28175 11:35:53.252827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28176 11:35:53.253243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28178 11:35:53.296626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28180 11:35:53.297190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28181 11:35:53.353080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28183 11:35:53.353541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28184 11:35:53.390688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28186 11:35:53.391170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28187 11:35:53.425426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28188 11:35:53.425871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28190 11:35:53.460773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28191 11:35:53.461185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28193 11:35:53.496323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28194 11:35:53.496747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28196 11:35:53.531575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28197 11:35:53.532002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28199 11:35:53.567249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28201 11:35:53.567712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28202 11:35:53.609787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28203 11:35:53.610210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28205 11:35:53.659976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28206 11:35:53.660402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28208 11:35:53.716386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28209 11:35:53.716810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28211 11:35:53.763395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28213 11:35:53.763873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28214 11:35:53.798133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28216 11:35:53.798491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28217 11:35:53.833553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28218 11:35:53.833977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28220 11:35:53.868814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28222 11:35:53.869435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28223 11:35:53.907869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28224 11:35:53.908289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28226 11:35:53.947312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28227 11:35:53.947717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28229 11:35:53.987616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28230 11:35:53.988107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28232 11:35:54.028276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28234 11:35:54.028952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28235 11:35:54.086920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28236 11:35:54.087304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28238 11:35:54.123607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28239 11:35:54.124117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28241 11:35:54.159241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28243 11:35:54.159696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28244 11:35:54.208245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28245 11:35:54.208664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28247 11:35:54.248101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28248 11:35:54.248603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28250 11:35:54.284885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28251 11:35:54.285328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28253 11:35:54.322848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28255 11:35:54.323311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28256 11:35:54.363985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28257 11:35:54.364411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28259 11:35:54.399885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28260 11:35:54.400303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28262 11:35:54.436466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28264 11:35:54.436933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28265 11:35:54.471841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28267 11:35:54.472294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28268 11:35:54.507136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28270 11:35:54.507591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28271 11:35:54.541480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28273 11:35:54.541946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28274 11:35:54.576440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28275 11:35:54.576875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28277 11:35:54.611636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28278 11:35:54.612080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28280 11:35:54.649657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28281 11:35:54.650099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28283 11:35:54.685856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28284 11:35:54.686308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28286 11:35:54.722536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28288 11:35:54.723052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28289 11:35:54.759311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28291 11:35:54.759771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28292 11:35:54.795852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28293 11:35:54.796240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28295 11:35:54.831858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28296 11:35:54.832292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28298 11:35:54.868673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28299 11:35:54.869113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28301 11:35:54.904786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28303 11:35:54.905275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28304 11:35:54.939655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28305 11:35:54.940077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28307 11:35:54.977803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28308 11:35:54.978210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28310 11:35:55.018608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28312 11:35:55.019195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28313 11:35:55.054571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28315 11:35:55.055326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28316 11:35:55.094553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28318 11:35:55.094966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28319 11:35:55.131723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28321 11:35:55.132037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28322 11:35:55.169011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28324 11:35:55.169407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28325 11:35:55.206275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28326 11:35:55.206681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28328 11:35:55.243544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28329 11:35:55.243961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28331 11:35:55.280182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28332 11:35:55.280604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28334 11:35:55.328425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28335 11:35:55.328862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28337 11:35:55.365175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28338 11:35:55.365617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28340 11:35:55.401327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28342 11:35:55.401803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28343 11:35:55.436499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28345 11:35:55.436955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28346 11:35:55.472553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28348 11:35:55.473017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28349 11:35:55.509168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28351 11:35:55.509842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28352 11:35:55.548113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28354 11:35:55.548648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28355 11:35:55.585720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28356 11:35:55.586140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28358 11:35:55.621148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28360 11:35:55.621610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28361 11:35:55.656113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28362 11:35:55.656569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28364 11:35:55.692401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28366 11:35:55.692868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28367 11:35:55.728964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28368 11:35:55.729390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28370 11:35:55.766533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28372 11:35:55.766969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28373 11:35:55.803963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28374 11:35:55.804331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28376 11:35:55.853982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28378 11:35:55.854454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28379 11:35:55.899755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28380 11:35:55.900300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28382 11:35:55.958091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28384 11:35:55.958757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28385 11:35:56.016463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28387 11:35:56.016883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28388 11:35:56.074554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28390 11:35:56.075175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28391 11:35:56.116675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28392 11:35:56.117145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28394 11:35:56.153967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28395 11:35:56.154404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28397 11:35:56.191946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28399 11:35:56.192410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28400 11:35:56.232825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28401 11:35:56.233258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28403 11:35:56.274121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28405 11:35:56.274589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28406 11:35:56.311548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28408 11:35:56.312011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28409 11:35:56.350500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28411 11:35:56.350975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28412 11:35:56.396623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28413 11:35:56.397040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28415 11:35:56.436927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28417 11:35:56.437389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28418 11:35:56.477279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28419 11:35:56.477692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28421 11:35:56.527946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28422 11:35:56.528383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28424 11:35:56.564773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28426 11:35:56.565257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28427 11:35:56.601150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28428 11:35:56.601581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28430 11:35:56.636449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28431 11:35:56.636888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28433 11:35:56.673156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28435 11:35:56.673619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28436 11:35:56.709180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28438 11:35:56.709662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28439 11:35:56.744961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28441 11:35:56.745431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28442 11:35:56.781185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28443 11:35:56.781618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28445 11:35:56.820355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28446 11:35:56.820784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28448 11:35:56.858322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28450 11:35:56.858786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28451 11:35:56.896639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28453 11:35:56.897105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28454 11:35:56.933587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28455 11:35:56.934012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28457 11:35:56.969867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28459 11:35:56.970334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28460 11:35:57.009814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28461 11:35:57.010237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28463 11:35:57.046807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28465 11:35:57.047343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28466 11:35:57.083066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28467 11:35:57.083471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28469 11:35:57.120162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28471 11:35:57.120652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28472 11:35:57.157841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28474 11:35:57.158308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28475 11:35:57.203817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28477 11:35:57.204275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28478 11:35:57.240647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28479 11:35:57.241066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28481 11:35:57.277215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28483 11:35:57.277675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28484 11:35:57.313519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28486 11:35:57.313986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28487 11:35:57.350027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28489 11:35:57.350498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28490 11:35:57.387682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28491 11:35:57.388124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28493 11:35:57.424768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28494 11:35:57.425215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28496 11:35:57.463691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28497 11:35:57.464130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28499 11:35:57.505441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28500 11:35:57.505849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28502 11:35:57.543900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28504 11:35:57.544372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28505 11:35:57.585302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28506 11:35:57.585744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28508 11:35:57.624739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28509 11:35:57.625165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28511 11:35:57.683655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28512 11:35:57.684096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28514 11:35:57.741983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28515 11:35:57.742381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28517 11:35:57.797572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28518 11:35:57.798019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28520 11:35:57.842140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28521 11:35:57.842587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28523 11:35:57.879841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28524 11:35:57.880298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28526 11:35:57.916055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28528 11:35:57.916516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28529 11:35:57.954666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28531 11:35:57.955424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28532 11:35:57.993872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28534 11:35:57.994599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28535 11:35:58.036406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28536 11:35:58.036780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28538 11:35:58.086034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28539 11:35:58.086462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28541 11:35:58.125790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28542 11:35:58.126243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28544 11:35:58.170151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28545 11:35:58.170575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28547 11:35:58.205716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28548 11:35:58.206157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28550 11:35:58.243322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28552 11:35:58.243785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28553 11:35:58.280576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28554 11:35:58.281031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28556 11:35:58.338510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28558 11:35:58.339126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28559 11:35:58.387886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28560 11:35:58.388324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28562 11:35:58.428587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28564 11:35:58.429095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28565 11:35:58.476440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28567 11:35:58.476920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28568 11:35:58.532492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28570 11:35:58.532970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28571 11:35:58.572232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28572 11:35:58.572670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28574 11:35:58.611666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28575 11:35:58.612125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28577 11:35:58.665783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28579 11:35:58.666261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28580 11:35:58.703876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28581 11:35:58.704322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28583 11:35:58.746162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28584 11:35:58.746656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28586 11:35:58.800625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28588 11:35:58.801002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28589 11:35:58.856250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28590 11:35:58.856679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28592 11:35:58.897894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28594 11:35:58.898284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28595 11:35:58.946487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28597 11:35:58.947029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28598 11:35:58.992718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28599 11:35:58.993149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28601 11:35:59.043621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28603 11:35:59.044104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28604 11:35:59.088586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28605 11:35:59.089020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28607 11:35:59.141637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28608 11:35:59.142007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28610 11:35:59.228907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28612 11:35:59.229451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28613 11:35:59.278049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28614 11:35:59.278489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28616 11:35:59.326702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28618 11:35:59.327121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28619 11:35:59.364034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28620 11:35:59.364425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28622 11:35:59.405363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28623 11:35:59.405852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28625 11:35:59.451291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28626 11:35:59.451719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28628 11:35:59.487258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28630 11:35:59.487722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28631 11:35:59.523778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28633 11:35:59.524198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28634 11:35:59.563169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28635 11:35:59.563714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28637 11:35:59.614333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28639 11:35:59.614802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28640 11:35:59.653216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28641 11:35:59.653641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28643 11:35:59.711908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28644 11:35:59.712339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28646 11:35:59.747918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28647 11:35:59.748357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28649 11:35:59.788469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28651 11:35:59.788944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28652 11:35:59.827420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28653 11:35:59.827844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28655 11:35:59.878446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28657 11:35:59.878924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28658 11:35:59.920509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28659 11:35:59.920929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28661 11:35:59.957690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28663 11:35:59.958155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28664 11:35:59.999253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28665 11:35:59.999776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28667 11:36:00.048369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28669 11:36:00.049135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28670 11:36:00.085724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28672 11:36:00.086415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28673 11:36:00.129161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28675 11:36:00.129961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28676 11:36:00.165558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28678 11:36:00.166040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28679 11:36:00.203198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28681 11:36:00.203675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28682 11:36:00.241825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28683 11:36:00.242258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28685 11:36:00.283469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28686 11:36:00.283918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28688 11:36:00.321366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28689 11:36:00.321833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28691 11:36:00.362292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28693 11:36:00.362723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28694 11:36:00.400351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28696 11:36:00.400773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28697 11:36:00.439652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28698 11:36:00.440038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28700 11:36:00.479717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28701 11:36:00.480052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28703 11:36:00.522122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28705 11:36:00.522711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28706 11:36:00.562013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28708 11:36:00.562440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28709 11:36:00.598305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28711 11:36:00.598756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28712 11:36:00.636209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28714 11:36:00.636629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28715 11:36:00.673231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28716 11:36:00.673641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28718 11:36:00.709891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28720 11:36:00.710645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28721 11:36:00.746517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28723 11:36:00.746988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28724 11:36:00.784091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28726 11:36:00.784555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28727 11:36:00.823356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28728 11:36:00.823804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28730 11:36:00.860466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28731 11:36:00.860958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28733 11:36:00.894778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28735 11:36:00.895339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28736 11:36:00.929302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28737 11:36:00.929770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28739 11:36:00.964003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28741 11:36:00.964464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28742 11:36:01.000302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28744 11:36:01.001043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28745 11:36:01.035796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28746 11:36:01.036269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28748 11:36:01.071726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28750 11:36:01.072379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28751 11:36:01.108388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28752 11:36:01.108911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28754 11:36:01.145987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
28756 11:36:01.146700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
28757 11:36:01.183611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
28758 11:36:01.184008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
28760 11:36:01.223243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
28762 11:36:01.223970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
28763 11:36:01.260479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
28764 11:36:01.261015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
28766 11:36:01.303341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
28767 11:36:01.303864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
28769 11:36:01.350092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
28770 11:36:01.350576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
28772 11:36:01.396846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
28774 11:36:01.397486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
28775 11:36:01.444286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
28777 11:36:01.445079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
28778 11:36:01.482145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
28779 11:36:01.482574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
28781 11:36:01.520406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
28783 11:36:01.520867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
28784 11:36:01.557340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
28786 11:36:01.557839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
28787 11:36:01.596116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
28788 11:36:01.596676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
28790 11:36:01.641093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
28791 11:36:01.641538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
28793 11:36:01.681248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
28794 11:36:01.681759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
28796 11:36:01.718794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
28798 11:36:01.719255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
28799 11:36:01.756022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
28800 11:36:01.756440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
28802 11:36:01.791766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
28804 11:36:01.792375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
28805 11:36:01.829040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
28806 11:36:01.829463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
28808 11:36:01.866438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
28810 11:36:01.866864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
28811 11:36:01.902214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
28812 11:36:01.902597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
28814 11:36:01.946554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
28816 11:36:01.946940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
28817 11:36:01.981031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
28819 11:36:01.981481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
28820 11:36:02.015502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
28821 11:36:02.015914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
28823 11:36:02.051059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
28825 11:36:02.051530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
28826 11:36:02.087651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
28827 11:36:02.088107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
28829 11:36:02.142396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
28830 11:36:02.142960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
28832 11:36:02.179261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
28834 11:36:02.179879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
28835 11:36:02.215827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
28836 11:36:02.216223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
28838 11:36:02.254969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
28840 11:36:02.255439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
28841 11:36:02.290493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
28843 11:36:02.290968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
28844 11:36:02.325868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
28845 11:36:02.326284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
28847 11:36:02.363602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
28848 11:36:02.364144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
28850 11:36:02.401267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
28851 11:36:02.401682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
28853 11:36:02.436582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
28854 11:36:02.437024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
28856 11:36:02.491697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
28857 11:36:02.492267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
28859 11:36:02.527131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
28861 11:36:02.527886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
28862 11:36:02.573987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
28864 11:36:02.574567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
28865 11:36:02.628490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
28866 11:36:02.628913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
28868 11:36:02.682204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
28869 11:36:02.682576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
28871 11:36:02.734494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
28873 11:36:02.735096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
28874 11:36:02.781770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
28875 11:36:02.782205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
28877 11:36:02.828572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
28879 11:36:02.828962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
28880 11:36:02.875859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
28882 11:36:02.876246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
28883 11:36:02.911445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
28885 11:36:02.911927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
28886 11:36:02.947794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
28887 11:36:02.948368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
28889 11:36:02.993634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
28890 11:36:02.994155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
28892 11:36:03.031546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
28894 11:36:03.032012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
28895 11:36:03.067893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
28897 11:36:03.068360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
28898 11:36:03.104514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
28900 11:36:03.104982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
28901 11:36:03.143441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
28902 11:36:03.143814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
28904 11:36:03.179688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
28905 11:36:03.180145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
28907 11:36:03.216714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
28908 11:36:03.217258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
28910 11:36:03.251352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
28911 11:36:03.251796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
28913 11:36:03.288753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
28915 11:36:03.289230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
28916 11:36:03.328924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
28918 11:36:03.329515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
28919 11:36:03.367470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
28921 11:36:03.367949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
28922 11:36:03.408887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
28923 11:36:03.409285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
28925 11:36:03.454124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
28926 11:36:03.454526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
28928 11:36:03.493807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
28929 11:36:03.494194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
28931 11:36:03.546783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
28933 11:36:03.547388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
28934 11:36:03.586675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
28936 11:36:03.587052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
28937 11:36:03.623428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
28939 11:36:03.623843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
28940 11:36:03.662588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
28942 11:36:03.663056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
28943 11:36:03.707710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
28944 11:36:03.708250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
28946 11:36:03.755441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
28947 11:36:03.755885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
28949 11:36:03.792171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
28950 11:36:03.792577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
28952 11:36:03.833446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
28954 11:36:03.833929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
28955 11:36:03.868858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
28957 11:36:03.869423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
28958 11:36:03.908313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
28959 11:36:03.908753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
28961 11:36:03.946994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
28962 11:36:03.947437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
28964 11:36:03.981696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
28965 11:36:03.982122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
28967 11:36:04.035094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
28969 11:36:04.035568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
28970 11:36:04.078054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
28971 11:36:04.078551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
28973 11:36:04.111910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
28974 11:36:04.112359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
28976 11:36:04.145581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
28978 11:36:04.146051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
28979 11:36:04.185272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
28981 11:36:04.185747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
28982 11:36:04.220713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
28983 11:36:04.221154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
28985 11:36:04.266070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
28986 11:36:04.266525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
28988 11:36:04.332059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
28990 11:36:04.332530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
28991 11:36:04.380346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
28992 11:36:04.380791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
28994 11:36:04.440249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
28995 11:36:04.440655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
28997 11:36:04.498207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
28998 11:36:04.498610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29000 11:36:04.547020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29001 11:36:04.547440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29003 11:36:04.585712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29005 11:36:04.586170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29006 11:36:04.634239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29008 11:36:04.634718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29009 11:36:04.681010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29010 11:36:04.681443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29012 11:36:04.721818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29013 11:36:04.722206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29015 11:36:04.761246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29016 11:36:04.761681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29018 11:36:04.804491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29019 11:36:04.804911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29021 11:36:04.845398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29023 11:36:04.845866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29024 11:36:04.882080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29026 11:36:04.882556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29027 11:36:04.929560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29028 11:36:04.930008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29030 11:36:04.972647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29032 11:36:04.973043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29033 11:36:05.008453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29035 11:36:05.008825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29036 11:36:05.045863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29037 11:36:05.046343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29039 11:36:05.099563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29041 11:36:05.100211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29042 11:36:05.148082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29044 11:36:05.148546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29045 11:36:05.191987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29046 11:36:05.192557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29048 11:36:05.226628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29050 11:36:05.227105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29051 11:36:05.262770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29052 11:36:05.263208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29054 11:36:05.308762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29056 11:36:05.309411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29057 11:36:05.356398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29058 11:36:05.356818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29060 11:36:05.403967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29061 11:36:05.404415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29063 11:36:05.450161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29064 11:36:05.450722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29066 11:36:05.485571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29067 11:36:05.486023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29069 11:36:05.520006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29070 11:36:05.520438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29072 11:36:05.554621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29074 11:36:05.555309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29075 11:36:05.594446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29077 11:36:05.594912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29078 11:36:05.632718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29079 11:36:05.633166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29081 11:36:05.668818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29082 11:36:05.669273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29084 11:36:05.703879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29085 11:36:05.704325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29087 11:36:05.745595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29088 11:36:05.746047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29090 11:36:05.786147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29092 11:36:05.786609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29093 11:36:05.822228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29094 11:36:05.822727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29096 11:36:05.857779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29097 11:36:05.858235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29099 11:36:05.894522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29101 11:36:05.894996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29102 11:36:05.931532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29103 11:36:05.931975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29105 11:36:05.967238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29106 11:36:05.967690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29108 11:36:06.013347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29110 11:36:06.013833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29111 11:36:06.052565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29112 11:36:06.053120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29114 11:36:06.090516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29116 11:36:06.091181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29117 11:36:06.129038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29118 11:36:06.129603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29120 11:36:06.175651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29121 11:36:06.176377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29123 11:36:06.218064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29124 11:36:06.218465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29126 11:36:06.263729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29127 11:36:06.264159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29129 11:36:06.309380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29131 11:36:06.309883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29132 11:36:06.350056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29134 11:36:06.350533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29135 11:36:06.388952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29137 11:36:06.389462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29138 11:36:06.433357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29139 11:36:06.433794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29141 11:36:06.479955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29143 11:36:06.480410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29144 11:36:06.521236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29145 11:36:06.521802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29147 11:36:06.563221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29149 11:36:06.563684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29150 11:36:06.601497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29151 11:36:06.601999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29153 11:36:06.644307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29154 11:36:06.644732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29156 11:36:06.693978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29157 11:36:06.694501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29159 11:36:06.733015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29160 11:36:06.733574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29162 11:36:06.771978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29163 11:36:06.772400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29165 11:36:06.812126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29166 11:36:06.812549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29168 11:36:06.850555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29170 11:36:06.851003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29171 11:36:06.891540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29173 11:36:06.892213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29174 11:36:06.942089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29175 11:36:06.942645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29177 11:36:06.982025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29178 11:36:06.982517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29180 11:36:07.016967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29182 11:36:07.017432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29183 11:36:07.055355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29184 11:36:07.055747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29186 11:36:07.108021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29187 11:36:07.108513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29189 11:36:07.159489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29190 11:36:07.159964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29192 11:36:07.198255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29193 11:36:07.198825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29195 11:36:07.236705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29196 11:36:07.237142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29198 11:36:07.270445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29199 11:36:07.270873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29201 11:36:07.315400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29202 11:36:07.315948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29204 11:36:07.348434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29206 11:36:07.348806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29207 11:36:07.386249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29208 11:36:07.386673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29210 11:36:07.423703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29211 11:36:07.424118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29213 11:36:07.460340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29214 11:36:07.460784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29216 11:36:07.499819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29218 11:36:07.500239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29219 11:36:07.533758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29220 11:36:07.534159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29222 11:36:07.569625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29224 11:36:07.570106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29225 11:36:07.605005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29227 11:36:07.605379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29228 11:36:07.639049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29229 11:36:07.639594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29231 11:36:07.673731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29233 11:36:07.674339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29234 11:36:07.711911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29235 11:36:07.712391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29237 11:36:07.748414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29238 11:36:07.748904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29240 11:36:07.796619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29241 11:36:07.797130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29243 11:36:07.830967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29245 11:36:07.831416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29246 11:36:07.864882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29247 11:36:07.865325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29249 11:36:07.901629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29250 11:36:07.902088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29252 11:36:07.936060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29254 11:36:07.936525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29255 11:36:07.969709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29257 11:36:07.970162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29258 11:36:08.008252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29260 11:36:08.008698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29261 11:36:08.045495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29262 11:36:08.045934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29264 11:36:08.081671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29266 11:36:08.082122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29267 11:36:08.134519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29269 11:36:08.134982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29270 11:36:08.171644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29272 11:36:08.172053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29273 11:36:08.208626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29274 11:36:08.208996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29276 11:36:08.249042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29277 11:36:08.249476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29279 11:36:08.294553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29281 11:36:08.295036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29282 11:36:08.339855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29284 11:36:08.340512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29285 11:36:08.377483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29287 11:36:08.378142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29288 11:36:08.413900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29289 11:36:08.414325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29291 11:36:08.449202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29292 11:36:08.449698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29294 11:36:08.495755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29296 11:36:08.496518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29297 11:36:08.538382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29299 11:36:08.538819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29300 11:36:08.572830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29301 11:36:08.573246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29303 11:36:08.618286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29305 11:36:08.618765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29306 11:36:08.658587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29308 11:36:08.659068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29309 11:36:08.699456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29311 11:36:08.699917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29312 11:36:08.738151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29313 11:36:08.738570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29315 11:36:08.778544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29317 11:36:08.779173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29318 11:36:08.812603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29319 11:36:08.813085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29321 11:36:08.855579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29322 11:36:08.856134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29324 11:36:08.895996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29325 11:36:08.896420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29327 11:36:08.932461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29329 11:36:08.932827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29330 11:36:08.967911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29331 11:36:08.968393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29333 11:36:09.003233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29335 11:36:09.003904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29336 11:36:09.038797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29337 11:36:09.039288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29339 11:36:09.081673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29341 11:36:09.082249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29342 11:36:09.120014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29344 11:36:09.120487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29345 11:36:09.165144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29346 11:36:09.165546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29348 11:36:09.206026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29349 11:36:09.206470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29351 11:36:09.242308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29353 11:36:09.242716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29354 11:36:09.279898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29356 11:36:09.280502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29357 11:36:09.337493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29358 11:36:09.337922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29360 11:36:09.393346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29362 11:36:09.393974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29363 11:36:09.470781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29365 11:36:09.471410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29366 11:36:09.510071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29367 11:36:09.510585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29369 11:36:09.550183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29370 11:36:09.550626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29372 11:36:09.589961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29374 11:36:09.590449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29375 11:36:09.627708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29377 11:36:09.628176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29378 11:36:09.667802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29379 11:36:09.668268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29381 11:36:09.727893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29382 11:36:09.728327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29384 11:36:09.780998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29385 11:36:09.781454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29387 11:36:09.825293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29388 11:36:09.825687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29390 11:36:09.869473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29392 11:36:09.869950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29393 11:36:09.911633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29395 11:36:09.912058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29396 11:36:09.952710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29397 11:36:09.953157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29399 11:36:09.998494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29400 11:36:09.998923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29402 11:36:10.040066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29404 11:36:10.040524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29405 11:36:10.091749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29407 11:36:10.092211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29408 11:36:10.140847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29410 11:36:10.141617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29411 11:36:10.184952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29412 11:36:10.185331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29414 11:36:10.224370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29416 11:36:10.224819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29417 11:36:10.263989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29418 11:36:10.264433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29420 11:36:10.312651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29421 11:36:10.313124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29423 11:36:10.353444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29425 11:36:10.353916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29426 11:36:10.401336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29427 11:36:10.401799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29429 11:36:10.451492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29431 11:36:10.451963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29432 11:36:10.494471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29434 11:36:10.494950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29435 11:36:10.536762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29437 11:36:10.537239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29438 11:36:10.581827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29439 11:36:10.582229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29441 11:36:10.627046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29443 11:36:10.627514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29444 11:36:10.671213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29445 11:36:10.671661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29447 11:36:10.707825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29448 11:36:10.708273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29450 11:36:10.749427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29451 11:36:10.749933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29453 11:36:10.787648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29454 11:36:10.788076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29456 11:36:10.831777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29457 11:36:10.832217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29459 11:36:10.867579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29460 11:36:10.868087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29462 11:36:10.912997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29463 11:36:10.913564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29465 11:36:10.958497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29467 11:36:10.959125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29468 11:36:11.001476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29470 11:36:11.001951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29471 11:36:11.053957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29472 11:36:11.054438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29474 11:36:11.105982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29475 11:36:11.106471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29477 11:36:11.159647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29479 11:36:11.160063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29480 11:36:11.208508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29481 11:36:11.208992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29483 11:36:11.243808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29484 11:36:11.244378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29486 11:36:11.279101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29487 11:36:11.279635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29489 11:36:11.313620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29490 11:36:11.314173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29492 11:36:11.355331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29494 11:36:11.355803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29495 11:36:11.404675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29496 11:36:11.405071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29498 11:36:11.445427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29500 11:36:11.445899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29501 11:36:11.481831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29502 11:36:11.482275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29504 11:36:11.520549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29505 11:36:11.521005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29507 11:36:11.564242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29508 11:36:11.564672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29510 11:36:11.623620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29511 11:36:11.624049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29513 11:36:11.665781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29514 11:36:11.666166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29516 11:36:11.701838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29518 11:36:11.702325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29519 11:36:11.746281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29521 11:36:11.746775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29522 11:36:11.796363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29524 11:36:11.796831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29525 11:36:11.843965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29527 11:36:11.844451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29528 11:36:11.891288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29530 11:36:11.891764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29531 11:36:11.931452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29532 11:36:11.931906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29534 11:36:11.968552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29535 11:36:11.968999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29537 11:36:12.008960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29538 11:36:12.009392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29540 11:36:12.053054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29541 11:36:12.053507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29543 11:36:12.092352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29545 11:36:12.092819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29546 11:36:12.137536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29548 11:36:12.138013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29549 11:36:12.181858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29550 11:36:12.182298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29552 11:36:12.220045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29554 11:36:12.220504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29555 11:36:12.259271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29556 11:36:12.259681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29558 11:36:12.306952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29559 11:36:12.307510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29561 11:36:12.357434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29562 11:36:12.357849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29564 11:36:12.407594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29566 11:36:12.407941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29567 11:36:12.457138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29568 11:36:12.457528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29570 11:36:12.502659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29571 11:36:12.503241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29573 11:36:12.549496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29574 11:36:12.549940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29576 11:36:12.590296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29577 11:36:12.590683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29579 11:36:12.627626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29580 11:36:12.628067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29582 11:36:12.660594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29584 11:36:12.661057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29585 11:36:12.695962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29586 11:36:12.696517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29588 11:36:12.732873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29589 11:36:12.733347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29591 11:36:12.769547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29592 11:36:12.769983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29594 11:36:12.806241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29596 11:36:12.806616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29597 11:36:12.843623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29598 11:36:12.843992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29600 11:36:12.879242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29602 11:36:12.879711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29603 11:36:12.915114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29604 11:36:12.915595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29606 11:36:12.951512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29607 11:36:12.951896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29609 11:36:12.985887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29610 11:36:12.986334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29612 11:36:13.022314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29613 11:36:13.022742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29615 11:36:13.072586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29617 11:36:13.073076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29618 11:36:13.128336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29620 11:36:13.128779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29621 11:36:13.172370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29622 11:36:13.172778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29624 11:36:13.207986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29625 11:36:13.208408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29627 11:36:13.244898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29629 11:36:13.245360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29630 11:36:13.281579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29631 11:36:13.282103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29633 11:36:13.321324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29634 11:36:13.321910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29636 11:36:13.361006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29637 11:36:13.361504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29639 11:36:13.402332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29641 11:36:13.402976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29642 11:36:13.441510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29643 11:36:13.441918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29645 11:36:13.485339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29646 11:36:13.485796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29648 11:36:13.529914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29649 11:36:13.530371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29651 11:36:13.569320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29652 11:36:13.569750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29654 11:36:13.610533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29656 11:36:13.611010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29657 11:36:13.657745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29658 11:36:13.658192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29660 11:36:13.696340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29661 11:36:13.696788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29663 11:36:13.732169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29664 11:36:13.732615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29666 11:36:13.773168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29667 11:36:13.773595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29669 11:36:13.828285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29671 11:36:13.828764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29672 11:36:13.883492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29673 11:36:13.883949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29675 11:36:13.931749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29677 11:36:13.932241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29678 11:36:13.976968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29680 11:36:13.977442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29681 11:36:14.021722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29683 11:36:14.022183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29684 11:36:14.077396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29685 11:36:14.077859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29687 11:36:14.119229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29688 11:36:14.119667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29690 11:36:14.157977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29691 11:36:14.158372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29693 11:36:14.193496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29695 11:36:14.194100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29696 11:36:14.228496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29698 11:36:14.228868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29699 11:36:14.267793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29701 11:36:14.268551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29702 11:36:14.313062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29703 11:36:14.313495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29705 11:36:14.349224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29707 11:36:14.349845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29708 11:36:14.388479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29709 11:36:14.388953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29711 11:36:14.424182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29712 11:36:14.424602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29714 11:36:14.460021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29716 11:36:14.460496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29717 11:36:14.496264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29718 11:36:14.496701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29720 11:36:14.560961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29722 11:36:14.561420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29723 11:36:14.594689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29725 11:36:14.595056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29726 11:36:14.629860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29728 11:36:14.630542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29729 11:36:14.665066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29731 11:36:14.665486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29732 11:36:14.699510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29733 11:36:14.699905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29735 11:36:14.735196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29737 11:36:14.735972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29738 11:36:14.777494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29740 11:36:14.778127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29741 11:36:14.812046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29743 11:36:14.812613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29744 11:36:14.848718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29745 11:36:14.849271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29747 11:36:14.888026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29749 11:36:14.888678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29750 11:36:14.923606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29752 11:36:14.924067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29753 11:36:14.962955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29754 11:36:14.963379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
29756 11:36:14.999854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
29758 11:36:15.000312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
29759 11:36:15.038288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
29761 11:36:15.038762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
29762 11:36:15.085656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
29763 11:36:15.086088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
29765 11:36:15.121966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
29766 11:36:15.122414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
29768 11:36:15.159297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
29769 11:36:15.159727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
29771 11:36:15.195344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
29772 11:36:15.195755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
29774 11:36:15.231610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
29775 11:36:15.232104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
29777 11:36:15.267920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
29779 11:36:15.268404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
29780 11:36:15.301912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
29782 11:36:15.302391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
29783 11:36:15.338197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
29785 11:36:15.338671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
29786 11:36:15.374383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
29788 11:36:15.374851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
29789 11:36:15.413920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
29790 11:36:15.414364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
29792 11:36:15.459749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
29794 11:36:15.460212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
29795 11:36:15.500258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
29796 11:36:15.500694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
29798 11:36:15.556439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
29799 11:36:15.556884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
29801 11:36:15.606156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
29803 11:36:15.606583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
29804 11:36:15.654593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
29806 11:36:15.657877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
29807 11:36:15.704024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
29809 11:36:15.704500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
29810 11:36:15.753956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
29811 11:36:15.754390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
29813 11:36:15.796636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
29814 11:36:15.797038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
29816 11:36:15.847183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
29818 11:36:15.847816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
29819 11:36:15.891788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
29821 11:36:15.892292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
29822 11:36:15.940238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
29823 11:36:15.940624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
29825 11:36:15.989355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
29826 11:36:15.989802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
29828 11:36:16.032680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
29829 11:36:16.033108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
29831 11:36:16.069089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
29832 11:36:16.069542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
29834 11:36:16.115764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
29835 11:36:16.116217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
29837 11:36:16.151486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
29839 11:36:16.151916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
29840 11:36:16.187844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
29841 11:36:16.188399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
29843 11:36:16.229287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
29844 11:36:16.229675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
29846 11:36:16.265895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
29848 11:36:16.266537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
29849 11:36:16.311112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
29850 11:36:16.311566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
29852 11:36:16.350723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
29854 11:36:16.351211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
29855 11:36:16.396045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
29856 11:36:16.396474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
29858 11:36:16.433071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
29859 11:36:16.433495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
29861 11:36:16.471309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
29862 11:36:16.471740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
29864 11:36:16.516211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
29865 11:36:16.516652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
29867 11:36:16.554184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
29868 11:36:16.554740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
29870 11:36:16.593212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
29871 11:36:16.593697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
29873 11:36:16.637614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
29874 11:36:16.638076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
29876 11:36:16.680471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
29877 11:36:16.680921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
29879 11:36:16.736600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
29881 11:36:16.737062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
29882 11:36:16.772788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
29884 11:36:16.773247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
29885 11:36:16.808900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
29886 11:36:16.809307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
29888 11:36:16.845969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
29889 11:36:16.846424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
29891 11:36:16.886614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
29893 11:36:16.887133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
29894 11:36:16.935760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
29896 11:36:16.936255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
29897 11:36:16.993000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
29898 11:36:16.993424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
29900 11:36:17.041521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
29901 11:36:17.041959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
29903 11:36:17.099549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
29904 11:36:17.099949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
29906 11:36:17.156163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
29907 11:36:17.156610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
29909 11:36:17.205463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
29911 11:36:17.205970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
29912 11:36:17.253725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
29913 11:36:17.254191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
29915 11:36:17.300153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
29916 11:36:17.300557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
29918 11:36:17.342178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
29919 11:36:17.342714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
29921 11:36:17.382343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
29923 11:36:17.383031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
29924 11:36:17.433078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
29925 11:36:17.433542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
29927 11:36:17.483675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
29929 11:36:17.484152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
29930 11:36:17.541684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
29931 11:36:17.542086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
29933 11:36:17.593087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
29934 11:36:17.593445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
29936 11:36:17.631115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
29937 11:36:17.631677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
29939 11:36:17.668169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
29941 11:36:17.668931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
29942 11:36:17.724375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
29943 11:36:17.724943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
29945 11:36:17.766495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
29947 11:36:17.766989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
29948 11:36:17.811299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
29950 11:36:17.811788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
29951 11:36:17.861447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
29952 11:36:17.861893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
29954 11:36:17.899581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
29955 11:36:17.899969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
29957 11:36:17.949393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
29958 11:36:17.949824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
29960 11:36:17.983545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
29962 11:36:17.984076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
29963 11:36:18.027713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
29964 11:36:18.028110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
29966 11:36:18.074247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
29968 11:36:18.074999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
29969 11:36:18.112702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
29971 11:36:18.113201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
29972 11:36:18.169974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
29973 11:36:18.170428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
29975 11:36:18.218101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
29976 11:36:18.218530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
29978 11:36:18.256365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
29979 11:36:18.256782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
29981 11:36:18.298142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
29982 11:36:18.298623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
29984 11:36:18.341887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
29986 11:36:18.342382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
29987 11:36:18.381536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
29988 11:36:18.382112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
29990 11:36:18.427471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
29991 11:36:18.427866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
29993 11:36:18.460966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
29994 11:36:18.461350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
29996 11:36:18.494021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
29998 11:36:18.494443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
29999 11:36:18.527476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30001 11:36:18.527893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30002 11:36:18.565864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30004 11:36:18.566258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30005 11:36:18.599565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30006 11:36:18.599941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30008 11:36:18.636595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30009 11:36:18.637073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30011 11:36:18.684530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30012 11:36:18.684927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30014 11:36:18.720402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30015 11:36:18.720875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30017 11:36:18.766121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30019 11:36:18.766602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30020 11:36:18.800801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30022 11:36:18.801374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30023 11:36:18.834941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30024 11:36:18.835443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30026 11:36:18.885767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30027 11:36:18.886215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30029 11:36:18.931826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30031 11:36:18.932408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30032 11:36:18.969217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30034 11:36:18.969682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30035 11:36:19.013206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30036 11:36:19.013774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30038 11:36:19.050254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30039 11:36:19.050676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30041 11:36:19.093864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30043 11:36:19.094349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30044 11:36:19.139772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30045 11:36:19.140228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30047 11:36:19.176408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30048 11:36:19.176838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30050 11:36:19.210516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30052 11:36:19.211167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30053 11:36:19.245202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30054 11:36:19.245670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30056 11:36:19.278890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30057 11:36:19.279391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30059 11:36:19.313997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30060 11:36:19.314420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30062 11:36:19.357555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30063 11:36:19.358163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30065 11:36:19.396810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30067 11:36:19.397522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30068 11:36:19.436711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30070 11:36:19.437190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30071 11:36:19.490200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30072 11:36:19.490625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30074 11:36:19.546035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30075 11:36:19.546500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30077 11:36:19.591099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30079 11:36:19.591589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30080 11:36:19.631757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30081 11:36:19.632399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30083 11:36:19.705717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30085 11:36:19.706147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30086 11:36:19.752309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30087 11:36:19.752756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30089 11:36:19.790511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30091 11:36:19.790944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30092 11:36:19.843212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30093 11:36:19.843642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30095 11:36:19.888334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30096 11:36:19.888725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30098 11:36:19.927929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30099 11:36:19.928374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30101 11:36:19.963970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30102 11:36:19.964417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30104 11:36:19.998941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30105 11:36:19.999420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30107 11:36:20.035927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30108 11:36:20.036372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30110 11:36:20.083521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30112 11:36:20.084189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30113 11:36:20.125318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30114 11:36:20.125764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30116 11:36:20.166523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30118 11:36:20.167296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30119 11:36:20.205739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30120 11:36:20.206230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30122 11:36:20.244876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30123 11:36:20.245361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30125 11:36:20.284234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30127 11:36:20.284932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30128 11:36:20.321914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30129 11:36:20.322465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30131 11:36:20.360601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30133 11:36:20.361015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30134 11:36:20.404294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30135 11:36:20.404667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30137 11:36:20.443393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30139 11:36:20.443874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30140 11:36:20.480040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30142 11:36:20.480504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30143 11:36:20.516487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30144 11:36:20.516910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30146 11:36:20.553409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30147 11:36:20.553826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30149 11:36:20.590004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30150 11:36:20.590425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30152 11:36:20.629250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30154 11:36:20.629679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30155 11:36:20.668248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30156 11:36:20.668634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30158 11:36:20.711772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30159 11:36:20.712148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30161 11:36:20.765852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30163 11:36:20.766338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30164 11:36:20.815616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30165 11:36:20.816123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30167 11:36:20.851208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30168 11:36:20.851771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30170 11:36:20.895226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30171 11:36:20.895745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30173 11:36:20.946790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30175 11:36:20.947527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30176 11:36:21.005543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30178 11:36:21.006139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30179 11:36:21.061054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30180 11:36:21.061507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30182 11:36:21.101798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30183 11:36:21.102243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30185 11:36:21.143491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30186 11:36:21.143939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30188 11:36:21.183189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30190 11:36:21.183661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30191 11:36:21.223336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30193 11:36:21.223820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30194 11:36:21.263701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30195 11:36:21.264187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30197 11:36:21.304701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30198 11:36:21.305155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30200 11:36:21.339934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30201 11:36:21.340453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30203 11:36:21.373408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30205 11:36:21.374175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30206 11:36:21.406572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30208 11:36:21.407046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30209 11:36:21.440192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30211 11:36:21.440655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30212 11:36:21.473769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30213 11:36:21.474210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30215 11:36:21.508882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30217 11:36:21.509340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30218 11:36:21.544082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30219 11:36:21.544503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30221 11:36:21.577764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30222 11:36:21.578225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30224 11:36:21.611857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30225 11:36:21.612295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30227 11:36:21.646053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30228 11:36:21.646532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30230 11:36:21.679909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30231 11:36:21.680397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30233 11:36:21.714502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30235 11:36:21.715174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30236 11:36:21.748423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30238 11:36:21.748913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30239 11:36:21.783970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30240 11:36:21.784402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30242 11:36:21.821263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30243 11:36:21.821687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30245 11:36:21.858424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30247 11:36:21.858917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30248 11:36:21.902130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30250 11:36:21.902536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30251 11:36:21.940945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30252 11:36:21.941322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30254 11:36:21.978312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30255 11:36:21.978741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30257 11:36:22.015850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30259 11:36:22.016433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30260 11:36:22.054698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30262 11:36:22.055444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30263 11:36:22.091396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30264 11:36:22.091916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30266 11:36:22.129209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30267 11:36:22.129612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30269 11:36:22.174142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30271 11:36:22.174803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30272 11:36:22.221315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30274 11:36:22.221782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30275 11:36:22.261687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30277 11:36:22.262286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30278 11:36:22.296138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30279 11:36:22.296580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30281 11:36:22.345300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30282 11:36:22.345695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30284 11:36:22.389537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30285 11:36:22.389961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30287 11:36:22.431566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30288 11:36:22.432025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30290 11:36:22.476273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30292 11:36:22.476696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30293 11:36:22.525689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30295 11:36:22.526189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30296 11:36:22.577977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30297 11:36:22.578364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30299 11:36:22.624270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30300 11:36:22.624673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30302 11:36:22.670055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30304 11:36:22.670655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30305 11:36:22.716452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30307 11:36:22.717200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30308 11:36:22.755850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30309 11:36:22.756394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30311 11:36:22.801043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30313 11:36:22.801776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30314 11:36:22.844982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30315 11:36:22.845369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30317 11:36:22.890480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30319 11:36:22.890959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30320 11:36:22.935686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30321 11:36:22.936121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30323 11:36:22.981329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30325 11:36:22.981800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30326 11:36:23.020447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30327 11:36:23.020871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30329 11:36:23.059971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30330 11:36:23.060390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30332 11:36:23.113727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30333 11:36:23.114157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30335 11:36:23.159475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30336 11:36:23.159914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30338 11:36:23.208212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30339 11:36:23.208641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30341 11:36:23.259737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30342 11:36:23.260150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30344 11:36:23.305241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30345 11:36:23.305694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30347 11:36:23.350654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30349 11:36:23.351122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30350 11:36:23.403287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30351 11:36:23.403869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30353 11:36:23.441710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30355 11:36:23.442173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30356 11:36:23.483261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30358 11:36:23.483741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30359 11:36:23.527904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30360 11:36:23.528382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30362 11:36:23.569620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30363 11:36:23.570106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30365 11:36:23.615101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30366 11:36:23.615674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30368 11:36:23.661015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30370 11:36:23.661777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30371 11:36:23.704374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30373 11:36:23.704910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30374 11:36:23.748876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30376 11:36:23.749542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30377 11:36:23.797131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30379 11:36:23.797894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30380 11:36:23.844276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30381 11:36:23.844712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30383 11:36:23.886113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30384 11:36:23.886668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30386 11:36:23.928058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30388 11:36:23.928439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30389 11:36:23.970362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30391 11:36:23.971113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30392 11:36:24.015755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30394 11:36:24.016274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30395 11:36:24.058125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30396 11:36:24.058543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30398 11:36:24.109627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30399 11:36:24.110131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30401 11:36:24.145097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30402 11:36:24.145540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30404 11:36:24.181143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30405 11:36:24.181656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30407 11:36:24.217298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30409 11:36:24.217919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30410 11:36:24.255146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30411 11:36:24.255599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30413 11:36:24.309248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30414 11:36:24.309690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30416 11:36:24.353277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30417 11:36:24.353689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30419 11:36:24.400133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30420 11:36:24.400597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30422 11:36:24.439235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30423 11:36:24.439688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30425 11:36:24.478167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30426 11:36:24.478728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30428 11:36:24.536734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30430 11:36:24.537205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30431 11:36:24.579866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30433 11:36:24.580399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30434 11:36:24.621992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30435 11:36:24.622384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30437 11:36:24.662765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30438 11:36:24.663250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30440 11:36:24.711689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30441 11:36:24.712140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30443 11:36:24.751815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30445 11:36:24.753829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30446 11:36:24.814940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30448 11:36:24.815405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30449 11:36:24.851754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30451 11:36:24.852214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30452 11:36:24.887247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30453 11:36:24.887808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30455 11:36:24.923550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30456 11:36:24.924022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30458 11:36:24.959422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30459 11:36:24.959829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30461 11:36:24.996204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30462 11:36:24.996490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30464 11:36:25.033729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30465 11:36:25.034088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30467 11:36:25.073055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30468 11:36:25.073397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30470 11:36:25.119575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30471 11:36:25.119936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30473 11:36:25.160553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30475 11:36:25.161231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30476 11:36:25.196966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30477 11:36:25.197354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30479 11:36:25.236092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30480 11:36:25.236533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30482 11:36:25.271605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30483 11:36:25.272034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30485 11:36:25.308375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30487 11:36:25.308941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30488 11:36:25.343467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30490 11:36:25.343912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30491 11:36:25.379299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30492 11:36:25.379750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30494 11:36:25.415132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30496 11:36:25.415598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30497 11:36:25.451327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30499 11:36:25.451796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30500 11:36:25.492865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30501 11:36:25.493306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30503 11:36:25.528695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30505 11:36:25.529209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30506 11:36:25.567454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30507 11:36:25.567944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30509 11:36:25.600542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30511 11:36:25.601131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30512 11:36:25.633531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30513 11:36:25.633997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30515 11:36:25.665762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30516 11:36:25.666151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30518 11:36:25.703671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30520 11:36:25.704313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30521 11:36:25.736829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30523 11:36:25.737408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30524 11:36:25.768891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30526 11:36:25.769485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30527 11:36:25.801812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30529 11:36:25.802414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30530 11:36:25.832882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30532 11:36:25.833427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30533 11:36:25.863823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30534 11:36:25.864362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30536 11:36:25.898084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30538 11:36:25.898472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30539 11:36:25.934161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30540 11:36:25.934554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30542 11:36:25.967103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30544 11:36:25.967678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30545 11:36:25.998906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30546 11:36:25.999375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30548 11:36:26.031743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30549 11:36:26.032221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30551 11:36:26.063879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30552 11:36:26.064345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30554 11:36:26.095480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30555 11:36:26.095933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30557 11:36:26.126508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30559 11:36:26.126977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30560 11:36:26.159590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30561 11:36:26.159986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30563 11:36:26.191167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30564 11:36:26.191584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30566 11:36:26.222639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30568 11:36:26.223075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30569 11:36:26.254706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30571 11:36:26.255344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30572 11:36:26.285383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30573 11:36:26.285879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30575 11:36:26.317836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30577 11:36:26.318361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30578 11:36:26.348693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30579 11:36:26.349076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30581 11:36:26.379657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30583 11:36:26.380074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30584 11:36:26.412175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30585 11:36:26.412558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30587 11:36:26.443570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30588 11:36:26.443944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30590 11:36:26.474382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30592 11:36:26.474833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30593 11:36:26.505202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30594 11:36:26.505566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30596 11:36:26.537237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30597 11:36:26.537651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30599 11:36:26.568460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30600 11:36:26.568871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30602 11:36:26.600801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30603 11:36:26.601220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30605 11:36:26.634362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30607 11:36:26.634833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30608 11:36:26.667004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30609 11:36:26.667407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30611 11:36:26.699285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30612 11:36:26.699713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30614 11:36:26.731555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30615 11:36:26.731980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30617 11:36:26.763185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30618 11:36:26.763572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30620 11:36:26.794606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30622 11:36:26.794985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30623 11:36:26.826301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30624 11:36:26.826638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30626 11:36:26.857380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30627 11:36:26.857728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30629 11:36:26.889353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30630 11:36:26.889676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30632 11:36:26.922770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30633 11:36:26.923166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30635 11:36:26.957231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30637 11:36:26.957817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30638 11:36:26.991594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30640 11:36:26.992199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30641 11:36:27.027046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30642 11:36:27.027444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30644 11:36:27.062260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30645 11:36:27.062676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30647 11:36:27.096628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30648 11:36:27.097059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30650 11:36:27.132337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30651 11:36:27.132757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30653 11:36:27.168788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30655 11:36:27.169233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30656 11:36:27.202892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30658 11:36:27.203342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30659 11:36:27.237984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30660 11:36:27.238468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30662 11:36:27.271955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30664 11:36:27.272440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30665 11:36:27.306162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30666 11:36:27.306585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30668 11:36:27.340703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30670 11:36:27.341268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30671 11:36:27.375173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30673 11:36:27.375718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30674 11:36:27.409039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30676 11:36:27.409609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30677 11:36:27.443128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30678 11:36:27.443547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30680 11:36:27.477046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30682 11:36:27.477549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30683 11:36:27.509922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30684 11:36:27.510351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30686 11:36:27.543933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30687 11:36:27.544410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30689 11:36:27.581160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30691 11:36:27.581834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30692 11:36:27.616126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30694 11:36:27.616757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30695 11:36:27.650047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30696 11:36:27.650532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30698 11:36:27.685373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30699 11:36:27.685866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30701 11:36:27.719317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30702 11:36:27.719792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30704 11:36:27.753046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30706 11:36:27.753693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30707 11:36:27.786486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30709 11:36:27.787128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30710 11:36:27.819998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30711 11:36:27.820470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30713 11:36:27.855409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30715 11:36:27.856044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30716 11:36:27.889487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30717 11:36:27.889980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30719 11:36:27.924248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30721 11:36:27.924701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30722 11:36:27.959162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30724 11:36:27.959614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30725 11:36:27.993770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30727 11:36:27.994238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30728 11:36:28.028145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30729 11:36:28.028617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30731 11:36:28.061956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30732 11:36:28.062379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30734 11:36:28.097559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30735 11:36:28.098042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30737 11:36:28.132584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30739 11:36:28.133129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30740 11:36:28.168176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30741 11:36:28.168600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30743 11:36:28.204895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30745 11:36:28.205413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30746 11:36:28.240313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30747 11:36:28.240772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30749 11:36:28.275125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30750 11:36:28.275567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30752 11:36:28.309543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
30753 11:36:28.309962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30755 11:36:28.342928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
30757 11:36:28.343501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
30758 11:36:28.378144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
30759 11:36:28.378620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
30761 11:36:28.410524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
30763 11:36:28.411140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
30764 11:36:28.441584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
30765 11:36:28.441996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
30767 11:36:28.472382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
30768 11:36:28.472785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
30770 11:36:28.503735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
30771 11:36:28.504178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
30773 11:36:28.534411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
30775 11:36:28.534940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
30776 11:36:28.565540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
30778 11:36:28.565935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
30779 11:36:28.597393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
30780 11:36:28.597859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
30782 11:36:28.629278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
30783 11:36:28.629692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
30785 11:36:28.660422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
30786 11:36:28.660828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
30788 11:36:28.691454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
30789 11:36:28.691822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
30791 11:36:28.722099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
30792 11:36:28.722531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
30794 11:36:28.753492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
30795 11:36:28.753838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
30797 11:36:28.783975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
30798 11:36:28.784386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
30800 11:36:28.815269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
30801 11:36:28.815610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
30803 11:36:28.846141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
30804 11:36:28.846525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
30806 11:36:28.876596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
30808 11:36:28.877090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
30809 11:36:28.908131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
30810 11:36:28.908513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
30812 11:36:28.939376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
30813 11:36:28.939751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
30815 11:36:28.969818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
30816 11:36:28.970206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
30818 11:36:29.002313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
30820 11:36:29.002786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
30821 11:36:29.033510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
30822 11:36:29.033946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
30824 11:36:29.064386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
30825 11:36:29.064819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
30827 11:36:29.095971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
30828 11:36:29.096449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
30830 11:36:29.127704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
30831 11:36:29.128158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
30833 11:36:29.159261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
30835 11:36:29.159805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
30836 11:36:29.191221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
30838 11:36:29.191786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
30839 11:36:29.222940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
30841 11:36:29.223490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
30842 11:36:29.254110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
30844 11:36:29.254648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
30845 11:36:29.286855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
30846 11:36:29.287345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
30848 11:36:29.319098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
30849 11:36:29.319578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
30851 11:36:29.350586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
30853 11:36:29.351103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
30854 11:36:29.381534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
30856 11:36:29.382052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
30857 11:36:29.412495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
30858 11:36:29.412938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
30860 11:36:29.443992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
30862 11:36:29.444536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
30863 11:36:29.475195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
30864 11:36:29.475682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
30866 11:36:29.506334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
30868 11:36:29.506833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
30869 11:36:29.537813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
30871 11:36:29.538366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
30872 11:36:29.570167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
30874 11:36:29.570613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
30875 11:36:29.601940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
30876 11:36:29.602334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
30878 11:36:29.633640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
30879 11:36:29.634065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
30881 11:36:29.665369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
30883 11:36:29.665813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
30884 11:36:29.697766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
30886 11:36:29.698209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
30887 11:36:29.728955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
30888 11:36:29.729368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
30890 11:36:29.762048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
30892 11:36:29.762517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
30893 11:36:29.793400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
30895 11:36:29.793846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
30896 11:36:29.824626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
30898 11:36:29.825053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
30899 11:36:29.857215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
30900 11:36:29.857659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
30902 11:36:29.908747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
30903 11:36:29.909177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
30905 11:36:29.941361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
30907 11:36:29.941816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
30908 11:36:29.973345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
30909 11:36:29.973746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
30911 11:36:30.004464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
30913 11:36:30.005013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
30914 11:36:30.035435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
30915 11:36:30.035881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
30917 11:36:30.067288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
30919 11:36:30.067852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
30920 11:36:30.098601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
30922 11:36:30.099275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
30923 11:36:30.130083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
30924 11:36:30.130505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
30926 11:36:30.161198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
30928 11:36:30.161687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
30929 11:36:30.192301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
30930 11:36:30.192684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
30932 11:36:30.223159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
30933 11:36:30.223546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
30935 11:36:30.254507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
30937 11:36:30.255055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
30938 11:36:30.285573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
30940 11:36:30.286074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
30941 11:36:30.316618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
30943 11:36:30.317166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
30944 11:36:30.349894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
30946 11:36:30.350428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
30947 11:36:30.381027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
30949 11:36:30.381436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
30950 11:36:30.411684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
30952 11:36:30.412096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
30953 11:36:30.442835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
30954 11:36:30.443236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
30956 11:36:30.473701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
30958 11:36:30.474180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
30959 11:36:30.505227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
30960 11:36:30.505620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
30962 11:36:30.536455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
30963 11:36:30.536935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
30965 11:36:30.568526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
30966 11:36:30.569008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
30968 11:36:30.600326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
30969 11:36:30.600806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
30971 11:36:30.632053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
30972 11:36:30.632536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
30974 11:36:30.663672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
30976 11:36:30.664289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
30977 11:36:30.694580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
30979 11:36:30.695237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
30980 11:36:30.726185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
30982 11:36:30.726811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
30983 11:36:30.757425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
30984 11:36:30.757889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
30986 11:36:30.789202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
30988 11:36:30.789782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
30989 11:36:30.820466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
30990 11:36:30.820908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
30992 11:36:30.851743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
30993 11:36:30.852189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
30995 11:36:30.884283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
30996 11:36:30.884767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
30998 11:36:30.916050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31000 11:36:30.916596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31001 11:36:30.947548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31002 11:36:30.947956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31004 11:36:30.979039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31005 11:36:30.979447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31007 11:36:31.010173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31008 11:36:31.010651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31010 11:36:31.041886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31012 11:36:31.042484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31013 11:36:31.073377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31015 11:36:31.073966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31016 11:36:31.104633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31018 11:36:31.105179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31019 11:36:31.136061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31020 11:36:31.136495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31022 11:36:31.167341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31024 11:36:31.167864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31025 11:36:31.198667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31026 11:36:31.199141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31028 11:36:31.231291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31029 11:36:31.231745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31031 11:36:31.262978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31033 11:36:31.263542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31034 11:36:31.296075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31035 11:36:31.296505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31037 11:36:31.328589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31039 11:36:31.329131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31040 11:36:31.360464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31042 11:36:31.360994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31043 11:36:31.391893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31045 11:36:31.392324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31046 11:36:31.423556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31047 11:36:31.423998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31049 11:36:31.454100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31050 11:36:31.454522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31052 11:36:31.486229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31054 11:36:31.486800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31055 11:36:31.517814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31057 11:36:31.518440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31058 11:36:31.548679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31059 11:36:31.549081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31061 11:36:31.579691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31062 11:36:31.580050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31064 11:36:31.611898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31065 11:36:31.612303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31067 11:36:31.643679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31069 11:36:31.644067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31070 11:36:31.674962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31071 11:36:31.675318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31073 11:36:31.706616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31075 11:36:31.707096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31076 11:36:31.738707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31078 11:36:31.739215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31079 11:36:31.770583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31081 11:36:31.771145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31082 11:36:31.803449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31083 11:36:31.803856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31085 11:36:31.835917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31086 11:36:31.836379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31088 11:36:31.870486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31090 11:36:31.870964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31091 11:36:31.903046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31092 11:36:31.903430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31094 11:36:31.935142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31096 11:36:31.935493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31097 11:36:31.967192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31098 11:36:31.967586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31100 11:36:31.998784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31102 11:36:31.999319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31103 11:36:32.029949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31104 11:36:32.030349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31106 11:36:32.061682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31108 11:36:32.062043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31109 11:36:32.093461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31110 11:36:32.093902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31112 11:36:32.125009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31114 11:36:32.125575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31115 11:36:32.156446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31116 11:36:32.156826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31118 11:36:32.188063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31119 11:36:32.188455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31121 11:36:32.219496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31123 11:36:32.219995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31124 11:36:32.251368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31126 11:36:32.251933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31127 11:36:32.283178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31128 11:36:32.283572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31130 11:36:32.314151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31131 11:36:32.314536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31133 11:36:32.345691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31134 11:36:32.346084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31136 11:36:32.377952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31137 11:36:32.378331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31139 11:36:32.409342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31140 11:36:32.409699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31142 11:36:32.441041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31144 11:36:32.441606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31145 11:36:32.472440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31147 11:36:32.473006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31148 11:36:32.503641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31150 11:36:32.504197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31151 11:36:32.535338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31153 11:36:32.535895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31154 11:36:32.567145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31155 11:36:32.567493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31157 11:36:32.598870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31158 11:36:32.599223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31160 11:36:32.631559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31162 11:36:32.631960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31163 11:36:32.663308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31164 11:36:32.663692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31166 11:36:32.694953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31168 11:36:32.695424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31169 11:36:32.726292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31171 11:36:32.726851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31172 11:36:32.759015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31173 11:36:32.759426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31175 11:36:32.790662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31177 11:36:32.791088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31178 11:36:32.823371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31179 11:36:32.823785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31181 11:36:32.855826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31183 11:36:32.856368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31184 11:36:32.887340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31186 11:36:32.887909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31187 11:36:32.918250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31189 11:36:32.918805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31190 11:36:32.949792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31192 11:36:32.950331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31193 11:36:32.981767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31195 11:36:32.982309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31196 11:36:33.013367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31198 11:36:33.013802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31199 11:36:33.045607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31200 11:36:33.046019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31202 11:36:33.077671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31204 11:36:33.078281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31205 11:36:33.111647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31207 11:36:33.112208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31208 11:36:33.147810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31209 11:36:33.148234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31211 11:36:33.184751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31213 11:36:33.185253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31214 11:36:33.221405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31215 11:36:33.221964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31217 11:36:33.258346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31219 11:36:33.258799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31220 11:36:33.299545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31222 11:36:33.300000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31223 11:36:33.333900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31224 11:36:33.334237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31226 11:36:33.369292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31228 11:36:33.369748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31229 11:36:33.403912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31231 11:36:33.404437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31232 11:36:33.439697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31233 11:36:33.440119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31235 11:36:33.474051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31237 11:36:33.474523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31238 11:36:33.508192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31240 11:36:33.508720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31241 11:36:33.543806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31242 11:36:33.544292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31244 11:36:33.578294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31246 11:36:33.578676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31247 11:36:33.612632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31249 11:36:33.613127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31250 11:36:33.647723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31251 11:36:33.648174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31253 11:36:33.681634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31255 11:36:33.682151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31256 11:36:33.716464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31258 11:36:33.716952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31259 11:36:33.751204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31261 11:36:33.751742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31262 11:36:33.784981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31264 11:36:33.785504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31265 11:36:33.819352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31267 11:36:33.819824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31268 11:36:33.853187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31270 11:36:33.853723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31271 11:36:33.888459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31273 11:36:33.889097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31274 11:36:33.923374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31275 11:36:33.923669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31277 11:36:33.957826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31279 11:36:33.958149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31280 11:36:33.992017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31281 11:36:33.992393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31283 11:36:34.026864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31284 11:36:34.027210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31286 11:36:34.060922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31287 11:36:34.061266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31289 11:36:34.097509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31290 11:36:34.097912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31292 11:36:34.132011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31293 11:36:34.132345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31295 11:36:34.166420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31297 11:36:34.167080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31298 11:36:34.203357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31300 11:36:34.203826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31301 11:36:34.235173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31302 11:36:34.235521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31304 11:36:34.266539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31306 11:36:34.266932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31307 11:36:34.301474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31308 11:36:34.301911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31310 11:36:34.332481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31312 11:36:34.332884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31313 11:36:34.363722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31315 11:36:34.364257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31316 11:36:34.395044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31317 11:36:34.395508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31319 11:36:34.425978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31320 11:36:34.426462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31322 11:36:34.457478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31323 11:36:34.457939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31325 11:36:34.489861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31326 11:36:34.490402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31328 11:36:34.522864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31329 11:36:34.523402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31331 11:36:34.554074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31333 11:36:34.554529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31334 11:36:34.585396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31335 11:36:34.585813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31337 11:36:34.616962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31339 11:36:34.617531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31340 11:36:34.647971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31342 11:36:34.648517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31343 11:36:34.679082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31344 11:36:34.679483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31346 11:36:34.709927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31348 11:36:34.710334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31349 11:36:34.741350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31350 11:36:34.741869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31352 11:36:34.773208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31353 11:36:34.773666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31355 11:36:34.804379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31357 11:36:34.804914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31358 11:36:34.835603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31360 11:36:34.836133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31361 11:36:34.866600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31363 11:36:34.867129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31364 11:36:34.897956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31365 11:36:34.898408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31367 11:36:34.929458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31368 11:36:34.929935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31370 11:36:34.960918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31372 11:36:34.961413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31373 11:36:34.991955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31375 11:36:34.992467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31376 11:36:35.045304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31378 11:36:35.045838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31379 11:36:35.076297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31380 11:36:35.076619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31382 11:36:35.107958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31384 11:36:35.108513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31385 11:36:35.140134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31387 11:36:35.140680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31388 11:36:35.171521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31390 11:36:35.172144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31391 11:36:35.203063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31392 11:36:35.203516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31394 11:36:35.233932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31395 11:36:35.234411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31397 11:36:35.265485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31398 11:36:35.265964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31400 11:36:35.297448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31402 11:36:35.297999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31403 11:36:35.329412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31404 11:36:35.329870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31406 11:36:35.360760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31407 11:36:35.361203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31409 11:36:35.392236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31411 11:36:35.392778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31412 11:36:35.423453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31413 11:36:35.423888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31415 11:36:35.454025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31416 11:36:35.454381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31418 11:36:35.488253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31419 11:36:35.488660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31421 11:36:35.520065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31423 11:36:35.520569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31424 11:36:35.552055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31425 11:36:35.552437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31427 11:36:35.583997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31429 11:36:35.584506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31430 11:36:35.616495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31431 11:36:35.616969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31433 11:36:35.650571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31435 11:36:35.651155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31436 11:36:35.683355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31437 11:36:35.683852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31439 11:36:35.716195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31441 11:36:35.716814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31442 11:36:35.748457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31443 11:36:35.748932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31445 11:36:35.781332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31446 11:36:35.781804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31448 11:36:35.813014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31449 11:36:35.813411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31451 11:36:35.845022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31452 11:36:35.845452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31454 11:36:35.875879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31455 11:36:35.876352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31457 11:36:35.908152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31459 11:36:35.908713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31460 11:36:35.940191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31462 11:36:35.940737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31463 11:36:35.971651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31465 11:36:35.972205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31466 11:36:36.003563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31467 11:36:36.003951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31469 11:36:36.035502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31471 11:36:36.036000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31472 11:36:36.065966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31473 11:36:36.066382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31475 11:36:36.097852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31477 11:36:36.098368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31478 11:36:36.129469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31479 11:36:36.129865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31481 11:36:36.162642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31483 11:36:36.163238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31484 11:36:36.197567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31485 11:36:36.197972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31487 11:36:36.228324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31488 11:36:36.228785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31490 11:36:36.259757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31492 11:36:36.260304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31493 11:36:36.292011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31494 11:36:36.292473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31496 11:36:36.324221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31498 11:36:36.324788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31499 11:36:36.356076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31500 11:36:36.356538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31502 11:36:36.387123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31503 11:36:36.387482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31505 11:36:36.418040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31507 11:36:36.418516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31508 11:36:36.449167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31509 11:36:36.449553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31511 11:36:36.479679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31512 11:36:36.480073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31514 11:36:36.511355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31515 11:36:36.511734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31517 11:36:36.542381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31519 11:36:36.542878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31520 11:36:36.574619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31522 11:36:36.575107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31523 11:36:36.605392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31524 11:36:36.605800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31526 11:36:36.636231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31527 11:36:36.636623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31529 11:36:36.667419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31531 11:36:36.668008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31532 11:36:36.698220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31533 11:36:36.698632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31535 11:36:36.729242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31537 11:36:36.729732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31538 11:36:36.760268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31539 11:36:36.760759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31541 11:36:36.792201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31543 11:36:36.792737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31544 11:36:36.823716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31545 11:36:36.824136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31547 11:36:36.856669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31549 11:36:36.857140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31550 11:36:36.887695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31551 11:36:36.888092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31553 11:36:36.919258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31555 11:36:36.919764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31556 11:36:36.949758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31557 11:36:36.950138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31559 11:36:36.980523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31560 11:36:36.980872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31562 11:36:37.012064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31563 11:36:37.012461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31565 11:36:37.043126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31566 11:36:37.043551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31568 11:36:37.074487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31570 11:36:37.074927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31571 11:36:37.106597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31573 11:36:37.107064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31574 11:36:37.139068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31575 11:36:37.139487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31577 11:36:37.171147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31579 11:36:37.171582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31580 11:36:37.202330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31582 11:36:37.202776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31583 11:36:37.234043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31585 11:36:37.234495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31586 11:36:37.265354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31587 11:36:37.265777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31589 11:36:37.297486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31591 11:36:37.297932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31592 11:36:37.329367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31593 11:36:37.329778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31595 11:36:37.361680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31596 11:36:37.362087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31598 11:36:37.393284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31600 11:36:37.393722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31601 11:36:37.424554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31602 11:36:37.424956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31604 11:36:37.456703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31606 11:36:37.457273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31607 11:36:37.488043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31609 11:36:37.488573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31610 11:36:37.519656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31611 11:36:37.520059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31613 11:36:37.550527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31615 11:36:37.551049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31616 11:36:37.582616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31618 11:36:37.583100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31619 11:36:37.613515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31621 11:36:37.614011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31622 11:36:37.644486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31623 11:36:37.644914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31625 11:36:37.675542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31626 11:36:37.675917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31628 11:36:37.706050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31629 11:36:37.706408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31631 11:36:37.737060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31632 11:36:37.737464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31634 11:36:37.768429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31635 11:36:37.768775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31637 11:36:37.799663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31638 11:36:37.800074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31640 11:36:37.831555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31641 11:36:37.831962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31643 11:36:37.862195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31645 11:36:37.862676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31646 11:36:37.893344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31647 11:36:37.893738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31649 11:36:37.924384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31650 11:36:37.924770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31652 11:36:37.954935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31653 11:36:37.955341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31655 11:36:37.986203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31657 11:36:37.986644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31658 11:36:38.018277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31659 11:36:38.018736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31661 11:36:38.049533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31663 11:36:38.050090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31664 11:36:38.080522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31666 11:36:38.081061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31667 11:36:38.113534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31669 11:36:38.113998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31670 11:36:38.144102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31671 11:36:38.144536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31673 11:36:38.177329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31674 11:36:38.177798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31676 11:36:38.212818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31678 11:36:38.213380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31679 11:36:38.248117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31681 11:36:38.248675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31682 11:36:38.284171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31684 11:36:38.284789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31685 11:36:38.316076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31686 11:36:38.316539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31688 11:36:38.347560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31690 11:36:38.347999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31691 11:36:38.379206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31692 11:36:38.379686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31694 11:36:38.410176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31696 11:36:38.410730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31697 11:36:38.440783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31699 11:36:38.441272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31700 11:36:38.471559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31701 11:36:38.471965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31703 11:36:38.502959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31705 11:36:38.503443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31706 11:36:38.534041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31708 11:36:38.534511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31709 11:36:38.565171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31711 11:36:38.565810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31712 11:36:38.597349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31713 11:36:38.597780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31715 11:36:38.628370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31717 11:36:38.628932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31718 11:36:38.659136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31720 11:36:38.659657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31721 11:36:38.690540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31723 11:36:38.691114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31724 11:36:38.721717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31725 11:36:38.722106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31727 11:36:38.755566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31729 11:36:38.756001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31730 11:36:38.788874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31732 11:36:38.789271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31733 11:36:38.822369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31735 11:36:38.822768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31736 11:36:38.857977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31737 11:36:38.858414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31739 11:36:38.892744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31740 11:36:38.893184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31742 11:36:38.927375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31743 11:36:38.927777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31745 11:36:38.961011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31746 11:36:38.961446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31748 11:36:38.994381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31749 11:36:38.994795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31751 11:36:39.028728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31753 11:36:39.029299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31754 11:36:39.063009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
31755 11:36:39.063426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
31757 11:36:39.096492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
31758 11:36:39.096857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
31760 11:36:39.130130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
31761 11:36:39.130496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
31763 11:36:39.164059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
31765 11:36:39.164631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
31766 11:36:39.198981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
31768 11:36:39.199602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
31769 11:36:39.233042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
31770 11:36:39.233521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
31772 11:36:39.267046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
31774 11:36:39.267700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
31775 11:36:39.300373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
31776 11:36:39.300869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
31778 11:36:39.334638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
31780 11:36:39.335192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
31781 11:36:39.368458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
31782 11:36:39.368869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
31784 11:36:39.402966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
31786 11:36:39.403422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
31787 11:36:39.436464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
31788 11:36:39.436903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
31790 11:36:39.470492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
31792 11:36:39.470969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
31793 11:36:39.504312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
31795 11:36:39.504761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
31796 11:36:39.536323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
31797 11:36:39.536788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
31799 11:36:39.567858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
31800 11:36:39.568279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
31802 11:36:39.599629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
31804 11:36:39.600129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
31805 11:36:39.630702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
31806 11:36:39.631100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
31808 11:36:39.662236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
31810 11:36:39.662689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
31811 11:36:39.694090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
31812 11:36:39.694504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
31814 11:36:39.725193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
31815 11:36:39.725586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
31817 11:36:39.769815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
31818 11:36:39.770343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
31820 11:36:39.811642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
31821 11:36:39.812138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
31823 11:36:39.845667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
31824 11:36:39.846096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
31826 11:36:39.879580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
31828 11:36:39.879940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
31829 11:36:39.911881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
31830 11:36:39.912339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
31832 11:36:39.943744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
31833 11:36:39.944155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
31835 11:36:39.974976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
31837 11:36:39.975523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
31838 11:36:40.006107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
31839 11:36:40.006542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
31841 11:36:40.037622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
31843 11:36:40.038080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
31844 11:36:40.068443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
31845 11:36:40.068775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
31847 11:36:40.099448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
31848 11:36:40.099793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
31850 11:36:40.151961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
31851 11:36:40.152398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
31853 11:36:40.183004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
31854 11:36:40.183352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
31856 11:36:40.213866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
31857 11:36:40.214207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
31859 11:36:40.244610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
31861 11:36:40.245034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
31862 11:36:40.275497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
31864 11:36:40.276071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
31865 11:36:40.306512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
31867 11:36:40.307083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
31868 11:36:40.337537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
31869 11:36:40.338005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
31871 11:36:40.368139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
31873 11:36:40.368626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
31874 11:36:40.398937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
31876 11:36:40.399425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
31877 11:36:40.429214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
31879 11:36:40.429738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
31880 11:36:40.459869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
31881 11:36:40.460208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
31883 11:36:40.490627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
31885 11:36:40.491027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
31886 11:36:40.520995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
31887 11:36:40.521404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
31889 11:36:40.552084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
31890 11:36:40.552479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
31892 11:36:40.583568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
31894 11:36:40.584005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
31895 11:36:40.614399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
31897 11:36:40.614843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
31898 11:36:40.645719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
31900 11:36:40.646268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
31901 11:36:40.676660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
31902 11:36:40.677109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
31904 11:36:40.708052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
31905 11:36:40.708452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
31907 11:36:40.739798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
31909 11:36:40.740355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
31910 11:36:40.771255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
31911 11:36:40.771734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
31913 11:36:40.801887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
31914 11:36:40.802338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
31916 11:36:40.832817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
31917 11:36:40.833254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
31919 11:36:40.863705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
31920 11:36:40.864142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
31922 11:36:40.895672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
31924 11:36:40.896211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
31925 11:36:40.927440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
31926 11:36:40.927872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
31928 11:36:40.960152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
31930 11:36:40.960600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
31931 11:36:40.991929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
31932 11:36:40.992343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
31934 11:36:41.024169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
31935 11:36:41.024605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
31937 11:36:41.057389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
31939 11:36:41.057958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
31940 11:36:41.089052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
31942 11:36:41.089585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
31943 11:36:41.122493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
31945 11:36:41.122856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
31946 11:36:41.153963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
31947 11:36:41.154421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
31949 11:36:41.185206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
31950 11:36:41.185669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
31952 11:36:41.216494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
31954 11:36:41.217037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
31955 11:36:41.248033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
31957 11:36:41.248572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
31958 11:36:41.279988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
31959 11:36:41.280459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
31961 11:36:41.314449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
31963 11:36:41.314914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
31964 11:36:41.346917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
31966 11:36:41.347369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
31967 11:36:41.379081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
31969 11:36:41.379520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
31970 11:36:41.410106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
31971 11:36:41.410514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
31973 11:36:41.441238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
31974 11:36:41.441700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
31976 11:36:41.472407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
31977 11:36:41.472871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
31979 11:36:41.514111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
31981 11:36:41.514659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
31982 11:36:41.560076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
31984 11:36:41.560640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
31985 11:36:41.593350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
31986 11:36:41.593751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
31988 11:36:41.627700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
31989 11:36:41.628099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
31991 11:36:41.660497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
31993 11:36:41.660899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
31994 11:36:41.691816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
31995 11:36:41.692204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
31997 11:36:41.723994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
31998 11:36:41.724395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32000 11:36:41.755863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32001 11:36:41.756286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32003 11:36:41.787188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32005 11:36:41.787616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32006 11:36:41.817996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32008 11:36:41.818533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32009 11:36:41.849251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32010 11:36:41.849687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32012 11:36:41.880327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32014 11:36:41.880838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32015 11:36:41.911335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32017 11:36:41.911912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32018 11:36:41.941562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32020 11:36:41.942071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32021 11:36:41.972479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32023 11:36:41.972947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32024 11:36:42.004214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32026 11:36:42.004707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32027 11:36:42.035162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32028 11:36:42.035561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32030 11:36:42.065520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32031 11:36:42.065878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32033 11:36:42.095975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32035 11:36:42.096354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32036 11:36:42.126697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32038 11:36:42.127141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32039 11:36:42.157775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32041 11:36:42.158203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32042 11:36:42.189629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32043 11:36:42.190102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32045 11:36:42.220669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32046 11:36:42.221065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32048 11:36:42.252565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32049 11:36:42.252974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32051 11:36:42.283443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32052 11:36:42.283840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32054 11:36:42.314200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32056 11:36:42.314749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32057 11:36:42.345705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32059 11:36:42.346243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32060 11:36:42.376804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32062 11:36:42.377351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32063 11:36:42.409705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32065 11:36:42.410146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32066 11:36:42.440706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32068 11:36:42.441237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32069 11:36:42.472112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32070 11:36:42.472578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32072 11:36:42.503928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32074 11:36:42.504468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32075 11:36:42.535199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32076 11:36:42.535673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32078 11:36:42.565882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32079 11:36:42.566365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32081 11:36:42.597487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32082 11:36:42.597980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32084 11:36:42.629264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32085 11:36:42.629691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32087 11:36:42.660445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32089 11:36:42.661003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32090 11:36:42.692415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32092 11:36:42.692958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32093 11:36:42.723914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32095 11:36:42.724468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32096 11:36:42.756345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32097 11:36:42.756804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32099 11:36:42.787609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32100 11:36:42.788056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32102 11:36:42.818214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32104 11:36:42.818661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32105 11:36:42.849184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32106 11:36:42.849604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32108 11:36:42.880392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32109 11:36:42.880782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32111 11:36:42.912920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32112 11:36:42.913316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32114 11:36:42.944005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32116 11:36:42.944579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32117 11:36:42.975453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32118 11:36:42.975848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32120 11:36:43.006448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32122 11:36:43.006957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32123 11:36:43.037009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32124 11:36:43.037424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32126 11:36:43.068446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32128 11:36:43.069067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32129 11:36:43.100530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32130 11:36:43.101013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32132 11:36:43.132300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32134 11:36:43.132864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32135 11:36:43.163527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32137 11:36:43.164059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32138 11:36:43.195245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32139 11:36:43.195709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32141 11:36:43.227136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32143 11:36:43.227530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32144 11:36:43.260502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32145 11:36:43.260923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32147 11:36:43.295205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32148 11:36:43.295642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32150 11:36:43.328522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32152 11:36:43.329065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32153 11:36:43.362548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32155 11:36:43.363129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32156 11:36:43.394139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32157 11:36:43.394568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32159 11:36:43.425788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32161 11:36:43.426308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32162 11:36:43.457296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32163 11:36:43.457770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32165 11:36:43.489264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32166 11:36:43.489701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32168 11:36:43.521675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32169 11:36:43.522095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32171 11:36:43.553361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32172 11:36:43.553735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32174 11:36:43.585270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32176 11:36:43.585663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32177 11:36:43.616576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32178 11:36:43.616985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32180 11:36:43.648502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32181 11:36:43.648900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32183 11:36:43.680072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32184 11:36:43.680478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32186 11:36:43.712784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32187 11:36:43.713236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32189 11:36:43.744599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32190 11:36:43.745011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32192 11:36:43.776230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32194 11:36:43.776754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32195 11:36:43.808574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32196 11:36:43.809038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32198 11:36:43.841221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32200 11:36:43.841800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32201 11:36:43.872811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32203 11:36:43.873340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32204 11:36:43.904792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32206 11:36:43.905329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32207 11:36:43.936794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32209 11:36:43.937322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32210 11:36:43.968532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32211 11:36:43.968984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32213 11:36:44.001239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32214 11:36:44.001692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32216 11:36:44.033551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32218 11:36:44.034153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32219 11:36:44.064772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32220 11:36:44.065157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32222 11:36:44.096280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32223 11:36:44.096676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32225 11:36:44.128207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32226 11:36:44.128669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32228 11:36:44.159705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32229 11:36:44.160178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32231 11:36:44.192879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32233 11:36:44.193516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32234 11:36:44.225799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32236 11:36:44.226439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32237 11:36:44.256986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32238 11:36:44.257396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32240 11:36:44.289151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32241 11:36:44.289561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32243 11:36:44.322549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32245 11:36:44.323205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32246 11:36:44.356054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32247 11:36:44.356503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32249 11:36:44.394332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32250 11:36:44.394786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32252 11:36:44.438717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32253 11:36:44.439229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32255 11:36:44.479960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32257 11:36:44.480394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32258 11:36:44.524276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32259 11:36:44.524657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32261 11:36:44.569443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32262 11:36:44.569870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32264 11:36:44.604460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32266 11:36:44.604895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32267 11:36:44.637932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32268 11:36:44.638299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32270 11:36:44.672316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32271 11:36:44.672743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32273 11:36:44.706562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32275 11:36:44.707017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32276 11:36:44.741409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32277 11:36:44.741856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32279 11:36:44.775614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32280 11:36:44.776034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32282 11:36:44.810641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32284 11:36:44.811106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32285 11:36:44.845893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32286 11:36:44.846349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32288 11:36:44.880141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32289 11:36:44.880506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32291 11:36:44.915169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32292 11:36:44.915542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32294 11:36:44.948629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32295 11:36:44.949047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32297 11:36:44.981728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32298 11:36:44.982144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32300 11:36:45.014222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32301 11:36:45.014687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32303 11:36:45.047913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32304 11:36:45.048332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32306 11:36:45.082693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32308 11:36:45.083246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32309 11:36:45.115399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32310 11:36:45.115828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32312 11:36:45.147418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32313 11:36:45.147889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32315 11:36:45.178526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32317 11:36:45.179045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32318 11:36:45.211134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32319 11:36:45.211541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32321 11:36:45.259725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32322 11:36:45.260140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32324 11:36:45.292392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32325 11:36:45.292857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32327 11:36:45.323726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32328 11:36:45.324138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32330 11:36:45.355499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32331 11:36:45.355947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32333 11:36:45.387351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32334 11:36:45.387790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32336 11:36:45.418984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32337 11:36:45.419394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32339 11:36:45.450169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32340 11:36:45.450571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32342 11:36:45.481052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32343 11:36:45.481500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32345 11:36:45.512223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32346 11:36:45.512650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32348 11:36:45.544712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32349 11:36:45.545125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32351 11:36:45.577540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32352 11:36:45.578012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32354 11:36:45.609863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32355 11:36:45.610292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32357 11:36:45.641674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32358 11:36:45.642107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32360 11:36:45.673197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32361 11:36:45.673617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32363 11:36:45.704379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32364 11:36:45.704785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32366 11:36:45.735998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32367 11:36:45.736446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32369 11:36:45.768718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32370 11:36:45.769197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32372 11:36:45.800305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32373 11:36:45.800767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32375 11:36:45.831757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32376 11:36:45.832214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32378 11:36:45.864412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32379 11:36:45.864852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32381 11:36:45.896296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32382 11:36:45.896717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32384 11:36:45.927739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32385 11:36:45.928177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32387 11:36:45.960136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32388 11:36:45.960516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32390 11:36:45.991943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32391 11:36:45.992347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32393 11:36:46.023906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32394 11:36:46.024306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32396 11:36:46.055582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32397 11:36:46.055959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32399 11:36:46.087678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32400 11:36:46.088081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32402 11:36:46.120843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32403 11:36:46.121265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32405 11:36:46.155386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32406 11:36:46.155878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32408 11:36:46.189710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32409 11:36:46.190100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32411 11:36:46.223904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32412 11:36:46.224330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32414 11:36:46.258073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32415 11:36:46.258528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32417 11:36:46.292300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32418 11:36:46.292719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32420 11:36:46.326303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32422 11:36:46.326733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32423 11:36:46.359951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32425 11:36:46.360373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32426 11:36:46.394064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32428 11:36:46.394463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32429 11:36:46.428342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32431 11:36:46.428788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32432 11:36:46.462929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32433 11:36:46.463357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32435 11:36:46.499033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32436 11:36:46.499449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32438 11:36:46.532792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32439 11:36:46.533210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32441 11:36:46.566017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32442 11:36:46.566471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32444 11:36:46.600371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32446 11:36:46.600868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32447 11:36:46.633930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32449 11:36:46.634350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32450 11:36:46.667915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32452 11:36:46.668327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32453 11:36:46.699912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32454 11:36:46.700280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32456 11:36:46.731961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32457 11:36:46.732352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32459 11:36:46.764266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32460 11:36:46.764659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32462 11:36:46.795665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32463 11:36:46.796078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32465 11:36:46.827549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32466 11:36:46.827970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32468 11:36:46.858882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32469 11:36:46.859352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32471 11:36:46.890116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32472 11:36:46.890571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32474 11:36:46.922048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32475 11:36:46.922502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32477 11:36:46.953390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32478 11:36:46.953817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32480 11:36:46.985048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32481 11:36:46.985461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32483 11:36:47.018180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32484 11:36:47.018599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32486 11:36:47.050031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32487 11:36:47.050487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32489 11:36:47.081496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32490 11:36:47.081954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32492 11:36:47.113630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32493 11:36:47.114100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32495 11:36:47.145143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32496 11:36:47.145584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32498 11:36:47.176508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32499 11:36:47.176935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32501 11:36:47.207837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32502 11:36:47.208270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32504 11:36:47.239739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32505 11:36:47.240197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32507 11:36:47.271557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32508 11:36:47.271995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32510 11:36:47.303542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32511 11:36:47.303986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32513 11:36:47.336283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32514 11:36:47.336751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32516 11:36:47.367970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32517 11:36:47.368419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32519 11:36:47.399499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32520 11:36:47.399895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32522 11:36:47.431635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32523 11:36:47.432029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32525 11:36:47.463452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32526 11:36:47.463848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32528 11:36:47.494766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32530 11:36:47.495405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32531 11:36:47.527319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32532 11:36:47.527766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32534 11:36:47.558934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32535 11:36:47.559352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32537 11:36:47.590609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32539 11:36:47.591320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32540 11:36:47.624072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32541 11:36:47.624491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32543 11:36:47.656075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32544 11:36:47.656527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32546 11:36:47.688211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32547 11:36:47.688661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32549 11:36:47.720411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32550 11:36:47.720865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32552 11:36:47.752179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32553 11:36:47.752589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32555 11:36:47.783526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32556 11:36:47.783937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32558 11:36:47.815084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32559 11:36:47.815496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32561 11:36:47.846876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32562 11:36:47.847286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32564 11:36:47.879495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32565 11:36:47.879951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32567 11:36:47.910514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32569 11:36:47.911101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32570 11:36:47.941790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32571 11:36:47.942201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32573 11:36:47.973429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32574 11:36:47.973900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32576 11:36:48.004801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32577 11:36:48.005254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32579 11:36:48.036685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32580 11:36:48.037064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32582 11:36:48.068288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32583 11:36:48.068631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32585 11:36:48.100102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32586 11:36:48.100557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32588 11:36:48.132137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32589 11:36:48.132593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32591 11:36:48.163829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32592 11:36:48.164293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32594 11:36:48.195462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32595 11:36:48.195920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32597 11:36:48.227070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32598 11:36:48.227505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32600 11:36:48.258541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32602 11:36:48.258972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32603 11:36:48.290462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32605 11:36:48.290898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32606 11:36:48.323307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32607 11:36:48.323772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32609 11:36:48.357758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32610 11:36:48.358256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32612 11:36:48.391201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32614 11:36:48.391764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32615 11:36:48.422953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32616 11:36:48.423401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32618 11:36:48.454192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32619 11:36:48.454643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32621 11:36:48.485952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32622 11:36:48.486417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32624 11:36:48.517092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32625 11:36:48.517538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32627 11:36:48.549499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32628 11:36:48.549953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32630 11:36:48.581422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32631 11:36:48.581880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32633 11:36:48.613457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32634 11:36:48.613924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32636 11:36:48.645694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32637 11:36:48.646138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32639 11:36:48.679362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32640 11:36:48.679779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32642 11:36:48.712988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32644 11:36:48.713565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32645 11:36:48.747061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32647 11:36:48.747457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32648 11:36:48.779948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32649 11:36:48.780357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32651 11:36:48.811354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32652 11:36:48.811742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32654 11:36:48.842955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32655 11:36:48.843350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32657 11:36:48.874011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32658 11:36:48.874433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32660 11:36:48.905064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32662 11:36:48.905583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32663 11:36:48.936114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32665 11:36:48.936604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32666 11:36:48.968056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32668 11:36:48.968564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32669 11:36:49.000046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32670 11:36:49.000480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32672 11:36:49.032651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32673 11:36:49.033118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32675 11:36:49.064771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32676 11:36:49.065235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32678 11:36:49.096129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32680 11:36:49.096747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32681 11:36:49.127353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32683 11:36:49.127967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32684 11:36:49.158489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32686 11:36:49.159142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32687 11:36:49.189876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32688 11:36:49.190357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32690 11:36:49.221440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32691 11:36:49.221917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32693 11:36:49.252808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32695 11:36:49.253438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32696 11:36:49.284585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32698 11:36:49.285142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32699 11:36:49.315562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32701 11:36:49.316012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32702 11:36:49.347289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32703 11:36:49.347681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32705 11:36:49.378264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32706 11:36:49.378663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32708 11:36:49.409200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32710 11:36:49.409665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32711 11:36:49.440192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32713 11:36:49.440785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32714 11:36:49.471398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32715 11:36:49.471852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32717 11:36:49.502644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32719 11:36:49.503211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32720 11:36:49.533818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32721 11:36:49.534254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32723 11:36:49.565536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32724 11:36:49.566006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32726 11:36:49.597333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32728 11:36:49.597940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32729 11:36:49.628361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32731 11:36:49.628796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32732 11:36:49.659918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32733 11:36:49.660344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32735 11:36:49.691545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32736 11:36:49.691975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32738 11:36:49.723274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32739 11:36:49.723757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32741 11:36:49.755648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32742 11:36:49.756201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32744 11:36:49.804193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32745 11:36:49.804697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32747 11:36:49.841600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32749 11:36:49.842369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32750 11:36:49.876475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32751 11:36:49.876968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32753 11:36:49.912079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
32754 11:36:49.912516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
32756 11:36:49.946462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
32758 11:36:49.946944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
32759 11:36:49.980276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
32760 11:36:49.980724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
32762 11:36:50.021260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
32764 11:36:50.021816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
32765 11:36:50.058406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
32767 11:36:50.058969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
32768 11:36:50.091698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
32769 11:36:50.092145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
32771 11:36:50.125533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
32772 11:36:50.125991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
32774 11:36:50.159270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
32775 11:36:50.159697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
32777 11:36:50.192673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
32779 11:36:50.193113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
32780 11:36:50.225559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
32781 11:36:50.226024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
32783 11:36:50.258908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
32784 11:36:50.259341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
32786 11:36:50.290780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
32787 11:36:50.291260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
32789 11:36:50.321896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
32791 11:36:50.322529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
32792 11:36:50.387464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
32793 11:36:50.387928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
32795 11:36:50.420314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
32796 11:36:50.420687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
32798 11:36:50.453912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
32800 11:36:50.454317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
32801 11:36:50.486768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
32802 11:36:50.487130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
32804 11:36:50.523406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
32805 11:36:50.523799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
32807 11:36:50.564437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
32808 11:36:50.564808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
32810 11:36:50.597571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
32811 11:36:50.598011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
32813 11:36:50.629873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
32814 11:36:50.630362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
32816 11:36:50.663408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
32817 11:36:50.663882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
32819 11:36:50.696937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
32821 11:36:50.697524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
32822 11:36:50.731867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
32824 11:36:50.732392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
32825 11:36:50.765025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
32827 11:36:50.765529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
32828 11:36:50.798212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
32829 11:36:50.798622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
32831 11:36:50.830563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
32833 11:36:50.831209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
32834 11:36:50.863003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
32835 11:36:50.863461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
32837 11:36:50.897464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
32838 11:36:50.897940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
32840 11:36:50.930524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
32842 11:36:50.930954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
32843 11:36:50.978680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
32845 11:36:50.979149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
32846 11:36:51.015562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
32847 11:36:51.015991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
32849 11:36:51.049727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
32850 11:36:51.050295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
32852 11:36:51.085464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
32853 11:36:51.085880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
32855 11:36:51.120159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
32856 11:36:51.120565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
32858 11:36:51.152539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
32859 11:36:51.153020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
32861 11:36:51.185633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
32862 11:36:51.186096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
32864 11:36:51.221211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
32865 11:36:51.221582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
32867 11:36:51.255103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
32868 11:36:51.255518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
32870 11:36:51.287509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
32871 11:36:51.287951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
32873 11:36:51.319060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
32875 11:36:51.319530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
32876 11:36:51.352655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
32877 11:36:51.353077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
32879 11:36:51.386255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
32881 11:36:51.386700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
32882 11:36:51.418829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
32883 11:36:51.419289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
32885 11:36:51.450055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
32886 11:36:51.450477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
32888 11:36:51.481308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
32890 11:36:51.481862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
32891 11:36:51.512365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
32892 11:36:51.512771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
32894 11:36:51.544217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
32895 11:36:51.544633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
32897 11:36:51.575297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
32898 11:36:51.575710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
32900 11:36:51.605979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
32901 11:36:51.606397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
32903 11:36:51.636778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
32904 11:36:51.637181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
32906 11:36:51.668137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
32908 11:36:51.668627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
32909 11:36:51.701219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
32911 11:36:51.701612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
32912 11:36:51.734218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
32913 11:36:51.734580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
32915 11:36:51.768530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
32916 11:36:51.768906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
32918 11:36:51.802321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
32920 11:36:51.802891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
32921 11:36:51.835762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
32922 11:36:51.836152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
32924 11:36:51.872061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
32926 11:36:51.872655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
32927 11:36:51.906007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
32929 11:36:51.906509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
32930 11:36:51.940301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
32931 11:36:51.940732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
32933 11:36:51.974362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
32935 11:36:51.974945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
32936 11:36:52.008182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
32938 11:36:52.008778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
32939 11:36:52.041879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
32940 11:36:52.042285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
32942 11:36:52.075562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
32943 11:36:52.075977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
32945 11:36:52.111961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
32946 11:36:52.112411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
32948 11:36:52.145641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
32950 11:36:52.146142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
32951 11:36:52.179393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
32952 11:36:52.179846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
32954 11:36:52.212833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
32956 11:36:52.213228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
32957 11:36:52.248836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
32959 11:36:52.249309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
32960 11:36:52.282208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
32962 11:36:52.282587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
32963 11:36:52.316214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
32964 11:36:52.316642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
32966 11:36:52.349220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
32968 11:36:52.349796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
32969 11:36:52.381941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
32971 11:36:52.382474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
32972 11:36:52.416460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
32974 11:36:52.417012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
32975 11:36:52.450804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
32977 11:36:52.451532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
32978 11:36:52.484982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
32979 11:36:52.485409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
32981 11:36:52.519814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
32982 11:36:52.520231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
32984 11:36:52.554379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
32985 11:36:52.554805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
32987 11:36:52.588365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
32989 11:36:52.588945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
32990 11:36:52.623577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
32991 11:36:52.623993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
32993 11:36:52.656199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
32994 11:36:52.656611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
32996 11:36:52.689116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
32998 11:36:52.689749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
32999 11:36:52.721049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33000 11:36:52.721511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33002 11:36:52.752850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33003 11:36:52.753383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33005 11:36:52.785562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33006 11:36:52.786060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33008 11:36:52.817908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33009 11:36:52.818395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33011 11:36:52.851873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33013 11:36:52.852522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33014 11:36:52.884587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33016 11:36:52.885322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33017 11:36:52.916393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33018 11:36:52.916908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33020 11:36:52.947989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33022 11:36:52.948533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33023 11:36:52.979268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33025 11:36:52.979787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33026 11:36:53.011120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33028 11:36:53.011660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33029 11:36:53.042058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33030 11:36:53.042498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33032 11:36:53.073203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33033 11:36:53.073683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33035 11:36:53.103868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33036 11:36:53.104306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33038 11:36:53.136348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33039 11:36:53.136827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33041 11:36:53.173240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33042 11:36:53.173618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33044 11:36:53.208172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33045 11:36:53.208610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33047 11:36:53.242247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33048 11:36:53.242695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33050 11:36:53.277013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33051 11:36:53.277460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33053 11:36:53.311434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33055 11:36:53.311977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33056 11:36:53.343583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33058 11:36:53.344135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33059 11:36:53.376069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33060 11:36:53.376478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33062 11:36:53.408592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33063 11:36:53.408971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33065 11:36:53.441701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33066 11:36:53.442084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33068 11:36:53.475303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33069 11:36:53.475722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33071 11:36:53.509126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33072 11:36:53.509617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33074 11:36:53.542195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33075 11:36:53.542692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33077 11:36:53.576968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33079 11:36:53.577612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33080 11:36:53.609934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33081 11:36:53.610363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33083 11:36:53.644432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33084 11:36:53.644878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33086 11:36:53.679601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33087 11:36:53.680008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33089 11:36:53.713403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33090 11:36:53.713818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33092 11:36:53.747958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33094 11:36:53.748458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33095 11:36:53.782594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33097 11:36:53.783074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33098 11:36:53.816776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33100 11:36:53.817281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33101 11:36:53.850655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33103 11:36:53.851246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33104 11:36:53.883536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33105 11:36:53.883950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33107 11:36:53.917131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33109 11:36:53.917730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33110 11:36:53.949963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33112 11:36:53.950591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33113 11:36:53.982027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33114 11:36:53.982574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33116 11:36:54.016261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33117 11:36:54.016770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33119 11:36:54.051427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33120 11:36:54.051817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33122 11:36:54.083940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33124 11:36:54.084514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33125 11:36:54.115416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33126 11:36:54.115817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33128 11:36:54.146844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33129 11:36:54.147307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33131 11:36:54.177852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33133 11:36:54.178405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33134 11:36:54.211522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33135 11:36:54.211953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33137 11:36:54.243250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33138 11:36:54.243677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33140 11:36:54.275046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33141 11:36:54.275501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33143 11:36:54.306210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33144 11:36:54.306660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33146 11:36:54.337350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33147 11:36:54.337791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33149 11:36:54.368401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33150 11:36:54.368835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33152 11:36:54.399739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33153 11:36:54.400140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33155 11:36:54.431937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33157 11:36:54.432524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33158 11:36:54.463435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33159 11:36:54.463879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33161 11:36:54.494773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33163 11:36:54.495383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33164 11:36:54.525800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33165 11:36:54.526269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33167 11:36:54.558521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33169 11:36:54.558991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33170 11:36:54.591152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33172 11:36:54.591595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33173 11:36:54.623001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33174 11:36:54.623466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33176 11:36:54.654187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33178 11:36:54.654769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33179 11:36:54.685330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33181 11:36:54.685955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33182 11:36:54.717501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33183 11:36:54.717979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33185 11:36:54.748448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33186 11:36:54.748861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33188 11:36:54.780223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33190 11:36:54.780673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33191 11:36:54.811808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33192 11:36:54.812206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33194 11:36:54.843413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33195 11:36:54.843887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33197 11:36:54.874200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33199 11:36:54.874682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33200 11:36:54.904858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33201 11:36:54.905314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33203 11:36:54.936723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33204 11:36:54.937180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33206 11:36:54.968192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33208 11:36:54.968815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33209 11:36:54.999535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33211 11:36:55.000069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33212 11:36:55.030672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33214 11:36:55.031288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33215 11:36:55.062213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33216 11:36:55.062677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33218 11:36:55.095237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33220 11:36:55.095882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33221 11:36:55.126666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33223 11:36:55.127289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33224 11:36:55.157779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33226 11:36:55.158336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33227 11:36:55.189044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33229 11:36:55.189601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33230 11:36:55.220620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33231 11:36:55.221071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33233 11:36:55.251836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33234 11:36:55.252296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33236 11:36:55.283689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33237 11:36:55.284083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33239 11:36:55.315237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33240 11:36:55.315662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33242 11:36:55.346308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33244 11:36:55.346790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33245 11:36:55.377225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33246 11:36:55.377624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33248 11:36:55.408303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33249 11:36:55.408723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33251 11:36:55.440029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33252 11:36:55.440451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33254 11:36:55.471513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33256 11:36:55.472134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33257 11:36:55.517977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33259 11:36:55.518596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33260 11:36:55.549368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33261 11:36:55.549827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33263 11:36:55.580637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33264 11:36:55.581094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33266 11:36:55.613318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33268 11:36:55.613806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33269 11:36:55.646213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33270 11:36:55.646672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33272 11:36:55.679967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33273 11:36:55.680389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33275 11:36:55.711969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33276 11:36:55.712362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33278 11:36:55.744814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33279 11:36:55.745272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33281 11:36:55.780129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33282 11:36:55.780596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33284 11:36:55.811790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33286 11:36:55.812361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33287 11:36:55.842195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33288 11:36:55.842628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33290 11:36:55.873721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33292 11:36:55.874275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33293 11:36:55.905597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33294 11:36:55.906020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33296 11:36:55.937499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33298 11:36:55.938096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33299 11:36:55.970544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33301 11:36:55.971122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33302 11:36:56.003517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33303 11:36:56.003929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33305 11:36:56.034810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33306 11:36:56.035229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33308 11:36:56.066398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33310 11:36:56.066857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33311 11:36:56.097895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33312 11:36:56.098296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33314 11:36:56.129885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33316 11:36:56.130335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33317 11:36:56.161390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33318 11:36:56.161790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33320 11:36:56.192824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33321 11:36:56.193231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33323 11:36:56.224094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33324 11:36:56.224482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33326 11:36:56.255485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33328 11:36:56.255908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33329 11:36:56.287135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33330 11:36:56.287535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33332 11:36:56.318905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33333 11:36:56.319305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33335 11:36:56.350537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33337 11:36:56.350962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33338 11:36:56.382277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33339 11:36:56.382689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33341 11:36:56.413796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33343 11:36:56.414227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33344 11:36:56.445162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33345 11:36:56.445567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33347 11:36:56.477680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33349 11:36:56.478118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33350 11:36:56.509128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33352 11:36:56.509725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33353 11:36:56.540532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33354 11:36:56.540947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33356 11:36:56.572044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33357 11:36:56.572475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33359 11:36:56.603358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33360 11:36:56.603761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33362 11:36:56.634053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33363 11:36:56.634456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33365 11:36:56.665175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33367 11:36:56.665710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33368 11:36:56.701339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33369 11:36:56.701679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33371 11:36:56.733886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33372 11:36:56.734330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33374 11:36:56.765611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33375 11:36:56.765954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33377 11:36:56.796644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33379 11:36:56.797013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33380 11:36:56.828141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33382 11:36:56.828543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33383 11:36:56.859473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33384 11:36:56.859898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33386 11:36:56.891326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33388 11:36:56.891864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33389 11:36:56.922311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33391 11:36:56.922856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33392 11:36:56.953481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33394 11:36:56.954039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33395 11:36:56.985052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33397 11:36:56.985595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33398 11:36:57.016775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33400 11:36:57.017360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33401 11:36:57.048006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33403 11:36:57.048536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33404 11:36:57.079623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33405 11:36:57.080073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33407 11:36:57.111694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33408 11:36:57.112177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33410 11:36:57.143352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33412 11:36:57.143943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33413 11:36:57.173985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33415 11:36:57.174408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33416 11:36:57.204807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33418 11:36:57.205256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33419 11:36:57.236052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33421 11:36:57.236607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33422 11:36:57.267247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33423 11:36:57.267684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33425 11:36:57.298263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33427 11:36:57.298782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33428 11:36:57.329379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33430 11:36:57.329834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33431 11:36:57.361769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33432 11:36:57.362231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33434 11:36:57.393254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33435 11:36:57.393698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33437 11:36:57.424620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33438 11:36:57.425105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33440 11:36:57.456926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33441 11:36:57.457406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33443 11:36:57.489780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33445 11:36:57.490327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33446 11:36:57.523565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33447 11:36:57.524019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33449 11:36:57.555286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33450 11:36:57.555694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33452 11:36:57.586992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33453 11:36:57.587387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33455 11:36:57.619847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33456 11:36:57.620280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33458 11:36:57.651430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33459 11:36:57.651835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33461 11:36:57.683662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33462 11:36:57.684149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33464 11:36:57.715780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33466 11:36:57.716223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33467 11:36:57.747721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33468 11:36:57.748111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33470 11:36:57.780861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33471 11:36:57.781274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33473 11:36:57.813449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33474 11:36:57.813884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33476 11:36:57.845527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33478 11:36:57.846091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33479 11:36:57.877545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33480 11:36:57.877964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33482 11:36:57.908505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33483 11:36:57.908906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33485 11:36:57.939945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33487 11:36:57.940489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33488 11:36:57.971569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33489 11:36:57.972040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33491 11:36:58.004826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33493 11:36:58.005446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33494 11:36:58.036441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33496 11:36:58.037151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33497 11:36:58.067842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33499 11:36:58.068407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33500 11:36:58.099104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33501 11:36:58.099562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33503 11:36:58.130036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33504 11:36:58.130463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33506 11:36:58.163713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33508 11:36:58.164185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33509 11:36:58.212435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33510 11:36:58.212803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33512 11:36:58.250060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33513 11:36:58.250534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33515 11:36:58.284155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33517 11:36:58.284518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33518 11:36:58.315401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33519 11:36:58.315734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33521 11:36:58.347216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33522 11:36:58.347694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33524 11:36:58.379350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33526 11:36:58.379902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33527 11:36:58.410647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33529 11:36:58.411177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33530 11:36:58.442096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33532 11:36:58.442525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33533 11:36:58.473564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33535 11:36:58.474005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33536 11:36:58.506375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33538 11:36:58.506928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33539 11:36:58.539287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33541 11:36:58.539852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33542 11:36:58.573217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33544 11:36:58.573795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33545 11:36:58.604882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33547 11:36:58.605311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33548 11:36:58.636647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33549 11:36:58.637093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33551 11:36:58.669825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33552 11:36:58.670272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33554 11:36:58.701668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33556 11:36:58.702311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33557 11:36:58.732811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33558 11:36:58.733263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33560 11:36:58.765224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33562 11:36:58.765869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33563 11:36:58.796613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33565 11:36:58.797102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33566 11:36:58.828216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33568 11:36:58.828610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33569 11:36:58.859317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33571 11:36:58.859839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33572 11:36:58.890257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33574 11:36:58.890632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33575 11:36:58.920982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33577 11:36:58.921570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33578 11:36:58.951727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33580 11:36:58.952273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33581 11:36:58.983690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33583 11:36:58.984179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33584 11:36:59.014314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33586 11:36:59.014728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33587 11:36:59.045501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33589 11:36:59.046095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33590 11:36:59.076014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33592 11:36:59.076516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33593 11:36:59.106738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33594 11:36:59.107187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33596 11:36:59.141852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33597 11:36:59.142235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33599 11:36:59.173421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33600 11:36:59.173908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33602 11:36:59.205426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33604 11:36:59.206076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33605 11:36:59.237417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33607 11:36:59.238030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33608 11:36:59.268465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33609 11:36:59.268912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33611 11:36:59.299612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33612 11:36:59.300023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33614 11:36:59.330817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33615 11:36:59.331273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33617 11:36:59.361855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33619 11:36:59.362422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33620 11:36:59.394519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33622 11:36:59.395069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33623 11:36:59.425929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33624 11:36:59.426418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33626 11:36:59.456844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33627 11:36:59.457289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33629 11:36:59.489156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33630 11:36:59.489581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33632 11:36:59.522615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33634 11:36:59.522999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33635 11:36:59.555887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33636 11:36:59.556307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33638 11:36:59.588577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33640 11:36:59.588980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33641 11:36:59.624988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33642 11:36:59.625371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33644 11:36:59.658199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33645 11:36:59.658611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33647 11:36:59.691067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33648 11:36:59.691481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33650 11:36:59.723375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33651 11:36:59.723792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33653 11:36:59.756801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33654 11:36:59.757214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33656 11:36:59.792868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33657 11:36:59.793278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33659 11:36:59.825069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33660 11:36:59.825531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33662 11:36:59.865876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33663 11:36:59.866351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33665 11:36:59.898670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33667 11:36:59.899305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33668 11:36:59.932774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33670 11:36:59.933407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33671 11:36:59.964437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33672 11:36:59.964866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33674 11:36:59.996237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33675 11:36:59.996698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33677 11:37:00.027619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33678 11:37:00.028090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33680 11:37:00.059097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33681 11:37:00.059566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33683 11:37:00.091970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33685 11:37:00.092429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33686 11:37:00.123572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33688 11:37:00.124021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33689 11:37:00.155128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33690 11:37:00.155586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33692 11:37:00.187384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33693 11:37:00.187852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33695 11:37:00.221935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33696 11:37:00.222408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33698 11:37:00.253815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33699 11:37:00.254299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33701 11:37:00.284774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33702 11:37:00.285187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33704 11:37:00.315698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33706 11:37:00.316121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33707 11:37:00.347334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33709 11:37:00.347897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33710 11:37:00.379045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33712 11:37:00.379689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33713 11:37:00.410756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33715 11:37:00.411201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33716 11:37:00.442234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33717 11:37:00.442649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33719 11:37:00.475356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33721 11:37:00.475829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33722 11:37:00.507770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33723 11:37:00.508153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33725 11:37:00.539208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33726 11:37:00.539588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33728 11:37:00.570293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33729 11:37:00.570663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33731 11:37:00.619617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33732 11:37:00.620103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33734 11:37:00.654105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33736 11:37:00.654653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33737 11:37:00.685017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33738 11:37:00.685476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33740 11:37:00.715473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33742 11:37:00.716096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33743 11:37:00.746836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33744 11:37:00.747317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33746 11:37:00.778884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33747 11:37:00.779379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33749 11:37:00.810278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33751 11:37:00.810847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33752 11:37:00.841235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33754 11:37:00.841747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33755 11:37:00.872022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33756 11:37:00.872464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
33758 11:37:00.903801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33760 11:37:00.904428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33761 11:37:00.934579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33763 11:37:00.935177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33764 11:37:00.969208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33765 11:37:00.969702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
33767 11:37:01.000616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33768 11:37:01.001094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33770 11:37:01.032296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33772 11:37:01.032930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33773 11:37:01.063689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
33775 11:37:01.064233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33776 11:37:01.094748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33778 11:37:01.095280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33779 11:37:01.126277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33781 11:37:01.126830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33782 11:37:01.157358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33783 11:37:01.157796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
33785 11:37:01.187968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33786 11:37:01.188383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33788 11:37:01.218880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
33789 11:37:01.219334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
33791 11:37:01.249443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33792 11:37:01.249895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33794 11:37:01.280651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
33796 11:37:01.281175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33797 11:37:01.312957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33799 11:37:01.313535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33800 11:37:01.344786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33801 11:37:01.345236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33803 11:37:01.375814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
33805 11:37:01.376331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33806 11:37:01.407230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33807 11:37:01.407680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33809 11:37:01.438134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33811 11:37:01.438678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33812 11:37:01.471139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
33814 11:37:01.471699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33815 11:37:01.501805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33816 11:37:01.502185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33818 11:37:01.534738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33820 11:37:01.535287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33821 11:37:01.566572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
33823 11:37:01.567112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33824 11:37:01.597919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33826 11:37:01.598461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33827 11:37:01.629657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33829 11:37:01.630119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33830 11:37:01.661244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33831 11:37:01.661692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
33833 11:37:01.692522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33834 11:37:01.692960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33836 11:37:01.723814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
33837 11:37:01.724263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
33839 11:37:01.756103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33841 11:37:01.756781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33842 11:37:01.790005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33843 11:37:01.790461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
33845 11:37:01.823730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33847 11:37:01.824352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33848 11:37:01.856406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33849 11:37:01.856850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33851 11:37:01.888113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33852 11:37:01.888545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
33854 11:37:01.923707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33856 11:37:01.924174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33857 11:37:01.955793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33858 11:37:01.956262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33860 11:37:01.987362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33861 11:37:01.987802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
33863 11:37:02.019357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33864 11:37:02.019976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33866 11:37:02.052285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33867 11:37:02.052836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33869 11:37:02.084167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33870 11:37:02.084638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
33872 11:37:02.116137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33873 11:37:02.116548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33875 11:37:02.148778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33876 11:37:02.149220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33878 11:37:02.180674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
33880 11:37:02.181123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33881 11:37:02.212583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33883 11:37:02.213030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33884 11:37:02.244352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
33886 11:37:02.244988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
33887 11:37:02.275781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33888 11:37:02.276238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33890 11:37:02.308230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
33892 11:37:02.308670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33893 11:37:02.339823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33894 11:37:02.340281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33896 11:37:02.372238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33897 11:37:02.372702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33899 11:37:02.405615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
33901 11:37:02.406192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33902 11:37:02.437196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33903 11:37:02.437632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33905 11:37:02.469079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33907 11:37:02.469526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33908 11:37:02.505924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33909 11:37:02.506427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
33911 11:37:02.543169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33912 11:37:02.543570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33914 11:37:02.580568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33915 11:37:02.581042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33917 11:37:02.616554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33918 11:37:02.617012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
33920 11:37:02.656422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33921 11:37:02.656890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33923 11:37:02.691739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33924 11:37:02.692226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33926 11:37:02.724562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33927 11:37:02.724997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
33929 11:37:02.757684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33931 11:37:02.758222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33932 11:37:02.789852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
33934 11:37:02.790305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
33935 11:37:02.823045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33936 11:37:02.823516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33938 11:37:02.856445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33939 11:37:02.856873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
33941 11:37:02.889172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33943 11:37:02.889715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33944 11:37:02.922057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33945 11:37:02.922475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33947 11:37:02.955421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
33949 11:37:02.955969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33950 11:37:02.989642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33952 11:37:02.990226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33953 11:37:03.023542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33954 11:37:03.023987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33956 11:37:03.058579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
33958 11:37:03.059172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33959 11:37:03.092985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33961 11:37:03.093529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33962 11:37:03.126395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33964 11:37:03.126952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33965 11:37:03.160348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33966 11:37:03.160785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
33968 11:37:03.194950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33969 11:37:03.195448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33971 11:37:03.229778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33972 11:37:03.230275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33974 11:37:03.264176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
33976 11:37:03.264727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33977 11:37:03.297987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33978 11:37:03.298486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33980 11:37:03.331370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
33981 11:37:03.331924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
33983 11:37:03.364417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33984 11:37:03.364836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33986 11:37:03.396825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33987 11:37:03.397200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
33989 11:37:03.429342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33990 11:37:03.429787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33992 11:37:03.461540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33993 11:37:03.461934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33995 11:37:03.495194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
33997 11:37:03.495582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33998 11:37:03.528475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34000 11:37:03.529042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34001 11:37:03.562092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34002 11:37:03.562540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34004 11:37:03.593902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34005 11:37:03.594389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34007 11:37:03.625772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34009 11:37:03.626378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34010 11:37:03.660567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34011 11:37:03.661014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34013 11:37:03.697679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34014 11:37:03.698129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34016 11:37:03.735907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34017 11:37:03.736355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34019 11:37:03.770724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34021 11:37:03.771526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34022 11:37:03.803531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34023 11:37:03.804061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34025 11:37:03.836625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34026 11:37:03.837058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34028 11:37:03.873318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34030 11:37:03.873693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34031 11:37:03.905288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34032 11:37:03.905692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34034 11:37:03.936563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34036 11:37:03.937109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34037 11:37:03.968032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34039 11:37:03.968605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34040 11:37:03.999708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34041 11:37:04.000130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34043 11:37:04.031181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34044 11:37:04.031624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34046 11:37:04.064825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34048 11:37:04.065454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34049 11:37:04.096181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34051 11:37:04.096951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34052 11:37:04.127266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34054 11:37:04.127715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34055 11:37:04.158101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34057 11:37:04.158574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34058 11:37:04.189495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34059 11:37:04.189921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34061 11:37:04.221034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34062 11:37:04.221441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34064 11:37:04.252255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34065 11:37:04.252646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34067 11:37:04.284584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34069 11:37:04.285028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34070 11:37:04.317193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34071 11:37:04.317637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34073 11:37:04.350650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34075 11:37:04.351215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34076 11:37:04.384697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34077 11:37:04.385137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34079 11:37:04.418927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34080 11:37:04.419364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34082 11:37:04.452877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34084 11:37:04.453570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34085 11:37:04.489320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34086 11:37:04.489777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34088 11:37:04.524223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34089 11:37:04.524657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34091 11:37:04.558678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34093 11:37:04.559201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34094 11:37:04.590690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34096 11:37:04.591216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34097 11:37:04.621564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34099 11:37:04.621966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34100 11:37:04.652288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34102 11:37:04.652812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34103 11:37:04.683585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34105 11:37:04.684179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34106 11:37:04.715358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34108 11:37:04.715910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34109 11:37:04.746497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34111 11:37:04.747085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34112 11:37:04.778023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34114 11:37:04.778603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34115 11:37:04.809906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34116 11:37:04.810308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34118 11:37:04.841248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34119 11:37:04.841668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34121 11:37:04.872775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34122 11:37:04.873203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34124 11:37:04.904401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34126 11:37:04.904966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34127 11:37:04.936466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34128 11:37:04.936920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34130 11:37:04.968096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34131 11:37:04.968503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34133 11:37:04.999828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34134 11:37:05.000243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34136 11:37:05.031847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34137 11:37:05.032297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34139 11:37:05.063260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34140 11:37:05.063678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34142 11:37:05.095575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34143 11:37:05.095985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34145 11:37:05.127403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34146 11:37:05.127762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34148 11:37:05.158915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34149 11:37:05.159263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34151 11:37:05.190053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34152 11:37:05.190526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34154 11:37:05.221636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34155 11:37:05.222095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34157 11:37:05.252730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34158 11:37:05.253128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34160 11:37:05.284066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34161 11:37:05.284528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34163 11:37:05.316315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34164 11:37:05.316765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34166 11:37:05.347763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34168 11:37:05.348326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34169 11:37:05.379449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34170 11:37:05.379866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34172 11:37:05.410987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34173 11:37:05.411401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34175 11:37:05.442112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34176 11:37:05.442532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34178 11:37:05.474393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34180 11:37:05.475016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34181 11:37:05.507996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34182 11:37:05.508468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34184 11:37:05.540723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34185 11:37:05.541186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34187 11:37:05.572136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34188 11:37:05.572609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34190 11:37:05.603575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34192 11:37:05.604227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34193 11:37:05.635191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34194 11:37:05.635647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34196 11:37:05.666786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34198 11:37:05.667349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34199 11:37:05.699092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34201 11:37:05.699727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34202 11:37:05.753184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34203 11:37:05.753603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34205 11:37:05.787205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34206 11:37:05.787602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34208 11:37:05.819820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34209 11:37:05.820289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34211 11:37:05.852893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34212 11:37:05.853293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34214 11:37:05.886165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34216 11:37:05.886631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34217 11:37:05.918935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34218 11:37:05.919383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34220 11:37:05.951230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34221 11:37:05.951697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34223 11:37:05.983209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34224 11:37:05.983655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34226 11:37:06.016882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34228 11:37:06.017460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34229 11:37:06.051632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34230 11:37:06.052022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34232 11:37:06.083756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34233 11:37:06.084215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34235 11:37:06.116582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34236 11:37:06.116996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34238 11:37:06.150332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34239 11:37:06.150804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34241 11:37:06.182151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34242 11:37:06.182509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34244 11:37:06.213551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34245 11:37:06.213918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34247 11:37:06.244383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34248 11:37:06.244797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34250 11:37:06.275958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34251 11:37:06.276356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34253 11:37:06.307423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34254 11:37:06.307795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34256 11:37:06.338119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34257 11:37:06.338556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34259 11:37:06.368748 <47>[ 406.800070] systemd-journald[105]: Sent WATCHDOG=1 notification.
34260 11:37:06.375857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34261 11:37:06.376303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34263 11:37:06.407391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34265 11:37:06.407856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34266 11:37:06.438576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34268 11:37:06.439037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34269 11:37:06.470111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34270 11:37:06.470468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34272 11:37:06.501147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34273 11:37:06.501496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34275 11:37:06.534085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34276 11:37:06.534477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34278 11:37:06.566096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34279 11:37:06.566544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34281 11:37:06.597231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34282 11:37:06.597692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34284 11:37:06.628572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34285 11:37:06.629000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34287 11:37:06.659759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34288 11:37:06.660162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34290 11:37:06.691161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34291 11:37:06.691510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34293 11:37:06.722811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34294 11:37:06.723176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34296 11:37:06.754712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34298 11:37:06.755303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34299 11:37:06.786185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34300 11:37:06.786555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34302 11:37:06.818559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34304 11:37:06.818925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34305 11:37:06.849527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34306 11:37:06.849969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34308 11:37:06.882051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34309 11:37:06.882519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34311 11:37:06.913444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34312 11:37:06.913958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34314 11:37:06.944472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34315 11:37:06.944909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34317 11:37:06.975669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34319 11:37:06.976103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34320 11:37:07.007171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34322 11:37:07.007719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34323 11:37:07.038188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34324 11:37:07.038676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34326 11:37:07.069464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34328 11:37:07.069806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34329 11:37:07.100102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34330 11:37:07.100469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34332 11:37:07.131123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34333 11:37:07.131533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34335 11:37:07.163225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34337 11:37:07.163659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34338 11:37:07.194042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34339 11:37:07.194443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34341 11:37:07.225239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34342 11:37:07.225630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34344 11:37:07.256538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34346 11:37:07.256972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34347 11:37:07.291218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34348 11:37:07.291630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34350 11:37:07.324739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34352 11:37:07.325189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34353 11:37:07.358355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34355 11:37:07.358893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34356 11:37:07.392725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34357 11:37:07.393105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34359 11:37:07.434621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34361 11:37:07.435072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34362 11:37:07.465890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34363 11:37:07.466267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34365 11:37:07.498576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34367 11:37:07.499049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34368 11:37:07.529336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34369 11:37:07.529688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34371 11:37:07.561053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34372 11:37:07.561429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34374 11:37:07.592310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34375 11:37:07.592590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34377 11:37:07.623484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34378 11:37:07.623835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34380 11:37:07.653925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34381 11:37:07.654204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34383 11:37:07.684374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34384 11:37:07.684726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34386 11:37:07.715373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34387 11:37:07.715720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34389 11:37:07.745964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34391 11:37:07.746403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34392 11:37:07.776701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34393 11:37:07.777069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34395 11:37:07.807492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34396 11:37:07.807855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34398 11:37:07.838602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34400 11:37:07.839070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34401 11:37:07.869083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34402 11:37:07.869449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34404 11:37:07.900501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34405 11:37:07.900865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34407 11:37:07.931651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34408 11:37:07.932021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34410 11:37:07.962518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34412 11:37:07.962946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34413 11:37:07.992888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34415 11:37:07.993304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34416 11:37:08.024162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34418 11:37:08.024584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34419 11:37:08.055043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34420 11:37:08.055406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34422 11:37:08.085710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34423 11:37:08.086054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34425 11:37:08.116424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34426 11:37:08.116773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34428 11:37:08.147122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34429 11:37:08.147464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34431 11:37:08.178203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34433 11:37:08.178624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34434 11:37:08.181045 + set +x
34435 11:37:08.181232 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 562716_1.1.3.5>
34436 11:37:08.181554 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 562716_1.1.3.5
34437 11:37:08.181703 Ending use of test pattern.
34438 11:37:08.181827 Ending test lava.1_kselftest-arm64_qemu (562716_1.1.3.5), duration 386.70
34440 11:37:08.184170 <LAVA_TEST_RUNNER EXIT>
34441 11:37:08.184577 ok: lava_test_shell seems to have completed
34442 11:37:08.273126 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34443 11:37:08.402437 end: 3.1 lava-test-shell (duration 00:06:28) [common]
34444 11:37:08.402749 end: 3 lava-test-retry (duration 00:06:28) [common]
34445 11:37:08.402969 start: 4 finalize (timeout 00:02:13) [common]
34446 11:37:08.403184 start: 4.1 power-off (timeout 00:00:30) [common]
34447 11:37:08.403390 end: 4.1 power-off (duration 00:00:00) [common]
34448 11:37:08.403589 start: 4.2 read-feedback (timeout 00:02:13) [common]
34449 11:37:08.403942 Listened to connection for namespace 'common' for up to 1s
34450 11:37:08.404372 Listened to connection for namespace 'common' for up to 1s
34451 11:37:09.408928 Finalising connection for namespace 'common'
34453 11:37:09.509989 / # poweroff
34454 11:37:09.510673 Already disconnected
34455 11:37:09.510947 poweroff
34456 11:37:09.913511 end: 4.2 read-feedback (duration 00:00:02) [common]
34457 11:37:09.913772 Already disconnected
34458 11:37:09.913903 end: 4 finalize (duration 00:00:02) [common]
34459 11:37:09.914038 Cleaning after the job
34460 11:37:09.914185 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/562716/deployimages-kzri8r96/kernel
34461 11:37:09.920043 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/562716/deployimages-kzri8r96/ramdisk
34462 11:37:09.933657 Stopping the qemu container lava-docker-qemu-562716-2.1.1-pxgdojamxi
34463 11:37:10.743379 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/562716
34464 11:37:10.837010 Job finished correctly